Fix sparc when assembler lacks support for vis3/fmaf instructions.

gcc/

	* config/sparc/sparc.h: Do not force TARGET_VIS3 and TARGET_FMAF
	to zero when assembler lacks support for such instructions.
	* config/sparc/sparc.c (sparc_option_override): Clear MASK_VIS3
	and MASK_FMAF in defaults when assembler lacks necessary support.

gcc/testsuite/

	* gcc.target/sparc/cmask.c: Remove 'vis3' target check and specify
	'-mvis3' instead of 'mcpu=niagara3' in options.
	* gcc.target/sparc/fhalve.c: Likewise.
	* gcc.target/sparc/fnegop.c: Likewise.
	* gcc.target/sparc/fpadds.c: Likewise.
	* gcc.target/sparc/fshift.c: Likewise.
	* gcc.target/sparc/fucmp.c: Likewise.
	* gcc.target/sparc/lzd.c: Likewise.
	* gcc.target/sparc/vis3misc.c: Likewise.
	* gcc.target/sparc/xmul.c: Likewise.

From-SVN: r179875

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cdc939122d005dbb81efbb233bdd655ab981b9d8..017594f98dfa7b664da2250abce004cd176197fe 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2011-10-12  David S. Miller  <davem@davemloft.net>
+
+       * config/sparc/sparc.h: Do not force TARGET_VIS3 and TARGET_FMAF
+       to zero when assembler lacks support for such instructions.
+       * config/sparc/sparc.c (sparc_option_override): Clear MASK_VIS3
+       and MASK_FMAF in defaults when assembler lacks necessary support.
+
 2011-10-12  Jakub Jelinek  <jakub@redhat.com>
 
        * config/i386/sse.md (vec_unpacks_lo_<mode>,

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 9c7cc56b43e0a224f4d5e91a2f9d525dfb2714d7..fa790b359d2aa10736592cd8f33d1799c8774d20 100644 (file)
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -850,7 +850,11 @@ sparc_option_override (void)
 
   cpu = &cpu_table[(int) sparc_cpu_and_features];
   target_flags &= ~cpu->disable;
-  target_flags |= cpu->enable;
+  target_flags |= (cpu->enable
+#ifndef HAVE_AS_FMAF_HPC_VIS3
+                  & ~(MASK_FMAF | MASK_VIS3)
+#endif
+                  );
 
   /* If -mfpu or -mno-fpu was explicitly used, don't override with
      the processor default.  */

diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 0642ff2f9e8a2a29a6e9cb6ef7bbeddcd857a118..669f106fe32620dd7c45560f1d59a084529c07e0 100644 (file)
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1871,10 +1871,6 @@ extern int sparc_indent_opcode;
 
 #ifndef HAVE_AS_FMAF_HPC_VIS3
 #define AS_NIAGARA3_FLAG "b"
-#undef TARGET_FMAF
-#define TARGET_FMAF 0
-#undef TARGET_VIS3
-#define TARGET_VIS3 0
 #else
 #define AS_NIAGARA3_FLAG "d"
 #endif

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9e8f1f9b952a4900a960bd834ca537f838cc1d2f..943f36f4ab08cb1f061a7d8b6d4f27e3f1d53172 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,16 @@
+2011-10-12  David S. Miller  <davem@davemloft.net>
+
+       * gcc.target/sparc/cmask.c: Remove 'vis3' target check and specify
+       '-mvis3' instead of 'mcpu=niagara3' in options.
+       * gcc.target/sparc/fhalve.c: Likewise.
+       * gcc.target/sparc/fnegop.c: Likewise.
+       * gcc.target/sparc/fpadds.c: Likewise.
+       * gcc.target/sparc/fshift.c: Likewise.
+       * gcc.target/sparc/fucmp.c: Likewise.
+       * gcc.target/sparc/lzd.c: Likewise.
+       * gcc.target/sparc/vis3misc.c: Likewise.
+       * gcc.target/sparc/xmul.c: Likewise.
+
 2011-10-12  Eric Botcazou  <ebotcazou@adacore.com>
 
        * gnat.dg/vect1.ad[sb]: New test.

diff --git a/gcc/testsuite/gcc.target/sparc/cmask.c b/gcc/testsuite/gcc.target/sparc/cmask.c
index 989274c68584c66afd0d59d1c4c9409bd1314aab..d1be910f5e0b1cf28aa81d1c06a809bdad8877c3 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/cmask.c
+++ b/gcc/testsuite/gcc.target/sparc/cmask.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 
 void test_cm8 (long x)
 {

diff --git a/gcc/testsuite/gcc.target/sparc/fhalve.c b/gcc/testsuite/gcc.target/sparc/fhalve.c
index 737fc71bbcf64cbf7f8819bd92fddc236c477b59..b8f0745afc989b0d5e8b26ed032e0f76c484fc8a 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/fhalve.c
+++ b/gcc/testsuite/gcc.target/sparc/fhalve.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 
 float test_fhadds (float x, float y)
 {

diff --git a/gcc/testsuite/gcc.target/sparc/fnegop.c b/gcc/testsuite/gcc.target/sparc/fnegop.c
index 3e3e72c820cab695478345ebded37056f107351f..cbdf28f4c6017adc5d3708c98b7e5c06b9ac8a40 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/fnegop.c
+++ b/gcc/testsuite/gcc.target/sparc/fnegop.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-O2 -mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mvis3" } */
 
 float test_fnadds(float x, float y)
 {

diff --git a/gcc/testsuite/gcc.target/sparc/fpadds.c b/gcc/testsuite/gcc.target/sparc/fpadds.c
index f55cb057a2ad2f21881c53f1358613f5ee632594..9b1027d5fcab807ea59205e71047600d4158e03c 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/fpadds.c
+++ b/gcc/testsuite/gcc.target/sparc/fpadds.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef int __v2si __attribute__((vector_size(8)));
 typedef int __v1si __attribute__((vector_size(4)));
 typedef short __v4hi __attribute__((vector_size(8)));

diff --git a/gcc/testsuite/gcc.target/sparc/fshift.c b/gcc/testsuite/gcc.target/sparc/fshift.c
index 6adbed6917190fa79876855ea58d33176854b8ba..1f032151c16ba85cc4758f017037e30e4d14cd6b 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/fshift.c
+++ b/gcc/testsuite/gcc.target/sparc/fshift.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef int __v2si __attribute__((vector_size(8)));
 typedef short __v4hi __attribute__((vector_size(8)));
 

diff --git a/gcc/testsuite/gcc.target/sparc/fucmp.c b/gcc/testsuite/gcc.target/sparc/fucmp.c
index 4e7ecadcd4aeaca1613911ba971d2c6bc57af07b..6e8f1b3418efd8f9bba2c475aaa7c141460d17dd 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/fucmp.c
+++ b/gcc/testsuite/gcc.target/sparc/fucmp.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef unsigned char vec8 __attribute__((vector_size(8)));
 
 long test_fucmple8 (vec8 a, vec8 b)

diff --git a/gcc/testsuite/gcc.target/sparc/lzd.c b/gcc/testsuite/gcc.target/sparc/lzd.c
index 5ffaf56e5584cac7da0d17e2e68d97a058573a5c..bc2b8522be8af72ef7fe6f5dcc2388ceac294b45 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/lzd.c
+++ b/gcc/testsuite/gcc.target/sparc/lzd.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 int test_clz(int a)
 {
   return __builtin_clz(a);

diff --git a/gcc/testsuite/gcc.target/sparc/vis3misc.c b/gcc/testsuite/gcc.target/sparc/vis3misc.c
index e3ef49e210d3d26d1fc76d182d24c5b0456bc06a..7286d705dd5612f9b09502c59fde13e6e1ba84d7 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/vis3misc.c
+++ b/gcc/testsuite/gcc.target/sparc/vis3misc.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef int __v2si __attribute__((vector_size(8)));
 typedef short __v4hi __attribute__((vector_size(8)));
 typedef unsigned char __v8qi __attribute__((vector_size(8)));

diff --git a/gcc/testsuite/gcc.target/sparc/xmul.c b/gcc/testsuite/gcc.target/sparc/xmul.c
index 5d249d092dbc5b19de4733e44ec4bc258c06eabf..a432ee1fec1d2e0e8abd9eb07ed782606d4302a8 100644 (file)
--- a/gcc/testsuite/gcc.target/sparc/xmul.c
+++ b/gcc/testsuite/gcc.target/sparc/xmul.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef long long int64_t;
 
 int64_t test_umulxhi (int64_t x, int64_t y)