]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
ARM: dts: rockchip: add tsadc node for RV1108 SoC
authorRocky Hao <rocky.hao@rock-chips.com>
Thu, 24 Aug 2017 10:27:53 +0000 (18:27 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 17 Oct 2017 18:53:29 +0000 (20:53 +0200)
Add tsadc needed main information for RV1108 SoC.
750000Hz is the max clock rate supported by tsadc module.

Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm/boot/dts/rv1108.dtsi

index e7cd1315db1b7bc08c688867dd77c4687396fe92..658a458a5b387653c745da3d26038fb183d48683 100644 (file)
                status = "disabled";
        };
 
+       tsadc: tsadc@10370000 {
+               compatible = "rockchip,rv1108-tsadc";
+               reg = <0x10370000 0x100>;
+               interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+               assigned-clocks = <&cru SCLK_TSADC>;
+               assigned-clock-rates = <750000>;
+               clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+               clock-names = "tsadc", "apb_pclk";
+               pinctrl-names = "init", "default", "sleep";
+               pinctrl-0 = <&otp_gpio>;
+               pinctrl-1 = <&otp_out>;
+               pinctrl-2 = <&otp_gpio>;
+               resets = <&cru SRST_TSADC>;
+               reset-names = "tsadc-apb";
+               rockchip,hw-tshut-temp = <120000>;
+               #thermal-sensor-cells = <1>;
+               status = "disabled";
+       };
+
        adc: adc@1038c000 {
                compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
                reg = <0x1038c000 0x100>;
                        };
                };
 
+               tsadc {
+                       otp_out: otp-out {
+                               rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       otp_gpio: otp-gpio {
+                               rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+                       };
+               };
+
                uart0 {
                        uart0_xfer: uart0-xfer {
                                rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,