--- /dev/null
+From 91cb2c8b072e00632adf463b78b44f123d46a0fa Mon Sep 17 00:00:00 2001
+From: Catalin Marinas <catalin.marinas@arm.com>
+Date: Mon, 1 Feb 2021 19:06:33 +0000
+Subject: arm64: Do not pass tagged addresses to __is_lm_address()
+
+From: Catalin Marinas <catalin.marinas@arm.com>
+
+commit 91cb2c8b072e00632adf463b78b44f123d46a0fa upstream.
+
+Commit 519ea6f1c82f ("arm64: Fix kernel address detection of
+__is_lm_address()") fixed the incorrect validation of addresses below
+PAGE_OFFSET. However, it no longer allowed tagged addresses to be passed
+to virt_addr_valid().
+
+Fix this by explicitly resetting the pointer tag prior to invoking
+__is_lm_address(). This is consistent with the __lm_to_phys() macro.
+
+Fixes: 519ea6f1c82f ("arm64: Fix kernel address detection of __is_lm_address()")
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Acked-by: Ard Biesheuvel <ardb@kernel.org>
+Cc: <stable@vger.kernel.org> # 5.4.x
+Cc: Will Deacon <will@kernel.org>
+Cc: Vincenzo Frascino <vincenzo.frascino@arm.com>
+Cc: Mark Rutland <mark.rutland@arm.com>
+Link: https://lore.kernel.org/r/20210201190634.22942-2-catalin.marinas@arm.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/include/asm/memory.h | 2 +-
+ arch/arm64/mm/physaddr.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/include/asm/memory.h
++++ b/arch/arm64/include/asm/memory.h
+@@ -323,7 +323,7 @@ static inline void *phys_to_virt(phys_ad
+ #endif /* !CONFIG_SPARSEMEM_VMEMMAP || CONFIG_DEBUG_VIRTUAL */
+
+ #define virt_addr_valid(addr) ({ \
+- __typeof__(addr) __addr = addr; \
++ __typeof__(addr) __addr = __tag_reset(addr); \
+ __is_lm_address(__addr) && pfn_valid(virt_to_pfn(__addr)); \
+ })
+
+--- a/arch/arm64/mm/physaddr.c
++++ b/arch/arm64/mm/physaddr.c
+@@ -9,7 +9,7 @@
+
+ phys_addr_t __virt_to_phys(unsigned long x)
+ {
+- WARN(!__is_lm_address(x),
++ WARN(!__is_lm_address(__tag_reset(x)),
+ "virt_to_phys used for non-linear address: %pK (%pS)\n",
+ (void *)x,
+ (void *)x);
--- /dev/null
+From 03544505cb10ddc73df3b6176e71cdb366834134 Mon Sep 17 00:00:00 2001
+From: Robin Murphy <robin.murphy@arm.com>
+Date: Tue, 22 Sep 2020 15:16:50 +0100
+Subject: arm64: dts: meson: Describe G12b GPU as coherent
+
+From: Robin Murphy <robin.murphy@arm.com>
+
+commit 03544505cb10ddc73df3b6176e71cdb366834134 upstream.
+
+According to a downstream commit I found in the Khadas vendor kernel,
+the GPU on G12b is wired up for ACE-lite, so (now that Panfrost knows
+how to handle this properly) we should describe it as such. Otherwise
+the mismatch leads to all manner of fun with mismatched attributes and
+inadvertently snooping stale data from caches, which would account for
+at least some of the brokenness observed on this platform.
+
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Tested-by: Neil Armstrong <narmstrong@baylibre.com>
+Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/765446e529e50b304af63432da7836c4d31eb8d4.1600780574.git.robin.murphy@arm.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+@@ -135,3 +135,7 @@
+ };
+ };
+ };
++
++&mali {
++ dma-coherent;
++};
--- /dev/null
+From 519ea6f1c82fcdc9842908155ae379de47818778 Mon Sep 17 00:00:00 2001
+From: Vincenzo Frascino <vincenzo.frascino@arm.com>
+Date: Tue, 26 Jan 2021 13:40:56 +0000
+Subject: arm64: Fix kernel address detection of __is_lm_address()
+
+From: Vincenzo Frascino <vincenzo.frascino@arm.com>
+
+commit 519ea6f1c82fcdc9842908155ae379de47818778 upstream.
+
+Currently, the __is_lm_address() check just masks out the top 12 bits
+of the address, but if they are 0, it still yields a true result.
+This has as a side effect that virt_addr_valid() returns true even for
+invalid virtual addresses (e.g. 0x0).
+
+Fix the detection checking that it's actually a kernel address starting
+at PAGE_OFFSET.
+
+Fixes: 68dd8ef32162 ("arm64: memory: Fix virt_addr_valid() using __is_lm_address()")
+Cc: <stable@vger.kernel.org> # 5.4.x
+Cc: Will Deacon <will@kernel.org>
+Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
+Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
+Acked-by: Mark Rutland <mark.rutland@arm.com>
+Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
+Link: https://lore.kernel.org/r/20210126134056.45747-1-vincenzo.frascino@arm.com
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/include/asm/memory.h | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/include/asm/memory.h
++++ b/arch/arm64/include/asm/memory.h
+@@ -238,11 +238,11 @@ static inline const void *__tag_set(cons
+
+
+ /*
+- * The linear kernel range starts at the bottom of the virtual address
+- * space. Testing the top bit for the start of the region is a
+- * sufficient check and avoids having to worry about the tag.
++ * Check whether an arbitrary address is within the linear map, which
++ * lives in the [PAGE_OFFSET, PAGE_END) interval at the bottom of the
++ * kernel's TTBR1 address range.
+ */
+-#define __is_lm_address(addr) (!(((u64)addr) & BIT(vabits_actual - 1)))
++#define __is_lm_address(addr) (((u64)(addr) ^ PAGE_OFFSET) < (PAGE_END - PAGE_OFFSET))
+
+ #define __lm_to_phys(addr) (((addr) & ~PAGE_OFFSET) + PHYS_OFFSET)
+ #define __kimg_to_phys(addr) ((addr) - kimage_voffset)
--- /dev/null
+From 268af50f38b1f2199a2e85e38073d7a25c20190c Mon Sep 17 00:00:00 2001
+From: Robin Murphy <robin.murphy@arm.com>
+Date: Tue, 22 Sep 2020 15:16:49 +0100
+Subject: drm/panfrost: Support cache-coherent integrations
+
+From: Robin Murphy <robin.murphy@arm.com>
+
+commit 268af50f38b1f2199a2e85e38073d7a25c20190c upstream.
+
+When the GPU's ACE-Lite interface is fully wired up and capable of
+snooping CPU caches, it may be described as "dma-coherent" in
+devicetree, which will already inform the DMA layer not to perform
+unnecessary cache maintenance. However, we still need to ensure that
+the GPU uses the appropriate cacheable outer-shareable attributes in
+order to generate the requisite snoop signals, and that CPU mappings
+don't create a mismatch by using a non-cacheable type either.
+
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Tested-by: Neil Armstrong <narmstrong@baylibre.com>
+Reviewed-by: Steven Price <steven.price@arm.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/7024ce18c1cb1a226e918037d49175571db0b436.1600780574.git.robin.murphy@arm.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
+ drivers/gpu/drm/panfrost/panfrost_drv.c | 2 ++
+ drivers/gpu/drm/panfrost/panfrost_gem.c | 2 ++
+ drivers/gpu/drm/panfrost/panfrost_mmu.c | 1 +
+ 4 files changed, 6 insertions(+)
+
+--- a/drivers/gpu/drm/panfrost/panfrost_device.h
++++ b/drivers/gpu/drm/panfrost/panfrost_device.h
+@@ -88,6 +88,7 @@ struct panfrost_device {
+ /* pm_domains for devices with more than one. */
+ struct device *pm_domain_devs[MAX_PM_DOMAINS];
+ struct device_link *pm_domain_links[MAX_PM_DOMAINS];
++ bool coherent;
+
+ struct panfrost_features features;
+ const struct panfrost_compatible *comp;
+--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
++++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
+@@ -587,6 +587,8 @@ static int panfrost_probe(struct platfor
+ if (!pfdev->comp)
+ return -ENODEV;
+
++ pfdev->coherent = device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT;
++
+ /* Allocate and initialze the DRM device. */
+ ddev = drm_dev_alloc(&panfrost_drm_driver, &pdev->dev);
+ if (IS_ERR(ddev))
+--- a/drivers/gpu/drm/panfrost/panfrost_gem.c
++++ b/drivers/gpu/drm/panfrost/panfrost_gem.c
+@@ -218,6 +218,7 @@ static const struct drm_gem_object_funcs
+ */
+ struct drm_gem_object *panfrost_gem_create_object(struct drm_device *dev, size_t size)
+ {
++ struct panfrost_device *pfdev = dev->dev_private;
+ struct panfrost_gem_object *obj;
+
+ obj = kzalloc(sizeof(*obj), GFP_KERNEL);
+@@ -227,6 +228,7 @@ struct drm_gem_object *panfrost_gem_crea
+ INIT_LIST_HEAD(&obj->mappings.list);
+ mutex_init(&obj->mappings.lock);
+ obj->base.base.funcs = &panfrost_gem_funcs;
++ obj->base.map_cached = pfdev->coherent;
+
+ return &obj->base.base;
+ }
+--- a/drivers/gpu/drm/panfrost/panfrost_mmu.c
++++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c
+@@ -371,6 +371,7 @@ int panfrost_mmu_pgtable_alloc(struct pa
+ .pgsize_bitmap = SZ_4K | SZ_2M,
+ .ias = FIELD_GET(0xff, pfdev->features.mmu_features),
+ .oas = FIELD_GET(0xff00, pfdev->features.mmu_features),
++ .coherent_walk = pfdev->coherent,
+ .tlb = &mmu_tlb_ops,
+ .iommu_dev = pfdev->dev,
+ };
--- /dev/null
+From e41aec79e62fa50f940cf222d1e9577f14e149dc Mon Sep 17 00:00:00 2001
+From: Lijun Pan <ljp@linux.ibm.com>
+Date: Wed, 27 Jan 2021 19:34:42 -0600
+Subject: ibmvnic: Ensure that CRQ entry read are correctly ordered
+
+From: Lijun Pan <ljp@linux.ibm.com>
+
+commit e41aec79e62fa50f940cf222d1e9577f14e149dc upstream.
+
+Ensure that received Command-Response Queue (CRQ) entries are
+properly read in order by the driver. dma_rmb barrier has
+been added before accessing the CRQ descriptor to ensure
+the entire descriptor is read before processing.
+
+Fixes: 032c5e82847a ("Driver for IBM System i/p VNIC protocol")
+Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
+Link: https://lore.kernel.org/r/20210128013442.88319-1-ljp@linux.ibm.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/ethernet/ibm/ibmvnic.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/net/ethernet/ibm/ibmvnic.c
++++ b/drivers/net/ethernet/ibm/ibmvnic.c
+@@ -4979,6 +4979,12 @@ static void ibmvnic_tasklet(struct taskl
+ while (!done) {
+ /* Pull all the valid messages off the CRQ */
+ while ((crq = ibmvnic_next_crq(adapter)) != NULL) {
++ /* This barrier makes sure ibmvnic_next_crq()'s
++ * crq->generic.first & IBMVNIC_CRQ_CMD_RSP is loaded
++ * before ibmvnic_handle_crq()'s
++ * switch(gen_crq->first) and switch(gen_crq->cmd).
++ */
++ dma_rmb();
+ ibmvnic_handle_crq(crq, adapter);
+ crq->generic.first = 0;
+ }
--- /dev/null
+From 728da60da7c1ec1e21ae64648e376666de3c279c Mon Sep 17 00:00:00 2001
+From: Robin Murphy <robin.murphy@arm.com>
+Date: Tue, 22 Sep 2020 15:16:48 +0100
+Subject: iommu/io-pgtable-arm: Support coherency for Mali LPAE
+
+From: Robin Murphy <robin.murphy@arm.com>
+
+commit 728da60da7c1ec1e21ae64648e376666de3c279c upstream.
+
+Midgard GPUs have ACE-Lite master interfaces which allows systems to
+integrate them in an I/O-coherent manner. It seems that from the GPU's
+viewpoint, the rest of the system is its outer shareable domain, and so
+even when snoop signals are wired up, they are only emitted for outer
+shareable accesses. As such, setting the TTBR_SHARE_OUTER bit does
+indeed get coherent pagetable walks working nicely for the coherent
+T620 in the Arm Juno SoC.
+
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Tested-by: Neil Armstrong <narmstrong@baylibre.com>
+Reviewed-by: Steven Price <steven.price@arm.com>
+Acked-by: Will Deacon <will@kernel.org>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/8df778355378127ea7eccc9521d6427e3e48d4f2.1600780574.git.robin.murphy@arm.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/iommu/io-pgtable-arm.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+--- a/drivers/iommu/io-pgtable-arm.c
++++ b/drivers/iommu/io-pgtable-arm.c
+@@ -417,7 +417,13 @@ static arm_lpae_iopte arm_lpae_prot_to_p
+ << ARM_LPAE_PTE_ATTRINDX_SHIFT);
+ }
+
+- if (prot & IOMMU_CACHE)
++ /*
++ * Also Mali has its own notions of shareability wherein its Inner
++ * domain covers the cores within the GPU, and its Outer domain is
++ * "outside the GPU" (i.e. either the Inner or System domain in CPU
++ * terms, depending on coherency).
++ */
++ if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE)
+ pte |= ARM_LPAE_PTE_SH_IS;
+ else
+ pte |= ARM_LPAE_PTE_SH_OS;
+@@ -1021,6 +1027,9 @@ arm_mali_lpae_alloc_pgtable(struct io_pg
+ cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
+ ARM_MALI_LPAE_TTBR_READ_INNER |
+ ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
++ if (cfg->coherent_walk)
++ cfg->arm_mali_lpae_cfg.transtab |= ARM_MALI_LPAE_TTBR_SHARE_OUTER;
++
+ return &data->iop;
+
+ out_free_data:
--- /dev/null
+From cf3c46631e1637582f517a574c77cd6c05793817 Mon Sep 17 00:00:00 2001
+From: Pan Bian <bianpan2016@163.com>
+Date: Thu, 21 Jan 2021 04:33:43 -0800
+Subject: net: dsa: bcm_sf2: put device node before return
+
+From: Pan Bian <bianpan2016@163.com>
+
+commit cf3c46631e1637582f517a574c77cd6c05793817 upstream.
+
+Put the device node dn before return error code on failure path.
+
+Fixes: 461cd1b03e32 ("net: dsa: bcm_sf2: Register our slave MDIO bus")
+Signed-off-by: Pan Bian <bianpan2016@163.com>
+Link: https://lore.kernel.org/r/20210121123343.26330-1-bianpan2016@163.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/dsa/bcm_sf2.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -509,15 +509,19 @@ static int bcm_sf2_mdio_register(struct
+ /* Find our integrated MDIO bus node */
+ dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
+ priv->master_mii_bus = of_mdio_find_bus(dn);
+- if (!priv->master_mii_bus)
++ if (!priv->master_mii_bus) {
++ of_node_put(dn);
+ return -EPROBE_DEFER;
++ }
+
+ get_device(&priv->master_mii_bus->dev);
+ priv->master_mii_dn = dn;
+
+ priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
+- if (!priv->slave_mii_bus)
++ if (!priv->slave_mii_bus) {
++ of_node_put(dn);
+ return -ENOMEM;
++ }
+
+ priv->slave_mii_bus->priv = priv;
+ priv->slave_mii_bus->name = "sf2 slave mii";
--- /dev/null
+From 20776b465c0c249f5e5b5b4fe077cd24ef1cda86 Mon Sep 17 00:00:00 2001
+From: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Date: Mon, 25 Jan 2021 13:41:16 +0100
+Subject: net: switchdev: don't set port_obj_info->handled true when -EOPNOTSUPP
+
+From: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+
+commit 20776b465c0c249f5e5b5b4fe077cd24ef1cda86 upstream.
+
+It's not true that switchdev_port_obj_notify() only inspects the
+->handled field of "struct switchdev_notifier_port_obj_info" if
+call_switchdev_blocking_notifiers() returns 0 - there's a WARN_ON()
+triggering for a non-zero return combined with ->handled not being
+true. But the real problem here is that -EOPNOTSUPP is not being
+properly handled.
+
+The wrapper functions switchdev_handle_port_obj_add() et al change a
+return value of -EOPNOTSUPP to 0, and the treatment of ->handled in
+switchdev_port_obj_notify() seems to be designed to change that back
+to -EOPNOTSUPP in case nobody actually acted on the notifier (i.e.,
+everybody returned -EOPNOTSUPP).
+
+Currently, as soon as some device down the stack passes the check_cb()
+check, ->handled gets set to true, which means that
+switchdev_port_obj_notify() cannot actually ever return -EOPNOTSUPP.
+
+This, for example, means that the detection of hardware offload
+support in the MRP code is broken: switchdev_port_obj_add() used by
+br_mrp_switchdev_send_ring_test() always returns 0, so since the MRP
+code thinks the generation of MRP test frames has been offloaded, no
+such frames are actually put on the wire. Similarly,
+br_mrp_switchdev_set_ring_role() also always returns 0, causing
+mrp->ring_role_offloaded to be set to 1.
+
+To fix this, continue to set ->handled true if any callback returns
+success or any error distinct from -EOPNOTSUPP. But if all the
+callbacks return -EOPNOTSUPP, make sure that ->handled stays false, so
+the logic in switchdev_port_obj_notify() can propagate that
+information.
+
+Fixes: 9a9f26e8f7ea ("bridge: mrp: Connect MRP API with the switchdev API")
+Fixes: f30f0601eb93 ("switchdev: Add helpers to aid traversal through lower devices")
+Reviewed-by: Petr Machata <petrm@nvidia.com>
+Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Link: https://lore.kernel.org/r/20210125124116.102928-1-rasmus.villemoes@prevas.dk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ net/switchdev/switchdev.c | 23 +++++++++++++----------
+ 1 file changed, 13 insertions(+), 10 deletions(-)
+
+--- a/net/switchdev/switchdev.c
++++ b/net/switchdev/switchdev.c
+@@ -460,10 +460,11 @@ static int __switchdev_handle_port_obj_a
+ extack = switchdev_notifier_info_to_extack(&port_obj_info->info);
+
+ if (check_cb(dev)) {
+- /* This flag is only checked if the return value is success. */
+- port_obj_info->handled = true;
+- return add_cb(dev, port_obj_info->obj, port_obj_info->trans,
+- extack);
++ err = add_cb(dev, port_obj_info->obj, port_obj_info->trans,
++ extack);
++ if (err != -EOPNOTSUPP)
++ port_obj_info->handled = true;
++ return err;
+ }
+
+ /* Switch ports might be stacked under e.g. a LAG. Ignore the
+@@ -515,9 +516,10 @@ static int __switchdev_handle_port_obj_d
+ int err = -EOPNOTSUPP;
+
+ if (check_cb(dev)) {
+- /* This flag is only checked if the return value is success. */
+- port_obj_info->handled = true;
+- return del_cb(dev, port_obj_info->obj);
++ err = del_cb(dev, port_obj_info->obj);
++ if (err != -EOPNOTSUPP)
++ port_obj_info->handled = true;
++ return err;
+ }
+
+ /* Switch ports might be stacked under e.g. a LAG. Ignore the
+@@ -568,9 +570,10 @@ static int __switchdev_handle_port_attr_
+ int err = -EOPNOTSUPP;
+
+ if (check_cb(dev)) {
+- port_attr_info->handled = true;
+- return set_cb(dev, port_attr_info->attr,
+- port_attr_info->trans);
++ err = set_cb(dev, port_attr_info->attr, port_attr_info->trans);
++ if (err != -EOPNOTSUPP)
++ port_attr_info->handled = true;
++ return err;
+ }
+
+ /* Switch ports might be stacked under e.g. a LAG. Ignore the
net-octeontx2-make-sure-the-buffer-is-128-byte-aligned.patch
stmmac-intel-configure-ehl-pse0-gbe-and-pse1-gbe-to-32-bits-dma-addressing.patch
mlxsw-spectrum_span-do-not-overwrite-policer-configuration.patch
+net-dsa-bcm_sf2-put-device-node-before-return.patch
+net-switchdev-don-t-set-port_obj_info-handled-true-when-eopnotsupp.patch
+ibmvnic-ensure-that-crq-entry-read-are-correctly-ordered.patch
+iommu-io-pgtable-arm-support-coherency-for-mali-lpae.patch
+drm-panfrost-support-cache-coherent-integrations.patch
+arm64-dts-meson-describe-g12b-gpu-as-coherent.patch
+arm64-fix-kernel-address-detection-of-__is_lm_address.patch
+arm64-do-not-pass-tagged-addresses-to-__is_lm_address.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
