]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS
authorJohan Jonker <jbx6244@gmail.com>
Mon, 26 Aug 2024 16:39:46 +0000 (18:39 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Wed, 28 Aug 2024 19:25:50 +0000 (21:25 +0200)
CLK_NR_CLKS and CLKPMU_NR_CLKS should not be part of the binding.
Remove since the kernel code no longer uses it.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/a3292ed0-3489-4887-8567-40ea4983c592@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
include/dt-bindings/clock/px30-cru.h
include/dt-bindings/clock/rk3036-cru.h
include/dt-bindings/clock/rk3228-cru.h
include/dt-bindings/clock/rk3288-cru.h
include/dt-bindings/clock/rk3308-cru.h
include/dt-bindings/clock/rk3328-cru.h
include/dt-bindings/clock/rk3368-cru.h
include/dt-bindings/clock/rk3399-cru.h

index 5b1416fcde6fcc0262acb3016222c7fc1568d3cb..a2abf1995c34284719a5857d5b67eebdc2eee376 100644 (file)
 #define PCLK_CIF               352
 #define PCLK_OTP_PHY           353
 
-#define CLK_NR_CLKS            (PCLK_OTP_PHY + 1)
-
 /* pmu-clocks indices */
 
 #define PLL_GPLL               1
 #define PCLK_GPIO0_PMU         20
 #define PCLK_UART0_PMU         21
 
-#define CLKPMU_NR_CLKS         (PCLK_UART0_PMU + 1)
-
 /* soft-reset indices */
 #define SRST_CORE0_PO          0
 #define SRST_CORE1_PO          1
index a96a9870ad59bef673ba65ce3abcb07fb0ae1e56..99cc617e1e54762e363cbca0088a67714248f6c6 100644 (file)
@@ -94,8 +94,6 @@
 #define HCLK_CPU               477
 #define HCLK_PERI              478
 
-#define CLK_NR_CLKS            (HCLK_PERI + 1)
-
 /* soft-reset indices */
 #define SRST_CORE0             0
 #define SRST_CORE1             1
index de550ea56eeb0ef32e98a8549a14d750ab4d4dfb..138b6ce514ddcfd477cc10037a9c59e304db92cb 100644 (file)
 #define HCLK_S_CRYPTO          477
 #define HCLK_PERI              478
 
-#define CLK_NR_CLKS            (HCLK_PERI + 1)
-
 /* soft-reset indices */
 #define SRST_CORE0_PO          0
 #define SRST_CORE1_PO          1
index 33819acbfc561d72241ca17288daaeddf7fc0602..c6034b01b050adb3275061311512efe02f131f30 100644 (file)
 #define HCLK_CPU               477
 #define HCLK_PERI              478
 
-#define CLK_NR_CLKS            (HCLK_PERI + 1)
-
 /* soft-reset indices */
 #define SRST_CORE0             0
 #define SRST_CORE1             1
index d97840f9ee2e15e31cc2f93dcde4afe3c4a1e9e2..ce4cd72b9d3d8d1511e358ff2657a4ead6fc69a6 100644 (file)
 #define PCLK_CAN               233
 #define PCLK_OWIRE             234
 
-#define CLK_NR_CLKS            (PCLK_OWIRE + 1)
-
 /* soft-reset indices */
 
 /* cru_softrst_con0 */
index 555b4ff660ae6d3fa5b53bbf27d3b28a99d6a6c2..8885a2e98c65b63e0f643adc70a070e1ed056e24 100644 (file)
 #define HCLK_RGA               340
 #define HCLK_HDCP              341
 
-#define CLK_NR_CLKS            (HCLK_HDCP + 1)
-
 /* soft-reset indices */
 #define SRST_CORE0_PO          0
 #define SRST_CORE1_PO          1
index 83c72a163fd3a769cbf73d2d2a059315aac6d797..ebae3cbf8192b1769b2a6346145420c3ac1b3dd2 100644 (file)
 #define HCLK_BUS               477
 #define HCLK_PERI              478
 
-#define CLK_NR_CLKS            (HCLK_PERI + 1)
-
 /* soft-reset indices */
 #define SRST_CORE_B0           0
 #define SRST_CORE_B1           1
index 39169d94a44ecd889d7338430e5f3522783c8fab..4c90c7703a83256c073aacbca74aeaf2ed981d90 100644 (file)
 #define HCLK_SDIO_NOC                  495
 #define HCLK_SDIOAUDIO_NOC             496
 
-#define CLK_NR_CLKS                    (HCLK_SDIOAUDIO_NOC + 1)
-
 /* pmu-clocks indices */
 
 #define PLL_PPLL                       1
 #define PCLK_INTR_ARB_PMU              49
 #define HCLK_NOC_PMU                   50
 
-#define CLKPMU_NR_CLKS                 (HCLK_NOC_PMU + 1)
-
 /* soft-reset indices */
 
 /* cru_softrst_con0 */