Fixes for 5.10

Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/queue-5.10/revert-clocksource-drivers-riscv-events-are-stopped-.patch b/queue-5.10/revert-clocksource-drivers-riscv-events-are-stopped-.patch
new file mode 100644 (file)
index 0000000..bf14366
--- /dev/null
+++ b/queue-5.10/revert-clocksource-drivers-riscv-events-are-stopped-.patch
@@ -0,0 +1,96 @@
+From d827b21d88ccf29d0a9b5d7b43f1464755c08243 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 22 Nov 2022 12:16:21 +0000
+Subject: Revert "clocksource/drivers/riscv: Events are stopped during CPU
+ suspend"
+
+From: Conor Dooley <conor.dooley@microchip.com>
+
+[ Upstream commit d9f15a9de44affe733e34f93bc184945ba277e6d ]
+
+This reverts commit 232ccac1bd9b5bfe73895f527c08623e7fa0752d.
+
+On the subject of suspend, the RISC-V SBI spec states:
+
+  This does not cover whether any given events actually reach the hart or
+  not, just what the hart will do if it receives an event. On PolarFire
+  SoC, and potentially other SiFive based implementations, events from the
+  RISC-V timer do reach a hart during suspend. This is not the case for the
+  implementation on the Allwinner D1 - there timer events are not received
+  during suspend.
+
+To fix this, the CLOCK_EVT_FEAT_C3STOP (mis)feature was enabled for the
+timer driver - but this has broken both RCU stall detection and timers
+generally on PolarFire SoC and potentially other SiFive based
+implementations.
+
+If an AXI read to the PCIe controller on PolarFire SoC times out, the
+system will stall, however, with CLOCK_EVT_FEAT_C3STOP active, the system
+just locks up without RCU stalling:
+
+       io scheduler mq-deadline registered
+       io scheduler kyber registered
+       microchip-pcie 2000000000.pcie: host bridge /soc/pcie@2000000000 ranges:
+       microchip-pcie 2000000000.pcie:      MEM 0x2008000000..0x2087ffffff -> 0x0008000000
+       microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer
+       microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer
+       microchip-pcie 2000000000.pcie: axi read request error
+       microchip-pcie 2000000000.pcie: axi read timeout
+       microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer
+       microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer
+       microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer
+       microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer
+       microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer
+       microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer
+       Freeing initrd memory: 7332K
+
+Similarly issues were reported with clock_nanosleep() - with a test app
+that sleeps each cpu for 6, 5, 4, 3 ms respectively, HZ=250 & the blamed
+commit in place, the sleep times are rounded up to the next jiffy:
+
+== CPU: 1 ==      == CPU: 2 ==      == CPU: 3 ==      == CPU: 4 ==
+Mean: 7.974992    Mean: 7.976534    Mean: 7.962591    Mean: 3.952179
+Std Dev: 0.154374 Std Dev: 0.156082 Std Dev: 0.171018 Std Dev: 0.076193
+Hi: 9.472000      Hi: 10.495000     Hi: 8.864000      Hi: 4.736000
+Lo: 6.087000      Lo: 6.380000      Lo: 4.872000      Lo: 3.403000
+Samples: 521      Samples: 521      Samples: 521      Samples: 521
+
+Fortunately, the D1 has a second timer, which is "currently used in
+preference to the RISC-V/SBI timer driver" so a revert here does not
+hurt operation of D1 in its current form.
+
+Ultimately, a DeviceTree property (or node) will be added to encode the
+behaviour of the timers, but until then revert the addition of
+CLOCK_EVT_FEAT_C3STOP.
+
+Fixes: 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during CPU suspend")
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
+Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
+Acked-by: Samuel Holland <samuel@sholland.org>
+Link: https://lore.kernel.org/linux-riscv/YzYTNQRxLr7Q9JR0@spud/
+Link: https://github.com/riscv-non-isa/riscv-sbi-doc/issues/98/
+Link: https://lore.kernel.org/linux-riscv/bf6d3b1f-f703-4a25-833e-972a44a04114@sholland.org/
+Link: https://lore.kernel.org/r/20221122121620.3522431-1-conor.dooley@microchip.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clocksource/timer-riscv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
+index 0e7748df4be3..c51c5ed15aa7 100644
+--- a/drivers/clocksource/timer-riscv.c
++++ b/drivers/clocksource/timer-riscv.c
+@@ -32,7 +32,7 @@ static int riscv_clock_next_event(unsigned long delta,
+ static unsigned int riscv_clock_event_irq;
+ static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
+       .name                   = "riscv_timer_clockevent",
+-      .features               = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP,
++      .features               = CLOCK_EVT_FEAT_ONESHOT,
+       .rating                 = 100,
+       .set_next_event         = riscv_clock_next_event,
+ };
+-- 
+2.35.1
+

diff --git a/queue-5.10/series b/queue-5.10/series
index 07ac09e29621c3e5c898735a6269482adfca93be..57efed51252900f809db16937707d50b40a60042 100644 (file)
--- a/queue-5.10/series
+++ b/queue-5.10/series
@@ -86,3 +86,4 @@ i2c-npcm7xx-fix-error-handling-in-npcm_i2c_init.patch
 i2c-imx-only-dma-messages-with-i2c_m_dma_safe-flag-s.patch
 acpi-hmat-remove-unnecessary-variable-initialization.patch
 acpi-hmat-fix-initiator-registration-for-single-init.patch
+revert-clocksource-drivers-riscv-events-are-stopped-.patch