crypto: octeontx2 - Rework how engine group number is obtained

By default, otx2_cpt_get_kcrypto_eng_grp_num() returns the engine group
number of SE engine type. Add an engine type parameter to support
retrieving the engine group number for different engine types.

Since otx2_cpt_get_kcrypto_eng_grp_num() always returns the kernel crypto
engine group number, rename it to otx2_cpt_get_eng_grp_num().

Signed-off-by: Amit Singh Tomar <amitsinght@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h
index 90a031421aacbffe7313aec23be66727845af9a8..e64ca30335dea5c115c9e1264fe5eff3641a16a4 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h
@@ -555,6 +555,7 @@ struct otx2_cptlf_wqe;
 int otx2_cpt_do_request(struct pci_dev *pdev, struct otx2_cpt_req_info *req,
                        int cpu_num);
 void otx2_cpt_post_process(struct otx2_cptlf_wqe *wqe);
-int otx2_cpt_get_kcrypto_eng_grp_num(struct pci_dev *pdev);
+int otx2_cpt_get_eng_grp_num(struct pci_dev *pdev,
+                            enum otx2_cpt_eng_type);
 
 #endif /* __OTX2_CPT_REQMGR_H */

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h b/drivers/crypto/marvell/octeontx2/otx2_cptlf.h
index 6e004a5568d8862648b4b5ca789f22c0c34c43c3..49ec2b92e86d475676a2eea43ca7a68521c2a5cf 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptlf.h
@@ -124,7 +124,7 @@ struct otx2_cptlfs_info {
        struct cpt_hw_ops *ops;
        u8 are_lfs_attached;    /* Whether CPT LFs are attached */
        u8 lfs_num;             /* Number of CPT LFs */
-       u8 kcrypto_eng_grp_num; /* Kernel crypto engine group number */
+       u8 kcrypto_se_eng_grp_num; /* Crypto symmetric engine group number */
        u8 kvf_limits;          /* Kernel crypto limits */
        atomic_t state;         /* LF's state. started/reset */
        int blkaddr;            /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c b/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c
index 7eb0bc13994d90e905726bc7610cee6a87e20dfa..8d9f394d6b50ea0680653ff44423adb249672625 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c
@@ -384,7 +384,8 @@ static inline int cpt_enc_dec(struct skcipher_request *req, u32 enc)
        req_info->req_type = OTX2_CPT_ENC_DEC_REQ;
        req_info->is_enc = enc;
        req_info->is_trunc_hmac = false;
-       req_info->ctrl.s.grp = otx2_cpt_get_kcrypto_eng_grp_num(pdev);
+       req_info->ctrl.s.grp = otx2_cpt_get_eng_grp_num(pdev,
+                                                       OTX2_CPT_SE_TYPES);
 
        req_info->req.cptr = ctx->er_ctx.hw_ctx;
        req_info->req.cptr_dma = ctx->er_ctx.cptr_dma;
@@ -1288,7 +1289,8 @@ static int cpt_aead_enc_dec(struct aead_request *req, u8 reg_type, u8 enc)
        if (status)
                return status;
 
-       req_info->ctrl.s.grp = otx2_cpt_get_kcrypto_eng_grp_num(pdev);
+       req_info->ctrl.s.grp = otx2_cpt_get_eng_grp_num(pdev,
+                                                       OTX2_CPT_SE_TYPES);
 
        /*
         * We perform an asynchronous send and once

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c b/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
index 56904bdfd6e82bb8fb63730acd361ce94630414c..79adc224066ebed2196c438ad4f9ef038b043eaf 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
@@ -265,17 +265,18 @@ static int cptvf_lf_init(struct otx2_cptvf_dev *cptvf)
        u8 eng_grp_msk;
 
        /* Get engine group number for symmetric crypto */
-       cptvf->lfs.kcrypto_eng_grp_num = OTX2_CPT_INVALID_CRYPTO_ENG_GRP;
+       cptvf->lfs.kcrypto_se_eng_grp_num = OTX2_CPT_INVALID_CRYPTO_ENG_GRP;
        ret = otx2_cptvf_send_eng_grp_num_msg(cptvf, OTX2_CPT_SE_TYPES);
        if (ret)
                return ret;
 
-       if (cptvf->lfs.kcrypto_eng_grp_num == OTX2_CPT_INVALID_CRYPTO_ENG_GRP) {
-               dev_err(dev, "Engine group for kernel crypto not available\n");
-               ret = -ENOENT;
-               return ret;
+       if (cptvf->lfs.kcrypto_se_eng_grp_num ==
+               OTX2_CPT_INVALID_CRYPTO_ENG_GRP) {
+               dev_err(dev,
+                       "Symmetric Engine group for crypto not available\n");
+               return -ENOENT;
        }
-       eng_grp_msk = 1 << cptvf->lfs.kcrypto_eng_grp_num;
+       eng_grp_msk = 1 << cptvf->lfs.kcrypto_se_eng_grp_num;
 
        ret = otx2_cptvf_send_kvf_limits_msg(cptvf);
        if (ret)

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c b/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
index 931b72580fd9f8c1f2f4ce25626007d4c0f2ce5e..f36d75f40014921ff104a1add1a502e4208cce57 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
@@ -75,6 +75,7 @@ static void process_pfvf_mbox_mbox_msg(struct otx2_cptvf_dev *cptvf,
        struct otx2_cpt_caps_rsp *eng_caps;
        struct cpt_rd_wr_reg_msg *rsp_reg;
        struct msix_offset_rsp *rsp_msix;
+       u8 grp_num;
        int i;
 
        if (msg->id >= MBOX_MSG_MAX) {
@@ -122,7 +123,9 @@ static void process_pfvf_mbox_mbox_msg(struct otx2_cptvf_dev *cptvf,
                break;
        case MBOX_MSG_GET_ENG_GRP_NUM:
                rsp_grp = (struct otx2_cpt_egrp_num_rsp *) msg;
-               cptvf->lfs.kcrypto_eng_grp_num = rsp_grp->eng_grp_num;
+               grp_num = rsp_grp->eng_grp_num;
+               if (rsp_grp->eng_type == OTX2_CPT_SE_TYPES)
+                       cptvf->lfs.kcrypto_se_eng_grp_num = grp_num;
                break;
        case MBOX_MSG_GET_KVF_LIMITS:
                rsp_limits = (struct otx2_cpt_kvf_limits_rsp *) msg;

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c b/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c
index 426244107037297fa3b25d153345b3a0380fb687..8b4ac269330acebe97531e22b933ae42586334f7 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c
@@ -391,9 +391,17 @@ void otx2_cpt_post_process(struct otx2_cptlf_wqe *wqe)
                              &wqe->lfs->lf[wqe->lf_num].pqueue);
 }
 
-int otx2_cpt_get_kcrypto_eng_grp_num(struct pci_dev *pdev)
+int otx2_cpt_get_eng_grp_num(struct pci_dev *pdev,
+                            enum otx2_cpt_eng_type eng_type)
 {
        struct otx2_cptvf_dev *cptvf = pci_get_drvdata(pdev);
 
-       return cptvf->lfs.kcrypto_eng_grp_num;
+       switch (eng_type) {
+       case OTX2_CPT_SE_TYPES:
+               return cptvf->lfs.kcrypto_se_eng_grp_num;
+       default:
+               dev_err(&cptvf->pdev->dev, "Unsupported engine type");
+               break;
+       }
+       return -ENXIO;
 }