drm/amdgpu: Modify the seq64 VM cache policy

The seq64 VM cache policy should be set to UC (Uncached) to
match with userqueue fence address kernel mapped memory's
cache settings.

Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c
index 2de1a844282ecd58f223eef02e929d70ac725ff1..3939761be31c9a5d2d9c073bff11712010ffab9d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c
@@ -67,9 +67,9 @@ static inline u64 amdgpu_seq64_get_va_base(struct amdgpu_device *adev)
 int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm,
                     struct amdgpu_bo_va **bo_va)
 {
+       u64 seq64_addr, va_flags;
        struct amdgpu_bo *bo;
        struct drm_exec exec;
-       u64 seq64_addr;
        int r;
 
        bo = adev->seq64.sbo;
@@ -93,8 +93,10 @@ int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm,
        }
 
        seq64_addr = amdgpu_seq64_get_va_base(adev) & AMDGPU_GMC_HOLE_MASK;
+
+       va_flags = amdgpu_gem_va_map_flags(adev, AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_MTYPE_UC);
        r = amdgpu_vm_bo_map(adev, *bo_va, seq64_addr, 0, AMDGPU_VA_RESERVED_SEQ64_SIZE,
-                            AMDGPU_PTE_READABLE);
+                            va_flags);
        if (r) {
                DRM_ERROR("failed to do bo_map on userq sem, err=%d\n", r);
                amdgpu_vm_bo_del(adev, *bo_va);