]> git.ipfire.org Git - thirdparty/qemu.git/commitdiff
target/mips: Remove CPU_NANOMIPS32 definition
authorPhilippe Mathieu-Daudé <f4bug@amsat.org>
Sun, 10 Jan 2021 21:44:59 +0000 (22:44 +0100)
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>
Thu, 14 Jan 2021 16:13:54 +0000 (17:13 +0100)
nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already
defined as ISA_NANOMIPS32.
Remove this incorrect definition and update the single CPU
implementing it, the I7200.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-3-f4bug@amsat.org>

target/mips/cpu-defs.c.inc
target/mips/mips-defs.h

index ba22ff4bcd1fb050d9fa59a9801f925c9369b160..9f7bac879321f2feee99c5664183d94a38855c48 100644 (file)
@@ -486,8 +486,8 @@ const mips_def_t mips_defs[] =
         .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
         .SEGBITS = 32,
         .PABITS = 32,
-        .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 |
-                      ASE_MT,
+        .insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 |
+                      ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT,
         .mmu_type = MMU_TYPE_R4000,
     },
 #if defined(TARGET_MIPS64)
index b7879be9e90b387734107ab9a3e42a3b06cdb882..3704db8553200e30244135fd035003736012deac 100644 (file)
@@ -86,9 +86,6 @@
 #define CPU_MIPS32R6    (CPU_MIPS32R5 | ISA_MIPS_R6)
 #define CPU_MIPS64R6    (CPU_MIPS64R5 | CPU_MIPS32R6)
 
-/* Wave Computing: "nanoMIPS" */
-#define CPU_NANOMIPS32  (CPU_MIPS32R6 | ISA_NANOMIPS32)
-
 #define CPU_LOONGSON3A  (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
 
 /*