Enable VBMI2 support [1/7]

gcc/
	* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI2_SET,
	OPTION_MASK_ISA_AVX512VBMI2_UNSET): New.
	(ix86_handle_option): Handle -mavx512vbmi2.
	* config/i386/cpuid.h: Add bit_AVX512VBMI2.
	* config/i386/driver-i386.c (host_detect_local_cpu): Handle new bit.
	* config/i386/i386-c.c (__AVX512VBMI2__): New.
	* config/i386/i386.c (ix86_target_string): Handle -mavx512vbmi2.
	(ix86_valid_target_attribute_inner_p): Ditto.
	* config/i386/i386.h (TARGET_AVX512VBMI2, TARGET_AVX512VBMI2_P): New.
	* config/i386/i386.opt (mavx512vbmi2): New option.
	* doc/invoke.texi: Add new option.

From-SVN: r254796

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bb2c688a544136cd4e92b1cfe5c29dc93ae0c234..8a716afb006666cfe6d537577cac193985ad28b5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,19 @@
 2017-11-16  Julia Koval  <julia.koval@intel.com>
 
+       * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI2_SET,
+       OPTION_MASK_ISA_AVX512VBMI2_UNSET): New.
+       (ix86_handle_option): Handle -mavx512vbmi2.
+       * config/i386/cpuid.h: Add bit_AVX512VBMI2.
+       * config/i386/driver-i386.c (host_detect_local_cpu): Handle new bit.
+       * config/i386/i386-c.c (__AVX512VBMI2__): New.
+       * config/i386/i386.c (ix86_target_string): Handle -mavx512vbmi2.
+       (ix86_valid_target_attribute_inner_p): Ditto.
+       * config/i386/i386.h (TARGET_AVX512VBMI2, TARGET_AVX512VBMI2_P): New.
+       * config/i386/i386.opt (mavx512vbmi2): New option.
+       * doc/invoke.texi: Add new option.
+
+[2017-11-16  Julia Koval  <julia.koval@intel.com>
+
        * config/i386/gfniintrin.h (_mm_gf2p8mul_epi8, _mm256_gf2p8mul_epi8,
        _mm_mask_gf2p8mul_epi8, _mm_maskz_gf2p8mul_epi8,
        _mm256_mask_gf2p8mul_epi8, _mm256_maskz_gf2p8mul_epi8,

diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index acad2485110ec6a5b1cd10a81dd455e2853dbf4a..b7a0ff5feb8fcd80b4928ad57705fd61f4131044 100644 (file)
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -80,6 +80,7 @@ along with GCC; see the file COPYING3.  If not see
   (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
 #define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS
 #define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW
+#define OPTION_MASK_ISA_AVX512VBMI2_SET OPTION_MASK_ISA_AVX512VBMI2
 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET OPTION_MASK_ISA_AVX512VPOPCNTDQ
 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
@@ -191,6 +192,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
 #define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS
 #define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW
+#define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
@@ -565,6 +567,21 @@ ix86_handle_option (struct gcc_options *opts,
        }
       return true;
 
+    case OPT_mavx512vbmi2:
+      if (value)
+       {
+         opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512VBMI2_SET;
+         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
+         opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
+         opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
+       }
+      else
+       {
+         opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
+         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
+       }
+      return true;
+
     case OPT_mavx512vpopcntdq:
       if (value)
        {

diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 8cb1848dff5c1a7e414704ecacab699eb608788e..4fad5d2b6e1e701de5a2cf1464ac373c2d5f3335 100644 (file)
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -97,6 +97,7 @@
 #define bit_AVX512VBMI (1 << 1)
 #define bit_PKU        (1 << 3)
 #define bit_OSPKE      (1 << 4)
+#define bit_AVX512VBMI2        (1 << 6)
 #define bit_SHSTK      (1 << 7)
 #define bit_GFNI       (1 << 8)
 #define bit_AVX512VPOPCNTDQ    (1 << 14)

diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 80283996343bc0f62ff8a844855e8b7436bc3cab..8482eeba3d6ebdda91f419db08ca5d9264bdb35c 100644 (file)
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -415,7 +415,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
   unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
   unsigned int has_mwaitx = 0, has_clzero = 0, has_pku = 0, has_rdpid = 0;
   unsigned int has_avx5124fmaps = 0, has_avx5124vnniw = 0;
-  unsigned int has_gfni = 0;
+  unsigned int has_gfni = 0, has_avx512vbmi2 = 0;
   unsigned int has_ibt = 0, has_shstk = 0;
 
   bool arch;
@@ -505,6 +505,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       has_prefetchwt1 = ecx & bit_PREFETCHWT1;
       has_avx512vbmi = ecx & bit_AVX512VBMI;
       has_pku = ecx & bit_OSPKE;
+      has_avx512vbmi2 = ecx & bit_AVX512VBMI2;
       has_rdpid = ecx & bit_RDPID;
       has_gfni = ecx & bit_GFNI;
 
@@ -1048,6 +1049,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
       const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
       const char *avx5124vnniw = has_avx5124vnniw ? " -mavx5124vnniw" : " -mno-avx5124vnniw";
+      const char *avx512vbmi2 = has_avx512vbmi2 ? " -mavx512vbmi2" : " -mno-avx512vbmi2";
       const char *avx5124fmaps = has_avx5124fmaps ? " -mavx5124fmaps" : " -mno-avx5124fmaps";
       const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
       const char *mwaitx  = has_mwaitx  ? " -mmwaitx"  : " -mno-mwaitx"; 
@@ -1066,7 +1068,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
                        avx512cd, avx512pf, prefetchwt1, clflushopt,
                        xsavec, xsaves, avx512dq, avx512bw, avx512vl,
                        avx512ifma, avx512vbmi, avx5124fmaps, avx5124vnniw,
-                       clwb, mwaitx, clzero, pku, rdpid, gfni, ibt, shstk, NULL);
+                       clwb, mwaitx, clzero, pku, rdpid, gfni, ibt, shstk,
+                       avx512vbmi2, NULL);
     }
 
 done:

diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 18042cd10a84128a95791605d8549472b3d61941..e812ce99b79e9552d9396df93499d6d982ebf848 100644 (file)
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -385,6 +385,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     def_or_undef (parse_in, "__AVX512IFMA__");
   if (isa_flag2 & OPTION_MASK_ISA_AVX5124VNNIW)
     def_or_undef (parse_in, "__AVX5124VNNIW__");
+  if (isa_flag2 & OPTION_MASK_ISA_AVX512VBMI2)
+    def_or_undef (parse_in, "__AVX512VBMI2__");
   if (isa_flag2 & OPTION_MASK_ISA_SGX)
     def_or_undef (parse_in, "__SGX__");
   if (isa_flag2 & OPTION_MASK_ISA_AVX5124FMAPS)

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index c736cd6370c6a868638233fbaff7ffd0d4f7ad5f..7d4cc61bf4ae0b9bd0a329a4ca73ebd07657b367 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2744,6 +2744,7 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2,
   static struct ix86_target_opts isa2_opts[] =
   {
     { "-mmpx",         OPTION_MASK_ISA_MPX },
+    { "-mavx512vbmi2", OPTION_MASK_ISA_AVX512VBMI2 },
     { "-mrdpid",       OPTION_MASK_ISA_RDPID },
     { "-msgx",         OPTION_MASK_ISA_SGX },
     { "-mavx5124vnniw", OPTION_MASK_ISA_AVX5124VNNIW },
@@ -5243,6 +5244,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
     IX86_ATTR_ISA ("avx5124fmaps", OPT_mavx5124fmaps),
     IX86_ATTR_ISA ("avx5124vnniw", OPT_mavx5124vnniw),
     IX86_ATTR_ISA ("avx512vpopcntdq", OPT_mavx512vpopcntdq),
+    IX86_ATTR_ISA ("avx512vbmi2", OPT_mavx512vbmi2),
 
     IX86_ATTR_ISA ("avx512vbmi", OPT_mavx512vbmi),
     IX86_ATTR_ISA ("avx512ifma", OPT_mavx512ifma),

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index a45e2df578374c65d3d9eccef98aead24cc72960..bc601c8e6f8739d026292fee1a16c0718f55d852 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -85,6 +85,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define TARGET_AVX5124FMAPS_P(x) TARGET_ISA_AVX5124FMAPS_P(x)
 #define TARGET_AVX5124VNNIW    TARGET_ISA_AVX5124VNNIW
 #define TARGET_AVX5124VNNIW_P(x) TARGET_ISA_AVX5124VNNIW_P(x)
+#define TARGET_AVX512VBMI2     TARGET_ISA_AVX512VBMI2
+#define TARGET_AVX512VBMI2_P(x) TARGET_ISA_AVX512VBMI2_P(x)
 #define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ
 #define TARGET_AVX512VPOPCNTDQ_P(x) TARGET_ISA_AVX512VPOPCNTDQ_P(x)
 #define TARGET_FMA     TARGET_ISA_FMA

diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index d2c10ab24d1b799136d81052f9a51a4570574815..0fb46989ef5cd56a54d36de407a6fbd5b5ce1f3e 100644 (file)
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -717,6 +717,10 @@ mavx512vpopcntdq
 Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation.
 
+mavx512vbmi2
+Target Report Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation.
+
 mfma
 Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation.

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 163e16819e63e119f2b8a7e0cf37282e23372b86..85c980bdfc9cfaf74d81313913be0f3f112fc769 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1204,8 +1204,8 @@ See RS/6000 and PowerPC Options.
 -mprefetchwt1  -mclflushopt  -mxsavec  -mxsaves @gol
 -msse4a  -m3dnow  -m3dnowa  -mpopcnt  -mabm  -mbmi  -mtbm  -mfma4  -mxop @gol
 -mlzcnt  -mbmi2  -mfxsr  -mxsave  -mxsaveopt  -mrtm  -mlwp  -mmpx  @gol
--mmwaitx  -mclzero  -mpku  -mthreads @gol
--mcet -mibt -mshstk -mforce-indirect-call @gol
+-mmwaitx  -mclzero  -mpku  -mthreads -mgfni @gol
+-mcet -mibt -mshstk -mforce-indirect-call -mavx512vbmi2 @gol
 -mms-bitfields  -mno-align-stringops  -minline-all-stringops @gol
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg} @gol
 -mmemcpy-strategy=@var{strategy}  -mmemset-strategy=@var{strategy} @gol
@@ -26012,12 +26012,18 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @need 200
 @itemx -mcet
 @opindex mcet
+@need 200
+@itemx -mavx512vbmi2
+@opindex mavx512vbmi2
+@need 200
+@itemx -mgfni
+@opindex mgfni
 These switches enable the use of instructions in the MMX, SSE,
 SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD,
 SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM,
-AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA AVX512VBMI, BMI, BMI2, FXSR,
-XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU, IBT, SHSTK,
-3DNow!@: or enhanced 3DNow!@: extended instruction sets.  Each has a
+AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, BMI, BMI2,
+FXSR, XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU, IBT, SHSTK, AVX512VBMI2,
+GFNI, 3DNow!@: or enhanced 3DNow!@: extended instruction sets.  Each has a
 corresponding @option{-mno-} option to disable use of these instructions.
 
 These extensions are also available as built-in functions: see