switch (op3) {
case LDDA:
if (!chk_asi(sregs, &asi, op3)) break;
+ ATTRIBUTE_FALLTHROUGH;
case LDD:
if (address & 0x7) {
sregs->trap = TRAP_UNALI;
case LDA:
if (!chk_asi(sregs, &asi, op3)) break;
+ ATTRIBUTE_FALLTHROUGH;
case LD:
if (address & 0x3) {
sregs->trap = TRAP_UNALI;
break;
case LDSTUBA:
if (!chk_asi(sregs, &asi, op3)) break;
+ ATTRIBUTE_FALLTHROUGH;
case LDSTUB:
mexc = memory_read(asi, address, &data, 0, &ws);
sregs->hold += ws;
case LDSBA:
case LDUBA:
if (!chk_asi(sregs, &asi, op3)) break;
+ ATTRIBUTE_FALLTHROUGH;
case LDSB:
case LDUB:
mexc = memory_read(asi, address, &data, 0, &ws);
case LDSHA:
case LDUHA:
if (!chk_asi(sregs, &asi, op3)) break;
+ ATTRIBUTE_FALLTHROUGH;
case LDSH:
case LDUH:
if (address & 0x1) {
case STA:
if (!chk_asi(sregs, &asi, op3)) break;
+ ATTRIBUTE_FALLTHROUGH;
case ST:
if (address & 0x3) {
sregs->trap = TRAP_UNALI;
break;
case STBA:
if (!chk_asi(sregs, &asi, op3)) break;
+ ATTRIBUTE_FALLTHROUGH;
case STB:
mexc = memory_write(asi, address, rdd, 0, &ws);
sregs->hold += ws;
break;
case STDA:
if (!chk_asi(sregs, &asi, op3)) break;
+ ATTRIBUTE_FALLTHROUGH;
case STD:
if (address & 0x7) {
sregs->trap = TRAP_UNALI;
break;
case STHA:
if (!chk_asi(sregs, &asi, op3)) break;
+ ATTRIBUTE_FALLTHROUGH;
case STH:
if (address & 0x1) {
sregs->trap = TRAP_UNALI;
break;
case SWAPA:
if (!chk_asi(sregs, &asi, op3)) break;
+ ATTRIBUTE_FALLTHROUGH;
case SWAP:
if (address & 0x3) {
sregs->trap = TRAP_UNALI;