RISC-V: Add new constraint R for register even-odd pairs

Although this constraint is not currently used for any instructions, it is very
useful for custom instructions. Additionally, some new standard extensions
(not yet upstream), such as `Zilsd` and `Zclsd`, are potential users of this
constraint. Therefore, I believe there is sufficient justification to add it
now.

gcc/ChangeLog:

	* config/riscv/constraints.md (R): New constraint.
	* doc/md.texi: Document new constraint `R`.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/constraint-R.c: New.

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 2dce9832219b9193a75145c2569a0603a3168d58..ebb71000d123d830f4901fcc34e48af2e1358941 100644 (file)
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -28,6 +28,10 @@
 (define_register_constraint "j" "SIBCALL_REGS"
   "@internal")
 
+(define_register_constraint "R" "GR_REGS"
+  "Even-odd general purpose register pair."
+  "regno % 2 == 0")
+
 ;; Avoid using register t0 for JALR's argument, because for some
 ;; microarchitectures that is a return-address stack hint.
 (define_register_constraint "l" "JALR_REGS"

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index d5e5367e4efe31727aa08d0a8c638090a7f909ca..32faede817ad69a2361aacbddf9eed07f15bb010 100644 (file)
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3667,6 +3667,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item R
+Even-odd general purpose register pair.
+
 @end table
 
 @item RX---@file{config/rx/constraints.md}

diff --git a/gcc/testsuite/gcc.target/riscv/constraint-R.c b/gcc/testsuite/gcc.target/riscv/constraint-R.c
new file mode 100644 (file)
index 0000000..cb13d8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-R.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-additional-options "-std=gnu99" } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi t1, (a[0246]|s[02468]|t[02]), 1
+**   ...
+*/
+    __asm__ volatile("addi t1, %0, 1" : : "R" (a1) : "memory");
+}
+void foo2(int a0, long long a1a2) {
+/*
+** foo2:
+**   ...
+**   addi t1, (a[0246]|s[02468]|t[02]), 1
+**   ...
+*/
+    __asm__ volatile("addi t1, %0, 1" : : "R" (a1a2) : "memory");
+}