drm/amdgpu: Add gfx doorbell setting for Vangogh

Using KIQ to map GFX queues instead of MMIO for gfx async ring,
add missing doorbell range setting.

v2: fix typo

Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a6d03931f7fa40a678ff71fcd2cba681437334d9..c291d1ba446b9a961eba68f97ec5fa2c2a141dae 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5995,17 +5995,19 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
 {
        u32 tmp;
 
-       tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
-       if (ring->use_doorbell) {
-               tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
-                                   DOORBELL_OFFSET, ring->doorbell_index);
-               tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
-                                   DOORBELL_EN, 1);
-       } else {
-               tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
-                                   DOORBELL_EN, 0);
+       if (!amdgpu_async_gfx_ring) {
+               tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
+               if (ring->use_doorbell) {
+                       tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
+                                               DOORBELL_OFFSET, ring->doorbell_index);
+                       tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
+                                               DOORBELL_EN, 1);
+               } else {
+                       tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
+                                               DOORBELL_EN, 0);
+               }
+               WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
        }
-       WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
@@ -6349,6 +6351,8 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
                                    DOORBELL_EN, 0);
        mqd->cp_rb_doorbell_control = tmp;
 
+       /* set doorbell range */
+       gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
        /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
        ring->wptr = 0;
        mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 27d9000b1955841ef8a4091515fbf6ea67808fa7..1c1af7483dfe3eb5f7261fc761223da036fe0220 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -761,7 +761,7 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
        return ret;
 }
 
-int vangogh_set_default_dpm_tables(struct smu_context *smu)
+static int vangogh_set_default_dpm_tables(struct smu_context *smu)
 {
        struct smu_table_context *smu_table = &smu->smu_table;