--- /dev/null
+From 753872373b599384ac7df809aa61ea12d1c4d5d1 Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+Date: Thu, 22 Mar 2018 10:11:30 +0100
+Subject: clk: bcm2835: De-assert/assert PLL reset signal when appropriate
+
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+
+commit 753872373b599384ac7df809aa61ea12d1c4d5d1 upstream.
+
+In order to enable a PLL, not only the PLL has to be powered up and
+locked, but you also have to de-assert the reset signal. The last part
+was missing. Add it so PLLs that were not enabled by the FW/bootloader
+can be enabled from Linux.
+
+Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/bcm/clk-bcm2835.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -545,9 +545,7 @@ static void bcm2835_pll_off(struct clk_h
+ const struct bcm2835_pll_data *data = pll->data;
+
+ spin_lock(&cprman->regs_lock);
+- cprman_write(cprman, data->cm_ctrl_reg,
+- cprman_read(cprman, data->cm_ctrl_reg) |
+- CM_PLL_ANARST);
++ cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
+ cprman_write(cprman, data->a2w_ctrl_reg,
+ cprman_read(cprman, data->a2w_ctrl_reg) |
+ A2W_PLL_CTRL_PWRDN);
+@@ -583,6 +581,10 @@ static int bcm2835_pll_on(struct clk_hw
+ cpu_relax();
+ }
+
++ cprman_write(cprman, data->a2w_ctrl_reg,
++ cprman_read(cprman, data->a2w_ctrl_reg) |
++ A2W_PLL_CTRL_PRST_DISABLE);
++
+ return 0;
+ }
+
--- /dev/null
+From ce33f284935e08229046b30635e6aadcbab02b53 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Fri, 16 Feb 2018 16:27:47 +0100
+Subject: clk: fix false-positive Wmaybe-uninitialized warning
+
+From: Arnd Bergmann <arnd@arndb.de>
+
+commit ce33f284935e08229046b30635e6aadcbab02b53 upstream.
+
+When we build this driver with on x86-32, gcc produces a false-positive warning:
+
+drivers/clk/renesas/clk-sh73a0.c: In function 'sh73a0_cpg_clocks_init':
+drivers/clk/renesas/clk-sh73a0.c:155:10: error: 'parent_name' may be used uninitialized in this function [-Werror=maybe-uninitialized]
+ return clk_register_fixed_factor(NULL, name, parent_name, 0,
+
+We can work around that warning by adding a fake initialization, I tried
+and failed to come up with any better workaround. This is currently one
+of few remaining warnings for a 4.14.y randconfig build, so it would be
+good to also have it backported at least to that version. Older versions
+have more randconfig warnings, so we might not care.
+
+I had not noticed this earlier, because one patch in my randconfig test
+tree removes the '-ffreestanding' option on x86-32, and that avoids
+the warning. The -ffreestanding flag was originally global but moved
+into arch/i386 by Andi Kleen in commit 6edfba1b33c7 ("[PATCH] x86_64:
+Don't define string functions to builtin") as a 'temporary workaround'.
+
+Like many temporary hacks, this turned out to be rather long-lived, from
+all I can tell we still need a simple fix to asm/string_32.h before it
+can be removed, but I'm not sure about how to best do that.
+
+Cc: stable@vger.kernel.org
+Cc: Andi Kleen <ak@linux.intel.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/renesas/clk-sh73a0.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/renesas/clk-sh73a0.c
++++ b/drivers/clk/renesas/clk-sh73a0.c
+@@ -46,7 +46,7 @@ struct div4_clk {
+ unsigned int shift;
+ };
+
+-static struct div4_clk div4_clks[] = {
++static const struct div4_clk div4_clks[] = {
+ { "zg", "pll0", CPG_FRQCRA, 16 },
+ { "m3", "pll1", CPG_FRQCRA, 12 },
+ { "b", "pll1", CPG_FRQCRA, 8 },
+@@ -79,7 +79,7 @@ sh73a0_cpg_register_clock(struct device_
+ {
+ const struct clk_div_table *table = NULL;
+ unsigned int shift, reg, width;
+- const char *parent_name;
++ const char *parent_name = NULL;
+ unsigned int mult = 1;
+ unsigned int div = 1;
+
+@@ -135,7 +135,7 @@ sh73a0_cpg_register_clock(struct device_
+ shift = 24;
+ width = 5;
+ } else {
+- struct div4_clk *c;
++ const struct div4_clk *c;
+
+ for (c = div4_clks; c->name; c++) {
+ if (!strcmp(name, c->name)) {
--- /dev/null
+From 9593f4f56cf5d1c443f66660a0c7f01de38f979d Mon Sep 17 00:00:00 2001
+From: Ralph Sennhauser <ralph.sennhauser@gmail.com>
+Date: Wed, 24 May 2017 16:58:52 +0200
+Subject: clk: mvebu: armada-38x: add support for 1866MHz variants
+
+From: Ralph Sennhauser <ralph.sennhauser@gmail.com>
+
+commit 9593f4f56cf5d1c443f66660a0c7f01de38f979d upstream.
+
+The Linksys WRT3200ACM CPU is clocked at 1866MHz. Add 1866MHz to the
+list of supported CPU frequencies. Also update multiplier and divisor
+for the l2clk and ddrclk.
+
+Noticed by the following warning:
+[ 0.000000] Selected CPU frequency (16) unsupported
+
+Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
+Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/mvebu/armada-38x.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/mvebu/armada-38x.c
++++ b/drivers/clk/mvebu/armada-38x.c
+@@ -49,7 +49,8 @@ static const u32 armada_38x_cpu_frequenc
+ 0, 0, 0, 0,
+ 1066 * 1000 * 1000, 0, 0, 0,
+ 1332 * 1000 * 1000, 0, 0, 0,
+- 1600 * 1000 * 1000,
++ 1600 * 1000 * 1000, 0, 0, 0,
++ 1866 * 1000 * 1000,
+ };
+
+ static u32 __init armada_38x_get_cpu_freq(void __iomem *sar)
+@@ -79,7 +80,7 @@ static const int armada_38x_cpu_l2_ratio
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+- {0, 1}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+@@ -90,7 +91,7 @@ static const int armada_38x_cpu_ddr_rati
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+- {0, 1}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
--- /dev/null
+From 6a4a4595804548e173f0763a0e7274a3521c59a9 Mon Sep 17 00:00:00 2001
+From: Richard Genoud <richard.genoud@gmail.com>
+Date: Tue, 13 Mar 2018 16:27:02 +0100
+Subject: clk: mvebu: armada-38x: add support for missing clocks
+
+From: Richard Genoud <richard.genoud@gmail.com>
+
+commit 6a4a4595804548e173f0763a0e7274a3521c59a9 upstream.
+
+Clearfog boards can come with a CPU clocked at 1600MHz (commercial)
+or 1333MHz (industrial).
+
+They have also some dip-switches to select a different clock (666, 800,
+1066, 1200).
+
+The funny thing is that the recovery button is on the MPP34 fq selector.
+So, when booting an industrial board with this button down, the frequency
+666MHz is selected (and the kernel didn't boot).
+
+This patch add all the missing clocks.
+
+The only mode I didn't test is 2GHz (uboot found 4294MHz instead :/ ).
+
+Fixes: 0e85aeced4d6 ("clk: mvebu: add clock support for Armada 380/385")
+Cc: <stable@vger.kernel.org> # 3.16.x: 9593f4f56cf5: clk: mvebu: armada-38x: add support for 1866MHz variants
+Cc: <stable@vger.kernel.org> # 3.16.x
+
+Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
+Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/mvebu/armada-38x.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+--- a/drivers/clk/mvebu/armada-38x.c
++++ b/drivers/clk/mvebu/armada-38x.c
+@@ -46,11 +46,11 @@ static u32 __init armada_38x_get_tclk_fr
+ }
+
+ static const u32 armada_38x_cpu_frequencies[] __initconst = {
+- 0, 0, 0, 0,
+- 1066 * 1000 * 1000, 0, 0, 0,
++ 666 * 1000 * 1000, 0, 800 * 1000 * 1000, 0,
++ 1066 * 1000 * 1000, 0, 1200 * 1000 * 1000, 0,
+ 1332 * 1000 * 1000, 0, 0, 0,
+ 1600 * 1000 * 1000, 0, 0, 0,
+- 1866 * 1000 * 1000,
++ 1866 * 1000 * 1000, 0, 0, 2000 * 1000 * 1000,
+ };
+
+ static u32 __init armada_38x_get_cpu_freq(void __iomem *sar)
+@@ -76,11 +76,11 @@ static const struct coreclk_ratio armada
+ };
+
+ static const int armada_38x_cpu_l2_ratios[32][2] __initconst = {
+- {0, 1}, {0, 1}, {0, 1}, {0, 1},
+- {1, 2}, {0, 1}, {0, 1}, {0, 1},
+- {1, 2}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {1, 2}, {0, 1},
++ {1, 2}, {0, 1}, {1, 2}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {0, 1}, {1, 2},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+@@ -91,7 +91,7 @@ static const int armada_38x_cpu_ddr_rati
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+- {1, 2}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {0, 1}, {7, 15},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
--- /dev/null
+From 55a5fcafe3a94e8a0777bb993d09107d362258d2 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Thu, 1 Mar 2018 11:27:50 +0800
+Subject: dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4
+
+From: Sean Wang <sean.wang@mediatek.com>
+
+commit 55a5fcafe3a94e8a0777bb993d09107d362258d2 upstream.
+
+Just add binding for a fixed-factor clock axisel_d4, which would be
+referenced by PWM devices on MT7623 or MT2701 SoC.
+
+Cc: stable@vger.kernel.org
+Fixes: 1de9b21633d6 ("clk: mediatek: Add dt-bindings for MT2701 clocks")
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Cc: Mark Rutland <mark.rutland@arm.com>
+Cc: devicetree@vger.kernel.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ include/dt-bindings/clock/mt2701-clk.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/include/dt-bindings/clock/mt2701-clk.h
++++ b/include/dt-bindings/clock/mt2701-clk.h
+@@ -176,7 +176,8 @@
+ #define CLK_TOP_AUD_EXT1 156
+ #define CLK_TOP_AUD_EXT2 157
+ #define CLK_TOP_NFI1X_PAD 158
+-#define CLK_TOP_NR 159
++#define CLK_TOP_AXISEL_D4 159
++#define CLK_TOP_NR 160
+
+ /* APMIXEDSYS */
+
--- /dev/null
+From bbe4b3af9d9e3172fb9aa1f8dcdfaedcb381fc64 Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Sat, 24 Feb 2018 13:42:27 +0800
+Subject: iommu/vt-d: Fix a potential memory leak
+
+From: Lu Baolu <baolu.lu@linux.intel.com>
+
+commit bbe4b3af9d9e3172fb9aa1f8dcdfaedcb381fc64 upstream.
+
+A memory block was allocated in intel_svm_bind_mm() but never freed
+in a failure path. This patch fixes this by free it to avoid memory
+leakage.
+
+Cc: Ashok Raj <ashok.raj@intel.com>
+Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
+Cc: <stable@vger.kernel.org> # v4.4+
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Fixes: 2f26e0a9c9860 ('iommu/vt-d: Add basic SVM PASID support')
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/iommu/intel-svm.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/iommu/intel-svm.c
++++ b/drivers/iommu/intel-svm.c
+@@ -389,6 +389,7 @@ int intel_svm_bind_mm(struct device *dev
+ pasid_max - 1, GFP_KERNEL);
+ if (ret < 0) {
+ kfree(svm);
++ kfree(sdev);
+ goto out;
+ }
+ svm->pasid = ret;
--- /dev/null
+From a04f0017c22453613d5f423326b190c61e3b4f98 Mon Sep 17 00:00:00 2001
+From: Alex Smith <alex.smith@imgtec.com>
+Date: Wed, 28 Mar 2018 18:00:43 -0300
+Subject: mmc: jz4740: Fix race condition in IRQ mask update
+
+From: Alex Smith <alex.smith@imgtec.com>
+
+commit a04f0017c22453613d5f423326b190c61e3b4f98 upstream.
+
+A spinlock is held while updating the internal copy of the IRQ mask,
+but not while writing it to the actual IMASK register. After the lock
+is released, an IRQ can occur before the IMASK register is written.
+If handling this IRQ causes the mask to be changed, when the handler
+returns back to the middle of the first mask update, a stale value
+will be written to the mask register.
+
+If this causes an IRQ to become unmasked that cannot have its status
+cleared by writing a 1 to it in the IREG register, e.g. the SDIO IRQ,
+then we can end up stuck with the same IRQ repeatedly being fired but
+not handled. Normally the MMC IRQ handler attempts to clear any
+unexpected IRQs by writing IREG, but for those that cannot be cleared
+in this way then the IRQ will just repeatedly fire.
+
+This was resulting in lockups after a while of using Wi-Fi on the
+CI20 (GitHub issue #19).
+
+Resolve by holding the spinlock until after the IMASK register has
+been updated.
+
+Cc: stable@vger.kernel.org
+Link: https://github.com/MIPS/CI20_linux/issues/19
+Fixes: 61bfbdb85687 ("MMC: Add support for the controller on JZ4740 SoCs.")
+Tested-by: Mathieu Malaterre <malat@debian.org>
+Signed-off-by: Alex Smith <alex.smith@imgtec.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mmc/host/jz4740_mmc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mmc/host/jz4740_mmc.c
++++ b/drivers/mmc/host/jz4740_mmc.c
+@@ -368,9 +368,9 @@ static void jz4740_mmc_set_irq_enabled(s
+ host->irq_mask &= ~irq;
+ else
+ host->irq_mask |= irq;
+- spin_unlock_irqrestore(&host->lock, flags);
+
+ writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
++ spin_unlock_irqrestore(&host->lock, flags);
+ }
+
+ static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
--- /dev/null
+From 78727137fdf49edf9f731bde79d7189067b4047a Mon Sep 17 00:00:00 2001
+From: Dan Williams <dan.j.williams@intel.com>
+Date: Mon, 2 Apr 2018 16:40:04 -0700
+Subject: nfit, address-range-scrub: fix scrub in-progress reporting
+
+From: Dan Williams <dan.j.williams@intel.com>
+
+commit 78727137fdf49edf9f731bde79d7189067b4047a upstream.
+
+There is a small window whereby ARS scan requests can schedule work that
+userspace will miss when polling scrub_show. Hold the init_mutex lock
+over calls to report the status to close this potential escape. Also,
+make sure that requests to cancel the ARS workqueue are treated as an
+idle event.
+
+Cc: <stable@vger.kernel.org>
+Cc: Vishal Verma <vishal.l.verma@intel.com>
+Fixes: 37b137ff8c83 ("nfit, libnvdimm: allow an ARS scrub...")
+Reviewed-by: Dave Jiang <dave.jiang@intel.com>
+Signed-off-by: Dan Williams <dan.j.williams@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/acpi/nfit/core.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/acpi/nfit/core.c
++++ b/drivers/acpi/nfit/core.c
+@@ -967,8 +967,11 @@ static ssize_t scrub_show(struct device
+ if (nd_desc) {
+ struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
+
++ mutex_lock(&acpi_desc->init_mutex);
+ rc = sprintf(buf, "%d%s", acpi_desc->scrub_count,
+- (work_busy(&acpi_desc->work)) ? "+\n" : "\n");
++ work_busy(&acpi_desc->work)
++ && !acpi_desc->cancel ? "+\n" : "\n");
++ mutex_unlock(&acpi_desc->init_mutex);
+ }
+ device_unlock(dev);
+ return rc;
--- /dev/null
+From 6225f9c64b40bc8a22503e9cda70f55d7a9dd3c6 Mon Sep 17 00:00:00 2001
+From: Ryo Kodama <ryo.kodama.vz@renesas.com>
+Date: Fri, 9 Mar 2018 20:24:21 +0900
+Subject: pwm: rcar: Fix a condition to prevent mismatch value setting to duty
+
+From: Ryo Kodama <ryo.kodama.vz@renesas.com>
+
+commit 6225f9c64b40bc8a22503e9cda70f55d7a9dd3c6 upstream.
+
+This patch fixes an issue that is possible to set mismatch value to duty
+for R-Car PWM if we input the following commands:
+
+ # cd /sys/class/pwm/<pwmchip>/
+ # echo 0 > export
+ # cd pwm0
+ # echo 30 > period
+ # echo 30 > duty_cycle
+ # echo 0 > duty_cycle
+ # cat duty_cycle
+ 0
+ # echo 1 > enable
+ --> Then, the actual duty_cycle is 30, not 0.
+
+So, this patch adds a condition into rcar_pwm_config() to fix this
+issue.
+
+Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
+[shimoda: revise the commit log and add Fixes and Cc tags]
+Fixes: ed6c1476bf7f ("pwm: Add support for R-Car PWM Timer")
+Cc: Cc: <stable@vger.kernel.org> # v4.4+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pwm/pwm-rcar.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+--- a/drivers/pwm/pwm-rcar.c
++++ b/drivers/pwm/pwm-rcar.c
+@@ -156,8 +156,12 @@ static int rcar_pwm_config(struct pwm_ch
+ if (div < 0)
+ return div;
+
+- /* Let the core driver set pwm->period if disabled and duty_ns == 0 */
+- if (!pwm_is_enabled(pwm) && !duty_ns)
++ /*
++ * Let the core driver set pwm->period if disabled and duty_ns == 0.
++ * But, this driver should prevent to set the new duty_ns if current
++ * duty_cycle is not set
++ */
++ if (!pwm_is_enabled(pwm) && !duty_ns && !pwm->state.duty_cycle)
+ return 0;
+
+ rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
ib-srp-fix-completion-vector-assignment-algorithm.patch
dmaengine-at_xdmac-fix-rare-residue-corruption.patch
libnvdimm-namespace-use-a-safe-lookup-for-dimm-device-name.patch
+nfit-address-range-scrub-fix-scrub-in-progress-reporting.patch
+um-compile-with-modern-headers.patch
+um-use-posix-ucontext_t-instead-of-struct-ucontext.patch
+iommu-vt-d-fix-a-potential-memory-leak.patch
+mmc-jz4740-fix-race-condition-in-irq-mask-update.patch
+clk-mvebu-armada-38x-add-support-for-1866mhz-variants.patch
+clk-mvebu-armada-38x-add-support-for-missing-clocks.patch
+clk-fix-false-positive-wmaybe-uninitialized-warning.patch
+clk-bcm2835-de-assert-assert-pll-reset-signal-when-appropriate.patch
+pwm-rcar-fix-a-condition-to-prevent-mismatch-value-setting-to-duty.patch
+thermal-imx-fix-race-condition-in-imx_thermal_probe.patch
+dt-bindings-clock-mediatek-add-binding-for-fixed-factor-clock-axisel_d4.patch
+watchdog-f71808e_wdt-fix-wd_en-register-read.patch
+vfio-pci-virtualize-maximum-read-request-size.patch
--- /dev/null
+From cf1ba1d73a33944d8c1a75370a35434bf146b8a7 Mon Sep 17 00:00:00 2001
+From: Mikhail Lappo <mikhail.lappo@esrlabs.com>
+Date: Fri, 2 Feb 2018 16:17:46 -0200
+Subject: thermal: imx: Fix race condition in imx_thermal_probe()
+
+From: Mikhail Lappo <mikhail.lappo@esrlabs.com>
+
+commit cf1ba1d73a33944d8c1a75370a35434bf146b8a7 upstream.
+
+When device boots with T > T_trip_1 and requests interrupt,
+the race condition takes place. The interrupt comes before
+THERMAL_DEVICE_ENABLED is set. This leads to an attempt to
+reading sensor value from irq and disabling the sensor, based on
+the data->mode field, which expected to be THERMAL_DEVICE_ENABLED,
+but still stays as THERMAL_DEVICE_DISABLED. Afher this issue
+sensor is never re-enabled, as the driver state is wrong.
+
+Fix this problem by setting the 'data' members prior to
+requesting the interrupts.
+
+Fixes: 37713a1e8e4c ("thermal: imx: implement thermal alarm interrupt handling")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Mikhail Lappo <mikhail.lappo@esrlabs.com>
+Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
+Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
+Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
+Signed-off-by: Zhang Rui <rui.zhang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/thermal/imx_thermal.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/thermal/imx_thermal.c
++++ b/drivers/thermal/imx_thermal.c
+@@ -587,6 +587,9 @@ static int imx_thermal_probe(struct plat
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP);
+
++ data->irq_enabled = true;
++ data->mode = THERMAL_DEVICE_ENABLED;
++
+ ret = devm_request_threaded_irq(&pdev->dev, data->irq,
+ imx_thermal_alarm_irq, imx_thermal_alarm_irq_thread,
+ 0, "imx_thermal", data);
+@@ -598,9 +601,6 @@ static int imx_thermal_probe(struct plat
+ return ret;
+ }
+
+- data->irq_enabled = true;
+- data->mode = THERMAL_DEVICE_ENABLED;
+-
+ return 0;
+ }
+
--- /dev/null
+From 530ba6c7cb3c22435a4d26de47037bb6f86a5329 Mon Sep 17 00:00:00 2001
+From: "Jason A. Donenfeld" <Jason@zx2c4.com>
+Date: Thu, 14 Dec 2017 03:23:37 +0100
+Subject: um: Compile with modern headers
+
+From: Jason A. Donenfeld <Jason@zx2c4.com>
+
+commit 530ba6c7cb3c22435a4d26de47037bb6f86a5329 upstream.
+
+Recent libcs have gotten a bit more strict, so we actually need to
+include the right headers and use the right types. This enables UML to
+compile again.
+
+Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Richard Weinberger <richard@nod.at>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/um/os-Linux/file.c | 1 +
+ arch/um/os-Linux/signal.c | 1 +
+ arch/x86/um/stub_segv.c | 1 +
+ 3 files changed, 3 insertions(+)
+
+--- a/arch/um/os-Linux/file.c
++++ b/arch/um/os-Linux/file.c
+@@ -12,6 +12,7 @@
+ #include <sys/mount.h>
+ #include <sys/socket.h>
+ #include <sys/stat.h>
++#include <sys/sysmacros.h>
+ #include <sys/un.h>
+ #include <sys/types.h>
+ #include <os.h>
+--- a/arch/um/os-Linux/signal.c
++++ b/arch/um/os-Linux/signal.c
+@@ -16,6 +16,7 @@
+ #include <os.h>
+ #include <sysdep/mcontext.h>
+ #include <um_malloc.h>
++#include <sys/ucontext.h>
+
+ void (*sig_info[NSIG])(int, struct siginfo *, struct uml_pt_regs *) = {
+ [SIGTRAP] = relay_signal,
+--- a/arch/x86/um/stub_segv.c
++++ b/arch/x86/um/stub_segv.c
+@@ -6,6 +6,7 @@
+ #include <sysdep/stub.h>
+ #include <sysdep/faultinfo.h>
+ #include <sysdep/mcontext.h>
++#include <sys/ucontext.h>
+
+ void __attribute__ ((__section__ (".__syscall_stub")))
+ stub_segv_handler(int sig, siginfo_t *info, void *p)
--- /dev/null
+From 4d1a535b8ec5e74b42dfd9dc809142653b2597f6 Mon Sep 17 00:00:00 2001
+From: Krzysztof Mazur <krzysiek@podlesie.net>
+Date: Wed, 15 Nov 2017 11:12:39 +0100
+Subject: um: Use POSIX ucontext_t instead of struct ucontext
+
+From: Krzysztof Mazur <krzysiek@podlesie.net>
+
+commit 4d1a535b8ec5e74b42dfd9dc809142653b2597f6 upstream.
+
+glibc 2.26 removed the 'struct ucontext' to "improve" POSIX compliance
+and break programs, including User Mode Linux. Fix User Mode Linux
+by using POSIX ucontext_t.
+
+This fixes:
+
+arch/um/os-Linux/signal.c: In function 'hard_handler':
+arch/um/os-Linux/signal.c:163:22: error: dereferencing pointer to incomplete type 'struct ucontext'
+ mcontext_t *mc = &uc->uc_mcontext;
+arch/x86/um/stub_segv.c: In function 'stub_segv_handler':
+arch/x86/um/stub_segv.c:16:13: error: dereferencing pointer to incomplete type 'struct ucontext'
+ &uc->uc_mcontext);
+
+Cc: stable@vger.kernel.org
+Signed-off-by: Krzysztof Mazur <krzysiek@podlesie.net>
+Signed-off-by: Richard Weinberger <richard@nod.at>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/um/os-Linux/signal.c | 2 +-
+ arch/x86/um/stub_segv.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/um/os-Linux/signal.c
++++ b/arch/um/os-Linux/signal.c
+@@ -160,7 +160,7 @@ static void (*handlers[_NSIG])(int sig,
+
+ static void hard_handler(int sig, siginfo_t *si, void *p)
+ {
+- struct ucontext *uc = p;
++ ucontext_t *uc = p;
+ mcontext_t *mc = &uc->uc_mcontext;
+ unsigned long pending = 1UL << sig;
+
+--- a/arch/x86/um/stub_segv.c
++++ b/arch/x86/um/stub_segv.c
+@@ -11,7 +11,7 @@
+ void __attribute__ ((__section__ (".__syscall_stub")))
+ stub_segv_handler(int sig, siginfo_t *info, void *p)
+ {
+- struct ucontext *uc = p;
++ ucontext_t *uc = p;
+
+ GET_FAULTINFO_FROM_MC(*((struct faultinfo *) STUB_DATA),
+ &uc->uc_mcontext);
--- /dev/null
+From cf0d53ba4947aad6e471491d5b20a567cbe92e56 Mon Sep 17 00:00:00 2001
+From: Alex Williamson <alex.williamson@redhat.com>
+Date: Mon, 2 Oct 2017 12:39:10 -0600
+Subject: vfio/pci: Virtualize Maximum Read Request Size
+
+From: Alex Williamson <alex.williamson@redhat.com>
+
+commit cf0d53ba4947aad6e471491d5b20a567cbe92e56 upstream.
+
+MRRS defines the maximum read request size a device is allowed to
+make. Drivers will often increase this to allow more data transfer
+with a single request. Completions to this request are bound by the
+MPS setting for the bus. Aside from device quirks (none known), it
+doesn't seem to make sense to set an MRRS value less than MPS, yet
+this is a likely scenario given that user drivers do not have a
+system-wide view of the PCI topology. Virtualize MRRS such that the
+user can set MRRS >= MPS, but use MPS as the floor value that we'll
+write to hardware.
+
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/vfio/pci/vfio_pci_config.c | 29 ++++++++++++++++++++++++++---
+ 1 file changed, 26 insertions(+), 3 deletions(-)
+
+--- a/drivers/vfio/pci/vfio_pci_config.c
++++ b/drivers/vfio/pci/vfio_pci_config.c
+@@ -810,6 +810,7 @@ static int vfio_exp_config_write(struct
+ {
+ __le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
+ offset + PCI_EXP_DEVCTL);
++ int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ;
+
+ count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
+ if (count < 0)
+@@ -835,6 +836,27 @@ static int vfio_exp_config_write(struct
+ pci_try_reset_function(vdev->pdev);
+ }
+
++ /*
++ * MPS is virtualized to the user, writes do not change the physical
++ * register since determining a proper MPS value requires a system wide
++ * device view. The MRRS is largely independent of MPS, but since the
++ * user does not have that system-wide view, they might set a safe, but
++ * inefficiently low value. Here we allow writes through to hardware,
++ * but we set the floor to the physical device MPS setting, so that
++ * we can at least use full TLPs, as defined by the MPS value.
++ *
++ * NB, if any devices actually depend on an artificially low MRRS
++ * setting, this will need to be revisited, perhaps with a quirk
++ * though pcie_set_readrq().
++ */
++ if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) {
++ readrq = 128 <<
++ ((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12);
++ readrq = max(readrq, pcie_get_mps(vdev->pdev));
++
++ pcie_set_readrq(vdev->pdev, readrq);
++ }
++
+ return count;
+ }
+
+@@ -853,11 +875,12 @@ static int __init init_pci_cap_exp_perm(
+ * Allow writes to device control fields, except devctl_phantom,
+ * which could confuse IOMMU, MPS, which can break communication
+ * with other physical devices, and the ARI bit in devctl2, which
+- * is set at probe time. FLR gets virtualized via our writefn.
++ * is set at probe time. FLR and MRRS get virtualized via our
++ * writefn.
+ */
+ p_setw(perm, PCI_EXP_DEVCTL,
+- PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD,
+- ~PCI_EXP_DEVCTL_PHANTOM);
++ PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD |
++ PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM);
+ p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
+ return 0;
+ }
--- /dev/null
+From 977f6f68331f94bb72ad84ee96b7b87ce737d89d Mon Sep 17 00:00:00 2001
+From: Igor Pylypiv <igor.pylypiv@gmail.com>
+Date: Tue, 6 Mar 2018 23:47:25 -0800
+Subject: watchdog: f71808e_wdt: Fix WD_EN register read
+
+From: Igor Pylypiv <igor.pylypiv@gmail.com>
+
+commit 977f6f68331f94bb72ad84ee96b7b87ce737d89d upstream.
+
+F71808FG_FLAG_WD_EN defines bit position, not a bitmask
+
+Signed-off-by: Igor Pylypiv <igor.pylypiv@gmail.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+Cc: stable <stable@vger.kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/watchdog/f71808e_wdt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/watchdog/f71808e_wdt.c
++++ b/drivers/watchdog/f71808e_wdt.c
+@@ -496,7 +496,7 @@ static bool watchdog_is_running(void)
+
+ is_running = (superio_inb(watchdog.sioaddr, SIO_REG_ENABLE) & BIT(0))
+ && (superio_inb(watchdog.sioaddr, F71808FG_REG_WDT_CONF)
+- & F71808FG_FLAG_WD_EN);
++ & BIT(F71808FG_FLAG_WD_EN));
+
+ superio_exit(watchdog.sioaddr);
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
