aarch64: Mark predicate-as-counter pseudo instructions

Using explicit pseudo aliases is clearer and more consistent with other
instruction aliases.

This does not change behaviour.  For the non-alias instructions
(everything except mov) we already picked the first matching entry for
disassembly by default.  For mov we picked the last matching aliased
entry, which remained the original alias since do_misc_decoding doesn't
recognise OP_MOV_PN_PN.

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 5cb12cc53238bc004176421576138c858c8bd7a5..844cc6d8389f6ff6935e488afc7b11adcd43aa98 100644 (file)
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -584,6 +584,10 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
     case 1488: /* fdup */
       value = 1488;    /* --> fdup.  */
       break;
+    case 1774: /* ldr */
+    case 1773: /* ldr */
+      value = 1773;    /* --> ldr.  */
+      break;
     case 1320: /* mov */
     case 1804: /* orr */
       value = 1804;    /* --> orr.  */
@@ -601,6 +605,10 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
     case 1808: /* orrs */
       value = 1808;    /* --> orrs.  */
       break;
+    case 1811: /* pfalse */
+    case 1810: /* pfalse */
+      value = 1810;    /* --> pfalse.  */
+      break;
     case 1329: /* mov */
     case 1871: /* sel */
       value = 1871;    /* --> sel.  */
@@ -609,6 +617,10 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
     case 1872: /* sel */
       value = 1872;    /* --> sel.  */
       break;
+    case 1993: /* str */
+    case 1992: /* str */
+      value = 1992;    /* --> str.  */
+      break;
     case 2420: /* mov */
     case 2422: /* mova */
       value = 2422;    /* --> mova.  */
@@ -617,6 +629,10 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
     case 2423: /* mova */
       value = 2423;    /* --> mova.  */
       break;
+    case 2441: /* psel */
+    case 2440: /* psel */
+      value = 2440;    /* --> psel.  */
+      break;
     case 2646: /* mov */
     case 2654: /* mova */
       value = 2654;    /* --> mova.  */

diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 9de93e99c01875a6b0ab2aa037b85f709c7ea41d..6af624469f9689ecc4aa5d056b5946dbc331d2d0 100644 (file)
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -34600,8 +34600,6 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
     case 2442: return NULL;            /* rprfm --> NULL.  */
     case 2449: value = 3265; break;    /* fclamp --> bfclamp.  */
     case 3265: return NULL;            /* bfclamp --> NULL.  */
-    case 1773: value = 1774; break;    /* ldr --> ldr.  */
-    case 1774: return NULL;            /* ldr --> NULL.  */
     case 1445: value = 3268; break;    /* fadd --> bfadd.  */
     case 3268: return NULL;            /* bfadd --> NULL.  */
     case 1512: value = 3269; break;    /* fmul --> bfmul.  */
@@ -34610,14 +34608,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
     case 3270: return NULL;            /* bfsub --> NULL.  */
     case 1503: value = 3261; break;    /* fmla --> bfmla.  */
     case 3261: return NULL;            /* bfmla --> NULL.  */
-    case 1992: value = 1993; break;    /* str --> str.  */
-    case 1993: return NULL;            /* str --> NULL.  */
     case 1507: value = 3262; break;    /* fmls --> bfmls.  */
     case 3262: return NULL;            /* bfmls --> NULL.  */
-    case 2440: value = 2441; break;    /* psel --> psel.  */
-    case 2441: return NULL;            /* psel --> NULL.  */
-    case 1810: value = 1811; break;    /* pfalse --> pfalse.  */
-    case 1811: return NULL;            /* pfalse --> NULL.  */
     case 1446: value = 3256; break;    /* fadd --> bfadd.  */
     case 3256: return NULL;            /* bfadd --> NULL.  */
     case 1493: value = 3258; break;    /* fmaxnm --> bfmaxnm.  */
@@ -34992,14 +34984,18 @@ aarch64_find_alias_opcode (const aarch64_opcode *opcode)
     case 1459: value = 2094; break;    /* fcmgt --> fcmlt.  */
     case 1465: value = 1319; break;    /* fcpy --> fmov.  */
     case 1488: value = 1318; break;    /* fdup --> fmov.  */
+    case 1773: value = 1774; break;    /* ldr --> ldr.  */
     case 1804: value = 1320; break;    /* orr --> mov.  */
     case 1805: value = 2097; break;    /* orr --> orn.  */
     case 1807: value = 1324; break;    /* orr --> mov.  */
     case 1808: value = 1334; break;    /* orrs --> movs.  */
+    case 1810: value = 1811; break;    /* pfalse --> pfalse.  */
     case 1871: value = 1329; break;    /* sel --> mov.  */
     case 1872: value = 1332; break;    /* sel --> mov.  */
+    case 1992: value = 1993; break;    /* str --> str.  */
     case 2422: value = 2420; break;    /* mova --> mov.  */
     case 2423: value = 2421; break;    /* mova --> mov.  */
+    case 2440: value = 2441; break;    /* psel --> psel.  */
     case 2654: value = 2646; break;    /* mova --> mov.  */
     case 2655: value = 2647; break;    /* mova --> mov.  */
     case 2656: value = 2648; break;    /* mova --> mov.  */
@@ -35201,15 +35197,19 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode)
     case 2094: value = 1459; break;    /* fcmlt --> fcmgt.  */
     case 1319: value = 1465; break;    /* fmov --> fcpy.  */
     case 1318: value = 1488; break;    /* fmov --> fdup.  */
+    case 1774: value = 1773; break;    /* ldr --> ldr.  */
     case 1320: value = 1804; break;    /* mov --> orr.  */
     case 2097: value = 1805; break;    /* orn --> orr.  */
     case 1324: value = 1323; break;    /* mov --> mov.  */
     case 1323: value = 1807; break;    /* mov --> orr.  */
     case 1334: value = 1808; break;    /* movs --> orrs.  */
+    case 1811: value = 1810; break;    /* pfalse --> pfalse.  */
     case 1329: value = 1871; break;    /* mov --> sel.  */
     case 1332: value = 1872; break;    /* mov --> sel.  */
+    case 1993: value = 1992; break;    /* str --> str.  */
     case 2420: value = 2422; break;    /* mov --> mova.  */
     case 2421: value = 2423; break;    /* mov --> mova.  */
+    case 2441: value = 2440; break;    /* psel --> psel.  */
     case 2646: value = 2654; break;    /* mov --> mova.  */
     case 2647: value = 2655; break;    /* mov --> mova.  */
     case 2648: value = 2656; break;    /* mov --> mova.  */

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index ae268b0778e8df544273c57cb59ad058644d6b73..77c3dc855b739a1e283d2945a9f1a73d7b18e4c1 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4690,7 +4690,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
   _SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0),
   _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0),
-  _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_PN_PN, OP2 (SVE_PNd, SVE_PNn), OP_SVE_BB, F_ALIAS | F_MISC, 0),
+  _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_PN_PN, OP2 (SVE_PNd, SVE_PNn), OP_SVE_BB, F_ALIAS | F_PSEUDO | F_MISC, 0),
   _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
   _SVE_INSN ("mov", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM_MOV), OP_SVE_VU_BHSD, F_ALIAS, 0),
   _SVE_INSN ("mov", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_ALIAS, 0),
@@ -5147,8 +5147,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSN ("ldnt1h", 0xa480e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0),
   _SVE_INSN ("ldnt1w", 0xa500c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0),
   _SVE_INSN ("ldnt1w", 0xa500e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0),
-  _SVE_INSN ("ldr", 0x85800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
-  _SVE_INSN ("ldr", 0x85800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_PNt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
+  _SVE_INSN ("ldr", 0x85800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, F_HAS_ALIAS, 0),
+  _SVE_INSN ("ldr", 0x85800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_PNt, SVE_ADDR_RI_S9xVL), {}, F_ALIAS | F_PSEUDO, 0),
   _SVE_INSN ("ldr", 0x85804000, 0xffc0e000, sve_misc, 0, OP2 (SVE_Zt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
   _SVE_INSN ("lsl", 0x04208c00, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0),
   _SVE_INSN ("lsl", 0x04209c00, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0),
@@ -5184,8 +5184,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSN ("orr", 0x25804000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0),
   _SVE_INSN ("orrs", 0x25c04000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0),
   _SVE_INSN ("orv", 0x04182000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
-  _SVE_INSN ("pfalse", 0x2518e400, 0xfffffff0, sve_misc, 0, OP1 (SVE_Pd), OP_SVE_B, 0, 0),
-  _SVE_INSN ("pfalse", 0x2518e400, 0xfffffff0, sve_misc, 0, OP1 (SVE_PNd), OP_SVE_B, 0, 0),
+  _SVE_INSN ("pfalse", 0x2518e400, 0xfffffff0, sve_misc, 0, OP1 (SVE_Pd), OP_SVE_B, F_HAS_ALIAS, 0),
+  _SVE_INSN ("pfalse", 0x2518e400, 0xfffffff0, sve_misc, 0, OP1 (SVE_PNd), OP_SVE_B, F_ALIAS | F_PSEUDO, 0),
   _SVE_INSN ("pfirst", 0x2558c000, 0xfffffe10, sve_misc, 0, OP3 (SVE_Pd, SVE_Pg4_5, SVE_Pd), OP_SVE_BUB, 0, 2),
   _SVE_INSN ("pnext", 0x2519c400, 0xff3ffe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pg4_5, SVE_Pd), OP_SVE_VUV_BHSD, 0, 2),
   _SVE_INSN ("prfb", 0x8400c000, 0xffe0e010, sve_misc, 0, OP3 (SVE_PRFOP, SVE_Pg3, SVE_ADDR_RX), {}, 0, 0),
@@ -5366,8 +5366,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSN ("stnt1h", 0xe490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HUU, F_OD(1), 0),
   _SVE_INSN ("stnt1w", 0xe5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SUU, F_OD(1), 0),
   _SVE_INSN ("stnt1w", 0xe510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SUU, F_OD(1), 0),
-  _SVE_INSN ("str", 0xe5800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
-  _SVE_INSN ("str", 0xe5800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_PNt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
+  _SVE_INSN ("str", 0xe5800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, F_HAS_ALIAS, 0),
+  _SVE_INSN ("str", 0xe5800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_PNt, SVE_ADDR_RI_S9xVL), {}, F_ALIAS | F_PSEUDO, 0),
   _SVE_INSN ("str", 0xe5804000, 0xffc0e000, sve_misc, 0, OP2 (SVE_Zt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
   _SVE_INSN ("sub", 0x04200400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
   _SVE_INSNC ("sub", 0x2521c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
@@ -5827,8 +5827,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   SVE2p1_SME_INSNC ("revd", 0x052e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0),
   SVE2p1_SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
   SVE2p1_SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
-  SVE2p1_SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
+  SVE2p1_SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, F_HAS_ALIAS, 0),
+  SVE2p1_SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, F_ALIAS | F_PSEUDO, 0),
 
   /* Added in SME2, but part of the prefetch hint space and available
      without special command-line flags.  */