]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
Daily bump.
authorGCC Administrator <gccadmin@gcc.gnu.org>
Sun, 18 May 2025 00:17:00 +0000 (00:17 +0000)
committerGCC Administrator <gccadmin@gcc.gnu.org>
Sun, 18 May 2025 00:17:00 +0000 (00:17 +0000)
gcc/ChangeLog
gcc/DATESTAMP
gcc/testsuite/ChangeLog
libgcc/ChangeLog

index 9f28a43370189d17f1ab75d3afce2c0b6d3e5960..1ef84b9c122c2334a0bfaa7e378663edf936a67c 100644 (file)
@@ -1,3 +1,49 @@
+2025-05-17  Jeff Law  <jlaw@ventanamicro.com>
+
+       * config/riscv/riscv-vect-permconst.cc (vector_permconst:process_bb):
+       Use rtvec_alloc, not gen_rtvec since we don't want/need to initialize
+       the vector.
+
+2025-05-17  Yuao Ma  <c8ef@outlook.com>
+
+       * doc/extend.texi: Mention new builtins.
+
+2025-05-17  Yuao Ma  <c8ef@outlook.com>
+
+       * builtins.def (TRIG_TYPE): New.
+       (BUILT_IN_ACOSPI): New.
+       (BUILT_IN_ACOSPIF): New.
+       (BUILT_IN_ACOSPIL): New.
+       (BUILT_IN_ASINPI): New.
+       (BUILT_IN_ASINPIF): New.
+       (BUILT_IN_ASINPIL): New.
+       (BUILT_IN_ATANPI): New.
+       (BUILT_IN_ATANPIF): New.
+       (BUILT_IN_ATANPIL): New.
+       (BUILT_IN_COSPI): New.
+       (BUILT_IN_COSPIF): New.
+       (BUILT_IN_COSPIL): New.
+       (BUILT_IN_SINPI): New.
+       (BUILT_IN_SINPIF): New.
+       (BUILT_IN_SINPIL): New.
+       (BUILT_IN_TANPI): New.
+       (BUILT_IN_TANPIF): New.
+       (BUILT_IN_TANPIL): New.
+       (TRIG2_TYPE): New.
+       (BUILT_IN_ATAN2PI): New.
+       (BUILT_IN_ATAN2PIF): New.
+       (BUILT_IN_ATAN2PIL): New.
+
+2025-05-17  Jeff Law  <jlaw@ventanamicro.com>
+
+       * config/riscv/riscv.cc (synthesize_ior_xor): Avoid writing
+       operands[0] more than once, use new pseudos instead.
+
+2025-05-17  Jin Ma  <jinma@linux.alibaba.com>
+
+       * config/riscv/riscv.cc (riscv_gpr_save_operation_p): Remove
+       break and fixbug for elt index.
+
 2025-05-16  Pengxuan Zheng  <quic_pzheng@quicinc.com>
 
        PR target/100165
index f5d7faa1be8b977595d1a591163c9c715e1f6d09..b2067301b4fb4ec5090b546dd6f91a5cf196ba81 100644 (file)
@@ -1 +1 @@
-20250517
+20250518
index f13a988695a6559aa86f21360284f9f48e2dfd73..c24ec79b3587ff3b090462fb938052a073634fa8 100644 (file)
@@ -1,3 +1,45 @@
+2025-05-17  Yuao Ma  <c8ef@outlook.com>
+
+       * gcc.dg/builtins-1.c: Builtin codegen test.
+       * gcc.dg/c23-builtins-1.c: Builtin signature test.
+
+2025-05-17  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/sat/sat_arith.h: Add more helper macros.
+       * gcc.target/riscv/sat/sat_arith_data.h: Add the test data
+       for scalar unsigned SAT_ADD.
+       * gcc.target/riscv/sat/sat_u_add-run-1-u16.c: Leverage the test
+       data from the shared header file.
+       * gcc.target/riscv/sat/sat_u_add-run-1-u32.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-1-u64.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-1-u8.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-2-u16.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-2-u32.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-2-u64.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-2-u8.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-3-u16.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-3-u32.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-3-u64.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-3-u8.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-4-u16.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-4-u32.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-4-u64.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-4-u8.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-5-u16.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-5-u32.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-5-u64.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-5-u8.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-6-u16.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-6-u32.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-6-u64.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-6-u8.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c: Ditto
+       * gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c: Ditto
+
 2025-05-16  Pengxuan Zheng  <quic_pzheng@quicinc.com>
 
        PR target/100165
index dc90779525902d1709569e0c54adf14c144119be..3f532de19ddd0e684bee95072271cad8e1d011fb 100644 (file)
@@ -1,3 +1,8 @@
+2025-05-17  Oleg Endo  <olegendo@gcc.gnu.org>
+
+       * config/sh/lib1funcs.S (ashiftrt_r4_32): Increase alignment.
+       (movemem): Force alignment of the mova intruction.
+
 2025-04-25  Thomas Schwinge  <tschwinge@baylibre.com>
 
        PR target/119853