PCI: dwc: Remove default MSI initialization for platform specific MSI chips

Platforms which populate msi_host_init() have their own MSI controller
logic. Writing to MSI control registers on platforms which do not use
Designware's MSI controller logic might have side effects.

To be safe, do not write to MSI control registers if the platform uses
its own MSI controller logic instead of Designware's MSI one.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 498422397609292de8bdfaa38a51ca5547120ef1..7e0ff7d428a9900ce121b396d68d1cd22762cdfe 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -626,17 +626,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 
        dw_pcie_setup(pci);
 
-       num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
-
-       /* Initialize IRQ Status array */
-       for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
-               pp->irq_mask[ctrl] = ~0;
-               dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
-                                       (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
-                                   4, pp->irq_mask[ctrl]);
-               dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
-                                       (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
-                                   4, ~0);
+       if (!pp->ops->msi_host_init) {
+               num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+
+               /* Initialize IRQ Status array */
+               for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
+                       pp->irq_mask[ctrl] = ~0;
+                       dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
+                                           (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
+                                           4, pp->irq_mask[ctrl]);
+                       dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
+                                           (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
+                                           4, ~0);
+               }
        }
 
        /* Setup RC BARs */