+2021-07-29 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * config/tc-aarch64.c (s_aarch64_capinit, s_aarch64_chericap):
+ Automatically align to 16 bytes.
+ * testsuite/gas/aarch64/morello-capinit-align.s: New.
+ * testsuite/gas/aarch64/morello-capinit-align.d: New.
+
2021-07-29 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (s_aarch64_capinit): Use 16 as size required.
return;
}
+ /* align to 16 bytes. */
+ do_align (4, (char *) NULL, 0, 0);
+
frag_grow (16);
fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 16, &exp, 0,
BFD_RELOC_MORELLO_CAPINIT);
md_flush_pending_output ();
#endif
+ /* align to 16 bytes. */
+ do_align (4, (char *) NULL, 0, 0);
+
frag_grow (16);
fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 16, &exp, 0,
BFD_RELOC_MORELLO_CAPINIT);
--- /dev/null
+#name: capinit and chericap automatically align
+#as: -march=armv8-a+c64
+#readelf: --relocs
+
+Relocation section '\.rela\.data' at offset 0x138 contains 4 entries:
+ Offset Info Type Sym\. Value Sym\. Name \+ Addend
+000000000010 00040000e800 R_MORELLO_CAPINIT 0000000000000000 f \+ 0
+000000000030 00040000e800 R_MORELLO_CAPINIT 0000000000000000 f \+ 0
+000000000040 00040000e800 R_MORELLO_CAPINIT 0000000000000000 f \+ 0
+000000000050 00040000e800 R_MORELLO_CAPINIT 0000000000000000 f \+ 0
--- /dev/null
+.data
+f:
+// A few capability initialisation directives with a single byte to show the
+// padding gets introduced when needed.
+.byte 0
+.capinit f
+.xword 0
+.xword 0
+.byte 0
+.chericap f
+// A few directives without any bytes in between to show no extra padding gets
+// added when not needed.
+.chericap f
+.capinit f
+.xword 0
+.xword 0