RISC-V: Add basic XAndes vendor extension support.

This patch add basic support for the following XAndes ISA extensions:

XANDESPERF
XANDESBFHCVT
XANDESVBFHCVT
XANDESVSINTLOAD
XANDESVPACKFPH
XANDESVDOT

gcc/ChangeLog:

	* config/riscv/riscv-ext.def: Include riscv-ext-andes.def.
	* config/riscv/riscv-ext.opt (riscv_xandes_subext): New variable.
	(XANDESPERF) : New mask.
	(XANDESBFHCVT): Ditto.
	(XANDESVBFHCVT): Ditto.
	(XANDESVSINTLOAD): Ditto.
	(XANDESVPACKFPH): Ditto.
	(XANDESVDOT): Ditto.
	* config/riscv/t-riscv: Add riscv-ext-andes.def.
	* doc/riscv-ext.texi: Regenerated.
	* config/riscv/riscv-ext-andes.def: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xandes/xandes-predef-1.c: New test.
	* gcc.target/riscv/xandes/xandes-predef-2.c: New test.
	* gcc.target/riscv/xandes/xandes-predef-3.c: New test.
	* gcc.target/riscv/xandes/xandes-predef-4.c: New test.
	* gcc.target/riscv/xandes/xandes-predef-5.c: New test.
	* gcc.target/riscv/xandes/xandes-predef-6.c: New test.

	Co-author: Lino Hsing-Yu Peng (linopeng@andestech.com)
	Co-author: Kai Kai-Yi Weng (kaiweng@andestech.com).

diff --git a/gcc/config/riscv/riscv-ext-andes.def b/gcc/config/riscv/riscv-ext-andes.def
new file mode 100644 (file)
index 0000000..4226e3e
--- /dev/null
+++ b/gcc/config/riscv/riscv-ext-andes.def
@@ -0,0 +1,100 @@
+/* Andes extension definition file for RISC-V.
+   Copyright (C) 2025 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.
+
+Please run `make riscv-regen` in build folder to make sure updated anything.
+
+Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def.  */
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xandesperf,
+  /* UPPERCASE_NAME */ XANDESPERF,
+  /* FULL_NAME */ "Andes performace extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+  /* FLAG_GROUP */ xandes,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xandesbfhcvt,
+  /* UPPERCASE_NAME */ XANDESBFHCVT,
+  /* FULL_NAME */ "Andes bfloat16 conversion extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+  /* FLAG_GROUP */ xandes,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xandesvbfhcvt,
+  /* UPPERCASE_NAME */ XANDESVBFHCVT,
+  /* FULL_NAME */ "Andes vector bfloat16 conversion extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+  /* FLAG_GROUP */ xandes,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xandesvsintload,
+  /* UPPERCASE_NAME */ XANDESVSINTLOAD,
+  /* FULL_NAME */ "Andes vector INT4 load extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+  /* FLAG_GROUP */ xandes,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xandesvpackfph,
+  /* UPPERCASE_NAME */ XANDESVPACKFPH,
+  /* FULL_NAME */ "Andes vector packed FP16 extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+  /* FLAG_GROUP */ xandes,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xandesvdot,
+  /* UPPERCASE_NAME */ XANDESVDOT,
+  /* FULL_NAME */ "Andes vector dot product extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{5, 0}}),
+  /* FLAG_GROUP */ xandes,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 09f18adfd45208be3b45ab7983f7adf360078e56..d162fa47efd90c079309b209648bb392833f4c02 100644 (file)
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -2083,3 +2083,4 @@ DEFINE_RISCV_EXT(
 #include "riscv-ext-thead.def"
 #include "riscv-ext-ventana.def"
 #include "riscv-ext-mips.def"
+#include "riscv-ext-andes.def"

diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index ced05d22311e72049268c59b46d5fa7b11c1f0ee..2036c16498b612d53f1b60fde48c4dfd949dab9a 100644 (file)
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -43,6 +43,9 @@ int riscv_su_subext
 TargetVariable
 int riscv_sv_subext
 
+TargetVariable
+int riscv_xandes_subext
+
 TargetVariable
 int riscv_xcv_subext
 
@@ -400,6 +403,18 @@ Mask(SVADE) Var(riscv_sv_subext)
 
 Mask(SVBARE) Var(riscv_sv_subext)
 
+Mask(XANDESPERF) Var(riscv_xandes_subext)
+
+Mask(XANDESBFHCVT) Var(riscv_xandes_subext)
+
+Mask(XANDESVBFHCVT) Var(riscv_xandes_subext)
+
+Mask(XANDESVSINTLOAD) Var(riscv_xandes_subext)
+
+Mask(XANDESVPACKFPH) Var(riscv_xandes_subext)
+
+Mask(XANDESVDOT) Var(riscv_xandes_subext)
+
 Mask(XCVALU) Var(riscv_xcv_subext)
 
 Mask(XCVBI) Var(riscv_xcv_subext)

diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index a7eaa8b0da962cc7861e2fdacdc1542b540b9e5d..a1df143f439f40861a239be840cae45470d32243 100644 (file)
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -195,7 +195,8 @@ RISCV_EXT_DEFS = \
   $(srcdir)/config/riscv/riscv-ext-sifive.def \
   $(srcdir)/config/riscv/riscv-ext-thead.def \
   $(srcdir)/config/riscv/riscv-ext-ventana.def \
-  $(srcdir)/config/riscv/riscv-ext-mips.def
+  $(srcdir)/config/riscv/riscv-ext-mips.def \
+  $(srcdir)/config/riscv/riscv-ext-andes.def
 
 $(srcdir)/config/riscv/riscv-ext.opt: $(RISCV_EXT_DEFS)
 

diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 185084edde7e5021d09015af7fbb050bd6e5f5f2..13056e73bad95e0687ef2c2c158d303e57044e79 100644 (file)
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -722,4 +722,28 @@
 @tab 1.0
 @tab Mips Prefetch extension
 
+@item xandesperf
+@tab 5.0
+@tab Andes performace extension
+
+@item xandesbfhcvt
+@tab 5.0
+@tab Andes bfloat16 conversion extension
+
+@item xandesvbfhcvt
+@tab 5.0
+@tab Andes vector bfloat16 conversion extension
+
+@item xandesvsintload
+@tab 5.0
+@tab Andes vector INT4 load extension
+
+@item xandesvpackfph
+@tab 5.0
+@tab Andes vector packed FP16 extension
+
+@item xandesvdot
+@tab 5.0
+@tab Andes vector dot product extension
+
 @end multitable

diff --git a/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-1.c b/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-1.c
new file mode 100644 (file)
index 0000000..2439131
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xandesperf -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xandesperf)
+#error "__riscv_xandesperf"
+#endif
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-2.c b/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-2.c
new file mode 100644 (file)
index 0000000..0e2e2d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xandesbfhcvt -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xandesbfhcvt)
+#error "__riscv_xandesbfhcvt"
+#endif
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-3.c b/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-3.c
new file mode 100644 (file)
index 0000000..62f4c28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xandesvbfhcvt -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xandesvbfhcvt)
+#error "__riscv_xandesvbfhcvt"
+#endif
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-4.c b/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-4.c
new file mode 100644 (file)
index 0000000..3074b5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xandesvsintload -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xandesvsintload)
+#error "__riscv_xandesvsintload"
+#endif
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-5.c b/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-5.c
new file mode 100644 (file)
index 0000000..de5fe31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xandesvpackfph -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xandesvpackfph)
+#error "__riscv_xandesvpackfph"
+#endif
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-6.c b/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-6.c
new file mode 100644 (file)
index 0000000..728d541
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xandes/xandes-predef-6.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xandesvdot -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xandesvdot)
+#error "__riscv_xandesvdot"
+#endif
+
+  return 0;
+}