clk: versal: Enable only GATE type clocks

Clocks should be enabled or disabled only if they are of GATE type
clocks. If they are not of GATE type clocks, don't touch them.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>

diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 86d35bfdce3f894e7c72919e2a667969df9d8a7e..3134ca5a52693063c3f01548e2b0a175ef5e1bb8 100644 (file)
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk)
 
        clk_id = priv->clk[clk->id].clk_id;
 
-       return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+       if (versal_clock_gate(clk_id))
+               return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+
+       return 0;
 }
 
 static struct clk_ops versal_clk_ops = {