msm:disp:dpu1: Fix core clk rate in display driver

Fix max core clk rate during dt parsing in display driver.

Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
index ec1437b0ef75b8b3fccc3739c7e90672525f8876..078afc5f58820e81b2f8994f10ff6538719a033a 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
@@ -175,6 +175,7 @@ int msm_dss_parse_clock(struct platform_device *pdev,
                        continue;
                mp->clk_config[i].rate = rate;
                mp->clk_config[i].type = DSS_CLK_PCLK;
+               mp->clk_config[i].max_rate = rate;
        }
 
        mp->num_clk = num_clk;