mn10300.md (andsi3, [...]): Make them set_zn.

* config/mn10300/mn10300.md (andsi3, iorsi3, xorsi3,
one_complsi2, bit-clear, bit-set, iorqi3): Make them set_zn.

From-SVN: r71499

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7b606eccda8dc81d81dc8dc81ec2a4df00f294c2..2ac36e9d44722bf424a7aae3f36bc85b810c795f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2003-09-17  Alexandre Oliva  <aoliva@redhat.com>
+
+       * config/mn10300/mn10300.md (andsi3, iorsi3, xorsi3,
+       one_complsi2, bit-clear, bit-set, iorqi3): Make them set_zn.
+
 2003-09-17  Richard Henderson  <rth@redhat.com>
 
        * tree-optimize.c (tree_rest_of_compilation): Save and restore

diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md
index 27a40ef37204c4564539de0302c0cdb0d64cd1fe..46a8ff125cdcd0c7f559780cf16e1ed59502c0fb 100644 (file)
--- a/gcc/config/mn10300/mn10300.md
+++ b/gcc/config/mn10300/mn10300.md
@@ -1224,7 +1224,7 @@
     return \"and %1,%0\";
   return \"and %2,%0\";
 }"
-  [(set_attr "cc" "none_0hit,set_znv,set_znv")])
+  [(set_attr "cc" "none_0hit,set_zn,set_zn")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx,dx")
@@ -1255,7 +1255,7 @@
     return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
   return \"and %2,%0\";
 }"
-  [(set_attr "cc" "none_0hit,set_znv")])
+  [(set_attr "cc" "none_0hit,set_zn")])
 
 ;; ----------------------------------------------------------------------
 ;; OR INSTRUCTIONS
@@ -1291,7 +1291,7 @@
     return \"or %1,%0\";
   return \"or %2,%0\";
 }"
-  [(set_attr "cc" "set_znv")])
+  [(set_attr "cc" "set_zn")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx")
@@ -1299,7 +1299,7 @@
                (match_operand:SI 2 "nonmemory_operand" "dxi")))]
   ""
   "or %2,%0"
-  [(set_attr "cc" "set_znv")])
+  [(set_attr "cc" "set_zn")])
 
 ;; ----------------------------------------------------------------------
 ;; XOR INSTRUCTIONS
@@ -1335,7 +1335,7 @@
     return \"xor %1,%0\";
   return \"xor %2,%0\";
 }"
-  [(set_attr "cc" "set_znv")])
+  [(set_attr "cc" "set_zn")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx")
@@ -1343,7 +1343,7 @@
                (match_operand:SI 2 "nonmemory_operand" "dxi")))]
   ""
   "xor %2,%0"
-  [(set_attr "cc" "set_znv")])
+  [(set_attr "cc" "set_zn")])
 
 ;; ----------------------------------------------------------------------
 ;; NOT INSTRUCTIONS
@@ -1360,14 +1360,14 @@
        (not:SI (match_operand:SI 1 "register_operand" "0,0")))]
   "TARGET_AM33"
   "not %0"
-  [(set_attr "cc" "set_znv")])
+  [(set_attr "cc" "set_zn")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx")
        (not:SI (match_operand:SI 1 "register_operand" "0")))]
   ""
   "not %0"
-  [(set_attr "cc" "set_znv")])
+  [(set_attr "cc" "set_zn")])
 \f
 ;; -----------------------------------------------------------------
 ;; BIT FIELDS
@@ -1404,7 +1404,7 @@
   "@
   bclr %N1,%A0
   and %1,%0"
-  [(set_attr "cc" "clobber,set_znv")])
+  [(set_attr "cc" "clobber,set_zn")])
 
 (define_insn ""
   [(set (match_operand:QI 0 "memory_operand" "=R,T")
@@ -1426,7 +1426,7 @@
   "@
   bset %U1,%A0
   or %1,%0"
-  [(set_attr "cc" "clobber,set_znv")])
+  [(set_attr "cc" "clobber,set_zn")])
 
 (define_expand "iorqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -1449,7 +1449,7 @@
   bset %U2,%A0
   bset %2,%0
   or %2,%0"
-  [(set_attr "cc" "clobber,clobber,set_znv")])
+  [(set_attr "cc" "clobber,clobber,set_zn")])
 
 (define_insn ""
   [(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,d")
@@ -1464,7 +1464,7 @@
   bset %U2,%A0
   bset %2,%0
   or %2,%0"
-  [(set_attr "cc" "clobber,clobber,set_znv")])
+  [(set_attr "cc" "clobber,clobber,set_zn")])
 
 (define_insn ""
   [(set (cc0)