+++ /dev/null
-From d9cd70b32d438acfe63a77de50676970903e08e7 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Fri, 16 Nov 2018 15:31:10 +0530
-Subject: ARM: dts: exynos: Add all CPUs in cooling maps
-
-From: Viresh Kumar <viresh.kumar@linaro.org>
-
-[ Upstream commit 670734f5581023a2e695e82ea662e4d603fd3e8a ]
-
-Each CPU can (and does) participate in cooling down the system but the
-DT only captures a handful of them, normally CPU0, in the cooling maps.
-Things work by chance currently as under normal circumstances its the
-first CPU of each cluster which is used by the operating systems to
-probe the cooling devices. But as soon as this CPU ordering changes and
-any other CPU is used to bring up the cooling device, we will start
-seeing failures.
-
-Also the DT is rather incomplete when we list only one CPU in the
-cooling maps, as the hardware doesn't have any such limitations.
-
-Update cooling maps to include all devices affected by individual trip
-points.
-
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
-Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
-Stable-dep-of: 33e2c595e2e4 ("ARM: dts: exynos: correct TMU phandle in Exynos5250")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm/boot/dts/exynos3250-artik5.dtsi | 6 +-
- arch/arm/boot/dts/exynos3250-monk.dts | 6 +-
- arch/arm/boot/dts/exynos3250-rinato.dts | 6 +-
- arch/arm/boot/dts/exynos4210-trats.dts | 4 +-
- arch/arm/boot/dts/exynos4210.dtsi | 2 +-
- .../boot/dts/exynos4412-itop-scp-core.dtsi | 8 +-
- arch/arm/boot/dts/exynos4412-midas.dtsi | 8 +-
- .../boot/dts/exynos4412-odroid-common.dtsi | 8 +-
- arch/arm/boot/dts/exynos4412-odroidu3.dts | 18 ++-
- arch/arm/boot/dts/exynos4412.dtsi | 6 +-
- arch/arm/boot/dts/exynos5250.dtsi | 7 +-
- arch/arm/boot/dts/exynos5422-odroidhc1.dts | 106 +++++++++++-------
- .../boot/dts/exynos5422-odroidxu3-common.dtsi | 106 +++++++++++-------
- 13 files changed, 178 insertions(+), 113 deletions(-)
-
-diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
-index 6e30db644c83a..86aa0956b2d3b 100644
---- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
-+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
-@@ -36,11 +36,13 @@
- cooling-maps {
- map0 {
- /* Corresponds to 500MHz */
-- cooling-device = <&cpu0 5 5>;
-+ cooling-device = <&cpu0 5 5>,
-+ <&cpu1 5 5>;
- };
- map1 {
- /* Corresponds to 200MHz */
-- cooling-device = <&cpu0 8 8>;
-+ cooling-device = <&cpu0 8 8>,
-+ <&cpu1 8 8>;
- };
- };
- };
-diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
-index d343dc13ceecd..c9b6fb65d6861 100644
---- a/arch/arm/boot/dts/exynos3250-monk.dts
-+++ b/arch/arm/boot/dts/exynos3250-monk.dts
-@@ -121,11 +121,13 @@
- cooling-maps {
- map0 {
- /* Correspond to 500MHz at freq_table */
-- cooling-device = <&cpu0 5 5>;
-+ cooling-device = <&cpu0 5 5>,
-+ <&cpu1 5 5>;
- };
- map1 {
- /* Correspond to 200MHz at freq_table */
-- cooling-device = <&cpu0 8 8>;
-+ cooling-device = <&cpu0 8 8>,
-+ <&cpu1 8 8>;
- };
- };
- };
-diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
-index e398604b2ce0f..4eb5f79b1c3b2 100644
---- a/arch/arm/boot/dts/exynos3250-rinato.dts
-+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
-@@ -116,11 +116,13 @@
- cooling-maps {
- map0 {
- /* Corresponds to 500MHz */
-- cooling-device = <&cpu0 5 5>;
-+ cooling-device = <&cpu0 5 5>,
-+ <&cpu1 5 5>;
- };
- map1 {
- /* Corresponds to 200MHz */
-- cooling-device = <&cpu0 8 8>;
-+ cooling-device = <&cpu0 8 8>,
-+ <&cpu1 8 8>;
- };
- };
- };
-diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
-index 6f1d76cb79515..230969556e1ce 100644
---- a/arch/arm/boot/dts/exynos4210-trats.dts
-+++ b/arch/arm/boot/dts/exynos4210-trats.dts
-@@ -138,11 +138,11 @@
- cooling-maps {
- map0 {
- /* Corresponds to 800MHz at freq_table */
-- cooling-device = <&cpu0 2 2>;
-+ cooling-device = <&cpu0 2 2>, <&cpu1 2 2>;
- };
- map1 {
- /* Corresponds to 200MHz at freq_table */
-- cooling-device = <&cpu0 4 4>;
-+ cooling-device = <&cpu0 4 4>, <&cpu1 4 4>;
- };
- };
- };
-diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
-index 24bea84034af2..b7b6edbc0499e 100644
---- a/arch/arm/boot/dts/exynos4210.dtsi
-+++ b/arch/arm/boot/dts/exynos4210.dtsi
-@@ -51,7 +51,7 @@
- #cooling-cells = <2>; /* min followed by max */
- };
-
-- cpu@901 {
-+ cpu1: cpu@901 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0x901>;
-diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
-index ab7affab7f1c0..4ca05599ee2ac 100644
---- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
-+++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
-@@ -45,11 +45,15 @@
- cooling-maps {
- map0 {
- /* Corresponds to 800MHz at freq_table */
-- cooling-device = <&cpu0 7 7>;
-+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
-+ <&cpu2 7 7>, <&cpu3 7 7>;
- };
- map1 {
- /* Corresponds to 200MHz at freq_table */
-- cooling-device = <&cpu0 13 13>;
-+ cooling-device = <&cpu0 13 13>,
-+ <&cpu1 13 13>,
-+ <&cpu2 13 13>,
-+ <&cpu3 13 13>;
- };
- };
- };
-diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi
-index 93c8918e599bd..047240a32097a 100644
---- a/arch/arm/boot/dts/exynos4412-midas.dtsi
-+++ b/arch/arm/boot/dts/exynos4412-midas.dtsi
-@@ -267,11 +267,15 @@
- cooling-maps {
- map0 {
- /* Corresponds to 800MHz at freq_table */
-- cooling-device = <&cpu0 7 7>;
-+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
-+ <&cpu2 7 7>, <&cpu3 7 7>;
- };
- map1 {
- /* Corresponds to 200MHz at freq_table */
-- cooling-device = <&cpu0 13 13>;
-+ cooling-device = <&cpu0 13 13>,
-+ <&cpu1 13 13>,
-+ <&cpu2 13 13>,
-+ <&cpu3 13 13>;
- };
- };
- };
-diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
-index dbca8eeefae13..e269818668bb1 100644
---- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
-+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
-@@ -72,11 +72,15 @@
- cooling-maps {
- cooling_map0: map0 {
- /* Corresponds to 800MHz at freq_table */
-- cooling-device = <&cpu0 7 7>;
-+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
-+ <&cpu2 7 7>, <&cpu3 7 7>;
- };
- cooling_map1: map1 {
- /* Corresponds to 200MHz at freq_table */
-- cooling-device = <&cpu0 13 13>;
-+ cooling-device = <&cpu0 13 13>,
-+ <&cpu1 13 13>,
-+ <&cpu2 13 13>,
-+ <&cpu3 13 13>;
- };
- };
- };
-diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts
-index 459919b65df81..2bdf899df4366 100644
---- a/arch/arm/boot/dts/exynos4412-odroidu3.dts
-+++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts
-@@ -45,24 +45,22 @@
- cooling-maps {
- map0 {
- trip = <&cpu_alert1>;
-- cooling-device = <&cpu0 9 9>;
-+ cooling-device = <&cpu0 9 9>, <&cpu1 9 9>,
-+ <&cpu2 9 9>, <&cpu3 9 9>,
-+ <&fan0 1 2>;
- };
- map1 {
- trip = <&cpu_alert2>;
-- cooling-device = <&cpu0 15 15>;
-+ cooling-device = <&cpu0 15 15>,
-+ <&cpu1 15 15>,
-+ <&cpu2 15 15>,
-+ <&cpu3 15 15>,
-+ <&fan0 2 3>;
- };
- map2 {
- trip = <&cpu_alert0>;
- cooling-device = <&fan0 0 1>;
- };
-- map3 {
-- trip = <&cpu_alert1>;
-- cooling-device = <&fan0 1 2>;
-- };
-- map4 {
-- trip = <&cpu_alert2>;
-- cooling-device = <&fan0 2 3>;
-- };
- };
- };
- };
-diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
-index 51f72f0327e52..cd04bb4aea5f8 100644
---- a/arch/arm/boot/dts/exynos4412.dtsi
-+++ b/arch/arm/boot/dts/exynos4412.dtsi
-@@ -45,7 +45,7 @@
- #cooling-cells = <2>; /* min followed by max */
- };
-
-- cpu@a01 {
-+ cpu1: cpu@a01 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xA01>;
-@@ -55,7 +55,7 @@
- #cooling-cells = <2>; /* min followed by max */
- };
-
-- cpu@a02 {
-+ cpu2: cpu@a02 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xA02>;
-@@ -65,7 +65,7 @@
- #cooling-cells = <2>; /* min followed by max */
- };
-
-- cpu@a03 {
-+ cpu3: cpu@a03 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0xA03>;
-diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
-index b85527faa6ea4..e6b1a8a9b832c 100644
---- a/arch/arm/boot/dts/exynos5250.dtsi
-+++ b/arch/arm/boot/dts/exynos5250.dtsi
-@@ -59,7 +59,7 @@
- operating-points-v2 = <&cpu0_opp_table>;
- #cooling-cells = <2>; /* min followed by max */
- };
-- cpu@1 {
-+ cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <1>;
-@@ -1066,11 +1066,12 @@
- cooling-maps {
- map0 {
- /* Corresponds to 800MHz at freq_table */
-- cooling-device = <&cpu0 9 9>;
-+ cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
- };
- map1 {
- /* Corresponds to 200MHz at freq_table */
-- cooling-device = <&cpu0 15 15>;
-+ cooling-device = <&cpu0 15 15>,
-+ <&cpu1 15 15>;
- };
- };
- };
-diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
-index abc6fb7d27259..fce5a4579693e 100644
---- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts
-+++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
-@@ -56,24 +56,30 @@
- */
- map0 {
- trip = <&cpu0_alert0>;
-- cooling-device = <&cpu0 0 2>;
-- };
-- map1 {
-- trip = <&cpu0_alert0>;
-- cooling-device = <&cpu4 0 2>;
-+ cooling-device = <&cpu0 0 2>,
-+ <&cpu1 0 2>,
-+ <&cpu2 0 2>,
-+ <&cpu3 0 2>,
-+ <&cpu4 0 2>,
-+ <&cpu5 0 2>,
-+ <&cpu6 0 2>,
-+ <&cpu7 0 2>;
- };
- /*
- * When reaching cpu0_alert1, reduce CPU
- * further, down to 600 MHz (12 steps for big,
- * 7 steps for LITTLE).
- */
-- map2 {
-- trip = <&cpu0_alert1>;
-- cooling-device = <&cpu0 3 7>;
-- };
-- map3 {
-+ map1 {
- trip = <&cpu0_alert1>;
-- cooling-device = <&cpu4 3 12>;
-+ cooling-device = <&cpu0 3 7>,
-+ <&cpu1 3 7>,
-+ <&cpu2 3 7>,
-+ <&cpu3 3 7>,
-+ <&cpu4 3 12>,
-+ <&cpu5 3 12>,
-+ <&cpu6 3 12>,
-+ <&cpu7 3 12>;
- };
- };
- };
-@@ -99,19 +105,25 @@
- cooling-maps {
- map0 {
- trip = <&cpu1_alert0>;
-- cooling-device = <&cpu0 0 2>;
-+ cooling-device = <&cpu0 0 2>,
-+ <&cpu1 0 2>,
-+ <&cpu2 0 2>,
-+ <&cpu3 0 2>,
-+ <&cpu4 0 2>,
-+ <&cpu5 0 2>,
-+ <&cpu6 0 2>,
-+ <&cpu7 0 2>;
- };
- map1 {
-- trip = <&cpu1_alert0>;
-- cooling-device = <&cpu4 0 2>;
-- };
-- map2 {
-- trip = <&cpu1_alert1>;
-- cooling-device = <&cpu0 3 7>;
-- };
-- map3 {
- trip = <&cpu1_alert1>;
-- cooling-device = <&cpu4 3 12>;
-+ cooling-device = <&cpu0 3 7>,
-+ <&cpu1 3 7>,
-+ <&cpu2 3 7>,
-+ <&cpu3 3 7>,
-+ <&cpu4 3 12>,
-+ <&cpu5 3 12>,
-+ <&cpu6 3 12>,
-+ <&cpu7 3 12>;
- };
- };
- };
-@@ -137,19 +149,25 @@
- cooling-maps {
- map0 {
- trip = <&cpu2_alert0>;
-- cooling-device = <&cpu0 0 2>;
-+ cooling-device = <&cpu0 0 2>,
-+ <&cpu1 0 2>,
-+ <&cpu2 0 2>,
-+ <&cpu3 0 2>,
-+ <&cpu4 0 2>,
-+ <&cpu5 0 2>,
-+ <&cpu6 0 2>,
-+ <&cpu7 0 2>;
- };
- map1 {
-- trip = <&cpu2_alert0>;
-- cooling-device = <&cpu4 0 2>;
-- };
-- map2 {
-- trip = <&cpu2_alert1>;
-- cooling-device = <&cpu0 3 7>;
-- };
-- map3 {
- trip = <&cpu2_alert1>;
-- cooling-device = <&cpu4 3 12>;
-+ cooling-device = <&cpu0 3 7>,
-+ <&cpu1 3 7>,
-+ <&cpu2 3 7>,
-+ <&cpu3 3 7>,
-+ <&cpu4 3 12>,
-+ <&cpu5 3 12>,
-+ <&cpu6 3 12>,
-+ <&cpu7 3 12>;
- };
- };
- };
-@@ -175,19 +193,25 @@
- cooling-maps {
- map0 {
- trip = <&cpu3_alert0>;
-- cooling-device = <&cpu0 0 2>;
-+ cooling-device = <&cpu0 0 2>,
-+ <&cpu1 0 2>,
-+ <&cpu2 0 2>,
-+ <&cpu3 0 2>,
-+ <&cpu4 0 2>,
-+ <&cpu5 0 2>,
-+ <&cpu6 0 2>,
-+ <&cpu7 0 2>;
- };
- map1 {
-- trip = <&cpu3_alert0>;
-- cooling-device = <&cpu4 0 2>;
-- };
-- map2 {
-- trip = <&cpu3_alert1>;
-- cooling-device = <&cpu0 3 7>;
-- };
-- map3 {
- trip = <&cpu3_alert1>;
-- cooling-device = <&cpu4 3 12>;
-+ cooling-device = <&cpu0 3 7>,
-+ <&cpu1 3 7>,
-+ <&cpu2 3 7>,
-+ <&cpu3 3 7>,
-+ <&cpu4 3 12>,
-+ <&cpu5 3 12>,
-+ <&cpu6 3 12>,
-+ <&cpu7 3 12>;
- };
- };
- };
-diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
-index 96e281c0a118a..264651141d688 100644
---- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
-+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
-@@ -113,24 +113,30 @@
- */
- map3 {
- trip = <&cpu0_alert3>;
-- cooling-device = <&cpu0 0 2>;
-- };
-- map4 {
-- trip = <&cpu0_alert3>;
-- cooling-device = <&cpu4 0 2>;
-+ cooling-device = <&cpu0 0 2>,
-+ <&cpu1 0 2>,
-+ <&cpu2 0 2>,
-+ <&cpu3 0 2>,
-+ <&cpu4 0 2>,
-+ <&cpu5 0 2>,
-+ <&cpu6 0 2>,
-+ <&cpu7 0 2>;
- };
- /*
- * When reaching cpu0_alert4, reduce CPU
- * further, down to 600 MHz (12 steps for big,
- * 7 steps for LITTLE).
- */
-- map5 {
-- trip = <&cpu0_alert4>;
-- cooling-device = <&cpu0 3 7>;
-- };
-- map6 {
-+ map4 {
- trip = <&cpu0_alert4>;
-- cooling-device = <&cpu4 3 12>;
-+ cooling-device = <&cpu0 3 7>,
-+ <&cpu1 3 7>,
-+ <&cpu2 3 7>,
-+ <&cpu3 3 7>,
-+ <&cpu4 3 12>,
-+ <&cpu5 3 12>,
-+ <&cpu6 3 12>,
-+ <&cpu7 3 12>;
- };
- };
- };
-@@ -185,19 +191,25 @@
- };
- map3 {
- trip = <&cpu1_alert3>;
-- cooling-device = <&cpu0 0 2>;
-+ cooling-device = <&cpu0 0 2>,
-+ <&cpu1 0 2>,
-+ <&cpu2 0 2>,
-+ <&cpu3 0 2>,
-+ <&cpu4 0 2>,
-+ <&cpu5 0 2>,
-+ <&cpu6 0 2>,
-+ <&cpu7 0 2>;
- };
- map4 {
-- trip = <&cpu1_alert3>;
-- cooling-device = <&cpu4 0 2>;
-- };
-- map5 {
-- trip = <&cpu1_alert4>;
-- cooling-device = <&cpu0 3 7>;
-- };
-- map6 {
- trip = <&cpu1_alert4>;
-- cooling-device = <&cpu4 3 12>;
-+ cooling-device = <&cpu0 3 7>,
-+ <&cpu1 3 7>,
-+ <&cpu2 3 7>,
-+ <&cpu3 3 7>,
-+ <&cpu4 3 12>,
-+ <&cpu5 3 12>,
-+ <&cpu6 3 12>,
-+ <&cpu7 3 12>;
- };
- };
- };
-@@ -252,19 +264,25 @@
- };
- map3 {
- trip = <&cpu2_alert3>;
-- cooling-device = <&cpu0 0 2>;
-+ cooling-device = <&cpu0 0 2>,
-+ <&cpu1 0 2>,
-+ <&cpu2 0 2>,
-+ <&cpu3 0 2>,
-+ <&cpu4 0 2>,
-+ <&cpu5 0 2>,
-+ <&cpu6 0 2>,
-+ <&cpu7 0 2>;
- };
- map4 {
-- trip = <&cpu2_alert3>;
-- cooling-device = <&cpu4 0 2>;
-- };
-- map5 {
-- trip = <&cpu2_alert4>;
-- cooling-device = <&cpu0 3 7>;
-- };
-- map6 {
- trip = <&cpu2_alert4>;
-- cooling-device = <&cpu4 3 12>;
-+ cooling-device = <&cpu0 3 7>,
-+ <&cpu1 3 7>,
-+ <&cpu2 3 7>,
-+ <&cpu3 3 7>,
-+ <&cpu4 3 12>,
-+ <&cpu5 3 12>,
-+ <&cpu6 3 12>,
-+ <&cpu7 3 12>;
- };
- };
- };
-@@ -319,19 +337,25 @@
- };
- map3 {
- trip = <&cpu3_alert3>;
-- cooling-device = <&cpu0 0 2>;
-+ cooling-device = <&cpu0 0 2>,
-+ <&cpu1 0 2>,
-+ <&cpu2 0 2>,
-+ <&cpu3 0 2>,
-+ <&cpu4 0 2>,
-+ <&cpu5 0 2>,
-+ <&cpu6 0 2>,
-+ <&cpu7 0 2>;
- };
- map4 {
-- trip = <&cpu3_alert3>;
-- cooling-device = <&cpu4 0 2>;
-- };
-- map5 {
-- trip = <&cpu3_alert4>;
-- cooling-device = <&cpu0 3 7>;
-- };
-- map6 {
- trip = <&cpu3_alert4>;
-- cooling-device = <&cpu4 3 12>;
-+ cooling-device = <&cpu0 3 7>,
-+ <&cpu1 3 7>,
-+ <&cpu2 3 7>,
-+ <&cpu3 3 7>,
-+ <&cpu4 3 12>,
-+ <&cpu5 3 12>,
-+ <&cpu6 3 12>,
-+ <&cpu7 3 12>;
- };
- };
- };
---
-2.39.2
-
+++ /dev/null
-From 7fd595cc9228be7aa82860d3122dc81e890481e2 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 9 Feb 2023 11:58:37 +0100
-Subject: ARM: dts: exynos: correct TMU phandle in Exynos4210
-
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-
-[ Upstream commit 408ab6786dbf6dd696488054c9559681112ef994 ]
-
-TMU node uses 0 as thermal-sensor-cells, thus thermal zone referencing
-it must not have an argument to phandle. Since thermal-sensors property is
-already defined in included exynos4-cpu-thermal.dtsi, drop it from
-exynos4210.dtsi to fix the error and remoev redundancy.
-
-Fixes: 9843a2236003 ("ARM: dts: Provide dt bindings identical for Exynos TMU")
-Cc: <stable@vger.kernel.org>
-Link: https://lore.kernel.org/r/20230209105841.779596-2-krzysztof.kozlowski@linaro.org
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm/boot/dts/exynos4210.dtsi | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
-index 2ec6c01550564..24bea84034af2 100644
---- a/arch/arm/boot/dts/exynos4210.dtsi
-+++ b/arch/arm/boot/dts/exynos4210.dtsi
-@@ -387,7 +387,6 @@
- &cpu_thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-- thermal-sensors = <&tmu 0>;
- };
-
- &gic {
---
-2.39.2
-
+++ /dev/null
-From 0ffc2afdbdd2b023b1395a53f5ef720f53bec6cf Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 9 Feb 2023 11:58:38 +0100
-Subject: ARM: dts: exynos: correct TMU phandle in Exynos5250
-
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-
-[ Upstream commit 33e2c595e2e4016991ead44933a29d1ef93d5f26 ]
-
-TMU node uses 0 as thermal-sensor-cells, thus thermal zone referencing
-it must not have an argument to phandle.
-
-Cc: <stable@vger.kernel.org>
-Fixes: 9843a2236003 ("ARM: dts: Provide dt bindings identical for Exynos TMU")
-Link: https://lore.kernel.org/r/20230209105841.779596-3-krzysztof.kozlowski@linaro.org
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm/boot/dts/exynos5250.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
-index 1883b8c2cd7b9..c6b0e6413c683 100644
---- a/arch/arm/boot/dts/exynos5250.dtsi
-+++ b/arch/arm/boot/dts/exynos5250.dtsi
-@@ -1061,7 +1061,7 @@
- &cpu_thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-- thermal-sensors = <&tmu 0>;
-+ thermal-sensors = <&tmu>;
-
- cooling-maps {
- map0 {
---
-2.39.2
-
+++ /dev/null
-From 4855ea12ed452e3e87aa8fcb6c9e22f4c35c0eea Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 9 Feb 2023 11:58:40 +0100
-Subject: ARM: dts: exynos: correct TMU phandle in Odroid HC1
-
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-
-[ Upstream commit 2e3d0e20d8456f876607a8af61fdb83dfbf98cb6 ]
-
-TMU node uses 0 as thermal-sensor-cells, thus thermal zone referencing
-it must not have an argument to phandle. This was not critical before,
-but since rework of thermal Devicetree initialization in the
-commit 3fd6d6e2b4e8 ("thermal/of: Rework the thermal device tree
-initialization"), this leads to errors registering thermal zones other
-than first one:
-
- thermal_sys: cpu0-thermal: Failed to read thermal-sensors cells: -2
- thermal_sys: Failed to find thermal zone for tmu id=0
- exynos-tmu 10064000.tmu: Failed to register sensor: -2
- exynos-tmu: probe of 10064000.tmu failed with error -2
-
-Fixes: 1ac49427b566 ("ARM: dts: exynos: Add support for Hardkernel's Odroid HC1 board")
-Cc: <stable@vger.kernel.org>
-Link: https://lore.kernel.org/r/20230209105841.779596-5-krzysztof.kozlowski@linaro.org
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm/boot/dts/exynos5422-odroidhc1.dts | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
-index 3235d7a27e042..b423cea4c0e99 100644
---- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts
-+++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
-@@ -29,7 +29,7 @@
-
- thermal-zones {
- cpu0_thermal: cpu0-thermal {
-- thermal-sensors = <&tmu_cpu0 0>;
-+ thermal-sensors = <&tmu_cpu0>;
- trips {
- cpu0_alert0: cpu-alert-0 {
- temperature = <70000>; /* millicelsius */
-@@ -84,7 +84,7 @@
- };
- };
- cpu1_thermal: cpu1-thermal {
-- thermal-sensors = <&tmu_cpu1 0>;
-+ thermal-sensors = <&tmu_cpu1>;
- trips {
- cpu1_alert0: cpu-alert-0 {
- temperature = <70000>;
-@@ -128,7 +128,7 @@
- };
- };
- cpu2_thermal: cpu2-thermal {
-- thermal-sensors = <&tmu_cpu2 0>;
-+ thermal-sensors = <&tmu_cpu2>;
- trips {
- cpu2_alert0: cpu-alert-0 {
- temperature = <70000>;
-@@ -172,7 +172,7 @@
- };
- };
- cpu3_thermal: cpu3-thermal {
-- thermal-sensors = <&tmu_cpu3 0>;
-+ thermal-sensors = <&tmu_cpu3>;
- trips {
- cpu3_alert0: cpu-alert-0 {
- temperature = <70000>;
-@@ -216,7 +216,7 @@
- };
- };
- gpu_thermal: gpu-thermal {
-- thermal-sensors = <&tmu_gpu 0>;
-+ thermal-sensors = <&tmu_gpu>;
- trips {
- gpu_alert0: gpu-alert-0 {
- temperature = <70000>;
---
-2.39.2
-
+++ /dev/null
-From 8b5793dfb041672ca78d92341260463a2d4fb0db Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 9 Feb 2023 11:58:41 +0100
-Subject: ARM: dts: exynos: correct TMU phandle in Odroid XU3 family
-
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-
-[ Upstream commit a3583e92d188ec6c58c7f603ac5e72dd8a11c21a ]
-
-TMU node uses 0 as thermal-sensor-cells, thus thermal zone referencing
-it must not have an argument to phandle. This was not critical before,
-but since rework of thermal Devicetree initialization in the
-commit 3fd6d6e2b4e8 ("thermal/of: Rework the thermal device tree
-initialization"), this leads to errors registering thermal zones other
-than first one:
-
- thermal_sys: cpu0-thermal: Failed to read thermal-sensors cells: -2
- thermal_sys: Failed to find thermal zone for tmu id=0
- exynos-tmu 10064000.tmu: Failed to register sensor: -2
- exynos-tmu: probe of 10064000.tmu failed with error -2
-
-Fixes: f1722d7dd8b8 ("ARM: dts: Define default thermal-zones for exynos5422")
-Cc: <stable@vger.kernel.org>
-Link: https://lore.kernel.org/r/20230209105841.779596-6-krzysztof.kozlowski@linaro.org
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
-index 402d69877fd97..86f64db15a3dd 100644
---- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
-+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
-@@ -52,7 +52,7 @@
-
- thermal-zones {
- cpu0_thermal: cpu0-thermal {
-- thermal-sensors = <&tmu_cpu0 0>;
-+ thermal-sensors = <&tmu_cpu0>;
- polling-delay-passive = <250>;
- polling-delay = <0>;
- trips {
-@@ -141,7 +141,7 @@
- };
- };
- cpu1_thermal: cpu1-thermal {
-- thermal-sensors = <&tmu_cpu1 0>;
-+ thermal-sensors = <&tmu_cpu1>;
- polling-delay-passive = <250>;
- polling-delay = <0>;
- trips {
-@@ -214,7 +214,7 @@
- };
- };
- cpu2_thermal: cpu2-thermal {
-- thermal-sensors = <&tmu_cpu2 0>;
-+ thermal-sensors = <&tmu_cpu2>;
- polling-delay-passive = <250>;
- polling-delay = <0>;
- trips {
-@@ -287,7 +287,7 @@
- };
- };
- cpu3_thermal: cpu3-thermal {
-- thermal-sensors = <&tmu_cpu3 0>;
-+ thermal-sensors = <&tmu_cpu3>;
- polling-delay-passive = <250>;
- polling-delay = <0>;
- trips {
-@@ -360,7 +360,7 @@
- };
- };
- gpu_thermal: gpu-thermal {
-- thermal-sensors = <&tmu_gpu 0>;
-+ thermal-sensors = <&tmu_gpu>;
- polling-delay-passive = <250>;
- polling-delay = <0>;
- trips {
---
-2.39.2
-
+++ /dev/null
-From a9791b54725cf8c5054b41421193012efb76ac99 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 18 Jun 2019 21:07:32 +0200
-Subject: ARM: dts: exynos: Fix language typo and indentation
-
-From: Krzysztof Kozlowski <krzk@kernel.org>
-
-[ Upstream commit c31b11c3eb4d41df4038b0441b15f3f0b2fca5d4 ]
-
-Correct language typo and wrong indentation.
-
-Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
-Stable-dep-of: 408ab6786dbf ("ARM: dts: exynos: correct TMU phandle in Exynos4210")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm/boot/dts/exynos4210.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
-index b6091c27f155d..0ed9ef75075bc 100644
---- a/arch/arm/boot/dts/exynos4210.dtsi
-+++ b/arch/arm/boot/dts/exynos4210.dtsi
-@@ -8,7 +8,7 @@
- * www.linaro.org
- *
- * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
-- * based board files can include this file and provide values for board specfic
-+ * based board files can include this file and provide values for board specific
- * bindings.
- *
- * Note: This file does not include device nodes for all the controllers in
-@@ -379,13 +379,13 @@
-
- trips {
- cpu_alert0: cpu-alert-0 {
-- temperature = <85000>; /* millicelsius */
-+ temperature = <85000>; /* millicelsius */
- };
- cpu_alert1: cpu-alert-1 {
-- temperature = <100000>; /* millicelsius */
-+ temperature = <100000>; /* millicelsius */
- };
- cpu_alert2: cpu-alert-2 {
-- temperature = <110000>; /* millicelsius */
-+ temperature = <110000>; /* millicelsius */
- };
- };
- };
---
-2.39.2
-
+++ /dev/null
-From c732800feec8ea9f551d804ee788ef5b3a356f6f Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 15 Apr 2019 20:05:07 +0200
-Subject: ARM: dts: exynos: Move pmu and timer nodes out of soc
-
-From: Krzysztof Kozlowski <krzk@kernel.org>
-
-[ Upstream commit be00300147ae3c0b2fa4dbc5f00d4332a8d00fac ]
-
-The ARM PMU and ARM architected timer nodes are part of ARM CPU design
-therefore they should not be inside the soc node. This also fixes DTC
-W=1 warnings like:
-
- arch/arm/boot/dts/exynos3250.dtsi:106.21-135.5:
- Warning (simple_bus_reg): /soc/fixed-rate-clocks: missing or empty reg/ranges property
- arch/arm/boot/dts/exynos3250.dtsi:676.7-680.5:
- Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property
-
-Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
-Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
-Stable-dep-of: 33e2c595e2e4 ("ARM: dts: exynos: correct TMU phandle in Exynos5250")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm/boot/dts/exynos3250.dtsi | 12 +++++-----
- arch/arm/boot/dts/exynos4.dtsi | 12 +++++-----
- arch/arm/boot/dts/exynos5250.dtsi | 40 +++++++++++++++----------------
- arch/arm/boot/dts/exynos54xx.dtsi | 38 ++++++++++++++---------------
- 4 files changed, 51 insertions(+), 51 deletions(-)
-
-diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
-index 5892a9f7622fa..af54b306204b8 100644
---- a/arch/arm/boot/dts/exynos3250.dtsi
-+++ b/arch/arm/boot/dts/exynos3250.dtsi
-@@ -97,6 +97,12 @@
- };
- };
-
-+ pmu {
-+ compatible = "arm,cortex-a7-pmu";
-+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
- soc: soc {
- compatible = "simple-bus";
- #address-cells = <1>;
-@@ -673,12 +679,6 @@
- status = "disabled";
- };
-
-- pmu {
-- compatible = "arm,cortex-a7-pmu";
-- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-- };
--
- ppmu_dmc0: ppmu_dmc0@106a0000 {
- compatible = "samsung,exynos-ppmu";
- reg = <0x106a0000 0x2000>;
-diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
-index 3f7488833745d..33eb2810cdaa2 100644
---- a/arch/arm/boot/dts/exynos4.dtsi
-+++ b/arch/arm/boot/dts/exynos4.dtsi
-@@ -51,6 +51,12 @@
- serial3 = &serial_3;
- };
-
-+ pmu: pmu {
-+ compatible = "arm,cortex-a9-pmu";
-+ interrupt-parent = <&combiner>;
-+ interrupts = <2 2>, <3 2>;
-+ };
-+
- soc: soc {
- compatible = "simple-bus";
- #address-cells = <1>;
-@@ -169,12 +175,6 @@
- reg = <0x10440000 0x1000>;
- };
-
-- pmu: pmu {
-- compatible = "arm,cortex-a9-pmu";
-- interrupt-parent = <&combiner>;
-- interrupts = <2 2>, <3 2>;
-- };
--
- sys_reg: syscon@10010000 {
- compatible = "samsung,exynos4-sysreg", "syscon";
- reg = <0x10010000 0x400>;
-diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
-index e6b1a8a9b832c..59e5f0016b862 100644
---- a/arch/arm/boot/dts/exynos5250.dtsi
-+++ b/arch/arm/boot/dts/exynos5250.dtsi
-@@ -157,6 +157,12 @@
- };
- };
-
-+ pmu {
-+ compatible = "arm,cortex-a15-pmu";
-+ interrupt-parent = <&combiner>;
-+ interrupts = <1 2>, <22 4>;
-+ };
-+
- soc: soc {
- sysram@2020000 {
- compatible = "mmio-sram";
-@@ -227,20 +233,6 @@
- power-domains = <&pd_mau>;
- };
-
-- timer {
-- compatible = "arm,armv7-timer";
-- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-- /*
-- * Unfortunately we need this since some versions
-- * of U-Boot on Exynos don't set the CNTFRQ register,
-- * so we need the value from DT.
-- */
-- clock-frequency = <24000000>;
-- };
--
- mct@101c0000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x101C0000 0x800>;
-@@ -265,12 +257,6 @@
- };
- };
-
-- pmu {
-- compatible = "arm,cortex-a15-pmu";
-- interrupt-parent = <&combiner>;
-- interrupts = <1 2>, <22 4>;
-- };
--
- pinctrl_0: pinctrl@11400000 {
- compatible = "samsung,exynos5250-pinctrl";
- reg = <0x11400000 0x1000>;
-@@ -1076,6 +1062,20 @@
- };
- };
- };
-+
-+ timer {
-+ compatible = "arm,armv7-timer";
-+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-+ /*
-+ * Unfortunately we need this since some versions
-+ * of U-Boot on Exynos don't set the CNTFRQ register,
-+ * so we need the value from DT.
-+ */
-+ clock-frequency = <24000000>;
-+ };
- };
-
- &dp {
-diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
-index de26e5ee0d2de..ae866bcc30c4e 100644
---- a/arch/arm/boot/dts/exynos54xx.dtsi
-+++ b/arch/arm/boot/dts/exynos54xx.dtsi
-@@ -25,27 +25,27 @@
- usbdrdphy1 = &usbdrd_phy1;
- };
-
-- soc: soc {
-- arm_a7_pmu: arm-a7-pmu {
-- compatible = "arm,cortex-a7-pmu";
-- interrupt-parent = <&gic>;
-- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
-- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
-- <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
-- <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
-- status = "disabled";
-- };
-+ arm_a7_pmu: arm-a7-pmu {
-+ compatible = "arm,cortex-a7-pmu";
-+ interrupt-parent = <&gic>;
-+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-
-- arm_a15_pmu: arm-a15-pmu {
-- compatible = "arm,cortex-a15-pmu";
-- interrupt-parent = <&combiner>;
-- interrupts = <1 2>,
-- <7 0>,
-- <16 6>,
-- <19 2>;
-- status = "disabled";
-- };
-+ arm_a15_pmu: arm-a15-pmu {
-+ compatible = "arm,cortex-a15-pmu";
-+ interrupt-parent = <&combiner>;
-+ interrupts = <1 2>,
-+ <7 0>,
-+ <16 6>,
-+ <19 2>;
-+ status = "disabled";
-+ };
-
-+ soc: soc {
- sysram@2020000 {
- compatible = "mmio-sram";
- reg = <0x02020000 0x54000>;
---
-2.39.2
-
udf-remove-pointless-union-in-udf_inode_info.patch
udf-preserve-link-count-of-system-files.patch
udf-detect-system-inodes-linked-into-directory-hiera.patch
-arm-dts-exynos-fix-language-typo-and-indentation.patch
-arm-dts-exynos-correct-tmu-phandle-in-exynos4210.patch
-arm-dts-exynos-add-all-cpus-in-cooling-maps.patch
-arm-dts-exynos-move-pmu-and-timer-nodes-out-of-soc.patch
-arm-dts-exynos-correct-tmu-phandle-in-exynos5250.patch
kbuild-fix-false-positive-need-builtin-calculation.patch
kbuild-generate-modules.order-only-in-directories-vi.patch
-arm-dts-exynos-correct-tmu-phandle-in-odroid-hc1.patch
-arm-dts-exynos-correct-tmu-phandle-in-odroid-xu3-fam.patch
scsi-core-remove-the-proc-scsi-proc_name-directory-e.patch
revert-spi-mt7621-fix-an-error-message-in-mt7621_spi_probe.patch
clk-qcom-mmcc-apq8084-remove-spdm-clocks.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
