power-domains = <&versal_firmware PM_DEV_I2C_1>;
};
+&i2c2 {
+ clocks = <&versal_clk I2C_REF>;
+ power-domains = <&versal_firmware PM_DEV_I2C_PMC>;
+};
+
&lpd_dma_chan0 {
clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;
power-domains = <&versal_firmware PM_DEV_ADMA_0>;
/*
* dts file for Xilinx Versal
*
- * (C) Copyright 2017 - 2019, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#size-cells = <0>;
};
+ i2c2: i2c@f1000000 {
+ compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
+ status = "disabled";
+ reg = <0 0xf1000000 0 0x1000>;
+ interrupts = <0 123 4>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
mc0: memory-controller@f6150000 {
compatible = "xlnx,versal-ddrmc-edac";
status = "disabled";