RISC-V: Add testcase for pr114734

gcc/testsuite/ChangeLog:

	PR middle-end/114734

	* gcc.target/riscv/rvv/autovec/pr114734.c: New test.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
new file mode 100644 (file)
index 0000000..b605d99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v } */
+/* { dg-options { -march=rv64gcv_zvl256b -mabi=lp64d -fwhole-program -O3 -mrvv-vector-bits=zvl  } } */
+
+int f[18];
+int g[18];
+int h[18][18][18];
+int a[324];
+long b[18];
+int *i = g;
+int (*j)[18][18] = h;
+int z;
+int main() {
+  for (int m = 0; m < 18; ++m)
+    f[m] = 3;
+  for (int m = 0; m < 18; m += 1)
+    for (int n = 0; n < 18; n += 3) {
+      a[m * 8 + n] = j[m][m][0] ? i[n] : 0;
+      b[n] = f[n] ? -i[m] : 0;
+    }
+  for (long n = 0; n < 8; ++n)
+    z = a[n];
+  if (b[15] != 0)
+    __builtin_abort();
+}