RISC-V: Add pattern for vector-scalar single-width floating-point add

This pattern enables the combine pass (or late-combine, depending on the case)
to merge a vec_duplicate into a plus RTL instruction.

Before this patch, we have two instructions, e.g.:
  vfmv.v.f       v2,fa0
  vfadd.vv       v1,v1,v2

After, we get only one:
  vfadd.vf       v1,v1,fa0

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*vfadd_vf_<mode>): New pattern to
	combine vec_duplicate + vfadd.vv into vfadd.vf.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c: Adjust scan
	dump.
	* gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfadd.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for
	vfadd.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f64.c: New test.

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 82a5fa0fae902e01b8492fb84dfcf12a2dedd022..f51b8ba8052377615578f98f4a593dcc27ffc12d 100644 (file)
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -2169,3 +2169,22 @@
   }
   [(set_attr "type" "vfwmul")]
 )
+
+;; vfadd.vf
+(define_insn_and_split "*vfadd_vf_<mode>"
+  [(set (match_operand:V_VLSF 0 "register_operand")
+    (plus:V_VLSF
+      (vec_duplicate:V_VLSF
+        (match_operand:<VEL> 2 "register_operand"))
+      (match_operand:V_VLSF 1 "register_operand")))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+    riscv_vector::emit_vlmax_insn (code_for_pred_scalar (PLUS, <MODE>mode),
+                                  riscv_vector::BINARY_OP_FRM_DYN, operands);
+    DONE;
+  }
+  [(set_attr "type" "vfalu")]
+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c
index 042dd0d5ccc68ed04f625aa53b11250c8a5c8f84..00b9222e76570abf551b792d5b0a2b190364325f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c
@@ -39,5 +39,5 @@ DEF_OP_VX (add, 128, double, +)
 DEF_OP_VX (add, 256, double, +)
 DEF_OP_VX (add, 512, double, +)
 
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c
index fffaa12323e59f855e641cf496e8d36199957e3a..4a7ede9ff325f54dcdcb4eaebce9e0258e2ba7eb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c
@@ -39,5 +39,5 @@ DEF_OP_VI_15 (add, 128, double, +)
 DEF_OP_VI_15 (add, 256, double, +)
 DEF_OP_VI_15 (add, 512, double, +)
 
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c
index 54a3adf3d1067e34de81e55837e0d6c10a14a84e..2591fb8073d7c2993d1b2432a50989ac5428dec3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c
@@ -39,5 +39,5 @@ DEF_OP_VI_15 (sub, 128, double, -)
 DEF_OP_VI_15 (sub, 256, double, -)
 DEF_OP_VI_15 (sub, 512, double, -)
 
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */
 /* { dg-final { scan-assembler-not {csrr} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
index cbec87e6c0b332ab867d5a4aeeafc37ecf1ec3d1..ad3e1999d3ebea249ac585a44e5b4354112ba0f5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
@@ -17,6 +17,7 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac)
 DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, -, nacc)
 DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac)
 DEF_VF_BINOP_CASE_0 (_Float16, *, mul)
+DEF_VF_BINOP_CASE_0 (_Float16, +, add)
 DEF_VF_BINOP_REVERSE_CASE_0 (_Float16, /, rdiv)
 DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min)
 DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min)
@@ -37,6 +38,7 @@ DEF_VF_BINOP_WIDEN_CASE_0 (_Float16, float, *, mul)
 /* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
 /* { dg-final { scan-assembler-times {vfmax.vf} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
index b6d94c650b0cd6eff20e1b5482f4185dd7cba650..dae2d04c3ede21c421e6a985651fa205a305a010 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
@@ -17,6 +17,7 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac)
 DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, -, nacc)
 DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac)
 DEF_VF_BINOP_CASE_0 (float, *, mul)
+DEF_VF_BINOP_CASE_0 (float, +, add)
 DEF_VF_BINOP_REVERSE_CASE_0 (float, /, rdiv)
 DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_0_WRAP (float), min)
 DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_1_WRAP (float), min)
@@ -37,6 +38,7 @@ DEF_VF_BINOP_WIDEN_CASE_0 (float, double, *, mul)
 /* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
 /* { dg-final { scan-assembler-times {vfmax.vf} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
index 4eb4a4e4b0668a86e4e5e0b986681b223f6ecd98..cb36ef846939f06bbfe64db091f0671a26b186b2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
@@ -13,6 +13,7 @@ DEF_VF_MULOP_ACC_CASE_0 (double, -, +, sac)
 DEF_VF_MULOP_ACC_CASE_0 (double, +, -, nacc)
 DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac)
 DEF_VF_BINOP_CASE_0 (double, *, mul)
+DEF_VF_BINOP_CASE_0 (double, +, add)
 DEF_VF_BINOP_REVERSE_CASE_0 (double, /, rdiv)
 DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_0_WRAP (double), min)
 DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_1_WRAP (double), min)
@@ -28,6 +29,7 @@ DEF_VF_BINOP_CASE_2_WRAP (double, MAX_FUNC_1_WRAP (double), max)
 /* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
 /* { dg-final { scan-assembler-times {vfmax.vf} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
index 3f31568825e4ad1b3caa36c89eb370db787eb510..eebb69f30915eddbdd1ae07edf022e6efb825679 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
@@ -16,6 +16,7 @@
 /* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */
 /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
 /* { dg-final { scan-assembler-not {vfmul.vf} } } */
+/* { dg-final { scan-assembler-not {vfadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
index 21a3e1d16aa5d64cd4ffb5d6d11ed500d8e0fdea..64ab5b191e14f8bb6118e2cc55474190cacd9a32 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
@@ -16,6 +16,7 @@
 /* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */
 /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
 /* { dg-final { scan-assembler-not {vfmul.vf} } } */
+/* { dg-final { scan-assembler-not {vfadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
index ffffde7a8a3f5f51252a4055de058e3895f2db70..b8497170d30ec7e81b09fbfd6e83d8c8d1ba0496 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
@@ -12,6 +12,7 @@
 /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */
 /* { dg-final { scan-assembler-not {vfmul.vf} } } */
+/* { dg-final { scan-assembler-not {vfadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
index 522b5d294649e8b138bcbf2053c6e7087366f4de..12e779c8a3c9b63fa666e9ec77ec532b90ada250 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
@@ -17,6 +17,7 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac)
 DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, -, nacc)
 DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac)
 DEF_VF_BINOP_CASE_1 (_Float16, *, mul, VF_BINOP_BODY_X128)
+DEF_VF_BINOP_CASE_1 (_Float16, +, add, VF_BINOP_BODY_X128)
 DEF_VF_BINOP_REVERSE_CASE_1 (_Float16, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
 DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min,
                          VF_BINOP_FUNC_BODY_X128)
@@ -41,6 +42,7 @@ DEF_VF_BINOP_WIDEN_CASE_1 (_Float16, float, *, mul)
 /* { dg-final { scan-assembler {vfwnmacc.vf} } } */
 /* { dg-final { scan-assembler {vfwnmsac.vf} } } */
 /* { dg-final { scan-assembler {vfmul.vf} } } */
+/* { dg-final { scan-assembler {vfadd.vf} } } */
 /* { dg-final { scan-assembler {vfrdiv.vf} } } */
 /* { dg-final { scan-assembler {vfmin.vf} } } */
 /* { dg-final { scan-assembler {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
index 8d05c54c7729918f13266b72c09a0d1c01ba9ce1..49ebc2bbace3764fc365959922379a4686393614 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
@@ -17,6 +17,7 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac)
 DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, -, nacc)
 DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac)
 DEF_VF_BINOP_CASE_1 (float, *, mul, VF_BINOP_BODY_X128)
+DEF_VF_BINOP_CASE_1 (float, +, add, VF_BINOP_BODY_X128)
 DEF_VF_BINOP_REVERSE_CASE_1 (float, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
 DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_0_WRAP (float), min,
                          VF_BINOP_FUNC_BODY_X128)
@@ -41,6 +42,7 @@ DEF_VF_BINOP_WIDEN_CASE_1 (float, double, *, mul)
 /* { dg-final { scan-assembler {vfwnmacc.vf} } } */
 /* { dg-final { scan-assembler {vfwnmsac.vf} } } */
 /* { dg-final { scan-assembler {vfmul.vf} } } */
+/* { dg-final { scan-assembler {vfadd.vf} } } */
 /* { dg-final { scan-assembler {vfrdiv.vf} } } */
 /* { dg-final { scan-assembler {vfmin.vf} } } */
 /* { dg-final { scan-assembler {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
index 831646f6a40703d99bf50c38cc71e44b3db05151..9f898d2d24918283c3d9ac7f166dfb077ca748d7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
@@ -13,6 +13,7 @@ DEF_VF_MULOP_ACC_CASE_1 (double, -, +, sac, VF_MULOP_ACC_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (double, +, -, nacc, VF_MULOP_ACC_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128)
 DEF_VF_BINOP_CASE_1 (double, *, mul, VF_BINOP_BODY_X128)
+DEF_VF_BINOP_CASE_1 (double, +, add, VF_BINOP_BODY_X128)
 DEF_VF_BINOP_REVERSE_CASE_1 (double, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
 DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_0_WRAP (double), min,
                          VF_BINOP_FUNC_BODY_X128)
@@ -32,6 +33,7 @@ DEF_VF_BINOP_CASE_3_WRAP (double, MAX_FUNC_1_WRAP (double), max,
 /* { dg-final { scan-assembler {vfnmacc.vf} } } */
 /* { dg-final { scan-assembler {vfnmsac.vf} } } */
 /* { dg-final { scan-assembler {vfmul.vf} } } */
+/* { dg-final { scan-assembler {vfadd.vf} } } */
 /* { dg-final { scan-assembler {vfrdiv.vf} } } */
 /* { dg-final { scan-assembler {vfmin.vf} } } */
 /* { dg-final { scan-assembler {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
index 3058367785e9acf69c5dc2901bc6245d6bf4c27a..eab87ef6022298ef56e5f6a0a5f24778350d5b83 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
@@ -16,6 +16,7 @@
 /* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */
 /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
 /* { dg-final { scan-assembler-not {vfmul.vf} } } */
+/* { dg-final { scan-assembler-not {vfadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
index d687f8f6f62475eeb74385923181ad9a6815fd48..5cd4d57a23b4ce3306add9abc3e6209d9a1ec533 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
@@ -16,6 +16,7 @@
 /* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */
 /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
 /* { dg-final { scan-assembler-not {vfmul.vf} } } */
+/* { dg-final { scan-assembler-not {vfadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
index d29006e5849a3fa8936e9fbe9f55cd4847e9fb18..437631c6626fe087eb03ea331bf83ea3b5711d76 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
@@ -12,6 +12,7 @@
 /* { dg-final { scan-assembler-not {vfnmacc.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */
 /* { dg-final { scan-assembler-not {vfmul.vf} } } */
+/* { dg-final { scan-assembler-not {vfadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
index 2f79cee16ca6f96a5760cf85e0a076ae7f3d44ce..48f7a26b9d2b3fabf3044f7266ddb73ed772b830 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
@@ -154,6 +154,153 @@ double TEST_BINOP_DATA(double, mul)[][4][N] =
   },
 };
 
+_Float16 TEST_BINOP_DATA(_Float16, add)[][4][N] =
+{
+  {
+    { 0x1.0000000000000p+0f16 },
+    {
+    0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16,
+    0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16,
+    0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16,
+    0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16,
+    },
+    {
+    0x1.9fc0000000000p+4f16, 0x1.9fc0000000000p+4f16, 0x1.9fc0000000000p+4f16, 0x1.9fc0000000000p+4f16,
+    0x1.bc80000000000p+6f16, 0x1.bc80000000000p+6f16, 0x1.bc80000000000p+6f16, 0x1.bc80000000000p+6f16,
+    0x1.acc0000000000p+5f16, 0x1.acc0000000000p+5f16, 0x1.acc0000000000p+5f16, 0x1.acc0000000000p+5f16,
+    0x1.7f80000000000p+4f16, 0x1.7f80000000000p+4f16, 0x1.7f80000000000p+4f16, 0x1.7f80000000000p+4f16,
+    },
+  },
+  {
+    { 0x1.9000000000000p+6f16 },
+    {
+    -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
+    0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16,
+    -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
+    -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
+    },
+    {
+    0x1.cc40000000000p+5f16, 0x1.cc40000000000p+5f16, 0x1.cc40000000000p+5f16, 0x1.cc40000000000p+5f16,
+    0x1.a980000000000p+7f16, 0x1.a980000000000p+7f16, 0x1.a980000000000p+7f16, 0x1.a980000000000p+7f16,
+    -0x1.37c0000000000p+7f16, -0x1.37c0000000000p+7f16, -0x1.37c0000000000p+7f16, -0x1.37c0000000000p+7f16,
+    -0x1.2800000000000p+0f16, -0x1.2800000000000p+0f16, -0x1.2800000000000p+0f16, -0x1.2800000000000p+0f16,
+    },
+  },
+  {
+    { -0x1.9000000000000p+6f16 },
+    {
+    -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
+    -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
+    0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16,
+    -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
+    },
+    {
+    -0x1.0980000000000p+7f16, -0x1.0980000000000p+7f16, -0x1.0980000000000p+7f16, -0x1.0980000000000p+7f16,
+    -0x1.5680000000000p+8f16, -0x1.5680000000000p+8f16, -0x1.5680000000000p+8f16, -0x1.5680000000000p+8f16,
+    -0x1.2a40000000000p+6f16, -0x1.2a40000000000p+6f16, -0x1.2a40000000000p+6f16, -0x1.2a40000000000p+6f16,
+    -0x1.0a40000000000p+7f16, -0x1.0a40000000000p+7f16, -0x1.0a40000000000p+7f16, -0x1.0a40000000000p+7f16,
+    },
+  },
+};
+
+float TEST_BINOP_DATA(float, add)[][4][N] =
+{
+  {
+    { 0x1.fffffe0000000p+63f },
+    {
+    0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f,
+    0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f,
+    0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f,
+    0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f,
+    },
+    {
+    0x1.18fe140000000p+64f, 0x1.18fe140000000p+64f, 0x1.18fe140000000p+64f, 0x1.18fe140000000p+64f,
+    0x1.6e2d4c0000000p+64f, 0x1.6e2d4c0000000p+64f, 0x1.6e2d4c0000000p+64f, 0x1.6e2d4c0000000p+64f,
+    0x1.349d660000000p+64f, 0x1.349d660000000p+64f, 0x1.349d660000000p+64f, 0x1.349d660000000p+64f,
+    0x1.16faec0000000p+64f, 0x1.16faec0000000p+64f, 0x1.16faec0000000p+64f, 0x1.16faec0000000p+64f,
+    },
+  },
+  {
+    { 0x1.bc16d60000000p+59f },
+    {
+    -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f,
+    0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f,
+    -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f,
+    -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f,
+    },
+    {
+    -0x1.c9b60a0000000p+60f, -0x1.c9b60a0000000p+60f, -0x1.c9b60a0000000p+60f, -0x1.c9b60a0000000p+60f,
+    0x1.fabc560000000p+62f, 0x1.fabc560000000p+62f, 0x1.fabc560000000p+62f, 0x1.fabc560000000p+62f,
+    -0x1.e420960000000p+63f, -0x1.e420960000000p+63f, -0x1.e420960000000p+63f, -0x1.e420960000000p+63f,
+    -0x1.5d4fcc0000000p+62f, -0x1.5d4fcc0000000p+62f, -0x1.5d4fcc0000000p+62f, -0x1.5d4fcc0000000p+62f,
+    },
+  },
+  {
+    { -0x1.5af1d80000000p+66f },
+    {
+    -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f,
+    -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f,
+    0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f,
+    -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f,
+    },
+    {
+    -0x1.63232a0000000p+66f, -0x1.63232a0000000p+66f, -0x1.63232a0000000p+66f, -0x1.63232a0000000p+66f,
+    -0x1.97a04a0000000p+66f, -0x1.97a04a0000000p+66f, -0x1.97a04a0000000p+66f, -0x1.97a04a0000000p+66f,
+    -0x1.5496800000000p+66f, -0x1.5496800000000p+66f, -0x1.5496800000000p+66f, -0x1.5496800000000p+66f,
+    -0x1.6339320000000p+66f, -0x1.6339320000000p+66f, -0x1.6339320000000p+66f, -0x1.6339320000000p+66f,
+    },
+  },
+};
+
+double TEST_BINOP_DATA(double, add)[][4][N] =
+{
+  {
+    { 0x1.317e5ef3ab327p+508 },
+    {
+    0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508,
+    0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510,
+    0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509,
+    0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508,
+    },
+    {
+    0x1.60afdaa95eed0p+509, 0x1.60afdaa95eed0p+509, 0x1.60afdaa95eed0p+509, 0x1.60afdaa95eed0p+509,
+    0x1.028a65ca864cap+511, 0x1.028a65ca864cap+511, 0x1.028a65ca864cap+511, 0x1.028a65ca864cap+511,
+    0x1.1ed532988d1f4p+510, 0x1.1ed532988d1f4p+510, 0x1.1ed532988d1f4p+510, 0x1.1ed532988d1f4p+510,
+    0x1.50969d2ba0938p+509, 0x1.50969d2ba0938p+509, 0x1.50969d2ba0938p+509, 0x1.50969d2ba0938p+509,
+    },
+  },
+  {
+    { 0x1.317e5ef3ab327p+508 },
+    {
+    -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509,
+    0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510,
+    -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511,
+    -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510,
+    },
+    {
+    -0x1.7643190f36ca9p+508, -0x1.7643190f36ca9p+508, -0x1.7643190f36ca9p+508, -0x1.7643190f36ca9p+508,
+    0x1.07cc8a55d3706p+511, 0x1.07cc8a55d3706p+511, 0x1.07cc8a55d3706p+511, 0x1.07cc8a55d3706p+511,
+    -0x1.d9b238912437ep+511, -0x1.d9b238912437ep+511, -0x1.d9b238912437ep+511, -0x1.d9b238912437ep+511,
+    -0x1.487311435414ep+510, -0x1.487311435414ep+510, -0x1.487311435414ep+510, -0x1.487311435414ep+510,
+    },
+  },
+  {
+    { -0x1.317e5ef3ab327p+508 },
+    {
+    -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509,
+    -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511,
+    0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508,
+    -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509,
+    },
+    {
+    -0x1.9ee9651b12854p+509, -0x1.9ee9651b12854p+509, -0x1.9ee9651b12854p+509, -0x1.9ee9651b12854p+509,
+    -0x1.05d1b1f39c559p+512, -0x1.05d1b1f39c559p+512, -0x1.05d1b1f39c559p+512, -0x1.05d1b1f39c559p+512,
+    0x1.955d935b3ac44p+506, 0x1.955d935b3ac44p+506, 0x1.955d935b3ac44p+506, 0x1.955d935b3ac44p+506,
+    -0x1.a1aa9281a490cp+509, -0x1.a1aa9281a490cp+509, -0x1.a1aa9281a490cp+509, -0x1.a1aa9281a490cp+509,
+    },
+  },
+};
+
 _Float16 TEST_BINOP_DATA(_Float16, rdiv)[][4][N] =
 {
   {

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f16.c
new file mode 100644 (file)
index 0000000..ffbc288
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f16.c
@@ -0,0 +1,19 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T    _Float16
+#define NAME add
+
+DEF_VF_BINOP_CASE_0_WRAP (T, +, NAME)
+
+#define TEST_DATA                        TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n)
+
+#include "vf_binop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f32.c
new file mode 100644 (file)
index 0000000..91f4f03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T    float
+#define NAME add
+
+DEF_VF_BINOP_CASE_0_WRAP (T, +, NAME)
+
+#define TEST_DATA                        TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n)
+
+#include "vf_binop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f64.c
new file mode 100644 (file)
index 0000000..02578fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T    double
+#define NAME add
+
+DEF_VF_BINOP_CASE_0_WRAP (T, +, NAME)
+
+#define TEST_DATA                        TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_0_WRAP(T, NAME, out, in, f, n)
+
+#include "vf_binop_run.h"