5.10-stable patches

added patches:
	can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch
	clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch
	clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch

diff --git a/queue-5.10/can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch b/queue-5.10/can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch
new file mode 100644 (file)
index 0000000..8154f96
--- /dev/null
+++ b/queue-5.10/can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch
@@ -0,0 +1,52 @@
+From 7dd9c26bd6cf679bcfdef01a8659791aa6487a29 Mon Sep 17 00:00:00 2001
+From: Simon Arlott <simon@octiron.net>
+Date: Thu, 22 Aug 2024 08:25:07 +0100
+Subject: can: mcp251x: fix deadlock if an interrupt occurs during mcp251x_open
+
+From: Simon Arlott <simon@octiron.net>
+
+commit 7dd9c26bd6cf679bcfdef01a8659791aa6487a29 upstream.
+
+The mcp251x_hw_wake() function is called with the mpc_lock mutex held and
+disables the interrupt handler so that no interrupts can be processed while
+waking the device. If an interrupt has already occurred then waiting for
+the interrupt handler to complete will deadlock because it will be trying
+to acquire the same mutex.
+
+CPU0                           CPU1
+----                           ----
+mcp251x_open()
+ mutex_lock(&priv->mcp_lock)
+  request_threaded_irq()
+                               <interrupt>
+                               mcp251x_can_ist()
+                                mutex_lock(&priv->mcp_lock)
+  mcp251x_hw_wake()
+   disable_irq() <-- deadlock
+
+Use disable_irq_nosync() instead because the interrupt handler does
+everything while holding the mutex so it doesn't matter if it's still
+running.
+
+Fixes: 8ce8c0abcba3 ("can: mcp251x: only reset hardware as required")
+Signed-off-by: Simon Arlott <simon@octiron.net>
+Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/all/4fc08687-1d80-43fe-9f0d-8ef8475e75f6@0882a8b5-c6c3-11e9-b005-00805fc181fe.uuid.home.arpa
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/can/spi/mcp251x.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/can/spi/mcp251x.c
++++ b/drivers/net/can/spi/mcp251x.c
+@@ -755,7 +755,7 @@ static int mcp251x_hw_wake(struct spi_de
+       int ret;
+ 
+       /* Force wakeup interrupt to wake device, but don't execute IST */
+-      disable_irq(spi->irq);
++      disable_irq_nosync(spi->irq);
+       mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF);
+ 
+       /* Wait for oscillator startup timer after wake up */

diff --git a/queue-5.10/clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch b/queue-5.10/clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch
new file mode 100644 (file)
index 0000000..6232cf8
--- /dev/null
+++ b/queue-5.10/clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch
@@ -0,0 +1,33 @@
+From 2c4553e6c485a96b5d86989eb9654bf20e51e6dd Mon Sep 17 00:00:00 2001
+From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
+Date: Wed, 31 Jul 2024 11:59:09 +0530
+Subject: clk: qcom: clk-alpha-pll: Fix the pll post div mask
+
+From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
+
+commit 2c4553e6c485a96b5d86989eb9654bf20e51e6dd upstream.
+
+The PLL_POST_DIV_MASK should be 0 to (width - 1) bits. Fix it.
+
+Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
+Cc: stable@vger.kernel.org
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
+Link: https://lore.kernel.org/r/20240731062916.2680823-2-quic_skakitap@quicinc.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/clk/qcom/clk-alpha-pll.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/qcom/clk-alpha-pll.c
++++ b/drivers/clk/qcom/clk-alpha-pll.c
+@@ -38,7 +38,7 @@
+ 
+ #define PLL_USER_CTL(p)               ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
+ # define PLL_POST_DIV_SHIFT   8
+-# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
++# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
+ # define PLL_ALPHA_EN         BIT(24)
+ # define PLL_ALPHA_MODE               BIT(25)
+ # define PLL_VCO_SHIFT                20

diff --git a/queue-5.10/clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch b/queue-5.10/clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch
new file mode 100644 (file)
index 0000000..ee4ac46
--- /dev/null
+++ b/queue-5.10/clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch
@@ -0,0 +1,37 @@
+From 4ad1ed6ef27cab94888bb3c740c14042d5c0dff2 Mon Sep 17 00:00:00 2001
+From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
+Date: Wed, 31 Jul 2024 11:59:10 +0530
+Subject: clk: qcom: clk-alpha-pll: Fix the trion pll postdiv set rate API
+
+From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
+
+commit 4ad1ed6ef27cab94888bb3c740c14042d5c0dff2 upstream.
+
+Correct the pll postdiv shift used in clk_trion_pll_postdiv_set_rate
+API. The shift value is not same for different types of plls and
+should be taken from the pll's .post_div_shift member.
+
+Fixes: 548a909597d5 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs")
+Cc: stable@vger.kernel.org
+Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/20240731062916.2680823-3-quic_skakitap@quicinc.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/clk/qcom/clk-alpha-pll.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/qcom/clk-alpha-pll.c
++++ b/drivers/clk/qcom/clk-alpha-pll.c
+@@ -1321,8 +1321,8 @@ clk_trion_pll_postdiv_set_rate(struct cl
+       }
+ 
+       return regmap_update_bits(regmap, PLL_USER_CTL(pll),
+-                                PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
+-                                val << PLL_POST_DIV_SHIFT);
++                                PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
++                                val << pll->post_div_shift);
+ }
+ 
+ const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {

diff --git a/queue-5.10/series b/queue-5.10/series
index 272d44093203c346d4af367713ad22db1b961872..4b9476b30c9c1be0ae85b40d9c8387e4f525a88c 100644 (file)
--- a/queue-5.10/series
+++ b/queue-5.10/series
@@ -64,3 +64,6 @@ mmc-dw_mmc-fix-idmac-operation-with-pages-bigger-than-4k.patch
 mmc-sdhci-of-aspeed-fix-module-autoloading.patch
 fuse-update-stats-for-pages-in-dropped-aux-writeback-list.patch
 fuse-use-unsigned-type-for-getxattr-listxattr-size-truncation.patch
+clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch
+clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch
+can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch