riscv: Add stimecmp save and restore

If the HW support the SSTC extension, we should save and restore the
stimecmp register while cpu non retention suspend.

Signed-off-by: Nick Hu <nick.hu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250219114135.27764-2-nick.hu@sifive.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>

diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
index 4ffb022b097f42b084b3328de8f10a8d87d28355..dc5782b5fbad04d971b503166ba79a7a84420b86 100644 (file)
--- a/arch/riscv/include/asm/suspend.h
+++ b/arch/riscv/include/asm/suspend.h
@@ -18,6 +18,10 @@ struct suspend_context {
        unsigned long ie;
 #ifdef CONFIG_MMU
        unsigned long satp;
+       unsigned long stimecmp;
+#if __riscv_xlen < 64
+       unsigned long stimecmph;
+#endif
 #endif
 };
 

diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
index 9a8a0dc035b2601fadd6625ced653a9820b243b4..24b3f57d467f83c3d4f012dfba16425146c18d61 100644 (file)
--- a/arch/riscv/kernel/suspend.c
+++ b/arch/riscv/kernel/suspend.c
@@ -30,6 +30,13 @@ void suspend_save_csrs(struct suspend_context *context)
         */
 
 #ifdef CONFIG_MMU
+       if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SSTC)) {
+               context->stimecmp = csr_read(CSR_STIMECMP);
+#if __riscv_xlen < 64
+               context->stimecmph = csr_read(CSR_STIMECMPH);
+#endif
+       }
+
        context->satp = csr_read(CSR_SATP);
 #endif
 }
@@ -43,6 +50,13 @@ void suspend_restore_csrs(struct suspend_context *context)
        csr_write(CSR_IE, context->ie);
 
 #ifdef CONFIG_MMU
+       if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SSTC)) {
+               csr_write(CSR_STIMECMP, context->stimecmp);
+#if __riscv_xlen < 64
+               csr_write(CSR_STIMECMPH, context->stimecmph);
+#endif
+       }
+
        csr_write(CSR_SATP, context->satp);
 #endif
 }