/capsule.*.efi-capsule
/capsule*.map
/keep-syms-lto.*
+/*imx8mimage*
+/*imx8mcst*
#
# Generated include files
Fabio Estevam <fabio.estevam@nxp.com>
Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com>
+Heiko Stuebner <heiko.stuebner@cherry.de> <heiko.stuebner@theobroma-systems.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> <ibai.erkiaga-elorza@xilinx.com>
Jagan Teki <jaganna@xilinx.com>
Jagan Teki <jagannadh.teki@gmail.com>
Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
+Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de> <jakob.unterwurzacher@theobroma-systems.com>
Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com>
Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
John Linn <john.linn@amd.com> <john.linn@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com>
+Klaus Goger <klaus.goger@cherry.de> <klaus.goger@theobroma-systems.com>
Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org>
Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com>
Lukasz Majewski <lukma@denx.de>
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
+Philipp Tomsich <philipp.tomsich@vrull.eu> <philipp.tomsich@theobroma-systems.com>
Piyush Mehta <piyush.mehta@amd.com> <piyush.mehta@xilinx.com>
Prabhakar Kushwaha <prabhakar@freescale.com>
Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@amd.com> <punnaiah.choudary.kalluri@xilinx.com>
+Quentin Schulz <quentin.schulz@cherry.de> <quentin.schulz@theobroma-systems.com>
Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> <radhey.shyam.pandey@xilinx.com>
Rajeshwari Shinde <rajeshwari.s@samsung.com>
Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com> <raju.kumar-pothuraju@xilinx.com>
F: board/freescale/*mx*/
F: board/freescale/common/
F: common/spl/spl_imx_container.c
+F: doc/imx/
F: drivers/serial/serial_mxc.c
F: include/imx_container.h
ARM SAMSUNG EXYNOS850 SOC
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
-F: arch/arm/dts/exynos850-pinctrl.dtsi
-F: arch/arm/dts/exynos850.dtsi
-F: doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
F: drivers/clk/exynos/clk-exynos850.c
F: drivers/pinctrl/exynos/pinctrl-exynos850.c
-F: include/dt-bindings/clock/exynos850.h
ARM SAMSUNG SOC DRIVERS
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
-F: doc/device-tree-bindings/soc/samsung/*
+F: doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml
F: drivers/soc/samsung/*
-F: include/dt-bindings/soc/samsung,*.h
ARM SANCLOUD
M: Paul Barker <paul.barker@sancloud.com>
F: doc/api/dfu.rst
F: doc/usage/dfu.rst
F: drivers/dfu/
+F: drivers/usb/*/*gadget*
F: drivers/usb/gadget/
F: include/dfu.h
+F: include/linux/usb/ch9.h
+F: include/linux/usb/gadget.h
DRIVER MODEL
M: Simon Glass <sjg@chromium.org>
FASTBOOT
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
S: Maintained
+T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: cmd/fastboot.c
F: doc/android/fastboot*.rst
F: include/fastboot.h
F: drivers/watchdog/sp805_wdt.c
F: drivers/watchdog/sbsa_gwdt.c
+FWU Multi Bank Update
+M: Sughosh Ganu <sughosh.ganu@linaro.org>
+S: Maintained
+T: git https://source.denx.de/u-boot/custodians/u-boot-efi.git
+F: lib/fwu_updates/*
+F: drivers/fwu-mdata/*
+F: tools/mkfwumdata.c
+
GATEWORKS_SC
M: Tim Harvey <tharvey@gateworks.com>
S: Maintained
VERSION = 2024
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
# is "yes"), so compile examples after U-Boot is compiled.
examples: $(filter-out examples, $(u-boot-dirs))
+# The setlocalversion script comes from linux and expects a
+# KERNELVERSION variable in the environment for figuring out which
+# annotated tags are relevant. Pass UBOOTVERSION.
define filechk_uboot.release
- echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
+ KERNELVERSION=$(UBOOTVERSION) $(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree)
endef
# Store (new) UBOOTRELEASE string in include/config/uboot.release
# Remove include/asm symlink created by U-Boot before v2014.01
MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \
ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
- drivers/video/fonts/*.S include/asm
+ drivers/video/fonts/*.S include/asm *imx8mimage* *imx8mcst*
# clean - Delete most, but leave enough to build external modules
#
$(PERL) $(src)/scripts/checkstack.pl $(ARCH)
ubootrelease:
- @echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
+ @$(filechk_uboot.release)
ubootversion:
@echo $(UBOOTVERSION)
#include <clock_legacy.h>
#include <init.h>
#include <malloc.h>
-#include <vsprintf.h>
+#include <stdio.h>
#include <asm/arcregs.h>
#include <asm/cache.h>
#include <asm/global_data.h>
select SERIAL_SEARCH_ALL
imply CMD_DM
imply FAT_WRITE
+ imply OF_HAS_PRIOR_STAGE
config ARCH_BCMSTB
bool "Broadcom BCM7XXX family"
dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
-dtb-$(CONFIG_TARGET_E850_96) += exynos850-e850-96.dtb
dtb-$(CONFIG_ARCH_APPLE) += \
t8103-j274.dtb \
t8103-j457.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += \
- da850-evm.dtb \
da850-lcdk.dtb \
da850-lego-ev3.dtb
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb
-dtb-$(CONFIG_ROCKCHIP_RK3308) += \
- rk3308-evb.dtb \
- rk3308-roc-cc.dtb \
- rk3308-rock-pi-s.dtb
-
-dtb-$(CONFIG_ROCKCHIP_RK3328) += \
- rk3328-evb.dtb \
- rk3328-nanopi-r2c.dtb \
- rk3328-nanopi-r2c-plus.dtb \
- rk3328-nanopi-r2s.dtb \
- rk3328-orangepi-r1-plus.dtb \
- rk3328-orangepi-r1-plus-lts.dtb \
- rk3328-roc-cc.dtb \
- rk3328-rock64.dtb \
- rk3328-rock-pi-e.dtb
-
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-lion-haikou.dtb \
rk3368-sheep.dtb \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
-dtb-$(CONFIG_ROCKCHIP_RK3399) += \
- rk3399-evb.dtb \
- rk3399-eaidk-610.dtb \
- rk3399-ficus.dtb \
- rk3399-firefly.dtb \
- rk3399-gru-bob.dtb \
- rk3399-gru-kevin.dtb \
- rk3399-khadas-edge.dtb \
- rk3399-khadas-edge-captain.dtb \
- rk3399-khadas-edge-v.dtb \
- rk3399-leez-p710.dtb \
- rk3399-nanopc-t4.dtb \
- rk3399-nanopi-m4.dtb \
- rk3399-nanopi-m4-2gb.dtb \
- rk3399-nanopi-m4b.dtb \
- rk3399-nanopi-neo4.dtb \
- rk3399-nanopi-r4s.dtb \
- rk3399-orangepi.dtb \
- rk3399-pinebook-pro.dtb \
- rk3399-pinephone-pro.dtb \
- rk3399-puma-haikou.dtb \
- rk3399-roc-pc.dtb \
- rk3399-roc-pc-mezzanine.dtb \
- rk3399-rock-4c-plus.dtb \
- rk3399-rock-4se.dtb \
- rk3399-rock-pi-4a.dtb \
- rk3399-rock-pi-4c.dtb \
- rk3399-rock960.dtb \
- rk3399-rockpro64.dtb \
- rk3399pro-rock-pi-n10.dtb
-
-dtb-$(CONFIG_ROCKCHIP_RK3568) += \
- rk3566-anbernic-rgxx3.dtb \
- rk3566-pinetab2-v0.1.dtb \
- rk3566-pinetab2-v2.0.dtb \
- rk3566-quartz64-a.dtb \
- rk3566-quartz64-b.dtb \
- rk3566-radxa-cm3-io.dtb \
- rk3566-soquartz-blade.dtb \
- rk3566-soquartz-cm4.dtb \
- rk3566-soquartz-model-a.dtb \
- rk3568-bpi-r2-pro.dtb \
- rk3568-evb.dtb \
- rk3568-generic.dtb \
- rk3568-lubancat-2.dtb \
- rk3568-nanopi-r5c.dtb \
- rk3568-nanopi-r5s.dtb \
- rk3568-odroid-m1.dtb \
- rk3568-radxa-e25.dtb \
- rk3568-rock-3a.dtb
-
-dtb-$(CONFIG_ROCKCHIP_RK3588) += \
- rk3588s-coolpi-4b.dtb \
- rk3588-coolpi-cm5-evb.dtb \
- rk3588-edgeble-neu6a-io.dtb \
- rk3588-edgeble-neu6b-io.dtb \
- rk3588-evb1-v10.dtb \
- rk3588-generic.dtb \
- rk3588-jaguar.dtb \
- rk3588-nanopc-t6.dtb \
- rk3588s-orangepi-5.dtb \
- rk3588-orangepi-5-plus.dtb \
- rk3588-quartzpro64.dtb \
- rk3588s-rock-5a.dtb \
- rk3588-rock-5b.dtb \
- rk3588-toybrick-x0.dtb \
- rk3588-turing-rk1.dtb
-
-dtb-$(CONFIG_ROCKCHIP_RV1108) += \
- rv1108-elgin-r1.dtb \
- rv1108-evb.dtb
-
-dtb-$(CONFIG_ROCKCHIP_RV1126) += \
- rv1126-edgeble-neu2-io.dtb
-
dtb-$(CONFIG_ARCH_S5P4418) += \
s5p4418-nanopi2.dtb
am437x-idk-evm.dtb \
am4372-generic.dtb \
am437x-cm-t43.dtb
-dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
imx8mm-kontron-bl-osm-s.dtb \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
- imx8mm-phyboard-polis-rdk.dtb \
- imx8mm-phygate-tauri-l.dtb \
imx8mn-bsh-smm-s2.dtb \
imx8mn-bsh-smm-s2pro.dtb \
imx8mq-cm.dtb \
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \
- imx8mp-phyboard-pollux-rdk.dtb \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb \
imx8mq-librem5-r4.dtb
imxrt1020-evk.dtb \
imxrt1170-evk.dtb \
-dtb-$(CONFIG_RCAR_GEN2) += \
- r8a7790-lager.dtb \
- r8a7790-stout.dtb \
- r8a7791-koelsch.dtb \
- r8a7791-porter.dtb \
- r8a7792-blanche.dtb \
- r8a7793-gose.dtb \
- r8a7794-alt.dtb \
- r8a7794-silk.dtb
-
-dtb-$(CONFIG_RCAR_GEN3) += \
- r8a774a1-beacon-rzg2m-kit.dtb \
- r8a774b1-beacon-rzg2n-kit.dtb \
- r8a774e1-beacon-rzg2h-kit.dtb \
- r8a774a1-hihope-rzg2m.dtb \
- r8a774b1-hihope-rzg2n.dtb \
- r8a774c0-ek874.dtb \
- r8a774e1-hihope-rzg2h.dtb \
- r8a77951-ulcb.dtb \
- r8a77951-salvator-x.dtb \
- r8a77960-ulcb.dtb \
- r8a77960-salvator-x.dtb \
- r8a77965-ulcb.dtb \
- r8a77965-salvator-x.dtb \
- r8a77970-eagle.dtb \
- r8a77970-v3msk.dtb \
- r8a77980-condor.dtb \
- r8a77980-v3hsk.dtb \
- r8a77990-ebisu.dtb \
- r8a77995-draak.dtb
-
-dtb-$(CONFIG_RCAR_GEN4) += \
- r8a779a0-falcon.dtb \
- r8a779f0-spider.dtb \
- r8a779g0-white-hawk.dtb \
- r8a779h0-gray-hawk.dtb
-
dtb-$(CONFIG_TARGET_RZG2L) += \
r9a07g044l2-smarc.dts
dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb
-dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \
- logicpd-som-lv-35xx-devkit.dtb \
- logicpd-som-lv-37xx-devkit.dtb \
- logicpd-torpedo-35xx-devkit.dtb \
- logicpd-torpedo-37xx-devkit.dtb
-
dtb-$(CONFIG_TARGET_OMAP3_EVM) += \
omap3-evm-37xx.dtb \
omap3-evm.dtb
dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb
-dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
- omap3-igep0020.dtb
-
dtb-$(CONFIG_TARGET_OMAP4_PANDA) += \
omap4-panda.dtb \
omap4-panda-es.dtb
k3-j721e-beagleboneai64.dtb \
k3-j721e-r5-beagleboneai64.dtb
-dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
- k3-am68-sk-r5-base-board.dtb\
- k3-j721s2-common-proc-board.dtb\
+dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am3517.dtsi"
-#include "am3517-som.dtsi"
-#include "am3517-evm-ui.dtsi"
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)";
- compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3";
-
- aliases {
- display0 = &lcd0;
- };
-
- chosen {
- stdout-path = &uart3;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256 MB */
- };
-
- vmmc_fixed: vmmc {
- compatible = "regulator-fixed";
- regulator-name = "vmmc_fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
-
- button-user {
- label = "User Push Button";
- linux,code = <BTN_0>;
- gpios = <&tca6416 5 GPIO_ACTIVE_LOW>;
- };
-
- switch-1 {
- label = "User Switch 1";
- linux,code = <BTN_1>;
- gpios = <&tca6416 8 GPIO_ACTIVE_LOW>;
- };
-
- switch-2 {
- label = "User Switch 2";
- linux,code = <BTN_2>;
- gpios = <&tca6416 9 GPIO_ACTIVE_LOW>;
- };
-
- switch-3 {
- label = "User Switch 3";
- linux,code = <BTN_3>;
- gpios = <&tca6416 10 GPIO_ACTIVE_LOW>;
- };
-
- switch-4 {
- label = "User Switch 4";
- linux,code = <BTN_4>;
- gpios = <&tca6416 11 GPIO_ACTIVE_LOW>;
- };
-
- switch-5 {
- label = "User Switch 5";
- linux,code = <BTN_5>;
- gpios = <&tca6416 12 GPIO_ACTIVE_LOW>;
- };
-
- switch-6 {
- label = "User Switch 6";
- linux,code = <BTN_6>;
- gpios = <&tca6416 13 GPIO_ACTIVE_LOW>;
- };
-
- switch-7 {
- label = "User Switch 7";
- linux,code = <BTN_7>;
- gpios = <&tca6416 14 GPIO_ACTIVE_LOW>;
- };
-
- switch-8 {
- label = "User Switch 8";
- linux,code = <BTN_8>;
- gpios = <&tca6416 15 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- pinctrl-names = "default";
- pinctrl-0 = <&leds_pins>;
-
- user_led_1 {
- label = "am3517evm:green:user_led_1";
- gpios = <&tca6416 7 GPIO_ACTIVE_LOW>;
- default-state = "on";
- };
-
- user_led_2 {
- label = "am3517evm:green:user_led_2";
- gpios = <&tca6416 6 GPIO_ACTIVE_LOW>;
- default-state = "on";
- };
-
- user_led_3 {
- label = "am3517evm:green:user_led_3";
- gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0"; /* SD/MMC card activity */
- };
-
- user_led_4 {
- label = "am3517evm:green:user_led_4";
- gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- lcd0: display@0 {
- /* This isn't the exact LCD, but the timings meet spec */
- /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */
- compatible = "newhaven,nhd-4.3-480272ef-atxl";
- label = "15";
- backlight = <&bl>;
- enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */
- vcc-supply = <&vdd_io_reg>;
-
- port {
- lcd_in: endpoint {
- remote-endpoint = <&dpi_out>;
- };
- };
- };
-
- bl: backlight {
- compatible = "pwm-backlight";
- pinctrl-names = "default";
- power-supply = <&vdd_io_reg>;
- pinctrl-0 = <&backlight_pins>;
- pwms = <&pwm11 0 5000000 0>;
- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
- default-brightness-level = <7>;
- enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */
- };
-
- pwm11: pwm-11 {
- compatible = "ti,omap-dmtimer-pwm";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm_pins>;
- ti,timers = <&timer11>;
- #pwm-cells = <3>;
- ti,clock-source = <0x01>;
- };
-
- /* HS USB Host PHY on PORT 1 */
- hsusb1_phy: hsusb1_phy {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb1_rst_pins>;
- compatible = "usb-nop-xceiv";
- reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */
- #phy-cells = <0>;
- };
-};
-
-&davinci_emac {
- pinctrl-names = "default";
- pinctrl-0 = <ðernet_pins>;
- status = "okay";
-};
-
-&davinci_mdio {
- status = "okay";
-};
-
-&dss {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&dss_dpi_pins>;
-
- vdds_dsi-supply = <&vdd_io_reg>;
- vdda_video-supply = <&vdd_io_reg>;
-
- port {
- dpi_out: endpoint {
- remote-endpoint = <&lcd_in>;
- data-lines = <16>;
- };
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- /* User DIP swithes [1:8] / User LEDS [1:2] */
- tca6416: gpio@21 {
- compatible = "ti,tca6416";
- reg = <0x21>;
- gpio-controller;
- #gpio-cells = <2>;
- vcc-supply = <&vdd_io_reg>;
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
-};
-
-&mmc1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
- vmmc-supply = <&vmmc_fixed>;
- bus-width = <4>;
- wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
- cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio_127 */
-};
-
-&mmc3 {
- status = "disabled";
-};
-
-&usbhshost {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb1_pins>;
- port1-mode = "ehci-phy";
-};
-
-&usbhsehci {
- phys = <&hsusb1_phy>;
-};
-
-&omap3_pmx_core {
-
- ethernet_pins: pinmux_ethernet_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */
- OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */
- OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd0 */
- OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd1 */
- OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_crs_dv */
- OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_rxer */
- OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd0 */
- OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd1 */
- OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN |MUX_MODE0) /* rmii_txen */
- OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */
- >;
- };
-
- leds_pins: pinmux_leds_pins {
- pinctrl-single,pins = <
- OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 */
- OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu1.gpio_31 */
- >;
- };
-
- mmc1_pins: pinmux_mmc1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
- OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat4.gpio_126 */
- OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat5.gpio_127 */
- >;
- };
-
- pwm_pins: pinmux_pwm_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE1) /* mcspi2_cs0.gpt11_pwm */
- >;
- };
-
- backlight_pins: pinmux_backlight_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT | MUX_MODE4) /* mcspi2_cs1.gpio_182 */
- >;
- };
-
- dss_dpi_pins: pinmux_dss_dpi_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21d2, PIN_OUTPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
- >;
- };
-
- hsusb1_rst_pins: pinmux_hsusb1_rst_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
- >;
- };
-};
-
-&omap3_pmx_core2 {
-
- hsusb1_pins: pinmux_hsusb1_pins {
- pinctrl-single,pins = <
- OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
- OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
- OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */
- OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */
- OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */
- OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */
- OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */
- OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */
- OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */
- OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */
- OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */
- OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */
- >;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2016 Derald D. Woods <woods.technical@gmail.com>
- *
- * Based on am3517-evm.dts
- */
-
-/ {
- cpus {
- cpu@0 {
- cpu0-supply = <&vdd_core_reg>;
- };
- };
-
- wl12xx_buffer: wl12xx_buf {
- compatible = "regulator-fixed";
- regulator-name = "wl1271_buf";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- pinctrl-names = "default";
- pinctrl-0 = <&wl12xx_buffer_pins>;
- gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */
- regulator-always-on;
- vin-supply = <&vdd_1v8_reg>;
- };
-
- wl12xx_vmmc2: wl12xx_vmmc2 {
- compatible = "regulator-fixed";
- regulator-name = "vwl1271";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- pinctrl-names = "default";
- pinctrl-0 = <&wl12xx_wkup_pins>;
- gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */
- startup-delay-us = <70000>;
- enable-active-high;
- regulator-always-on;
- vin-supply = <&wl12xx_buffer>;
- };
-};
-
-&gpmc {
- ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
-
- nand@0,0 {
- compatible = "ti,omap2-nand";
- linux,mtd-name = "micron,mt29f4g16abchch";
- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
- nand-bus-width = <16>;
- ti,nand-ecc-opt = "bch8";
- gpmc,sync-clk-ps = <0>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <44>;
- gpmc,cs-wr-off-ns = <44>;
- gpmc,adv-on-ns = <6>;
- gpmc,adv-rd-off-ns = <34>;
- gpmc,adv-wr-off-ns = <44>;
- gpmc,we-off-ns = <40>;
- gpmc,oe-off-ns = <54>;
- gpmc,access-ns = <64>;
- gpmc,rd-cycle-ns = <82>;
- gpmc,wr-cycle-ns = <82>;
- gpmc,wr-access-ns = <40>;
- gpmc,wr-data-mux-bus-ns = <0>;
- gpmc,device-width = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
-
- s35390a: s35390a@30 {
- compatible = "sii,s35390a";
- reg = <0x30>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&rtc_pins>;
- interrupts-extended = <&gpio2 23 IRQ_TYPE_EDGE_FALLING>; /* gpio_55 */
- };
-
- tps: tps65023@48 {
- compatible = "ti,tps65023";
- reg = <0x48>;
-
- regulators {
- vdd_core_reg: VDCDC1 {
- regulator-name = "vdd_core";
- regulator-always-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- vdd_io_reg: VDCDC2 {
- regulator-name = "vdd_io";
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vdd_1v8_reg: VDCDC3 {
- regulator-name = "vdd_1v8";
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vdd_usb18_reg: LDO1 {
- regulator-name = "vdd_usb18";
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vdd_usb33_reg: LDO2 {
- regulator-name = "vdd_usb33";
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
-
- touchscreen: tsc2004@4b {
- compatible = "ti,tsc2004";
- reg = <0x4b>;
-
- vio-supply = <&vdd_io_reg>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&tsc2004_pins>;
- interrupts-extended = <&gpio3 1 IRQ_TYPE_EDGE_RISING>; /* gpio_65 */
-
- touchscreen-fuzz-x = <4>;
- touchscreen-fuzz-y = <7>;
- touchscreen-fuzz-pressure = <2>;
- touchscreen-size-x = <480>;
- touchscreen-size-y = <272>;
- touchscreen-max-pressure = <2048>;
-
- ti,x-plate-ohms = <280>;
- ti,esd-recovery-timeout-ms = <8000>;
- };
-};
-
-&mmc2 {
- interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>;
-
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins>;
- vmmc-supply = <&wl12xx_vmmc2>;
- non-removable;
- bus-width = <4>;
- cap-power-off-card;
- #address-cells = <1>;
- #size-cells = <0>;
- wlcore: wlcore@2 {
- compatible = "ti,wl1271";
- reg = <2>;
- interrupt-parent = <&gpio6>;
- interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */
- ref-clock-frequency = <26000000>;
- tcxo-clock-frequency = <26000000>;
- };
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-
- bluetooth {
- compatible = "ti,wl1271-st";
- enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */
- max-speed = <3000000>;
- };
-};
-
-&omap3_pmx_core {
-
- wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */
- >;
- };
-
- mmc2_pins: pinmux_mmc2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */
- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */
- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */
- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */
- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */
- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */
- OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */
- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */
- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */
- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */
- OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */
- >;
- };
-
- rtc_pins: pinmux_rtc_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */
- >;
- };
-
- tsc2004_pins: pinmux_tsc2004_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */
- >;
- };
-
- uart2_pins: pinmux_uart2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */
- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
- OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */
- >;
- };
-};
-
-&omap3_pmx_wkup {
-
- wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins {
- pinctrl-single,pins = <
- OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
- >;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for am3517 SoC
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include "omap3.dtsi"
-
-/ {
- aliases {
- serial3 = &uart4;
- can = &hecc;
- };
-
- ocp@68000000 {
- am35x_otg_hs: am35x_otg_hs@5c040000 {
- compatible = "ti,omap3-musb";
- ti,hwmods = "am35x_otg_hs";
- status = "disabled";
- reg = <0x5c040000 0x1000>;
- interrupts = <71>;
- interrupt-names = "mc";
- };
-
- davinci_emac: ethernet@5c000000 {
- compatible = "ti,am3517-emac";
- ti,hwmods = "davinci_emac";
- status = "disabled";
- reg = <0x5c000000 0x30000>;
- interrupts = <67 68 69 70>;
- syscon = <&scm_conf>;
- ti,davinci-ctrl-reg-offset = <0x10000>;
- ti,davinci-ctrl-mod-reg-offset = <0>;
- ti,davinci-ctrl-ram-offset = <0x20000>;
- ti,davinci-ctrl-ram-size = <0x2000>;
- ti,davinci-rmii-en = /bits/ 8 <1>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- clocks = <&emac_ick>;
- clock-names = "ick";
- };
-
- davinci_mdio: mdio@5c030000 {
- compatible = "ti,davinci_mdio";
- ti,hwmods = "davinci_mdio";
- status = "disabled";
- reg = <0x5c030000 0x1000>;
- bus_freq = <1000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&emac_fck>;
- clock-names = "fck";
- };
-
- uart4: serial@4809e000 {
- compatible = "ti,omap3-uart";
- ti,hwmods = "uart4";
- status = "disabled";
- reg = <0x4809e000 0x400>;
- interrupts = <84>;
- dmas = <&sdma 55 &sdma 54>;
- dma-names = "tx", "rx";
- clock-frequency = <48000000>;
- };
-
- omap3_pmx_core2: pinmux@480025d8 {
- compatible = "ti,omap3-padconf", "pinctrl-single";
- reg = <0x480025d8 0x24>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0xff1f>;
- };
-
- hecc: can@5c050000 {
- compatible = "ti,am3517-hecc";
- status = "disabled";
- reg = <0x5c050000 0x80>,
- <0x5c053000 0x180>,
- <0x5c052000 0x200>;
- reg-names = "hecc", "hecc-ram", "mbx";
- interrupts = <24>;
- clocks = <&hecc_ck>;
- };
- };
-};
-
-/* Table Table 5-79 of the TRM shows 480ab000 is reserved */
-&usb_otg_hs {
- status = "disabled";
-};
-
-&iva {
- status = "disabled";
-};
-
-&mailbox {
- status = "disabled";
-};
-
-&mmu_isp {
- status = "disabled";
-};
-
-/include/ "am35xx-clocks.dtsi"
-/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP3 clock data
- *
- * Copyright (C) 2013 Texas Instruments, Inc.
- */
-&scm_clocks {
- emac_ick: emac_ick@32c {
- #clock-cells = <0>;
- compatible = "ti,am35xx-gate-clock";
- clocks = <&ipss_ick>;
- reg = <0x032c>;
- ti,bit-shift = <1>;
- };
-
- emac_fck: emac_fck@32c {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&rmii_ck>;
- reg = <0x032c>;
- ti,bit-shift = <9>;
- };
-
- vpfe_ick: vpfe_ick@32c {
- #clock-cells = <0>;
- compatible = "ti,am35xx-gate-clock";
- clocks = <&ipss_ick>;
- reg = <0x032c>;
- ti,bit-shift = <2>;
- };
-
- vpfe_fck: vpfe_fck@32c {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&pclk_ck>;
- reg = <0x032c>;
- ti,bit-shift = <10>;
- };
-
- hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c {
- #clock-cells = <0>;
- compatible = "ti,am35xx-gate-clock";
- clocks = <&ipss_ick>;
- reg = <0x032c>;
- ti,bit-shift = <0>;
- };
-
- hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_ck>;
- reg = <0x032c>;
- ti,bit-shift = <8>;
- };
-
- hecc_ck: hecc_ck@32c {
- #clock-cells = <0>;
- compatible = "ti,am35xx-gate-clock";
- clocks = <&sys_ck>;
- reg = <0x032c>;
- ti,bit-shift = <3>;
- };
-};
-&cm_clocks {
- ipss_ick: ipss_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,am35xx-interface-clock";
- clocks = <&core_l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <4>;
- };
-
- rmii_ck: rmii_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- pclk_ck: pclk_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <27000000>;
- };
-
- uart4_ick_am35xx: uart4_ick_am35xx@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <23>;
- };
-
- uart4_fck_am35xx: uart4_fck_am35xx@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <23>;
- };
-};
-
-&cm_clockdomains {
- core_l3_clkdm: core_l3_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
- <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
- <&hecc_ck>;
- };
-
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
- <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
- <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
- <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree for DA850 EVM board
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-#include "da850.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "ti,da850-evm", "ti,da850";
- model = "DA850/AM1808/OMAP-L138 EVM";
-
- chosen {
- stdout-path = &serial2;
- };
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- ethernet0 = ð0;
- spi0 = &spi1;
- };
-
- backlight: backlight-pwm {
- pinctrl-names = "default";
- pinctrl-0 = <&ecap2_pins>;
- power-supply = <&backlight_lcd>;
- compatible = "pwm-backlight";
- /*
- * The PWM here corresponds to production hardware. The
- * schematic needs to be 1015171 (15 March 2010), Rev A
- * or newer.
- */
- pwms = <&ecap2 0 50000 0>;
- brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
- default-brightness-level = <7>;
- };
-
- panel {
- compatible = "ti,tilcdc,panel";
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_pins>;
- /*
- * The vpif and the LCD are mutually exclusive.
- * To enable VPIF, change the status below to 'disabled' then
- * then change the status of the vpif below to 'okay'
- */
- status = "okay";
- enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */
-
- panel-info {
- ac-bias = <255>;
- ac-bias-intrpt = <0>;
- dma-burst-sz = <16>;
- bpp = <16>;
- fdd = <0x80>;
- sync-edge = <0>;
- sync-ctrl = <1>;
- raster-order = <0>;
- fifo-th = <0>;
- };
-
- display-timings {
- native-mode = <&timing0>;
- timing0: 480x272 {
- clock-frequency = <9000000>;
- hactive = <480>;
- vactive = <272>;
- hfront-porch = <3>;
- hback-porch = <2>;
- hsync-len = <42>;
- vback-porch = <3>;
- vfront-porch = <4>;
- vsync-len = <11>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
- };
- };
-
- vbat: fixedregulator0 {
- compatible = "regulator-fixed";
- regulator-name = "vbat";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- };
-
- baseboard_3v3: fixedregulator-3v3 {
- /* TPS73701DCQ */
- compatible = "regulator-fixed";
- regulator-name = "baseboard_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vbat>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- baseboard_1v8: fixedregulator-1v8 {
- /* TPS73701DCQ */
- compatible = "regulator-fixed";
- regulator-name = "baseboard_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vbat>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- backlight_lcd: backlight-regulator {
- compatible = "regulator-fixed";
- regulator-name = "lcd_backlight_pwr";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */
- enable-active-high;
- };
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "DA850-OMAPL138 EVM";
- simple-audio-card,widgets =
- "Line", "Line In",
- "Line", "Line Out";
- simple-audio-card,routing =
- "LINE1L", "Line In",
- "LINE1R", "Line In",
- "Line Out", "LLOUT",
- "Line Out", "RLOUT";
- simple-audio-card,format = "dsp_b";
- simple-audio-card,bitclock-master = <&link0_codec>;
- simple-audio-card,frame-master = <&link0_codec>;
- simple-audio-card,bitclock-inversion;
-
- simple-audio-card,cpu {
- sound-dai = <&mcasp0>;
- system-clock-frequency = <24576000>;
- };
-
- link0_codec: simple-audio-card,codec {
- sound-dai = <&tlv320aic3106>;
- system-clock-frequency = <24576000>;
- };
- };
-};
-
-&ecap2 {
- status = "okay";
-};
-
-&ref_clk {
- clock-frequency = <24000000>;
-};
-
-&pmx_core {
- status = "okay";
-
- mcasp0_pins: pinmux_mcasp0_pins {
- pinctrl-single,bits = <
- /*
- * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR,
- * AFSR, AMUTE
- */
- 0x00 0x11111111 0xffffffff
- /* AXR11, AXR12 */
- 0x04 0x00011000 0x000ff000
- >;
- };
- nand_pins: nand_pins {
- pinctrl-single,bits = <
- /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */
- 0x1c 0x10110110 0xf0ff0ff0
- /*
- * EMA_D[0], EMA_D[1], EMA_D[2],
- * EMA_D[3], EMA_D[4], EMA_D[5],
- * EMA_D[6], EMA_D[7]
- */
- 0x24 0x11111111 0xffffffff
- /* EMA_A[1], EMA_A[2] */
- 0x30 0x01100000 0x0ff00000
- >;
- };
-};
-
-&sata {
- status = "okay";
-};
-
-&serial0 {
- status = "okay";
-};
-
-&serial1 {
- status = "okay";
-};
-
-&serial2 {
- status = "okay";
-};
-
-&rtc0 {
- status = "okay";
-};
-
-&lcdc {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
-
- tps: tps@48 {
- reg = <0x48>;
- };
- tlv320aic3106: tlv320aic3106@18 {
- #sound-dai-cells = <0>;
- compatible = "ti,tlv320aic3106";
- reg = <0x18>;
- status = "okay";
-
- /* Regulators */
- IOVDD-supply = <&vdcdc2_reg>;
- AVDD-supply = <&baseboard_3v3>;
- DRVDD-supply = <&baseboard_3v3>;
- DVDD-supply = <&baseboard_1v8>;
- };
- tca6416: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
- tca6416_bb: gpio@21 {
- compatible = "ti,tca6416";
- reg = <0x21>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&wdt {
- status = "okay";
-};
-
-&mmc0 {
- max-frequency = <50000000>;
- bus-width = <4>;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins>;
- cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio 65 GPIO_ACTIVE_HIGH>;
-};
-
-&spi1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
- flash: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "m25p64";
- spi-max-frequency = <30000000>;
- m25p,fast-read;
- reg = <0>;
- partition@0 {
- label = "U-Boot-SPL";
- reg = <0x00000000 0x00010000>;
- read-only;
- };
- partition@1 {
- label = "U-Boot";
- reg = <0x00010000 0x00080000>;
- read-only;
- };
- partition@2 {
- label = "U-Boot-Env";
- reg = <0x00090000 0x00010000>;
- read-only;
- };
- partition@3 {
- label = "Kernel";
- reg = <0x000a0000 0x00280000>;
- };
- partition@4 {
- label = "Filesystem";
- reg = <0x00320000 0x00400000>;
- };
- partition@5 {
- label = "MAC-Address";
- reg = <0x007f0000 0x00010000>;
- read-only;
- };
- };
-};
-
-&mdio {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mdio_pins>;
- bus_freq = <2200000>;
-};
-
-ð0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mii_pins>;
-};
-
-&gpio {
- status = "okay";
-};
-
-/include/ "tps6507x.dtsi"
-
-&tps {
- vdcdc1_2-supply = <&vbat>;
- vdcdc3-supply = <&vbat>;
- vldo1_2-supply = <&vbat>;
-
- regulators {
- vdcdc1_reg: regulator@0 {
- regulator-name = "VDCDC1_3.3V";
- regulator-min-microvolt = <3150000>;
- regulator-max-microvolt = <3450000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdcdc2_reg: regulator@1 {
- regulator-name = "VDCDC2_3.3V";
- regulator-min-microvolt = <1710000>;
- regulator-max-microvolt = <3450000>;
- regulator-always-on;
- regulator-boot-on;
- ti,defdcdc_default = <1>;
- };
-
- vdcdc3_reg: regulator@2 {
- regulator-name = "VDCDC3_1.2V";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-boot-on;
- ti,defdcdc_default = <1>;
- };
-
- ldo1_reg: regulator@3 {
- regulator-name = "LDO1_1.8V";
- regulator-min-microvolt = <1710000>;
- regulator-max-microvolt = <1890000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo2_reg: regulator@4 {
- regulator-name = "LDO2_1.2V";
- regulator-min-microvolt = <1140000>;
- regulator-max-microvolt = <1320000>;
- regulator-always-on;
- regulator-boot-on;
- };
- };
-};
-
-&mcasp0 {
- #sound-dai-cells = <0>;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcasp0_pins>;
-
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
- /* 4 serializer */
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 0 0 0 0
- 0 0 0 0
- 0 0 0 1
- 2 0 0 0
- >;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
-};
-
-&edma0 {
- ti,edma-reserved-slot-ranges = <32 50>;
-};
-
-&edma1 {
- ti,edma-reserved-slot-ranges = <32 90>;
-};
-
-&aemif {
- pinctrl-names = "default";
- pinctrl-0 = <&nand_pins>;
- status = "okay";
- cs3 {
- #address-cells = <2>;
- #size-cells = <1>;
- clock-ranges;
- ranges;
-
- ti,cs-chipselect = <3>;
-
- nand@2000000,0 {
- compatible = "ti,davinci-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0x02000000 0x02000000
- 1 0x00000000 0x00008000>;
-
- ti,davinci-chipselect = <1>;
- ti,davinci-mask-ale = <0>;
- ti,davinci-mask-cle = <0>;
- ti,davinci-mask-chipsel = <0>;
- ti,davinci-ecc-mode = "hw";
- ti,davinci-ecc-bits = <4>;
- ti,davinci-nand-use-bbt;
- };
- };
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&vpif {
- pinctrl-names = "default";
- pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
- /*
- * The vpif and the LCD are mutually exclusive.
- * To enable VPIF, disable the ti,tilcdc,panel then
- * change the status below to 'okay'
- */
- status = "disabled";
-};
* Copyright (c) 2023 Linaro Ltd.
*/
-&cmu_top {
- bootph-all;
-};
-
-&cmu_peri {
- bootph-all;
-};
-
-&oscclk {
- bootph-all;
-};
-
-&pinctrl_alive {
- bootph-all;
-};
-
&pmu_system_controller {
bootph-all;
samsung,uart-debug-1;
};
-
-&serial_0 {
- bootph-all;
-};
-
-&uart1_pins {
- bootph-all;
-};
-
-&usi_uart {
- bootph-all;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * WinLink E850-96 board device tree source
- *
- * Copyright (C) 2018 Samsung Electronics Co., Ltd.
- * Copyright (C) 2021 Linaro Ltd.
- *
- * Device tree source file for WinLink's E850-96 board which is based on
- * Samsung Exynos850 SoC.
- */
-
-/dts-v1/;
-
-#include "exynos850.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "WinLink E850-96 board";
- compatible = "winlink,e850-96", "samsung,exynos850";
-
- aliases {
- mmc0 = &mmc_0;
- serial0 = &serial_0;
- };
-
- chosen {
- stdout-path = &serial_0;
- };
-
- connector {
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- label = "micro-USB";
- type = "micro";
- vbus-supply = <®_usb_host_vbus>;
- id-gpios = <&gpa0 0 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <µ_usb_det_pins>;
-
- port {
- usb_dr_connector: endpoint {
- remote-endpoint = <&usb1_drd_sw>;
- };
- };
- };
-
- /*
- * RAM: 4 GiB (eMCP):
- * - 2 GiB at 0x80000000
- * - 2 GiB at 0x880000000
- *
- * 0xbab00000..0xbfffffff: secure memory (85 MiB).
- */
- memory@80000000 {
- device_type = "memory";
- reg = <0x0 0x80000000 0x3ab00000>,
- <0x0 0xc0000000 0x40000000>,
- <0x8 0x80000000 0x80000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&key_voldown_pins &key_volup_pins>;
-
- volume-down-key {
- label = "Volume Down";
- linux,code = <KEY_VOLUMEDOWN>;
- gpios = <&gpa1 0 GPIO_ACTIVE_LOW>;
- };
-
- volume-up-key {
- label = "Volume Up";
- linux,code = <KEY_VOLUMEUP>;
- gpios = <&gpa0 7 GPIO_ACTIVE_LOW>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- /* HEART_BEAT_LED */
- user_led1: led-1 {
- label = "yellow:user1";
- gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_YELLOW>;
- function = LED_FUNCTION_HEARTBEAT;
- linux,default-trigger = "heartbeat";
- };
-
- /* eMMC_LED */
- user_led2: led-2 {
- label = "yellow:user2";
- gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_YELLOW>;
- linux,default-trigger = "mmc0";
- };
-
- /* SD_LED */
- user_led3: led-3 {
- label = "white:user3";
- gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_WHITE>;
- function = LED_FUNCTION_SD;
- linux,default-trigger = "mmc2";
- };
-
- /* WIFI_LED */
- wlan_active_led: led-4 {
- label = "yellow:wlan";
- gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_YELLOW>;
- function = LED_FUNCTION_WLAN;
- linux,default-trigger = "phy0tx";
- default-state = "off";
- };
-
- /* BLUETOOTH_LED */
- bt_active_led: led-5 {
- label = "blue:bt";
- gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_BLUETOOTH;
- linux,default-trigger = "hci0-power";
- default-state = "off";
- };
- };
-
- /* TODO: Remove this once PMIC is implemented */
- reg_dummy: regulator-0 {
- compatible = "regulator-fixed";
- regulator-name = "dummy_reg";
- };
-
- reg_usb_host_vbus: regulator-1 {
- compatible = "regulator-fixed";
- regulator-name = "usb_host_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpa3 5 GPIO_ACTIVE_LOW>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- ramoops@f0000000 {
- compatible = "ramoops";
- reg = <0x0 0xf0000000 0x200000>;
- record-size = <0x20000>;
- console-size = <0x20000>;
- ftrace-size = <0x100000>;
- pmsg-size = <0x20000>;
- };
- };
-
- /*
- * RTC clock (XrtcXTI); external, must be 32.768 kHz.
- *
- * TODO: Remove this once RTC clock is implemented properly as part of
- * PMIC driver.
- */
- rtcclk: clock-rtcclk {
- compatible = "fixed-clock";
- clock-output-names = "rtcclk";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
-};
-
-&cmu_hsi {
- clocks = <&oscclk>, <&rtcclk>,
- <&cmu_top CLK_DOUT_HSI_BUS>,
- <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
- <&cmu_top CLK_DOUT_HSI_USB20DRD>;
- clock-names = "oscclk", "rtcclk", "dout_hsi_bus",
- "dout_hsi_mmc_card", "dout_hsi_usb20drd";
-};
-
-&mmc_0 {
- status = "okay";
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- cap-mmc-highspeed;
- non-removable;
- mmc-hs400-enhanced-strobe;
- card-detect-delay = <200>;
- clock-frequency = <800000000>;
- bus-width = <8>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <0 4>;
- samsung,dw-mshc-ddr-timing = <2 4>;
- samsung,dw-mshc-hs400-timing = <0 2>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins
- &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>;
-};
-
-&oscclk {
- clock-frequency = <26000000>;
-};
-
-&pinctrl_alive {
- key_voldown_pins: key-voldown-pins {
- samsung,pins = "gpa1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- key_volup_pins: key-volup-pins {
- samsung,pins = "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- micro_usb_det_pins: micro-usb-det-pins {
- samsung,pins = "gpa0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-};
-
-&rtc {
- status = "okay";
- clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>;
- clock-names = "rtc", "rtc_src";
-};
-
-&serial_0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
-};
-
-&usbdrd {
- status = "okay";
- vdd10-supply = <®_dummy>;
- vdd33-supply = <®_dummy>;
-};
-
-&usbdrd_dwc3 {
- dr_mode = "otg";
- usb-role-switch;
- role-switch-default-mode = "host";
-
- port {
- usb1_drd_sw: endpoint {
- remote-endpoint = <&usb_dr_connector>;
- };
- };
-};
-
-&usbdrd_phy {
- status = "okay";
-};
-
-&usi_uart {
- samsung,clkreq-on; /* needed for UART mode */
- status = "okay";
-};
-
-&watchdog_cl0 {
- status = "okay";
-};
-
-&watchdog_cl1 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
- *
- * Copyright (C) 2017 Samsung Electronics Co., Ltd.
- * Copyright (C) 2021 Linaro Ltd.
- *
- * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
- * tree nodes in this file.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "exynos-pinctrl.h"
-
-&pinctrl_alive {
- gpa0: gpa0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpa1: gpa1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpa2: gpa2-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpa3: gpa3-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpa4: gpa4-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpq0: gpq0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- /* I2C5 (also called CAM_PMIC_I2C in TRM) */
- i2c5_pins: i2c5-pins {
- samsung,pins = "gpa3-5", "gpa3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* I2C6 (also called MOTOR_I2C in TRM) */
- i2c6_pins: i2c6-pins {
- samsung,pins = "gpa3-7", "gpa4-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI: UART_DEBUG_0 pins */
- uart0_pins: uart0-pins {
- samsung,pins = "gpq0-0", "gpq0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-
- /* USI: UART_DEBUG_1 pins */
- uart1_pins: uart1-pins {
- samsung,pins = "gpa3-7", "gpa4-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-};
-
-&pinctrl_cmgp {
- gpm0: gpm0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm1: gpm1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm2: gpm2-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm3: gpm3-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm4: gpm4-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm5: gpm5-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm6: gpm6-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpm7: gpm7-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- /* USI_CMGP0: HSI2C function */
- hsi2c3_pins: hsi2c3-pins {
- samsung,pins = "gpm0-0", "gpm1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */
- uart1_single_pins: uart1-single-pins {
- samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-
- /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */
- uart1_dual_pins: uart1-dual-pins {
- samsung,pins = "gpm0-0", "gpm1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-
- /* USI_CMGP0: SPI function */
- spi1_pins: spi1-pins {
- samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI_CMGP1: HSI2C function */
- hsi2c4_pins: hsi2c4-pins {
- samsung,pins = "gpm4-0", "gpm5-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */
- uart2_single_pins: uart2-single-pins {
- samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-
- /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */
- uart2_dual_pins: uart2-dual-pins {
- samsung,pins = "gpm4-0", "gpm5-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-
- /* USI_CMGP1: SPI function */
- spi2_pins: spi2-pins {
- samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-};
-
-&pinctrl_aud {
- gpb0: gpb0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpb1: gpb1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- aud_codec_mclk_pins: aud-codec-mclk-pins {
- samsung,pins = "gpb0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins {
- samsung,pins = "gpb0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_i2s0_pins: aud-i2s0-pins {
- samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_i2s0_idle_pins: aud-i2s0-idle-pins {
- samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_i2s1_pins: aud-i2s1-pins {
- samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_i2s1_idle_pins: aud-i2s1-idle-pins {
- samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_fm_pins: aud-fm-pins {
- samsung,pins = "gpb1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-
- aud_fm_idle_pins: aud-fm-idle-pins {
- samsung,pins = "gpb1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-};
-
-&pinctrl_hsi {
- gpf2: gpf2-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sd2_clk_pins: sd2-clk-pins {
- samsung,pins = "gpf2-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
- };
-
- sd2_cmd_pins: sd2-cmd-pins {
- samsung,pins = "gpf2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
- };
-
- sd2_bus1_pins: sd2-bus1-pins {
- samsung,pins = "gpf2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
- };
-
- sd2_bus4_pins: sd2-bus4-pins {
- samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
- };
-
- sd2_pdn_pins: sd2-pdn-pins {
- samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
- "gpf2-4", "gpf2-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- };
-};
-
-&pinctrl_core {
- gpf0: gpf0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpf1: gpf1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sd0_clk_pins: sd0-clk-pins {
- samsung,pins = "gpf0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-
- sd0_cmd_pins: sd0-cmd-pins {
- samsung,pins = "gpf0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-
- sd0_rdqs_pins: sd0-rdqs-pins {
- samsung,pins = "gpf0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-
- sd0_nreset_pins: sd0-nreset-pins {
- samsung,pins = "gpf0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-
- sd0_bus1_pins: sd0-bus1-pins {
- samsung,pins = "gpf1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-
- sd0_bus4_pins: sd0-bus4-pins {
- samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-
- sd0_bus8_pins: sd0-bus8-pins {
- samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
- };
-};
-
-&pinctrl_peri {
- gpc0: gpc0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpc1: gpc1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpg0: gpg0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpg1: gpg1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpg2: gpg2-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpg3: gpg3-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpp0: gpp0-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- gpp1: gpp1-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpp2: gpp2-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sensor_mclk0_in_pins: sensor-mclk0-in-pins {
- samsung,pins = "gpc0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk0_out_pins: sensor-mclk0-out-pins {
- samsung,pins = "gpc0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk0_fn_pins: sensor-mclk0-fn-pins {
- samsung,pins = "gpc0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk1_in_pins: sensor-mclk1-in-pins {
- samsung,pins = "gpc0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk1_out_pins: sensor-mclk1-out-pins {
- samsung,pins = "gpc0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk1_fn_pins: sensor-mclk1-fn-pins {
- samsung,pins = "gpc0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk2_in_pins: sensor-mclk2-in-pins {
- samsung,pins = "gpc0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk2_out_pins: sensor-mclk2-out-pins {
- samsung,pins = "gpc0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- sensor_mclk2_fn_pins: sensor-mclk2-fn-pins {
- samsung,pins = "gpc0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
- };
-
- /* USI: HSI2C0 */
- hsi2c0_pins: hsi2c0-pins {
- samsung,pins = "gpc1-0", "gpc1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI: HSI2C1 */
- hsi2c1_pins: hsi2c1-pins {
- samsung,pins = "gpc1-2", "gpc1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI: HSI2C2 */
- hsi2c2_pins: hsi2c2-pins {
- samsung,pins = "gpc1-4", "gpc1-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- /* USI: SPI */
- spi0_pins: spi0-pins {
- samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- i2c0_pins: i2c0-pins {
- samsung,pins = "gpp0-0", "gpp0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- i2c1_pins: i2c1-pins {
- samsung,pins = "gpp0-2", "gpp0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- i2c2_pins: i2c2-pins {
- samsung,pins = "gpp0-4", "gpp0-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- i2c3_pins: i2c3-pins {
- samsung,pins = "gpp1-0", "gpp1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- i2c4_pins: i2c4-pins {
- samsung,pins = "gpp1-2", "gpp1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
- };
-
- xclkout_pins: xclkout-pins {
- samsung,pins = "gpq0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Samsung Exynos850 SoC device tree source
- *
- * Copyright (C) 2018 Samsung Electronics Co., Ltd.
- * Copyright (C) 2021 Linaro Ltd.
- *
- * Samsung Exynos850 SoC device nodes are listed in this file.
- * Exynos850 based board files can include this file and provide
- * values for board specific bindings.
- */
-
-#include <dt-bindings/clock/exynos850.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/samsung,exynos-usi.h>
-
-/ {
- /* Also known under engineering name Exynos3830 */
- compatible = "samsung,exynos850";
- #address-cells = <2>;
- #size-cells = <1>;
-
- interrupt-parent = <&gic>;
-
- aliases {
- pinctrl0 = &pinctrl_alive;
- pinctrl1 = &pinctrl_cmgp;
- pinctrl2 = &pinctrl_aud;
- pinctrl3 = &pinctrl_hsi;
- pinctrl4 = &pinctrl_core;
- pinctrl5 = &pinctrl_peri;
- };
-
- arm-pmu {
- compatible = "arm,cortex-a55-pmu";
- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
- <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
- };
-
- /* Main system clock (XTCXO); external, must be 26 MHz */
- oscclk: clock-oscclk {
- compatible = "fixed-clock";
- clock-output-names = "oscclk";
- #clock-cells = <0>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
- core1 {
- cpu = <&cpu1>;
- };
- core2 {
- cpu = <&cpu2>;
- };
- core3 {
- cpu = <&cpu3>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&cpu4>;
- };
- core1 {
- cpu = <&cpu5>;
- };
- core2 {
- cpu = <&cpu6>;
- };
- core3 {
- cpu = <&cpu7>;
- };
- };
- };
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0>;
- enable-method = "psci";
- };
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x1>;
- enable-method = "psci";
- };
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x2>;
- enable-method = "psci";
- };
- cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x3>;
- enable-method = "psci";
- };
- cpu4: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x100>;
- enable-method = "psci";
- };
- cpu5: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x101>;
- enable-method = "psci";
- };
- cpu6: cpu@102 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x102>;
- enable-method = "psci";
- };
- cpu7: cpu@103 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x103>;
- enable-method = "psci";
- };
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- /* Hypervisor Virtual Timer interrupt is not wired to GIC */
- interrupts =
- <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- soc: soc@0 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x20000000>;
-
- chipid@10000000 {
- compatible = "samsung,exynos850-chipid";
- reg = <0x10000000 0x100>;
- };
-
- timer@10040000 {
- compatible = "samsung,exynos850-mct",
- "samsung,exynos4210-mct";
- reg = <0x10040000 0x800>;
- interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>;
- clock-names = "fin_pll", "mct";
- };
-
- gic: interrupt-controller@12a01000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- reg = <0x12a01000 0x1000>,
- <0x12a02000 0x2000>,
- <0x12a04000 0x2000>,
- <0x12a06000 0x2000>;
- interrupt-controller;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
- IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- pmu_system_controller: system-controller@11860000 {
- compatible = "samsung,exynos850-pmu", "syscon";
- reg = <0x11860000 0x10000>;
-
- reboot: syscon-reboot {
- compatible = "syscon-reboot";
- regmap = <&pmu_system_controller>;
- offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
- mask = <0x2>; /* SWRESET_SYSTEM */
- value = <0x2>; /* reset value */
- };
- };
-
- watchdog_cl0: watchdog@10050000 {
- compatible = "samsung,exynos850-wdt";
- reg = <0x10050000 0x100>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;
- clock-names = "watchdog", "watchdog_src";
- samsung,syscon-phandle = <&pmu_system_controller>;
- samsung,cluster-index = <0>;
- status = "disabled";
- };
-
- watchdog_cl1: watchdog@10060000 {
- compatible = "samsung,exynos850-wdt";
- reg = <0x10060000 0x100>;
- interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>;
- clock-names = "watchdog", "watchdog_src";
- samsung,syscon-phandle = <&pmu_system_controller>;
- samsung,cluster-index = <1>;
- status = "disabled";
- };
-
- cmu_peri: clock-controller@10030000 {
- compatible = "samsung,exynos850-cmu-peri";
- reg = <0x10030000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
- <&cmu_top CLK_DOUT_PERI_UART>,
- <&cmu_top CLK_DOUT_PERI_IP>;
- clock-names = "oscclk", "dout_peri_bus",
- "dout_peri_uart", "dout_peri_ip";
- };
-
- cmu_g3d: clock-controller@11400000 {
- compatible = "samsung,exynos850-cmu-g3d";
- reg = <0x11400000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
- clock-names = "oscclk", "dout_g3d_switch";
- };
-
- cmu_apm: clock-controller@11800000 {
- compatible = "samsung,exynos850-cmu-apm";
- reg = <0x11800000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
- clock-names = "oscclk", "dout_clkcmu_apm_bus";
- };
-
- cmu_cmgp: clock-controller@11c00000 {
- compatible = "samsung,exynos850-cmu-cmgp";
- reg = <0x11c00000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>;
- clock-names = "oscclk", "gout_clkcmu_cmgp_bus";
- };
-
- cmu_core: clock-controller@12000000 {
- compatible = "samsung,exynos850-cmu-core";
- reg = <0x12000000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
- <&cmu_top CLK_DOUT_CORE_CCI>,
- <&cmu_top CLK_DOUT_CORE_MMC_EMBD>,
- <&cmu_top CLK_DOUT_CORE_SSS>;
- clock-names = "oscclk", "dout_core_bus",
- "dout_core_cci", "dout_core_mmc_embd",
- "dout_core_sss";
- };
-
- cmu_top: clock-controller@120e0000 {
- compatible = "samsung,exynos850-cmu-top";
- reg = <0x120e0000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>;
- clock-names = "oscclk";
- };
-
- cmu_mfcmscl: clock-controller@12c00000 {
- compatible = "samsung,exynos850-cmu-mfcmscl";
- reg = <0x12c00000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>,
- <&cmu_top CLK_DOUT_MFCMSCL_MFC>,
- <&cmu_top CLK_DOUT_MFCMSCL_M2M>,
- <&cmu_top CLK_DOUT_MFCMSCL_MCSC>,
- <&cmu_top CLK_DOUT_MFCMSCL_JPEG>;
- clock-names = "oscclk", "dout_mfcmscl_mfc",
- "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc",
- "dout_mfcmscl_jpeg";
- };
-
- cmu_dpu: clock-controller@13000000 {
- compatible = "samsung,exynos850-cmu-dpu";
- reg = <0x13000000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>;
- clock-names = "oscclk", "dout_dpu";
- };
-
- cmu_hsi: clock-controller@13400000 {
- compatible = "samsung,exynos850-cmu-hsi";
- reg = <0x13400000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>,
- <&cmu_top CLK_DOUT_HSI_BUS>,
- <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
- <&cmu_top CLK_DOUT_HSI_USB20DRD>;
- clock-names = "oscclk", "dout_hsi_bus",
- "dout_hsi_mmc_card", "dout_hsi_usb20drd";
- };
-
- cmu_is: clock-controller@14500000 {
- compatible = "samsung,exynos850-cmu-is";
- reg = <0x14500000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>,
- <&cmu_top CLK_DOUT_IS_BUS>,
- <&cmu_top CLK_DOUT_IS_ITP>,
- <&cmu_top CLK_DOUT_IS_VRA>,
- <&cmu_top CLK_DOUT_IS_GDC>;
- clock-names = "oscclk", "dout_is_bus", "dout_is_itp",
- "dout_is_vra", "dout_is_gdc";
- };
-
- cmu_aud: clock-controller@14a00000 {
- compatible = "samsung,exynos850-cmu-aud";
- reg = <0x14a00000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>;
- clock-names = "oscclk", "dout_aud";
- };
-
- pinctrl_alive: pinctrl@11850000 {
- compatible = "samsung,exynos850-pinctrl";
- reg = <0x11850000 0x1000>;
-
- wakeup-interrupt-controller {
- compatible = "samsung,exynos850-wakeup-eint";
- };
- };
-
- pinctrl_cmgp: pinctrl@11c30000 {
- compatible = "samsung,exynos850-pinctrl";
- reg = <0x11c30000 0x1000>;
-
- wakeup-interrupt-controller {
- compatible = "samsung,exynos850-wakeup-eint";
- };
- };
-
- pinctrl_core: pinctrl@12070000 {
- compatible = "samsung,exynos850-pinctrl";
- reg = <0x12070000 0x1000>;
- interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pinctrl_hsi: pinctrl@13430000 {
- compatible = "samsung,exynos850-pinctrl";
- reg = <0x13430000 0x1000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pinctrl_peri: pinctrl@139b0000 {
- compatible = "samsung,exynos850-pinctrl";
- reg = <0x139b0000 0x1000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pinctrl_aud: pinctrl@14a60000 {
- compatible = "samsung,exynos850-pinctrl";
- reg = <0x14a60000 0x1000>;
- };
-
- rtc: rtc@11a30000 {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x11a30000 0x100>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>;
- clock-names = "rtc";
- status = "disabled";
- };
-
- mmc_0: mmc@12100000 {
- compatible = "samsung,exynos7-dw-mshc-smu";
- reg = <0x12100000 0x2000>;
- interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>,
- <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x40>;
- status = "disabled";
- };
-
- i2c_0: i2c@13830000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13830000 0x100>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- i2c_1: i2c@13840000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13840000 0x100>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- i2c_2: i2c@13850000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13850000 0x100>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- i2c_3: i2c@13860000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13860000 0x100>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- i2c_4: i2c@13870000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13870000 0x100>;
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- /* I2C_5 (also called CAM_PMIC_I2C in TRM) */
- i2c_5: i2c@13880000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13880000 0x100>;
- interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- /* I2C_6 (also called MOTOR_I2C in TRM) */
- i2c_6: i2c@13890000 {
- compatible = "samsung,s3c2440-i2c";
- reg = <0x13890000 0x100>;
- interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6_pins>;
- clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
- clock-names = "i2c";
- status = "disabled";
- };
-
- sysmmu_mfcmscl: sysmmu@12c50000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x12c50000 0x9000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "sysmmu";
- clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>;
- #iommu-cells = <0>;
- };
-
- sysmmu_dpu: sysmmu@130c0000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x130c0000 0x9000>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "sysmmu";
- clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>;
- #iommu-cells = <0>;
- };
-
- sysmmu_is0: sysmmu@14550000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x14550000 0x9000>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "sysmmu";
- clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>;
- #iommu-cells = <0>;
- };
-
- sysmmu_is1: sysmmu@14570000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x14570000 0x9000>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "sysmmu";
- clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>;
- #iommu-cells = <0>;
- };
-
- sysmmu_aud: sysmmu@14850000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x14850000 0x9000>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "sysmmu";
- clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>;
- #iommu-cells = <0>;
- };
-
- sysreg_peri: syscon@10020000 {
- compatible = "samsung,exynos850-peri-sysreg",
- "samsung,exynos850-sysreg", "syscon";
- reg = <0x10020000 0x10000>;
- clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>;
- };
-
- sysreg_cmgp: syscon@11c20000 {
- compatible = "samsung,exynos850-cmgp-sysreg",
- "samsung,exynos850-sysreg", "syscon";
- reg = <0x11c20000 0x10000>;
- clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
- };
-
- usbdrd: usb@13600000 {
- compatible = "samsung,exynos850-dwusb3";
- ranges = <0x0 0x13600000 0x10000>;
- clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>,
- <&cmu_hsi CLK_GOUT_USB_REF_CLK>;
- clock-names = "bus_early", "ref";
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
-
- usbdrd_dwc3: usb@0 {
- compatible = "snps,dwc3";
- reg = <0x0 0x10000>;
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usbdrd_phy 0>;
- phy-names = "usb2-phy";
- };
- };
-
- usbdrd_phy: phy@135d0000 {
- compatible = "samsung,exynos850-usbdrd-phy";
- reg = <0x135d0000 0x100>;
- clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>,
- <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>;
- clock-names = "phy", "ref";
- samsung,pmu-syscon = <&pmu_system_controller>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- usi_uart: usi@138200c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x138200c0 0x20>;
- samsung,sysreg = <&sysreg_peri 0x1010>;
- samsung,mode = <USI_V2_UART>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
- <&cmu_peri CLK_GOUT_UART_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
-
- serial_0: serial@13820000 {
- compatible = "samsung,exynos850-uart";
- reg = <0x13820000 0xc0>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
- <&cmu_peri CLK_GOUT_UART_IPCLK>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
- };
-
- usi_hsi2c_0: usi@138a00c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x138a00c0 0x20>;
- samsung,sysreg = <&sysreg_peri 0x1020>;
- samsung,mode = <USI_V2_I2C>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>,
- <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
-
- hsi2c_0: i2c@138a0000 {
- compatible = "samsung,exynosautov9-hsi2c";
- reg = <0x138a0000 0xc0>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c0_pins>;
- clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>,
- <&cmu_peri CLK_GOUT_HSI2C0_PCLK>;
- clock-names = "hsi2c", "hsi2c_pclk";
- status = "disabled";
- };
- };
-
- usi_hsi2c_1: usi@138b00c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x138b00c0 0x20>;
- samsung,sysreg = <&sysreg_peri 0x1030>;
- samsung,mode = <USI_V2_I2C>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>,
- <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
-
- hsi2c_1: i2c@138b0000 {
- compatible = "samsung,exynosautov9-hsi2c";
- reg = <0x138b0000 0xc0>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c1_pins>;
- clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>,
- <&cmu_peri CLK_GOUT_HSI2C1_PCLK>;
- clock-names = "hsi2c", "hsi2c_pclk";
- status = "disabled";
- };
- };
-
- usi_hsi2c_2: usi@138c00c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x138c00c0 0x20>;
- samsung,sysreg = <&sysreg_peri 0x1040>;
- samsung,mode = <USI_V2_I2C>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>,
- <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
-
- hsi2c_2: i2c@138c0000 {
- compatible = "samsung,exynosautov9-hsi2c";
- reg = <0x138c0000 0xc0>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c2_pins>;
- clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>,
- <&cmu_peri CLK_GOUT_HSI2C2_PCLK>;
- clock-names = "hsi2c", "hsi2c_pclk";
- status = "disabled";
- };
- };
-
- usi_spi_0: usi@139400c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x139400c0 0x20>;
- samsung,sysreg = <&sysreg_peri 0x1050>;
- samsung,mode = <USI_V2_SPI>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
- <&cmu_peri CLK_GOUT_SPI0_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
- };
-
- usi_cmgp0: usi@11d000c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x11d000c0 0x20>;
- samsung,sysreg = <&sysreg_cmgp 0x2000>;
- samsung,mode = <USI_V2_I2C>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
- <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
-
- hsi2c_3: i2c@11d00000 {
- compatible = "samsung,exynosautov9-hsi2c";
- reg = <0x11d00000 0xc0>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c3_pins>;
- clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>,
- <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>;
- clock-names = "hsi2c", "hsi2c_pclk";
- status = "disabled";
- };
-
- serial_1: serial@11d00000 {
- compatible = "samsung,exynos850-uart";
- reg = <0x11d00000 0xc0>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_single_pins>;
- clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
- <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
- };
-
- usi_cmgp1: usi@11d200c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x11d200c0 0x20>;
- samsung,sysreg = <&sysreg_cmgp 0x2010>;
- samsung,mode = <USI_V2_I2C>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
- <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
- clock-names = "pclk", "ipclk";
- status = "disabled";
-
- hsi2c_4: i2c@11d20000 {
- compatible = "samsung,exynosautov9-hsi2c";
- reg = <0x11d20000 0xc0>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c4_pins>;
- clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>,
- <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>;
- clock-names = "hsi2c", "hsi2c_pclk";
- status = "disabled";
- };
-
- serial_2: serial@11d20000 {
- compatible = "samsung,exynos850-uart";
- reg = <0x11d20000 0xc0>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_single_pins>;
- clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
- <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
- };
- };
-};
-
-#include "exynos850-pinctrl.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2022 PHYTEC Messtechnik GmbH
- * Author: Teresa Remmet <t.remmet@phytec.de>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-#include "imx8mm-phycore-som.dtsi"
-
-/ {
- model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
- compatible = "phytec,imx8mm-phyboard-polis-rdk",
- "phytec,imx8mm-phycore-som", "fsl,imx8mm";
-
- chosen {
- stdout-path = &uart3;
- };
-
- bt_osc_32k: bt-lp-clock {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "bt_osc_32k";
- #clock-cells = <0>;
- };
-
- can_osc_40m: can-clock {
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- clock-output-names = "can_osc_40m";
- #clock-cells = <0>;
- };
-
- fan {
- compatible = "gpio-fan";
- gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = <0 0
- 13000 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fan>;
- #cooling-cells = <2>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_leds>;
-
- led-0 {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_DISK;
- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc2";
- };
-
- led-1 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_DISK;
- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc1";
- };
-
- led-2 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_CPU;
- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- usdhc1_pwrseq: pwr-seq {
- compatible = "mmc-pwrseq-simple";
- post-power-on-delay-ms = <100>;
- power-off-delay-us = <60>;
- reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
- };
-
- reg_can_en: regulator-can-en {
- compatible = "regulator-fixed";
- gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can_en>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "CAN_EN";
- startup-delay-us = <20>;
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1 {
- compatible = "regulator-fixed";
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
- regulator-name = "usb_otg1_vbus";
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- off-on-delay-us = <20000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "VSD_3V3";
- };
-
- reg_vcc_3v3: regulator-vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "VCC_3V3";
- };
-};
-
-/* SPI - CAN MCP251XFD */
-&ecspi1 {
- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- status = "okay";
-
- can0: can@0 {
- compatible = "microchip,mcp251xfd";
- clocks = <&can_osc_40m>;
- interrupt-parent = <&gpio1>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can_int>;
- reg = <0>;
- spi-max-frequency = <20000000>;
- xceiver-supply = <®_can_en>;
- };
-};
-
-&gpio1 {
- gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
- "", "", "", "RESET_ETHPHY",
- "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
- "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
-};
-
-&gpio2 {
- gpio-line-names = "", "", "", "",
- "", "", "BT_REG_ON", "WL_REG_ON",
- "BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
- "X_SD2_CD_B", "", "", "",
- "", "", "", "SD2_RESET_B";
-};
-
-&gpio4 {
- gpio-line-names = "", "", "", "",
- "", "", "", "",
- "FAN", "miniPCIe_nPERST", "", "",
- "COEX1", "COEX2";
-};
-
-&gpio5 {
- gpio-line-names = "", "", "", "",
- "", "", "", "",
- "", "ECSPI1_SS0";
-};
-
-&i2c4 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
-};
-
-/* PCIe */
-&pcie0 {
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- assigned-clock-rates = <10000000>, <250000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&pcie_phy {
- clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
- fsl,clkreq-unsupported;
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
- fsl,tx-deemph-gen1 = <0x2d>;
- fsl,tx-deemph-gen2 = <0xf>;
- status = "okay";
-};
-
-&rv3028 {
- trickle-resistor-ohms = <3000>;
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-/* UART - RS232/RS485 */
-&uart1 {
- assigned-clocks = <&clk IMX8MM_CLK_UART1>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- uart-has-rtscts;
- status = "okay";
-};
-
-/* UART - Sterling-LWB Bluetooth */
-&uart2 {
- assigned-clocks = <&clk IMX8MM_CLK_UART2>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
- fsl,dte-mode;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2_bt>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- clocks = <&bt_osc_32k>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
- interrupt-names = "host-wakeup";
- interrupt-parent = <&gpio2>;
- interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
- max-speed = <2000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_bt>;
- shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
- vddio-supply = <®_vcc_3v3>;
- };
-};
-
-/* UART - console */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-/* USB */
-&usbotg1 {
- adp-disable;
- dr_mode = "otg";
- over-current-active-low;
- samsung,picophy-pre-emp-curr-control = <3>;
- samsung,picophy-dc-vol-level-adjust = <7>;
- srp-disable;
- vbus-supply = <®_usb_otg1_vbus>;
- status = "okay";
-};
-
-&usbotg2 {
- disable-over-current;
- dr_mode = "host";
- samsung,picophy-pre-emp-curr-control = <3>;
- samsung,picophy-dc-vol-level-adjust = <7>;
- status = "okay";
-};
-
-/* SDIO - Sterling-LWB Wifi */
-&usdhc1 {
- assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
- assigned-clock-rates = <200000000>;
- bus-width = <4>;
- mmc-pwrseq = <&usdhc1_pwrseq>;
- non-removable;
- no-1-8-v;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- };
-};
-
-/* SD-Card */
-&usdhc2 {
- assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
- assigned-clock-rates = <200000000>;
- bus-width = <4>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- vmmc-supply = <®_usdhc2_vmmc>;
- vqmmc-supply = <®_nvcc_sd2>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_bt: btgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
- MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
- MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
- >;
- };
-
- pinctrl_can_en: can-engrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
- >;
- };
-
- pinctrl_can_int: can-intgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
- >;
- };
-
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
- MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
- MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
- >;
- };
-
- pinctrl_fan: fan0grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
- >;
- };
-
- pinctrl_leds: leds1grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
- >;
- };
-
- pinctrl_pcie: pciegrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
- MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
- MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
- MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
- MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
- MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
- >;
- };
-
- pinctrl_uart2_bt: uart2btgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
- MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
- MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
- MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
- >;
- };
-
- pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- >;
- };
-
- pinctrl_wlan: wlangrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00
- >;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2022 PHYTEC Messtechnik GmbH
- * Author: Teresa Remmet <t.remmet@phytec.de>
- */
-
-#include "imx8mm.dtsi"
-#include <dt-bindings/net/ti-dp83867.h>
-
-/ {
- model = "PHYTEC phyCORE-i.MX8MM";
- compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
-
- aliases {
- rtc0 = &rv3028;
- rtc1 = &snvs_rtc;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-
- reg_vdd_3v3_s: regulator-vdd-3v3-s {
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "VDD_3V3_S";
- };
-};
-
-&A53_0 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&A53_1 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&A53_2 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&A53_3 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25000000 {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-750000000 {
- opp-hz = /bits/ 64 <750000000>;
- };
- };
-};
-
-/* Ethernet */
-&fec1 {
- fsl,magic-packet;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- enet-phy-lane-no-swap;
- ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- reg = <0>;
- reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- reset-assert-us = <1000>;
- reset-deassert-us = <1000>;
- };
- };
-};
-
-/* SPI Flash */
-&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi0>;
- status = "okay";
-
- som_flash: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <80000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <1>;
- };
-};
-
-&gpio1 {
- gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT",
- "", "", "", "RESET_ETHPHY",
- "", "", "nENABLE_FLATLINK";
-};
-
-/* I2C1 */
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default","gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- pmic@8 {
- compatible = "nxp,pf8121a";
- reg = <0x08>;
-
- regulators {
- reg_nvcc_sd1: ldo1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "NVCC_SD1 (LDO1)";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- reg_nvcc_sd2: ldo2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "NVCC_SD2 (LDO2)";
- vselect-en;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- reg_vcc_enet: ldo3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <2500000>;
- regulator-min-microvolt = <1500000>;
- regulator-name = "VCC_ENET_2V5 (LDO3)";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- reg_vdda_1v8: ldo4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1500000>;
- regulator-name = "VDDA_1V8 (LDO4)";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-min-microvolt = <1500000>;
- regulator-suspend-max-microvolt = <1500000>;
- };
- };
-
- reg_soc_vdda_phy: buck1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <900000>;
- regulator-min-microvolt = <400000>;
- regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-min-microvolt = <400000>;
- regulator-suspend-max-microvolt = <400000>;
- };
- };
-
- reg_vdd_gpu_dram: buck2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1000000>;
- regulator-min-microvolt = <1000000>;
- regulator-name = "VDD_GPU_DRAM (BUCK2)";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-max-microvolt = <1000000>;
- regulator-suspend-min-microvolt = <1000000>;
- };
- };
-
- reg_vdd_gpu: buck3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1000000>;
- regulator-min-microvolt = <400000>;
- regulator-name = "VDD_VPU (BUCK3)";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- reg_vdd_mipi: buck4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1050000>;
- regulator-min-microvolt = <900000>;
- regulator-name = "VDD_MIPI_0P9 (BUCK4)";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- reg_vdd_arm: buck5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1050000>;
- regulator-min-microvolt = <400000>;
- regulator-name = "VDD_ARM (BUCK5)";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- reg_vdd_1v8: buck6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "VDD_1V8 (BUCK6)";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-max-microvolt = <1800000>;
- regulator-suspend-min-microvolt = <1800000>;
- };
- };
-
- reg_nvcc_dram: buck7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1100000>;
- regulator-min-microvolt = <1100000>;
- regulator-name = "NVCC_DRAM_1P1V (BUCK7)";
- };
-
- reg_vsnvs: vsnvs {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "NVCC_SNVS_1P8 (VSNVS)";
- };
- };
- };
-
- sn65dsi83: bridge@2d {
- compatible = "ti,sn65dsi83";
- enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sn65dsi83>;
- reg = <0x2d>;
- status = "disabled";
- };
-
- eeprom@51 {
- compatible = "atmel,24c32";
- pagesize = <32>;
- reg = <0x51>;
- vcc-supply = <®_vdd_3v3_s>;
- };
-
- rv3028: rtc@52 {
- compatible = "microcrystal,rv3028";
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rtc>;
- reg = <0x52>;
- };
-};
-
-/* EMMC */
-&usdhc3 {
- assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
- assigned-clock-rates = <400000000>;
- bus-width = <8>;
- keep-power-in-suspend;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- non-removable;
- status = "okay";
-};
-
-/* Watchdog */
-&wdog1 {
- fsl,ext-reset-output;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2
- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2
- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10
- >;
- };
-
- pinctrl_flexspi0: flexspi0grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
- MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
- MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
- MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
- MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
- MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0
- MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0
- >;
- };
-
- pinctrl_rtc: rtcgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
- >;
- };
-
- pinctrl_sn65dsi83: sn65dsi83grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26
- >;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2023 PHYTEC Messtechnik GmbH
- */
-
-/dts-v1/;
-
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/leds/common.h>
-#include "imx8mm-phycore-som.dtsi"
-
-/ {
- model = "PHYTEC phyGATE-Tauri-L-iMX8MM";
- compatible = "phytec,imx8mm-phygate-tauri-l",
- "phytec,imx8mm-phycore-som", "fsl,imx8mm";
-
- chosen {
- stdout-path = &uart3;
- };
-
- can_osc_40m: clock-can {
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- clock-output-names = "can_osc_40m";
- #clock-cells = <0>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpiokeys>;
-
- key {
- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
- label = "KEY-A";
- linux,code = <KEY_A>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_leds>;
-
- led-1 {
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "none";
- };
-
- led-2 {
- color = <LED_COLOR_ID_YELLOW>;
- gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "none";
- };
- };
-
- usdhc1_pwrseq: pwr-seq {
- compatible = "mmc-pwrseq-simple";
- post-power-on-delay-ms = <100>;
- power-off-delay-us = <60>;
- reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
- };
-
- reg_usb_hub_vbus: regulator-hub-otg1 {
- compatible = "regulator-fixed";
- gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbhubpwr>;
- regulator-name = "usb_hub_vbus";
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1 {
- compatible = "regulator-fixed";
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1pwr>;
- regulator-name = "usb_otg1_vbus";
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- off-on-delay-us = <20000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "VSD_3V3";
- };
-};
-
-&ecspi1 {
- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
- <&gpio5 13 GPIO_ACTIVE_LOW>,
- <&gpio5 2 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- /* CAN MCP251XFD */
- can0: can@0 {
- compatible = "microchip,mcp251xfd";
- reg = <0>;
- clocks = <&can_osc_40m>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can_int>;
- spi-max-frequency = <10000000>;
- };
-
- tpm: tpm@1 {
- compatible = "tcg,tpm_tis-spi";
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tpm>;
- reg = <1>;
- spi-max-frequency = <38000000>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- temp_sense0: temperature-sensor@49 {
- compatible = "ti,tmp102";
- reg = <0x49>;
- interrupt-parent = <&gpio4>;
- interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tempsense>;
- #thermal-sensor-cells = <1>;
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- pinctrl-1 = <&pinctrl_i2c4_gpio>;
- scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-/* PCIe */
-&pcie0 {
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_PHY>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_100M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- assigned-clock-rates = <10000000>, <100000000>, <250000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1>;
- status = "okay";
-};
-
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm3>;
- status = "okay";
-};
-
-&pwm4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm4>;
- status = "okay";
-};
-
-/* RTC */
-&rv3028 {
- trickle-resistor-ohms = <3000>;
-};
-
-&uart1 {
- assigned-clocks = <&clk IMX8MM_CLK_UART1>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* UART2 - RS232 */
-&uart2 {
- assigned-clocks = <&clk IMX8MM_CLK_UART2>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-/* UART - console */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-/* USB */
-&usbotg1 {
- adp-disable;
- dr_mode = "otg";
- over-current-active-low;
- samsung,picophy-pre-emp-curr-control = <3>;
- samsung,picophy-dc-vol-level-adjust = <7>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1>;
- srp-disable;
- vbus-supply = <®_usb_otg1_vbus>;
- status = "okay";
-};
-
-&usbotg2 {
- disable-over-current;
- dr_mode = "host";
- samsung,picophy-pre-emp-curr-control = <3>;
- samsung,picophy-dc-vol-level-adjust = <7>;
- vbus-supply = <®_usb_hub_vbus>;
- status = "okay";
-};
-
-/* SD-Card */
-&usdhc2 {
- assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
- assigned-clock-rates = <200000000>;
- bus-width = <4>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- vmmc-supply = <®_usdhc2_vmmc>;
- vqmmc-supply = <®_nvcc_sd2>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_can_int: can-intgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
- >;
- };
-
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
- MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
- MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
- >;
- };
-
- pinctrl_ecspi1_cs: ecspi1csgrp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00
- MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00
- >;
- };
-
- pinctrl_gpiokeys: keygrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0
- MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0
- >;
- };
-
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0
- MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c4_gpio: i2c4gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0
- MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0
- >;
- };
-
- pinctrl_leds: leds1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00
- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00
- >;
- };
-
- pinctrl_pcie: pciegrp {
- fsl,pins = <
- /* COEX2 */
- MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00
- /* COEX1 */
- MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
- >;
- };
-
- pinctrl_pwm1: pwm1grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40
- >;
- };
-
- pinctrl_pwm3: pwm3grp {
- fsl,pins = <
- MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40
- >;
- };
-
- pinctrl_pwm4: pwm4grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
- >;
- };
-
- pinctrl_tempsense: tempsensegrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00
- >;
- };
-
- pinctrl_tpm: tpmgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00
- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
- >;
- };
-
- pinctrl_usbhubpwr: usbhubpwrgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00
- >;
- };
-
- pinctrl_usbotg1pwr: usbotg1pwrgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
- >;
- };
-
- pinctrl_usbotg1: usbotg1grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- >;
- };
-};
};
#endif
- nxp-imx8mimage {
- filename = "u-boot-spl-mkimage.bin";
- nxp,boot-from = "sd";
- nxp,rom-version = <1>;
+#ifdef CONFIG_IMX_HAB
+ nxp-imx8mcst@0 {
+ filename = "u-boot-spl-mkimage.signed.bin";
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ nxp,unlock;
args; /* Needed by mkimage etype superclass */
+#endif
- section {
- align = <4>;
- align-size = <4>;
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
-
- u-boot-spl {
- align-end = <4>;
- filename = "u-boot-spl.bin";
- };
+ binman_imx_spl: nxp-imx8mimage {
+ filename = "u-boot-spl-mkimage.bin";
+ nxp,boot-from = "sd";
+ nxp,rom-version = <1>;
+ nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ args; /* Needed by mkimage etype superclass */
+
+ section {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-1d-imem-fw {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-1d-dmem-fw {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-2d-imem-fw {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
+ ddr-2d-dmem-fw {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
- fit {
- description = "Configuration to load ATF before U-Boot";
-#ifndef CONFIG_IMX_HAB
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-#endif
- fit,fdt-list = "of-list";
- #address-cells = <1>;
+ nxp-imx8mcst@1 {
+ filename = "u-boot-fit.signed.bin";
+ nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
#ifdef CONFIG_FSPI_CONF_HEADER
offset = <0x58C00>;
#else
offset = <0x57c00>;
#endif
- images {
- uboot {
- arch = "arm64";
- compression = "none";
- description = "U-Boot (64-bit)";
- load = <CONFIG_TEXT_BASE>;
- type = "standalone";
+ args; /* Needed by mkimage etype superclass */
+#endif
- uboot-blob {
- filename = "u-boot-nodtb.bin";
- type = "blob-ext";
+ binman_imx_fit: fit {
+ description = "Configuration to load ATF before U-Boot";
+#ifndef CONFIG_IMX_HAB
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+#endif
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+#ifdef CONFIG_FSPI_CONF_HEADER
+ offset = <0x58C00>;
+#else
+ offset = <0x57c00>;
+#endif
+
+ images {
+ uboot {
+ arch = "arm64";
+ compression = "none";
+ description = "U-Boot (64-bit)";
+ load = <CONFIG_TEXT_BASE>;
+ type = "standalone";
+
+ uboot-blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
};
- };
#ifndef CONFIG_ARMV8_PSCI
- atf {
- arch = "arm64";
- compression = "none";
- description = "ARM Trusted Firmware";
- entry = <0x920000>;
- load = <0x920000>;
- type = "firmware";
-
- atf-blob {
- filename = "bl31.bin";
- type = "atf-bl31";
+ atf {
+ arch = "arm64";
+ compression = "none";
+ description = "ARM Trusted Firmware";
+ entry = <0x920000>;
+ load = <0x920000>;
+ type = "firmware";
+
+ atf-blob {
+ filename = "bl31.bin";
+ type = "atf-bl31";
+ };
};
- };
#endif
- binman_fip: fip {
- arch = "arm64";
- compression = "none";
- description = "Trusted Firmware FIP";
- load = <0x40310000>;
- type = "firmware";
- };
+ binman_fip: fip {
+ arch = "arm64";
+ compression = "none";
+ description = "Trusted Firmware FIP";
+ load = <0x40310000>;
+ type = "firmware";
+ };
- @fdt-SEQ {
- compression = "none";
- description = "NAME";
- type = "flat_dt";
+ @fdt-SEQ {
+ compression = "none";
+ description = "NAME";
+ type = "flat_dt";
- uboot-fdt-blob {
- filename = "u-boot.dtb";
- type = "blob-ext";
+ uboot-fdt-blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
};
};
- };
- configurations {
- default = "@config-DEFAULT-SEQ";
+ configurations {
+ default = "@config-DEFAULT-SEQ";
- @config-SEQ {
- description = "NAME";
- fdt = "fdt-SEQ";
- firmware = "uboot";
+ @config-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
- loadables = "atf";
+ loadables = "atf";
#endif
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
+#endif
};
};
bootph-pre-ram;
};
-&binman {
- section {
- fit {
- offset = <0x5fc00>;
- };
- };
+&binman_imx_fit {
+ offset = <0x5fc00>;
};
&gpio1 {
};
#endif
- nxp-imx8mimage {
- filename = "u-boot-spl-mkimage.bin";
- nxp,boot-from = "sd";
- nxp,rom-version = <2>;
+#ifdef CONFIG_IMX_HAB
+ nxp-imx8mcst@0 {
+ filename = "u-boot-spl-mkimage.signed.bin";
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ nxp,unlock;
args; /* Needed by mkimage etype superclass */
+#endif
- section {
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
- align-size = <4>;
- align = <4>;
-
- u-boot-spl {
- align-end = <4>;
- filename = "u-boot-spl.bin";
- };
+ binman_imx_spl: nxp-imx8mimage {
+ filename = "u-boot-spl-mkimage.bin";
+ nxp,boot-from = "sd";
+ nxp,rom-version = <2>;
+ nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ args; /* Needed by mkimage etype superclass */
+
+ section {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
- ddr-1d-imem-fw {
+ ddr-1d-imem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
- filename = "lpddr4_pmu_train_1d_imem.bin";
+ filename = "lpddr4_pmu_train_1d_imem.bin";
#elif CONFIG_IMX8M_DDR4
- filename = "ddr4_imem_1d_201810.bin";
+ filename = "ddr4_imem_1d_201810.bin";
#else
- filename = "ddr3_imem_1d.bin";
+ filename = "ddr3_imem_1d.bin";
#endif
- type = "blob-ext";
- align-end = <4>;
- };
+ type = "blob-ext";
+ align-end = <4>;
+ };
- ddr-1d-dmem-fw {
+ ddr-1d-dmem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
- filename = "lpddr4_pmu_train_1d_dmem.bin";
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
#elif CONFIG_IMX8M_DDR4
- filename = "ddr4_dmem_1d_201810.bin";
+ filename = "ddr4_dmem_1d_201810.bin";
#else
- filename = "ddr3_dmem_1d.bin";
+ filename = "ddr3_dmem_1d.bin";
#endif
- type = "blob-ext";
- align-end = <4>;
- };
+ type = "blob-ext";
+ align-end = <4>;
+ };
#if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4)
- ddr-2d-imem-fw {
+ ddr-2d-imem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
- filename = "lpddr4_pmu_train_2d_imem.bin";
+ filename = "lpddr4_pmu_train_2d_imem.bin";
#else
- filename = "ddr4_imem_2d_201810.bin";
+ filename = "ddr4_imem_2d_201810.bin";
#endif
- type = "blob-ext";
- align-end = <4>;
- };
+ type = "blob-ext";
+ align-end = <4>;
+ };
- ddr-2d-dmem-fw {
+ ddr-2d-dmem-fw {
#ifdef CONFIG_IMX8M_LPDDR4
- filename = "lpddr4_pmu_train_2d_dmem.bin";
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
#else
- filename = "ddr4_dmem_2d_201810.bin";
+ filename = "ddr4_dmem_2d_201810.bin";
#endif
- type = "blob-ext";
- align-end = <4>;
- };
+ type = "blob-ext";
+ align-end = <4>;
+ };
#endif
+ };
};
+
+#ifdef CONFIG_IMX_HAB
};
- fit {
- description = "Configuration to load ATF before U-Boot";
-#ifndef CONFIG_IMX_HAB
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-#endif
- fit,fdt-list = "of-list";
- #address-cells = <1>;
+ nxp-imx8mcst@1 {
+ filename = "u-boot-fit.signed.bin";
+ nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
#ifdef CONFIG_FSPI_CONF_HEADER
offset = <0x59000>;
#else
offset = <0x58000>;
#endif
+ args; /* Needed by mkimage etype superclass */
+#endif
- images {
- uboot {
- arch = "arm64";
- compression = "none";
- description = "U-Boot (64-bit)";
- load = <CONFIG_TEXT_BASE>;
- type = "standalone";
+ binman_imx_fit: fit {
+ description = "Configuration to load ATF before U-Boot";
+#ifndef CONFIG_IMX_HAB
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+#endif
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+#ifdef CONFIG_FSPI_CONF_HEADER
+ offset = <0x59000>;
+#else
+ offset = <0x58000>;
+#endif
- uboot-blob {
- filename = "u-boot-nodtb.bin";
- type = "blob-ext";
+ images {
+ uboot {
+ arch = "arm64";
+ compression = "none";
+ description = "U-Boot (64-bit)";
+ load = <CONFIG_TEXT_BASE>;
+ type = "standalone";
+
+ uboot-blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
};
- };
#ifndef CONFIG_ARMV8_PSCI
- atf {
- arch = "arm64";
- compression = "none";
- description = "ARM Trusted Firmware";
- entry = <0x960000>;
- load = <0x960000>;
- type = "firmware";
-
- atf-blob {
- filename = "bl31.bin";
- type = "atf-bl31";
+ atf {
+ arch = "arm64";
+ compression = "none";
+ description = "ARM Trusted Firmware";
+ entry = <0x960000>;
+ load = <0x960000>;
+ type = "firmware";
+
+ atf-blob {
+ filename = "bl31.bin";
+ type = "atf-bl31";
+ };
};
- };
#endif
- binman_fip: fip {
- arch = "arm64";
- compression = "none";
- description = "Trusted Firmware FIP";
- load = <0x40310000>;
- type = "firmware";
- };
+ binman_fip: fip {
+ arch = "arm64";
+ compression = "none";
+ description = "Trusted Firmware FIP";
+ load = <0x40310000>;
+ type = "firmware";
+ };
- @fdt-SEQ {
- compression = "none";
- description = "NAME";
- type = "flat_dt";
+ @fdt-SEQ {
+ compression = "none";
+ description = "NAME";
+ type = "flat_dt";
- uboot-fdt-blob {
- filename = "u-boot.dtb";
- type = "blob-ext";
+ uboot-fdt-blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
};
};
- };
- configurations {
- default = "@config-DEFAULT-SEQ";
+ configurations {
+ default = "@config-DEFAULT-SEQ";
- @config-SEQ {
- description = "NAME";
- fdt = "fdt-SEQ";
- firmware = "uboot";
+ @config-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
- loadables = "atf";
+ loadables = "atf";
#endif
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
+#endif
};
};
bootph-pre-ram;
};
-&binman {
- section {
- fit {
- images {
- fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast {
- description = "imx8mp-dhcom-som-overlay-eth1xfast";
- type = "flat_dt";
- compression = "none";
-
- blob-ext {
- filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo";
- };
- };
-
- fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast {
- description = "imx8mp-dhcom-som-overlay-eth2xfast";
- type = "flat_dt";
- compression = "none";
-
- blob-ext {
- filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo";
- };
- };
-
- fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast {
- description = "imx8mp-dhcom-pdk-overlay-eth2xfast";
- type = "flat_dt";
- compression = "none";
-
- blob-ext {
- filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo";
- };
- };
-
- fdt-dto-imx8mp-dhcom-som-overlay-rev100 {
- description = "imx8mp-dhcom-som-overlay-rev100";
- type = "flat_dt";
- compression = "none";
-
- blob-ext {
- filename = "imx8mp-dhcom-som-overlay-rev100.dtbo";
- };
- };
-
- fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 {
- description = "imx8mp-dhcom-pdk3-overlay-rev100";
- type = "flat_dt";
- compression = "none";
-
- blob-ext {
- filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo";
- };
- };
+&binman_imx_fit {
+ images {
+ fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast {
+ description = "imx8mp-dhcom-som-overlay-eth1xfast";
+ type = "flat_dt";
+ compression = "none";
+
+ blob-ext {
+ filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo";
};
+ };
+
+ fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast {
+ description = "imx8mp-dhcom-som-overlay-eth2xfast";
+ type = "flat_dt";
+ compression = "none";
+
+ blob-ext {
+ filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo";
+ };
+ };
+
+ fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast {
+ description = "imx8mp-dhcom-pdk-overlay-eth2xfast";
+ type = "flat_dt";
+ compression = "none";
+
+ blob-ext {
+ filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo";
+ };
+ };
- configurations {
- default = "@config-DEFAULT-SEQ";
-
- @config-SEQ {
- fdt = "fdt-1",
- "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast",
- "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast",
- "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast",
- "fdt-dto-imx8mp-dhcom-som-overlay-rev100",
- "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100";
- };
+ fdt-dto-imx8mp-dhcom-som-overlay-rev100 {
+ description = "imx8mp-dhcom-som-overlay-rev100";
+ type = "flat_dt";
+ compression = "none";
+
+ blob-ext {
+ filename = "imx8mp-dhcom-som-overlay-rev100.dtbo";
+ };
+ };
+
+ fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 {
+ description = "imx8mp-dhcom-pdk3-overlay-rev100";
+ type = "flat_dt";
+ compression = "none";
+
+ blob-ext {
+ filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo";
};
};
};
+
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+
+ @config-SEQ {
+ fdt = "fdt-1",
+ "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast",
+ "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast",
+ "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast",
+ "fdt-dto-imx8mp-dhcom-som-overlay-rev100",
+ "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100";
+ };
+ };
};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020 PHYTEC Messtechnik GmbH
- * Author: Teresa Remmet <t.remmet@phytec.de>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/leds/leds-pca9532.h>
-#include <dt-bindings/pwm/pwm.h>
-#include "imx8mp-phycore-som.dtsi"
-
-/ {
- model = "PHYTEC phyBOARD-Pollux i.MX8MP";
- compatible = "phytec,imx8mp-phyboard-pollux-rdk",
- "phytec,imx8mp-phycore-som", "fsl,imx8mp";
-
- chosen {
- stdout-path = &uart1;
- };
-
- reg_can1_stby: regulator-can1-stby {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1_reg>;
- gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "can1-stby";
- };
-
- reg_can2_stby: regulator-can2-stby {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2_reg>;
- gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "can2-stby";
- };
-
- reg_usb1_vbus: regulator-usb1-vbus {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1_vbus>;
- gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- regulator-name = "usb1_host_vbus";
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- startup-delay-us = <100>;
- off-on-delay-us = <12000>;
- };
-};
-
-&eqos {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eqos>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x1>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
- enet-phy-lane-no-swap;
- };
- };
-};
-
-/* CAN FD */
-&flexcan1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- xceiver-supply = <®_can1_stby>;
- status = "okay";
-};
-
-&flexcan2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- xceiver-supply = <®_can2_stby>;
- status = "okay";
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-
- leds@62 {
- compatible = "nxp,pca9533";
- reg = <0x62>;
-
- led-1 {
- type = <PCA9532_TYPE_LED>;
- };
-
- led-2 {
- type = <PCA9532_TYPE_LED>;
- };
-
- led-3 {
- type = <PCA9532_TYPE_LED>;
- };
- };
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-/* debug console */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* USB1 Host mode Type-A */
-&usb3_phy0 {
- vbus-supply = <®_usb1_vbus>;
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&usb_dwc3_0 {
- dr_mode = "host";
- status = "okay";
-};
-
-/* USB2 4-port USB3.0 HUB */
-&usb3_phy1 {
- status = "okay";
-};
-
-&usb3_1 {
- fsl,permanently-attached;
- fsl,disable-port-power-control;
- status = "okay";
-};
-
-&usb_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-/* RS232/RS485 */
-&uart2 {
- assigned-clocks = <&clk IMX8MP_CLK_UART2>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- uart-has-rtscts;
- status = "okay";
-};
-
-/* SD-Card */
-&usdhc2 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
- assigned-clock-rates = <200000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- bus-width = <4>;
- status = "okay";
-};
-
-&gpio1 {
- gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
- "PMIC_SD_VSEL", "", "", "", "", "",
- "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
-};
-
-&gpio2 {
- gpio-line-names = "", "", "", "",
- "", "", "", "", "", "",
- "", "", "X_SD2_CD_B", "", "", "",
- "", "", "", "SD2_RESET_B";
-};
-
-&gpio3 {
- gpio-line-names = "", "", "", "",
- "", "", "", "", "", "",
- "", "", "", "", "", "",
- "", "", "", "", "nCAN1_EN", "nCAN2_EN";
-};
-
-&gpio4 {
- gpio-line-names = "", "", "", "",
- "", "", "", "", "", "",
- "", "", "", "", "", "",
- "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
-};
-
-&iomuxc {
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
- MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
- MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
- MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
- >;
- };
-
- pinctrl_flexcan1_reg: flexcan1reggrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154
- >;
- };
-
- pinctrl_flexcan2_reg: flexcan2reggrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
- MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
- >;
- };
-
- pinctrl_usb1_vbus: usb1vbusgrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
- MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140
- MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140
- >;
- };
-
- pinctrl_usdhc2_pins: usdhc2-gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020 PHYTEC Messtechnik GmbH
- * Author: Teresa Remmet <t.remmet@phytec.de>
- */
-
-#include <dt-bindings/net/ti-dp83867.h>
-#include "imx8mp.dtsi"
-
-/ {
- model = "PHYTEC phyCORE-i.MX8MP";
- compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
-
- aliases {
- rtc0 = &rv3028;
- rtc1 = &snvs_rtc;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2>;
-};
-
-/* ethernet 1 */
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy1>;
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- interrupt-parent = <&gpio1>;
- interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
- ti,min-output-impedance;
- enet-phy-lane-no-swap;
- };
- };
-};
-
-&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi0>;
- status = "okay";
-
- som_flash: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <80000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- pmic: pmic@25 {
- reg = <0x25>;
- compatible = "nxp,pca9450c";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio4>;
- interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
-
- regulators {
- buck1: BUCK1 {
- regulator-compatible = "BUCK1";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- };
-
- buck2: BUCK2 {
- regulator-compatible = "BUCK2";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
- };
-
- buck4: BUCK4 {
- regulator-compatible = "BUCK4";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5: BUCK5 {
- regulator-compatible = "BUCK5";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck6: BUCK6 {
- regulator-compatible = "BUCK6";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1: LDO1 {
- regulator-compatible = "LDO1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2: LDO2 {
- regulator-compatible = "LDO2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3: LDO3 {
- regulator-compatible = "LDO3";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4: LDO4 {
- regulator-compatible = "LDO4";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo5: LDO5 {
- regulator-compatible = "LDO5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-
- eeprom@51 {
- compatible = "atmel,24c32";
- reg = <0x51>;
- pagesize = <32>;
- };
-
- rv3028: rtc@52 {
- compatible = "microcrystal,rv3028";
- reg = <0x52>;
- trickle-resistor-ohms = <3000>;
- };
-};
-
-/* eMMC */
-&usdhc3 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
- MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12
- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12
- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
- MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11
- >;
- };
-
- pinctrl_flexspi0: flexspi0grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
- MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
- MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
- MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
- MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
- MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3
- MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3
- >;
- };
-
- pinctrl_pmic: pmicirqgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6
- >;
- };
-};
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
-&binman {
- section {
- fit {
- images {
- fip {
- description = "Trusted Firmware FIP";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x40310000>;
-
- fip_blob: blob-ext{
- filename = "fip.bin";
- };
- };
+&binman_imx_fit {
+ images {
+ fip {
+ description = "Trusted Firmware FIP";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x40310000>;
+
+ fip_blob: blob-ext{
+ filename = "fip.bin";
};
};
};
section {
pad-byte = <0x00>;
- nxp-imx8mimage {
- filename = "u-boot-spl-mkimage.bin";
- nxp,boot-from = "sd";
- nxp,rom-version = <2>;
+#ifdef CONFIG_IMX_HAB
+ nxp-imx8mcst@0 {
+ filename = "u-boot-spl-mkimage.signed.bin";
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ nxp,unlock;
args; /* Needed by mkimage etype superclass */
+#endif
- section {
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
- align-size = <4>;
- align = <4>;
-
- u-boot-spl {
- align-end = <4>;
- };
+ binman_imx_spl: nxp-imx8mimage {
+ filename = "u-boot-spl-mkimage.bin";
+ nxp,boot-from = "sd";
+ nxp,rom-version = <2>;
+ nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ args; /* Needed by mkimage etype superclass */
+
+ section {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem_202006.bin";
- type = "blob-ext";
- align-end = <4>;
- };
+ ddr-1d-imem-fw {
+ filename = "lpddr4_pmu_train_1d_imem_202006.bin";
+ type = "blob-ext";
+ align-end = <4>;
+ };
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
- type = "blob-ext";
- align-end = <4>;
- };
+ ddr-1d-dmem-fw {
+ filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
+ type = "blob-ext";
+ align-end = <4>;
+ };
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem_202006.bin";
- type = "blob-ext";
- align-end = <4>;
- };
+ ddr-2d-imem-fw {
+ filename = "lpddr4_pmu_train_2d_imem_202006.bin";
+ type = "blob-ext";
+ align-end = <4>;
+ };
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
- type = "blob-ext";
- align-end = <4>;
+ ddr-2d-dmem-fw {
+ filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
+ type = "blob-ext";
+ align-end = <4>;
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
- fit {
- description = "Configuration to load ATF before U-Boot";
-#ifndef CONFIG_IMX_HAB
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-#endif
- fit,fdt-list = "of-list";
- #address-cells = <1>;
+ nxp-imx8mcst@1 {
+ filename = "u-boot-fit.signed.bin";
+ nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
offset = <0x58000>;
+ args; /* Needed by mkimage etype superclass */
+#endif
- images {
- uboot {
- description = "U-Boot (64-bit)";
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
-
- uboot_blob: blob-ext {
- filename = "u-boot-nodtb.bin";
+ binman_imx_fit: fit {
+ description = "Configuration to load ATF before U-Boot";
+#ifndef CONFIG_IMX_HAB
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+#endif
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+ offset = <0x58000>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
};
- };
#ifndef CONFIG_ARMV8_PSCI
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x970000>;
- entry = <0x970000>;
-
- atf_blob: atf-blob {
- filename = "bl31.bin";
- type = "atf-bl31";
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x970000>;
+ entry = <0x970000>;
+
+ atf_blob: atf-blob {
+ filename = "bl31.bin";
+ type = "atf-bl31";
+ };
};
- };
#endif
- @fdt-SEQ {
- description = "NAME";
- type = "flat_dt";
- compression = "none";
+ @fdt-SEQ {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
- blob-ext {
- filename = "u-boot.dtb";
+ blob-ext {
+ filename = "u-boot.dtb";
+ };
};
};
- };
- configurations {
- default = "@config-DEFAULT-SEQ";
+ configurations {
+ default = "@config-DEFAULT-SEQ";
- @config-SEQ {
- description = "NAME";
- fdt = "fdt-SEQ";
- firmware = "uboot";
+ @config-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
- loadables = "atf";
+ loadables = "atf";
#endif
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
+#endif
};
};
bootph-pre-ram;
};
-&binman {
+&binman_imx_spl {
section {
- nxp-imx8mimage {
- section {
- signed-hdmi-imx8m {
- filename = "signed_dp_imx8m.bin";
- };
- };
+ signed-hdmi-imx8m {
+ filename = "signed_dp_imx8m.bin";
};
};
};
section {
pad-byte = <0x00>;
- nxp-imx8mimage {
- filename = "u-boot-spl-mkimage.bin";
- nxp,boot-from = "sd";
- nxp,rom-version = <1>;
+#ifdef CONFIG_IMX_HAB
+ nxp-imx8mcst@0 {
+ filename = "u-boot-spl-mkimage.signed.bin";
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ nxp,unlock;
args; /* Needed by mkimage etype superclass */
+#endif
- section {
- align = <4>;
- align-size = <4>;
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
-
- u-boot-spl {
- align-end = <4>;
- filename = "u-boot-spl.bin";
- };
+ binman_imx_spl: nxp-imx8mimage {
+ filename = "u-boot-spl-mkimage.bin";
+ nxp,boot-from = "sd";
+ nxp,rom-version = <1>;
+ nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
+ args; /* Needed by mkimage etype superclass */
+
+ section {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-1d-imem-fw {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-1d-dmem-fw {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-2d-imem-fw {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-2d-dmem-fw {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- signed-hdmi-imx8m {
- filename = "signed_hdmi_imx8m.bin";
- type = "blob-ext";
+ signed-hdmi-imx8m {
+ filename = "signed_hdmi_imx8m.bin";
+ type = "blob-ext";
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
- fit {
- description = "Configuration to load ATF before U-Boot";
+ nxp-imx8mcst@1 {
+ filename = "u-boot-fit.signed.bin";
+ nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
+ offset = <0x58000>;
+ args; /* Needed by mkimage etype superclass */
+#endif
+
+ binman_imx_fit: fit {
+ description = "Configuration to load ATF before U-Boot";
#ifndef CONFIG_IMX_HAB
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
#endif
- #address-cells = <1>;
-
- images {
- uboot {
- arch = "arm64";
- compression = "none";
- description = "U-Boot (64-bit)";
- load = <CONFIG_TEXT_BASE>;
- type = "standalone";
-
- uboot-blob {
- filename = "u-boot-nodtb.bin";
- type = "blob-ext";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ arch = "arm64";
+ compression = "none";
+ description = "U-Boot (64-bit)";
+ load = <CONFIG_TEXT_BASE>;
+ type = "standalone";
+
+ uboot-blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
};
- };
#ifndef CONFIG_ARMV8_PSCI
- atf {
- arch = "arm64";
- compression = "none";
- description = "ARM Trusted Firmware";
- entry = <0x910000>;
- load = <0x910000>;
- type = "firmware";
-
- atf-blob {
- filename = "bl31.bin";
- type = "blob-ext";
+ atf {
+ arch = "arm64";
+ compression = "none";
+ description = "ARM Trusted Firmware";
+ entry = <0x910000>;
+ load = <0x910000>;
+ type = "firmware";
+
+ atf-blob {
+ filename = "bl31.bin";
+ type = "blob-ext";
+ };
};
- };
#endif
- fdt {
- compression = "none";
- description = "NAME";
- type = "flat_dt";
+ fdt {
+ compression = "none";
+ description = "NAME";
+ type = "flat_dt";
- uboot-fdt-blob {
- filename = "u-boot.dtb";
- type = "blob-ext";
+ uboot-fdt-blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
};
};
- };
- configurations {
- default = "conf";
+ configurations {
+ default = "conf";
- conf {
- description = "NAME";
- fdt = "fdt";
- firmware = "uboot";
+ conf {
+ description = "NAME";
+ fdt = "fdt";
+ firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
- loadables = "atf";
+ loadables = "atf";
#endif
+ };
};
};
+#ifdef CONFIG_IMX_HAB
};
+#endif
};
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family Main Domain peripherals
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
};
};
- main_conf: syscon@100000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x00 0x00100000 0x00 0x20000>;
+ main_conf: bus@100000 {
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x00100000 0x20000>;
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
- <0x00 0x4bc00000 0x00 0x100000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>,
+ <0x00 0x48420000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "rflow";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
main_gpio0: gpio@600000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00600000 0x0 0x100>;
+ gpio-ranges = <&main_pmx0 0 0 32>,
+ <&main_pmx0 32 33 38>,
+ <&main_pmx0 70 72 22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00601000 0x0 0x100>;
gpio-controller;
+ gpio-ranges = <&main_pmx0 0 94 41>,
+ <&main_pmx0 41 136 6>,
+ <&main_pmx0 47 143 3>,
+ <&main_pmx0 50 149 2>;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <180>, <181>, <182>,
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 57 6>;
assigned-clock-parents = <&k3_clks 57 8>;
+ bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
- ti,trm-icp = <0x2>;
- bus-width = <8>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
clock-names = "clk_ahb", "clk_xin";
- ti,trm-icp = <0x2>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x8>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sd-hs = <0x1>;
ti,itap-del-sel-sdr12 = <0xa>;
ti,itap-del-sel-sdr25 = <0x1>;
- ti,clkbuf-sel = <0x7>;
- bus-width = <4>;
status = "disabled";
};
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
clock-names = "clk_ahb", "clk_xin";
- ti,trm-icp = <0x2>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x8>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sd-hs = <0xa>;
ti,itap-del-sel-sdr12 = <0xa>;
ti,itap-del-sel-sdr25 = <0x1>;
- ti,clkbuf-sel = <0x7>;
status = "disabled";
};
interrupt-names = "host", "peripheral";
maximum-speed = "high-speed";
dr_mode = "otg";
+ snps,usb2-gadget-lpm-disable;
+ snps,usb2-lpm-disable;
};
};
interrupt-names = "host", "peripheral";
maximum-speed = "high-speed";
dr_mode = "otg";
+ snps,usb2-gadget-lpm-disable;
+ snps,usb2-lpm-disable;
};
};
};
};
+ gpu: gpu@fd00000 {
+ compatible = "ti,am62-gpu", "img,img-axe";
+ reg = <0x00 0x0fd00000 0x00 0x20000>;
+ clocks = <&k3_clks 187 0>;
+ clock-names = "core";
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
+ };
+
cpsw3g: ethernet@8000000 {
compatible = "ti,am642-cpsw-nuss";
#address-cells = <2>;
<0x00 0x30207000 0x00 0x1000>, /* ovr1 */
<0x00 0x30208000 0x00 0x1000>, /* ovr2 */
<0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
- <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */
+ <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
+ <0x00 0x30201000 0x00 0x1000>; /* common1 */
reg-names = "common", "vidl1", "vid",
- "ovr1", "ovr2", "vp1", "vp2";
+ "ovr1", "ovr2", "vp1", "vp2", "common1";
power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 186 6>,
<&dss_vp1_clk>,
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
+
+ ti_csi2rx0: ticsi2rx@30102000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ dmas = <&main_bcdma 0 0x4700 0>;
+ dma-names = "rx0";
+ reg = <0x00 0x30102000 0x00 0x1000>;
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ cdns_csi2rx0: csi-bridge@30101000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x00 0x30101000 0x00 0x1000>;
+ clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
+ <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi0_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi0_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi0_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi0_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ dphy0: phy@30110000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x00 0x30110000 0x00 0x1100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family MCU Domain peripherals
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
#include <dt-bindings/thermal/thermal.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/bus/ti-sysc.h>
+
&cbass_wakeup {
wkup_conf: syscon@43000000 {
bootph-all;
};
};
- wkup_uart0: serial@2b300000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x2b300000 0x00 0x100>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ target-module@2b300050 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x00 0x2b300050 0x00 0x4>,
+ <0x00 0x2b300054 0x00 0x4>,
+ <0x00 0x2b300058 0x00 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ ti,no-reset-on-init;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
- clock-names = "fclk";
- status = "disabled";
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x2b300000 0x100000>;
+
+ wkup_uart0: serial@0 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
};
wkup_i2c0: i2c@2b200000 {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62 SoC Family
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
};
};
#endif
+
+&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan";
+};
+
+&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x20000>,
+ <0x00 0x484a0000 0x00 0x4000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
+ "tchan", "rchan", "rflow";
+ bootph-all;
+};
+
+&mdio0_pins_default {
+ bootph-all;
+};
+
+&cpsw3g_mdio {
+ bootph-all;
+};
+
+&cpsw3g_phy0 {
+ bootph-all;
+};
+
+&rgmii1_pins_default {
+ bootph-all;
+};
+
+&cpsw3g {
+ bootph-all;
+
+ ethernet-ports {
+ bootph-all;
+ };
+};
+
+&phy_gmii_sel {
+ bootph-all;
+};
+
+&cpsw_port1 {
+ bootph-all;
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* https://beagleplay.org/
*
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
- * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation
*/
/dts-v1/;
i2c3 = &main_i2c3;
i2c4 = &wkup_i2c0;
i2c5 = &mcu_i2c0;
- mdio-gpio0 = &mdio0;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
mmc2 = &sdhci2;
};
};
- /* Workaround for errata i2329 - just use mdio bitbang */
- mdio0: mdio {
- compatible = "virtual,mdio-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&mdio0_pins_default>;
- gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */
- <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw3g_phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- cpsw3g_phy1: ethernet-phy@1 {
- reg = <1>;
- reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
- reset-assert-us = <25>;
- reset-deassert-us = <60000>; /* T2 */
- };
- };
};
&main_pmx0 {
mdio0_pins_default: mdio0-default-pins {
pinctrl-single,pins = <
- AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */
- AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */
+ AM62X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
+ AM62X_IOPAD(0x015c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
+ AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */
+ AM62X_IOPAD(0x018c, PIN_INPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */
>;
};
AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */
AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */
AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */
- AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */
AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */
AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */
>;
>;
};
- console_pins_default: console-default-pins {
+ main_uart0_pins_default: main-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
};
&usbss0 {
+ bootph-all;
ti,vbus-divider;
status = "okay";
};
&usb0 {
+ bootph-all;
dr_mode = "peripheral";
};
};
&cpsw3g_mdio {
- /* Workaround for errata i2329 - Use mdio bitbang */
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio0_pins_default>;
+
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ reset-gpios = <&main_gpio0 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <50000>;
+ };
+
+ cpsw3g_phy1: ethernet-phy@1 {
+ reg = <1>;
+ reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <25>;
+ reset-deassert-us = <60000>; /* T2 */
+ };
};
&main_gpio0 {
"USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */
"EEPROM_WP", /* 10 */
"CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */
- "CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */
+ "CC1352P7_BOOT", "CC1352P7_RSTN", "GBE_RSTN", "", "", /* 13-17 */
"USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */
"", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */
"", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
status = "okay";
};
vmmc-supply = <&vdd_3v3_sd>;
vqmmc-supply = <&vdd_sd_dv>;
- ti,driver-strength-ohm = <50>;
disable-wp;
cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>;
cd-debounce-delay-ms = <100>;
vmmc-supply = <&wlan_en>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>;
- bus-width = <4>;
non-removable;
ti,fails-without-test-cd;
cap-power-off-card;
keep-power-in-suspend;
- ti,driver-strength-ohm = <50>;
assigned-clocks = <&k3_clks 157 158>;
assigned-clock-parents = <&k3_clks 157 160>;
#address-cells = <1>;
&main_uart0 {
bootph-all;
pinctrl-names = "default";
- pinctrl-0 = <&console_pins_default>;
+ pinctrl-0 = <&main_uart0_pins_default>;
status = "okay";
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* AM625 SK: https://www.ti.com/lit/zip/sprr448
*
- * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC family in Quad core configuration
*
* TRM: https://www.ti.com/lit/pdf/spruiv7
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A SoC Family Main Domain peripherals
*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
};
};
- main_conf: syscon@100000 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00 0x00100000 0x00 0x20000>;
+ main_conf: bus@100000 {
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x20000>;
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
- <0x00 0x4bc00000 0x00 0x100000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>,
+ <0x00 0x48420000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
ti,sci = <&dmsc>;
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "rflow";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
ti,sci = <&dmsc>;
};
};
+ dmss_csi: bus@4e000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>;
+
+ ti,sci-dev-id = <198>;
+
+ inta_main_dmss_csi: interrupt-controller@4e0a0000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x4e0a0000 0x00 0x8000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <200>;
+ ti,interrupt-ranges = <0 237 8>;
+ ti,unmapped-event-sources = <&main_bcdma_csi>;
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_bcdma_csi: dma-controller@4e230000 {
+ compatible = "ti,am62a-dmss-bcdma-csirx";
+ reg = <0x00 0x4e230000 0x00 0x100>,
+ <0x00 0x4e180000 0x00 0x8000>,
+ <0x00 0x4e100000 0x00 0x10000>;
+ reg-names = "gcfg", "rchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss_csi>;
+ #dma-cells = <3>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <199>;
+ ti,sci-rm-range-rchan = <0x21>;
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ };
+ };
+
dmsc: system-controller@44043000 {
compatible = "ti,k2g-sci";
reg = <0x00 0x44043000 0x00 0xfe0>;
<193>, <194>, <195>;
interrupt-controller;
#interrupt-cells = <2>;
- ti,ngpio = <87>;
+ ti,ngpio = <92>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
<183>, <184>, <185>;
interrupt-controller;
#interrupt-cells = <2>;
- ti,ngpio = <88>;
+ ti,ngpio = <52>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 78 0>;
status = "disabled";
};
+ sdhci0: mmc@fa10000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
+ clock-names = "clk_ahb", "clk_xin";
+ assigned-clocks = <&k3_clks 57 6>;
+ assigned-clock-parents = <&k3_clks 57 8>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-hs200 = <0x6>;
+ status = "disabled";
+ };
+
sdhci1: mmc@fa00000 {
compatible = "ti,am62-sdhci";
reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
clock-names = "clk_ahb", "clk_xin";
- ti,trm-icp = <0x2>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
- ti,clkbuf-sel = <0x7>;
+ no-1-8-v;
+ status = "disabled";
+ };
+
+ sdhci2: mmc@fa20000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
+ clock-names = "clk_ahb", "clk_xin";
bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
no-1-8-v;
status = "disabled";
};
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
+
+ ti_csi2rx0: ticsi2rx@30102000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ dmas = <&main_bcdma_csi 0 0x5000 0>;
+ dma-names = "rx0";
+ reg = <0x00 0x30102000 0x00 0x1000>;
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ cdns_csi2rx0: csi-bridge@30101000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x00 0x30101000 0x00 0x1000>;
+ clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
+ <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi0_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi0_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi0_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi0_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ dphy0: phy@30110000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x00 0x30110000 0x00 0x1100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ dss: dss@30200000 {
+ compatible = "ti,am62a7-dss";
+ reg = <0x00 0x30200000 0x00 0x1000>, /* common */
+ <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
+ <0x00 0x30206000 0x00 0x1000>, /* vid */
+ <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
+ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
+ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */
+ <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
+ <0x00 0x30201000 0x00 0x1000>; /* common1 */
+ reg-names = "common", "vidl1", "vid",
+ "ovr1", "ovr2", "vp1", "vp2", "common1";
+ power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 186 6>,
+ <&k3_clks 186 0>,
+ <&k3_clks 186 2>;
+ clock-names = "fck", "vp1", "vp2";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ dss_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family MCU Domain peripherals
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
#include <dt-bindings/thermal/thermal.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_wakeup {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A SoC Family
*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* AM62A SK: https://www.ti.com/lit/zip/sprr459
*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
serial0 = &wkup_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
+ mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
clock-frequency = <12288000>;
};
+ hdmi0: connector-hdmi {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&sii9022_out>;
+ };
+ };
+ };
+
codec_audio: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "AM62Ax-SKEVM";
};
&main_pmx0 {
+ main_dss0_pins_default: main-dss0-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x100, PIN_OUTPUT, 0) /* (V17) VOUT0_VSYNC */
+ AM62AX_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (T18) VOUT0_HSYNC */
+ AM62AX_IOPAD(0x104, PIN_OUTPUT, 0) /* (AA22) VOUT0_PCLK */
+ AM62AX_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (U17) VOUT0_DE */
+ AM62AX_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
+ AM62AX_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (U21) VOUT0_DATA1 */
+ AM62AX_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (U20) VOUT0_DATA2 */
+ AM62AX_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (U19) VOUT0_DATA3 */
+ AM62AX_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (T19) VOUT0_DATA4 */
+ AM62AX_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (U18) VOUT0_DATA5 */
+ AM62AX_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V22) VOUT0_DATA6 */
+ AM62AX_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA7 */
+ AM62AX_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V19) VOUT0_DATA8 */
+ AM62AX_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (V18) VOUT0_DATA9 */
+ AM62AX_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */
+ AM62AX_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA11 */
+ AM62AX_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (W20) VOUT0_DATA12 */
+ AM62AX_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (W19) VOUT0_DATA13 */
+ AM62AX_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y21) VOUT0_DATA14 */
+ AM62AX_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA15 */
+ AM62AX_IOPAD(0x05c, PIN_OUTPUT, 1) /* (P22) GPMC0_AD8.VOUT0_DATA16 */
+ AM62AX_IOPAD(0x060, PIN_OUTPUT, 1) /* (R19) GPMC0_AD9.VOUT0_DATA17 */
+ AM62AX_IOPAD(0x064, PIN_OUTPUT, 1) /* (R20) GPMC0_AD10.VOUT0_DATA18 */
+ AM62AX_IOPAD(0x068, PIN_OUTPUT, 1) /* (R22) GPMC0_AD11.VOUT0_DATA19 */
+ AM62AX_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
+ AM62AX_IOPAD(0x070, PIN_OUTPUT, 1) /* (R21) GPMC0_AD13.VOUT0_DATA21 */
+ AM62AX_IOPAD(0x074, PIN_OUTPUT, 1) /* (T20) GPMC0_AD14.VOUT0_DATA22 */
+ AM62AX_IOPAD(0x078, PIN_OUTPUT, 1) /* (T21) GPMC0_AD15.VOUT0_DATA23 */
+ >;
+ };
+
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
>;
};
+ main_mmc0_pins_default: main-mmc0-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
+ AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */
+ AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
+ AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
+ AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
+ AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
+ AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
+ AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
+ AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
+ AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
+ AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
+ >;
+ };
+
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
>;
};
+
+ main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */
+ >;
+ };
};
&mcu_pmx0 {
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
"BT_EN_SOC", "MMC1_SD_EN",
DRVDD-supply = <&vcc_3v3_sys>;
DVDD-supply = <&buck5>;
};
+
+ exp2: gpio@23 {
+ compatible = "ti,tca6424";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "", "",
+ "", "",
+ "", "",
+ "", "",
+ "WL_LT_EN", "CSI_RSTz",
+ "", "",
+ "", "",
+ "", "",
+ "SPI0_FET_SEL", "SPI0_FET_OE",
+ "RGMII2_BRD_CONN_DET", "CSI_SEL2",
+ "CSI_EN", "AUTO_100M_1000M_CONFIG",
+ "CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST";
+ };
+
+ sii9022: bridge-hdmi@3b {
+ compatible = "sil,sii9022";
+ reg = <0x3b>;
+ interrupt-parent = <&exp1>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ #sound-dai-cells = <0>;
+ sil,i2s-data-lanes = < 0 >;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sii9022_in: endpoint {
+ remote-endpoint = <&dpi1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ sii9022_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+};
+
+&main_i2c2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c2_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&sdhci0 {
+ /* eMMC */
+ status = "okay";
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc0_pins_default>;
+ disable-wp;
};
&sdhci1 {
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
};
tx-num-evt = <32>;
rx-num-evt = <32>;
};
+
+&dss {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_dss0_pins_default>;
+};
+
+&dss_ports {
+ /* VP2: DPI Output */
+ port@1 {
+ reg = <1>;
+
+ dpi1_out: endpoint {
+ remote-endpoint = <&sii9022_in>;
+ };
+ };
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A7 SoC family in Quad core configuration
*
* TRM: https://www.ti.com/lit/zip/spruj16
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Common dtsi for AM62x SK and derivatives
*
- * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/leds/common.h>
};
};
+&main_i2c2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c2_pins_default>;
+ clock-frequency = <400000>;
+};
+
&sdhci0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
};
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
};
};
&usbss0 {
+ bootph-all;
status = "okay";
ti,vbus-divider;
};
};
&usb0 {
+ bootph-all;
#address-cells = <1>;
#size-cells = <0>;
usb-role-switch;
};
};
};
+
+/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
+&mcu_gpio0 {
+ status = "reserved";
+};
+
+&mcu_gpio_intr {
+ status = "reserved";
+};
&cbass_mcu_wakeup {
bootph-all;
+};
+
+&wkup_conf {
+ bootph-all;
+};
- chipid@43000014 {
- bootph-all;
- };
+&chipid {
+ bootph-all;
};
&mcu_navss {
};
&mcu_udmap {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
bootph-all;
};
dr_mode = "peripheral";
bootph-all;
};
+
+#ifdef CONFIG_TARGET_J721S2_A72_EVM
+
+#define SPL_AM68_SK_DTB "spl/dts/ti/k3-am68-sk-base-board.dtb"
+#define AM68_SK_DTB "u-boot.dtb"
+
+&spl_j721s2_evm_dtb {
+ filename = SPL_AM68_SK_DTB;
+};
+
+&j721s2_evm_dtb {
+ filename = AM68_SK_DTB;
+};
+
+&spl_j721s2_evm_dtb_unsigned {
+ filename = SPL_AM68_SK_DTB;
+};
+
+&j721s2_evm_dtb_unsigned {
+ filename = AM68_SK_DTB;
+};
+
+#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Base Board: https://www.ti.com/lit/zip/SPRR463
- */
-
-/dts-v1/;
-
-#include "k3-am68-sk-som.dtsi"
-#include <dt-bindings/net/ti-dp83867.h>
-#include <dt-bindings/phy/phy-cadence.h>
-#include <dt-bindings/phy/phy.h>
-
-#include "k3-serdes.h"
-
-/ {
- compatible = "ti,am68-sk", "ti,j721s2";
- model = "Texas Instruments AM68 SK";
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart8;
- mmc1 = &main_sdhci1;
- can0 = &mcu_mcan0;
- can1 = &mcu_mcan1;
- can2 = &main_mcan6;
- can3 = &main_mcan7;
- };
-
- vusb_main: regulator-vusb-main5v0 {
- /* USB MAIN INPUT 5V DC */
- compatible = "regulator-fixed";
- regulator-name = "vusb-main5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vsys_3v3: regulator-vsys3v3 {
- /* Output of LM5141 */
- compatible = "regulator-fixed";
- regulator-name = "vsys_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vusb_main>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_mmc1: regulator-sd {
- /* Output of TPS22918 */
- compatible = "regulator-fixed";
- regulator-name = "vdd_mmc1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- enable-active-high;
- vin-supply = <&vsys_3v3>;
- gpio = <&exp1 8 GPIO_ACTIVE_HIGH>;
- };
-
- vdd_sd_dv: regulator-tlv71033 {
- /* Output of TLV71033 */
- compatible = "regulator-gpio";
- regulator-name = "tlv71033";
- pinctrl-names = "default";
- pinctrl-0 = <&vdd_sd_dv_pins_default>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- vin-supply = <&vsys_3v3>;
- gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0>,
- <3300000 0x1>;
- };
-
- vsys_io_1v8: regulator-vsys-io-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "vsys_io_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vsys_io_1v2: regulator-vsys-io-1v2 {
- compatible = "regulator-fixed";
- regulator-name = "vsys_io_1v2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- transceiver1: can-phy0 {
- compatible = "ti,tcan1042";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- };
-
- transceiver2: can-phy1 {
- compatible = "ti,tcan1042";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- };
-
- transceiver3: can-phy2 {
- compatible = "ti,tcan1042";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- };
-
- transceiver4: can-phy3 {
- compatible = "ti,tcan1042";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- };
-
- connector-hdmi {
- compatible = "hdmi-connector";
- label = "hdmi";
- type = "a";
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_hpd_pins_default>;
- ddc-i2c-bus = <&mcu_i2c1>;
- /* HDMI_HPD */
- hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&tfp410_out>;
- };
- };
- };
-
- bridge-dvi {
- compatible = "ti,tfp410";
- /* HDMI_PDn */
- powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>;
- ti,deskew = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- tfp410_in: endpoint {
- remote-endpoint = <&dpi_out0>;
- pclk-sample = <1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- tfp410_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-};
-
-&main_pmx0 {
- main_uart8_pins_default: main-uart8-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
- J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */
- J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
- J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
- J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
- J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
- J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
- J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
- >;
- };
-
- vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */
- >;
- };
-
- main_usbss0_pins_default: main-usbss0-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
- >;
- };
-
- main_mcan6_pins_default: main-mcan6-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */
- J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */
- >;
- };
-
- main_mcan7_pins_default: main-mcan7-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */
- J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */
- >;
- };
-
- main_i2c4_pins_default: main-i2c4-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */
- J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */
- >;
- };
-
- rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */
- J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */
- J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */
- J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */
- J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */
- J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */
- J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */
- J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */
- J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */
- J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */
- J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */
- J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */
- J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */
- J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */
- >;
- };
-
- dss_vout0_pins_default: dss-vout0-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */
- J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */
- J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */
- J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */
- J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */
- J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */
- J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */
- J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */
- J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */
- J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */
- J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */
- J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */
- J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */
- J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */
- J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */
- J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */
- J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */
- J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */
- J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */
- J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */
- J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */
- J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */
- J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */
- J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */
- J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */
- J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */
- J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */
- J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */
- >;
- };
-
- hdmi_hpd_pins_default: hdmi-hpd-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */
- >;
- };
-};
-
-&wkup_pmx2 {
- wkup_uart0_pins_default: wkup-uart0-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
- J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
- J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
- J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
- >;
- };
-
- mcu_cpsw_pins_default: mcu-cpsw-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
- J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
- J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
- J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
- J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
- J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
- J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
- J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
- J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
- J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
- J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
- J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
- >;
- };
-
- mcu_mdio_pins_default: mcu-mdio-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
- J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
- >;
- };
-
- mcu_mcan0_pins_default: mcu-mcan0-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
- J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
- >;
- };
-
- mcu_mcan1_pins_default: mcu-mcan1-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
- J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
- >;
- };
-
- mcu_i2c0_pins_default: mcu-i2c0-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */
- J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */
- >;
- };
-
- mcu_i2c1_pins_default: mcu-i2c1-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
- J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
- >;
- };
-
- mcu_uart0_pins_default: mcu-uart0-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
- J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
- >;
- };
-
- mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
- J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
- J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
- J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
- J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
- J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
- J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
- J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
- J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
- >;
- };
-};
-
-&wkup_pmx3 {
- mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
- >;
- };
-};
-
-&main_gpio0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&rpi_header_gpio0_pins_default>;
-};
-
-&wkup_gpio0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>;
-};
-
-&wkup_uart0 {
- status = "reserved";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&mcu_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
-};
-
-&main_uart8 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart8_pins_default>;
- /* Shared with TFA on this platform */
- power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
-};
-
-&main_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- exp1: gpio@21 {
- compatible = "ti,tca6416";
- reg = <0x21>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = " ", " ", " ", " ", " ",
- "BOARDID_EEPROM_WP", "CAN_STB", " ",
- "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz",
- "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " ";
- };
-};
-
-&main_i2c4 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c4_pins_default>;
- clock-frequency = <400000>;
-};
-
-&mcu_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_i2c0_pins_default>;
- clock-frequency = <400000>;
-};
-
-&mcu_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_i2c1_pins_default>;
- /* i2c1 is used for DVI DDC, so we need to use 100kHz */
- clock-frequency = <100000>;
-
- exp2: gpio@20 {
- compatible = "ti,tca6408";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "HDMI_PDn","HDMI_LS_OE",
- "DP0_3V3_EN","eDP_ENABLE";
- };
-};
-
-&main_sdhci1 {
- /* SD card */
- status = "okay";
- pinctrl-0 = <&main_mmc1_pins_default>;
- pinctrl-names = "default";
- disable-wp;
- vmmc-supply = <&vdd_mmc1>;
- vqmmc-supply = <&vdd_sd_dv>;
-};
-
-&mcu_cpsw {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
-};
-
-&davinci_mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,min-output-impedance;
- };
-};
-
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&phy0>;
-};
-
-&mcu_mcan0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mcan0_pins_default>;
- phys = <&transceiver1>;
-};
-
-&mcu_mcan1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mcan1_pins_default>;
- phys = <&transceiver2>;
-};
-
-&main_mcan6 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcan6_pins_default>;
- phys = <&transceiver3>;
-};
-
-&main_mcan7 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcan7_pins_default>;
- phys = <&transceiver4>;
-};
-
-&dss {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&dss_vout0_pins_default>;
- /*
- * These clock assignments are chosen to enable the following outputs:
- *
- * VP0 - DisplayPort SST
- * VP1 - DPI0
- * VP2 - DSI
- * VP3 - DPI1
- */
- assigned-clocks = <&k3_clks 158 2>,
- <&k3_clks 158 5>,
- <&k3_clks 158 14>,
- <&k3_clks 158 18>;
- assigned-clock-parents = <&k3_clks 158 3>,
- <&k3_clks 158 7>,
- <&k3_clks 158 16>,
- <&k3_clks 158 22>;
-};
-
-&dss_ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* HDMI */
- port@1 {
- reg = <1>;
-
- dpi_out0: endpoint {
- remote-endpoint = <&tfp410_in>;
- };
- };
-};
-
-&serdes_ln_ctrl {
- idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>,
- <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>;
-};
-
-&serdes_refclk {
- clock-frequency = <100000000>;
-};
-
-&serdes0 {
- status = "okay";
-
- serdes0_pcie_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <2>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
- };
-
- serdes0_usb_link: phy@2 {
- status = "okay";
- reg = <2>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_USB3>;
- resets = <&serdes_wiz0 3>;
- };
-};
-
-&pcie1_rc {
- status = "okay";
- reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>;
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
-};
-
-&usb_serdes_mux {
- idle-states = <0>; /* USB0 to SERDES lane 2 */
-};
-
-&usbss0 {
- status = "okay";
- pinctrl-0 = <&main_usbss0_pins_default>;
- pinctrl-names = "default";
- ti,vbus-divider;
-};
-
-&usb0 {
- dr_mode = "host";
- maximum-speed = "super-speed";
- phys = <&serdes0_usb_link>;
- phy-names = "cdns3,usb3-phy";
-};
#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
#include "k3-j721s2-ddr.dtsi"
#include "k3-am68-sk-base-board-u-boot.dtsi"
-
-/ {
- chosen {
- tick-timer = &mcu_timer0;
- };
-
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- };
-
- a72_0: a72@0 {
- compatible = "ti,am654-rproc";
- reg = <0x0 0x00a90000 0x0 0x10>;
- power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
- resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 1>;
- assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
- assigned-clock-parents = <&k3_clks 61 2>;
- assigned-clock-rates = <200000000>, <2000000000>;
- ti,sci = <&sms>;
- ti,sci-proc-id = <32>;
- ti,sci-host-id = <10>;
- bootph-pre-ram;
- };
-
- dm_tifs: dm-tifs {
- compatible = "ti,j721e-dm-sci";
- ti,host-id = <3>;
- ti,secure-host;
- mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_mcu 21>,
- <&secure_proxy_mcu 23>;
- bootph-pre-ram;
- };
-};
-
-&mcu_timer0 {
- clock-frequency = <250000000>;
- bootph-pre-ram;
-};
-
-&secure_proxy_mcu {
- bootph-pre-ram;
-};
-
-&secure_proxy_sa3 {
- bootph-pre-ram;
-};
-
-&cbass_mcu_wakeup {
- sysctrler: sysctrler {
- compatible = "ti,am654-system-controller";
- mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>;
- mbox-names = "tx", "rx", "boot_notify";
- bootph-pre-ram;
- };
-};
-
-&sms {
- mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
- mbox-names = "tx", "rx", "notify";
- ti,host-id = <4>;
- ti,secure-host;
-};
-
-&mcu_ringacc {
- ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
- ti,sci = <&dm_tifs>;
-};
+#include "k3-j721s2-r5.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-j721s2.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- memory@80000000 {
- device_type = "memory";
- /* 16 GB RAM */
- reg = <0x00 0x80000000 0x00 0x80000000>,
- <0x08 0x80000000 0x03 0x80000000>;
- };
-
- reserved_memory: reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>;
- no-map;
- };
-
- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0000000 0x00 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0100000 0x00 0xf00000>;
- no-map;
- };
-
- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1000000 0x00 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa4000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa4100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa5000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa5100000 0x00 0xf00000>;
- no-map;
- };
-
- c71_0_dma_memory_region: c71-dma-memory@a6000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa6000000 0x00 0x100000>;
- no-map;
- };
-
- c71_0_memory_region: c71-memory@a6100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa6100000 0x00 0xf00000>;
- no-map;
- };
-
- c71_1_dma_memory_region: c71-dma-memory@a7000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa7000000 0x00 0x100000>;
- no-map;
- };
-
- c71_1_memory_region: c71-memory@a7100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa7100000 0x00 0xf00000>;
- no-map;
- };
-
- rtos_ipc_memory_region: ipc-memories@a8000000 {
- reg = <0x00 0xa8000000 0x00 0x01c00000>;
- alignment = <0x1000>;
- no-map;
- };
- };
-};
-
-&wkup_pmx2 {
- wkup_i2c0_pins_default: wkup-i2c0-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
- J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
- >;
- };
-};
-
-&wkup_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- eeprom@51 {
- /* AT24C512C-MAHM-T */
- compatible = "atmel,24c512";
- reg = <0x51>;
- };
-};
-
-&mailbox0_cluster0 {
- status = "okay";
- interrupts = <436>;
- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster1 {
- status = "okay";
- interrupts = <432>;
- mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster2 {
- status = "okay";
- interrupts = <428>;
- mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster4 {
- status = "okay";
- interrupts = <420>;
- mbox_c71_0: mbox-c71-0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_c71_1: mbox-c71-1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
- memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
- <&mcu_r5fss0_core0_memory_region>;
-};
-
-&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
- memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
- <&mcu_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
- memory-region = <&main_r5fss0_core0_dma_memory_region>,
- <&main_r5fss0_core0_memory_region>;
-};
-
-&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
- memory-region = <&main_r5fss0_core1_dma_memory_region>,
- <&main_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
- memory-region = <&main_r5fss1_core0_dma_memory_region>,
- <&main_r5fss1_core0_memory_region>;
-};
-
-&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
- memory-region = <&main_r5fss1_core1_dma_memory_region>,
- <&main_r5fss1_core1_memory_region>;
-};
-
-&c71_0 {
- status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
- memory-region = <&c71_0_dma_memory_region>,
- <&c71_0_memory_region>;
-};
-
-&c71_1 {
- status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
- memory-region = <&c71_1_dma_memory_region>,
- <&c71_1_memory_region>;
-};
#ifdef CONFIG_TARGET_J721S2_A72_EVM
-#define SPL_J721S2_EVM_DTB "spl/dts/k3-j721s2-common-proc-board.dtb"
-#define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb"
-
+#define SPL_J721S2_EVM_DTB "spl/dts/ti/k3-j721s2-common-proc-board.dtb"
#define J721S2_EVM_DTB "u-boot.dtb"
-#define AM68_SK_DTB "arch/arm/dts/k3-am68-sk-base-board.dtb"
&binman {
ti-dm {
};
};
-
- fdt-1 {
- description = "k3-am68-sk-base-board";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&spl_am68_sk_dtb>;
- keyfile = "custMpk.pem";
- };
- spl_am68_sk_dtb: blob-ext {
- filename = SPL_AM68_SK_DTB;
- };
- };
};
configurations {
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
-
- conf-1 {
- description = "k3-am68-sk-base-board";
- firmware = "atf";
- loadables = "tee", "dm", "spl";
- fdt = "fdt-1";
- };
};
};
};
algo = "crc32";
};
};
-
- fdt-1 {
- description = "k3-am68-sk-base-board";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&am68_sk_dtb>;
- keyfile = "custMpk.pem";
- };
- am68_sk_dtb: blob-ext {
- filename = AM68_SK_DTB;
- };
-
- hash {
- algo = "crc32";
- };
- };
-
};
configurations {
loadables = "uboot";
fdt = "fdt-0";
};
- conf-1 {
- description = "k3-am68-sk-base-board";
- firmware = "uboot";
- loadables = "uboot";
- fdt = "fdt-1";
- };
-
};
};
};
type = "flat_dt";
arch = "arm";
compression = "none";
- blob {
+ spl_j721s2_evm_dtb_unsigned: blob {
filename = SPL_J721S2_EVM_DTB;
};
};
- fdt-1 {
- description = "k3-am68-sk-base-board";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- blob {
- filename = SPL_AM68_SK_DTB;
- };
- };
-
};
configurations {
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
- conf-1 {
- description = "k3-am68-sk-base-board";
- firmware = "atf";
- loadables = "tee", "dm", "spl";
- fdt = "fdt-1";
- };
};
};
};
type = "flat_dt";
arch = "arm";
compression = "none";
- blob {
+ j721s2_evm_dtb_unsigned: blob {
filename = J721S2_EVM_DTB;
};
hash {
algo = "crc32";
};
};
- fdt-1 {
- description = "k3-am68-sk-base-board";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
- blob {
- filename = AM68_SK_DTB;
- };
- hash {
- algo = "crc32";
- };
- };
-
};
configurations {
loadables = "uboot";
fdt = "fdt-0";
};
- conf-1 {
- description = "k3-am68-sk-base-board";
- firmware = "uboot";
- loadables = "uboot";
- fdt = "fdt-1";
- };
};
};
};
&cbass_mcu_wakeup {
bootph-all;
+};
- chipid@43000014 {
- bootph-all;
- };
+&wkup_conf {
+ bootph-all;
+};
+
+&chipid {
+ bootph-all;
};
&mcu_navss {
};
&mcu_udmap {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
bootph-all;
};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM
- */
-
-/dts-v1/;
-
-#include "k3-j721s2-som-p0.dtsi"
-#include <dt-bindings/net/ti-dp83867.h>
-#include <dt-bindings/phy/phy-cadence.h>
-#include <dt-bindings/phy/phy.h>
-
-#include "k3-serdes.h"
-
-/ {
- compatible = "ti,j721s2-evm", "ti,j721s2";
- model = "Texas Instruments J721S2 EVM";
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- aliases {
- serial1 = &mcu_uart0;
- serial2 = &main_uart8;
- mmc0 = &main_sdhci0;
- mmc1 = &main_sdhci1;
- can0 = &main_mcan16;
- can1 = &mcu_mcan0;
- can2 = &mcu_mcan1;
- can3 = &main_mcan3;
- can4 = &main_mcan5;
- };
-
- evm_12v0: fixedregulator-evm12v0 {
- /* main supply */
- compatible = "regulator-fixed";
- regulator-name = "evm_12v0";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vsys_3v3: fixedregulator-vsys3v3 {
- /* Output of LM5140 */
- compatible = "regulator-fixed";
- regulator-name = "vsys_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&evm_12v0>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vsys_5v0: fixedregulator-vsys5v0 {
- /* Output of LM5140 */
- compatible = "regulator-fixed";
- regulator-name = "vsys_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&evm_12v0>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_mmc1: fixedregulator-sd {
- /* Output of TPS22918 */
- compatible = "regulator-fixed";
- regulator-name = "vdd_mmc1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- enable-active-high;
- vin-supply = <&vsys_3v3>;
- gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
- };
-
- vdd_sd_dv: gpio-regulator-TLV71033 {
- /* Output of TLV71033 */
- compatible = "regulator-gpio";
- regulator-name = "tlv71033";
- pinctrl-names = "default";
- pinctrl-0 = <&vdd_sd_dv_pins_default>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- vin-supply = <&vsys_5v0>;
- gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0>,
- <3300000 0x1>;
- };
-
- transceiver1: can-phy1 {
- compatible = "ti,tcan1043";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
- standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>;
- enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
- };
-
- transceiver2: can-phy2 {
- compatible = "ti,tcan1042";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
- standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
- };
-
- transceiver3: can-phy3 {
- compatible = "ti,tcan1043";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
- enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
- mux-states = <&mux0 1>;
- };
-
- transceiver4: can-phy4 {
- compatible = "ti,tcan1042";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>;
- mux-states = <&mux1 1>;
- };
-};
-
-&main_pmx0 {
- main_uart8_pins_default: main-uart8-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
- J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
- J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
- J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
- >;
- };
-
- main_i2c3_pins_default: main-i2c3-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */
- J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
- J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
- J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
- J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
- J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
- J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
- J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
- >;
- };
-
- vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
- >;
- };
-
- main_usbss0_pins_default: main-usbss0-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
- >;
- };
-
- main_mcan3_pins_default: main-mcan3-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */
- J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */
- >;
- };
-
- main_mcan5_pins_default: main-mcan5-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */
- J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */
- >;
- };
-};
-
-&wkup_pmx2 {
- wkup_uart0_pins_default: wkup-uart0-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
- J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
- J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
- J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
- >;
- };
-
- mcu_uart0_pins_default: mcu-uart0-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */
- J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
- J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
- J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
- >;
- };
-
- mcu_cpsw_pins_default: mcu-cpsw-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
- J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
- J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
- J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
- J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
- J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
- J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
- J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
- J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
- J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
- J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
- J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
- >;
- };
-
- mcu_mdio_pins_default: mcu-mdio-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
- J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
- >;
- };
-
- mcu_mcan0_pins_default: mcu-mcan0-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
- J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
- >;
- };
-
- mcu_mcan1_pins_default: mcu-mcan1-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
- J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */
- >;
- };
-
- mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */
- J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */
- >;
- };
-
- mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
- >;
- };
-
- mcu_adc0_pins_default: mcu-adc0-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */
- J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */
- J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */
- J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */
- J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */
- J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */
- J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */
- J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */
- >;
- };
-
- mcu_adc1_pins_default: mcu-adc1-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */
- J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */
- J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */
- J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */
- J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */
- J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */
- J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */
- J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */
- >;
- };
-};
-
-&wkup_pmx1 {
- mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
- J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
- J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
- J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
- J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
- J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
- J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
- J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
- >;
- };
-};
-
-&main_gpio0 {
- status = "okay";
-};
-
-&wkup_gpio0 {
- status = "okay";
-};
-
-&wkup_uart0 {
- status = "reserved";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&mcu_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
-};
-
-&main_uart8 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart8_pins_default>;
- /* Shared with TFA on this platform */
- power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
-};
-
-&main_i2c0 {
- clock-frequency = <400000>;
-
- exp1: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ",
- "PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ",
- "PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#",
- "PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1",
- "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz";
- };
-
- exp2: gpio@22 {
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN",
- "USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#",
- "MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1",
- "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL",
- "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL",
- "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2";
- };
-};
-
-&main_sdhci0 {
- /* eMMC */
- status = "okay";
- non-removable;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&main_sdhci1 {
- /* SD card */
- status = "okay";
- pinctrl-0 = <&main_mmc1_pins_default>;
- pinctrl-names = "default";
- disable-wp;
- vmmc-supply = <&vdd_mmc1>;
- vqmmc-supply = <&vdd_sd_dv>;
-};
-
-&mcu_cpsw {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
-};
-
-&davinci_mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,min-output-impedance;
- };
-};
-
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&phy0>;
-};
-
-&serdes_ln_ctrl {
- idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
- <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
-};
-
-&serdes_refclk {
- clock-frequency = <100000000>;
-};
-
-&serdes0 {
- status = "okay";
- serdes0_pcie_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- resets = <&serdes_wiz0 1>;
- };
-};
-
-&usb_serdes_mux {
- idle-states = <1>; /* USB0 to SERDES lane 1 */
-};
-
-&usbss0 {
- status = "okay";
- pinctrl-0 = <&main_usbss0_pins_default>;
- pinctrl-names = "default";
- ti,vbus-divider;
- ti,usb2-only;
-};
-
-&usb0 {
- dr_mode = "otg";
- maximum-speed = "high-speed";
-};
-
-&ospi1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <40000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <2>;
- };
-};
-
-&pcie1_rc {
- status = "okay";
- reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <1>;
-};
-
-&mcu_mcan0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mcan0_pins_default>;
- phys = <&transceiver1>;
-};
-
-&mcu_mcan1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mcan1_pins_default>;
- phys = <&transceiver2>;
-};
-
-&tscadc0 {
- pinctrl-0 = <&mcu_adc0_pins_default>;
- pinctrl-names = "default";
- status = "okay";
- adc {
- ti,adc-channels = <0 1 2 3 4 5 6 7>;
- };
-};
-
-&tscadc1 {
- pinctrl-0 = <&mcu_adc1_pins_default>;
- pinctrl-names = "default";
- status = "okay";
- adc {
- ti,adc-channels = <0 1 2 3 4 5 6 7>;
- };
-};
-
-&main_mcan3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcan3_pins_default>;
- phys = <&transceiver3>;
-};
-
-&main_mcan5 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcan5_pins_default>;
- phys = <&transceiver4>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for J721S2 SoC Family Main Domain peripherals
- *
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/phy/phy-cadence.h>
-#include <dt-bindings/phy/phy-ti.h>
-
-/ {
- serdes_refclk: clock-cmnrefclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-};
-
-&cbass_main {
- msmc_ram: sram@70000000 {
- compatible = "mmio-sram";
- reg = <0x0 0x70000000 0x0 0x400000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x70000000 0x400000>;
-
- atf-sram@0 {
- reg = <0x0 0x20000>;
- };
-
- tifs-sram@1f0000 {
- reg = <0x1f0000 0x10000>;
- };
-
- l3cache-sram@200000 {
- reg = <0x200000 0x200000>;
- };
- };
-
- scm_conf: syscon@104000 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00 0x00104000 0x00 0x18000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x00104000 0x18000>;
-
- usb_serdes_mux: mux-controller@0 {
- compatible = "mmio-mux";
- reg = <0x0 0x4>;
- #mux-control-cells = <1>;
- mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
- };
-
- phy_gmii_sel_cpsw: phy@34 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x34 0x4>;
- #phy-cells = <1>;
- };
-
- serdes_ln_ctrl: mux-controller@80 {
- compatible = "mmio-mux";
- reg = <0x80 0x10>;
- #mux-control-cells = <1>;
- mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
- <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
- };
-
- ehrpwm_tbclk: clock-controller@140 {
- compatible = "ti,am654-ehrpwm-tbclk";
- reg = <0x140 0x18>;
- #clock-cells = <1>;
- };
- };
-
- main_ehrpwm0: pwm@3000000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x3000000 0x00 0x100>;
- power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- main_ehrpwm1: pwm@3010000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x3010000 0x00 0x100>;
- power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- main_ehrpwm2: pwm@3020000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x3020000 0x00 0x100>;
- power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- main_ehrpwm3: pwm@3030000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x3030000 0x00 0x100>;
- power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- main_ehrpwm4: pwm@3040000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x3040000 0x00 0x100>;
- power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- main_ehrpwm5: pwm@3050000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x3050000 0x00 0x100>;
- power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- gic500: interrupt-controller@1800000 {
- compatible = "arm,gic-v3";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>, /* GICR */
- <0x00 0x6f000000 0x00 0x2000>, /* GICC */
- <0x00 0x6f010000 0x00 0x1000>, /* GICH */
- <0x00 0x6f020000 0x00 0x2000>; /* GICV */
-
- /* vcpumntirq: virtual CPU interface maintenance interrupt */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- gic_its: msi-controller@1820000 {
- compatible = "arm,gic-v3-its";
- reg = <0x00 0x01820000 0x00 0x10000>;
- socionext,synquacer-pre-its = <0x1000000 0x400000>;
- msi-controller;
- #msi-cells = <1>;
- };
- };
-
- main_gpio_intr: interrupt-controller@a00000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x00a00000 0x00 0x800>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&sms>;
- ti,sci-dev-id = <148>;
- ti,interrupt-ranges = <8 392 56>;
- };
-
- main_pmx0: pinctrl@11c000 {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x0 0x11c000 0x0 0x120>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
- main_timerio_input: pinctrl@104200 {
- compatible = "pinctrl-single";
- reg = <0x00 0x104200 0x00 0x50>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x00000007>;
- };
-
- /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
- main_timerio_output: pinctrl@104280 {
- compatible = "pinctrl-single";
- reg = <0x00 0x104280 0x00 0x20>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000001f>;
- };
-
- main_crypto: crypto@4e00000 {
- compatible = "ti,j721e-sa2ul";
- reg = <0x00 0x04e00000 0x00 0x1200>;
- power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
-
- dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
- <&main_udmap 0x4a41>;
- dma-names = "tx", "rx1", "rx2";
-
- rng: rng@4e10000 {
- compatible = "inside-secure,safexcel-eip76";
- reg = <0x00 0x04e10000 0x00 0x7d>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- main_timer0: timer@2400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2400000 0x00 0x400>;
- interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 63 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 63 1>;
- assigned-clock-parents = <&k3_clks 63 2>;
- power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer1: timer@2410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2410000 0x00 0x400>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 64 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 64 1>;
- assigned-clock-parents = <&k3_clks 64 2>;
- power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer2: timer@2420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2420000 0x00 0x400>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 65 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 65 1>;
- assigned-clock-parents = <&k3_clks 65 2>;
- power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer3: timer@2430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2430000 0x00 0x400>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 66 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 66 1>;
- assigned-clock-parents = <&k3_clks 66 2>;
- power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer4: timer@2440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2440000 0x00 0x400>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 67 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 67 1>;
- assigned-clock-parents = <&k3_clks 67 2>;
- power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer5: timer@2450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2450000 0x00 0x400>;
- interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 68 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 68 1>;
- assigned-clock-parents = <&k3_clks 68 2>;
- power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer6: timer@2460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2460000 0x00 0x400>;
- interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 69 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 69 1>;
- assigned-clock-parents = <&k3_clks 69 2>;
- power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer7: timer@2470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2470000 0x00 0x400>;
- interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 70 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 70 1>;
- assigned-clock-parents = <&k3_clks 70 2>;
- power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer8: timer@2480000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2480000 0x00 0x400>;
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 71 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 71 1>;
- assigned-clock-parents = <&k3_clks 71 2>;
- power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer9: timer@2490000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2490000 0x00 0x400>;
- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 72 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 72 1>;
- assigned-clock-parents = <&k3_clks 72 2>;
- power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer10: timer@24a0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24a0000 0x00 0x400>;
- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 73 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 73 1>;
- assigned-clock-parents = <&k3_clks 73 2>;
- power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer11: timer@24b0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24b0000 0x00 0x400>;
- interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 74 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 74 1>;
- assigned-clock-parents = <&k3_clks 74 2>;
- power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer12: timer@24c0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24c0000 0x00 0x400>;
- interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 75 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 75 1>;
- assigned-clock-parents = <&k3_clks 75 2>;
- power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer13: timer@24d0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24d0000 0x00 0x400>;
- interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 76 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 76 1>;
- assigned-clock-parents = <&k3_clks 76 2>;
- power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer14: timer@24e0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24e0000 0x00 0x400>;
- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 77 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 77 1>;
- assigned-clock-parents = <&k3_clks 77 2>;
- power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer15: timer@24f0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24f0000 0x00 0x400>;
- interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 78 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 78 1>;
- assigned-clock-parents = <&k3_clks 78 2>;
- power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer16: timer@2500000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2500000 0x00 0x400>;
- interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 79 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 79 1>;
- assigned-clock-parents = <&k3_clks 79 2>;
- power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer17: timer@2510000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2510000 0x00 0x400>;
- interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 80 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 80 1>;
- assigned-clock-parents = <&k3_clks 80 2>;
- power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer18: timer@2520000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2520000 0x00 0x400>;
- interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 81 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 81 1>;
- assigned-clock-parents = <&k3_clks 81 2>;
- power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer19: timer@2530000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2530000 0x00 0x400>;
- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 82 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 82 1>;
- assigned-clock-parents = <&k3_clks 82 2>;
- power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_uart0: serial@2800000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02800000 0x00 0x200>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
- clocks = <&k3_clks 146 3>;
- clock-names = "fclk";
- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart1: serial@2810000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02810000 0x00 0x200>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
- clocks = <&k3_clks 350 3>;
- clock-names = "fclk";
- power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart2: serial@2820000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02820000 0x00 0x200>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
- clocks = <&k3_clks 351 3>;
- clock-names = "fclk";
- power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart3: serial@2830000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02830000 0x00 0x200>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
- clocks = <&k3_clks 352 3>;
- clock-names = "fclk";
- power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart4: serial@2840000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02840000 0x00 0x200>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
- clocks = <&k3_clks 353 3>;
- clock-names = "fclk";
- power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart5: serial@2850000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02850000 0x00 0x200>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
- clocks = <&k3_clks 354 3>;
- clock-names = "fclk";
- power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart6: serial@2860000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02860000 0x00 0x200>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
- clocks = <&k3_clks 355 3>;
- clock-names = "fclk";
- power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart7: serial@2870000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02870000 0x00 0x200>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
- clocks = <&k3_clks 356 3>;
- clock-names = "fclk";
- power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart8: serial@2880000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02880000 0x00 0x200>;
- interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
- clocks = <&k3_clks 357 3>;
- clock-names = "fclk";
- power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart9: serial@2890000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x02890000 0x00 0x200>;
- interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
- clocks = <&k3_clks 358 3>;
- clock-names = "fclk";
- power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_gpio0: gpio@600000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00600000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <145>, <146>, <147>, <148>, <149>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <66>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 111 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio2: gpio@610000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00610000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <154>, <155>, <156>, <157>, <158>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <66>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 112 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio4: gpio@620000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00620000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <163>, <164>, <165>, <166>, <167>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <66>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 113 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio6: gpio@630000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00630000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <172>, <173>, <174>, <175>, <176>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <66>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 114 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_i2c0: i2c@2000000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02000000 0x00 0x100>;
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 214 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
- };
-
- main_i2c1: i2c@2010000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02010000 0x00 0x100>;
- interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 215 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c2: i2c@2020000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02020000 0x00 0x100>;
- interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 216 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c3: i2c@2030000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02030000 0x00 0x100>;
- interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 217 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c4: i2c@2040000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02040000 0x00 0x100>;
- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 218 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c5: i2c@2050000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02050000 0x00 0x100>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 219 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c6: i2c@2060000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02060000 0x00 0x100>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 220 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_sdhci0: mmc@4f80000 {
- compatible = "ti,j721e-sdhci-8bit";
- reg = <0x00 0x04f80000 0x00 0x1000>,
- <0x00 0x04f88000 0x00 0x400>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
- clock-names = "clk_ahb", "clk_xin";
- assigned-clocks = <&k3_clks 98 1>;
- assigned-clock-parents = <&k3_clks 98 2>;
- bus-width = <8>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-ddr52 = <0x6>;
- ti,otap-del-sel-hs200 = <0x8>;
- ti,otap-del-sel-hs400 = <0x5>;
- ti,itap-del-sel-legacy = <0x10>;
- ti,itap-del-sel-mmc-hs = <0xa>;
- ti,strobe-sel = <0x77>;
- ti,clkbuf-sel = <0x7>;
- ti,trm-icp = <0x8>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- dma-coherent;
- status = "disabled";
- };
-
- main_sdhci1: mmc@4fb0000 {
- compatible = "ti,j721e-sdhci-4bit";
- reg = <0x00 0x04fb0000 0x00 0x1000>,
- <0x00 0x04fb8000 0x00 0x400>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
- clock-names = "clk_ahb", "clk_xin";
- assigned-clocks = <&k3_clks 99 1>;
- assigned-clock-parents = <&k3_clks 99 2>;
- bus-width = <4>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x5>;
- ti,otap-del-sel-ddr50 = <0xc>;
- ti,itap-del-sel-legacy = <0x0>;
- ti,itap-del-sel-sd-hs = <0x0>;
- ti,itap-del-sel-sdr12 = <0x0>;
- ti,itap-del-sel-sdr25 = <0x0>;
- ti,clkbuf-sel = <0x7>;
- ti,trm-icp = <0x8>;
- dma-coherent;
- /* Masking support for SDR104 capability */
- sdhci-caps-mask = <0x00000003 0x00000000>;
- status = "disabled";
- };
-
- main_navss: bus@30000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
- ti,sci-dev-id = <224>;
- dma-coherent;
- dma-ranges;
-
- main_navss_intr: interrupt-controller@310e0000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x310e0000 0x00 0x4000>;
- ti,intr-trigger-type = <4>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&sms>;
- ti,sci-dev-id = <227>;
- ti,interrupt-ranges = <0 64 64>,
- <64 448 64>,
- <128 672 64>;
- };
-
- main_udmass_inta: msi-controller@33d00000 {
- compatible = "ti,sci-inta";
- reg = <0x00 0x33d00000 0x00 0x100000>;
- interrupt-controller;
- #interrupt-cells = <0>;
- interrupt-parent = <&main_navss_intr>;
- msi-controller;
- ti,sci = <&sms>;
- ti,sci-dev-id = <265>;
- ti,interrupt-ranges = <0 0 256>;
- ti,unmapped-event-sources = <&main_bcdma_csi>;
- };
-
- secure_proxy_main: mailbox@32c00000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x32c00000 0x00 0x100000>,
- <0x00 0x32400000 0x00 0x100000>,
- <0x00 0x32800000 0x00 0x100000>;
- interrupt-names = "rx_011";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- hwspinlock: spinlock@30e00000 {
- compatible = "ti,am654-hwspinlock";
- reg = <0x00 0x30e00000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
-
- mailbox0_cluster0: mailbox@31f80000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f80000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster1: mailbox@31f81000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f81000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster2: mailbox@31f82000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f82000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster3: mailbox@31f83000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f83000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster4: mailbox@31f84000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f84000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster5: mailbox@31f85000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f85000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster6: mailbox@31f86000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f86000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster7: mailbox@31f87000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f87000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster8: mailbox@31f88000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f88000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster9: mailbox@31f89000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f89000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster10: mailbox@31f8a000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f8a000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox0_cluster11: mailbox@31f8b000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f8b000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox1_cluster0: mailbox@31f90000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f90000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox1_cluster1: mailbox@31f91000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f91000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox1_cluster2: mailbox@31f92000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f92000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox1_cluster3: mailbox@31f93000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f93000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox1_cluster4: mailbox@31f94000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f94000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox1_cluster5: mailbox@31f95000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f95000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox1_cluster6: mailbox@31f96000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f96000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox1_cluster7: mailbox@31f97000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f97000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox1_cluster8: mailbox@31f98000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f98000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox1_cluster9: mailbox@31f99000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f99000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox1_cluster10: mailbox@31f9a000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f9a000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- mailbox1_cluster11: mailbox@31f9b000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f9b000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&main_navss_intr>;
- status = "disabled";
- };
-
- main_ringacc: ringacc@3c000000 {
- compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x3c000000 0x0 0x400000>,
- <0x0 0x38000000 0x0 0x400000>,
- <0x0 0x31120000 0x0 0x100>,
- <0x0 0x33000000 0x0 0x40000>,
- <0x0 0x31080000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- ti,num-rings = <1024>;
- ti,sci-rm-range-gp-rings = <0x1>;
- ti,sci = <&sms>;
- ti,sci-dev-id = <259>;
- msi-parent = <&main_udmass_inta>;
- };
-
- main_udmap: dma-controller@31150000 {
- compatible = "ti,j721e-navss-main-udmap";
- reg = <0x0 0x31150000 0x0 0x100>,
- <0x0 0x34000000 0x0 0x80000>,
- <0x0 0x35000000 0x0 0x200000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
- msi-parent = <&main_udmass_inta>;
- #dma-cells = <1>;
-
- ti,sci = <&sms>;
- ti,sci-dev-id = <263>;
- ti,ringacc = <&main_ringacc>;
-
- ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
- <0x0f>, /* TX_HCHAN */
- <0x10>; /* TX_UHCHAN */
- ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
- <0x0b>, /* RX_HCHAN */
- <0x0c>; /* RX_UHCHAN */
- ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
- };
-
- main_bcdma_csi: dma-controller@311a0000 {
- compatible = "ti,j721s2-dmss-bcdma-csi";
- reg = <0x00 0x311a0000 0x00 0x100>,
- <0x00 0x35d00000 0x00 0x20000>,
- <0x00 0x35c00000 0x00 0x10000>,
- <0x00 0x35e00000 0x00 0x80000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
- msi-parent = <&main_udmass_inta>;
- #dma-cells = <3>;
- ti,sci = <&sms>;
- ti,sci-dev-id = <225>;
- ti,sci-rm-range-rchan = <0x21>;
- ti,sci-rm-range-tchan = <0x22>;
- status = "disabled";
- };
-
- cpts@310d0000 {
- compatible = "ti,j721e-cpts";
- reg = <0x0 0x310d0000 0x0 0x400>;
- reg-names = "cpts";
- clocks = <&k3_clks 226 5>;
- clock-names = "cpts";
- assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
- assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
- interrupts-extended = <&main_navss_intr 391>;
- interrupt-names = "cpts";
- ti,cpts-periodic-outputs = <6>;
- ti,cpts-ext-ts-inputs = <8>;
- };
- };
-
- main_cpsw: ethernet@c200000 {
- compatible = "ti,j721e-cpsw-nuss";
- reg = <0x00 0xc200000 0x00 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
- #address-cells = <2>;
- #size-cells = <2>;
- dma-coherent;
- clocks = <&k3_clks 28 28>;
- clock-names = "fck";
- power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
-
- dmas = <&main_udmap 0xc640>,
- <&main_udmap 0xc641>,
- <&main_udmap 0xc642>,
- <&main_udmap 0xc643>,
- <&main_udmap 0xc644>,
- <&main_udmap 0xc645>,
- <&main_udmap 0xc646>,
- <&main_udmap 0xc647>,
- <&main_udmap 0x4640>;
- dma-names = "tx0", "tx1", "tx2", "tx3",
- "tx4", "tx5", "tx6", "tx7",
- "rx";
-
- status = "disabled";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- main_cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- phys = <&phy_gmii_sel_cpsw 1>;
- status = "disabled";
- };
- };
-
- main_cpsw_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x00 0xf00 0x00 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 28 28>;
- clock-names = "fck";
- bus_freq = <1000000>;
- status = "disabled";
- };
-
- cpts@3d000 {
- compatible = "ti,am65-cpts";
- reg = <0x00 0x3d000 0x00 0x400>;
- clocks = <&k3_clks 28 3>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
- };
- };
-
- usbss0: cdns-usb@4104000 {
- compatible = "ti,j721e-usb";
- reg = <0x00 0x04104000 0x00 0x100>;
- clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
- clock-names = "ref", "lpm";
- assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
- assigned-clock-parents = <&k3_clks 360 17>;
- power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- dma-coherent;
-
- status = "disabled"; /* Needs pinmux */
-
- usb0: usb@6000000 {
- compatible = "cdns,usb3";
- reg = <0x00 0x06000000 0x00 0x10000>,
- <0x00 0x06010000 0x00 0x10000>,
- <0x00 0x06020000 0x00 0x10000>;
- reg-names = "otg", "xhci", "dev";
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host", "peripheral", "otg";
- maximum-speed = "super-speed";
- dr_mode = "otg";
- };
- };
-
- serdes_wiz0: wiz@5060000 {
- compatible = "ti,j721s2-wiz-10g";
- #address-cells = <1>;
- #size-cells = <1>;
- power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
- clock-names = "fck", "core_ref_clk", "ext_ref_clk";
- num-lanes = <4>;
- #reset-cells = <1>;
- #clock-cells = <1>;
- ranges = <0x5060000 0x0 0x5060000 0x10000>;
-
- assigned-clocks = <&k3_clks 365 3>;
- assigned-clock-parents = <&k3_clks 365 7>;
-
- serdes0: serdes@5060000 {
- compatible = "ti,j721e-serdes-10g";
- reg = <0x05060000 0x00010000>;
- reg-names = "torrent_phy";
- resets = <&serdes_wiz0 0>;
- reset-names = "torrent_reset";
- clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
- <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
- clock-names = "refclk", "phy_en_refclk";
- assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
- <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
- <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
- assigned-clock-parents = <&k3_clks 365 3>,
- <&k3_clks 365 3>,
- <&k3_clks 365 3>;
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <1>;
-
- status = "disabled"; /* Needs lane config */
- };
- };
-
- pcie1_rc: pcie@2910000 {
- compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
- reg = <0x00 0x02910000 0x00 0x1000>,
- <0x00 0x02917000 0x00 0x400>,
- <0x00 0x0d800000 0x00 0x800000>,
- <0x00 0x18000000 0x00 0x1000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
- device_type = "pci";
- ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
- max-link-speed = <3>;
- num-lanes = <4>;
- power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 276 41>;
- clock-names = "fck";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x104c>;
- device-id = <0xb013>;
- msi-map = <0x0 &gic_its 0x0 0x10000>;
- dma-coherent;
- ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
- <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
- <0 0 0 2 &pcie1_intc 0>, /* INT B */
- <0 0 0 3 &pcie1_intc 0>, /* INT C */
- <0 0 0 4 &pcie1_intc 0>; /* INT D */
-
- status = "disabled"; /* Needs gpio and serdes info */
-
- pcie1_intc: interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic500>;
- interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- main_mcan0: can@2701000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02701000 0x00 0x200>,
- <0x00 0x02708000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan1: can@2711000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02711000 0x00 0x200>,
- <0x00 0x02718000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan2: can@2721000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02721000 0x00 0x200>,
- <0x00 0x02728000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan3: can@2731000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02731000 0x00 0x200>,
- <0x00 0x02738000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan4: can@2741000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02741000 0x00 0x200>,
- <0x00 0x02748000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan5: can@2751000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02751000 0x00 0x200>,
- <0x00 0x02758000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan6: can@2761000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02761000 0x00 0x200>,
- <0x00 0x02768000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan7: can@2771000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02771000 0x00 0x200>,
- <0x00 0x02778000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan8: can@2781000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02781000 0x00 0x200>,
- <0x00 0x02788000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan9: can@2791000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02791000 0x00 0x200>,
- <0x00 0x02798000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan10: can@27a1000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x027a1000 0x00 0x200>,
- <0x00 0x027a8000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan11: can@27b1000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x027b1000 0x00 0x200>,
- <0x00 0x027b8000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan12: can@27c1000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x027c1000 0x00 0x200>,
- <0x00 0x027c8000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan13: can@27d1000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x027d1000 0x00 0x200>,
- <0x00 0x027d8000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan14: can@2681000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02681000 0x00 0x200>,
- <0x00 0x02688000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan15: can@2691000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x02691000 0x00 0x200>,
- <0x00 0x02698000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan16: can@26a1000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x026a1000 0x00 0x200>,
- <0x00 0x026a8000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan17: can@26b1000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x026b1000 0x00 0x200>,
- <0x00 0x026b8000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_spi0: spi@2100000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02100000 0x00 0x400>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 339 1>;
- status = "disabled";
- };
-
- main_spi1: spi@2110000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02110000 0x00 0x400>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 340 1>;
- status = "disabled";
- };
-
- main_spi2: spi@2120000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02120000 0x00 0x400>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 341 1>;
- status = "disabled";
- };
-
- main_spi3: spi@2130000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02130000 0x00 0x400>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 342 1>;
- status = "disabled";
- };
-
- main_spi4: spi@2140000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02140000 0x00 0x400>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 343 1>;
- status = "disabled";
- };
-
- main_spi5: spi@2150000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02150000 0x00 0x400>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 344 1>;
- status = "disabled";
- };
-
- main_spi6: spi@2160000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02160000 0x00 0x400>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 345 1>;
- status = "disabled";
- };
-
- main_spi7: spi@2170000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x02170000 0x00 0x400>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 346 1>;
- status = "disabled";
- };
-
- dss: dss@4a00000 {
- compatible = "ti,j721e-dss";
- reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
- <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
- <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
- <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
- <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
- <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
- <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
- <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
- <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
- <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
- <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
- <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
- <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
- <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
- <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
- <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
- <0x00 0x04af0000 0x00 0x10000>; /* wb */
- reg-names = "common_m", "common_s0",
- "common_s1", "common_s2",
- "vidl1", "vidl2","vid1","vid2",
- "ovr1", "ovr2", "ovr3", "ovr4",
- "vp1", "vp2", "vp3", "vp4",
- "wb";
- clocks = <&k3_clks 158 0>,
- <&k3_clks 158 2>,
- <&k3_clks 158 5>,
- <&k3_clks 158 14>,
- <&k3_clks 158 18>;
- clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
- power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
- interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "common_m",
- "common_s0",
- "common_s1",
- "common_s2";
- status = "disabled";
-
- dss_ports: ports {
- };
- };
-
- main_r5fss0: r5fss@5c00000 {
- compatible = "ti,j721s2-r5fss";
- ti,cluster-mode = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
- <0x5d00000 0x00 0x5d00000 0x20000>;
- power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
-
- main_r5fss0_core0: r5f@5c00000 {
- compatible = "ti,j721s2-r5f";
- reg = <0x5c00000 0x00010000>,
- <0x5c10000 0x00010000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&sms>;
- ti,sci-dev-id = <279>;
- ti,sci-proc-ids = <0x06 0xff>;
- resets = <&k3_reset 279 1>;
- firmware-name = "j721s2-main-r5f0_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
-
- main_r5fss0_core1: r5f@5d00000 {
- compatible = "ti,j721s2-r5f";
- reg = <0x5d00000 0x00010000>,
- <0x5d10000 0x00010000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&sms>;
- ti,sci-dev-id = <280>;
- ti,sci-proc-ids = <0x07 0xff>;
- resets = <&k3_reset 280 1>;
- firmware-name = "j721s2-main-r5f0_1-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-
- main_r5fss1: r5fss@5e00000 {
- compatible = "ti,j721s2-r5fss";
- ti,cluster-mode = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
- <0x5f00000 0x00 0x5f00000 0x20000>;
- power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
-
- main_r5fss1_core0: r5f@5e00000 {
- compatible = "ti,j721s2-r5f";
- reg = <0x5e00000 0x00010000>,
- <0x5e10000 0x00010000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&sms>;
- ti,sci-dev-id = <281>;
- ti,sci-proc-ids = <0x08 0xff>;
- resets = <&k3_reset 281 1>;
- firmware-name = "j721s2-main-r5f1_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
-
- main_r5fss1_core1: r5f@5f00000 {
- compatible = "ti,j721s2-r5f";
- reg = <0x5f00000 0x00010000>,
- <0x5f10000 0x00010000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&sms>;
- ti,sci-dev-id = <282>;
- ti,sci-proc-ids = <0x09 0xff>;
- resets = <&k3_reset 282 1>;
- firmware-name = "j721s2-main-r5f1_1-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-
- c71_0: dsp@64800000 {
- compatible = "ti,j721s2-c71-dsp";
- reg = <0x00 0x64800000 0x00 0x00080000>,
- <0x00 0x64e00000 0x00 0x0000c000>;
- reg-names = "l2sram", "l1dram";
- ti,sci = <&sms>;
- ti,sci-dev-id = <8>;
- ti,sci-proc-ids = <0x30 0xff>;
- resets = <&k3_reset 8 1>;
- firmware-name = "j721s2-c71_0-fw";
- status = "disabled";
- };
-
- c71_1: dsp@65800000 {
- compatible = "ti,j721s2-c71-dsp";
- reg = <0x00 0x65800000 0x00 0x00080000>,
- <0x00 0x65e00000 0x00 0x0000c000>;
- reg-names = "l2sram", "l1dram";
- ti,sci = <&sms>;
- ti,sci-dev-id = <11>;
- ti,sci-proc-ids = <0x31 0xff>;
- resets = <&k3_reset 11 1>;
- firmware-name = "j721s2-c71_1-fw";
- status = "disabled";
- };
-
- main_esm: esm@700000 {
- compatible = "ti,j721e-esm";
- reg = <0x00 0x700000 0x00 0x1000>;
- ti,esm-pins = <688>, <689>;
- bootph-pre-ram;
- };
-
- watchdog0: watchdog@2200000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2200000 0x00 0x100>;
- clocks = <&k3_clks 286 1>;
- power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 286 1>;
- assigned-clock-parents = <&k3_clks 286 5>;
- };
-
- watchdog1: watchdog@2210000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2210000 0x00 0x100>;
- clocks = <&k3_clks 287 1>;
- power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 287 1>;
- assigned-clock-parents = <&k3_clks 287 5>;
- };
-
- /*
- * The following RTI instances are coupled with MCU R5Fs, c7x and
- * GPU so keeping them reserved as these will be used by their
- * respective firmware
- */
- watchdog2: watchdog@22f0000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x22f0000 0x00 0x100>;
- clocks = <&k3_clks 290 1>;
- power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 290 1>;
- assigned-clock-parents = <&k3_clks 290 5>;
- /* reserved for GPU */
- status = "reserved";
- };
-
- watchdog3: watchdog@2300000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2300000 0x00 0x100>;
- clocks = <&k3_clks 288 1>;
- power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 288 1>;
- assigned-clock-parents = <&k3_clks 288 5>;
- /* reserved for C7X_0 */
- status = "reserved";
- };
-
- watchdog4: watchdog@2310000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2310000 0x00 0x100>;
- clocks = <&k3_clks 289 1>;
- power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 289 1>;
- assigned-clock-parents = <&k3_clks 289 5>;
- /* reserved for C7X_1 */
- status = "reserved";
- };
-
- watchdog5: watchdog@23c0000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x23c0000 0x00 0x100>;
- clocks = <&k3_clks 291 1>;
- power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 291 1>;
- assigned-clock-parents = <&k3_clks 291 5>;
- /* reserved for MAIN_R5F0_0 */
- status = "reserved";
- };
-
- watchdog6: watchdog@23d0000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x23d0000 0x00 0x100>;
- clocks = <&k3_clks 292 1>;
- power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 292 1>;
- assigned-clock-parents = <&k3_clks 292 5>;
- /* reserved for MAIN_R5F0_1 */
- status = "reserved";
- };
-
- watchdog7: watchdog@23e0000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x23e0000 0x00 0x100>;
- clocks = <&k3_clks 293 1>;
- power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 293 1>;
- assigned-clock-parents = <&k3_clks 293 5>;
- /* reserved for MAIN_R5F1_0 */
- status = "reserved";
- };
-
- watchdog8: watchdog@23f0000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x23f0000 0x00 0x100>;
- clocks = <&k3_clks 294 1>;
- power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 294 1>;
- assigned-clock-parents = <&k3_clks 294 5>;
- /* reserved for MAIN_R5F1_1 */
- status = "reserved";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals
- *
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_mcu_wakeup {
- sms: system-controller@44083000 {
- compatible = "ti,k2g-sci";
- ti,host-id = <12>;
-
- mbox-names = "rx", "tx";
-
- mboxes = <&secure_proxy_main 11>,
- <&secure_proxy_main 13>;
-
- reg-names = "debug_messages";
- reg = <0x00 0x44083000 0x00 0x1000>;
-
- k3_pds: power-controller {
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <2>;
- };
-
- k3_clks: clock-controller {
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-
- k3_reset: reset-controller {
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
- };
-
- chipid@43000014 {
- compatible = "ti,am654-chipid";
- reg = <0x00 0x43000014 0x00 0x4>;
- };
-
- secure_proxy_sa3: mailbox@43600000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x43600000 0x00 0x10000>,
- <0x00 0x44880000 0x00 0x20000>,
- <0x00 0x44860000 0x00 0x20000>;
- /*
- * Marked Disabled:
- * Node is incomplete as it is meant for bootloaders and
- * firmware on non-MPU processors
- */
- status = "disabled";
- };
-
- mcu_ram: sram@41c00000 {
- compatible = "mmio-sram";
- reg = <0x00 0x41c00000 0x00 0x100000>;
- ranges = <0x00 0x00 0x41c00000 0x100000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- wkup_pmx0: pinctrl@4301c000 {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x00 0x4301c000 0x00 0x034>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- wkup_pmx1: pinctrl@4301c038 {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x00 0x4301c038 0x00 0x02C>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- wkup_pmx2: pinctrl@4301c068 {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x00 0x4301c068 0x00 0x120>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- wkup_pmx3: pinctrl@4301c190 {
- compatible = "pinctrl-single";
- /* Proxy 0 addressing */
- reg = <0x00 0x4301c190 0x00 0x004>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
- mcu_timerio_input: pinctrl@40f04200 {
- compatible = "pinctrl-single";
- reg = <0x00 0x40f04200 0x00 0x28>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
- mcu_timerio_output: pinctrl@40f04280 {
- compatible = "pinctrl-single";
- reg = <0x00 0x40f04280 0x00 0x28>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- wkup_gpio_intr: interrupt-controller@42200000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x42200000 0x00 0x400>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&sms>;
- ti,sci-dev-id = <125>;
- ti,interrupt-ranges = <16 960 16>;
- };
-
- mcu_conf: syscon@40f00000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x0 0x40f00000 0x0 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x40f00000 0x20000>;
-
- phy_gmii_sel: phy@4040 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4040 0x4>;
- #phy-cells = <1>;
- };
-
- };
-
- mcu_timer0: timer@40400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40400000 0x00 0x400>;
- interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 35 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 35 1>;
- assigned-clock-parents = <&k3_clks 35 2>;
- power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer1: timer@40410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40410000 0x00 0x400>;
- interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 83 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 83 1>;
- assigned-clock-parents = <&k3_clks 83 2>;
- power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer2: timer@40420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40420000 0x00 0x400>;
- interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 84 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 84 1>;
- assigned-clock-parents = <&k3_clks 84 2>;
- power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer3: timer@40430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40430000 0x00 0x400>;
- interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 85 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 85 1>;
- assigned-clock-parents = <&k3_clks 85 2>;
- power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer4: timer@40440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40440000 0x00 0x400>;
- interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 86 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 86 1>;
- assigned-clock-parents = <&k3_clks 86 2>;
- power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer5: timer@40450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40450000 0x00 0x400>;
- interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 87 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 87 1>;
- assigned-clock-parents = <&k3_clks 87 2>;
- power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer6: timer@40460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40460000 0x00 0x400>;
- interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 88 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 88 1>;
- assigned-clock-parents = <&k3_clks 88 2>;
- power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer7: timer@40470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40470000 0x00 0x400>;
- interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 89 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 89 1>;
- assigned-clock-parents = <&k3_clks 89 2>;
- power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer8: timer@40480000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40480000 0x00 0x400>;
- interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 90 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 90 1>;
- assigned-clock-parents = <&k3_clks 90 2>;
- power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- mcu_timer9: timer@40490000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40490000 0x00 0x400>;
- interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 91 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 91 1>;
- assigned-clock-parents = <&k3_clks 91 2>;
- power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- /* Non-MPU Firmware usage */
- status = "reserved";
- };
-
- wkup_uart0: serial@42300000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x42300000 0x00 0x200>;
- interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
- clocks = <&k3_clks 359 3>;
- clock-names = "fclk";
- power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcu_uart0: serial@40a00000 {
- compatible = "ti,j721e-uart", "ti,am654-uart";
- reg = <0x00 0x40a00000 0x00 0x200>;
- interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
- clocks = <&k3_clks 149 3>;
- clock-names = "fclk";
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- wkup_gpio0: gpio@42110000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x42110000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&wkup_gpio_intr>;
- interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <89>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 115 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- wkup_gpio1: gpio@42100000 {
- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
- reg = <0x00 0x42100000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&wkup_gpio_intr>;
- interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <89>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 116 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- wkup_i2c0: i2c@42120000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x42120000 0x00 0x100>;
- interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 223 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcu_i2c0: i2c@40b00000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x40b00000 0x00 0x100>;
- interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 221 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcu_i2c1: i2c@40b10000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x00 0x40b10000 0x00 0x100>;
- interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 222 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcu_mcan0: can@40528000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x40528000 0x00 0x200>,
- <0x00 0x40500000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- mcu_mcan1: can@40568000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x40568000 0x00 0x200>,
- <0x00 0x40540000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- mcu_spi0: spi@40300000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x040300000 0x00 0x400>;
- interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 347 0>;
- status = "disabled";
- };
-
- mcu_spi1: spi@40310000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x040310000 0x00 0x400>;
- interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 348 0>;
- status = "disabled";
- };
-
- mcu_spi2: spi@40320000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x040320000 0x00 0x400>;
- interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 349 0>;
- status = "disabled";
- };
-
- mcu_navss: bus@28380000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
- dma-coherent;
- dma-ranges;
-
- ti,sci-dev-id = <267>;
-
- mcu_ringacc: ringacc@2b800000 {
- compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- ti,num-rings = <286>;
- ti,sci-rm-range-gp-rings = <0x1>;
- ti,sci = <&sms>;
- ti,sci-dev-id = <272>;
- msi-parent = <&main_udmass_inta>;
- };
-
- mcu_udmap: dma-controller@285c0000 {
- compatible = "ti,j721e-navss-mcu-udmap";
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x2aa00000 0x0 0x40000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
- msi-parent = <&main_udmass_inta>;
- #dma-cells = <1>;
-
- ti,sci = <&sms>;
- ti,sci-dev-id = <273>;
- ti,ringacc = <&mcu_ringacc>;
- ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
- <0x0f>; /* TX_HCHAN */
- ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
- <0x0b>; /* RX_HCHAN */
- ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
- };
- };
-
- secure_proxy_mcu: mailbox@2a480000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x2a480000 0x00 0x80000>,
- <0x00 0x2a380000 0x00 0x80000>,
- <0x00 0x2a400000 0x00 0x80000>;
- /*
- * Marked Disabled:
- * Node is incomplete as it is meant for bootloaders and
- * firmware on non-MPU processors
- */
- status = "disabled";
- };
-
- mcu_cpsw: ethernet@46000000 {
- compatible = "ti,j721e-cpsw-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x0 0x46000000 0x0 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
- dma-coherent;
- clocks = <&k3_clks 29 28>;
- clock-names = "fck";
- power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
-
- dmas = <&mcu_udmap 0xf000>,
- <&mcu_udmap 0xf001>,
- <&mcu_udmap 0xf002>,
- <&mcu_udmap 0xf003>,
- <&mcu_udmap 0xf004>,
- <&mcu_udmap 0xf005>,
- <&mcu_udmap 0xf006>,
- <&mcu_udmap 0xf007>,
- <&mcu_udmap 0x7000>;
- dma-names = "tx0", "tx1", "tx2", "tx3",
- "tx4", "tx5", "tx6", "tx7",
- "rx";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- ti,syscon-efuse = <&mcu_conf 0x200>;
- phys = <&phy_gmii_sel 1>;
- };
- };
-
- davinci_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x0 0xf00 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 29 28>;
- clock-names = "fck";
- bus_freq = <1000000>;
- };
-
- cpts@3d000 {
- compatible = "ti,am65-cpts";
- reg = <0x0 0x3d000 0x0 0x400>;
- clocks = <&k3_clks 29 3>;
- clock-names = "cpts";
- assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
- assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
- interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
- };
- };
-
- tscadc0: tscadc@40200000 {
- compatible = "ti,am3359-tscadc";
- reg = <0x00 0x40200000 0x00 0x1000>;
- interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 0 0>;
- assigned-clocks = <&k3_clks 0 2>;
- assigned-clock-rates = <60000000>;
- clock-names = "fck";
- dmas = <&main_udmap 0x7400>,
- <&main_udmap 0x7401>;
- dma-names = "fifo0", "fifo1";
- status = "disabled";
-
- adc {
- #io-channel-cells = <1>;
- compatible = "ti,am3359-adc";
- };
- };
-
- tscadc1: tscadc@40210000 {
- compatible = "ti,am3359-tscadc";
- reg = <0x00 0x40210000 0x00 0x1000>;
- interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 1 0>;
- assigned-clocks = <&k3_clks 1 2>;
- assigned-clock-rates = <60000000>;
- clock-names = "fck";
- dmas = <&main_udmap 0x7402>,
- <&main_udmap 0x7403>;
- dma-names = "fifo0", "fifo1";
- status = "disabled";
-
- adc {
- #io-channel-cells = <1>;
- compatible = "ti,am3359-adc";
- };
- };
-
- fss: bus@47000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
- <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
-
- ospi0: spi@47040000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x00 0x47040000 0x00 0x100>,
- <0x05 0x00000000 0x01 0x00000000>;
- interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 109 5>;
- assigned-clocks = <&k3_clks 109 5>;
- assigned-clock-parents = <&k3_clks 109 7>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled"; /* Needs pinmux */
- };
-
- ospi1: spi@47050000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x00 0x47050000 0x00 0x100>,
- <0x07 0x00000000 0x01 0x00000000>;
- interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 110 5>;
- power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled"; /* Needs pinmux */
- };
- };
-
- wkup_vtm0: temperature-sensor@42040000 {
- compatible = "ti,j7200-vtm";
- reg = <0x00 0x42040000 0x0 0x350>,
- <0x00 0x42050000 0x0 0x350>;
- power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
- #thermal-sensor-cells = <1>;
- };
-
- mcu_r5fss0: r5fss@41000000 {
- compatible = "ti,j721s2-r5fss";
- ti,cluster-mode = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x41000000 0x00 0x41000000 0x20000>,
- <0x41400000 0x00 0x41400000 0x20000>;
- power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
-
- mcu_r5fss0_core0: r5f@41000000 {
- compatible = "ti,j721s2-r5f";
- reg = <0x41000000 0x00010000>,
- <0x41010000 0x00010000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&sms>;
- ti,sci-dev-id = <284>;
- ti,sci-proc-ids = <0x01 0xff>;
- resets = <&k3_reset 284 1>;
- firmware-name = "j721s2-mcu-r5f0_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
-
- mcu_r5fss0_core1: r5f@41400000 {
- compatible = "ti,j721s2-r5f";
- reg = <0x41400000 0x00010000>,
- <0x41410000 0x00010000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&sms>;
- ti,sci-dev-id = <285>;
- ti,sci-proc-ids = <0x02 0xff>;
- resets = <&k3_reset 285 1>;
- firmware-name = "j721s2-mcu-r5f0_1-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-
- mcu_esm: esm@40800000 {
- compatible = "ti,j721e-esm";
- reg = <0x00 0x40800000 0x00 0x1000>;
- ti,esm-pins = <95>;
- bootph-pre-ram;
- };
-
- wkup_esm: esm@42080000 {
- compatible = "ti,j721e-esm";
- reg = <0x00 0x42080000 0x00 0x1000>;
- ti,esm-pins = <63>;
- bootph-pre-ram;
- };
-
- /*
- * The 2 RTI instances are couple with MCU R5Fs so keeping them
- * reserved as these will be used by their respective firmware
- */
- mcu_watchdog0: watchdog@40600000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x40600000 0x00 0x100>;
- clocks = <&k3_clks 295 1>;
- power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 295 1>;
- assigned-clock-parents = <&k3_clks 295 5>;
- /* reserved for MCU_R5F0_0 */
- status = "reserved";
- };
-
- mcu_watchdog1: watchdog@40610000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x40610000 0x00 0x100>;
- clocks = <&k3_clks 296 1>;
- power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 296 1>;
- assigned-clock-parents = <&k3_clks 296 5>;
- /* reserved for MCU_R5F0_1 */
- status = "reserved";
- };
-};
#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
#include "k3-j721s2-ddr.dtsi"
#include "k3-j721s2-common-proc-board-u-boot.dtsi"
-
-/ {
- chosen {
- tick-timer = &mcu_timer0;
- };
-
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- };
-
- a72_0: a72@0 {
- compatible = "ti,am654-rproc";
- reg = <0x0 0x00a90000 0x0 0x10>;
- power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
- <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
- resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 1>;
- assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
- assigned-clock-parents = <&k3_clks 61 2>;
- assigned-clock-rates = <200000000>, <2000000000>;
- ti,sci = <&sms>;
- ti,sci-proc-id = <32>;
- ti,sci-host-id = <10>;
- bootph-pre-ram;
- };
-
- dm_tifs: dm-tifs {
- compatible = "ti,j721e-dm-sci";
- ti,host-id = <3>;
- ti,secure-host;
- mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_mcu 21>,
- <&secure_proxy_mcu 23>;
- bootph-pre-ram;
- };
-};
-
-&mcu_timer0 {
- clock-frequency = <250000000>;
- bootph-pre-ram;
-};
-
-&secure_proxy_sa3 {
- bootph-pre-ram;
- status = "okay";
-};
-
-&secure_proxy_mcu {
- bootph-pre-ram;
- status = "okay";
-};
-
-&cbass_mcu_wakeup {
- sysctrler: sysctrler {
- compatible = "ti,am654-system-controller";
- mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>;
- mbox-names = "tx", "rx", "boot_notify";
- bootph-pre-ram;
- };
-};
-
-&sms {
- mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
- mbox-names = "tx", "rx", "notify";
- ti,host-id = <4>;
- ti,secure-host;
-};
-
-&mcu_ringacc {
- ti,sci = <&dm_tifs>;
-};
-
-&mcu_udmap {
- ti,sci = <&dm_tifs>;
-};
+#include "k3-j721s2-r5.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ tick-timer = &mcu_timer0;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 202 0>;
+ clocks = <&k3_clks 61 1>;
+ assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <2000000000>;
+ ti,sci = <&sms>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_mcu 21>,
+ <&secure_proxy_mcu 23>;
+ bootph-pre-ram;
+ };
+};
+
+&mcu_timer0 {
+ clock-frequency = <250000000>;
+ bootph-pre-ram;
+};
+
+&secure_proxy_sa3 {
+ bootph-pre-ram;
+ status = "okay";
+};
+
+&secure_proxy_mcu {
+ bootph-pre-ram;
+ status = "okay";
+};
+
+&cbass_mcu_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-pre-ram;
+ };
+};
+
+&sms {
+ mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SoM: https://www.ti.com/lit/zip/sprr439
- *
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-j721s2.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- memory@80000000 {
- device_type = "memory";
- /* 16 GB RAM */
- reg = <0x00 0x80000000 0x00 0x80000000>,
- <0x08 0x80000000 0x03 0x80000000>;
- };
-
- /* Reserving memory regions still pending */
- reserved_memory: reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>;
- alignment = <0x1000>;
- no-map;
- };
-
- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0000000 0x00 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0100000 0x00 0xf00000>;
- no-map;
- };
-
- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1000000 0x00 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa4000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa4100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa5000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa5100000 0x00 0xf00000>;
- no-map;
- };
-
- c71_0_dma_memory_region: c71-dma-memory@a6000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa6000000 0x00 0x100000>;
- no-map;
- };
-
- c71_0_memory_region: c71-memory@a6100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa6100000 0x00 0xf00000>;
- no-map;
- };
-
- c71_1_dma_memory_region: c71-dma-memory@a7000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa7000000 0x00 0x100000>;
- no-map;
- };
-
- c71_1_memory_region: c71-memory@a7100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa7100000 0x00 0xf00000>;
- no-map;
- };
-
- rtos_ipc_memory_region: ipc-memories@a8000000 {
- reg = <0x00 0xa8000000 0x00 0x01c00000>;
- alignment = <0x1000>;
- no-map;
- };
- };
-
- mux0: mux-controller {
- compatible = "gpio-mux";
- #mux-state-cells = <1>;
- mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
- };
-
- mux1: mux-controller {
- compatible = "gpio-mux";
- #mux-state-cells = <1>;
- mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
- };
-
- transceiver0: can-phy0 {
- /* standby pin has been grounded by default */
- compatible = "ti,tcan1042";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- };
-};
-
-&wkup_pmx0 {
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
- J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
- J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
- J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
- J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
- J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
- J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
- J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
- J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
- J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
- J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
- J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
- >;
- };
-};
-
-&wkup_pmx2 {
- wkup_i2c0_pins_default: wkup-i2c0-default-pins {
- pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
- J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
- >;
- };
-};
-
-&main_pmx0 {
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
- J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
- >;
- };
-
- main_mcan16_pins_default: main-mcan16-default-pins {
- pinctrl-single,pins = <
- J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
- J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
- >;
- };
-};
-
-&wkup_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- eeprom@50 {
- /* CAV24C256WE-GT3 */
- compatible = "atmel,24c256";
- reg = <0x50>;
- };
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- exp_som: gpio@21 {
- compatible = "ti,tca6408";
- reg = <0x21>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
- "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
- "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
- "GPIO_LIN_EN", "CAN_STB";
- };
-};
-
-&main_mcan16 {
- status = "okay";
- pinctrl-0 = <&main_mcan16_pins_default>;
- pinctrl-names = "default";
- phys = <&transceiver0>;
-};
-
-&ospi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <25000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <4>;
- };
-};
-
-&mailbox0_cluster0 {
- status = "okay";
- interrupts = <436>;
- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster1 {
- status = "okay";
- interrupts = <432>;
- mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster2 {
- status = "okay";
- interrupts = <428>;
- mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mailbox0_cluster4 {
- status = "okay";
- interrupts = <420>;
- mbox_c71_0: mbox-c71-0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-
- mbox_c71_1: mbox-c71-1 {
- ti,mbox-rx = <2 0 0>;
- ti,mbox-tx = <3 0 0>;
- };
-};
-
-&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
- memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
- <&mcu_r5fss0_core0_memory_region>;
-};
-
-&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
- memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
- <&mcu_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
- memory-region = <&main_r5fss0_core0_dma_memory_region>,
- <&main_r5fss0_core0_memory_region>;
-};
-
-&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
- memory-region = <&main_r5fss0_core1_dma_memory_region>,
- <&main_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
- memory-region = <&main_r5fss1_core0_dma_memory_region>,
- <&main_r5fss1_core0_memory_region>;
-};
-
-&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
- memory-region = <&main_r5fss1_core1_dma_memory_region>,
- <&main_r5fss1_core1_memory_region>;
-};
-
-&c71_0 {
- status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
- memory-region = <&c71_0_dma_memory_region>,
- <&c71_0_memory_region>;
-};
-
-&c71_1 {
- status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
- memory-region = <&c71_1_dma_memory_region>,
- <&c71_1_memory_region>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-
-#include <dt-bindings/thermal/thermal.h>
-
-wkup0_thermal: wkup0-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 0>;
-
- trips {
- wkup0_crit: wkup0-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
-};
-
-wkup1_thermal: wkup1-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 1>;
-
- trips {
- wkup1_crit: wkup1-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
-};
-
-main0_thermal: main0-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 2>;
-
- trips {
- main0_crit: main0-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
-};
-
-main1_thermal: main1-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 3>;
-
- trips {
- main1_crit: main1-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
-};
-
-main2_thermal: main2-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 4>;
-
- trips {
- main2_crit: main2-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
-};
-
-main3_thermal: main3-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 5>;
-
- trips {
- main3_crit: main3-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
-};
-
-main4_thermal: main4-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 6>;
-
- trips {
- main4_crit: main4-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for J721S2 SoC Family
- *
- * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28
- *
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
- *
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/ti,sci_pm_domain.h>
-
-#include "k3-pinctrl.h"
-
-/ {
-
- model = "Texas Instruments K3 J721S2 SoC";
- compatible = "ti,j721s2";
- interrupt-parent = <&gic500>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu-map {
- cluster0: cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
-
- core1 {
- cpu = <&cpu1>;
- };
- };
- };
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a72";
- reg = <0x000>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_0>;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a72";
- reg = <0x001>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_0>;
- };
- };
-
- L2_0: l2-cache0 {
- compatible = "cache";
- cache-unified;
- cache-level = <2>;
- cache-size = <0x100000>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- next-level-cache = <&msmc_l3>;
- };
-
- msmc_l3: l3-cache0 {
- compatible = "cache";
- cache-level = <3>;
- cache-unified;
- };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- psci: psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
- };
-
- a72_timer0: timer-cl0-cpu0 {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
-
- };
-
- pmu: pmu {
- compatible = "arm,cortex-a72-pmu";
- /* Recommendation from GIC500 TRM Table A.3 */
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cbass_main: bus@100000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
- <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
- <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
- <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/
- <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
- <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
- <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
- <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
- <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
- <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
- <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
- <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
-
- /* MCUSS_WKUP Range */
- <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
- <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
- <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
- <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
-
- cbass_mcu_wakeup: bus@28380000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
- <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
- <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
- <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
-
- };
-
- };
-
- thermal_zones: thermal-zones {
- #include "k3-j721s2-thermal.dtsi"
- };
-};
-
-/* Now include peripherals from each bus segment */
-#include "k3-j721s2-main.dtsi"
-#include "k3-j721s2-mcu-wakeup.dtsi"
aliases {
/delete-property/ serial1;
/delete-property/ serial2;
+ /delete-property/ mmc1;
+ /delete-property/ mmc2;
};
ethernet@08000000 {
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-
-/dts-v1/;
-
-#include "omap34xx.dtsi"
-#include "logicpd-som-lv.dtsi"
-#include "logicpd-som-lv-baseboard.dtsi"
-#include "omap-gpmc-smsc9221.dtsi"
-
-/ {
- model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit";
- compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3";
-};
-
-&omap3_pmx_core2 {
-
- hsusb2_2_pins: pinmux_hsusb2_2_pins {
- pinctrl-single,pins = <
- OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
- OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
- OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
- OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
- OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
- OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
- >;
- };
-};
aliases {
/delete-property/ serial1;
/delete-property/ serial2;
+ /delete-property/ mmc1;
+ /delete-property/ mmc2;
};
ethernet@08000000 {
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-
-/dts-v1/;
-
-#include "omap36xx.dtsi"
-#include "logicpd-som-lv.dtsi"
-#include "logicpd-som-lv-baseboard.dtsi"
-#include "omap-gpmc-smsc9221.dtsi"
-
-/ {
- model = "LogicPD Zoom DM3730 SOM-LV Development Kit";
- compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3";
-};
-
-&omap3_pmx_core2 {
-
- hsusb2_2_pins: pinmux_hsusb2_2_pins {
- pinctrl-single,pins = <
- OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
- OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
- OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
- OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
- OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
- >;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-
-/ {
- gpio_keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_key_pins>;
-
- sysboot2 {
- label = "gpio3";
- gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* gpio_111 / uP_GPIO_3 */
- linux,code = <BTN_0>;
- wakeup-source;
- };
- };
-
- sound {
- compatible = "ti,omap-twl4030";
- ti,model = "omap3logic";
- ti,mcbsp = <&mcbsp2>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins &led_pins_wkup>;
-
- led1 {
- label = "led1";
- gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* gpio133 */
- linux,default-trigger = "cpu0";
- };
-
- led2 {
- label = "led2";
- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* gpio11 */
- linux,default-trigger = "none";
- };
- };
-};
-
-&vaux1 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
-};
-
-&vaux4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-};
-
-&mcbsp2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp2_pins>;
-};
-
-&charger {
- ti,bb-uvolt = <3200000>;
- ti,bb-uamp = <150>;
-};
-
-&gpmc {
- ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */
- 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */
- 2 0 0x10000000 0x2000000>; /* CS2: 32MB for NOR */
-
- ethernet@gpmc {
- pinctrl-names = "default";
- pinctrl-0 = <&lan9221_pins>;
- interrupt-parent = <&gpio5>;
- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; /* gpio_152 */
- reg = <1 0 0xff>;
- };
-};
-
-&vpll2 {
- regulator-always-on;
-};
-
-&dss {
- status = "okay";
- vdds_dsi-supply = <&vpll2>;
- vdda_video-supply = <&video_reg>;
- pinctrl-names = "default";
- pinctrl-0 = <&dss_dpi_pins1>;
- port {
- dpi_out: endpoint {
- remote-endpoint = <&lcd_in>;
- data-lines = <16>;
- };
- };
-};
-
-/ {
- aliases {
- display0 = &lcd0;
- };
-
- video_reg: video_reg {
- compatible = "regulator-fixed";
- regulator-name = "fixed-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- lcd0: display {
- /* This isn't the exact LCD, but the timings meet spec */
- compatible = "logicpd,type28";
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_enable_pin>;
- backlight = <&bl>;
- enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
- port {
- lcd_in: endpoint {
- remote-endpoint = <&dpi_out>;
- };
- };
- };
-
- bl: backlight {
- compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&backlight_pins>;
- pwms = <&twl_pwm 0 5000000>;
- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
- default-brightness-level = <7>;
- enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* gpio_8 */
- };
-};
-
-&mmc1 {
- interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
- wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
- cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */
- vmmc-supply = <&vmmc1>;
- bus-width = <4>;
- cap-power-off-card;
-};
-
-&omap3_pmx_core {
- gpio_key_pins: pinmux_gpio_key_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_xclkb.gpio_111 / uP_GPIO_3*/
- >;
- };
-
- led_pins: pinmux_led_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */
- >;
- };
-
- lan9221_pins: pinmux_lan9221_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */
- >;
- };
-
- mmc1_pins: pinmux_mmc1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
- OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 */
- OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */
- >;
- };
-
- lcd_enable_pin: pinmux_lcd_enable_pin {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */
- >;
- };
-
- dss_dpi_pins1: pinmux_dss_dpi_pins1 {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */
- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */
- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */
- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */
-
- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data0.dss_data0 */
- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data1.dss_data1 */
- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data2.dss_data2 */
- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data3.dss_data3 */
- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data4.dss_data4 */
- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data5.dss_data5 */
- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */
- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */
- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */
- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */
- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */
- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */
- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */
- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */
- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */
- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */
- >;
- };
-};
-
-&omap3_pmx_wkup {
- led_pins_wkup: pinmux_led_pins_wkup {
- pinctrl-single,pins = <
- OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 / uP_GPIO_1 */
- >;
- };
-
- backlight_pins: pinmux_backlight_pins {
- pinctrl-single,pins = <
- OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */
- >;
- };
-};
-
-
-&uart1 {
- interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
-};
-
-/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */
-&usb_otg_hs {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb_otg_pins>;
- interface-type = <0>;
- usb-phy = <&usb2_phy>;
- phys = <&usb2_phy>;
- phy-names = "usb2-phy";
- mode = <3>;
- power = <50>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <dt-bindings/input/input.h>
-
-/ {
- cpus {
- cpu@0 {
- cpu0-supply = <&vcc>;
- };
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0>;
- };
-
- wl12xx_vmmc: wl12xx_vmmc {
- compatible = "regulator-fixed";
- regulator-name = "vwl1271";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio1 3 0>; /* gpio_3 */
- startup-delay-us = <70000>;
- enable-active-high;
- vin-supply = <&vaux3>;
- };
-
- /* HS USB Host PHY on PORT 1 */
- hsusb2_phy: hsusb2_phy {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb2_reset_pin>;
- compatible = "usb-nop-xceiv";
- reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
- #phy-cells = <0>;
- };
-
- /* fixed 26MHz oscillator */
- hfclk_26m: oscillator {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- };
-};
-
-&gpmc {
- ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
-
- nand@0,0 {
- compatible = "ti,omap2-nand";
- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
- interrupt-parent = <&gpmc>;
- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
- <1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name = "micron,mt29f4g16abbda3w";
- nand-bus-width = <16>;
- ti,nand-ecc-opt = "bch8";
- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
- gpmc,sync-clk-ps = <0>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <44>;
- gpmc,cs-wr-off-ns = <44>;
- gpmc,adv-on-ns = <6>;
- gpmc,adv-rd-off-ns = <34>;
- gpmc,adv-wr-off-ns = <44>;
- gpmc,we-off-ns = <40>;
- gpmc,oe-off-ns = <54>;
- gpmc,access-ns = <64>;
- gpmc,rd-cycle-ns = <82>;
- gpmc,wr-cycle-ns = <82>;
- gpmc,wr-access-ns = <40>;
- gpmc,wr-data-mux-bus-ns = <0>;
- gpmc,device-width = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- clock-frequency = <2600000>;
-
- twl: twl@48 {
- reg = <0x48>;
- interrupts = <7>; /* SYS_NIRQ cascaded to intc */
- interrupt-parent = <&intc>;
- clocks = <&hfclk_26m>;
- clock-names = "fck";
- twl_audio: audio {
- compatible = "ti,twl4030-audio";
- codec {
- ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
- };
- };
- };
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- clock-frequency = <400000>;
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins>;
- clock-frequency = <400000>;
-
- touchscreen: tsc2004@48 {
- compatible = "ti,tsc2004";
- reg = <0x48>;
- vio-supply = <&vaux1>;
- pinctrl-names = "default";
- pinctrl-0 = <&tsc2004_pins>;
- interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */
-
- touchscreen-fuzz-x = <4>;
- touchscreen-fuzz-y = <7>;
- touchscreen-fuzz-pressure = <2>;
- touchscreen-size-x = <4096>;
- touchscreen-size-y = <4096>;
- touchscreen-max-pressure = <2048>;
-
- ti,x-plate-ohms = <280>;
- ti,esd-recovery-timeout-ms = <8000>;
- };
-};
-
-&mmc3 {
- interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
- pinctrl-0 = <&mmc3_pins &wl127x_gpio>;
- pinctrl-names = "default";
- vmmc-supply = <&wl12xx_vmmc>;
- non-removable;
- bus-width = <4>;
- cap-power-off-card;
- #address-cells = <1>;
- #size-cells = <0>;
- wlcore: wlcore@2 {
- compatible = "ti,wl1273";
- reg = <2>;
- interrupt-parent = <&gpio1>;
- interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 2 */
- ref-clock-frequency = <26000000>;
- };
-};
-
-&usbhshost {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb2_pins>, <&hsusb2_2_pins>;
- port2-mode = "ehci-phy";
-};
-
-&usbhsehci {
- phys = <0 &hsusb2_phy>;
-};
-
-
-&omap3_pmx_core {
-
- mmc3_pins: pinmux_mm3_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */
- OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */
- OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */
- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */
- OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
- OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */
- >;
- };
-
- mcbsp2_pins: pinmux_mcbsp2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */
- OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */
- OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */
- OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */
- >;
- };
- uart2_pins: pinmux_uart2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
- OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */
- >;
- };
-
- mcspi1_pins: pinmux_mcspi1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
- OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
- OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
- OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
- >;
- };
-
- hsusb2_pins: pinmux_hsusb2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
- OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
- OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
- OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
- >;
- };
-
- hsusb_otg_pins: pinmux_hsusb_otg_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
- OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
- OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
- OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
- OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
- OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
- OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
- OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
- OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
- OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
- OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
- OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
- >;
- };
-
- i2c1_pins: pinmux_i2c1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
- OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
- OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
- >;
- };
-
- i2c2_pins: pinmux_i2c2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
- OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
- >;
- };
-
- i2c3_pins: pinmux_i2c3_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
- >;
- };
-
- tsc2004_pins: pinmux_tsc2004_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */
- >;
- };
-};
-
-&omap3_pmx_wkup {
-
- hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
- pinctrl-single,pins = <
- OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */
- >;
- };
-
- wl127x_gpio: pinmux_wl127x_gpio_pin {
- pinctrl-single,pins = <
- OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
- OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
- >;
- };
-};
-
-&uart2 {
- interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-};
-
-&mcspi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcspi1_pins>;
-};
-
-#include "twl4030.dtsi"
-#include "twl4030_omap3.dtsi"
-
-&vaux3 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
-};
-
-&twl {
- twl_power: power {
- compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
- ti,use_poweroff;
- };
-};
-
-&twl_gpio {
- ti,use-leds;
-};
aliases {
/delete-property/ serial1;
/delete-property/ serial2;
+ /delete-property/ mmc1;
+ /delete-property/ mmc2;
};
ethernet@08000000 {
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-
-/dts-v1/;
-
-#include "omap34xx.dtsi"
-#include "logicpd-torpedo-som.dtsi"
-#include "logicpd-torpedo-baseboard.dtsi"
-#include "omap-gpmc-smsc9221.dtsi"
-
-/ {
- model = "LogicPD Zoom OMAP35xx Torpedo Development Kit";
- compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3430", "ti,omap3";
-};
-
-&omap3_pmx_core {
- isp1763_pins: pinmux_isp1763_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat6.gpio_128 */
- >;
- };
-};
aliases {
/delete-property/ serial1;
/delete-property/ serial2;
+ /delete-property/ mmc1;
+ /delete-property/ mmc2;
};
ethernet@08000000 {
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-
-/dts-v1/;
-
-#include "omap36xx.dtsi"
-#include "logicpd-torpedo-som.dtsi"
-#include "omap-gpmc-smsc9221.dtsi"
-#include "logicpd-torpedo-baseboard.dtsi"
-
-/ {
- model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit";
- compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3";
-
- wl12xx_vmmc: wl12xx_vmmc {
- compatible = "regulator-fixed";
- regulator-name = "vwl1271";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio5 29 0>; /* gpio157 */
- startup-delay-us = <70000>;
- enable-active-high;
- vin-supply = <&vmmc2>;
- };
-};
-
-/*
- * Only found on the wireless SOM. For the SOM without wireless, the pins for
- * MMC3 can be routed with jumpers to the second MMC slot on the devkit and
- * gpio157 is not connected. So this should be OK to keep common for now,
- * probably device tree overlays is the way to go with the various SOM and
- * jumpering combinations for the long run.
- */
-&mmc3 {
- interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
- pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>;
- pinctrl-names = "default";
- vmmc-supply = <&wl12xx_vmmc>;
- non-removable;
- bus-width = <4>;
- cap-power-off-card;
- #address-cells = <1>;
- #size-cells = <0>;
- wlcore: wlcore@2 {
- compatible = "ti,wl1283";
- reg = <2>;
- interrupt-parent = <&gpio5>;
- interrupts = <24 IRQ_TYPE_EDGE_RISING>; /* gpio 152 */
- ref-clock-frequency = <26000000>;
- tcxo-clock-frequency = <26000000>;
- };
-};
-
-&uart2 {
- /delete-property/dma-names;
- bluetooth {
- compatible = "ti,wl1283-st";
- enable-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio 162 */
- max-speed = <3000000>;
- };
-};
-
-/* The DM3730 has a faster L3 than OMAP35, so increase pixel clock */
-&mt9p031_out {
- pixel-clock-frequency = <90000000>;
-};
-
-&omap3_pmx_core {
- mmc3_pins: pinmux_mm3_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */
- OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */
- OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */
- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */
- OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */
- OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr.gpio_157 */
- >;
- };
-};
-
-&omap3_pmx_core2 {
- mmc3_core2_pins: pinmux_mmc3_core2_pins {
- pinctrl-single,pins = <
- OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */
- OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */
- >;
- };
-};
-
-/* The gpio muxing between omap3530 and dm3730 is different for GPIO_128 */
-&omap3_pmx_wkup {
- isp1763_pins: pinmux_isp1763_pins {
- pinctrl-single,pins = <
- OMAP3_WKUP_IOPAD(0x2a58, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_128 */
- >;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-
-/ {
- gpio_keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_key_pins &gpio_key_pins_wkup>;
-
- sysboot2 {
- label = "sysboot2";
- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* gpio2 */
- linux,code = <BTN_0>;
- wakeup-source;
- };
-
- sysboot5 {
- label = "sysboot5";
- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; /* gpio7 */
- linux,code = <BTN_1>;
- wakeup-source;
- };
-
- gpio1 {
- label = "gpio1";
- gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; /* gpio181 */
- linux,code = <BTN_2>;
- wakeup-source;
- };
-
- gpio2 {
- label = "gpio2";
- gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; /* gpio178 */
- linux,code = <BTN_3>;
- wakeup-source;
- };
- };
-
- sound {
- compatible = "ti,omap-twl4030";
- ti,model = "omap3logic";
- ti,mcbsp = <&mcbsp2>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins>;
-
- led1 {
- label = "led1";
- gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; /* gpio180 */
- linux,default-trigger = "cpu0";
- };
-
- led2 {
- label = "led2";
- gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; /* gpio179 */
- linux,default-trigger = "none";
- };
- };
-
- pwm10: dmtimer-pwm {
- compatible = "ti,omap-dmtimer-pwm";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm_pins>;
- ti,timers = <&timer10>;
- #pwm-cells = <3>;
- ti,clock-source = <0x01>;
- };
-
-};
-
-&vaux1 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
-};
-
-&vaux4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-};
-
-&mcbsp2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp2_pins>;
- status = "okay";
-};
-
-&charger {
- ti,bb-uvolt = <3200000>;
- ti,bb-uamp = <150>;
-};
-
-&gpmc {
- ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */
- 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */
- 6 0 0x28000000 0x1000000>; /* CS6: 16MB for ISP1763 */
-
- ethernet@gpmc {
- pinctrl-names = "default";
- pinctrl-0 = <&lan9221_pins>;
- interrupt-parent = <&gpio5>;
- interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* gpio129 */
- reg = <1 0 0xff>;
- };
-
- usb@6,0 {
- pinctrl-names = "default";
- pinctrl-0 = <&isp1763_pins>;
- compatible = "nxp,usb-isp1763";
- reg = <0x6 0x0 0xff>;
- interrupt-parent = <&gpio5>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "host";
- bus-width = <16>;
- dr_mode = "host";
- gpmc,mux-add-data = <0>;
- gpmc,device-width = <2>;
- gpmc,wait-pin = <0>;
- gpmc,burst-length = <4>;
- gpmc,cycle2cycle-samecsen = <1>;
- gpmc,cycle2cycle-diffcsen = <1>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <45>;
- gpmc,cs-wr-off-ns = <45>;
- gpmc,adv-on-ns = <0>;
- gpmc,adv-rd-off-ns = <0>;
- gpmc,adv-wr-off-ns = <0>;
- gpmc,oe-on-ns = <0>;
- gpmc,oe-off-ns = <45>;
- gpmc,we-on-ns = <0>;
- gpmc,we-off-ns = <25>;
- gpmc,rd-cycle-ns = <60>;
- gpmc,wr-cycle-ns = <45>;
- gpmc,access-ns = <35>;
- gpmc,page-burst-access-ns = <0>;
- gpmc,bus-turnaround-ns = <0>;
- gpmc,cycle2cycle-delay-ns = <60>;
- gpmc,wait-monitoring-ns = <0>;
- gpmc,clk-activation-ns = <0>;
- gpmc,wr-data-mux-bus-ns = <5>;
- gpmc,wr-access-ns = <20>;
- };
-};
-
-&hdqw1w {
- pinctrl-names = "default";
- pinctrl-0 = <&hdq_pins>;
-};
-
-
-&vpll2 {
- regulator-always-on;
-};
-
-&dss {
- status = "okay";
- vdds_dsi-supply = <&vpll2>;
- vdda_video-supply = <&vpll2>;
- pinctrl-names = "default";
- pinctrl-0 = <&dss_dpi_pins1>;
- port {
- dpi_out: endpoint {
- remote-endpoint = <&lcd_in>;
- data-lines = <16>;
- };
- };
-};
-
-/ {
- aliases {
- display0 = &lcd0;
- };
-
- lcd0: display {
- /* This isn't the exact LCD, but the timings meet spec */
- compatible = "newhaven,nhd-4.3-480272ef-atxl";
- label = "15";
- pinctrl-names = "default";
- pinctrl-0 = <&panel_pwr_pins>;
- backlight = <&bl>;
- enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
- port {
- lcd_in: endpoint {
- remote-endpoint = <&dpi_out>;
- };
- };
- };
-
- bl: backlight {
- compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&backlight_pins>;
- pwms = <&pwm10 0 5000000 0>;
- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
- default-brightness-level = <7>;
- enable-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */
- };
-};
-
-&mmc1 {
- interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins &mmc1_cd>;
- cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */
- vmmc-supply = <&vmmc1>;
- bus-width = <4>;
- cap-power-off-card;
-};
-
-&omap3_pmx_core {
- gpio_key_pins: pinmux_gpio_key_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_clk.gpio_178 */
- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 */
- >;
- };
-
- hdq_pins: hdq_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */
- >;
- };
-
- pwm_pins: pinmux_pwm_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */
- >;
- };
-
- led_pins: pinmux_led_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */
- OMAP3_CORE1_IOPAD(0x21da, PIN_OUTPUT | MUX_MODE4) /* gpio_180 */
- >;
- };
-
- mmc1_pins: pinmux_mmc1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
- >;
- };
-
- tsc2004_pins: pinmux_tsc2004_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */
- >;
- };
-
- backlight_pins: pinmux_backlight_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */
- >;
- };
-
- isp_pins: pinmux_isp_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */
- OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */
- OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */
- OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */
-
- OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */
- OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */
- OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */
- OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */
- OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */
- OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */
- OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6.cam_d6 */
- OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */
- >;
- };
-
- panel_pwr_pins: pinmux_panel_pwr_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */
- >;
- };
-
- dss_dpi_pins1: pinmux_dss_dpi_pins1 {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */
- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */
- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */
- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */
-
- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */
- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */
- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */
- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */
- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */
- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */
- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */
- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */
- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */
- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */
- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data16.dss_data16 */
- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data17.dss_data17 */
-
- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data18.dss_data0 */
- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data19.dss_data1 */
- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data20.dss_data2 */
- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data21.dss_data3 */
- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data22.dss_data4 */
- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data23.dss_data5 */
- >;
- };
-};
-
-&omap3_pmx_wkup {
- gpio_key_pins_wkup: pinmux_gpio_key_pins_wkup {
- pinctrl-single,pins = <
- OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot0.gpio_2 */
- OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot5.gpio_7 */
- >;
- };
-
- lan9221_pins: pinmux_lan9221_pins {
- pinctrl-single,pins = <
- OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */
- >;
- };
-
- mmc1_cd: pinmux_mmc1_cd {
- pinctrl-single,pins = <
- OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */
- >;
- };
-};
-
-&i2c2 {
- mt9p031@48 {
- compatible = "aptina,mt9p031";
- reg = <0x48>;
- clocks = <&isp 0>;
- vaa-supply = <&vaux4>;
- vdd-supply = <&vaux4>;
- vdd_io-supply = <&vaux4>;
- port {
- mt9p031_out: endpoint {
- input-clock-frequency = <24000000>;
- pixel-clock-frequency = <72000000>;
- remote-endpoint = <&ccdc_ep>;
- };
- };
- };
-};
-
-&i2c3 {
- touchscreen: tsc2004@48 {
- compatible = "ti,tsc2004";
- reg = <0x48>;
- vio-supply = <&vaux1>;
- pinctrl-names = "default";
- pinctrl-0 = <&tsc2004_pins>;
- interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */
-
- touchscreen-fuzz-x = <4>;
- touchscreen-fuzz-y = <7>;
- touchscreen-fuzz-pressure = <2>;
- touchscreen-size-x = <4096>;
- touchscreen-size-y = <4096>;
- touchscreen-max-pressure = <2048>;
-
- ti,x-plate-ohms = <280>;
- ti,esd-recovery-timeout-ms = <8000>;
- };
-};
-
-&mcspi1 {
- at25@0 {
- compatible = "atmel,at25";
- reg = <0>;
- spi-max-frequency = <5000000>;
- spi-cpha;
- spi-cpol;
-
- pagesize = <64>;
- size = <32768>;
- address-width = <16>;
- };
-};
-
-&isp {
- pinctrl-names = "default";
- pinctrl-0 = <&isp_pins>;
- ports {
- port@0 {
- reg = <0>;
- ccdc_ep: endpoint {
- remote-endpoint = <&mt9p031_out>;
- bus-width = <8>;
- hsync-active = <1>;
- vsync-active = <1>;
- pclk-sample = <0>;
- };
- };
- };
-};
-
-&uart1 {
- interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
-};
-
-/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */
-&usb_otg_hs {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb_otg_pins>;
- interface-type = <0>;
- usb-phy = <&usb2_phy>;
- phys = <&usb2_phy>;
- phy-names = "usb2-phy";
- mode = <3>;
- power = <50>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <dt-bindings/input/input.h>
-
-/ {
- chosen {
- stdout-path = &uart1;
- };
-
- cpus {
- cpu@0 {
- cpu0-supply = <&vcc>;
- };
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0>;
- };
-
- leds {
- compatible = "gpio-leds";
- user0 {
- label = "user0";
- gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
- linux,default-trigger = "none";
- };
- };
-
- /* fixed 26MHz oscillator */
- hfclk_26m: oscillator {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- };
-};
-
-/* The Torpedo doesn't route the USB host pins */
-&usbhshost {
- status = "disabled";
-};
-
-&gpmc {
- ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
-
- nand@0,0 {
- compatible = "ti,omap2-nand";
- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
- interrupt-parent = <&gpmc>;
- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
- <1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name = "micron,mt29f4g16abbda3w";
- nand-bus-width = <16>;
- ti,nand-ecc-opt = "bch8";
- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
- gpmc,sync-clk-ps = <0>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <44>;
- gpmc,cs-wr-off-ns = <44>;
- gpmc,adv-on-ns = <6>;
- gpmc,adv-rd-off-ns = <34>;
- gpmc,adv-wr-off-ns = <44>;
- gpmc,we-off-ns = <40>;
- gpmc,oe-off-ns = <54>;
- gpmc,access-ns = <64>;
- gpmc,rd-cycle-ns = <82>;
- gpmc,wr-cycle-ns = <82>;
- gpmc,wr-access-ns = <40>;
- gpmc,wr-data-mux-bus-ns = <0>;
- gpmc,device-width = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- clock-frequency = <2600000>;
-
- twl: twl@48 {
- reg = <0x48>;
- interrupts = <7>; /* SYS_NIRQ cascaded to intc */
- interrupt-parent = <&intc>;
- clocks = <&hfclk_26m>;
- clock-names = "fck";
-
- twl_audio: audio {
- compatible = "ti,twl4030-audio";
- codec {
- };
- };
- };
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- clock-frequency = <400000>;
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins>;
- clock-frequency = <400000>;
- at24@50 {
- compatible = "atmel,24c64";
- readonly;
- reg = <0x50>;
- };
-};
-
-&omap3_pmx_core {
- mcbsp2_pins: pinmux_mcbsp2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */
- OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */
- OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */
- OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */
- >;
- };
- uart2_pins: pinmux_uart2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
- OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */
- >;
- };
- mcspi1_pins: pinmux_mcspi1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
- OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
- OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
- OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
- >;
- };
- hsusb_otg_pins: pinmux_hsusb_otg_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
- OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
- OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
- OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
-
- OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
- OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
- OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
- OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
- OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
- OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
- OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
- OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
- >;
- };
- i2c1_pins: pinmux_i2c1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
- OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
- >;
- };
- i2c2_pins: pinmux_i2c2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
- OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
- >;
- };
- i2c3_pins: pinmux_i2c3_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
- >;
- };
-};
-
-&uart2 {
- interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-};
-
-&mcspi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcspi1_pins>;
-};
-
-#include "twl4030.dtsi"
-#include "twl4030_omap3.dtsi"
-
-&twl {
- twl_power: power {
- compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
- ti,use_poweroff;
- };
-};
-
-&twl_gpio {
- ti,use-leds;
-};
-
-&twl_keypad {
- status = "disabled";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Common device tree for IGEP boards based on AM/DM37x
- *
- * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
- * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
- */
-/dts-v1/;
-
-#include "omap36xx.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x20000000>; /* 512 MB */
- };
-
- chosen {
- stdout-path = &uart3;
- };
-
- sound {
- compatible = "ti,omap-twl4030";
- ti,model = "igep2";
- ti,mcbsp = <&mcbsp2>;
- };
-
- vdd33: regulator-vdd33 {
- compatible = "regulator-fixed";
- regulator-name = "vdd33";
- regulator-always-on;
- };
-
-};
-
-&omap3_pmx_core {
- gpmc_pins: pinmux_gpmc_pins {
- pinctrl-single,pins = <
- /* OneNAND seems to require PIN_INPUT on clock. */
- OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
- >;
- };
-
- uart1_pins: pinmux_uart1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
- OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
- >;
- };
-
- uart3_pins: pinmux_uart3_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
- >;
- };
-
- mcbsp2_pins: pinmux_mcbsp2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
- OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
- OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
- OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
- >;
- };
-
- mmc1_pins: pinmux_mmc1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
- >;
- };
-
- mmc2_pins: pinmux_mmc2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
- >;
- };
-
- i2c1_pins: pinmux_i2c1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
- OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
- >;
- };
-
- i2c3_pins: pinmux_i2c3_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
- >;
- };
-};
-
-&gpmc {
- pinctrl-names = "default";
- pinctrl-0 = <&gpmc_pins>;
-
- nand@0,0 {
- compatible = "ti,omap2-nand";
- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
- interrupt-parent = <&gpmc>;
- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
- <1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name = "micron,mt29c4g96maz";
- nand-bus-width = <16>;
- gpmc,device-width = <2>;
- ti,nand-ecc-opt = "bch8";
-
- gpmc,sync-clk-ps = <0>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <44>;
- gpmc,cs-wr-off-ns = <44>;
- gpmc,adv-on-ns = <6>;
- gpmc,adv-rd-off-ns = <34>;
- gpmc,adv-wr-off-ns = <44>;
- gpmc,we-off-ns = <40>;
- gpmc,oe-off-ns = <54>;
- gpmc,access-ns = <64>;
- gpmc,rd-cycle-ns = <82>;
- gpmc,wr-cycle-ns = <82>;
- gpmc,wr-access-ns = <40>;
- gpmc,wr-data-mux-bus-ns = <0>;
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- status = "okay";
- };
-
- onenand@0,0 {
- compatible = "ti,omap2-onenand";
- reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
-
- gpmc,sync-read;
- gpmc,sync-write;
- gpmc,burst-length = <16>;
- gpmc,burst-wrap;
- gpmc,burst-read;
- gpmc,burst-write;
- gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
- gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <96>;
- gpmc,cs-wr-off-ns = <96>;
- gpmc,adv-on-ns = <0>;
- gpmc,adv-rd-off-ns = <12>;
- gpmc,adv-wr-off-ns = <12>;
- gpmc,oe-on-ns = <18>;
- gpmc,oe-off-ns = <96>;
- gpmc,we-on-ns = <0>;
- gpmc,we-off-ns = <96>;
- gpmc,rd-cycle-ns = <114>;
- gpmc,wr-cycle-ns = <114>;
- gpmc,access-ns = <90>;
- gpmc,page-burst-access-ns = <12>;
- gpmc,bus-turnaround-ns = <0>;
- gpmc,cycle2cycle-delay-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
- gpmc,clk-activation-ns = <6>;
- gpmc,wr-data-mux-bus-ns = <30>;
- gpmc,wr-access-ns = <90>;
- gpmc,sync-clk-ps = <12000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- status = "disabled";
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- clock-frequency = <2600000>;
-
- twl: twl@48 {
- reg = <0x48>;
- interrupts = <7>; /* SYS_NIRQ cascaded to intc */
- interrupt-parent = <&intc>;
-
- twl_audio: audio {
- compatible = "ti,twl4030-audio";
- codec {
- };
- };
- };
-};
-
-#include "twl4030.dtsi"
-#include "twl4030_omap3.dtsi"
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins>;
-};
-
-&mcbsp2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp2_pins>;
- status = "okay";
-};
-
-&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
- vmmc-supply = <&vmmc1>;
- vmmc_aux-supply = <&vsim>;
- bus-width = <4>;
- cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
-};
-
-&mmc3 {
- status = "disabled";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
-
-&twl_gpio {
- ti,use-leds;
-};
-
-&usb_otg_hs {
- interface-type = <0>;
- usb-phy = <&usb2_phy>;
- phys = <&usb2_phy>;
- phy-names = "usb2-phy";
- mode = <3>;
- power = <50>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Common Device Tree Source for IGEPv2
- *
- * Copyright (C) 2014 Javier Martinez Canillas <javier@dowhile0.org>
- * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
- */
-
-#include "omap3-igep.dtsi"
-#include "omap-gpmc-smsc9221.dtsi"
-
-/ {
-
- leds {
- pinctrl-names = "default";
- pinctrl-0 = <&leds_pins>;
- compatible = "gpio-leds";
-
- boot {
- label = "omap3:green:boot";
- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- user0 {
- label = "omap3:red:user0";
- gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- user1 {
- label = "omap3:red:user1";
- gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- user2 {
- label = "omap3:green:user1";
- gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
- };
- };
-
- /* HS USB Port 1 Power */
- hsusb1_power: hsusb1_power_reg {
- compatible = "regulator-fixed";
- regulator-name = "hsusb1_vbus";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
- startup-delay-us = <70000>;
- };
-
- /* HS USB Host PHY on PORT 1 */
- hsusb1_phy: hsusb1_phy {
- compatible = "usb-nop-xceiv";
- reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
- vcc-supply = <&hsusb1_power>;
- #phy-cells = <0>;
- };
-
- tfp410: encoder {
- compatible = "ti,tfp410";
- powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- tfp410_in: endpoint {
- remote-endpoint = <&dpi_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- tfp410_out: endpoint {
- remote-endpoint = <&dvi_connector_in>;
- };
- };
- };
- };
-
- dvi0: connector {
- compatible = "dvi-connector";
- label = "dvi";
-
- digital;
-
- ddc-i2c-bus = <&i2c3>;
-
- port {
- dvi_connector_in: endpoint {
- remote-endpoint = <&tfp410_out>;
- };
- };
- };
-};
-
-&omap3_pmx_core {
- pinctrl-names = "default";
- pinctrl-0 = <
- &tfp410_pins
- &dss_dpi_pins
- >;
-
- tfp410_pins: pinmux_tfp410_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
- >;
- };
-
- dss_dpi_pins: pinmux_dss_dpi_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
- OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
- OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
- OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
- OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
- OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
- OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
- >;
- };
-
- uart2_pins: pinmux_uart2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
- >;
- };
-
- smsc9221_pins: pinmux_smsc9221_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
- >;
- };
-};
-
-&omap3_pmx_core2 {
- pinctrl-names = "default";
- pinctrl-0 = <
- &hsusbb1_pins
- >;
-
- hsusbb1_pins: pinmux_hsusbb1_pins {
- pinctrl-single,pins = <
- OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
- OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
- OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
- OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
- OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
- OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
- OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
- OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
- OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
- OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
- OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
- OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
- >;
- };
-
- leds_pins: pinmux_leds_pins {
- pinctrl-single,pins = <
- OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
- OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
- OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
- >;
- };
-
- mmc1_wp_pins: pinmux_mmc1_cd_pins {
- pinctrl-single,pins = <
- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */
- >;
- };
-};
-
-&i2c3 {
- clock-frequency = <100000>;
-
- /*
- * Display monitor features are burnt in the EEPROM
- * as EDID data.
- */
- eeprom@50 {
- compatible = "ti,eeprom";
- reg = <0x50>;
- };
-};
-
-&gpmc {
- ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */
- <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */
-
- ethernet@gpmc {
- pinctrl-names = "default";
- pinctrl-0 = <&smsc9221_pins>;
- reg = <5 0 0xff>;
- interrupt-parent = <&gpio6>;
- interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-};
-
-&usbhshost {
- port1-mode = "ehci-phy";
-};
-
-&usbhsehci {
- phys = <&hsusb1_phy>;
-};
-
-&vpll2 {
- /* Needed for DSS */
- regulator-name = "vdds_dsi";
-};
-
-&dss {
- status = "okay";
-
- port {
- dpi_out: endpoint {
- remote-endpoint = <&tfp410_in>;
- data-lines = <24>;
- };
- };
-};
-
-&mmc1 {
- pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>;
- wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */
-};
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
*/
+#include "omap3-u-boot.dtsi"
+
/ {
chosen {
stdout-path = &uart3;
};
};
-
-&uart1 {
- reg-shift = <2>;
-};
-
-&uart2 {
- reg-shift = <2>;
-};
-
-&uart3 {
- reg-shift = <2>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
- *
- * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
- * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
- */
-
-#include "omap3-igep0020-common.dtsi"
-
-/ {
- model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
-
- vmmcsdio_fixed: fixedregulator-mmcsdio {
- compatible = "regulator-fixed";
- regulator-name = "vmmcsdio_fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- mmc2_pwrseq: mmc2_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */
- <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */
- };
-};
-
-&omap3_pmx_core {
- lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */
- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
- OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */
- >;
- };
-};
-
-/* On board Wifi module */
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
- vmmc-supply = <&vmmcsdio_fixed>;
- mmc-pwrseq = <&mmc2_pwrseq>;
- bus-width = <4>;
- non-removable;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2020, Compass Electronics Group, LLC
- */
-
-/dts-v1/;
-
-#include "r8a774a1.dtsi"
-#include "beacon-renesom-som.dtsi"
-#include "beacon-renesom-baseboard.dtsi"
-
-/ {
- model = "Beacon EmbeddedWorks RZ/G2M Development Kit";
- compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &iic_pmic;
- serial0 = &scif2;
- serial1 = &hscif0;
- serial2 = &hscif1;
- serial3 = &scif0;
- serial4 = &hscif2;
- serial5 = &scif5;
- ethernet0 = &avb;
- mmc0 = &sdhi3;
- mmc1 = &sdhi0;
- mmc2 = &sdhi2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@600000000 {
- device_type = "memory";
- reg = <0x6 0x00000000 0x0 0x80000000>;
- };
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>,
- <&versaclock5 1>,
- <&x302_clk>,
- <&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.2",
- "dclkin.0", "dclkin.1", "dclkin.2";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 connected to
- * sub board
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-#include "r8a774a1-hihope-rzg2m.dts"
-#include "hihope-rzg2-ex.dtsi"
-
-/ {
- model = "HopeRun HiHope RZ/G2M with sub board";
- compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
- "renesas,r8a774a1";
-};
-
-/* SW43 should be OFF, if in ON state SATA port will be activated */
-&pciec1 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 main board
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a774a1.dtsi"
-#include "hihope-rev4.dtsi"
-
-/ {
- model = "HopeRun HiHope RZ/G2M main board based on r8a774a1";
- compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1";
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-
- memory@600000000 {
- device_type = "memory";
- reg = <0x6 0x00000000 0x0 0x80000000>;
- };
-};
-
-&du {
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>,
- <&versaclock5 1>,
- <&x302_clk>,
- <&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.2",
- "dclkin.0", "dclkin.1", "dclkin.2";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the r8a774a1 SoC
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
-#include <dt-bindings/power/r8a774a1-sysc.h>
-
-#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4
-
-/ {
- compatible = "renesas,r8a774a1";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cluster0_opp: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- opp-suspend;
- };
- };
-
- cluster1_opp: opp-table-1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&a57_0>;
- };
- core1 {
- cpu = <&a57_1>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&a53_0>;
- };
- core1 {
- cpu = <&a53_1>;
- };
- core2 {
- cpu = <&a53_2>;
- };
- core3 {
- cpu = <&a53_3>;
- };
- };
- };
-
- a57_0: cpu@0 {
- compatible = "arm,cortex-a57";
- reg = <0x0>;
- device_type = "cpu";
- power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- dynamic-power-coefficient = <854>;
- clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <1024>;
- #cooling-cells = <2>;
- };
-
- a57_1: cpu@1 {
- compatible = "arm,cortex-a57";
- reg = <0x1>;
- device_type = "cpu";
- power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <1024>;
- #cooling-cells = <2>;
- };
-
- a53_0: cpu@100 {
- compatible = "arm,cortex-a53";
- reg = <0x100>;
- device_type = "cpu";
- power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- #cooling-cells = <2>;
- dynamic-power-coefficient = <277>;
- clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <560>;
- };
-
- a53_1: cpu@101 {
- compatible = "arm,cortex-a53";
- reg = <0x101>;
- device_type = "cpu";
- power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <560>;
- };
-
- a53_2: cpu@102 {
- compatible = "arm,cortex-a53";
- reg = <0x102>;
- device_type = "cpu";
- power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <560>;
- };
-
- a53_3: cpu@103 {
- compatible = "arm,cortex-a53";
- reg = <0x103>;
- device_type = "cpu";
- power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <560>;
- };
-
- L2_CA57: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
- cache-unified;
- cache-level = <2>;
- };
-
- L2_CA53: cache-controller-1 {
- compatible = "cache";
- power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
- cache-unified;
- cache-level = <2>;
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- extalr_clk: extalr {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
- };
-
- pmu_a57 {
- compatible = "arm,cortex-a57-pmu";
- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a57_0>, <&a57_1>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a774a1-wdt",
- "renesas,rcar-gen3-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a774a1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a774a1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 29>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a774a1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 15>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a774a1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a774a1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 18>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a774a1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a774a1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 906>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 906>;
- };
-
- gpio7: gpio@e6055800 {
- compatible = "renesas,gpio-r8a774a1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055800 0 0x50>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 224 4>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a774a1";
- reg = <0 0xe6060000 0 0x50c>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a774a1-cmt0",
- "renesas,rcar-gen3-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 303>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 303>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a774a1-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 302>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 302>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a774a1-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 301>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 301>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a774a1-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a774a1-cpg-mssr";
- reg = <0 0xe6150000 0 0x0bb0>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a774a1-rst";
- reg = <0 0xe6160000 0 0x018c>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a774a1-sysc";
- reg = <0 0xe6180000 0 0x0400>;
- #power-domain-cells = <1>;
- };
-
- tsc: thermal@e6198000 {
- compatible = "renesas,r8a774a1-thermal";
- reg = <0 0xe6198000 0 0x100>,
- <0 0xe61a0000 0 0x100>,
- <0 0xe61a8000 0 0x100>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <1>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 125>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 125>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 123>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 123>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 122>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 122>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 121>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 121>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774a1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>,
- <&dmac2 0x91>, <&dmac2 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774a1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>,
- <&dmac2 0x93>, <&dmac2 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774a1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>,
- <&dmac2 0x95>, <&dmac2 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774a1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- dmas = <&dmac0 0x97>, <&dmac0 0x96>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774a1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- dmas = <&dmac0 0x99>, <&dmac0 0x98>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c5: i2c@e66e0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774a1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e0000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c6: i2c@e66e8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774a1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e8000 0 0x40>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- iic_pmic: i2c@e60b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a774a1",
- "renesas,rcar-gen3-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- dmas = <&dmac0 0x11>, <&dmac0 0x10>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a774a1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>,
- <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>,
- <&dmac2 0x31>, <&dmac2 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a774a1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6550000 0 0x60>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>,
- <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x33>, <&dmac1 0x32>,
- <&dmac2 0x33>, <&dmac2 0x32>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a774a1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6560000 0 0x60>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>,
- <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x35>, <&dmac1 0x34>,
- <&dmac2 0x35>, <&dmac2 0x34>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a774a1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66a0000 0 0x60>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x37>, <&dmac0 0x36>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- hscif4: serial@e66b0000 {
- compatible = "renesas,hscif-r8a774a1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66b0000 0 0x60>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x38>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 516>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a774a1",
- "renesas,rcar-gen3-usbhs";
- reg = <0 0xe6590000 0 0x200>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- renesas,buswait = <11>;
- phys = <&usb2_phy0 3>;
- phy-names = "usb";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 704>, <&cpg 703>;
- status = "disabled";
- };
-
- usb2_clksel: clock-controller@e6590630 {
- compatible = "renesas,r8a774a1-rcar-usb2-clock-sel",
- "renesas,rcar-gen3-usb2-clock-sel";
- reg = <0 0xe6590630 0 0x02>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
- <&usb_extal_clk>, <&usb3s0_clk>;
- clock-names = "ehci_ohci", "hs-usb-if",
- "usb_extal", "usb_xtal";
- #clock-cells = <0>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- reset-names = "ehci_ohci", "hs-usb-if";
- status = "disabled";
- };
-
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a774a1-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a774a1-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb3_phy0: usb-phy@e65ee000 {
- compatible = "renesas,r8a774a1-usb3-phy",
- "renesas,rcar-gen3-usb3-phy";
- reg = <0 0xe65ee000 0 0x90>;
- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
- <&usb_extal_clk>;
- clock-names = "usb3-if", "usb3s_clk", "usb_extal";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a774a1",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x10000>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
- };
-
- dmac1: dma-controller@e7300000 {
- compatible = "renesas,dmac-r8a774a1",
- "renesas,rcar-dmac";
- reg = <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
- };
-
- dmac2: dma-controller@e7310000 {
- compatible = "renesas,dmac-r8a774a1",
- "renesas,rcar-dmac";
- reg = <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 217>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 217>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
- };
-
- ipmmu_ds0: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a774a1";
- reg = <0 0xe6740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds1: iommu@e7740000 {
- compatible = "renesas,ipmmu-r8a774a1";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 1>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_hc: iommu@e6570000 {
- compatible = "renesas,ipmmu-r8a774a1";
- reg = <0 0xe6570000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 2>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@e67b0000 {
- compatible = "renesas,ipmmu-r8a774a1";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mp: iommu@ec670000 {
- compatible = "renesas,ipmmu-r8a774a1";
- reg = <0 0xec670000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 4>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv0: iommu@fd800000 {
- compatible = "renesas,ipmmu-r8a774a1";
- reg = <0 0xfd800000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 5>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv1: iommu@fd950000 {
- compatible = "renesas,ipmmu-r8a774a1";
- reg = <0 0xfd950000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 6>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: iommu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a774a1";
- reg = <0 0xfe6b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 8>;
- power-domains = <&sysc R8A774A1_PD_A3VC>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@febd0000 {
- compatible = "renesas,ipmmu-r8a774a1";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 9>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a774a1",
- "renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- iommus = <&ipmmu_ds0 16>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can0: can@e6c30000 {
- compatible = "renesas,can-r8a774a1",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c30000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6c38000 {
- compatible = "renesas,can-r8a774a1",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c38000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a774a1-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 914>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm5: pwm@e6e35000 {
- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
- reg = <0 0xe6e35000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm6: pwm@e6e36000 {
- compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
- reg = <0 0xe6e36000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a774a1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 0x40>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>,
- <&dmac2 0x51>, <&dmac2 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a774a1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 0x40>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>,
- <&dmac2 0x53>, <&dmac2 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scif2: serial@e6e88000 {
- compatible = "renesas,scif-r8a774a1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e88000 0 0x40>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>,
- <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x13>, <&dmac1 0x12>,
- <&dmac2 0x13>, <&dmac2 0x12>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 310>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a774a1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c50000 0 0x40>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x57>, <&dmac0 0x56>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a774a1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 0x40>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x59>, <&dmac0 0x58>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scif5: serial@e6f30000 {
- compatible = "renesas,scif-r8a774a1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6f30000 0 0x40>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>,
- <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
- <&dmac2 0x5b>, <&dmac2 0x5a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a774a1",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6e90000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
- dmas = <&dmac1 0x41>, <&dmac1 0x40>,
- <&dmac2 0x41>, <&dmac2 0x40>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a774a1",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
- dmas = <&dmac1 0x43>, <&dmac1 0x42>,
- <&dmac2 0x43>, <&dmac2 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 210>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a774a1",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
- dmas = <&dmac0 0x45>, <&dmac0 0x44>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 209>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a774a1",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x47>, <&dmac0 0x46>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a774a1";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- renesas,id = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin0csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin0>;
- };
- vin0csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin0>;
- };
- };
- };
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a774a1";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- renesas,id = <1>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin1csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin1>;
- };
- vin1csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin1>;
- };
- };
- };
- };
-
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a774a1";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- renesas,id = <2>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin2csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin2>;
- };
- vin2csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin2>;
- };
- };
- };
- };
-
- vin3: video@e6ef3000 {
- compatible = "renesas,vin-r8a774a1";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- renesas,id = <3>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin3csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin3>;
- };
- vin3csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin3>;
- };
- };
- };
- };
-
- vin4: video@e6ef4000 {
- compatible = "renesas,vin-r8a774a1";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 807>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 807>;
- renesas,id = <4>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin4csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin4>;
- };
- vin4csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin4>;
- };
- };
- };
- };
-
- vin5: video@e6ef5000 {
- compatible = "renesas,vin-r8a774a1";
- reg = <0 0xe6ef5000 0 0x1000>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 806>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 806>;
- renesas,id = <5>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin5csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin5>;
- };
- vin5csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin5>;
- };
- };
- };
- };
-
- vin6: video@e6ef6000 {
- compatible = "renesas,vin-r8a774a1";
- reg = <0 0xe6ef6000 0 0x1000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 805>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 805>;
- renesas,id = <6>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin6csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin6>;
- };
- vin6csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin6>;
- };
- };
- };
- };
-
- vin7: video@e6ef7000 {
- compatible = "renesas,vin-r8a774a1";
- reg = <0 0xe6ef7000 0 0x1000>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 804>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 804>;
- renesas,id = <7>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin7csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin7>;
- };
- vin7csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin7>;
- };
- };
- };
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- /*
- * #clock-cells is required for audio_clkout0/1/2/3
- *
- * clkout : #clock-cells = <0>; <&rcar_sound>;
- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6",
- "src.5", "src.4", "src.3", "src.2",
- "src.1", "src.0",
- "mix.1", "mix.0",
- "ctu.1", "ctu.0",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>,
- <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>,
- <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0";
- status = "disabled";
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma1 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma1 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>;
- dma-names = "rx", "tx";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>;
- dma-names = "rx", "tx";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>;
- dma-names = "rx", "tx";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>;
- dma-names = "rx", "tx";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>;
- dma-names = "rx", "tx";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>;
- dma-names = "rx", "tx";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>;
- dma-names = "rx", "tx";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>;
- dma-names = "rx", "tx";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>;
- dma-names = "rx", "tx";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssiu {
- ssiu00: ssiu-0 {
- dmas = <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx";
- };
- ssiu01: ssiu-1 {
- dmas = <&audma0 0x35>, <&audma1 0x36>;
- dma-names = "rx", "tx";
- };
- ssiu02: ssiu-2 {
- dmas = <&audma0 0x37>, <&audma1 0x38>;
- dma-names = "rx", "tx";
- };
- ssiu03: ssiu-3 {
- dmas = <&audma0 0x47>, <&audma1 0x48>;
- dma-names = "rx", "tx";
- };
- ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
- dma-names = "rx", "tx";
- };
- ssiu05: ssiu-5 {
- dmas = <&audma0 0x43>, <&audma1 0x44>;
- dma-names = "rx", "tx";
- };
- ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
- dma-names = "rx", "tx";
- };
- ssiu07: ssiu-7 {
- dmas = <&audma0 0x53>, <&audma1 0x54>;
- dma-names = "rx", "tx";
- };
- ssiu10: ssiu-8 {
- dmas = <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx";
- };
- ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
- dma-names = "rx", "tx";
- };
- ssiu12: ssiu-10 {
- dmas = <&audma0 0x57>, <&audma1 0x58>;
- dma-names = "rx", "tx";
- };
- ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
- dma-names = "rx", "tx";
- };
- ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
- dma-names = "rx", "tx";
- };
- ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
- dma-names = "rx", "tx";
- };
- ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
- dma-names = "rx", "tx";
- };
- ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
- dma-names = "rx", "tx";
- };
- ssiu20: ssiu-16 {
- dmas = <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx";
- };
- ssiu21: ssiu-17 {
- dmas = <&audma0 0x67>, <&audma1 0x68>;
- dma-names = "rx", "tx";
- };
- ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
- dma-names = "rx", "tx";
- };
- ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
- dma-names = "rx", "tx";
- };
- ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
- dma-names = "rx", "tx";
- };
- ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
- dma-names = "rx", "tx";
- };
- ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
- dma-names = "rx", "tx";
- };
- ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
- dma-names = "rx", "tx";
- };
- ssiu30: ssiu-24 {
- dmas = <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx";
- };
- ssiu31: ssiu-25 {
- dmas = <&audma0 0x21>, <&audma1 0x22>;
- dma-names = "rx", "tx";
- };
- ssiu32: ssiu-26 {
- dmas = <&audma0 0x23>, <&audma1 0x24>;
- dma-names = "rx", "tx";
- };
- ssiu33: ssiu-27 {
- dmas = <&audma0 0x25>, <&audma1 0x26>;
- dma-names = "rx", "tx";
- };
- ssiu34: ssiu-28 {
- dmas = <&audma0 0x27>, <&audma1 0x28>;
- dma-names = "rx", "tx";
- };
- ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
- dma-names = "rx", "tx";
- };
- ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
- dma-names = "rx", "tx";
- };
- ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
- dma-names = "rx", "tx";
- };
- ssiu40: ssiu-32 {
- dmas = <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx";
- };
- ssiu41: ssiu-33 {
- dmas = <&audma0 0x17>, <&audma1 0x18>;
- dma-names = "rx", "tx";
- };
- ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
- dma-names = "rx", "tx";
- };
- ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
- dma-names = "rx", "tx";
- };
- ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
- dma-names = "rx", "tx";
- };
- ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
- dma-names = "rx", "tx";
- };
- ssiu46: ssiu-38 {
- dmas = <&audma0 0x31>, <&audma1 0x32>;
- dma-names = "rx", "tx";
- };
- ssiu47: ssiu-39 {
- dmas = <&audma0 0x33>, <&audma1 0x34>;
- dma-names = "rx", "tx";
- };
- ssiu50: ssiu-40 {
- dmas = <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx";
- };
- ssiu60: ssiu-41 {
- dmas = <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx";
- };
- ssiu70: ssiu-42 {
- dmas = <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx";
- };
- ssiu80: ssiu-43 {
- dmas = <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx";
- };
- ssiu90: ssiu-44 {
- dmas = <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx";
- };
- ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
- dma-names = "rx", "tx";
- };
- ssiu92: ssiu-46 {
- dmas = <&audma0 0x81>, <&audma1 0x82>;
- dma-names = "rx", "tx";
- };
- ssiu93: ssiu-47 {
- dmas = <&audma0 0x83>, <&audma1 0x84>;
- dma-names = "rx", "tx";
- };
- ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
- dma-names = "rx", "tx";
- };
- ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
- dma-names = "rx", "tx";
- };
- ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
- dma-names = "rx", "tx";
- };
- ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
- dma-names = "rx", "tx";
- };
- };
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a774a1",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
- <&ipmmu_mp 2>, <&ipmmu_mp 3>,
- <&ipmmu_mp 4>, <&ipmmu_mp 5>,
- <&ipmmu_mp 6>, <&ipmmu_mp 7>,
- <&ipmmu_mp 8>, <&ipmmu_mp 9>,
- <&ipmmu_mp 10>, <&ipmmu_mp 11>,
- <&ipmmu_mp 12>, <&ipmmu_mp 13>,
- <&ipmmu_mp 14>, <&ipmmu_mp 15>;
- };
-
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a774a1",
- "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
- <&ipmmu_mp 18>, <&ipmmu_mp 19>,
- <&ipmmu_mp 20>, <&ipmmu_mp 21>,
- <&ipmmu_mp 22>, <&ipmmu_mp 23>,
- <&ipmmu_mp 24>, <&ipmmu_mp 25>,
- <&ipmmu_mp 26>, <&ipmmu_mp 27>,
- <&ipmmu_mp 28>, <&ipmmu_mp 29>,
- <&ipmmu_mp 30>, <&ipmmu_mp 31>;
- };
-
- xhci0: usb@ee000000 {
- compatible = "renesas,xhci-r8a774a1",
- "renesas,rcar-gen3-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- usb3_peri0: usb@ee020000 {
- compatible = "renesas,r8a774a1-usb3-peri",
- "renesas,rcar-gen3-usb3-peri";
- reg = <0 0xee020000 0 0x400>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- ohci0: usb@ee080000 {
- compatible = "generic-ohci";
- reg = <0 0xee080000 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ohci1: usb@ee0a0000 {
- compatible = "generic-ohci";
- reg = <0 0xee0a0000 0 0x100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>;
- phys = <&usb2_phy1 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- ehci0: usb@ee080100 {
- compatible = "generic-ehci";
- reg = <0 0xee080100 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 2>;
- phy-names = "usb";
- companion = <&ohci0>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ehci1: usb@ee0a0100 {
- compatible = "generic-ehci";
- reg = <0 0xee0a0100 0 0x100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>;
- phys = <&usb2_phy1 2>;
- phy-names = "usb";
- companion = <&ohci1>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- usb2_phy0: usb-phy@ee080200 {
- compatible = "renesas,usb2-phy-r8a774a1",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee080200 0 0x700>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- usb2_phy1: usb-phy@ee0a0200 {
- compatible = "renesas,usb2-phy-r8a774a1",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee0a0200 0 0x700>;
- clocks = <&cpg CPG_MOD 702>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a774a1",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee100000 0 0x2000>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
-
- sdhi1: mmc@ee120000 {
- compatible = "renesas,sdhi-r8a774a1",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee120000 0 0x2000>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 313>;
- status = "disabled";
- };
-
- sdhi2: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a774a1",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- status = "disabled";
- };
-
- sdhi3: mmc@ee160000 {
- compatible = "renesas,sdhi-r8a774a1",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee160000 0 0x2000>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a774a1-rpc-if",
- "renesas,rcar-gen3-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x4000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1010000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1010000 0 0x1000>,
- <0x0 0xf1020000 0 0x20000>,
- <0x0 0xf1040000 0 0x20000>,
- <0x0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- pciec0: pcie@fe000000 {
- compatible = "renesas,pcie-r8a774a1",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- iommu-map = <0 &ipmmu_hc 0 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- pciec1: pcie@ee800000 {
- compatible = "renesas,pcie-r8a774a1",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xee800000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- iommu-map = <0 &ipmmu_hc 1 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- pciec0_ep: pcie-ep@fe000000 {
- compatible = "renesas,r8a774a1-pcie-ep",
- "renesas,rcar-gen3-pcie-ep";
- reg = <0x0 0xfe000000 0 0x80000>,
- <0x0 0xfe100000 0 0x100000>,
- <0x0 0xfe200000 0 0x200000>,
- <0x0 0x30000000 0 0x8000000>,
- <0x0 0x38000000 0 0x8000000>;
- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>;
- clock-names = "pcie";
- resets = <&cpg 319>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pciec1_ep: pcie-ep@ee800000 {
- compatible = "renesas,r8a774a1-pcie-ep",
- "renesas,rcar-gen3-pcie-ep";
- reg = <0x0 0xee800000 0 0x80000>,
- <0x0 0xee900000 0 0x100000>,
- <0x0 0xeea00000 0 0x200000>,
- <0x0 0xc0000000 0 0x8000000>,
- <0x0 0xc8000000 0 0x8000000>;
- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- clock-names = "pcie";
- resets = <&cpg 318>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- fdp1@fe940000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe940000 0 0x2400>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 119>;
- power-domains = <&sysc R8A774A1_PD_A3VC>;
- resets = <&cpg 119>;
- renesas,fcp = <&fcpf0>;
- };
-
- fcpf0: fcp@fe950000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe950000 0 0x200>;
- clocks = <&cpg CPG_MOD 615>;
- power-domains = <&sysc R8A774A1_PD_A3VC>;
- resets = <&cpg 615>;
- };
-
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A774A1_PD_A3VC>;
- resets = <&cpg 607>;
- };
-
- fcpvd0: fcp@fea27000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea27000 0 0x200>;
- clocks = <&cpg CPG_MOD 603>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 603>;
- iommus = <&ipmmu_vi0 8>;
- };
-
- fcpvd1: fcp@fea2f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea2f000 0 0x200>;
- clocks = <&cpg CPG_MOD 602>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 602>;
- iommus = <&ipmmu_vi0 9>;
- };
-
- fcpvd2: fcp@fea37000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea37000 0 0x200>;
- clocks = <&cpg CPG_MOD 601>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 601>;
- iommus = <&ipmmu_vi0 10>;
- };
-
- fcpvi0: fcp@fe9af000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9af000 0 0x200>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A774A1_PD_A3VC>;
- resets = <&cpg 611>;
- iommus = <&ipmmu_vc0 19>;
- };
-
- vspb: vsp@fe960000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe960000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 626>;
- power-domains = <&sysc R8A774A1_PD_A3VC>;
- resets = <&cpg 626>;
-
- renesas,fcp = <&fcpvb0>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x5000>;
- interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
-
- renesas,fcp = <&fcpvd0>;
- };
-
- vspd1: vsp@fea28000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x5000>;
- interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 622>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 622>;
-
- renesas,fcp = <&fcpvd1>;
- };
-
- vspd2: vsp@fea30000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea30000 0 0x5000>;
- interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 621>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 621>;
-
- renesas,fcp = <&fcpvd2>;
- };
-
- vspi0: vsp@fe9a0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9a0000 0 0x8000>;
- interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 631>;
- power-domains = <&sysc R8A774A1_PD_A3VC>;
- resets = <&cpg 631>;
-
- renesas,fcp = <&fcpvi0>;
- };
-
- csi20: csi2@fea80000 {
- compatible = "renesas,r8a774a1-csi2";
- reg = <0 0xfea80000 0 0x10000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi20vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi20>;
- };
- csi20vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi20>;
- };
- csi20vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi20>;
- };
- csi20vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi20>;
- };
- csi20vin4: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&vin4csi20>;
- };
- csi20vin5: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&vin5csi20>;
- };
- csi20vin6: endpoint@6 {
- reg = <6>;
- remote-endpoint = <&vin6csi20>;
- };
- csi20vin7: endpoint@7 {
- reg = <7>;
- remote-endpoint = <&vin7csi20>;
- };
- };
- };
- };
-
- csi40: csi2@feaa0000 {
- compatible = "renesas,r8a774a1-csi2";
- reg = <0 0xfeaa0000 0 0x10000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi40vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi40>;
- };
- csi40vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi40>;
- };
- csi40vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi40>;
- };
- csi40vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi40>;
- };
- csi40vin4: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&vin4csi40>;
- };
- csi40vin5: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&vin5csi40>;
- };
- csi40vin6: endpoint@6 {
- reg = <6>;
- remote-endpoint = <&vin6csi40>;
- };
- csi40vin7: endpoint@7 {
- reg = <7>;
- remote-endpoint = <&vin7csi40>;
- };
- };
-
- };
- };
-
- hdmi0: hdmi@fead0000 {
- compatible = "renesas,r8a774a1-hdmi",
- "renesas,rcar-gen3-hdmi";
- reg = <0 0xfead0000 0 0x10000>;
- interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 729>,
- <&cpg CPG_CORE R8A774A1_CLK_HDMI>;
- clock-names = "iahb", "isfr";
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 729>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- dw_hdmi0_in: endpoint {
- remote-endpoint = <&du_out_hdmi0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- port@2 {
- /* HDMI sound */
- reg = <2>;
- };
- };
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a774a1";
- reg = <0 0xfeb00000 0 0x70000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>;
- clock-names = "du.0", "du.1", "du.2";
- resets = <&cpg 724>, <&cpg 722>;
- reset-names = "du.0", "du.2";
- status = "disabled";
-
- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- du_out_hdmi0: endpoint {
- remote-endpoint = <&dw_hdmi0_in>;
- };
- };
- port@2 {
- reg = <2>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
- };
- };
-
- lvds0: lvds@feb90000 {
- compatible = "renesas,r8a774a1-lvds";
- reg = <0 0xfeb90000 0 0x14>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
- resets = <&cpg 727>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- sensor1_thermal: sensor1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 0>;
- sustainable-power = <3874>;
-
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor2_thermal: sensor2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 1>;
- sustainable-power = <3874>;
-
- trips {
- sensor2_crit: sensor2-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor3_thermal: sensor3-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 2>;
- sustainable-power = <3874>;
-
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&a57_0 0 2>;
- contribution = <1024>;
- };
- map1 {
- trip = <&target>;
- cooling-device = <&a53_0 0 2>;
- contribution = <1024>;
- };
- };
- trips {
- target: trip-point1 {
- temperature = <100000>;
- hysteresis = <1000>;
- type = "passive";
- };
-
- sensor3_crit: sensor3-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- /* External USB clocks - can be overridden by the board */
- usb3s0_clk: usb3s0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2020, Compass Electronics Group, LLC
- */
-
-/dts-v1/;
-
-#include "r8a774b1.dtsi"
-#include "beacon-renesom-som.dtsi"
-#include "beacon-renesom-baseboard.dtsi"
-
-/ {
- model = "Beacon Embedded Works RZ/G2N Development Kit";
- compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1";
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &iic_pmic;
- serial0 = &scif2;
- serial1 = &hscif0;
- serial2 = &hscif1;
- serial3 = &scif0;
- serial4 = &hscif2;
- serial5 = &scif5;
- serial6 = &scif4;
- ethernet0 = &avb;
- mmc0 = &sdhi3;
- mmc1 = &sdhi0;
- mmc2 = &sdhi2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 721>,
- <&versaclock5 1>,
- <&x302_clk>,
- <&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.3",
- "dclkin.0", "dclkin.1", "dclkin.3";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to
- * sub board
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-#include "r8a774b1-hihope-rzg2n.dts"
-#include "hihope-rzg2-ex.dtsi"
-
-/ {
- model = "HopeRun HiHope RZ/G2N with sub board";
- compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
- "renesas,r8a774b1";
-};
-
-/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
-&sata {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a774b1.dtsi"
-#include "hihope-rev4.dtsi"
-
-/ {
- model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
- compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-
- memory@480000000 {
- device_type = "memory";
- reg = <0x4 0x80000000 0x0 0x80000000>;
- };
-};
-
-&du {
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 721>,
- <&versaclock5 1>,
- <&x302_clk>,
- <&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.3",
- "dclkin.0", "dclkin.1", "dclkin.3";
-};
-
-&sdhi3 {
- mmc-hs400-1_8v;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the r8a774b1 SoC
- *
- * Copyright (C) 2019 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
-#include <dt-bindings/power/r8a774b1-sysc.h>
-
-#define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4
-
-/ {
- compatible = "renesas,r8a774b1";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cluster0_opp: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <830000>;
- clock-latency-ns = <300000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <830000>;
- clock-latency-ns = <300000>;
- };
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <830000>;
- clock-latency-ns = <300000>;
- opp-suspend;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- a57_0: cpu@0 {
- compatible = "arm,cortex-a57";
- reg = <0x0>;
- device_type = "cpu";
- power-domains = <&sysc R8A774B1_PD_CA57_CPU0>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- #cooling-cells = <2>;
- dynamic-power-coefficient = <854>;
- clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- a57_1: cpu@1 {
- compatible = "arm,cortex-a57";
- reg = <0x1>;
- device_type = "cpu";
- power-domains = <&sysc R8A774B1_PD_CA57_CPU1>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- L2_CA57: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A774B1_PD_CA57_SCU>;
- cache-unified;
- cache-level = <2>;
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- extalr_clk: extalr {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- pmu_a57 {
- compatible = "arm,cortex-a57-pmu";
- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a57_0>, <&a57_1>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a774b1-wdt",
- "renesas,rcar-gen3-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a774b1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a774b1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 29>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a774b1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 15>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a774b1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a774b1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 18>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a774b1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a774b1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 906>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 906>;
- };
-
- gpio7: gpio@e6055800 {
- compatible = "renesas,gpio-r8a774b1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055800 0 0x50>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 224 4>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a774b1";
- reg = <0 0xe6060000 0 0x50c>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a774b1-cmt0",
- "renesas,rcar-gen3-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 303>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 303>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a774b1-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 302>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 302>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a774b1-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 301>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 301>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a774b1-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a774b1-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a774b1-rst";
- reg = <0 0xe6160000 0 0x0200>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a774b1-sysc";
- reg = <0 0xe6180000 0 0x0400>;
- #power-domain-cells = <1>;
- };
-
- tsc: thermal@e6198000 {
- compatible = "renesas,r8a774b1-thermal";
- reg = <0 0xe6198000 0 0x100>,
- <0 0xe61a0000 0 0x100>,
- <0 0xe61a8000 0 0x100>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <1>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 125>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 125>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 123>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 123>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 122>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 122>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 121>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 121>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774b1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>,
- <&dmac2 0x91>, <&dmac2 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774b1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>,
- <&dmac2 0x93>, <&dmac2 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774b1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>,
- <&dmac2 0x95>, <&dmac2 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774b1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- dmas = <&dmac0 0x97>, <&dmac0 0x96>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774b1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- dmas = <&dmac0 0x99>, <&dmac0 0x98>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c5: i2c@e66e0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774b1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e0000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c6: i2c@e66e8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774b1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e8000 0 0x40>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- iic_pmic: i2c@e60b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a774b1",
- "renesas,rcar-gen3-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- dmas = <&dmac0 0x11>, <&dmac0 0x10>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a774b1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>,
- <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>,
- <&dmac2 0x31>, <&dmac2 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a774b1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6550000 0 0x60>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>,
- <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x33>, <&dmac1 0x32>,
- <&dmac2 0x33>, <&dmac2 0x32>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a774b1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6560000 0 0x60>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>,
- <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x35>, <&dmac1 0x34>,
- <&dmac2 0x35>, <&dmac2 0x34>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a774b1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66a0000 0 0x60>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x37>, <&dmac0 0x36>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- hscif4: serial@e66b0000 {
- compatible = "renesas,hscif-r8a774b1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66b0000 0 0x60>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x38>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 516>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a774b1",
- "renesas,rcar-gen3-usbhs";
- reg = <0 0xe6590000 0 0x200>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- renesas,buswait = <11>;
- phys = <&usb2_phy0 3>;
- phy-names = "usb";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 704>, <&cpg 703>;
- status = "disabled";
- };
-
- usb2_clksel: clock-controller@e6590630 {
- compatible = "renesas,r8a774b1-rcar-usb2-clock-sel",
- "renesas,rcar-gen3-usb2-clock-sel";
- reg = <0 0xe6590630 0 0x02>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
- <&usb_extal_clk>, <&usb3s0_clk>;
- clock-names = "ehci_ohci", "hs-usb-if",
- "usb_extal", "usb_xtal";
- #clock-cells = <0>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- reset-names = "ehci_ohci", "hs-usb-if";
- status = "disabled";
- };
-
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a774b1-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a774b1-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb3_phy0: usb-phy@e65ee000 {
- compatible = "renesas,r8a774b1-usb3-phy",
- "renesas,rcar-gen3-usb3-phy";
- reg = <0 0xe65ee000 0 0x90>;
- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
- <&usb_extal_clk>;
- clock-names = "usb3-if", "usb3s_clk", "usb_extal";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a774b1",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x10000>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
- };
-
- dmac1: dma-controller@e7300000 {
- compatible = "renesas,dmac-r8a774b1",
- "renesas,rcar-dmac";
- reg = <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
- };
-
- dmac2: dma-controller@e7310000 {
- compatible = "renesas,dmac-r8a774b1",
- "renesas,rcar-dmac";
- reg = <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 217>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 217>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
- };
-
- ipmmu_ds0: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a774b1";
- reg = <0 0xe6740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds1: iommu@e7740000 {
- compatible = "renesas,ipmmu-r8a774b1";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 1>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_hc: iommu@e6570000 {
- compatible = "renesas,ipmmu-r8a774b1";
- reg = <0 0xe6570000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 2>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@e67b0000 {
- compatible = "renesas,ipmmu-r8a774b1";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mp: iommu@ec670000 {
- compatible = "renesas,ipmmu-r8a774b1";
- reg = <0 0xec670000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 4>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv0: iommu@fd800000 {
- compatible = "renesas,ipmmu-r8a774b1";
- reg = <0 0xfd800000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 6>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: iommu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a774b1";
- reg = <0 0xfe6b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 12>;
- power-domains = <&sysc R8A774B1_PD_A3VC>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@febd0000 {
- compatible = "renesas,ipmmu-r8a774b1";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 14>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vp0: iommu@fe990000 {
- compatible = "renesas,ipmmu-r8a774b1";
- reg = <0 0xfe990000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 16>;
- power-domains = <&sysc R8A774B1_PD_A3VP>;
- #iommu-cells = <1>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a774b1",
- "renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- iommus = <&ipmmu_ds0 16>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can0: can@e6c30000 {
- compatible = "renesas,can-r8a774b1",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c30000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A774B1_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6c38000 {
- compatible = "renesas,can-r8a774b1",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c38000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A774B1_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a774b1-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A774B1_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 914>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm5: pwm@e6e35000 {
- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
- reg = <0 0xe6e35000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm6: pwm@e6e36000 {
- compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
- reg = <0 0xe6e36000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a774b1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 0x40>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>,
- <&dmac2 0x51>, <&dmac2 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a774b1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 0x40>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>,
- <&dmac2 0x53>, <&dmac2 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scif2: serial@e6e88000 {
- compatible = "renesas,scif-r8a774b1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e88000 0 0x40>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>,
- <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x13>, <&dmac1 0x12>,
- <&dmac2 0x13>, <&dmac2 0x12>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 310>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a774b1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c50000 0 0x40>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x57>, <&dmac0 0x56>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a774b1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 0x40>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x59>, <&dmac0 0x58>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scif5: serial@e6f30000 {
- compatible = "renesas,scif-r8a774b1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6f30000 0 0x40>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>,
- <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
- <&dmac2 0x5b>, <&dmac2 0x5a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a774b1",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6e90000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
- dmas = <&dmac1 0x41>, <&dmac1 0x40>,
- <&dmac2 0x41>, <&dmac2 0x40>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a774b1",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
- dmas = <&dmac1 0x43>, <&dmac1 0x42>,
- <&dmac2 0x43>, <&dmac2 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 210>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a774b1",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
- dmas = <&dmac0 0x45>, <&dmac0 0x44>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 209>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a774b1",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x47>, <&dmac0 0x46>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a774b1";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- renesas,id = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin0csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin0>;
- };
- vin0csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin0>;
- };
- };
- };
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a774b1";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- renesas,id = <1>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin1csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin1>;
- };
- vin1csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin1>;
- };
- };
- };
- };
-
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a774b1";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- renesas,id = <2>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin2csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin2>;
- };
- vin2csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin2>;
- };
- };
- };
- };
-
- vin3: video@e6ef3000 {
- compatible = "renesas,vin-r8a774b1";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- renesas,id = <3>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin3csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin3>;
- };
- vin3csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin3>;
- };
- };
- };
- };
-
- vin4: video@e6ef4000 {
- compatible = "renesas,vin-r8a774b1";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 807>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 807>;
- renesas,id = <4>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin4csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin4>;
- };
- vin4csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin4>;
- };
- };
- };
- };
-
- vin5: video@e6ef5000 {
- compatible = "renesas,vin-r8a774b1";
- reg = <0 0xe6ef5000 0 0x1000>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 806>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 806>;
- renesas,id = <5>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin5csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin5>;
- };
- vin5csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin5>;
- };
- };
- };
- };
-
- vin6: video@e6ef6000 {
- compatible = "renesas,vin-r8a774b1";
- reg = <0 0xe6ef6000 0 0x1000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 805>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 805>;
- renesas,id = <6>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin6csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin6>;
- };
- vin6csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin6>;
- };
- };
- };
- };
-
- vin7: video@e6ef7000 {
- compatible = "renesas,vin-r8a774b1";
- reg = <0 0xe6ef7000 0 0x1000>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 804>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 804>;
- renesas,id = <7>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin7csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin7>;
- };
- vin7csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin7>;
- };
- };
- };
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- /*
- * #clock-cells is required for audio_clkout0/1/2/3
- *
- * clkout : #clock-cells = <0>; <&rcar_sound>;
- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A774B1_CLK_S0D4>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6",
- "src.5", "src.4", "src.3", "src.2",
- "src.1", "src.0",
- "mix.1", "mix.0",
- "ctu.1", "ctu.0",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>,
- <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>,
- <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0";
- status = "disabled";
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma1 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma1 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>;
- dma-names = "rx", "tx";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>;
- dma-names = "rx", "tx";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>;
- dma-names = "rx", "tx";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>;
- dma-names = "rx", "tx";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>;
- dma-names = "rx", "tx";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>;
- dma-names = "rx", "tx";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>;
- dma-names = "rx", "tx";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>;
- dma-names = "rx", "tx";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>;
- dma-names = "rx", "tx";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssiu {
- ssiu00: ssiu-0 {
- dmas = <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx";
- };
- ssiu01: ssiu-1 {
- dmas = <&audma0 0x35>, <&audma1 0x36>;
- dma-names = "rx", "tx";
- };
- ssiu02: ssiu-2 {
- dmas = <&audma0 0x37>, <&audma1 0x38>;
- dma-names = "rx", "tx";
- };
- ssiu03: ssiu-3 {
- dmas = <&audma0 0x47>, <&audma1 0x48>;
- dma-names = "rx", "tx";
- };
- ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
- dma-names = "rx", "tx";
- };
- ssiu05: ssiu-5 {
- dmas = <&audma0 0x43>, <&audma1 0x44>;
- dma-names = "rx", "tx";
- };
- ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
- dma-names = "rx", "tx";
- };
- ssiu07: ssiu-7 {
- dmas = <&audma0 0x53>, <&audma1 0x54>;
- dma-names = "rx", "tx";
- };
- ssiu10: ssiu-8 {
- dmas = <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx";
- };
- ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
- dma-names = "rx", "tx";
- };
- ssiu12: ssiu-10 {
- dmas = <&audma0 0x57>, <&audma1 0x58>;
- dma-names = "rx", "tx";
- };
- ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
- dma-names = "rx", "tx";
- };
- ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
- dma-names = "rx", "tx";
- };
- ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
- dma-names = "rx", "tx";
- };
- ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
- dma-names = "rx", "tx";
- };
- ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
- dma-names = "rx", "tx";
- };
- ssiu20: ssiu-16 {
- dmas = <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx";
- };
- ssiu21: ssiu-17 {
- dmas = <&audma0 0x67>, <&audma1 0x68>;
- dma-names = "rx", "tx";
- };
- ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
- dma-names = "rx", "tx";
- };
- ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
- dma-names = "rx", "tx";
- };
- ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
- dma-names = "rx", "tx";
- };
- ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
- dma-names = "rx", "tx";
- };
- ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
- dma-names = "rx", "tx";
- };
- ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
- dma-names = "rx", "tx";
- };
- ssiu30: ssiu-24 {
- dmas = <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx";
- };
- ssiu31: ssiu-25 {
- dmas = <&audma0 0x21>, <&audma1 0x22>;
- dma-names = "rx", "tx";
- };
- ssiu32: ssiu-26 {
- dmas = <&audma0 0x23>, <&audma1 0x24>;
- dma-names = "rx", "tx";
- };
- ssiu33: ssiu-27 {
- dmas = <&audma0 0x25>, <&audma1 0x26>;
- dma-names = "rx", "tx";
- };
- ssiu34: ssiu-28 {
- dmas = <&audma0 0x27>, <&audma1 0x28>;
- dma-names = "rx", "tx";
- };
- ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
- dma-names = "rx", "tx";
- };
- ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
- dma-names = "rx", "tx";
- };
- ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
- dma-names = "rx", "tx";
- };
- ssiu40: ssiu-32 {
- dmas = <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx";
- };
- ssiu41: ssiu-33 {
- dmas = <&audma0 0x17>, <&audma1 0x18>;
- dma-names = "rx", "tx";
- };
- ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
- dma-names = "rx", "tx";
- };
- ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
- dma-names = "rx", "tx";
- };
- ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
- dma-names = "rx", "tx";
- };
- ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
- dma-names = "rx", "tx";
- };
- ssiu46: ssiu-38 {
- dmas = <&audma0 0x31>, <&audma1 0x32>;
- dma-names = "rx", "tx";
- };
- ssiu47: ssiu-39 {
- dmas = <&audma0 0x33>, <&audma1 0x34>;
- dma-names = "rx", "tx";
- };
- ssiu50: ssiu-40 {
- dmas = <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx";
- };
- ssiu60: ssiu-41 {
- dmas = <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx";
- };
- ssiu70: ssiu-42 {
- dmas = <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx";
- };
- ssiu80: ssiu-43 {
- dmas = <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx";
- };
- ssiu90: ssiu-44 {
- dmas = <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx";
- };
- ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
- dma-names = "rx", "tx";
- };
- ssiu92: ssiu-46 {
- dmas = <&audma0 0x81>, <&audma1 0x82>;
- dma-names = "rx", "tx";
- };
- ssiu93: ssiu-47 {
- dmas = <&audma0 0x83>, <&audma1 0x84>;
- dma-names = "rx", "tx";
- };
- ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
- dma-names = "rx", "tx";
- };
- ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
- dma-names = "rx", "tx";
- };
- ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
- dma-names = "rx", "tx";
- };
- ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
- dma-names = "rx", "tx";
- };
- };
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a774b1",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <16>;
- };
-
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a774b1",
- "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <16>;
- };
-
- xhci0: usb@ee000000 {
- compatible = "renesas,xhci-r8a774b1",
- "renesas,rcar-gen3-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- usb3_peri0: usb@ee020000 {
- compatible = "renesas,r8a774b1-usb3-peri",
- "renesas,rcar-gen3-usb3-peri";
- reg = <0 0xee020000 0 0x400>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- ohci0: usb@ee080000 {
- compatible = "generic-ohci";
- reg = <0 0xee080000 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ohci1: usb@ee0a0000 {
- compatible = "generic-ohci";
- reg = <0 0xee0a0000 0 0x100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>;
- phys = <&usb2_phy1 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- ehci0: usb@ee080100 {
- compatible = "generic-ehci";
- reg = <0 0xee080100 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 2>;
- phy-names = "usb";
- companion = <&ohci0>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ehci1: usb@ee0a0100 {
- compatible = "generic-ehci";
- reg = <0 0xee0a0100 0 0x100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>;
- phys = <&usb2_phy1 2>;
- phy-names = "usb";
- companion = <&ohci1>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- usb2_phy0: usb-phy@ee080200 {
- compatible = "renesas,usb2-phy-r8a774b1",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee080200 0 0x700>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- usb2_phy1: usb-phy@ee0a0200 {
- compatible = "renesas,usb2-phy-r8a774b1",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee0a0200 0 0x700>;
- clocks = <&cpg CPG_MOD 702>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a774b1",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee100000 0 0x2000>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
-
- sdhi1: mmc@ee120000 {
- compatible = "renesas,sdhi-r8a774b1",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee120000 0 0x2000>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 313>;
- status = "disabled";
- };
-
- sdhi2: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a774b1",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- status = "disabled";
- };
-
- sdhi3: mmc@ee160000 {
- compatible = "renesas,sdhi-r8a774b1",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee160000 0 0x2000>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a774b1-rpc-if",
- "renesas,rcar-gen3-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x4000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sata: sata@ee300000 {
- compatible = "renesas,sata-r8a774b1",
- "renesas,rcar-gen3-sata";
- reg = <0 0xee300000 0 0x200000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 815>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 815>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1010000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1010000 0 0x1000>,
- <0x0 0xf1020000 0 0x20000>,
- <0x0 0xf1040000 0 0x20000>,
- <0x0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- pciec0: pcie@fe000000 {
- compatible = "renesas,pcie-r8a774b1",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- iommu-map = <0 &ipmmu_hc 0 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- pciec1: pcie@ee800000 {
- compatible = "renesas,pcie-r8a774b1",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xee800000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- iommu-map = <0 &ipmmu_hc 1 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- pciec0_ep: pcie-ep@fe000000 {
- compatible = "renesas,r8a774b1-pcie-ep",
- "renesas,rcar-gen3-pcie-ep";
- reg = <0x0 0xfe000000 0 0x80000>,
- <0x0 0xfe100000 0 0x100000>,
- <0x0 0xfe200000 0 0x200000>,
- <0x0 0x30000000 0 0x8000000>,
- <0x0 0x38000000 0 0x8000000>;
- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>;
- clock-names = "pcie";
- resets = <&cpg 319>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pciec1_ep: pcie-ep@ee800000 {
- compatible = "renesas,r8a774b1-pcie-ep",
- "renesas,rcar-gen3-pcie-ep";
- reg = <0x0 0xee800000 0 0x80000>,
- <0x0 0xee900000 0 0x100000>,
- <0x0 0xeea00000 0 0x200000>,
- <0x0 0xc0000000 0 0x8000000>,
- <0x0 0xc8000000 0 0x8000000>;
- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- clock-names = "pcie";
- resets = <&cpg 318>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- fdp1@fe940000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe940000 0 0x2400>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 119>;
- power-domains = <&sysc R8A774B1_PD_A3VP>;
- resets = <&cpg 119>;
- renesas,fcp = <&fcpf0>;
- };
-
- fcpf0: fcp@fe950000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe950000 0 0x200>;
- clocks = <&cpg CPG_MOD 615>;
- power-domains = <&sysc R8A774B1_PD_A3VP>;
- resets = <&cpg 615>;
- };
-
- vspb: vsp@fe960000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe960000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 626>;
- power-domains = <&sysc R8A774B1_PD_A3VP>;
- resets = <&cpg 626>;
-
- renesas,fcp = <&fcpvb0>;
- };
-
- vspi0: vsp@fe9a0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9a0000 0 0x8000>;
- interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 631>;
- power-domains = <&sysc R8A774B1_PD_A3VP>;
- resets = <&cpg 631>;
-
- renesas,fcp = <&fcpvi0>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x5000>;
- interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
-
- renesas,fcp = <&fcpvd0>;
- };
-
- vspd1: vsp@fea28000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x5000>;
- interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 622>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 622>;
-
- renesas,fcp = <&fcpvd1>;
- };
-
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A774B1_PD_A3VP>;
- resets = <&cpg 607>;
- };
-
- fcpvd0: fcp@fea27000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea27000 0 0x200>;
- clocks = <&cpg CPG_MOD 603>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 603>;
- };
-
- fcpvd1: fcp@fea2f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea2f000 0 0x200>;
- clocks = <&cpg CPG_MOD 602>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 602>;
- };
-
- fcpvi0: fcp@fe9af000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9af000 0 0x200>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A774B1_PD_A3VP>;
- resets = <&cpg 611>;
- };
-
- csi20: csi2@fea80000 {
- compatible = "renesas,r8a774b1-csi2";
- reg = <0 0xfea80000 0 0x10000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi20vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi20>;
- };
- csi20vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi20>;
- };
- csi20vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi20>;
- };
- csi20vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi20>;
- };
- csi20vin4: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&vin4csi20>;
- };
- csi20vin5: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&vin5csi20>;
- };
- csi20vin6: endpoint@6 {
- reg = <6>;
- remote-endpoint = <&vin6csi20>;
- };
- csi20vin7: endpoint@7 {
- reg = <7>;
- remote-endpoint = <&vin7csi20>;
- };
- };
- };
- };
-
- csi40: csi2@feaa0000 {
- compatible = "renesas,r8a774b1-csi2";
- reg = <0 0xfeaa0000 0 0x10000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi40vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi40>;
- };
- csi40vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi40>;
- };
- csi40vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi40>;
- };
- csi40vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi40>;
- };
- csi40vin4: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&vin4csi40>;
- };
- csi40vin5: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&vin5csi40>;
- };
- csi40vin6: endpoint@6 {
- reg = <6>;
- remote-endpoint = <&vin6csi40>;
- };
- csi40vin7: endpoint@7 {
- reg = <7>;
- remote-endpoint = <&vin7csi40>;
- };
- };
- };
- };
-
- hdmi0: hdmi@fead0000 {
- compatible = "renesas,r8a774b1-hdmi",
- "renesas,rcar-gen3-hdmi";
- reg = <0 0xfead0000 0 0x10000>;
- interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 729>,
- <&cpg CPG_CORE R8A774B1_CLK_HDMI>;
- clock-names = "iahb", "isfr";
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 729>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dw_hdmi0_in: endpoint {
- remote-endpoint = <&du_out_hdmi0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- port@2 {
- /* HDMI sound */
- reg = <2>;
- };
- };
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a774b1";
- reg = <0 0xfeb00000 0 0x80000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 721>;
- clock-names = "du.0", "du.1", "du.3";
- resets = <&cpg 724>, <&cpg 722>;
- reset-names = "du.0", "du.3";
- status = "disabled";
-
- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- du_out_hdmi0: endpoint {
- remote-endpoint = <&dw_hdmi0_in>;
- };
- };
- port@2 {
- reg = <2>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
- };
- };
-
- lvds0: lvds@feb90000 {
- compatible = "renesas,r8a774b1-lvds";
- reg = <0 0xfeb90000 0 0x14>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
- resets = <&cpg 727>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- sensor1_thermal: sensor1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 0>;
- sustainable-power = <2439>;
-
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor2_thermal: sensor2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 1>;
- sustainable-power = <2439>;
-
- trips {
- sensor2_crit: sensor2-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor3_thermal: sensor3-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 2>;
- sustainable-power = <2439>;
-
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&a57_0 0 2>;
- contribution = <1024>;
- };
- };
- trips {
- target: trip-point1 {
- temperature = <100000>;
- hysteresis = <1000>;
- type = "passive";
- };
-
- sensor3_crit: sensor3-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- /* External USB clocks - can be overridden by the board */
- usb3s0_clk: usb3s0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
- *
- * Copyright (C) 2019 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a774c0.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/display/tda998x.h>
-
-/ {
- model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
- compatible = "si-linux,cat874", "renesas,r8a774c0";
-
- aliases {
- serial0 = &scif2;
- serial1 = &hscif2;
- mmc0 = &sdhi0;
- mmc1 = &sdhi3;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_out: endpoint {
- remote-endpoint = <&tda19988_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led0 {
- gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
- label = "LED0";
- };
-
- led1 {
- gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
- label = "LED1";
- };
-
- led2 {
- gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
- label = "LED2";
- };
-
- led3 {
- gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;
- label = "LED3";
- };
- };
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-
- reg_12p0v: regulator-12p0v {
- compatible = "regulator-fixed";
- regulator-name = "D12.0V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sound: sound {
- compatible = "simple-audio-card";
-
- simple-audio-card,name = "CAT874 HDMI sound";
- simple-audio-card,format = "i2s";
- simple-audio-card,bitclock-master = <&sndcpu>;
- simple-audio-card,frame-master = <&sndcpu>;
-
- sndcodec: simple-audio-card,codec {
- sound-dai = <&tda19988>;
- };
-
- sndcpu: simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- wlan_en_reg: fixedregulator {
- compatible = "regulator-fixed";
- regulator-name = "wlan-en-regulator";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- startup-delay-us = <70000>;
-
- gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- x13_clk: x13 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <74250000>;
- };
-
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- data-role = "dual";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- hs_ep: endpoint {
- remote-endpoint = <&usb3_hs_ep>;
- };
- };
- port@1 {
- reg = <1>;
- ss_ep: endpoint {
- remote-endpoint = <&hd3ss3220_in_ep>;
- };
- };
- };
- };
-};
-
-&audio_clk_a {
- clock-frequency = <22579200>;
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&x13_clk>;
- clock-names = "du.0", "du.1", "dclkin.0";
-
- ports {
- port@0 {
- du_out_rgb: endpoint {
- remote-endpoint = <&tda19988_in>;
- };
- };
- };
-};
-
-&ehci0 {
- dr_mode = "host";
- status = "okay";
-};
-
-&extal_clk {
- clock-frequency = <48000000>;
-};
-
-&hscif2 {
- pinctrl-0 = <&hscif2_pins>;
- pinctrl-names = "default";
-
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "ti,wl1837-st";
- enable-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&i2c0 {
- status = "okay";
- clock-frequency = <100000>;
-
- hd3ss3220@47 {
- compatible = "ti,hd3ss3220";
- reg = <0x47>;
- interrupt-parent = <&gpio6>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- hd3ss3220_in_ep: endpoint {
- remote-endpoint = <&ss_ep>;
- };
- };
- port@1 {
- reg = <1>;
- hd3ss3220_out_ep: endpoint {
- remote-endpoint = <&usb3_role_switch>;
- };
- };
- };
- };
-
- tda19988: tda19988@70 {
- compatible = "nxp,tda998x";
- reg = <0x70>;
- interrupt-parent = <&gpio1>;
- interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
-
- video-ports = <0x234501>;
-
- #sound-dai-cells = <0>;
- audio-ports = <TDA998x_I2S 0x03>;
- clocks = <&rcar_sound 1>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- tda19988_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
-
- port@1 {
- reg = <1>;
- tda19988_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
- };
- };
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- rtc@32 {
- compatible = "epson,rx8571";
- reg = <0x32>;
- };
-};
-
-&lvds0 {
- status = "okay";
-
- clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>;
- clock-names = "fck", "dclkin.0", "extal";
-};
-
-&ohci0 {
- dr_mode = "host";
- status = "okay";
-};
-
-&pcie_bus_clk {
- clock-frequency = <100000000>;
-};
-
-&pciec0 {
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
-};
-
-&pfc {
- du_pins: du {
- groups = "du_rgb888", "du_clk_out_0", "du_sync", "du_disp",
- "du_clk_in_0";
- function = "du";
- };
-
- hscif2_pins: hscif2 {
- groups = "hscif2_data_a", "hscif2_ctrl_a";
- function = "hscif2";
- };
-
- i2c1_pins: i2c1 {
- groups = "i2c1_b";
- function = "i2c1";
- };
-
- scif2_pins: scif2 {
- groups = "scif2_data_a";
- function = "scif2";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi3_pins: sd3 {
- groups = "sdhi3_data4", "sdhi3_ctrl";
- function = "sdhi3";
- power-source = <1800>;
- };
-
- sound_clk_pins: sound_clk {
- groups = "audio_clkout1_a";
- function = "audio_clk";
- };
-
- sound_pins: sound {
- groups = "ssi01239_ctrl", "ssi0_data";
- function = "ssi";
- };
-
- usb30_pins: usb30 {
- groups = "usb30", "usb30_id";
- function = "usb30";
- };
-};
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
- pinctrl-names = "default";
-
- /* Single DAI */
- #sound-dai-cells = <0>;
-
- /* audio_clkout0/1/2/3 */
- #clock-cells = <1>;
- clock-frequency = <11289600>;
-
- status = "okay";
-
- rcar_sound,dai {
- dai0 {
- playback = <&ssi0>, <&src0>, <&dvc0>;
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdhi3 {
- status = "okay";
- pinctrl-0 = <&sdhi3_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&wlan_en_reg>;
- bus-width = <4>;
- non-removable;
- cap-power-off-card;
- keep-power-in-suspend;
-
- #address-cells = <1>;
- #size-cells = <0>;
- wlcore: wlcore@2 {
- compatible = "ti,wl1837";
- reg = <2>;
- interrupt-parent = <&gpio1>;
- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
- };
-};
-
-&usb2_phy0 {
- renesas,no-otg-pins;
- status = "okay";
-};
-
-&usb3_peri0 {
- companion = <&xhci0>;
- status = "okay";
- usb-role-switch;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- usb3_hs_ep: endpoint {
- remote-endpoint = <&hs_ep>;
- };
- };
- port@1 {
- reg = <1>;
- usb3_role_switch: endpoint {
- remote-endpoint = <&hd3ss3220_out_ep>;
- };
- };
- };
-};
-
-&xhci0 {
- pinctrl-0 = <&usb30_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874)
- *
- * Copyright (C) 2019 Renesas Electronics Corp.
- */
-
-#include "r8a774c0-cat874.dts"
-#include "cat875.dtsi"
-
-/ {
- model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)";
- compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the RZ/G2E (R8A774C0) SoC
- *
- * Copyright (C) 2018-2019 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a774c0-sysc.h>
-
-/ {
- compatible = "renesas,r8a774c0";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cluster1_opp: opp-table-1 {
- compatible = "operating-points-v2";
- opp-shared;
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- clock-latency-ns = <300000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- clock-latency-ns = <300000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- clock-latency-ns = <300000>;
- opp-suspend;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- a53_0: cpu@0 {
- compatible = "arm,cortex-a53";
- reg = <0>;
- device_type = "cpu";
- #cooling-cells = <2>;
- power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- dynamic-power-coefficient = <277>;
- clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- };
-
- a53_1: cpu@1 {
- compatible = "arm,cortex-a53";
- reg = <1>;
- device_type = "cpu";
- power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- };
-
- L2_CA53: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
- cache-unified;
- cache-level = <2>;
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a53_0>, <&a53_1>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc: soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a774c0-wdt",
- "renesas,rcar-gen3-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a774c0",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 18>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a774c0",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 23>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a774c0",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a774c0",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a774c0",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 11>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a774c0",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 20>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a774c0",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 18>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 906>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 906>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a774c0";
- reg = <0 0xe6060000 0 0x508>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a774c0-cmt0",
- "renesas,rcar-gen3-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 303>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 303>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a774c0-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 302>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 302>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a774c0-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 301>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 301>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a774c0-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a774c0-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>;
- clock-names = "extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a774c0-rst";
- reg = <0 0xe6160000 0 0x0200>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a774c0-sysc";
- reg = <0 0xe6180000 0 0x0400>;
- #power-domain-cells = <1>;
- };
-
- thermal: thermal@e6190000 {
- compatible = "renesas,thermal-r8a774c0";
- reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <0>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 125>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 125>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 123>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 123>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 122>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 122>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 121>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 121>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774c0",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>,
- <&dmac2 0x91>, <&dmac2 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774c0",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>,
- <&dmac2 0x93>, <&dmac2 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774c0",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>,
- <&dmac2 0x95>, <&dmac2 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774c0",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- dmas = <&dmac0 0x97>, <&dmac0 0x96>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774c0",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- dmas = <&dmac0 0x99>, <&dmac0 0x98>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c5: i2c@e66e0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774c0",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e0000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c6: i2c@e66e8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774c0",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e8000 0 0x40>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c7: i2c@e6690000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774c0",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6690000 0 0x40>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1003>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 1003>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- iic_pmic: i2c@e60b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a774c0",
- "renesas,rcar-gen3-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- dmas = <&dmac0 0x11>, <&dmac0 0x10>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a774c0",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>,
- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>,
- <&dmac2 0x31>, <&dmac2 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a774c0",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6550000 0 0x60>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>,
- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x33>, <&dmac1 0x32>,
- <&dmac2 0x33>, <&dmac2 0x32>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a774c0",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6560000 0 0x60>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>,
- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x35>, <&dmac1 0x34>,
- <&dmac2 0x35>, <&dmac2 0x34>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a774c0",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66a0000 0 0x60>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x37>, <&dmac0 0x36>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- hscif4: serial@e66b0000 {
- compatible = "renesas,hscif-r8a774c0",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66b0000 0 0x60>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x38>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 516>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a774c0",
- "renesas,rcar-gen3-usbhs";
- reg = <0 0xe6590000 0 0x200>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- renesas,buswait = <11>;
- phys = <&usb2_phy0 3>;
- phy-names = "usb";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 704>, <&cpg 703>;
- status = "disabled";
- };
-
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a774c0-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a774c0-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a774c0",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x10000>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
- };
-
- dmac1: dma-controller@e7300000 {
- compatible = "renesas,dmac-r8a774c0",
- "renesas,rcar-dmac";
- reg = <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
- };
-
- dmac2: dma-controller@e7310000 {
- compatible = "renesas,dmac-r8a774c0",
- "renesas,rcar-dmac";
- reg = <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 217>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 217>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
- };
-
- ipmmu_ds0: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a774c0";
- reg = <0 0xe6740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds1: iommu@e7740000 {
- compatible = "renesas,ipmmu-r8a774c0";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 1>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_hc: iommu@e6570000 {
- compatible = "renesas,ipmmu-r8a774c0";
- reg = <0 0xe6570000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 2>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@e67b0000 {
- compatible = "renesas,ipmmu-r8a774c0";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mp: iommu@ec670000 {
- compatible = "renesas,ipmmu-r8a774c0";
- reg = <0 0xec670000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 4>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv0: iommu@fd800000 {
- compatible = "renesas,ipmmu-r8a774c0";
- reg = <0 0xfd800000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 6>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: iommu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a774c0";
- reg = <0 0xfe6b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 12>;
- power-domains = <&sysc R8A774C0_PD_A3VC>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@febd0000 {
- compatible = "renesas,ipmmu-r8a774c0";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 14>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vp0: iommu@fe990000 {
- compatible = "renesas,ipmmu-r8a774c0";
- reg = <0 0xfe990000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 16>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a774c0",
- "renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- iommus = <&ipmmu_ds0 16>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can0: can@e6c30000 {
- compatible = "renesas,can-r8a774c0",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c30000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6c38000 {
- compatible = "renesas,can-r8a774c0",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c38000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a774c0-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 914>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm5: pwm@e6e35000 {
- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
- reg = <0 0xe6e35000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm6: pwm@e6e36000 {
- compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
- reg = <0 0xe6e36000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a774c0",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>,
- <&dmac2 0x51>, <&dmac2 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a774c0",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>,
- <&dmac2 0x53>, <&dmac2 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scif2: serial@e6e88000 {
- compatible = "renesas,scif-r8a774c0",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e88000 0 64>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>,
- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x13>, <&dmac1 0x12>,
- <&dmac2 0x13>, <&dmac2 0x12>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 310>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a774c0",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x57>, <&dmac0 0x56>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a774c0",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x59>, <&dmac0 0x58>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scif5: serial@e6f30000 {
- compatible = "renesas,scif-r8a774c0",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6f30000 0 64>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>,
- <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a774c0",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6e90000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
- dmas = <&dmac1 0x41>, <&dmac1 0x40>,
- <&dmac2 0x41>, <&dmac2 0x40>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a774c0",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
- dmas = <&dmac0 0x43>, <&dmac0 0x42>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 210>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a774c0",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
- dmas = <&dmac0 0x45>, <&dmac0 0x44>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 209>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a774c0",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x47>, <&dmac0 0x46>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin4: video@e6ef4000 {
- compatible = "renesas,vin-r8a774c0";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 807>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 807>;
- renesas,id = <4>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin4csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin4>;
- };
- };
- };
- };
-
- vin5: video@e6ef5000 {
- compatible = "renesas,vin-r8a774c0";
- reg = <0 0xe6ef5000 0 0x1000>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 806>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 806>;
- renesas,id = <5>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin5csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin5>;
- };
- };
- };
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- /*
- * #clock-cells is required for audio_clkout0/1/2/3
- *
- * clkout : #clock-cells = <0>; <&rcar_sound>;
- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a774c0",
- "renesas,rcar_sound-gen3";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6",
- "src.5", "src.4", "src.3", "src.2",
- "src.1", "src.0",
- "mix.1", "mix.0",
- "ctu.1", "ctu.0",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>,
- <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>,
- <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0";
- status = "disabled";
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma0 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma0 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma0 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma0 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma0 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma0 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma0 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma0 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma0 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma0 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma0 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma0 0xba>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma0 0x02>,
- <&audma0 0x15>, <&audma0 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma0 0x04>,
- <&audma0 0x49>, <&audma0 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma0 0x06>,
- <&audma0 0x63>, <&audma0 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma0 0x08>,
- <&audma0 0x6f>, <&audma0 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma0 0x0a>,
- <&audma0 0x71>, <&audma0 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma0 0x0c>,
- <&audma0 0x73>, <&audma0 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma0 0x0e>,
- <&audma0 0x75>, <&audma0 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma0 0x10>,
- <&audma0 0x79>, <&audma0 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma0 0x12>,
- <&audma0 0x7b>, <&audma0 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma0 0x14>,
- <&audma0 0x7d>, <&audma0 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- };
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a774c0",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
- <&ipmmu_mp 2>, <&ipmmu_mp 3>,
- <&ipmmu_mp 4>, <&ipmmu_mp 5>,
- <&ipmmu_mp 6>, <&ipmmu_mp 7>,
- <&ipmmu_mp 8>, <&ipmmu_mp 9>,
- <&ipmmu_mp 10>, <&ipmmu_mp 11>,
- <&ipmmu_mp 12>, <&ipmmu_mp 13>,
- <&ipmmu_mp 14>, <&ipmmu_mp 15>;
- };
-
- xhci0: usb@ee000000 {
- compatible = "renesas,xhci-r8a774c0",
- "renesas,rcar-gen3-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- usb3_peri0: usb@ee020000 {
- compatible = "renesas,r8a774c0-usb3-peri",
- "renesas,rcar-gen3-usb3-peri";
- reg = <0 0xee020000 0 0x400>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- ohci0: usb@ee080000 {
- compatible = "generic-ohci";
- reg = <0 0xee080000 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ehci0: usb@ee080100 {
- compatible = "generic-ehci";
- reg = <0 0xee080100 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 2>;
- phy-names = "usb";
- companion = <&ohci0>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- usb2_phy0: usb-phy@ee080200 {
- compatible = "renesas,usb2-phy-r8a774c0",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee080200 0 0x700>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a774c0",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee100000 0 0x2000>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
-
- sdhi1: mmc@ee120000 {
- compatible = "renesas,sdhi-r8a774c0",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee120000 0 0x2000>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 313>;
- status = "disabled";
- };
-
- sdhi3: mmc@ee160000 {
- compatible = "renesas,sdhi-r8a774c0",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee160000 0 0x2000>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a774c0-rpc-if",
- "renesas,rcar-gen3-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x4000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1010000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1010000 0 0x1000>,
- <0x0 0xf1020000 0 0x20000>,
- <0x0 0xf1040000 0 0x20000>,
- <0x0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- pciec0: pcie@fe000000 {
- compatible = "renesas,pcie-r8a774c0",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- iommu-map = <0 &ipmmu_hc 0 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- pciec0_ep: pcie-ep@fe000000 {
- compatible = "renesas,r8a774c0-pcie-ep",
- "renesas,rcar-gen3-pcie-ep";
- reg = <0x0 0xfe000000 0 0x80000>,
- <0x0 0xfe100000 0 0x100000>,
- <0x0 0xfe200000 0 0x200000>,
- <0x0 0x30000000 0 0x8000000>,
- <0x0 0x38000000 0 0x8000000>;
- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>;
- clock-names = "pcie";
- resets = <&cpg 319>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- vspb0: vsp@fe960000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe960000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 626>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 626>;
- renesas,fcp = <&fcpvb0>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x7000>;
- interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
- renesas,fcp = <&fcpvd0>;
- };
-
- vspd1: vsp@fea28000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x7000>;
- interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 622>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 622>;
- renesas,fcp = <&fcpvd1>;
- };
-
- vspi0: vsp@fe9a0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9a0000 0 0x8000>;
- interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 631>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 631>;
- renesas,fcp = <&fcpvi0>;
- };
-
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 607>;
- iommus = <&ipmmu_vp0 5>;
- };
-
- fcpvd0: fcp@fea27000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea27000 0 0x200>;
- clocks = <&cpg CPG_MOD 603>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 603>;
- iommus = <&ipmmu_vi0 8>;
- };
-
- fcpvd1: fcp@fea2f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea2f000 0 0x200>;
- clocks = <&cpg CPG_MOD 602>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 602>;
- iommus = <&ipmmu_vi0 9>;
- };
-
- fcpvi0: fcp@fe9af000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9af000 0 0x200>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 611>;
- iommus = <&ipmmu_vp0 8>;
- };
-
- csi40: csi2@feaa0000 {
- compatible = "renesas,r8a774c0-csi2";
- reg = <0 0xfeaa0000 0 0x10000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi40vin4: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin4csi40>;
- };
- csi40vin5: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin5csi40>;
- };
- };
- };
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a774c0";
- reg = <0 0xfeb00000 0 0x40000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
- clock-names = "du.0", "du.1";
- resets = <&cpg 724>;
- reset-names = "du.0";
- renesas,vsps = <&vspd0 0>, <&vspd1 0>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
-
- port@2 {
- reg = <2>;
- du_out_lvds1: endpoint {
- remote-endpoint = <&lvds1_in>;
- };
- };
- };
- };
-
- lvds0: lvds-encoder@feb90000 {
- compatible = "renesas,r8a774c0-lvds";
- reg = <0 0xfeb90000 0 0x20>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 727>;
- status = "disabled";
-
- renesas,companion = <&lvds1>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
-
- port@1 {
- reg = <1>;
- };
- };
- };
-
- lvds1: lvds-encoder@feb90100 {
- compatible = "renesas,r8a774c0-lvds";
- reg = <0 0xfeb90100 0 0x20>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 726>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds1_in: endpoint {
- remote-endpoint = <&du_out_lvds1>;
- };
- };
-
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- cpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <0>;
- thermal-sensors = <&thermal>;
- sustainable-power = <717>;
-
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&a53_0 0 2>;
- contribution = <1024>;
- };
- };
-
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <120000>;
- hysteresis = <2000>;
- type = "critical";
- };
-
- target: trip-point1 {
- temperature = <100000>;
- hysteresis = <2000>;
- type = "passive";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- /* External USB clocks - can be overridden by the board */
- usb3s0_clk: usb3s0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2020, Compass Electronics Group, LLC
- */
-
-/dts-v1/;
-
-#include "r8a774e1.dtsi"
-#include "beacon-renesom-som.dtsi"
-#include "beacon-renesom-baseboard.dtsi"
-
-/ {
- model = "Beacon Embedded Works RZ/G2H Development Kit";
- compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &iic_pmic;
- serial0 = &scif2;
- serial1 = &hscif0;
- serial2 = &hscif1;
- serial3 = &scif0;
- serial4 = &hscif2;
- serial5 = &scif5;
- serial6 = &scif4;
- ethernet0 = &avb;
- mmc0 = &sdhi3;
- mmc1 = &sdhi0;
- mmc2 = &sdhi2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@500000000 {
- device_type = "memory";
- reg = <0x5 0x00000000 0x0 0x80000000>;
- };
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 721>,
- <&versaclock5 1>,
- <&x302_clk>,
- <&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.3",
- "dclkin.0", "dclkin.1", "dclkin.3";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the HiHope RZ/G2H sub board
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-#include "r8a774e1-hihope-rzg2h.dts"
-#include "hihope-rzg2-ex.dtsi"
-
-/ {
- model = "HopeRun HiHope RZ/G2H with sub board";
- compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
- "renesas,r8a774e1";
-};
-
-/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
-&sata {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the HiHope RZ/G2H main board
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a774e1.dtsi"
-#include "hihope-rev4.dtsi"
-
-/ {
- model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
- compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-
- memory@500000000 {
- device_type = "memory";
- reg = <0x5 0x00000000 0x0 0x80000000>;
- };
-};
-
-&du {
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 721>,
- <&versaclock5 1>,
- <&x302_clk>,
- <&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.3",
- "dclkin.0", "dclkin.1", "dclkin.3";
-};
-
-&sdhi3 {
- mmc-hs400-1_8v;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the r8a774e1 SoC
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
-#include <dt-bindings/power/r8a774e1-sysc.h>
-
-#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4
-
-/ {
- compatible = "renesas,r8a774e1";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cluster0_opp: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- opp-suspend;
- };
- };
-
- cluster1_opp: opp-table-1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&a57_0>;
- };
- core1 {
- cpu = <&a57_1>;
- };
- core2 {
- cpu = <&a57_2>;
- };
- core3 {
- cpu = <&a57_3>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&a53_0>;
- };
- core1 {
- cpu = <&a53_1>;
- };
- core2 {
- cpu = <&a53_2>;
- };
- core3 {
- cpu = <&a53_3>;
- };
- };
- };
-
- a57_0: cpu@0 {
- compatible = "arm,cortex-a57";
- reg = <0x0>;
- device_type = "cpu";
- power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- dynamic-power-coefficient = <854>;
- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <1024>;
- #cooling-cells = <2>;
- };
-
- a57_1: cpu@1 {
- compatible = "arm,cortex-a57";
- reg = <0x1>;
- device_type = "cpu";
- power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <1024>;
- #cooling-cells = <2>;
- };
-
- a57_2: cpu@2 {
- compatible = "arm,cortex-a57";
- reg = <0x2>;
- device_type = "cpu";
- power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <1024>;
- #cooling-cells = <2>;
- };
-
- a57_3: cpu@3 {
- compatible = "arm,cortex-a57";
- reg = <0x3>;
- device_type = "cpu";
- power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <1024>;
- #cooling-cells = <2>;
- };
-
- a53_0: cpu@100 {
- compatible = "arm,cortex-a53";
- reg = <0x100>;
- device_type = "cpu";
- power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_1>;
- #cooling-cells = <2>;
- dynamic-power-coefficient = <277>;
- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <535>;
- };
-
- a53_1: cpu@101 {
- compatible = "arm,cortex-a53";
- reg = <0x101>;
- device_type = "cpu";
- power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_1>;
- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <535>;
- };
-
- a53_2: cpu@102 {
- compatible = "arm,cortex-a53";
- reg = <0x102>;
- device_type = "cpu";
- power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_1>;
- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <535>;
- };
-
- a53_3: cpu@103 {
- compatible = "arm,cortex-a53";
- reg = <0x103>;
- device_type = "cpu";
- power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_1>;
- clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <535>;
- };
-
- L2_CA57: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
- cache-unified;
- cache-level = <2>;
- };
-
- L2_CA53: cache-controller-1 {
- compatible = "cache";
- power-domains = <&sysc R8A774E1_PD_CA53_SCU>;
- cache-unified;
- cache-level = <2>;
- };
-
- idle-states {
- entry-method = "psci";
-
- CPU_SLEEP_0: cpu-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- local-timer-stop;
- entry-latency-us = <400>;
- exit-latency-us = <500>;
- min-residency-us = <4000>;
- };
-
- CPU_SLEEP_1: cpu-sleep-1 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- local-timer-stop;
- entry-latency-us = <700>;
- exit-latency-us = <700>;
- min-residency-us = <5000>;
- };
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- extalr_clk: extalr {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
- };
-
- pmu_a57 {
- compatible = "arm,cortex-a57-pmu";
- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a774e1-wdt",
- "renesas,rcar-gen3-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a774e1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a774e1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 29>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a774e1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 15>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a774e1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a774e1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 18>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a774e1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a774e1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 906>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 906>;
- };
-
- gpio7: gpio@e6055800 {
- compatible = "renesas,gpio-r8a774e1",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055800 0 0x50>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 224 4>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a774e1";
- reg = <0 0xe6060000 0 0x50c>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a774e1-cmt0",
- "renesas,rcar-gen3-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 303>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 303>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a774e1-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 302>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 302>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a774e1-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 301>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 301>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a774e1-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a774e1-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a774e1-rst";
- reg = <0 0xe6160000 0 0x0200>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a774e1-sysc";
- reg = <0 0xe6180000 0 0x0400>;
- #power-domain-cells = <1>;
- };
-
- tsc: thermal@e6198000 {
- compatible = "renesas,r8a774e1-thermal";
- reg = <0 0xe6198000 0 0x100>,
- <0 0xe61a0000 0 0x100>,
- <0 0xe61a8000 0 0x100>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <1>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 125>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 125>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 123>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 123>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 122>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 122>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 121>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 121>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774e1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>,
- <&dmac2 0x91>, <&dmac2 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774e1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>,
- <&dmac2 0x93>, <&dmac2 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774e1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>,
- <&dmac2 0x95>, <&dmac2 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774e1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- dmas = <&dmac0 0x97>, <&dmac0 0x96>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774e1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- dmas = <&dmac0 0x99>, <&dmac0 0x98>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c5: i2c@e66e0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774e1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e0000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c6: i2c@e66e8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a774e1",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e8000 0 0x40>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- iic_pmic: i2c@e60b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a774e1",
- "renesas,rcar-gen3-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- dmas = <&dmac0 0x11>, <&dmac0 0x10>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a774e1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>,
- <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>,
- <&dmac2 0x31>, <&dmac2 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a774e1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6550000 0 0x60>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>,
- <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x33>, <&dmac1 0x32>,
- <&dmac2 0x33>, <&dmac2 0x32>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a774e1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6560000 0 0x60>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>,
- <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x35>, <&dmac1 0x34>,
- <&dmac2 0x35>, <&dmac2 0x34>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a774e1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66a0000 0 0x60>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x37>, <&dmac0 0x36>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- hscif4: serial@e66b0000 {
- compatible = "renesas,hscif-r8a774e1",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66b0000 0 0x60>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x38>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 516>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a774e1",
- "renesas,rcar-gen3-usbhs";
- reg = <0 0xe6590000 0 0x200>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- renesas,buswait = <11>;
- phys = <&usb2_phy0 3>;
- phy-names = "usb";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 704>, <&cpg 703>;
- status = "disabled";
- };
-
- usb2_clksel: clock-controller@e6590630 {
- compatible = "renesas,r8a774e1-rcar-usb2-clock-sel",
- "renesas,rcar-gen3-usb2-clock-sel";
- reg = <0 0xe6590630 0 0x02>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
- <&usb_extal_clk>, <&usb3s0_clk>;
- clock-names = "ehci_ohci", "hs-usb-if",
- "usb_extal", "usb_xtal";
- #clock-cells = <0>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- reset-names = "ehci_ohci", "hs-usb-if";
- status = "disabled";
- };
-
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a774e1-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a774e1-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb3_phy0: usb-phy@e65ee000 {
- compatible = "renesas,r8a774e1-usb3-phy",
- "renesas,rcar-gen3-usb3-phy";
- reg = <0 0xe65ee000 0 0x90>;
- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
- <&usb_extal_clk>;
- clock-names = "usb3-if", "usb3s_clk", "usb_extal";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a774e1",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x10000>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
- };
-
- dmac1: dma-controller@e7300000 {
- compatible = "renesas,dmac-r8a774e1",
- "renesas,rcar-dmac";
- reg = <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
- };
-
- dmac2: dma-controller@e7310000 {
- compatible = "renesas,dmac-r8a774e1",
- "renesas,rcar-dmac";
- reg = <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 217>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 217>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
- };
-
- ipmmu_ds0: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xe6740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds1: iommu@e7740000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 1>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_hc: iommu@e6570000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xe6570000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 2>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@e67b0000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mp0: iommu@ec670000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xec670000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 4>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv0: iommu@fd800000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xfd800000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 6>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv1: iommu@fd950000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xfd950000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 7>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv2: iommu@fd960000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xfd960000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 8>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv3: iommu@fd970000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xfd970000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 9>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: iommu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xfe6b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 12>;
- power-domains = <&sysc R8A774E1_PD_A3VC>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc1: iommu@fe6f0000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xfe6f0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 13>;
- power-domains = <&sysc R8A774E1_PD_A3VC>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@febd0000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 14>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi1: iommu@febe0000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xfebe0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 15>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vp0: iommu@fe990000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xfe990000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 16>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vp1: iommu@fe980000 {
- compatible = "renesas,ipmmu-r8a774e1";
- reg = <0 0xfe980000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 17>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- #iommu-cells = <1>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a774e1",
- "renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- iommus = <&ipmmu_ds0 16>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can0: can@e6c30000 {
- compatible = "renesas,can-r8a774e1",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c30000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6c38000 {
- compatible = "renesas,can-r8a774e1",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c38000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a774e1-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 914>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm5: pwm@e6e35000 {
- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
- reg = <0 0xe6e35000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm6: pwm@e6e36000 {
- compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
- reg = <0 0xe6e36000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a774e1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 0x40>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>,
- <&dmac2 0x51>, <&dmac2 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a774e1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 0x40>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>,
- <&dmac2 0x53>, <&dmac2 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scif2: serial@e6e88000 {
- compatible = "renesas,scif-r8a774e1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e88000 0 0x40>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>,
- <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x13>, <&dmac1 0x12>,
- <&dmac2 0x13>, <&dmac2 0x12>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 310>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a774e1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c50000 0 0x40>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x57>, <&dmac0 0x56>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a774e1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 0x40>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x59>, <&dmac0 0x58>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scif5: serial@e6f30000 {
- compatible = "renesas,scif-r8a774e1",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6f30000 0 0x40>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>,
- <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
- <&dmac2 0x5b>, <&dmac2 0x5a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a774e1",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6e90000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
- dmas = <&dmac1 0x41>, <&dmac1 0x40>,
- <&dmac2 0x41>, <&dmac2 0x40>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a774e1",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
- dmas = <&dmac1 0x43>, <&dmac1 0x42>,
- <&dmac2 0x43>, <&dmac2 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 210>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a774e1",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
- dmas = <&dmac0 0x45>, <&dmac0 0x44>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 209>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a774e1",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x47>, <&dmac0 0x46>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a774e1";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- renesas,id = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin0csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin0>;
- };
- vin0csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin0>;
- };
- };
- };
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a774e1";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- renesas,id = <1>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin1csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin1>;
- };
- vin1csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin1>;
- };
- };
- };
- };
-
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a774e1";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- renesas,id = <2>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin2csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin2>;
- };
- vin2csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin2>;
- };
- };
- };
- };
-
- vin3: video@e6ef3000 {
- compatible = "renesas,vin-r8a774e1";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- renesas,id = <3>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin3csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin3>;
- };
- vin3csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin3>;
- };
- };
- };
- };
-
- vin4: video@e6ef4000 {
- compatible = "renesas,vin-r8a774e1";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 807>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 807>;
- renesas,id = <4>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin4csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin4>;
- };
- };
- };
- };
-
- vin5: video@e6ef5000 {
- compatible = "renesas,vin-r8a774e1";
- reg = <0 0xe6ef5000 0 0x1000>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 806>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 806>;
- renesas,id = <5>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin5csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin5>;
- };
- };
- };
- };
-
- vin6: video@e6ef6000 {
- compatible = "renesas,vin-r8a774e1";
- reg = <0 0xe6ef6000 0 0x1000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 805>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 805>;
- renesas,id = <6>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin6csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin6>;
- };
- };
- };
- };
-
- vin7: video@e6ef7000 {
- compatible = "renesas,vin-r8a774e1";
- reg = <0 0xe6ef7000 0 0x1000>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 804>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 804>;
- renesas,id = <7>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin7csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin7>;
- };
- };
- };
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- /*
- * #clock-cells is required for audio_clkout0/1/2/3
- *
- * clkout : #clock-cells = <0>; <&rcar_sound>;
- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A774E1_CLK_S0D4>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6",
- "src.5", "src.4", "src.3", "src.2",
- "src.1", "src.0",
- "mix.1", "mix.0",
- "ctu.1", "ctu.0",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>,
- <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>,
- <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0";
- status = "disabled";
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma1 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma1 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssiu {
- ssiu00: ssiu-0 {
- dmas = <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx";
- };
- ssiu01: ssiu-1 {
- dmas = <&audma0 0x35>, <&audma1 0x36>;
- dma-names = "rx", "tx";
- };
- ssiu02: ssiu-2 {
- dmas = <&audma0 0x37>, <&audma1 0x38>;
- dma-names = "rx", "tx";
- };
- ssiu03: ssiu-3 {
- dmas = <&audma0 0x47>, <&audma1 0x48>;
- dma-names = "rx", "tx";
- };
- ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
- dma-names = "rx", "tx";
- };
- ssiu05: ssiu-5 {
- dmas = <&audma0 0x43>, <&audma1 0x44>;
- dma-names = "rx", "tx";
- };
- ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
- dma-names = "rx", "tx";
- };
- ssiu07: ssiu-7 {
- dmas = <&audma0 0x53>, <&audma1 0x54>;
- dma-names = "rx", "tx";
- };
- ssiu10: ssiu-8 {
- dmas = <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx";
- };
- ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
- dma-names = "rx", "tx";
- };
- ssiu12: ssiu-10 {
- dmas = <&audma0 0x57>, <&audma1 0x58>;
- dma-names = "rx", "tx";
- };
- ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
- dma-names = "rx", "tx";
- };
- ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
- dma-names = "rx", "tx";
- };
- ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
- dma-names = "rx", "tx";
- };
- ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
- dma-names = "rx", "tx";
- };
- ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
- dma-names = "rx", "tx";
- };
- ssiu20: ssiu-16 {
- dmas = <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx";
- };
- ssiu21: ssiu-17 {
- dmas = <&audma0 0x67>, <&audma1 0x68>;
- dma-names = "rx", "tx";
- };
- ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
- dma-names = "rx", "tx";
- };
- ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
- dma-names = "rx", "tx";
- };
- ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
- dma-names = "rx", "tx";
- };
- ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
- dma-names = "rx", "tx";
- };
- ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
- dma-names = "rx", "tx";
- };
- ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
- dma-names = "rx", "tx";
- };
- ssiu30: ssiu-24 {
- dmas = <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx";
- };
- ssiu31: ssiu-25 {
- dmas = <&audma0 0x21>, <&audma1 0x22>;
- dma-names = "rx", "tx";
- };
- ssiu32: ssiu-26 {
- dmas = <&audma0 0x23>, <&audma1 0x24>;
- dma-names = "rx", "tx";
- };
- ssiu33: ssiu-27 {
- dmas = <&audma0 0x25>, <&audma1 0x26>;
- dma-names = "rx", "tx";
- };
- ssiu34: ssiu-28 {
- dmas = <&audma0 0x27>, <&audma1 0x28>;
- dma-names = "rx", "tx";
- };
- ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
- dma-names = "rx", "tx";
- };
- ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
- dma-names = "rx", "tx";
- };
- ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
- dma-names = "rx", "tx";
- };
- ssiu40: ssiu-32 {
- dmas = <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx";
- };
- ssiu41: ssiu-33 {
- dmas = <&audma0 0x17>, <&audma1 0x18>;
- dma-names = "rx", "tx";
- };
- ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
- dma-names = "rx", "tx";
- };
- ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
- dma-names = "rx", "tx";
- };
- ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
- dma-names = "rx", "tx";
- };
- ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
- dma-names = "rx", "tx";
- };
- ssiu46: ssiu-38 {
- dmas = <&audma0 0x31>, <&audma1 0x32>;
- dma-names = "rx", "tx";
- };
- ssiu47: ssiu-39 {
- dmas = <&audma0 0x33>, <&audma1 0x34>;
- dma-names = "rx", "tx";
- };
- ssiu50: ssiu-40 {
- dmas = <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx";
- };
- ssiu60: ssiu-41 {
- dmas = <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx";
- };
- ssiu70: ssiu-42 {
- dmas = <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx";
- };
- ssiu80: ssiu-43 {
- dmas = <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx";
- };
- ssiu90: ssiu-44 {
- dmas = <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx";
- };
- ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
- dma-names = "rx", "tx";
- };
- ssiu92: ssiu-46 {
- dmas = <&audma0 0x81>, <&audma1 0x82>;
- dma-names = "rx", "tx";
- };
- ssiu93: ssiu-47 {
- dmas = <&audma0 0x83>, <&audma1 0x84>;
- dma-names = "rx", "tx";
- };
- ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
- dma-names = "rx", "tx";
- };
- ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
- dma-names = "rx", "tx";
- };
- ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
- dma-names = "rx", "tx";
- };
- ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>;
- dma-names = "rx", "tx";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>;
- dma-names = "rx", "tx";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>;
- dma-names = "rx", "tx";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>;
- dma-names = "rx", "tx";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>;
- dma-names = "rx", "tx";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>;
- dma-names = "rx", "tx";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>;
- dma-names = "rx", "tx";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>;
- dma-names = "rx", "tx";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>;
- dma-names = "rx", "tx";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>;
- dma-names = "rx", "tx";
- };
- };
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a774e1",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
- <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
- <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
- <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
- <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
- <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
- <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
- <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
- };
-
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a774e1",
- "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
- <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
- <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
- <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
- <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
- <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
- <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
- <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
- };
-
- xhci0: usb@ee000000 {
- compatible = "renesas,xhci-r8a774e1",
- "renesas,rcar-gen3-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- usb3_peri0: usb@ee020000 {
- compatible = "renesas,r8a774e1-usb3-peri",
- "renesas,rcar-gen3-usb3-peri";
- reg = <0 0xee020000 0 0x400>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- ohci0: usb@ee080000 {
- compatible = "generic-ohci";
- reg = <0 0xee080000 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ohci1: usb@ee0a0000 {
- compatible = "generic-ohci";
- reg = <0 0xee0a0000 0 0x100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>;
- phys = <&usb2_phy1 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- ehci0: usb@ee080100 {
- compatible = "generic-ehci";
- reg = <0 0xee080100 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 2>;
- phy-names = "usb";
- companion = <&ohci0>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ehci1: usb@ee0a0100 {
- compatible = "generic-ehci";
- reg = <0 0xee0a0100 0 0x100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>;
- phys = <&usb2_phy1 2>;
- phy-names = "usb";
- companion = <&ohci1>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- usb2_phy0: usb-phy@ee080200 {
- compatible = "renesas,usb2-phy-r8a774e1",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee080200 0 0x700>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- usb2_phy1: usb-phy@ee0a0200 {
- compatible = "renesas,usb2-phy-r8a774e1",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee0a0200 0 0x700>;
- clocks = <&cpg CPG_MOD 702>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a774e1",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee100000 0 0x2000>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- iommus = <&ipmmu_ds1 32>;
- status = "disabled";
- };
-
- sdhi1: mmc@ee120000 {
- compatible = "renesas,sdhi-r8a774e1",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee120000 0 0x2000>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 313>;
- iommus = <&ipmmu_ds1 33>;
- status = "disabled";
- };
-
- sdhi2: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a774e1",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- iommus = <&ipmmu_ds1 34>;
- status = "disabled";
- };
-
- sdhi3: mmc@ee160000 {
- compatible = "renesas,sdhi-r8a774e1",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee160000 0 0x2000>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- iommus = <&ipmmu_ds1 35>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a774e1-rpc-if",
- "renesas,rcar-gen3-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x4000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sata: sata@ee300000 {
- compatible = "renesas,sata-r8a774e1",
- "renesas,rcar-gen3-sata";
- reg = <0 0xee300000 0 0x200000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 815>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 815>;
- iommus = <&ipmmu_hc 2>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1010000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1010000 0 0x1000>,
- <0x0 0xf1020000 0 0x20000>,
- <0x0 0xf1040000 0 0x20000>,
- <0x0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- pciec0: pcie@fe000000 {
- compatible = "renesas,pcie-r8a774e1",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- iommu-map = <0 &ipmmu_hc 0 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- pciec1: pcie@ee800000 {
- compatible = "renesas,pcie-r8a774e1",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xee800000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- iommu-map = <0 &ipmmu_hc 1 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- pciec0_ep: pcie-ep@fe000000 {
- compatible = "renesas,r8a774e1-pcie-ep",
- "renesas,rcar-gen3-pcie-ep";
- reg = <0x0 0xfe000000 0 0x80000>,
- <0x0 0xfe100000 0 0x100000>,
- <0x0 0xfe200000 0 0x200000>,
- <0x0 0x30000000 0 0x8000000>,
- <0x0 0x38000000 0 0x8000000>;
- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>;
- clock-names = "pcie";
- resets = <&cpg 319>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pciec1_ep: pcie-ep@ee800000 {
- compatible = "renesas,r8a774e1-pcie-ep",
- "renesas,rcar-gen3-pcie-ep";
- reg = <0x0 0xee800000 0 0x80000>,
- <0x0 0xee900000 0 0x100000>,
- <0x0 0xeea00000 0 0x200000>,
- <0x0 0xc0000000 0 0x8000000>,
- <0x0 0xc8000000 0 0x8000000>;
- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- clock-names = "pcie";
- resets = <&cpg 318>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- vspbc: vsp@fe920000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe920000 0 0x8000>;
- interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 624>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- resets = <&cpg 624>;
-
- renesas,fcp = <&fcpvb1>;
- };
-
- vspbd: vsp@fe960000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe960000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 626>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- resets = <&cpg 626>;
-
- renesas,fcp = <&fcpvb0>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x5000>;
- interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
-
- renesas,fcp = <&fcpvd0>;
- };
-
- vspd1: vsp@fea28000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x5000>;
- interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 622>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 622>;
-
- renesas,fcp = <&fcpvd1>;
- };
-
- vspi0: vsp@fe9a0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9a0000 0 0x8000>;
- interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 631>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- resets = <&cpg 631>;
-
- renesas,fcp = <&fcpvi0>;
- };
-
- vspi1: vsp@fe9b0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9b0000 0 0x8000>;
- interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 630>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- resets = <&cpg 630>;
-
- renesas,fcp = <&fcpvi1>;
- };
-
- fdp1@fe940000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe940000 0 0x2400>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 119>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- resets = <&cpg 119>;
- renesas,fcp = <&fcpf0>;
- };
-
- fdp1@fe944000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe944000 0 0x2400>;
- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 118>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- resets = <&cpg 118>;
- renesas,fcp = <&fcpf1>;
- };
-
- fcpf0: fcp@fe950000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe950000 0 0x200>;
- clocks = <&cpg CPG_MOD 615>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- resets = <&cpg 615>;
- };
-
- fcpf1: fcp@fe951000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe951000 0 0x200>;
- clocks = <&cpg CPG_MOD 614>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- resets = <&cpg 614>;
- };
-
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- resets = <&cpg 607>;
- };
-
- fcpvb1: fcp@fe92f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe92f000 0 0x200>;
- clocks = <&cpg CPG_MOD 606>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- resets = <&cpg 606>;
- };
-
- fcpvi0: fcp@fe9af000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9af000 0 0x200>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- resets = <&cpg 611>;
- };
-
- fcpvi1: fcp@fe9bf000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9bf000 0 0x200>;
- clocks = <&cpg CPG_MOD 610>;
- power-domains = <&sysc R8A774E1_PD_A3VP>;
- resets = <&cpg 610>;
- };
-
- fcpvd0: fcp@fea27000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea27000 0 0x200>;
- clocks = <&cpg CPG_MOD 603>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 603>;
- };
-
- fcpvd1: fcp@fea2f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea2f000 0 0x200>;
- clocks = <&cpg CPG_MOD 602>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 602>;
- };
-
- csi20: csi2@fea80000 {
- compatible = "renesas,r8a774e1-csi2";
- reg = <0 0xfea80000 0 0x10000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi20vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi20>;
- };
- csi20vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi20>;
- };
- csi20vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi20>;
- };
- csi20vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi20>;
- };
- csi20vin4: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&vin4csi20>;
- };
- csi20vin5: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&vin5csi20>;
- };
- csi20vin6: endpoint@6 {
- reg = <6>;
- remote-endpoint = <&vin6csi20>;
- };
- csi20vin7: endpoint@7 {
- reg = <7>;
- remote-endpoint = <&vin7csi20>;
- };
- };
- };
- };
-
- csi40: csi2@feaa0000 {
- compatible = "renesas,r8a774e1-csi2";
- reg = <0 0xfeaa0000 0 0x10000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi40vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi40>;
- };
- csi40vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi40>;
- };
- csi40vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi40>;
- };
- csi40vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi40>;
- };
- };
- };
- };
-
- hdmi0: hdmi@fead0000 {
- compatible = "renesas,r8a774e1-hdmi",
- "renesas,rcar-gen3-hdmi";
- reg = <0 0xfead0000 0 0x10000>;
- interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 729>,
- <&cpg CPG_CORE R8A774E1_CLK_HDMI>;
- clock-names = "iahb", "isfr";
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 729>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dw_hdmi0_in: endpoint {
- remote-endpoint = <&du_out_hdmi0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- port@2 {
- /* HDMI sound */
- reg = <2>;
- };
- };
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a774e1";
- reg = <0 0xfeb00000 0 0x80000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 721>;
- clock-names = "du.0", "du.1", "du.3";
- resets = <&cpg 724>, <&cpg 722>;
- reset-names = "du.0", "du.3";
- status = "disabled";
-
- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- du_out_hdmi0: endpoint {
- remote-endpoint = <&dw_hdmi0_in>;
- };
- };
- port@2 {
- reg = <2>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
- };
- };
-
- lvds0: lvds@feb90000 {
- compatible = "renesas,r8a774e1-lvds";
- reg = <0 0xfeb90000 0 0x14>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
- resets = <&cpg 727>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- sensor1_thermal: sensor1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 0>;
- sustainable-power = <6313>;
-
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor2_thermal: sensor2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 1>;
- sustainable-power = <6313>;
-
- trips {
- sensor2_crit: sensor2-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor3_thermal: sensor3-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 2>;
- sustainable-power = <6313>;
-
- trips {
- target: trip-point1 {
- temperature = <100000>;
- hysteresis = <1000>;
- type = "passive";
- };
-
- sensor3_crit: sensor3-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&a57_0 0 2>;
- contribution = <1024>;
- };
-
- map1 {
- trip = <&target>;
- cooling-device = <&a53_0 0 2>;
- contribution = <1024>;
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- /* External USB clocks - can be overridden by the board */
- usb3s0_clk: usb3s0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Lager board
- *
- * Copyright (C) 2013-2014 Renesas Solutions Corp.
- * Copyright (C) 2014 Cogent Embedded, Inc.
- * Copyright (C) 2015-2016 Renesas Electronics Corporation
- */
-
-/*
- * SSI-AK4643
- *
- * SW1: 1: AK4643
- * 2: CN22
- * 3: ADV7511
- *
- * This command is required when Playback/Capture
- *
- * amixer set "LINEOUT Mixer DACL" on
- * amixer set "DVC Out" 100%
- * amixer set "DVC In" 100%
- *
- * You can use Mute
- *
- * amixer set "DVC Out Mute" on
- * amixer set "DVC In Mute" on
- *
- * You can use Volume Ramp
- *
- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
- * amixer set "DVC Out Ramp" on
- * aplay xxx.wav &
- * amixer set "DVC Out" 80% // Volume Down
- * amixer set "DVC Out" 100% // Volume Up
- */
-
-/dts-v1/;
-#include "r8a7790.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Lager";
- compatible = "renesas,lager", "renesas,r8a7790";
-
- aliases {
- serial0 = &scif0;
- serial1 = &scifa1;
- i2c8 = &gpioi2c1;
- i2c9 = &gpioi2c2;
- i2c10 = &i2cexio0;
- i2c11 = &i2cexio1;
- i2c12 = &i2chdmi;
- i2c13 = &i2cpwr;
- mmc0 = &mmcif1;
- mmc1 = &sdhi0;
- mmc2 = &sdhi2;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0 0x40000000 0 0x40000000>;
- };
-
- memory@140000000 {
- device_type = "memory";
- reg = <1 0x40000000 0 0xc0000000>;
- };
-
- lbsc {
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- keyboard {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&keyboard_pins>;
- pinctrl-names = "default";
-
- one {
- linux,code = <KEY_1>;
- label = "SW2-1";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
- };
- two {
- linux,code = <KEY_2>;
- label = "SW2-2";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
- };
- three {
- linux,code = <KEY_3>;
- label = "SW2-3";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
- };
- four {
- linux,code = <KEY_4>;
- label = "SW2-4";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led6 {
- gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
- };
- led7 {
- gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
- };
- led8 {
- gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
- };
- };
-
- fixedregulator3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vcc_sdhi2: regulator-vcc-sdhi2 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI2 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi2: regulator-vccq-sdhi2 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI2 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- audio_clock: audio_clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <11289600>;
- };
-
- rsnd_ak4643: sound {
- compatible = "simple-audio-card";
-
- simple-audio-card,format = "left_j";
- simple-audio-card,bitclock-master = <&sndcodec>;
- simple-audio-card,frame-master = <&sndcodec>;
-
- sndcpu: simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
-
- sndcodec: simple-audio-card,codec {
- sound-dai = <&ak4643>;
- clocks = <&audio_clock>;
- };
- };
-
- vga-encoder {
- compatible = "adi,adv7123";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7123_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
- port@1 {
- reg = <1>;
- adv7123_out: endpoint {
- remote-endpoint = <&vga_in>;
- };
- };
- };
- };
-
- vga {
- compatible = "vga-connector";
-
- port {
- vga_in: endpoint {
- remote-endpoint = <&adv7123_out>;
- };
- };
- };
-
- hdmi-in {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&adv7612_in>;
- };
- };
- };
-
- cec_clock: cec-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_out: endpoint {
- remote-endpoint = <&adv7511_out>;
- };
- };
- };
-
- x2_clk: x2-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <148500000>;
- };
-
- x13_clk: x13-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <148500000>;
- };
-
- gpioi2c1: i2c-8 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "i2c-gpio";
- status = "disabled";
- scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <5>;
- };
-
- gpioi2c2: i2c-9 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "i2c-gpio";
- status = "disabled";
- scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <5>;
- };
-
- /*
- * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
- * We use the I2C demuxer, so the desired IP core can be selected at runtime
- * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0).
- * Note: For testing the I2C slave feature, it is convenient to connect this
- * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
- * instantiate the slave device at runtime according to the documentation.
- * You can then communicate with the slave via IIC3.
- *
- * IIC0/I2C0 does not appear to support fallback to GPIO.
- */
- i2cexio0: i2c-10 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&iic0>, <&i2c0>;
- i2c-bus-name = "i2c-exio0";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- /*
- * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
- * This is similar to the arangement described for i2cexio0 (above)
- * with a fallback to GPIO also provided.
- */
- i2cexio1: i2c-11 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
- i2c-bus-name = "i2c-exio1";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- /*
- * IIC2 and I2C2 may be switched using pinmux.
- * A fallback to GPIO is also provided.
- */
- i2chdmi: i2c-12 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
- i2c-bus-name = "i2c-hdmi";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ak4643: codec@12 {
- compatible = "asahi-kasei,ak4643";
- #sound-dai-cells = <0>;
- reg = <0x12>;
- };
-
- composite-in@20 {
- compatible = "adi,adv7180";
- reg = <0x20>;
-
- port {
- adv7180: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin1ep0>;
- };
- };
- };
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio1>;
- interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&cec_clock>;
- clock-names = "cec";
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
- };
- };
-
- hdmi-in@4c {
- compatible = "adi,adv7612";
- reg = <0x4c>;
- interrupt-parent = <&gpio1>;
- interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
- default-input = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7612_in: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
- };
-
- port@2 {
- reg = <2>;
- adv7612_out: endpoint {
- remote-endpoint = <&vin0ep2>;
- };
- };
- };
- };
- };
-
- /*
- * IIC3 and I2C3 may be switched using pinmux.
- * IIC3/I2C3 does not appear to support fallback to GPIO.
- */
- i2cpwr: i2c-13 {
- compatible = "i2c-demux-pinctrl";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_irq_pins>;
- i2c-parent = <&iic3>, <&i2c3>;
- i2c-bus-name = "i2c-pwr";
- #address-cells = <1>;
- #size-cells = <0>;
-
- pmic@58 {
- compatible = "dlg,da9063";
- reg = <0x58>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
-
- rtc {
- compatible = "dlg,da9063-rtc";
- };
-
- watchdog {
- compatible = "dlg,da9063-watchdog";
- };
- };
-
- vdd_dvfs: regulator@68 {
- compatible = "dlg,da9210";
- reg = <0x68>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
- <&x13_clk>, <&x2_clk>;
- clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1";
-
- ports {
- port@0 {
- endpoint {
- remote-endpoint = <&adv7123_in>;
- };
- };
- };
-};
-
-&lvds0 {
- status = "okay";
-
- ports {
- port@1 {
- endpoint {
- remote-endpoint = <&adv7511_in>;
- };
- };
- };
-};
-
-&lvds1 {
- ports {
- port@1 {
- lvds_connector: endpoint {
- };
- };
- };
-};
-
-&extal_clk {
- clock-frequency = <20000000>;
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- du_pins: du {
- groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
- function = "du";
- };
-
- scif0_pins: scif0 {
- groups = "scif0_data";
- function = "scif0";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk";
- function = "scif_clk";
- };
-
- ether_pins: ether {
- groups = "eth_link", "eth_mdio", "eth_rmii";
- function = "eth";
- };
-
- phy1_pins: phy1 {
- groups = "intc_irq0";
- function = "intc";
- };
-
- scifa1_pins: scifa1 {
- groups = "scifa1_data";
- function = "scifa1";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi2_pins: sd2 {
- groups = "sdhi2_data4", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <3300>;
- };
-
- sdhi2_pins_uhs: sd2_uhs {
- groups = "sdhi2_data4", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <1800>;
- };
-
- mmc1_pins: mmc1 {
- groups = "mmc1_data8", "mmc1_ctrl";
- function = "mmc1";
- };
-
- qspi_pins: qspi {
- groups = "qspi_ctrl", "qspi_data4";
- function = "qspi";
- };
-
- msiof1_pins: msiof1 {
- groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
- "msiof1_tx";
- function = "msiof1";
- };
-
- i2c0_pins: i2c0 {
- groups = "i2c0";
- function = "i2c0";
- };
-
- iic0_pins: iic0 {
- groups = "iic0";
- function = "iic0";
- };
-
- i2c1_pins: i2c1 {
- groups = "i2c1";
- function = "i2c1";
- };
-
- iic1_pins: iic1 {
- groups = "iic1";
- function = "iic1";
- };
-
- i2c2_pins: i2c2 {
- groups = "i2c2";
- function = "i2c2";
- };
-
- iic2_pins: iic2 {
- groups = "iic2";
- function = "iic2";
- };
-
- i2c3_pins: i2c3 {
- groups = "i2c3";
- function = "i2c3";
- };
-
- iic3_pins: iic3 {
- groups = "iic3";
- function = "iic3";
- };
-
- pmic_irq_pins: pmicirq {
- groups = "intc_irq2";
- function = "intc";
- };
-
- hsusb_pins: hsusb {
- groups = "usb0_ovc_vbus";
- function = "usb0";
- };
-
- usb0_pins: usb0 {
- groups = "usb0";
- function = "usb0";
- };
-
- usb1_pins: usb1 {
- groups = "usb1";
- function = "usb1";
- };
-
- usb2_pins: usb2 {
- groups = "usb2";
- function = "usb2";
- };
-
- vin0_pins: vin0 {
- groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
- function = "vin0";
- };
-
- vin1_pins: vin1 {
- groups = "vin1_data8", "vin1_clk";
- function = "vin1";
- };
-
- sound_pins: sound {
- groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
- function = "ssi";
- };
-
- sound_clk_pins: sound_clk {
- groups = "audio_clk_a";
- function = "audio_clk";
- };
-
- keyboard_pins: keyboard {
- pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28";
- bias-pull-up;
- };
-};
-
-ðer {
- pinctrl-0 = <ðer_pins>, <&phy1_pins>;
- pinctrl-names = "default";
-
- phy-handle = <&phy1>;
- renesas,ether-link-active-low;
- status = "okay";
-
- phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-id0022.1537",
- "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- interrupt-parent = <&irqc0>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- micrel,led-mode = <1>;
- reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
- };
-};
-
-&cmt0 {
- status = "okay";
-};
-
-&mmcif1 {
- pinctrl-0 = <&mmc1_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&fixedregulator3v3>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&sata1 {
- status = "okay";
-};
-
-&qspi {
- pinctrl-0 = <&qspi_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- flash: flash@0 {
- compatible = "spansion,s25fl512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <30000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- spi-cpha;
- spi-cpol;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "loader";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "user";
- reg = <0x00040000 0x00400000>;
- read-only;
- };
- partition@440000 {
- label = "flash";
- reg = <0x00440000 0x03bc0000>;
- };
- };
- };
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scifa1 {
- pinctrl-0 = <&scifa1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&msiof1 {
- pinctrl-0 = <&msiof1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- pmic: pmic@0 {
- compatible = "renesas,r2a11302ft";
- reg = <0>;
- spi-max-frequency = <6000000>;
- spi-cpol;
- spi-cpha;
- };
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdhi2 {
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-1 = <&sdhi2_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi2>;
- vqmmc-supply = <&vccq_sdhi2>;
- cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
- sd-uhs-sdr50;
- status = "okay";
-};
-
-&cpu0 {
- cpu0-supply = <&vdd_dvfs>;
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "i2c-exio0";
-};
-
-&iic0 {
- pinctrl-0 = <&iic0_pins>;
- pinctrl-names = "i2c-exio0";
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "i2c-exio1";
-};
-
-&iic1 {
- pinctrl-0 = <&iic1_pins>;
- pinctrl-names = "i2c-exio1";
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "i2c-hdmi";
-
- clock-frequency = <100000>;
-};
-
-&iic2 {
- pinctrl-0 = <&iic2_pins>;
- pinctrl-names = "i2c-hdmi";
-
- clock-frequency = <100000>;
-};
-
-&i2c3 {
- pinctrl-0 = <&i2c3_pins>;
- pinctrl-names = "i2c-pwr";
-};
-
-&iic3 {
- pinctrl-0 = <&iic3_pins>;
- pinctrl-names = "i2c-pwr";
-};
-
-&pci0 {
- status = "okay";
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-};
-
-&pci1 {
- status = "okay";
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-};
-
-&xhci {
- status = "okay";
- pinctrl-0 = <&usb2_pins>;
- pinctrl-names = "default";
-};
-
-&pci2 {
- status = "okay";
- pinctrl-0 = <&usb2_pins>;
- pinctrl-names = "default";
-};
-
-&hsusb {
- status = "okay";
- pinctrl-0 = <&hsusb_pins>;
- pinctrl-names = "default";
- renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
-};
-
-&usbphy {
- status = "okay";
-};
-
-/* HDMI video input */
-&vin0 {
- pinctrl-0 = <&vin0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- port {
- vin0ep2: endpoint {
- remote-endpoint = <&adv7612_out>;
- bus-width = <24>;
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- data-active = <1>;
- };
- };
-};
-
-/* composite video input */
-&vin1 {
- pinctrl-0 = <&vin1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- port {
- vin1ep0: endpoint {
- remote-endpoint = <&adv7180>;
- bus-width = <8>;
- };
- };
-};
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
- pinctrl-names = "default";
-
- /* Single DAI */
- #sound-dai-cells = <0>;
-
- status = "okay";
-
- rcar_sound,dai {
- dai0 {
- playback = <&ssi0>, <&src2>, <&dvc0>;
- capture = <&ssi1>, <&src3>, <&dvc1>;
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&ssi1 {
- shared-pin;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Stout board
- *
- * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
- */
-
-/dts-v1/;
-#include "r8a7790.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Stout";
- compatible = "renesas,stout", "renesas,r8a7790";
-
- aliases {
- serial0 = &scifa0;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0 0x40000000 0 0x40000000>;
- };
-
- leds {
- compatible = "gpio-leds";
- led1 {
- gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
- };
- led2 {
- gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
- };
- led3 {
- gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
- };
- led5 {
- gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
- };
- };
-
- fixedregulator3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_out: endpoint {
- remote-endpoint = <&adv7511_out>;
- };
- };
- };
-
- osc1_clk: osc1-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <148500000>;
- };
-
- osc4_clk: osc4-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
- <&osc1_clk>;
- clock-names = "du.0", "du.1", "du.2", "dclkin.0";
-
- ports {
- port@0 {
- endpoint {
- remote-endpoint = <&adv7511_in>;
- };
- };
- };
-};
-
-&lvds0 {
- ports {
- port@1 {
- lvds_connector0: endpoint {
- };
- };
- };
-};
-
-&lvds1 {
- ports {
- port@1 {
- lvds_connector1: endpoint {
- };
- };
- };
-};
-
-&extal_clk {
- clock-frequency = <20000000>;
-};
-
-&pfc {
-
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- du_pins: du {
- groups = "du_rgb888", "du_sync_1", "du_clk_out_0";
- function = "du";
- };
-
- scifa0_pins: scifa0 {
- groups = "scifa0_data_b";
- function = "scifa0";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk";
- function = "scif_clk";
- };
-
- ether_pins: ether {
- groups = "eth_link", "eth_mdio", "eth_rmii";
- function = "eth";
- };
-
- phy1_pins: phy1 {
- groups = "intc_irq1";
- function = "intc";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- qspi_pins: qspi {
- groups = "qspi_ctrl", "qspi_data4";
- function = "qspi";
- };
-
- iic2_pins: iic2 {
- groups = "iic2_b";
- function = "iic2";
- };
-
- iic3_pins: iic3 {
- groups = "iic3";
- function = "iic3";
- };
-
- pmic_irq_pins: pmicirq {
- groups = "intc_irq2";
- function = "intc";
- };
-
- usb0_pins: usb0 {
- groups = "usb0";
- function = "usb0";
- };
-};
-
-ðer {
- pinctrl-0 = <ðer_pins>, <&phy1_pins>;
- pinctrl-names = "default";
-
- phy-handle = <&phy1>;
- renesas,ether-link-active-low;
- status = "okay";
-
- phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-id0022.1537",
- "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- interrupt-parent = <&irqc0>;
- interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
- micrel,led-mode = <1>;
- reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
- };
-};
-
-&cmt0 {
- status = "okay";
-};
-
-&qspi {
- pinctrl-0 = <&qspi_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- flash: flash@0 {
- compatible = "spansion,s25fl512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <30000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- spi-cpha;
- spi-cpol;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "loader";
- reg = <0x00000000 0x00080000>;
- read-only;
- };
- partition@80000 {
- label = "uboot";
- reg = <0x00080000 0x00040000>;
- read-only;
- };
- partition@c0000 {
- label = "uboot-env";
- reg = <0x000c0000 0x00040000>;
- read-only;
- };
- partition@100000 {
- label = "flash";
- reg = <0x00100000 0x03f00000>;
- };
- };
- };
-};
-
-&scifa0 {
- pinctrl-0 = <&scifa0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&vcc_sdhi0>;
- cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&cpu0 {
- cpu0-supply = <&vdd_dvfs>;
-};
-
-&iic2 {
- status = "okay";
- pinctrl-0 = <&iic2_pins>;
- pinctrl-names = "default";
-
- clock-frequency = <100000>;
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio1>;
- interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&osc4_clk>;
- clock-names = "cec";
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
- };
- };
-};
-
-&iic3 {
- pinctrl-names = "default";
- pinctrl-0 = <&iic3_pins>, <&pmic_irq_pins>;
- status = "okay";
-
- pmic@58 {
- compatible = "dlg,da9063";
- reg = <0x58>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
-
- onkey {
- compatible = "dlg,da9063-onkey";
- };
-
- rtc {
- compatible = "dlg,da9063-rtc";
- };
-
- watchdog {
- compatible = "dlg,da9063-watchdog";
- };
- };
-
- vdd_dvfs: regulator@68 {
- compatible = "dlg,da9210";
- reg = <0x68>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vdd: regulator@70 {
- compatible = "dlg,da9210";
- reg = <0x70>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&pci0 {
- status = "okay";
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-};
-
-&usbphy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car H2 (R8A77900) SoC
- *
- * Copyright (C) 2015 Renesas Electronics Corporation
- * Copyright (C) 2013-2014 Renesas Solutions Corp.
- * Copyright (C) 2014 Cogent Embedded Inc.
- */
-
-#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/power/r8a7790-sysc.h>
-
-/ {
- compatible = "renesas,r8a7790";
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &iic0;
- i2c5 = &iic1;
- i2c6 = &iic2;
- i2c7 = &iic3;
- spi0 = &qspi;
- spi1 = &msiof0;
- spi2 = &msiof1;
- spi3 = &msiof2;
- spi4 = &msiof3;
- vin0 = &vin0;
- vin1 = &vin1;
- vin2 = &vin2;
- vin3 = &vin3;
- };
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0>;
- clock-frequency = <1300000000>;
- clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
- power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA15>;
- capacity-dmips-mhz = <1024>;
- voltage-tolerance = <1>; /* 1% */
- clock-latency = <300000>; /* 300 us */
-
- /* kHz - uV - OPPs unknown yet */
- operating-points = <1400000 1000000>,
- <1225000 1000000>,
- <1050000 1000000>,
- < 875000 1000000>,
- < 700000 1000000>,
- < 350000 1000000>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <1>;
- clock-frequency = <1300000000>;
- clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
- power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA15>;
- capacity-dmips-mhz = <1024>;
- voltage-tolerance = <1>; /* 1% */
- clock-latency = <300000>; /* 300 us */
-
- /* kHz - uV - OPPs unknown yet */
- operating-points = <1400000 1000000>,
- <1225000 1000000>,
- <1050000 1000000>,
- < 875000 1000000>,
- < 700000 1000000>,
- < 350000 1000000>;
- };
-
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <2>;
- clock-frequency = <1300000000>;
- clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
- power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA15>;
- capacity-dmips-mhz = <1024>;
- voltage-tolerance = <1>; /* 1% */
- clock-latency = <300000>; /* 300 us */
-
- /* kHz - uV - OPPs unknown yet */
- operating-points = <1400000 1000000>,
- <1225000 1000000>,
- <1050000 1000000>,
- < 875000 1000000>,
- < 700000 1000000>,
- < 350000 1000000>;
- };
-
- cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <3>;
- clock-frequency = <1300000000>;
- clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
- power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA15>;
- capacity-dmips-mhz = <1024>;
- voltage-tolerance = <1>; /* 1% */
- clock-latency = <300000>; /* 300 us */
-
- /* kHz - uV - OPPs unknown yet */
- operating-points = <1400000 1000000>,
- <1225000 1000000>,
- <1050000 1000000>,
- < 875000 1000000>,
- < 700000 1000000>,
- < 350000 1000000>;
- };
-
- cpu4: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0x100>;
- clock-frequency = <780000000>;
- clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
- power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA7>;
- capacity-dmips-mhz = <539>;
- };
-
- cpu5: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0x101>;
- clock-frequency = <780000000>;
- clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
- power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA7>;
- capacity-dmips-mhz = <539>;
- };
-
- cpu6: cpu@102 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0x102>;
- clock-frequency = <780000000>;
- clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
- power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA7>;
- capacity-dmips-mhz = <539>;
- };
-
- cpu7: cpu@103 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0x103>;
- clock-frequency = <780000000>;
- clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
- power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA7>;
- capacity-dmips-mhz = <539>;
- };
-
- L2_CA15: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A7790_PD_CA15_SCU>;
- cache-unified;
- cache-level = <2>;
- };
-
- L2_CA7: cache-controller-1 {
- compatible = "cache";
- power-domains = <&sysc R8A7790_PD_CA7_SCU>;
- cache-unified;
- cache-level = <2>;
- };
- };
-
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- pmu-0 {
- compatible = "arm,cortex-a15-pmu";
- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- pmu-1 {
- compatible = "arm,cortex-a7-pmu";
- interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
- };
-
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
-
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a7790-wdt",
- "renesas,rcar-gen2-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a7790",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a7790",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 30>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a7790",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 30>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a7790",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a7790",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a7790",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a7790";
- reg = <0 0xe6060000 0 0x250>;
- };
-
- tpu: pwm@e60f0000 {
- compatible = "renesas,tpu-r8a7790", "renesas,tpu";
- reg = <0 0xe60f0000 0 0x148>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 304>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 304>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7790-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&usb_extal_clk>;
- clock-names = "extal", "usb_extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- apmu@e6151000 {
- compatible = "renesas,r8a7790-apmu", "renesas,apmu";
- reg = <0 0xe6151000 0 0x188>;
- cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
- };
-
- apmu@e6152000 {
- compatible = "renesas,r8a7790-apmu", "renesas,apmu";
- reg = <0 0xe6152000 0 0x188>;
- cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7790-rst";
- reg = <0 0xe6160000 0 0x0100>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7790-sysc";
- reg = <0 0xe6180000 0 0x0200>;
- #power-domain-cells = <1>;
- };
-
- irqc0: interrupt-controller@e61c0000 {
- compatible = "renesas,irqc-r8a7790", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- thermal: thermal@e61f0000 {
- compatible = "renesas,thermal-r8a7790",
- "renesas,rcar-gen2-thermal",
- "renesas,rcar-thermal";
- reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <0>;
- };
-
- ipmmu_sy0: iommu@e6280000 {
- compatible = "renesas,ipmmu-r8a7790",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe6280000 0 0x1000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_sy1: iommu@e6290000 {
- compatible = "renesas,ipmmu-r8a7790",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe6290000 0 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_ds: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a7790",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe6740000 0 0x1000>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_mp: iommu@ec680000 {
- compatible = "renesas,ipmmu-r8a7790",
- "renesas,ipmmu-vmsa";
- reg = <0 0xec680000 0 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_mx: iommu@fe951000 {
- compatible = "renesas,ipmmu-r8a7790",
- "renesas,ipmmu-vmsa";
- reg = <0 0xfe951000 0 0x1000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_rt: iommu@ffc80000 {
- compatible = "renesas,ipmmu-r8a7790",
- "renesas,ipmmu-vmsa";
- reg = <0 0xffc80000 0 0x1000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- icram0: sram@e63a0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63a0000 0 0x12000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63a0000 0x12000>;
- };
-
- icram1: sram@e63c0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63c0000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63c0000 0x1000>;
-
- smp-sram@0 {
- compatible = "renesas,smp-sram";
- reg = <0 0x100>;
- };
- };
-
- i2c0: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7790",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c1: i2c@e6518000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7790",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6518000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6530000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7790",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6530000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e6540000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7790",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6540000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- iic0: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7790",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6500000 0 0x425>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- dmas = <&dmac0 0x61>, <&dmac0 0x62>,
- <&dmac1 0x61>, <&dmac1 0x62>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- status = "disabled";
- };
-
- iic1: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7790",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6510000 0 0x425>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 323>;
- dmas = <&dmac0 0x65>, <&dmac0 0x66>,
- <&dmac1 0x65>, <&dmac1 0x66>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 323>;
- status = "disabled";
- };
-
- iic2: i2c@e6520000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7790",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6520000 0 0x425>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
- <&dmac1 0x69>, <&dmac1 0x6a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
-
- iic3: i2c@e60b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7790",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- dmas = <&dmac0 0x77>, <&dmac0 0x78>,
- <&dmac1 0x77>, <&dmac1 0x78>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a7790",
- "renesas,rcar-gen2-usbhs";
- reg = <0 0xe6590000 0 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usbphy: usb-phy-controller@e6590100 {
- compatible = "renesas,usb-phy-r8a7790",
- "renesas,rcar-gen2-usb-phy";
- reg = <0 0xe6590100 0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cpg CPG_MOD 704>;
- clock-names = "usbhs";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- status = "disabled";
-
- usb0: usb-phy@0 {
- reg = <0>;
- #phy-cells = <1>;
- };
- usb2: usb-phy@2 {
- reg = <2>;
- #phy-cells = <1>;
- };
- };
-
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a7790-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a7790-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a7790",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
-
- dmac1: dma-controller@e6720000 {
- compatible = "renesas,dmac-r8a7790",
- "renesas,rcar-dmac";
- reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7790",
- "renesas,etheravb-rcar-gen2";
- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7790", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>,
- <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- scifa0: serial@e6c40000 {
- compatible = "renesas,scifa-r8a7790",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>;
- clock-names = "fck";
- dmas = <&dmac0 0x21>, <&dmac0 0x22>,
- <&dmac1 0x21>, <&dmac1 0x22>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scifa1: serial@e6c50000 {
- compatible = "renesas,scifa-r8a7790",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>;
- clock-names = "fck";
- dmas = <&dmac0 0x25>, <&dmac0 0x26>,
- <&dmac1 0x25>, <&dmac1 0x26>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scifa2: serial@e6c60000 {
- compatible = "renesas,scifa-r8a7790",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c60000 0 64>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>;
- clock-names = "fck";
- dmas = <&dmac0 0x27>, <&dmac0 0x28>,
- <&dmac1 0x27>, <&dmac1 0x28>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- scifb0: serial@e6c20000 {
- compatible = "renesas,scifb-r8a7790",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c20000 0 0x100>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>;
- clock-names = "fck";
- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
- <&dmac1 0x3d>, <&dmac1 0x3e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scifb1: serial@e6c30000 {
- compatible = "renesas,scifb-r8a7790",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c30000 0 0x100>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>;
- clock-names = "fck";
- dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
- <&dmac1 0x19>, <&dmac1 0x1a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scifb2: serial@e6ce0000 {
- compatible = "renesas,scifb-r8a7790",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6ce0000 0 0x100>;
- interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 216>;
- clock-names = "fck";
- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
- <&dmac1 0x1d>, <&dmac1 0x1e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 216>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a7790",
- "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 721>,
- <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
- <&dmac1 0x29>, <&dmac1 0x2a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 721>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a7790",
- "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 720>,
- <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
- <&dmac1 0x2d>, <&dmac1 0x2e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 720>;
- status = "disabled";
- };
-
- scif2: serial@e6e56000 {
- compatible = "renesas,scif-r8a7790",
- "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e56000 0 64>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>,
- <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
- <&dmac1 0x2b>, <&dmac1 0x2c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 310>;
- status = "disabled";
- };
-
- hscif0: serial@e62c0000 {
- compatible = "renesas,hscif-r8a7790",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c0000 0 96>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 717>,
- <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
- <&dmac1 0x39>, <&dmac1 0x3a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 717>;
- status = "disabled";
- };
-
- hscif1: serial@e62c8000 {
- compatible = "renesas,hscif-r8a7790",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c8000 0 96>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>,
- <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
- <&dmac1 0x4d>, <&dmac1 0x4e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
- };
-
- msiof0: spi@e6e20000 {
- compatible = "renesas,msiof-r8a7790",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e20000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 0>;
- dmas = <&dmac0 0x51>, <&dmac0 0x52>,
- <&dmac1 0x51>, <&dmac1 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6e10000 {
- compatible = "renesas,msiof-r8a7790",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e10000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x55>, <&dmac0 0x56>,
- <&dmac1 0x55>, <&dmac1 0x56>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6e00000 {
- compatible = "renesas,msiof-r8a7790",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 205>;
- dmas = <&dmac0 0x41>, <&dmac0 0x42>,
- <&dmac1 0x41>, <&dmac1 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 205>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c90000 {
- compatible = "renesas,msiof-r8a7790",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6c90000 0 0x0064>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 215>;
- dmas = <&dmac0 0x45>, <&dmac0 0x46>,
- <&dmac1 0x45>, <&dmac1 0x46>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 215>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm5: pwm@e6e35000 {
- compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
- reg = <0 0xe6e35000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm6: pwm@e6e36000 {
- compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
- reg = <0 0xe6e36000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- can0: can@e6e80000 {
- compatible = "renesas,can-r8a7790",
- "renesas,rcar-gen2-can";
- reg = <0 0xe6e80000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6e88000 {
- compatible = "renesas,can-r8a7790",
- "renesas,rcar-gen2-can";
- reg = <0 0xe6e88000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7790",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- status = "disabled";
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7790",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- status = "disabled";
- };
-
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a7790",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- status = "disabled";
- };
-
- vin3: video@e6ef3000 {
- compatible = "renesas,vin-r8a7790",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- status = "disabled";
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a7790",
- "renesas,rcar_sound-gen2";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
- <&cpg CPG_CORE R8A7790_CLK_M2>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6",
- "src.5", "src.4", "src.3", "src.2",
- "src.1", "src.0",
- "ctu.0", "ctu.1",
- "mix.0", "mix.1",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>,
- <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>,
- <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0";
-
- status = "disabled";
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma1 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma1 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>,
- <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>,
- <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>,
- <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>,
- <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>,
- <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>,
- <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>,
- <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>,
- <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>,
- <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>,
- <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- };
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a7790",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
-
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a7790",
- "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
-
- xhci: usb@ee000000 {
- compatible = "renesas,xhci-r8a7790",
- "renesas,rcar-gen2-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- phys = <&usb2 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- pci0: pci@ee090000 {
- compatible = "renesas,pci-r8a7790",
- "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee090000 0 0xc00>,
- <0 0xee080000 0 0x1100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xf800 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x800 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
- };
-
- usb@2,0 {
- reg = <0x1000 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
- };
- };
-
- pci1: pci@ee0b0000 {
- compatible = "renesas,pci-r8a7790",
- "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee0b0000 0 0xc00>,
- <0 0xee0a0000 0 0x1100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <1 1>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
- interrupt-map-mask = <0xf800 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pci2: pci@ee0d0000 {
- compatible = "renesas,pci-r8a7790",
- "renesas,pci-rcar-gen2";
- device_type = "pci";
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- reg = <0 0xee0d0000 0 0xc00>,
- <0 0xee0c0000 0 0x1100>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
-
- bus-range = <2 2>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xf800 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x20800 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
- };
-
- usb@2,0 {
- reg = <0x21000 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
- };
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a7790",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
-
- sdhi1: mmc@ee120000 {
- compatible = "renesas,sdhi-r8a7790",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee120000 0 0x328>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 313>;
- dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
- <&dmac1 0xc9>, <&dmac1 0xca>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 313>;
- status = "disabled";
- };
-
- sdhi2: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a7790",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee140000 0 0x100>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>;
- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
- <&dmac1 0xc1>, <&dmac1 0xc2>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- status = "disabled";
- };
-
- sdhi3: mmc@ee160000 {
- compatible = "renesas,sdhi-r8a7790",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee160000 0 0x100>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>;
- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
- <&dmac1 0xd3>, <&dmac1 0xd4>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
-
- mmcif0: mmc@ee200000 {
- compatible = "renesas,mmcif-r8a7790",
- "renesas,sh-mmcif";
- reg = <0 0xee200000 0 0x80>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 315>;
- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
- <&dmac1 0xd1>, <&dmac1 0xd2>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 315>;
- reg-io-width = <4>;
- status = "disabled";
- max-frequency = <97500000>;
- };
-
- mmcif1: mmc@ee220000 {
- compatible = "renesas,mmcif-r8a7790",
- "renesas,sh-mmcif";
- reg = <0 0xee220000 0 0x80>;
- interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 305>;
- dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
- <&dmac1 0xe1>, <&dmac1 0xe2>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 305>;
- reg-io-width = <4>;
- status = "disabled";
- max-frequency = <97500000>;
- };
-
- sata0: sata@ee300000 {
- compatible = "renesas,sata-r8a7790",
- "renesas,rcar-gen2-sata";
- reg = <0 0xee300000 0 0x200000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 815>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 815>;
- status = "disabled";
- };
-
- sata1: sata@ee500000 {
- compatible = "renesas,sata-r8a7790",
- "renesas,rcar-gen2-sata";
- reg = <0 0xee500000 0 0x200000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 814>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 814>;
- status = "disabled";
- };
-
- ether: ethernet@ee700000 {
- compatible = "renesas,ether-r8a7790",
- "renesas,rcar-gen2-ether";
- reg = <0 0xee700000 0 0x400>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- phy-mode = "rmii";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1001000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
- <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- pciec: pcie@fe000000 {
- compatible = "renesas,pcie-r8a7790",
- "renesas,pcie-rcar-gen2";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
- <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- status = "disabled";
- };
-
- vsp@fe920000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe920000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 130>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 130>;
- };
-
- vsp@fe928000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe928000 0 0x8000>;
- interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 131>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 131>;
- };
-
- vsp@fe930000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe930000 0 0x8000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 128>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 128>;
- };
-
- vsp@fe938000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe938000 0 0x8000>;
- interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 127>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 127>;
- };
-
- fdp1@fe940000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe940000 0 0x2400>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 119>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 119>;
- };
-
- fdp1@fe944000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe944000 0 0x2400>;
- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 118>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 118>;
- };
-
- fdp1@fe948000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe948000 0 0x2400>;
- interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 117>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 117>;
- };
-
- jpu: jpeg-codec@fe980000 {
- compatible = "renesas,jpu-r8a7790",
- "renesas,rcar-gen2-jpu";
- reg = <0 0xfe980000 0 0x10300>;
- interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 106>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 106>;
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a7790";
- reg = <0 0xfeb00000 0 0x70000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>;
- clock-names = "du.0", "du.1", "du.2";
- resets = <&cpg 724>;
- reset-names = "du.0";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- du_out_rgb: endpoint {
- };
- };
- port@1 {
- reg = <1>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
- port@2 {
- reg = <2>;
- du_out_lvds1: endpoint {
- remote-endpoint = <&lvds1_in>;
- };
- };
- };
- };
-
- lvds0: lvds@feb90000 {
- compatible = "renesas,r8a7790-lvds";
- reg = <0 0xfeb90000 0 0x1c>;
- clocks = <&cpg CPG_MOD 726>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 726>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
- port@1 {
- reg = <1>;
- lvds0_out: endpoint {
- };
- };
- };
- };
-
- lvds1: lvds@feb94000 {
- compatible = "renesas,r8a7790-lvds";
- reg = <0 0xfeb94000 0 0x1c>;
- clocks = <&cpg CPG_MOD 725>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 725>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds1_in: endpoint {
- remote-endpoint = <&du_out_lvds1>;
- };
- };
- port@1 {
- reg = <1>;
- lvds1_out: endpoint {
- };
- };
- };
- };
-
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
- };
-
- cmt0: timer@ffca0000 {
- compatible = "renesas,r8a7790-cmt0",
- "renesas,rcar-gen2-cmt0";
- reg = <0 0xffca0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
-
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7790-cmt1",
- "renesas,rcar-gen2-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 329>;
- clock-names = "fck";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 329>;
-
- status = "disabled";
- };
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
- thermal-sensors = <&thermal>;
-
- trips {
- cpu-crit {
- temperature = <95000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
- cooling-maps {
- };
- };
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- /* External USB clock - can be overridden by the board */
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Koelsch board
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- * Copyright (C) 2013-2014 Renesas Solutions Corp.
- * Copyright (C) 2014 Cogent Embedded, Inc.
- */
-
-/*
- * SSI-AK4643
- *
- * SW1: 1: AK4643
- * 2: CN22
- * 3: ADV7511
- *
- * This command is required when Playback/Capture
- *
- * amixer set "LINEOUT Mixer DACL" on
- * amixer set "DVC Out" 100%
- * amixer set "DVC In" 100%
- *
- * You can use Mute
- *
- * amixer set "DVC Out Mute" on
- * amixer set "DVC In Mute" on
- *
- * You can use Volume Ramp
- *
- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
- * amixer set "DVC Out Ramp" on
- * aplay xxx.wav &
- * amixer set "DVC Out" 80% // Volume Down
- * amixer set "DVC Out" 100% // Volume Up
- */
-
-/dts-v1/;
-#include "r8a7791.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Koelsch";
- compatible = "renesas,koelsch", "renesas,r8a7791";
-
- aliases {
- serial0 = &scif0;
- serial1 = &scif1;
- i2c9 = &gpioi2c1;
- i2c10 = &gpioi2c2;
- i2c11 = &gpioi2c4;
- i2c12 = &i2cexio1;
- i2c13 = &i2chdmi;
- i2c14 = &i2cexio4;
- mmc0 = &sdhi0;
- mmc1 = &sdhi1;
- mmc2 = &sdhi2;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0 0x40000000 0 0x40000000>;
- };
-
- memory@200000000 {
- device_type = "memory";
- reg = <2 0x00000000 0 0x40000000>;
- };
-
- lbsc {
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- keyboard {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&keyboard_pins>;
- pinctrl-names = "default";
-
- key-1 {
- gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_1>;
- label = "SW2-1";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-2 {
- gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_2>;
- label = "SW2-2";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-3 {
- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_3>;
- label = "SW2-3";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-4 {
- gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_4>;
- label = "SW2-4";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-a {
- gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_A>;
- label = "SW30";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-b {
- gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_B>;
- label = "SW31";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-c {
- gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_C>;
- label = "SW32";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-d {
- gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_D>;
- label = "SW33";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-e {
- gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_E>;
- label = "SW34";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-f {
- gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_F>;
- label = "SW35";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-g {
- gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_G>;
- label = "SW36";
- wakeup-source;
- debounce-interval = <20>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led6 {
- gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- label = "LED6";
- };
- led7 {
- gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
- label = "LED7";
- };
- led8 {
- gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
- label = "LED8";
- };
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vcc_sdhi1: regulator-vcc-sdhi1 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI1 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi1: regulator-vccq-sdhi1 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI1 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vcc_sdhi2: regulator-vcc-sdhi2 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI2 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi2: regulator-vccq-sdhi2 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI2 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- audio_clock: audio_clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <11289600>;
- };
-
- rsnd_ak4643: sound {
- compatible = "simple-audio-card";
-
- simple-audio-card,format = "left_j";
- simple-audio-card,bitclock-master = <&sndcodec>;
- simple-audio-card,frame-master = <&sndcodec>;
-
- sndcpu: simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
-
- sndcodec: simple-audio-card,codec {
- sound-dai = <&ak4643>;
- clocks = <&audio_clock>;
- };
- };
-
- hdmi-in {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&adv7612_in>;
- };
- };
- };
-
- cec_clock: cec-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_out: endpoint {
- remote-endpoint = <&adv7511_out>;
- };
- };
- };
-
- x2_clk: x2-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <74250000>;
- };
-
- x13_clk: x13-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <148500000>;
- };
-
- gpioi2c1: i2c-9 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "i2c-gpio";
- status = "disabled";
- scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <5>;
- };
-
- gpioi2c2: i2c-10 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "i2c-gpio";
- status = "disabled";
- scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <5>;
- };
-
- gpioi2c4: i2c-11 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "i2c-gpio";
- status = "disabled";
- scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <5>;
- };
-
- /*
- * I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA).
- * A fallback to GPIO is provided.
- */
- i2cexio1: i2c-12 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&i2c1>, <&gpioi2c1>;
- i2c-bus-name = "i2c-exio1";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- /*
- * A fallback to GPIO is provided for I2C2.
- */
- i2chdmi: i2c-13 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&i2c2>, <&gpioi2c2>;
- i2c-bus-name = "i2c-hdmi";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ak4643: codec@12 {
- compatible = "asahi-kasei,ak4643";
- #sound-dai-cells = <0>;
- reg = <0x12>;
- };
-
- composite-in@20 {
- compatible = "adi,adv7180";
- reg = <0x20>;
-
- port {
- adv7180: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin1ep>;
- };
- };
- };
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio3>;
- interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&cec_clock>;
- clock-names = "cec";
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
- };
- };
-
- hdmi-in@4c {
- compatible = "adi,adv7612";
- reg = <0x4c>;
- interrupt-parent = <&gpio4>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- default-input = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7612_in: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
- };
-
- port@2 {
- reg = <2>;
- adv7612_out: endpoint {
- remote-endpoint = <&vin0ep2>;
- };
- };
- };
- };
-
- eeprom@50 {
- compatible = "renesas,r1ex24002", "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
- };
-
- /*
- * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
- * A fallback to GPIO is provided.
- */
- i2cexio4: i2c-14 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&i2c4>, <&gpioi2c4>;
- i2c-bus-name = "i2c-exio4";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
- <&x13_clk>, <&x2_clk>;
- clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
-
- ports {
- port@0 {
- endpoint {
- remote-endpoint = <&adv7511_in>;
- };
- };
- };
-};
-
-&lvds0 {
- ports {
- port@1 {
- lvds_connector: endpoint {
- };
- };
- };
-};
-
-&extal_clk {
- clock-frequency = <20000000>;
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- i2c1_pins: i2c1 {
- groups = "i2c1";
- function = "i2c1";
- };
-
- i2c2_pins: i2c2 {
- groups = "i2c2";
- function = "i2c2";
- };
-
- i2c4_pins: i2c4 {
- groups = "i2c4_c";
- function = "i2c4";
- };
-
- du_pins: du {
- groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
- function = "du";
- };
-
- scif0_pins: scif0 {
- groups = "scif0_data_d";
- function = "scif0";
- };
-
- scif1_pins: scif1 {
- groups = "scif1_data_d";
- function = "scif1";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk";
- function = "scif_clk";
- };
-
- ether_pins: ether {
- groups = "eth_link", "eth_mdio", "eth_rmii";
- function = "eth";
- };
-
- phy1_pins: phy1 {
- groups = "intc_irq0";
- function = "intc";
- };
-
- pmic_irq_pins: pmicirq {
- groups = "intc_irq2";
- function = "intc";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi1_pins: sd1 {
- groups = "sdhi1_data4", "sdhi1_ctrl";
- function = "sdhi1";
- power-source = <3300>;
- };
-
- sdhi1_pins_uhs: sd1_uhs {
- groups = "sdhi1_data4", "sdhi1_ctrl";
- function = "sdhi1";
- power-source = <1800>;
- };
-
- sdhi2_pins: sd2 {
- groups = "sdhi2_data4", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <3300>;
- };
-
- sdhi2_pins_uhs: sd2_uhs {
- groups = "sdhi2_data4", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <1800>;
- };
-
- qspi_pins: qspi {
- groups = "qspi_ctrl", "qspi_data4";
- function = "qspi";
- };
-
- msiof0_pins: msiof0 {
- groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
- "msiof0_tx";
- function = "msiof0";
- };
-
- usb0_pins: usb0 {
- groups = "usb0";
- function = "usb0";
- };
-
- usb1_pins: usb1 {
- groups = "usb1";
- function = "usb1";
- };
-
- vin0_pins: vin0 {
- groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
- function = "vin0";
- };
-
- vin1_pins: vin1 {
- groups = "vin1_data8", "vin1_clk";
- function = "vin1";
- };
-
- sound_pins: sound {
- groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
- function = "ssi";
- };
-
- sound_clk_pins: sound_clk {
- groups = "audio_clk_a";
- function = "audio_clk";
- };
-
- keyboard_pins: keyboard {
- pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3";
- bias-pull-up;
- };
-};
-
-ðer {
- pinctrl-0 = <ðer_pins>, <&phy1_pins>;
- pinctrl-names = "default";
-
- phy-handle = <&phy1>;
- renesas,ether-link-active-low;
- status = "okay";
-
- phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-id0022.1537",
- "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- interrupt-parent = <&irqc0>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- micrel,led-mode = <1>;
- reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
- };
-};
-
-&cmt0 {
- status = "okay";
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&sata0 {
- status = "okay";
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif1 {
- pinctrl-0 = <&scif1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdhi1 {
- pinctrl-0 = <&sdhi1_pins>;
- pinctrl-1 = <&sdhi1_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi1>;
- vqmmc-supply = <&vccq_sdhi1>;
- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
- sd-uhs-sdr50;
- status = "okay";
-};
-
-&sdhi2 {
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-1 = <&sdhi2_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi2>;
- vqmmc-supply = <&vccq_sdhi2>;
- cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
- sd-uhs-sdr50;
- status = "okay";
-};
-
-&qspi {
- pinctrl-0 = <&qspi_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- flash: flash@0 {
- compatible = "spansion,s25fl512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <30000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- spi-cpha;
- spi-cpol;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "loader";
- reg = <0x00000000 0x00080000>;
- read-only;
- };
- partition@80000 {
- label = "user";
- reg = <0x00080000 0x00580000>;
- read-only;
- };
- partition@600000 {
- label = "flash";
- reg = <0x00600000 0x03a00000>;
- };
- };
- };
-};
-
-&msiof0 {
- pinctrl-0 = <&msiof0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- pmic: pmic@0 {
- compatible = "renesas,r2a11302ft";
- reg = <0>;
- spi-max-frequency = <6000000>;
- spi-cpol;
- spi-cpha;
- };
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "i2c-exio1";
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "i2c-hdmi";
-
- clock-frequency = <100000>;
-};
-
-&i2c4 {
- pinctrl-0 = <&i2c4_pins>;
- pinctrl-names = "i2c-exio4";
-};
-
-&i2c6 {
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_irq_pins>;
- status = "okay";
- clock-frequency = <100000>;
-
- pmic@58 {
- compatible = "dlg,da9063";
- reg = <0x58>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
-
- rtc {
- compatible = "dlg,da9063-rtc";
- };
-
- watchdog {
- compatible = "dlg,da9063-watchdog";
- };
- };
-
- vdd_dvfs: regulator@68 {
- compatible = "dlg,da9210";
- reg = <0x68>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&pci0 {
- status = "okay";
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-};
-
-&pci1 {
- status = "okay";
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-};
-
-&hsusb {
- status = "okay";
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
- renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
-};
-
-&usbphy {
- status = "okay";
-};
-
-&pcie_bus_clk {
- clock-frequency = <100000000>;
-};
-
-&pciec {
- status = "okay";
-};
-
-&cpu0 {
- cpu0-supply = <&vdd_dvfs>;
-};
-
-/* HDMI video input */
-&vin0 {
- status = "okay";
- pinctrl-0 = <&vin0_pins>;
- pinctrl-names = "default";
-
- port {
- vin0ep2: endpoint {
- remote-endpoint = <&adv7612_out>;
- bus-width = <24>;
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- data-active = <1>;
- };
- };
-};
-
-/* composite video input */
-&vin1 {
- status = "okay";
- pinctrl-0 = <&vin1_pins>;
- pinctrl-names = "default";
-
- port {
- vin1ep: endpoint {
- remote-endpoint = <&adv7180>;
- bus-width = <8>;
- };
- };
-};
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
- pinctrl-names = "default";
-
- /* Single DAI */
- #sound-dai-cells = <0>;
-
- status = "okay";
-
- rcar_sound,dai {
- dai0 {
- playback = <&ssi0>, <&src2>, <&dvc0>;
- capture = <&ssi1>, <&src3>, <&dvc1>;
- };
- };
-};
-
-&ssi1 {
- shared-pin;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Porter board
- *
- * Copyright (C) 2015 Cogent Embedded, Inc.
- */
-
-/*
- * SSI-AK4642
- *
- * JP3: 2-1: AK4642
- * 2-3: ADV7511
- *
- * This command is required before playback/capture:
- *
- * amixer set "LINEOUT Mixer DACL" on
- */
-
-/dts-v1/;
-#include "r8a7791.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Porter";
- compatible = "renesas,porter", "renesas,r8a7791";
-
- aliases {
- serial0 = &scif0;
- i2c9 = &gpioi2c2;
- i2c10 = &i2chdmi;
- mmc0 = &sdhi0;
- mmc1 = &sdhi2;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0 0x40000000 0 0x40000000>;
- };
-
- memory@200000000 {
- device_type = "memory";
- reg = <2 0x00000000 0 0x40000000>;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vcc_sdhi2: regulator-vcc-sdhi2 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI2 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vccq_sdhi2: regulator-vccq-sdhi2 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI2 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con: endpoint {
- remote-endpoint = <&adv7511_out>;
- };
- };
- };
-
- x3_clk: x3-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <148500000>;
- };
-
- x16_clk: x16-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <74250000>;
- };
-
- x14_clk: audio_clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <11289600>;
- };
-
- sound {
- compatible = "simple-audio-card";
-
- simple-audio-card,format = "left_j";
- simple-audio-card,bitclock-master = <&soundcodec>;
- simple-audio-card,frame-master = <&soundcodec>;
-
- simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
-
- soundcodec: simple-audio-card,codec {
- sound-dai = <&ak4642>;
- clocks = <&x14_clk>;
- };
- };
-
- gpioi2c2: i2c-9 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "i2c-gpio";
- status = "disabled";
- scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <5>;
- };
-
- /*
- * A fallback to GPIO is provided for I2C2.
- */
- i2chdmi: i2c-10 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&i2c2>, <&gpioi2c2>;
- i2c-bus-name = "i2c-hdmi";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ak4642: codec@12 {
- compatible = "asahi-kasei,ak4642";
- #sound-dai-cells = <0>;
- reg = <0x12>;
- };
-
- composite-in@20 {
- compatible = "adi,adv7180";
- reg = <0x20>;
-
- port {
- adv7180: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin0ep>;
- };
- };
- };
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio3>;
- interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con>;
- };
- };
- };
- };
- };
-};
-
-&extal_clk {
- clock-frequency = <20000000>;
-};
-
-&pfc {
- scif0_pins: scif0 {
- groups = "scif0_data_d";
- function = "scif0";
- };
-
- ether_pins: ether {
- groups = "eth_link", "eth_mdio", "eth_rmii";
- function = "eth";
- };
-
- phy1_pins: phy1 {
- groups = "intc_irq0";
- function = "intc";
- };
-
- pmic_irq_pins: pmicirq {
- groups = "intc_irq2";
- function = "intc";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- };
-
- sdhi2_pins: sd2 {
- groups = "sdhi2_data4", "sdhi2_ctrl";
- function = "sdhi2";
- };
-
- qspi_pins: qspi {
- groups = "qspi_ctrl", "qspi_data4";
- function = "qspi";
- };
-
- i2c2_pins: i2c2 {
- groups = "i2c2";
- function = "i2c2";
- };
-
- usb0_pins: usb0 {
- groups = "usb0";
- function = "usb0";
- };
-
- usb1_pins: usb1 {
- groups = "usb1";
- function = "usb1";
- };
-
- vin0_pins: vin0 {
- groups = "vin0_data8", "vin0_clk";
- function = "vin0";
- };
-
- can0_pins: can0 {
- groups = "can0_data";
- function = "can0";
- };
-
- du_pins: du {
- groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
- function = "du";
- };
-
- ssi_pins: sound {
- groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
- function = "ssi";
- };
-
- audio_clk_pins: audio_clk {
- groups = "audio_clk_a";
- function = "audio_clk";
- };
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-ðer {
- pinctrl-0 = <ðer_pins>, <&phy1_pins>;
- pinctrl-names = "default";
-
- phy-handle = <&phy1>;
- renesas,ether-link-active-low;
- status = "okay";
-
- phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-id0022.1537",
- "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- interrupt-parent = <&irqc0>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- micrel,led-mode = <1>;
- reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
- };
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&sdhi2 {
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&vcc_sdhi2>;
- vqmmc-supply = <&vccq_sdhi2>;
- cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&qspi {
- pinctrl-0 = <&qspi_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- flash@0 {
- compatible = "spansion,s25fl512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <30000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "loader_prg";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "user_prg";
- reg = <0x00040000 0x00400000>;
- read-only;
- };
- partition@440000 {
- label = "flash_fs";
- reg = <0x00440000 0x03bc0000>;
- };
- };
- };
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "i2c-hdmi";
-
- clock-frequency = <400000>;
-};
-
-&i2c6 {
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_irq_pins>;
- status = "okay";
- clock-frequency = <100000>;
-
- pmic@5a {
- compatible = "dlg,da9063l";
- reg = <0x5a>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
-
- watchdog {
- compatible = "dlg,da9063-watchdog";
- };
- };
-
- vdd_dvfs: regulator@68 {
- compatible = "dlg,da9210";
- reg = <0x68>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&sata0 {
- status = "okay";
-};
-
-&cpu0 {
- cpu0-supply = <&vdd_dvfs>;
-};
-
-/* composite video input */
-&vin0 {
- status = "okay";
- pinctrl-0 = <&vin0_pins>;
- pinctrl-names = "default";
-
- port {
- vin0ep: endpoint {
- remote-endpoint = <&adv7180>;
- bus-width = <8>;
- };
- };
-};
-
-&pci0 {
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&pci1 {
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&hsusb {
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-&pcie_bus_clk {
- clock-frequency = <100000000>;
-};
-
-&pciec {
- status = "okay";
-};
-
-&can0 {
- pinctrl-0 = <&can0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
- <&x3_clk>, <&x16_clk>;
- clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
-
- ports {
- port@0 {
- endpoint {
- remote-endpoint = <&adv7511_in>;
- };
- };
- };
-};
-
-&lvds0 {
- ports {
- port@1 {
- lvds_connector: endpoint {
- };
- };
- };
-};
-
-&rcar_sound {
- pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /* Single DAI */
- #sound-dai-cells = <0>;
-
- rcar_sound,dai {
- dai0 {
- playback = <&ssi0>;
- capture = <&ssi1>;
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&ssi1 {
- shared-pin;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car M2-W (R8A77910) SoC
- *
- * Copyright (C) 2013-2015 Renesas Electronics Corporation
- * Copyright (C) 2013-2014 Renesas Solutions Corp.
- * Copyright (C) 2014 Cogent Embedded Inc.
- */
-
-#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/power/r8a7791-sysc.h>
-
-/ {
- compatible = "renesas,r8a7791";
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &i2c7;
- i2c8 = &i2c8;
- spi0 = &qspi;
- spi1 = &msiof0;
- spi2 = &msiof1;
- spi3 = &msiof2;
- vin0 = &vin0;
- vin1 = &vin1;
- vin2 = &vin2;
- };
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0>;
- clock-frequency = <1500000000>;
- clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
- power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA15>;
- voltage-tolerance = <1>; /* 1% */
- clock-latency = <300000>; /* 300 us */
-
- /* kHz - uV - OPPs unknown yet */
- operating-points = <1500000 1000000>,
- <1312500 1000000>,
- <1125000 1000000>,
- < 937500 1000000>,
- < 750000 1000000>,
- < 375000 1000000>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <1>;
- clock-frequency = <1500000000>;
- clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
- power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA15>;
- voltage-tolerance = <1>; /* 1% */
- clock-latency = <300000>; /* 300 us */
-
- /* kHz - uV - OPPs unknown yet */
- operating-points = <1500000 1000000>,
- <1312500 1000000>,
- <1125000 1000000>,
- < 937500 1000000>,
- < 750000 1000000>,
- < 375000 1000000>;
- };
-
- L2_CA15: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A7791_PD_CA15_SCU>;
- cache-unified;
- cache-level = <2>;
- };
- };
-
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>;
- };
-
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
-
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a7791-wdt",
- "renesas,rcar-gen2-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a7791",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a7791",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a7791",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a7791",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a7791",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a7791",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a7791",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
-
- gpio7: gpio@e6055800 {
- compatible = "renesas,gpio-r8a7791",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055800 0 0x50>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 224 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 904>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 904>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a7791";
- reg = <0 0xe6060000 0 0x250>;
- };
-
- tpu: pwm@e60f0000 {
- compatible = "renesas,tpu-r8a7791", "renesas,tpu";
- reg = <0 0xe60f0000 0 0x148>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 304>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 304>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7791-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&usb_extal_clk>;
- clock-names = "extal", "usb_extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- apmu@e6152000 {
- compatible = "renesas,r8a7791-apmu", "renesas,apmu";
- reg = <0 0xe6152000 0 0x188>;
- cpus = <&cpu0>, <&cpu1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7791-rst";
- reg = <0 0xe6160000 0 0x0100>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7791-sysc";
- reg = <0 0xe6180000 0 0x0200>;
- #power-domain-cells = <1>;
- };
-
- irqc0: interrupt-controller@e61c0000 {
- compatible = "renesas,irqc-r8a7791", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- thermal: thermal@e61f0000 {
- compatible = "renesas,thermal-r8a7791",
- "renesas,rcar-gen2-thermal",
- "renesas,rcar-thermal";
- reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <0>;
- };
-
- ipmmu_sy0: iommu@e6280000 {
- compatible = "renesas,ipmmu-r8a7791",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe6280000 0 0x1000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_sy1: iommu@e6290000 {
- compatible = "renesas,ipmmu-r8a7791",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe6290000 0 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_ds: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a7791",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe6740000 0 0x1000>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_mp: iommu@ec680000 {
- compatible = "renesas,ipmmu-r8a7791",
- "renesas,ipmmu-vmsa";
- reg = <0 0xec680000 0 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_mx: iommu@fe951000 {
- compatible = "renesas,ipmmu-r8a7791",
- "renesas,ipmmu-vmsa";
- reg = <0 0xfe951000 0 0x1000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_rt: iommu@ffc80000 {
- compatible = "renesas,ipmmu-r8a7791",
- "renesas,ipmmu-vmsa";
- reg = <0 0xffc80000 0 0x1000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_gp: iommu@e62a0000 {
- compatible = "renesas,ipmmu-r8a7791",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe62a0000 0 0x1000>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- icram0: sram@e63a0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63a0000 0 0x12000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63a0000 0x12000>;
- };
-
- icram1: sram@e63c0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63c0000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63c0000 0x1000>;
-
- smp-sram@0 {
- compatible = "renesas,smp-sram";
- reg = <0 0x100>;
- };
- };
-
- /* The memory map in the User's Manual maps the cores to
- * bus numbers
- */
- i2c0: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c1: i2c@e6518000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6518000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6530000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6530000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e6540000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6540000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c4: i2c@e6520000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6520000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c5: i2c@e6528000 {
- /* doesn't need pinmux */
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6528000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 925>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 925>;
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c6: i2c@e60b0000 {
- /* doesn't need pinmux */
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7791",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- dmas = <&dmac0 0x77>, <&dmac0 0x78>,
- <&dmac1 0x77>, <&dmac1 0x78>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- status = "disabled";
- };
-
- i2c7: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7791",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6500000 0 0x425>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- dmas = <&dmac0 0x61>, <&dmac0 0x62>,
- <&dmac1 0x61>, <&dmac1 0x62>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- status = "disabled";
- };
-
- i2c8: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7791",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6510000 0 0x425>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 323>;
- dmas = <&dmac0 0x65>, <&dmac0 0x66>,
- <&dmac1 0x65>, <&dmac1 0x66>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 323>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a7791",
- "renesas,rcar-gen2-usbhs";
- reg = <0 0xe6590000 0 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usbphy: usb-phy-controller@e6590100 {
- compatible = "renesas,usb-phy-r8a7791",
- "renesas,rcar-gen2-usb-phy";
- reg = <0 0xe6590100 0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cpg CPG_MOD 704>;
- clock-names = "usbhs";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- status = "disabled";
-
- usb0: usb-phy@0 {
- reg = <0>;
- #phy-cells = <1>;
- };
- usb2: usb-phy@2 {
- reg = <2>;
- #phy-cells = <1>;
- };
- };
-
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a7791-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a7791-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a7791",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
-
- dmac1: dma-controller@e6720000 {
- compatible = "renesas,dmac-r8a7791",
- "renesas,rcar-dmac";
- reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7791",
- "renesas,etheravb-rcar-gen2";
- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7791", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>,
- <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- scifa0: serial@e6c40000 {
- compatible = "renesas,scifa-r8a7791",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>;
- clock-names = "fck";
- dmas = <&dmac0 0x21>, <&dmac0 0x22>,
- <&dmac1 0x21>, <&dmac1 0x22>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scifa1: serial@e6c50000 {
- compatible = "renesas,scifa-r8a7791",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>;
- clock-names = "fck";
- dmas = <&dmac0 0x25>, <&dmac0 0x26>,
- <&dmac1 0x25>, <&dmac1 0x26>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scifa2: serial@e6c60000 {
- compatible = "renesas,scifa-r8a7791",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c60000 0 64>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>;
- clock-names = "fck";
- dmas = <&dmac0 0x27>, <&dmac0 0x28>,
- <&dmac1 0x27>, <&dmac1 0x28>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- scifa3: serial@e6c70000 {
- compatible = "renesas,scifa-r8a7791",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c70000 0 64>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1106>;
- clock-names = "fck";
- dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
- <&dmac1 0x1b>, <&dmac1 0x1c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 1106>;
- status = "disabled";
- };
-
- scifa4: serial@e6c78000 {
- compatible = "renesas,scifa-r8a7791",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c78000 0 64>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1107>;
- clock-names = "fck";
- dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
- <&dmac1 0x1f>, <&dmac1 0x20>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 1107>;
- status = "disabled";
- };
-
- scifa5: serial@e6c80000 {
- compatible = "renesas,scifa-r8a7791",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c80000 0 64>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1108>;
- clock-names = "fck";
- dmas = <&dmac0 0x23>, <&dmac0 0x24>,
- <&dmac1 0x23>, <&dmac1 0x24>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 1108>;
- status = "disabled";
- };
-
- scifb0: serial@e6c20000 {
- compatible = "renesas,scifb-r8a7791",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c20000 0 0x100>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>;
- clock-names = "fck";
- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
- <&dmac1 0x3d>, <&dmac1 0x3e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scifb1: serial@e6c30000 {
- compatible = "renesas,scifb-r8a7791",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c30000 0 0x100>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>;
- clock-names = "fck";
- dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
- <&dmac1 0x19>, <&dmac1 0x1a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scifb2: serial@e6ce0000 {
- compatible = "renesas,scifb-r8a7791",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6ce0000 0 0x100>;
- interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 216>;
- clock-names = "fck";
- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
- <&dmac1 0x1d>, <&dmac1 0x1e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 216>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a7791",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
- <&dmac1 0x29>, <&dmac1 0x2a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 721>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a7791",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
- <&dmac1 0x2d>, <&dmac1 0x2e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 720>;
- status = "disabled";
- };
-
- scif2: serial@e6e58000 {
- compatible = "renesas,scif-r8a7791",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6e58000 0 64>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
- <&dmac1 0x2b>, <&dmac1 0x2c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 719>;
- status = "disabled";
- };
-
- scif3: serial@e6ea8000 {
- compatible = "renesas,scif-r8a7791",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6ea8000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
- <&dmac1 0x2f>, <&dmac1 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 718>;
- status = "disabled";
- };
-
- scif4: serial@e6ee0000 {
- compatible = "renesas,scif-r8a7791",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6ee0000 0 64>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
- <&dmac1 0xfb>, <&dmac1 0xfc>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 715>;
- status = "disabled";
- };
-
- scif5: serial@e6ee8000 {
- compatible = "renesas,scif-r8a7791",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6ee8000 0 64>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
- <&dmac1 0xfd>, <&dmac1 0xfe>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
- };
-
- hscif0: serial@e62c0000 {
- compatible = "renesas,hscif-r8a7791",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c0000 0 96>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
- <&dmac1 0x39>, <&dmac1 0x3a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 717>;
- status = "disabled";
- };
-
- hscif1: serial@e62c8000 {
- compatible = "renesas,hscif-r8a7791",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c8000 0 96>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
- <&dmac1 0x4d>, <&dmac1 0x4e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
- };
-
- hscif2: serial@e62d0000 {
- compatible = "renesas,hscif-r8a7791",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62d0000 0 96>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
- <&dmac1 0x3b>, <&dmac1 0x3c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 713>;
- status = "disabled";
- };
-
- msiof0: spi@e6e20000 {
- compatible = "renesas,msiof-r8a7791",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e20000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 000>;
- dmas = <&dmac0 0x51>, <&dmac0 0x52>,
- <&dmac1 0x51>, <&dmac1 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6e10000 {
- compatible = "renesas,msiof-r8a7791",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e10000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x55>, <&dmac0 0x56>,
- <&dmac1 0x55>, <&dmac1 0x56>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6e00000 {
- compatible = "renesas,msiof-r8a7791",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 205>;
- dmas = <&dmac0 0x41>, <&dmac0 0x42>,
- <&dmac1 0x41>, <&dmac1 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 205>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm5: pwm@e6e35000 {
- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
- reg = <0 0xe6e35000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm6: pwm@e6e36000 {
- compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
- reg = <0 0xe6e36000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- adc: adc@e6e54000 {
- compatible = "renesas,r8a7791-gyroadc",
- "renesas,rcar-gyroadc";
- reg = <0 0xe6e54000 0 64>;
- clocks = <&cpg CPG_MOD 901>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 901>;
- status = "disabled";
- };
-
- can0: can@e6e80000 {
- compatible = "renesas,can-r8a7791",
- "renesas,rcar-gen2-can";
- reg = <0 0xe6e80000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6e88000 {
- compatible = "renesas,can-r8a7791",
- "renesas,rcar-gen2-can";
- reg = <0 0xe6e88000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7791",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- status = "disabled";
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7791",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- status = "disabled";
- };
-
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a7791",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- status = "disabled";
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a7791",
- "renesas,rcar_sound-gen2";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
- <&cpg CPG_CORE R8A7791_CLK_M2>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0", "src.9", "src.8",
- "src.7", "src.6", "src.5", "src.4",
- "src.3", "src.2", "src.1", "src.0",
- "ctu.0", "ctu.1",
- "mix.0", "mix.1",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>,
- <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>,
- <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0";
-
- status = "disabled";
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma1 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma1 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>,
- <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>,
- <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>,
- <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>,
- <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>,
- <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>,
- <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>,
- <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>,
- <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>,
- <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>,
- <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- };
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a7791",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
-
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a7791",
- "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
-
- xhci: usb@ee000000 {
- compatible = "renesas,xhci-r8a7791",
- "renesas,rcar-gen2-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- phys = <&usb2 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- pci0: pci@ee090000 {
- compatible = "renesas,pci-r8a7791",
- "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee090000 0 0xc00>,
- <0 0xee080000 0 0x1100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xf800 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x800 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
- };
-
- usb@2,0 {
- reg = <0x1000 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
- };
- };
-
- pci1: pci@ee0d0000 {
- compatible = "renesas,pci-r8a7791",
- "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee0d0000 0 0xc00>,
- <0 0xee0c0000 0 0x1100>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <1 1>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xf800 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x10800 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
- };
-
- usb@2,0 {
- reg = <0x11000 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
- };
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a7791",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
-
- sdhi1: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a7791",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee140000 0 0x100>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>;
- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
- <&dmac1 0xc1>, <&dmac1 0xc2>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- status = "disabled";
- };
-
- sdhi2: mmc@ee160000 {
- compatible = "renesas,sdhi-r8a7791",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee160000 0 0x100>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>;
- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
- <&dmac1 0xd3>, <&dmac1 0xd4>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
-
- mmcif0: mmc@ee200000 {
- compatible = "renesas,mmcif-r8a7791",
- "renesas,sh-mmcif";
- reg = <0 0xee200000 0 0x80>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 315>;
- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
- <&dmac1 0xd1>, <&dmac1 0xd2>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 315>;
- reg-io-width = <4>;
- status = "disabled";
- max-frequency = <97500000>;
- };
-
- sata0: sata@ee300000 {
- compatible = "renesas,sata-r8a7791",
- "renesas,rcar-gen2-sata";
- reg = <0 0xee300000 0 0x200000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 815>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 815>;
- status = "disabled";
- };
-
- sata1: sata@ee500000 {
- compatible = "renesas,sata-r8a7791",
- "renesas,rcar-gen2-sata";
- reg = <0 0xee500000 0 0x200000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 814>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 814>;
- status = "disabled";
- };
-
- ether: ethernet@ee700000 {
- compatible = "renesas,ether-r8a7791",
- "renesas,rcar-gen2-ether";
- reg = <0 0xee700000 0 0x400>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- phy-mode = "rmii";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1001000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
- <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- pciec: pcie@fe000000 {
- compatible = "renesas,pcie-r8a7791",
- "renesas,pcie-rcar-gen2";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
- <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- status = "disabled";
- };
-
- vsp@fe928000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe928000 0 0x8000>;
- interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 131>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 131>;
- };
-
- vsp@fe930000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe930000 0 0x8000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 128>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 128>;
- };
-
- vsp@fe938000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe938000 0 0x8000>;
- interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 127>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 127>;
- };
-
- fdp1@fe940000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe940000 0 0x2400>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 119>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 119>;
- };
-
- fdp1@fe944000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe944000 0 0x2400>;
- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 118>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 118>;
- };
-
- jpu: jpeg-codec@fe980000 {
- compatible = "renesas,jpu-r8a7791",
- "renesas,rcar-gen2-jpu";
- reg = <0 0xfe980000 0 0x10300>;
- interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 106>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 106>;
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a7791";
- reg = <0 0xfeb00000 0 0x40000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
- clock-names = "du.0", "du.1";
- resets = <&cpg 724>;
- reset-names = "du.0";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- du_out_rgb: endpoint {
- };
- };
- port@1 {
- reg = <1>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
- };
- };
-
- lvds0: lvds@feb90000 {
- compatible = "renesas,r8a7791-lvds";
- reg = <0 0xfeb90000 0 0x1c>;
- clocks = <&cpg CPG_MOD 726>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 726>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
- port@1 {
- reg = <1>;
- lvds0_out: endpoint {
- };
- };
- };
- };
-
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
- };
-
- cmt0: timer@ffca0000 {
- compatible = "renesas,r8a7791-cmt0",
- "renesas,rcar-gen2-cmt0";
- reg = <0 0xffca0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
-
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7791-cmt1",
- "renesas,rcar-gen2-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 329>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 329>;
-
- status = "disabled";
- };
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
- thermal-sensors = <&thermal>;
-
- trips {
- cpu-crit {
- temperature = <95000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
- cooling-maps {
- };
- };
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- /* External USB clock - can be overridden by the board */
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Blanche board
- *
- * Copyright (C) 2014 Renesas Electronics Corporation
- * Copyright (C) 2016 Cogent Embedded, Inc.
- */
-
-/dts-v1/;
-#include "r8a7792.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Blanche";
- compatible = "renesas,blanche", "renesas,r8a7792";
-
- aliases {
- serial0 = &scif0;
- serial1 = &scif3;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0 0x40000000 0 0x40000000>;
- };
-
- d3_3v: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "D3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ethernet@18000000 {
- compatible = "smsc,lan89218", "smsc,lan9115";
- reg = <0 0x18000000 0 0x100>;
- phy-mode = "mii";
- interrupt-parent = <&irqc>;
- interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
- smsc,irq-push-pull;
- reg-io-width = <4>;
- vddvario-supply = <&d3_3v>;
- vdd33a-supply = <&d3_3v>;
-
- pinctrl-0 = <&lan89218_pins>;
- pinctrl-names = "default";
- };
-
- vga-encoder {
- compatible = "adi,adv7123";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7123_in: endpoint {
- remote-endpoint = <&du_out_rgb1>;
- };
- };
- port@1 {
- reg = <1>;
- adv7123_out: endpoint {
- remote-endpoint = <&vga_in>;
- };
- };
- };
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con: endpoint {
- remote-endpoint = <&adv7511_out>;
- };
- };
- };
-
- vga {
- compatible = "vga-connector";
-
- port {
- vga_in: endpoint {
- remote-endpoint = <&adv7123_out>;
- };
- };
- };
-
- x1_clk: x1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <74250000>;
- };
-
- x2_clk: x2 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <65000000>;
- };
-
- keyboard {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&keyboard_pins>;
- pinctrl-names = "default";
-
- key-1 {
- linux,code = <KEY_1>;
- label = "SW2-1";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
- };
- key-2 {
- linux,code = <KEY_2>;
- label = "SW2-2";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
- };
- key-3 {
- linux,code = <KEY_3>;
- label = "SW2-3";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- };
- key-4 {
- linux,code = <KEY_4>;
- label = "SW2-4";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
- };
- key-a {
- linux,code = <KEY_A>;
- label = "SW24";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
- };
- key-b {
- linux,code = <KEY_B>;
- label = "SW25";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio11 2 GPIO_ACTIVE_LOW>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led17 {
- gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>;
- };
- led18 {
- gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>;
- };
- led19 {
- gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>;
- };
- led20 {
- gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>;
- };
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&extal_clk {
- clock-frequency = <20000000>;
-};
-
-&can_clk {
- clock-frequency = <48000000>;
-};
-
-&pfc {
- scif0_pins: scif0 {
- groups = "scif0_data";
- function = "scif0";
- };
-
- scif3_pins: scif3 {
- groups = "scif3_data";
- function = "scif3";
- };
-
- lan89218_pins: lan89218 {
- intc {
- groups = "intc_irq0";
- function = "intc";
- };
- lbsc {
- groups = "lbsc_ex_cs0";
- function = "lbsc";
- };
- };
-
- can0_pins: can0 {
- groups = "can0_data", "can_clk";
- function = "can0";
- };
-
- sdhi0_pins: sdhi0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- };
-
- du0_pins: du0 {
- groups = "du0_rgb888", "du0_sync", "du0_disp";
- function = "du0";
- };
-
- du1_pins: du1 {
- groups = "du1_rgb666", "du1_sync", "du1_disp";
- function = "du1";
- };
-
- keyboard_pins: keyboard {
- pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_2";
- bias-pull-up;
- };
-
- pmic_irq_pins: pmicirq {
- groups = "intc_irq2";
- function = "intc";
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif3 {
- pinctrl-0 = <&scif3_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&can0 {
- pinctrl-0 = <&can0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&vcc_sdhi0>;
- cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
- clock-frequency = <400000>;
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&irqc>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&du_out_rgb0>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con>;
- };
- };
- };
- };
-};
-
-&iic3 {
- status = "okay";
-
- pmic@58 {
- compatible = "dlg,da9063";
- reg = <0x58>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_irq_pins>;
- interrupt-parent = <&irqc>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
-
- rtc {
- compatible = "dlg,da9063-rtc";
- };
-
- watchdog {
- compatible = "dlg,da9063-watchdog";
- };
- };
-};
-
-&du {
- pinctrl-0 = <&du0_pins>, <&du1_pins>;
- pinctrl-names = "default";
-
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;
- clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
- status = "okay";
-
- ports {
- port@0 {
- endpoint {
- remote-endpoint = <&adv7511_in>;
- };
- };
- port@1 {
- endpoint {
- remote-endpoint = <&adv7123_in>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car V2H (R8A77920) SoC
- *
- * Copyright (C) 2016 Cogent Embedded Inc.
- */
-
-#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a7792-sysc.h>
-
-/ {
- compatible = "renesas,r8a7792";
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &iic3;
- spi0 = &qspi;
- spi1 = &msiof0;
- spi2 = &msiof1;
- vin0 = &vin0;
- vin1 = &vin1;
- vin2 = &vin2;
- vin3 = &vin3;
- vin4 = &vin4;
- vin5 = &vin5;
- };
-
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0>;
- clock-frequency = <1000000000>;
- clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
- power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA15>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <1>;
- clock-frequency = <1000000000>;
- clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
- power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA15>;
- };
-
- L2_CA15: cache-controller-0 {
- compatible = "cache";
- cache-unified;
- cache-level = <2>;
- power-domains = <&sysc R8A7792_PD_CA15_SCU>;
- };
- };
-
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>;
- };
-
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
-
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a7792-wdt",
- "renesas,rcar-gen2-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a7792",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 29>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a7792",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 23>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a7792",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a7792",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 28>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a7792",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 17>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a7792",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 17>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055100 {
- compatible = "renesas,gpio-r8a7792",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055100 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 17>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
-
- gpio7: gpio@e6055200 {
- compatible = "renesas,gpio-r8a7792",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055200 0 0x50>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 224 17>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 904>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 904>;
- };
-
- gpio8: gpio@e6055300 {
- compatible = "renesas,gpio-r8a7792",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055300 0 0x50>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 256 17>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 921>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 921>;
- };
-
- gpio9: gpio@e6055400 {
- compatible = "renesas,gpio-r8a7792",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 288 17>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- };
-
- gpio10: gpio@e6055500 {
- compatible = "renesas,gpio-r8a7792",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055500 0 0x50>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 320 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 914>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 914>;
- };
-
- gpio11: gpio@e6055600 {
- compatible = "renesas,gpio-r8a7792",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055600 0 0x50>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 352 30>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 913>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 913>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a7792";
- reg = <0 0xe6060000 0 0x144>;
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7792-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>;
- clock-names = "extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- apmu@e6152000 {
- compatible = "renesas,r8a7792-apmu", "renesas,apmu";
- reg = <0 0xe6152000 0 0x188>;
- cpus = <&cpu0>, <&cpu1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7792-rst";
- reg = <0 0xe6160000 0 0x0100>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7792-sysc";
- reg = <0 0xe6180000 0 0x0200>;
- #power-domain-cells = <1>;
- };
-
- irqc: interrupt-controller@e61c0000 {
- compatible = "renesas,irqc-r8a7792", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- icram0: sram@e63a0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63a0000 0 0x12000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63a0000 0x12000>;
- };
-
- icram1: sram@e63c0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63c0000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63c0000 0x1000>;
-
- smp-sram@0 {
- compatible = "renesas,smp-sram";
- reg = <0 0x100>;
- };
- };
-
- /* I2C doesn't need pinmux */
- i2c0: i2c@e6508000 {
- compatible = "renesas,i2c-r8a7792",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@e6518000 {
- compatible = "renesas,i2c-r8a7792",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6518000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@e6530000 {
- compatible = "renesas,i2c-r8a7792",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6530000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@e6540000 {
- compatible = "renesas,i2c-r8a7792",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6540000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@e6520000 {
- compatible = "renesas,i2c-r8a7792",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6520000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c5: i2c@e6528000 {
- compatible = "renesas,i2c-r8a7792",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6528000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 925>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 925>;
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- iic3: i2c@e60b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7792",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- dmas = <&dmac0 0x77>, <&dmac0 0x78>,
- <&dmac1 0x77>, <&dmac1 0x78>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- status = "disabled";
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a7792",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
-
- dmac1: dma-controller@e6720000 {
- compatible = "renesas,dmac-r8a7792",
- "renesas,rcar-dmac";
- reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7792",
- "renesas,etheravb-rcar-gen2";
- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7792", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>,
- <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a7792",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 721>,
- <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
- <&dmac1 0x29>, <&dmac1 0x2a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 721>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a7792",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 720>,
- <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
- <&dmac1 0x2d>, <&dmac1 0x2e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 720>;
- status = "disabled";
- };
-
- scif2: serial@e6e58000 {
- compatible = "renesas,scif-r8a7792",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6e58000 0 64>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 719>,
- <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
- <&dmac1 0x2b>, <&dmac1 0x2c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 719>;
- status = "disabled";
- };
-
- scif3: serial@e6ea8000 {
- compatible = "renesas,scif-r8a7792",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6ea8000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 718>,
- <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
- <&dmac1 0x2f>, <&dmac1 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 718>;
- status = "disabled";
- };
-
- hscif0: serial@e62c0000 {
- compatible = "renesas,hscif-r8a7792",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c0000 0 96>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 717>,
- <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
- <&dmac1 0x39>, <&dmac1 0x3a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 717>;
- status = "disabled";
- };
-
- hscif1: serial@e62c8000 {
- compatible = "renesas,hscif-r8a7792",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c8000 0 96>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>,
- <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
- <&dmac1 0x4d>, <&dmac1 0x4e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
- };
-
- msiof0: spi@e6e20000 {
- compatible = "renesas,msiof-r8a7792",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e20000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 000>;
- dmas = <&dmac0 0x51>, <&dmac0 0x52>,
- <&dmac1 0x51>, <&dmac1 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6e10000 {
- compatible = "renesas,msiof-r8a7792",
- "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e10000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x55>, <&dmac0 0x56>,
- <&dmac1 0x55>, <&dmac1 0x56>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can0: can@e6e80000 {
- compatible = "renesas,can-r8a7792",
- "renesas,rcar-gen2-can";
- reg = <0 0xe6e80000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6e88000 {
- compatible = "renesas,can-r8a7792",
- "renesas,rcar-gen2-can";
- reg = <0 0xe6e88000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7792",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- status = "disabled";
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7792",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- status = "disabled";
- };
-
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a7792",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- status = "disabled";
- };
-
- vin3: video@e6ef3000 {
- compatible = "renesas,vin-r8a7792",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- status = "disabled";
- };
-
- vin4: video@e6ef4000 {
- compatible = "renesas,vin-r8a7792",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 805>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 805>;
- status = "disabled";
- };
-
- vin5: video@e6ef5000 {
- compatible = "renesas,vin-r8a7792",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef5000 0 0x1000>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 804>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 804>;
- status = "disabled";
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a7792",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- clocks = <&cpg CPG_MOD 314>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1001000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x2000>,
- <0 0xf1004000 0 0x2000>,
- <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- vsp@fe928000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe928000 0 0x8000>;
- interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 131>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 131>;
- };
-
- vsp@fe930000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe930000 0 0x8000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 128>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 128>;
- };
-
- vsp@fe938000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe938000 0 0x8000>;
- interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 127>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 127>;
- };
-
- jpu: jpeg-codec@fe980000 {
- compatible = "renesas,jpu-r8a7792",
- "renesas,rcar-gen2-jpu";
- reg = <0 0xfe980000 0 0x10300>;
- interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 106>;
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 106>;
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a7792";
- reg = <0 0xfeb00000 0 0x40000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
- clock-names = "du.0", "du.1";
- resets = <&cpg 724>;
- reset-names = "du.0";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- du_out_rgb0: endpoint {
- };
- };
- port@1 {
- reg = <1>;
- du_out_rgb1: endpoint {
- };
- };
- };
- };
-
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
- };
-
- cmt0: timer@ffca0000 {
- compatible = "renesas,r8a7792-cmt0",
- "renesas,rcar-gen2-cmt0";
- reg = <0 0xffca0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
-
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7792-cmt1",
- "renesas,rcar-gen2-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 329>;
- clock-names = "fck";
- power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
- resets = <&cpg 329>;
-
- status = "disabled";
- };
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Gose board
- *
- * Copyright (C) 2014-2015 Renesas Electronics Corporation
- */
-
-/*
- * SSI-AK4643
- *
- * SW1: 1: AK4643
- * 2: CN22
- * 3: ADV7511
- *
- * This command is required when Playback/Capture
- *
- * amixer set "LINEOUT Mixer DACL" on
- * amixer set "DVC Out" 100%
- * amixer set "DVC In" 100%
- *
- * You can use Mute
- *
- * amixer set "DVC Out Mute" on
- * amixer set "DVC In Mute" on
- *
- * You can use Volume Ramp
- *
- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
- * amixer set "DVC Out Ramp" on
- * aplay xxx.wav &
- * amixer set "DVC Out" 80% // Volume Down
- * amixer set "DVC Out" 100% // Volume Up
- */
-
-/dts-v1/;
-#include "r8a7793.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Gose";
- compatible = "renesas,gose", "renesas,r8a7793";
-
- aliases {
- serial0 = &scif0;
- serial1 = &scif1;
- i2c9 = &gpioi2c2;
- i2c10 = &gpioi2c4;
- i2c11 = &i2chdmi;
- i2c12 = &i2cexio4;
- mmc0 = &sdhi0;
- mmc1 = &sdhi1;
- mmc2 = &sdhi2;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0 0x40000000 0 0x40000000>;
- };
-
- keyboard {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&keyboard_pins>;
- pinctrl-names = "default";
-
- key-1 {
- gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_1>;
- label = "SW2-1";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-2 {
- gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_2>;
- label = "SW2-2";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-3 {
- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_3>;
- label = "SW2-3";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-4 {
- gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_4>;
- label = "SW2-4";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-a {
- gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_A>;
- label = "SW30";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-b {
- gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_B>;
- label = "SW31";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-c {
- gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_C>;
- label = "SW32";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-d {
- gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_D>;
- label = "SW33";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-e {
- gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_E>;
- label = "SW34";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-f {
- gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_F>;
- label = "SW35";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-g {
- gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_G>;
- label = "SW36";
- wakeup-source;
- debounce-interval = <20>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led6 {
- gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- label = "LED6";
- };
- led7 {
- gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
- label = "LED7";
- };
- led8 {
- gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
- label = "LED8";
- };
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vcc_sdhi1: regulator-vcc-sdhi1 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI1 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi1: regulator-vccq-sdhi1 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI1 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vcc_sdhi2: regulator-vcc-sdhi2 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI2 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi2: regulator-vccq-sdhi2 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI2 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- audio_clock: audio_clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <11289600>;
- };
-
- rsnd_ak4643: sound {
- compatible = "simple-audio-card";
-
- simple-audio-card,format = "left_j";
- simple-audio-card,bitclock-master = <&sndcodec>;
- simple-audio-card,frame-master = <&sndcodec>;
-
- sndcpu: simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
-
- sndcodec: simple-audio-card,codec {
- sound-dai = <&ak4643>;
- clocks = <&audio_clock>;
- };
- };
-
- hdmi-in {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&adv7612_in>;
- };
- };
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_out: endpoint {
- remote-endpoint = <&adv7511_out>;
- };
- };
- };
-
- composite-in {
- compatible = "composite-video-connector";
-
- port {
- composite_con_in: endpoint {
- remote-endpoint = <&adv7180_in>;
- };
- };
- };
-
- x2_clk: x2-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <74250000>;
- };
-
- x13_clk: x13-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <148500000>;
- };
-
- gpioi2c2: i2c-9 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "i2c-gpio";
- status = "disabled";
- scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <5>;
- };
-
- gpioi2c4: i2c-10 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "i2c-gpio";
- status = "disabled";
- scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <5>;
- };
-
- /*
- * A fallback to GPIO is provided for I2C2.
- */
- i2chdmi: i2c-11 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&i2c2>, <&gpioi2c2>;
- i2c-bus-name = "i2c-hdmi";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ak4643: codec@12 {
- compatible = "asahi-kasei,ak4643";
- #sound-dai-cells = <0>;
- reg = <0x12>;
- };
-
- composite-in@20 {
- compatible = "adi,adv7180cp";
- reg = <0x20>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7180_in: endpoint {
- remote-endpoint = <&composite_con_in>;
- };
- };
-
- port@3 {
- reg = <3>;
- adv7180_out: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin1ep>;
- };
- };
- };
- };
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio3>;
- interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
- };
- };
-
- hdmi-in@4c {
- compatible = "adi,adv7612";
- reg = <0x4c>;
- interrupt-parent = <&gpio4>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- default-input = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7612_in: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
- };
-
- port@2 {
- reg = <2>;
- adv7612_out: endpoint {
- remote-endpoint = <&vin0ep2>;
- };
- };
- };
- };
-
- eeprom@50 {
- compatible = "renesas,r1ex24002", "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
- };
-
- /*
- * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
- * A fallback to GPIO is provided.
- */
- i2cexio4: i2c-12 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&i2c4>, <&gpioi2c4>;
- i2c-bus-name = "i2c-exio4";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
- <&x13_clk>, <&x2_clk>;
- clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
-
- ports {
- port@0 {
- endpoint {
- remote-endpoint = <&adv7511_in>;
- };
- };
- };
-};
-
-&lvds0 {
- ports {
- port@1 {
- lvds_connector: endpoint {
- };
- };
- };
-};
-
-&extal_clk {
- clock-frequency = <20000000>;
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- i2c2_pins: i2c2 {
- groups = "i2c2";
- function = "i2c2";
- };
-
- i2c4_pins: i2c4 {
- groups = "i2c4_c";
- function = "i2c4";
- };
-
- du_pins: du {
- groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
- function = "du";
- };
-
- scif0_pins: scif0 {
- groups = "scif0_data_d";
- function = "scif0";
- };
-
- scif1_pins: scif1 {
- groups = "scif1_data_d";
- function = "scif1";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk";
- function = "scif_clk";
- };
-
- ether_pins: ether {
- groups = "eth_link", "eth_mdio", "eth_rmii";
- function = "eth";
- };
-
- phy1_pins: phy1 {
- groups = "intc_irq0";
- function = "intc";
- };
-
- pmic_irq_pins: pmicirq {
- groups = "intc_irq2";
- function = "intc";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi1_pins: sd1 {
- groups = "sdhi1_data4", "sdhi1_ctrl";
- function = "sdhi1";
- power-source = <3300>;
- };
-
- sdhi1_pins_uhs: sd1_uhs {
- groups = "sdhi1_data4", "sdhi1_ctrl";
- function = "sdhi1";
- power-source = <1800>;
- };
-
- sdhi2_pins: sd2 {
- groups = "sdhi2_data4", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <3300>;
- };
-
- sdhi2_pins_uhs: sd2_uhs {
- groups = "sdhi2_data4", "sdhi2_ctrl";
- function = "sdhi2";
- power-source = <1800>;
- };
-
- qspi_pins: qspi {
- groups = "qspi_ctrl", "qspi_data4";
- function = "qspi";
- };
-
- sound_pins: sound {
- groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
- function = "ssi";
- };
-
- sound_clk_pins: sound_clk {
- groups = "audio_clk_a";
- function = "audio_clk";
- };
-
- keyboard_pins: keyboard {
- pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3";
- bias-pull-up;
- };
-
- vin0_pins: vin0 {
- groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
- function = "vin0";
- };
-
- vin1_pins: vin1 {
- groups = "vin1_data8", "vin1_clk";
- function = "vin1";
- };
-};
-
-ðer {
- pinctrl-0 = <ðer_pins>, <&phy1_pins>;
- pinctrl-names = "default";
-
- phy-handle = <&phy1>;
- renesas,ether-link-active-low;
- status = "okay";
-
- phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-id0022.1537",
- "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- interrupt-parent = <&irqc0>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- micrel,led-mode = <1>;
- reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
- };
-};
-
-&cmt0 {
- status = "okay";
-};
-
-&cpu0 {
- cpu0-supply = <&vdd_dvfs>;
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif1 {
- pinctrl-0 = <&scif1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdhi1 {
- pinctrl-0 = <&sdhi1_pins>;
- pinctrl-1 = <&sdhi1_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi1>;
- vqmmc-supply = <&vccq_sdhi1>;
- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
- sd-uhs-sdr50;
- status = "okay";
-};
-
-&sdhi2 {
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-1 = <&sdhi2_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi2>;
- vqmmc-supply = <&vccq_sdhi2>;
- cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
- sd-uhs-sdr50;
- status = "okay";
-};
-
-&qspi {
- pinctrl-0 = <&qspi_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- flash@0 {
- compatible = "spansion,s25fl512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <30000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- spi-cpol;
- spi-cpha;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "loader";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "user";
- reg = <0x00040000 0x00400000>;
- read-only;
- };
- partition@440000 {
- label = "flash";
- reg = <0x00440000 0x03bc0000>;
- };
- };
- };
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "i2c-hdmi";
-
- status = "okay";
- clock-frequency = <100000>;
-
-};
-
-&i2c6 {
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_irq_pins>;
- status = "okay";
- clock-frequency = <100000>;
-
- pmic@58 {
- compatible = "dlg,da9063";
- reg = <0x58>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
-
- rtc {
- compatible = "dlg,da9063-rtc";
- };
-
- watchdog {
- compatible = "dlg,da9063-watchdog";
- };
- };
-
- vdd_dvfs: regulator@68 {
- compatible = "dlg,da9210";
- reg = <0x68>;
- interrupt-parent = <&irqc0>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&i2c4 {
- pinctrl-0 = <&i2c4_pins>;
- pinctrl-names = "i2c-exio4";
-};
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
- pinctrl-names = "default";
-
- /* Single DAI */
- #sound-dai-cells = <0>;
-
- status = "okay";
-
- rcar_sound,dai {
- dai0 {
- playback = <&ssi0>, <&src2>, <&dvc0>;
- capture = <&ssi1>, <&src3>, <&dvc1>;
- };
- };
-};
-
-&ssi1 {
- shared-pin;
-};
-
-/* HDMI video input */
-&vin0 {
- status = "okay";
- pinctrl-0 = <&vin0_pins>;
- pinctrl-names = "default";
-
- port {
- vin0ep2: endpoint {
- remote-endpoint = <&adv7612_out>;
- bus-width = <24>;
- hsync-active = <0>;
- vsync-active = <0>;
- pclk-sample = <1>;
- data-active = <1>;
- };
- };
-};
-
-/* composite video input */
-&vin1 {
- pinctrl-0 = <&vin1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- port {
- vin1ep: endpoint {
- remote-endpoint = <&adv7180_out>;
- bus-width = <8>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car M2-N (R8A77930) SoC
- *
- * Copyright (C) 2014-2015 Renesas Electronics Corporation
- */
-
-#include <dt-bindings/clock/r8a7793-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/power/r8a7793-sysc.h>
-
-/ {
- compatible = "renesas,r8a7793";
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &i2c7;
- i2c8 = &i2c8;
- spi0 = &qspi;
- };
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0>;
- clock-frequency = <1500000000>;
- clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
- power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
- enable-method = "renesas,apmu";
- voltage-tolerance = <1>; /* 1% */
- clock-latency = <300000>; /* 300 us */
-
- /* kHz - uV - OPPs unknown yet */
- operating-points = <1500000 1000000>,
- <1312500 1000000>,
- <1125000 1000000>,
- < 937500 1000000>,
- < 750000 1000000>,
- < 375000 1000000>;
- next-level-cache = <&L2_CA15>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <1>;
- clock-frequency = <1500000000>;
- clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
- power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
- enable-method = "renesas,apmu";
- voltage-tolerance = <1>; /* 1% */
- clock-latency = <300000>; /* 300 us */
-
- /* kHz - uV - OPPs unknown yet */
- operating-points = <1500000 1000000>,
- <1312500 1000000>,
- <1125000 1000000>,
- < 937500 1000000>,
- < 750000 1000000>,
- < 375000 1000000>;
- next-level-cache = <&L2_CA15>;
- };
-
- L2_CA15: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A7793_PD_CA15_SCU>;
- cache-unified;
- cache-level = <2>;
- };
- };
-
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>;
- };
-
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
-
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a7793-wdt",
- "renesas,rcar-gen2-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a7793",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a7793",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a7793",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a7793",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a7793",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a7793",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a7793",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
-
- gpio7: gpio@e6055800 {
- compatible = "renesas,gpio-r8a7793",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055800 0 0x50>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 224 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 904>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 904>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a7793";
- reg = <0 0xe6060000 0 0x250>;
- };
-
- /* Special CPG clocks */
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7793-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&usb_extal_clk>;
- clock-names = "extal", "usb_extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- apmu@e6152000 {
- compatible = "renesas,r8a7793-apmu", "renesas,apmu";
- reg = <0 0xe6152000 0 0x188>;
- cpus = <&cpu0>, <&cpu1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7793-rst";
- reg = <0 0xe6160000 0 0x0100>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7793-sysc";
- reg = <0 0xe6180000 0 0x0200>;
- #power-domain-cells = <1>;
- };
-
- irqc0: interrupt-controller@e61c0000 {
- compatible = "renesas,irqc-r8a7793", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- thermal: thermal@e61f0000 {
- compatible = "renesas,thermal-r8a7793",
- "renesas,rcar-gen2-thermal",
- "renesas,rcar-thermal";
- reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <0>;
- };
-
- ipmmu_sy0: iommu@e6280000 {
- compatible = "renesas,ipmmu-r8a7793",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe6280000 0 0x1000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_sy1: iommu@e6290000 {
- compatible = "renesas,ipmmu-r8a7793",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe6290000 0 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_ds: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a7793",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe6740000 0 0x1000>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_mp: iommu@ec680000 {
- compatible = "renesas,ipmmu-r8a7793",
- "renesas,ipmmu-vmsa";
- reg = <0 0xec680000 0 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_mx: iommu@fe951000 {
- compatible = "renesas,ipmmu-r8a7793",
- "renesas,ipmmu-vmsa";
- reg = <0 0xfe951000 0 0x1000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_rt: iommu@ffc80000 {
- compatible = "renesas,ipmmu-r8a7793",
- "renesas,ipmmu-vmsa";
- reg = <0 0xffc80000 0 0x1000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_gp: iommu@e62a0000 {
- compatible = "renesas,ipmmu-r8a7793",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe62a0000 0 0x1000>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- icram0: sram@e63a0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63a0000 0 0x12000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63a0000 0x12000>;
- };
-
- icram1: sram@e63c0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63c0000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63c0000 0x1000>;
-
- smp-sram@0 {
- compatible = "renesas,smp-sram";
- reg = <0 0x100>;
- };
- };
-
- /* The memory map in the User's Manual maps the cores to
- * bus numbers
- */
- i2c0: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7793",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c1: i2c@e6518000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7793",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6518000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6530000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7793",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6530000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e6540000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7793",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6540000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c4: i2c@e6520000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7793",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6520000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c5: i2c@e6528000 {
- /* doesn't need pinmux */
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7793",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6528000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 925>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 925>;
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c6: i2c@e60b0000 {
- /* doesn't need pinmux */
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7793",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- dmas = <&dmac0 0x77>, <&dmac0 0x78>,
- <&dmac1 0x77>, <&dmac1 0x78>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- status = "disabled";
- };
-
- i2c7: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7793",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6500000 0 0x425>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- dmas = <&dmac0 0x61>, <&dmac0 0x62>,
- <&dmac1 0x61>, <&dmac1 0x62>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- status = "disabled";
- };
-
- i2c8: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7793",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6510000 0 0x425>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 323>;
- dmas = <&dmac0 0x65>, <&dmac0 0x66>,
- <&dmac1 0x65>, <&dmac1 0x66>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 323>;
- status = "disabled";
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a7793",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
-
- dmac1: dma-controller@e6720000 {
- compatible = "renesas,dmac-r8a7793",
- "renesas,rcar-dmac";
- reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
-
- qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7793", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>,
- <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- scifa0: serial@e6c40000 {
- compatible = "renesas,scifa-r8a7793",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>;
- clock-names = "fck";
- dmas = <&dmac0 0x21>, <&dmac0 0x22>,
- <&dmac1 0x21>, <&dmac1 0x22>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scifa1: serial@e6c50000 {
- compatible = "renesas,scifa-r8a7793",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>;
- clock-names = "fck";
- dmas = <&dmac0 0x25>, <&dmac0 0x26>,
- <&dmac1 0x25>, <&dmac1 0x26>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scifa2: serial@e6c60000 {
- compatible = "renesas,scifa-r8a7793",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c60000 0 64>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>;
- clock-names = "fck";
- dmas = <&dmac0 0x27>, <&dmac0 0x28>,
- <&dmac1 0x27>, <&dmac1 0x28>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- scifa3: serial@e6c70000 {
- compatible = "renesas,scifa-r8a7793",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c70000 0 64>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1106>;
- clock-names = "fck";
- dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
- <&dmac1 0x1b>, <&dmac1 0x1c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 1106>;
- status = "disabled";
- };
-
- scifa4: serial@e6c78000 {
- compatible = "renesas,scifa-r8a7793",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c78000 0 64>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1107>;
- clock-names = "fck";
- dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
- <&dmac1 0x1f>, <&dmac1 0x20>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 1107>;
- status = "disabled";
- };
-
- scifa5: serial@e6c80000 {
- compatible = "renesas,scifa-r8a7793",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c80000 0 64>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1108>;
- clock-names = "fck";
- dmas = <&dmac0 0x23>, <&dmac0 0x24>,
- <&dmac1 0x23>, <&dmac1 0x24>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 1108>;
- status = "disabled";
- };
-
- scifb0: serial@e6c20000 {
- compatible = "renesas,scifb-r8a7793",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c20000 0 0x100>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>;
- clock-names = "fck";
- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
- <&dmac1 0x3d>, <&dmac1 0x3e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scifb1: serial@e6c30000 {
- compatible = "renesas,scifb-r8a7793",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c30000 0 0x100>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>;
- clock-names = "fck";
- dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
- <&dmac1 0x19>, <&dmac1 0x1a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scifb2: serial@e6ce0000 {
- compatible = "renesas,scifb-r8a7793",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6ce0000 0 0x100>;
- interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 216>;
- clock-names = "fck";
- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
- <&dmac1 0x1d>, <&dmac1 0x1e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 216>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a7793",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
- <&dmac1 0x29>, <&dmac1 0x2a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 721>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a7793",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
- <&dmac1 0x2d>, <&dmac1 0x2e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 720>;
- status = "disabled";
- };
-
- scif2: serial@e6e58000 {
- compatible = "renesas,scif-r8a7793",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6e58000 0 64>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
- <&dmac1 0x2b>, <&dmac1 0x2c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 719>;
- status = "disabled";
- };
-
- scif3: serial@e6ea8000 {
- compatible = "renesas,scif-r8a7793",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6ea8000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
- <&dmac1 0x2f>, <&dmac1 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 718>;
- status = "disabled";
- };
-
- scif4: serial@e6ee0000 {
- compatible = "renesas,scif-r8a7793",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6ee0000 0 64>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
- <&dmac1 0xfb>, <&dmac1 0xfc>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 715>;
- status = "disabled";
- };
-
- scif5: serial@e6ee8000 {
- compatible = "renesas,scif-r8a7793",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6ee8000 0 64>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
- <&dmac1 0xfd>, <&dmac1 0xfe>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
- };
-
- hscif0: serial@e62c0000 {
- compatible = "renesas,hscif-r8a7793",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c0000 0 96>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
- <&dmac1 0x39>, <&dmac1 0x3a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 717>;
- status = "disabled";
- };
-
- hscif1: serial@e62c8000 {
- compatible = "renesas,hscif-r8a7793",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c8000 0 96>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
- <&dmac1 0x4d>, <&dmac1 0x4e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
- };
-
- hscif2: serial@e62d0000 {
- compatible = "renesas,hscif-r8a7793",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62d0000 0 96>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
- <&dmac1 0x3b>, <&dmac1 0x3c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 713>;
- status = "disabled";
- };
-
- can0: can@e6e80000 {
- compatible = "renesas,can-r8a7793",
- "renesas,rcar-gen2-can";
- reg = <0 0xe6e80000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6e88000 {
- compatible = "renesas,can-r8a7793",
- "renesas,rcar-gen2-can";
- reg = <0 0xe6e88000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7793",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- status = "disabled";
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7793",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- status = "disabled";
- };
-
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a7793",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- status = "disabled";
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a7793",
- "renesas,rcar_sound-gen2";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
- <&cpg CPG_CORE R8A7793_CLK_M2>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6",
- "src.5", "src.4", "src.3", "src.2",
- "src.1", "src.0",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>,
- <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>,
- <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0";
-
- status = "disabled";
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma1 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma1 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>,
- <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>,
- <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>,
- <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>,
- <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>,
- <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>,
- <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>,
- <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>,
- <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>,
- <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>,
- <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- };
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a7793",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
-
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a7793",
- "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a7793",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
-
- sdhi1: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a7793",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee140000 0 0x100>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>;
- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
- <&dmac1 0xc1>, <&dmac1 0xc2>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- status = "disabled";
- };
-
- sdhi2: mmc@ee160000 {
- compatible = "renesas,sdhi-r8a7793",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee160000 0 0x100>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>;
- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
- <&dmac1 0xd3>, <&dmac1 0xd4>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
-
- mmcif0: mmc@ee200000 {
- compatible = "renesas,mmcif-r8a7793",
- "renesas,sh-mmcif";
- reg = <0 0xee200000 0 0x80>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 315>;
- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
- <&dmac1 0xd1>, <&dmac1 0xd2>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 315>;
- reg-io-width = <4>;
- status = "disabled";
- max-frequency = <97500000>;
- };
-
- ether: ethernet@ee700000 {
- compatible = "renesas,ether-r8a7793",
- "renesas,rcar-gen2-ether";
- reg = <0 0xee700000 0 0x400>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- phy-mode = "rmii";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1001000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x2000>,
- <0 0xf1004000 0 0x2000>,
- <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- fdp1@fe940000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe940000 0 0x2400>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 119>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 119>;
- };
-
- fdp1@fe944000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe944000 0 0x2400>;
- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 118>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 118>;
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a7793";
- reg = <0 0xfeb00000 0 0x40000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
- clock-names = "du.0", "du.1";
- resets = <&cpg 724>;
- reset-names = "du.0";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- du_out_rgb: endpoint {
- };
- };
- port@1 {
- reg = <1>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
- };
- };
-
- lvds0: lvds@feb90000 {
- compatible = "renesas,r8a7793-lvds";
- reg = <0 0xfeb90000 0 0x1c>;
- clocks = <&cpg CPG_MOD 726>;
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 726>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
- port@1 {
- reg = <1>;
- lvds0_out: endpoint {
- };
- };
- };
- };
-
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
- };
-
- cmt0: timer@ffca0000 {
- compatible = "renesas,r8a7793-cmt0",
- "renesas,rcar-gen2-cmt0";
- reg = <0 0xffca0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
-
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7793-cmt1",
- "renesas,rcar-gen2-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 329>;
- clock-names = "fck";
- power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
- resets = <&cpg 329>;
-
- status = "disabled";
- };
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
- thermal-sensors = <&thermal>;
-
- trips {
- cpu-crit {
- temperature = <95000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
- cooling-maps {
- };
- };
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- /* External USB clock - can be overridden by the board */
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Alt board
- *
- * Copyright (C) 2014 Renesas Electronics Corporation
- */
-
-/dts-v1/;
-#include "r8a7794.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Alt";
- compatible = "renesas,alt", "renesas,r8a7794";
-
- aliases {
- serial0 = &scif2;
- i2c9 = &gpioi2c1;
- i2c10 = &gpioi2c4;
- i2c11 = &i2chdmi;
- i2c12 = &i2cexio4;
- mmc0 = &mmcif0;
- mmc1 = &sdhi0;
- mmc2 = &sdhi1;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0 0x40000000 0 0x40000000>;
- };
-
- d3_3v: regulator-d3-3v {
- compatible = "regulator-fixed";
- regulator-name = "D3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vcc_sdhi1: regulator-vcc-sdhi1 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI1 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi1: regulator-vccq-sdhi1 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI1 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- lbsc {
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- keyboard {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&keyboard_pins>;
- pinctrl-names = "default";
-
- one {
- linux,code = <KEY_1>;
- label = "SW2-1";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
- };
- two {
- linux,code = <KEY_2>;
- label = "SW2-2";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
- };
- three {
- linux,code = <KEY_3>;
- label = "SW2-3";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
- };
- four {
- linux,code = <KEY_4>;
- label = "SW2-4";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- };
- };
-
- vga-encoder {
- compatible = "adi,adv7123";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7123_in: endpoint {
- remote-endpoint = <&du_out_rgb1>;
- };
- };
- port@1 {
- reg = <1>;
- adv7123_out: endpoint {
- remote-endpoint = <&vga_in>;
- };
- };
- };
- };
-
- vga {
- compatible = "vga-connector";
-
- port {
- vga_in: endpoint {
- remote-endpoint = <&adv7123_out>;
- };
- };
- };
-
- x2_clk: x2-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <74250000>;
- };
-
- x13_clk: x13-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <148500000>;
- };
-
- gpioi2c1: i2c-9 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "i2c-gpio";
- status = "disabled";
- scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- };
-
- gpioi2c4: i2c-10 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "i2c-gpio";
- status = "disabled";
- scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <5>;
- };
-
- /*
- * A fallback to GPIO is provided for I2C1.
- */
- i2chdmi: i2c-11 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&i2c1>, <&gpioi2c1>;
- i2c-bus-name = "i2c-hdmi";
- #address-cells = <1>;
- #size-cells = <0>;
-
- composite-in@20 {
- compatible = "adi,adv7180";
- reg = <0x20>;
-
- port {
- adv7180: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin0ep>;
- };
- };
- };
-
- eeprom@50 {
- compatible = "renesas,r1ex24002", "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
- };
-
- /*
- * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
- * A fallback to GPIO is provided.
- */
- i2cexio4: i2c-14 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&i2c4>, <&gpioi2c4>;
- i2c-bus-name = "i2c-exio4";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-};
-
-&pci0 {
- status = "okay";
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-};
-
-&pci1 {
- status = "okay";
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-};
-
-&usbphy {
- status = "okay";
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
- <&x13_clk>, <&x2_clk>;
- clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
-
- ports {
- port@1 {
- endpoint {
- remote-endpoint = <&adv7123_in>;
- };
- };
- };
-};
-
-&extal_clk {
- clock-frequency = <20000000>;
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- du_pins: du {
- groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
- function = "du1";
- };
-
- scif2_pins: scif2 {
- groups = "scif2_data";
- function = "scif2";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk";
- function = "scif_clk";
- };
-
- ether_pins: ether {
- groups = "eth_link", "eth_mdio", "eth_rmii";
- function = "eth";
- };
-
- phy1_pins: phy1 {
- groups = "intc_irq8";
- function = "intc";
- };
-
- i2c1_pins: i2c1 {
- groups = "i2c1";
- function = "i2c1";
- };
-
- i2c4_pins: i2c4 {
- groups = "i2c4";
- function = "i2c4";
- };
-
- vin0_pins: vin0 {
- groups = "vin0_data8", "vin0_clk";
- function = "vin0";
- };
-
- mmcif0_pins: mmcif0 {
- groups = "mmc_data8", "mmc_ctrl";
- function = "mmc";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi1_pins: sd1 {
- groups = "sdhi1_data4", "sdhi1_ctrl";
- function = "sdhi1";
- power-source = <3300>;
- };
-
- sdhi1_pins_uhs: sd1_uhs {
- groups = "sdhi1_data4", "sdhi1_ctrl";
- function = "sdhi1";
- power-source = <1800>;
- };
-
- usb0_pins: usb0 {
- groups = "usb0";
- function = "usb0";
- };
-
- usb1_pins: usb1 {
- groups = "usb1";
- function = "usb1";
- };
-
- keyboard_pins: keyboard {
- pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12";
- bias-pull-up;
- };
-};
-
-&cmt0 {
- status = "okay";
-};
-
-&pfc {
- qspi_pins: qspi {
- groups = "qspi_ctrl", "qspi_data4";
- function = "qspi";
- };
-};
-
-ðer {
- pinctrl-0 = <ðer_pins>, <&phy1_pins>;
- pinctrl-names = "default";
-
- phy-handle = <&phy1>;
- renesas,ether-link-active-low;
- status = "okay";
-
- phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-id0022.1537",
- "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- interrupt-parent = <&irqc0>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- micrel,led-mode = <1>;
- reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
- };
-};
-
-&mmcif0 {
- pinctrl-0 = <&mmcif0_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&d3_3v>;
- vqmmc-supply = <&d3_3v>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdhi1 {
- pinctrl-0 = <&sdhi1_pins>;
- pinctrl-1 = <&sdhi1_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi1>;
- vqmmc-supply = <&vccq_sdhi1>;
- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
- sd-uhs-sdr50;
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "i2c-hdmi";
-
- clock-frequency = <400000>;
-};
-
-&i2c4 {
- pinctrl-0 = <&i2c4_pins>;
- pinctrl-names = "i2c-exio4";
-};
-
-&i2c7 {
- status = "okay";
- clock-frequency = <100000>;
-
- pmic@58 {
- compatible = "dlg,da9063";
- reg = <0x58>;
- interrupt-parent = <&gpio3>;
- interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
-
- rtc {
- compatible = "dlg,da9063-rtc";
- };
-
- watchdog {
- compatible = "dlg,da9063-watchdog";
- };
- };
-};
-
-&vin0 {
- status = "okay";
- pinctrl-0 = <&vin0_pins>;
- pinctrl-names = "default";
-
- port {
- vin0ep: endpoint {
- remote-endpoint = <&adv7180>;
- bus-width = <8>;
- };
- };
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&qspi {
- pinctrl-0 = <&qspi_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- flash@0 {
- compatible = "spansion,s25fl512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <30000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- spi-cpol;
- spi-cpha;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "loader";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "system";
- reg = <0x00040000 0x00040000>;
- read-only;
- };
- partition@80000 {
- label = "user";
- reg = <0x00080000 0x03f80000>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the SILK board
- *
- * Copyright (C) 2014 Renesas Electronics Corporation
- * Copyright (C) 2014-2015 Renesas Solutions Corp.
- * Copyright (C) 2014-2015 Cogent Embedded, Inc.
- */
-
-/*
- * SSI-AK4643
- *
- * SW1: 2-1: AK4643
- * 2-3: ADV7511
- *
- * This command is required before playback/capture:
- *
- * amixer set "LINEOUT Mixer DACL" on
- */
-
-/dts-v1/;
-#include "r8a7794.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "SILK";
- compatible = "renesas,silk", "renesas,r8a7794";
-
- aliases {
- serial0 = &scif2;
- i2c9 = &gpioi2c1;
- i2c10 = &i2chdmi;
- mmc0 = &mmcif0;
- mmc1 = &sdhi1;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0 0x40000000 0 0x40000000>;
- };
-
- keyboard {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&keyboard_pins>;
- pinctrl-names = "default";
-
- key-3 {
- gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_3>;
- label = "SW3";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-4 {
- gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_4>;
- label = "SW4";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-6 {
- gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_6>;
- label = "SW6";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-a {
- gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_A>;
- label = "SW12-1";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-b {
- gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_B>;
- label = "SW12-2";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-c {
- gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_C>;
- label = "SW12-3";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-d {
- gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_D>;
- label = "SW12-4";
- wakeup-source;
- debounce-interval = <20>;
- };
- };
-
- d3_3v: regulator-d3-3v {
- compatible = "regulator-fixed";
- regulator-name = "D3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_sdhi1: regulator-vcc-sdhi1 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI1 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi1: regulator-vccq-sdhi1 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI1 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vga-encoder {
- compatible = "adi,adv7123";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7123_in: endpoint {
- remote-endpoint = <&du_out_rgb1>;
- };
- };
- port@1 {
- reg = <1>;
- adv7123_out: endpoint {
- remote-endpoint = <&vga_in>;
- };
- };
- };
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con: endpoint {
- remote-endpoint = <&adv7511_out>;
- };
- };
- };
-
- vga {
- compatible = "vga-connector";
-
- port {
- vga_in: endpoint {
- remote-endpoint = <&adv7123_out>;
- };
- };
- };
-
- x2_clk: x2-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <148500000>;
- };
-
- x3_clk: x3-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <74250000>;
- };
-
- x9_clk: audio_clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12288000>;
- };
-
- sound {
- compatible = "simple-audio-card";
-
- simple-audio-card,format = "left_j";
- simple-audio-card,bitclock-master = <&soundcodec>;
- simple-audio-card,frame-master = <&soundcodec>;
-
- simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
-
- soundcodec: simple-audio-card,codec {
- sound-dai = <&ak4643>;
- clocks = <&x9_clk>;
- };
- };
-
- gpioi2c1: i2c-9 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "i2c-gpio";
- status = "disabled";
- scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <5>;
- };
-
- /*
- * A fallback to GPIO is provided for I2C1.
- */
- i2chdmi: i2c-10 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&i2c1>, <&gpioi2c1>;
- i2c-bus-name = "i2c-hdmi";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ak4643: codec@12 {
- compatible = "asahi-kasei,ak4643";
- #sound-dai-cells = <0>;
- reg = <0x12>;
- };
-
- composite-in@20 {
- compatible = "adi,adv7180";
- reg = <0x20>;
-
- port {
- adv7180: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin0ep>;
- };
- };
- };
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio5>;
- interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&du_out_rgb0>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con>;
- };
- };
- };
- };
-
- eeprom@50 {
- compatible = "renesas,r1ex24002", "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
- };
-};
-
-&extal_clk {
- clock-frequency = <20000000>;
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- scif2_pins: scif2 {
- groups = "scif2_data";
- function = "scif2";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk";
- function = "scif_clk";
- };
-
- ether_pins: ether {
- groups = "eth_link", "eth_mdio", "eth_rmii";
- function = "eth";
- };
-
- phy1_pins: phy1 {
- groups = "intc_irq8";
- function = "intc";
- };
-
- i2c1_pins: i2c1 {
- groups = "i2c1";
- function = "i2c1";
- };
-
- mmcif0_pins: mmcif0 {
- groups = "mmc_data8", "mmc_ctrl";
- function = "mmc";
- };
-
- sdhi1_pins: sd1 {
- groups = "sdhi1_data4", "sdhi1_ctrl";
- function = "sdhi1";
- };
-
- qspi_pins: qspi {
- groups = "qspi_ctrl", "qspi_data4";
- function = "qspi";
- };
-
- vin0_pins: vin0 {
- groups = "vin0_data8", "vin0_clk";
- function = "vin0";
- };
-
- usb0_pins: usb0 {
- groups = "usb0";
- function = "usb0";
- };
-
- usb1_pins: usb1 {
- groups = "usb1";
- function = "usb1";
- };
-
- du0_pins: du0 {
- groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
- function = "du0";
- };
-
- du1_pins: du1 {
- groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
- function = "du1";
- };
-
- keyboard_pins: keyboard {
- pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12";
- bias-pull-up;
- };
-
- ssi_pins: sound {
- groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
- function = "ssi";
- };
-
- audio_clk_pins: audio_clk {
- groups = "audio_clkc";
- function = "audio_clk";
- };
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-ðer {
- pinctrl-0 = <ðer_pins>, <&phy1_pins>;
- pinctrl-names = "default";
-
- phy-handle = <&phy1>;
- renesas,ether-link-active-low;
- status = "okay";
-
- phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-id0022.1537",
- "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- interrupt-parent = <&irqc0>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- micrel,led-mode = <1>;
- reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
- };
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "i2c-hdmi";
-
- clock-frequency = <400000>;
-};
-
-&i2c7 {
- status = "okay";
- clock-frequency = <100000>;
-
- pmic@58 {
- compatible = "dlg,da9063";
- reg = <0x58>;
- interrupt-parent = <&gpio3>;
- interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
-
- onkey {
- compatible = "dlg,da9063-onkey";
- };
-
- rtc {
- compatible = "dlg,da9063-rtc";
- };
-
- watchdog {
- compatible = "dlg,da9063-watchdog";
- };
- };
-};
-
-&mmcif0 {
- pinctrl-0 = <&mmcif0_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&d3_3v>;
- vqmmc-supply = <&d3_3v>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&sdhi1 {
- pinctrl-0 = <&sdhi1_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&vcc_sdhi1>;
- vqmmc-supply = <&vccq_sdhi1>;
- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&qspi {
- pinctrl-0 = <&qspi_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- flash@0 {
- compatible = "spansion,s25fl512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <30000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- spi-cpol;
- spi-cpha;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "loader";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "user";
- reg = <0x00040000 0x00400000>;
- read-only;
- };
- partition@440000 {
- label = "flash";
- reg = <0x00440000 0x03bc0000>;
- };
- };
- };
-};
-
-/* composite video input */
-&vin0 {
- status = "okay";
- pinctrl-0 = <&vin0_pins>;
- pinctrl-names = "default";
-
- port {
- vin0ep: endpoint {
- remote-endpoint = <&adv7180>;
- bus-width = <8>;
- };
- };
-};
-
-&pci0 {
- status = "okay";
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-};
-
-&pci1 {
- status = "okay";
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-};
-
-&usbphy {
- status = "okay";
-};
-
-&du {
- pinctrl-0 = <&du0_pins>, <&du1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
- <&x2_clk>, <&x3_clk>;
- clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
-
- ports {
- port@0 {
- endpoint {
- remote-endpoint = <&adv7511_in>;
- };
- };
- port@1 {
- endpoint {
- remote-endpoint = <&adv7123_in>;
- };
- };
- };
-};
-
-&rcar_sound {
- pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /* Single DAI */
- #sound-dai-cells = <0>;
-
- rcar_sound,dai {
- dai0 {
- playback = <&ssi0>;
- capture = <&ssi1>;
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&ssi1 {
- shared-pin;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car E2 (R8A77940) SoC
- *
- * Copyright (C) 2014 Renesas Electronics Corporation
- * Copyright (C) 2014 Ulrich Hecht
- */
-
-#include <dt-bindings/clock/r8a7794-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/power/r8a7794-sysc.h>
-
-/ {
- compatible = "renesas,r8a7794";
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &i2c7;
- spi0 = &qspi;
- vin0 = &vin0;
- vin1 = &vin1;
- };
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clka: audio_clka {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clkb: audio_clkb {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
- audio_clkc: audio_clkc {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0>;
- clock-frequency = <1000000000>;
- clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
- power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA7>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <1>;
- clock-frequency = <1000000000>;
- clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
- power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
- enable-method = "renesas,apmu";
- next-level-cache = <&L2_CA7>;
- };
-
- L2_CA7: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A7794_PD_CA7_SCU>;
- cache-unified;
- cache-level = <2>;
- };
- };
-
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>;
- };
-
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
-
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a7794-wdt",
- "renesas,rcar-gen2-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a7794",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a7794",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a7794",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a7794",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a7794",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a7794",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 28>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a7794",
- "renesas,rcar-gen2-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a7794";
- reg = <0 0xe6060000 0 0x11c>;
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7794-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&usb_extal_clk>;
- clock-names = "extal", "usb_extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- apmu@e6151000 {
- compatible = "renesas,r8a7794-apmu", "renesas,apmu";
- reg = <0 0xe6151000 0 0x188>;
- cpus = <&cpu0>, <&cpu1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7794-rst";
- reg = <0 0xe6160000 0 0x0100>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7794-sysc";
- reg = <0 0xe6180000 0 0x0200>;
- #power-domain-cells = <1>;
- };
-
- irqc0: interrupt-controller@e61c0000 {
- compatible = "renesas,irqc-r8a7794", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- ipmmu_sy0: iommu@e6280000 {
- compatible = "renesas,ipmmu-r8a7794",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe6280000 0 0x1000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_sy1: iommu@e6290000 {
- compatible = "renesas,ipmmu-r8a7794",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe6290000 0 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_ds: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a7794",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe6740000 0 0x1000>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_mp: iommu@ec680000 {
- compatible = "renesas,ipmmu-r8a7794",
- "renesas,ipmmu-vmsa";
- reg = <0 0xec680000 0 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_mx: iommu@fe951000 {
- compatible = "renesas,ipmmu-r8a7794",
- "renesas,ipmmu-vmsa";
- reg = <0 0xfe951000 0 0x1000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- ipmmu_gp: iommu@e62a0000 {
- compatible = "renesas,ipmmu-r8a7794",
- "renesas,ipmmu-vmsa";
- reg = <0 0xe62a0000 0 0x1000>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- status = "disabled";
- };
-
- icram0: sram@e63a0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63a0000 0 0x12000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63a0000 0x12000>;
- };
-
- icram1: sram@e63c0000 {
- compatible = "mmio-sram";
- reg = <0 0xe63c0000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0xe63c0000 0x1000>;
-
- smp-sram@0 {
- compatible = "renesas,smp-sram";
- reg = <0 0x100>;
- };
- };
-
- /* The memory map in the User's Manual maps the cores to
- * bus numbers
- */
- i2c0: i2c@e6508000 {
- compatible = "renesas,i2c-r8a7794",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c1: i2c@e6518000 {
- compatible = "renesas,i2c-r8a7794",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6518000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6530000 {
- compatible = "renesas,i2c-r8a7794",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6530000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e6540000 {
- compatible = "renesas,i2c-r8a7794",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6540000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c4: i2c@e6520000 {
- compatible = "renesas,i2c-r8a7794",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6520000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c5: i2c@e6528000 {
- compatible = "renesas,i2c-r8a7794",
- "renesas,rcar-gen2-i2c";
- reg = <0 0xe6528000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 925>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 925>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c6: i2c@e6500000 {
- compatible = "renesas,iic-r8a7794",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6500000 0 0x425>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- dmas = <&dmac0 0x61>, <&dmac0 0x62>,
- <&dmac1 0x61>, <&dmac1 0x62>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c7: i2c@e6510000 {
- compatible = "renesas,iic-r8a7794",
- "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6510000 0 0x425>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 323>;
- dmas = <&dmac0 0x65>, <&dmac0 0x66>,
- <&dmac1 0x65>, <&dmac1 0x66>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 323>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a7794",
- "renesas,rcar-gen2-usbhs";
- reg = <0 0xe6590000 0 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usbphy: usb-phy-controller@e6590100 {
- compatible = "renesas,usb-phy-r8a7794",
- "renesas,rcar-gen2-usb-phy";
- reg = <0 0xe6590100 0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cpg CPG_MOD 704>;
- clock-names = "usbhs";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- status = "disabled";
-
- usb0: usb-phy@0 {
- reg = <0>;
- #phy-cells = <1>;
- };
- usb2: usb-phy@2 {
- reg = <2>;
- #phy-cells = <1>;
- };
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a7794",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
-
- dmac1: dma-controller@e6720000 {
- compatible = "renesas,dmac-r8a7794",
- "renesas,rcar-dmac";
- reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <15>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7794",
- "renesas,etheravb-rcar-gen2";
- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- qspi: spi@e6b10000 {
- compatible = "renesas,qspi-r8a7794", "renesas,qspi";
- reg = <0 0xe6b10000 0 0x2c>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- dmas = <&dmac0 0x17>, <&dmac0 0x18>,
- <&dmac1 0x17>, <&dmac1 0x18>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- scifa0: serial@e6c40000 {
- compatible = "renesas,scifa-r8a7794",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>;
- clock-names = "fck";
- dmas = <&dmac0 0x21>, <&dmac0 0x22>,
- <&dmac1 0x21>, <&dmac1 0x22>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scifa1: serial@e6c50000 {
- compatible = "renesas,scifa-r8a7794",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>;
- clock-names = "fck";
- dmas = <&dmac0 0x25>, <&dmac0 0x26>,
- <&dmac1 0x25>, <&dmac1 0x26>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scifa2: serial@e6c60000 {
- compatible = "renesas,scifa-r8a7794",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c60000 0 64>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>;
- clock-names = "fck";
- dmas = <&dmac0 0x27>, <&dmac0 0x28>,
- <&dmac1 0x27>, <&dmac1 0x28>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- scifa3: serial@e6c70000 {
- compatible = "renesas,scifa-r8a7794",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c70000 0 64>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1106>;
- clock-names = "fck";
- dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
- <&dmac1 0x1b>, <&dmac1 0x1c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 1106>;
- status = "disabled";
- };
-
- scifa4: serial@e6c78000 {
- compatible = "renesas,scifa-r8a7794",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c78000 0 64>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1107>;
- clock-names = "fck";
- dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
- <&dmac1 0x1f>, <&dmac1 0x20>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 1107>;
- status = "disabled";
- };
-
- scifa5: serial@e6c80000 {
- compatible = "renesas,scifa-r8a7794",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c80000 0 64>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1108>;
- clock-names = "fck";
- dmas = <&dmac0 0x23>, <&dmac0 0x24>,
- <&dmac1 0x23>, <&dmac1 0x24>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 1108>;
- status = "disabled";
- };
-
- scifb0: serial@e6c20000 {
- compatible = "renesas,scifb-r8a7794",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c20000 0 0x100>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>;
- clock-names = "fck";
- dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
- <&dmac1 0x3d>, <&dmac1 0x3e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scifb1: serial@e6c30000 {
- compatible = "renesas,scifb-r8a7794",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6c30000 0 0x100>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>;
- clock-names = "fck";
- dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
- <&dmac1 0x19>, <&dmac1 0x1a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scifb2: serial@e6ce0000 {
- compatible = "renesas,scifb-r8a7794",
- "renesas,rcar-gen2-scifb", "renesas,scifb";
- reg = <0 0xe6ce0000 0 0x100>;
- interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 216>;
- clock-names = "fck";
- dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
- <&dmac1 0x1d>, <&dmac1 0x1e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 216>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a7794",
- "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
- <&dmac1 0x29>, <&dmac1 0x2a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 721>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a7794",
- "renesas,rcar-gen2-scif",
- "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
- <&dmac1 0x2d>, <&dmac1 0x2e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 720>;
- status = "disabled";
- };
-
- scif2: serial@e6e58000 {
- compatible = "renesas,scif-r8a7794",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6e58000 0 64>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
- <&dmac1 0x2b>, <&dmac1 0x2c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 719>;
- status = "disabled";
- };
-
- scif3: serial@e6ea8000 {
- compatible = "renesas,scif-r8a7794",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6ea8000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
- <&dmac1 0x2f>, <&dmac1 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 718>;
- status = "disabled";
- };
-
- scif4: serial@e6ee0000 {
- compatible = "renesas,scif-r8a7794",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6ee0000 0 64>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
- <&dmac1 0xfb>, <&dmac1 0xfc>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 715>;
- status = "disabled";
- };
-
- scif5: serial@e6ee8000 {
- compatible = "renesas,scif-r8a7794",
- "renesas,rcar-gen2-scif", "renesas,scif";
- reg = <0 0xe6ee8000 0 64>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
- <&dmac1 0xfd>, <&dmac1 0xfe>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
- };
-
- hscif0: serial@e62c0000 {
- compatible = "renesas,hscif-r8a7794",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c0000 0 96>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 717>,
- <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
- <&dmac1 0x39>, <&dmac1 0x3a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 717>;
- status = "disabled";
- };
-
- hscif1: serial@e62c8000 {
- compatible = "renesas,hscif-r8a7794",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62c8000 0 96>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>,
- <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
- <&dmac1 0x4d>, <&dmac1 0x4e>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
- };
-
- hscif2: serial@e62d0000 {
- compatible = "renesas,hscif-r8a7794",
- "renesas,rcar-gen2-hscif", "renesas,hscif";
- reg = <0 0xe62d0000 0 96>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
- <&dmac1 0x3b>, <&dmac1 0x3c>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 713>;
- status = "disabled";
- };
-
- can0: can@e6e80000 {
- compatible = "renesas,can-r8a7794",
- "renesas,rcar-gen2-can";
- reg = <0 0xe6e80000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6e88000 {
- compatible = "renesas,can-r8a7794",
- "renesas,rcar-gen2-can";
- reg = <0 0xe6e88000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7794",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- status = "disabled";
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7794",
- "renesas,rcar-gen2-vin";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- status = "disabled";
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a7794",
- "renesas,rcar_sound-gen2";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
- <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
- <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
- <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
- <&cpg CPG_CORE R8A7794_CLK_M2>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0",
- "src.6", "src.5", "src.4", "src.3",
- "src.2", "src.1",
- "ctu.0", "ctu.1",
- "mix.0", "mix.1",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>,
- <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>,
- <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0";
-
- status = "disabled";
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma0 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma0 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,src {
- src-0 {
- status = "disabled";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma0 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma0 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma0 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma0 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma0 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma0 0xb4>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma0 0x02>,
- <&audma0 0x15>, <&audma0 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma0 0x04>,
- <&audma0 0x49>, <&audma0 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma0 0x06>,
- <&audma0 0x63>, <&audma0 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma0 0x08>,
- <&audma0 0x6f>, <&audma0 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma0 0x0a>,
- <&audma0 0x71>, <&audma0 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma0 0x0c>,
- <&audma0 0x73>, <&audma0 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma0 0x0e>,
- <&audma0 0x75>, <&audma0 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma0 0x10>,
- <&audma0 0x79>, <&audma0 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma0 0x12>,
- <&audma0 0x7b>, <&audma0 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma0 0x14>,
- <&audma0 0x7d>, <&audma0 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- };
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a7794",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3", "ch4",
- "ch5", "ch6", "ch7", "ch8", "ch9",
- "ch10", "ch11",
- "ch12";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <13>;
- };
-
- pci0: pci@ee090000 {
- compatible = "renesas,pci-r8a7794",
- "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee090000 0 0xc00>,
- <0 0xee080000 0 0x1100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xf800 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x800 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
- };
-
- usb@2,0 {
- reg = <0x1000 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
- };
- };
-
- pci1: pci@ee0d0000 {
- compatible = "renesas,pci-r8a7794",
- "renesas,pci-rcar-gen2";
- device_type = "pci";
- reg = <0 0xee0d0000 0 0xc00>,
- <0 0xee0c0000 0 0x1100>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
-
- bus-range = <1 1>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xf800 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x10800 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
- };
-
- usb@2,0 {
- reg = <0x11000 0 0 0 0>;
- phys = <&usb2 0>;
- phy-names = "usb";
- };
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a7794",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- status = "disabled";
- };
-
- sdhi1: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a7794",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee140000 0 0x100>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>;
- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
- <&dmac1 0xc1>, <&dmac1 0xc2>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- status = "disabled";
- };
-
- sdhi2: mmc@ee160000 {
- compatible = "renesas,sdhi-r8a7794",
- "renesas,rcar-gen2-sdhi";
- reg = <0 0xee160000 0 0x100>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>;
- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
- <&dmac1 0xd3>, <&dmac1 0xd4>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- status = "disabled";
- };
-
- mmcif0: mmc@ee200000 {
- compatible = "renesas,mmcif-r8a7794",
- "renesas,sh-mmcif";
- reg = <0 0xee200000 0 0x80>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 315>;
- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
- <&dmac1 0xd1>, <&dmac1 0xd2>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 315>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- ether: ethernet@ee700000 {
- compatible = "renesas,ether-r8a7794",
- "renesas,rcar-gen2-ether";
- reg = <0 0xee700000 0 0x400>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- phy-mode = "rmii";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1001000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x2000>,
- <0 0xf1004000 0 0x2000>,
- <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- vsp@fe928000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe928000 0 0x8000>;
- interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 131>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 131>;
- };
-
- vsp@fe930000 {
- compatible = "renesas,vsp1";
- reg = <0 0xfe930000 0 0x8000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 128>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 128>;
- };
-
- fdp1@fe940000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe940000 0 0x2400>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 119>;
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 119>;
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a7794";
- reg = <0 0xfeb00000 0 0x40000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
- clock-names = "du.0", "du.1";
- resets = <&cpg 724>;
- reset-names = "du.0";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- du_out_rgb0: endpoint {
- };
- };
- port@1 {
- reg = <1>;
- du_out_rgb1: endpoint {
- };
- };
- };
- };
-
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
- };
-
- cmt0: timer@ffca0000 {
- compatible = "renesas,r8a7794-cmt0",
- "renesas,rcar-gen2-cmt0";
- reg = <0 0xffca0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
-
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7794-cmt1",
- "renesas,rcar-gen2-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 329>;
- clock-names = "fck";
- power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
- resets = <&cpg 329>;
-
- status = "disabled";
- };
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- /* External USB clock - can be overridden by the board */
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a77950.dtsi"
-#include "salvator-x.dtsi"
-
-/ {
- model = "Renesas Salvator-X board based on r8a77950";
- compatible = "renesas,salvator-x", "renesas,r8a7795";
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x38000000>;
- };
-
- memory@500000000 {
- device_type = "memory";
- reg = <0x5 0x00000000 0x0 0x40000000>;
- };
-
- memory@600000000 {
- device_type = "memory";
- reg = <0x6 0x00000000 0x0 0x40000000>;
- };
-
- memory@700000000 {
- device_type = "memory";
- reg = <0x7 0x00000000 0x0 0x40000000>;
- };
-};
-
-&du {
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>,
- <&cpg CPG_MOD 721>,
- <&versaclock5 1>,
- <&x21_clk>,
- <&x22_clk>,
- <&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.2", "du.3",
- "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES1.x
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- * Copyright (C) 2016 Cogent Embedded, Inc.
- */
-
-/dts-v1/;
-#include "r8a77950.dtsi"
-#include "ulcb.dtsi"
-
-/ {
- model = "Renesas H3ULCB board based on r8a77950";
- compatible = "renesas,h3ulcb", "renesas,r8a7795";
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x38000000>;
- };
-
- memory@500000000 {
- device_type = "memory";
- reg = <0x5 0x00000000 0x0 0x40000000>;
- };
-
- memory@600000000 {
- device_type = "memory";
- reg = <0x6 0x00000000 0x0 0x40000000>;
- };
-
- memory@700000000 {
- device_type = "memory";
- reg = <0x7 0x00000000 0x0 0x40000000>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car H3 (R8A77950) SoC
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#include "r8a77951.dtsi"
-
-#undef SOC_HAS_USB2_CH3
-
-&audma0 {
- iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>,
- <&ipmmu_mp1 2>, <&ipmmu_mp1 3>,
- <&ipmmu_mp1 4>, <&ipmmu_mp1 5>,
- <&ipmmu_mp1 6>, <&ipmmu_mp1 7>,
- <&ipmmu_mp1 8>, <&ipmmu_mp1 9>,
- <&ipmmu_mp1 10>, <&ipmmu_mp1 11>,
- <&ipmmu_mp1 12>, <&ipmmu_mp1 13>,
- <&ipmmu_mp1 14>, <&ipmmu_mp1 15>;
-};
-
-&audma1 {
- iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>,
- <&ipmmu_mp1 18>, <&ipmmu_mp1 19>,
- <&ipmmu_mp1 20>, <&ipmmu_mp1 21>,
- <&ipmmu_mp1 22>, <&ipmmu_mp1 23>,
- <&ipmmu_mp1 24>, <&ipmmu_mp1 25>,
- <&ipmmu_mp1 26>, <&ipmmu_mp1 27>,
- <&ipmmu_mp1 28>, <&ipmmu_mp1 29>,
- <&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
-};
-
-&cluster0_opp {
- /delete-node/ opp-1600000000;
- /delete-node/ opp-1700000000;
-};
-
-&du {
- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;
-};
-
-&fcpvb1 {
- iommus = <&ipmmu_vp0 7>;
-};
-
-&fcpf1 {
- iommus = <&ipmmu_vp0 1>;
-};
-
-&fcpvi1 {
- iommus = <&ipmmu_vp0 9>;
-};
-
-&fcpvd2 {
- iommus = <&ipmmu_vi0 10>;
-};
-
-&gpio1 {
- gpio-ranges = <&pfc 0 32 28>;
-};
-
-&ipmmu_vi0 {
- renesas,ipmmu-main = <&ipmmu_mm 11>;
-};
-
-&ipmmu_vp0 {
- renesas,ipmmu-main = <&ipmmu_mm 12>;
-};
-
-&ipmmu_vc0 {
- renesas,ipmmu-main = <&ipmmu_mm 9>;
-};
-
-&ipmmu_vc1 {
- renesas,ipmmu-main = <&ipmmu_mm 10>;
-};
-
-&ipmmu_rt {
- renesas,ipmmu-main = <&ipmmu_mm 7>;
-};
-
-&soc {
- /delete-node/ dma-controller@e6460000;
- /delete-node/ dma-controller@e6470000;
-
- ipmmu_mp1: iommu@ec680000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xec680000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 5>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_sy: iommu@e7730000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xe7730000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 8>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- /delete-node/ iommu@fd950000;
- /delete-node/ iommu@fd960000;
- /delete-node/ iommu@fd970000;
- /delete-node/ iommu@febe0000;
- /delete-node/ iommu@fe980000;
-
- xhci1: usb@ee040000 {
- compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
- reg = <0 0xee040000 0 0xc00>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 327>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 327>;
- status = "disabled";
- };
-
- /delete-node/ usb@e659c000;
- /delete-node/ usb@ee0e0000;
- /delete-node/ usb@ee0e0100;
-
- /delete-node/ usb-phy@ee0e0200;
-
- fdp1@fe948000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe948000 0 0x2400>;
- interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 117>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 117>;
- renesas,fcp = <&fcpf2>;
- };
-
- fcpf2: fcp@fe952000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe952000 0 0x200>;
- clocks = <&cpg CPG_MOD 613>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 613>;
- iommus = <&ipmmu_vp0 2>;
- };
-
- fcpvd3: fcp@fea3f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea3f000 0 0x200>;
- clocks = <&cpg CPG_MOD 600>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 600>;
- iommus = <&ipmmu_vi0 11>;
- };
-
- fcpvi2: fcp@fe9cf000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9cf000 0 0x200>;
- clocks = <&cpg CPG_MOD 609>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 609>;
- iommus = <&ipmmu_vp0 10>;
- };
-
- vspd3: vsp@fea38000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea38000 0 0x5000>;
- interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 620>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 620>;
-
- renesas,fcp = <&fcpvd3>;
- };
-
- vspi2: vsp@fe9c0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9c0000 0 0x8000>;
- interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 629>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 629>;
-
- renesas,fcp = <&fcpvi2>;
- };
-
- csi21: csi2@fea90000 {
- compatible = "renesas,r8a7795-csi2";
- reg = <0 0xfea90000 0 0x10000>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 713>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 713>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi21vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi21>;
- };
- csi21vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi21>;
- };
- csi21vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi21>;
- };
- csi21vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi21>;
- };
- csi21vin4: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&vin4csi21>;
- };
- csi21vin5: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&vin5csi21>;
- };
- csi21vin6: endpoint@6 {
- reg = <6>;
- remote-endpoint = <&vin6csi21>;
- };
- csi21vin7: endpoint@7 {
- reg = <7>;
- remote-endpoint = <&vin7csi21>;
- };
- };
- };
- };
-};
-
-&vin0 {
- ports {
- port@1 {
- vin0csi21: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csi21vin0>;
- };
- };
- };
-};
-
-&vin1 {
- ports {
- port@1 {
- vin1csi21: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csi21vin1>;
- };
- };
- };
-};
-
-&vin2 {
- ports {
- port@1 {
- vin2csi21: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csi21vin2>;
- };
- };
- };
-};
-
-&vin3 {
- ports {
- port@1 {
- vin3csi21: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csi21vin3>;
- };
- };
- };
-};
-
-&vin4 {
- ports {
- port@1 {
- vin4csi21: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csi21vin4>;
- };
- };
- };
-};
-
-&vin5 {
- ports {
- port@1 {
- vin5csi21: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csi21vin5>;
- };
- };
- };
-};
-
-&vin6 {
- ports {
- port@1 {
- vin6csi21: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csi21vin6>;
- };
- };
- };
-};
-
-&vin7 {
- ports {
- port@1 {
- vin7csi21: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csi21vin7>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car H3 (R8A77951) SoC
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a7795-sysc.h>
-
-#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
-
-#define SOC_HAS_HDMI1
-#define SOC_HAS_SATA
-#define SOC_HAS_USB2_CH2
-#define SOC_HAS_USB2_CH3
-
-/ {
- compatible = "renesas,r8a7795";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cluster0_opp: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <830000>;
- clock-latency-ns = <300000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <830000>;
- clock-latency-ns = <300000>;
- };
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <830000>;
- clock-latency-ns = <300000>;
- opp-suspend;
- };
- opp-1600000000 {
- opp-hz = /bits/ 64 <1600000000>;
- opp-microvolt = <900000>;
- clock-latency-ns = <300000>;
- };
- opp-1700000000 {
- opp-hz = /bits/ 64 <1700000000>;
- opp-microvolt = <960000>;
- clock-latency-ns = <300000>;
- turbo-mode;
- };
- };
-
- cluster1_opp: opp-table-1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&a57_0>;
- };
- core1 {
- cpu = <&a57_1>;
- };
- core2 {
- cpu = <&a57_2>;
- };
- core3 {
- cpu = <&a57_3>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&a53_0>;
- };
- core1 {
- cpu = <&a53_1>;
- };
- core2 {
- cpu = <&a53_2>;
- };
- core3 {
- cpu = <&a53_3>;
- };
- };
- };
-
- a57_0: cpu@0 {
- compatible = "arm,cortex-a57";
- reg = <0x0>;
- device_type = "cpu";
- power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- dynamic-power-coefficient = <854>;
- clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <1024>;
- #cooling-cells = <2>;
- };
-
- a57_1: cpu@1 {
- compatible = "arm,cortex-a57";
- reg = <0x1>;
- device_type = "cpu";
- power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <1024>;
- #cooling-cells = <2>;
- };
-
- a57_2: cpu@2 {
- compatible = "arm,cortex-a57";
- reg = <0x2>;
- device_type = "cpu";
- power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <1024>;
- #cooling-cells = <2>;
- };
-
- a57_3: cpu@3 {
- compatible = "arm,cortex-a57";
- reg = <0x3>;
- device_type = "cpu";
- power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <1024>;
- #cooling-cells = <2>;
- };
-
- a53_0: cpu@100 {
- compatible = "arm,cortex-a53";
- reg = <0x100>;
- device_type = "cpu";
- power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_1>;
- #cooling-cells = <2>;
- dynamic-power-coefficient = <277>;
- clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <535>;
- };
-
- a53_1: cpu@101 {
- compatible = "arm,cortex-a53";
- reg = <0x101>;
- device_type = "cpu";
- power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_1>;
- clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <535>;
- };
-
- a53_2: cpu@102 {
- compatible = "arm,cortex-a53";
- reg = <0x102>;
- device_type = "cpu";
- power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_1>;
- clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <535>;
- };
-
- a53_3: cpu@103 {
- compatible = "arm,cortex-a53";
- reg = <0x103>;
- device_type = "cpu";
- power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_1>;
- clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <535>;
- };
-
- L2_CA57: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A7795_PD_CA57_SCU>;
- cache-unified;
- cache-level = <2>;
- };
-
- L2_CA53: cache-controller-1 {
- compatible = "cache";
- power-domains = <&sysc R8A7795_PD_CA53_SCU>;
- cache-unified;
- cache-level = <2>;
- };
-
- idle-states {
- entry-method = "psci";
-
- CPU_SLEEP_0: cpu-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- local-timer-stop;
- entry-latency-us = <400>;
- exit-latency-us = <500>;
- min-residency-us = <4000>;
- };
-
- CPU_SLEEP_1: cpu-sleep-1 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- local-timer-stop;
- entry-latency-us = <700>;
- exit-latency-us = <700>;
- min-residency-us = <5000>;
- };
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- extalr_clk: extalr {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a53_0>,
- <&a53_1>,
- <&a53_2>,
- <&a53_3>;
- };
-
- pmu_a57 {
- compatible = "arm,cortex-a57-pmu";
- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a57_0>,
- <&a57_1>,
- <&a57_2>,
- <&a57_3>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc: soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
-
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a7795",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a7795",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 29>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a7795",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 15>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a7795",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a7795",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 18>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a7795",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a7795",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 906>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 906>;
- };
-
- gpio7: gpio@e6055800 {
- compatible = "renesas,gpio-r8a7795",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055800 0 0x50>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 224 4>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a7795";
- reg = <0 0xe6060000 0 0x50c>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a7795-cmt0",
- "renesas,rcar-gen3-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 303>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 303>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7795-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 302>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 302>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a7795-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 301>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 301>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a7795-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7795-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7795-rst";
- reg = <0 0xe6160000 0 0x0200>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7795-sysc";
- reg = <0 0xe6180000 0 0x0400>;
- #power-domain-cells = <1>;
- };
-
- tsc: thermal@e6198000 {
- compatible = "renesas,r8a7795-thermal";
- reg = <0 0xe6198000 0 0x100>,
- <0 0xe61a0000 0 0x100>,
- <0 0xe61a8000 0 0x100>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <1>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a7795", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a7795", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 125>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 125>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a7795", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a7795", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 123>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 123>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a7795", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 122>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 122>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a7795", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 121>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 121>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7795",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>,
- <&dmac2 0x91>, <&dmac2 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7795",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>,
- <&dmac2 0x93>, <&dmac2 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7795",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>,
- <&dmac2 0x95>, <&dmac2 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7795",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- dmas = <&dmac0 0x97>, <&dmac0 0x96>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7795",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- dmas = <&dmac0 0x99>, <&dmac0 0x98>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c5: i2c@e66e0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7795",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e0000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c6: i2c@e66e8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7795",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e8000 0 0x40>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c_dvfs: i2c@e60b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7795",
- "renesas,rcar-gen3-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- dmas = <&dmac0 0x11>, <&dmac0 0x10>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a7795",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6540000 0 96>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>,
- <&cpg CPG_CORE R8A7795_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>,
- <&dmac2 0x31>, <&dmac2 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a7795",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6550000 0 96>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>,
- <&cpg CPG_CORE R8A7795_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x33>, <&dmac1 0x32>,
- <&dmac2 0x33>, <&dmac2 0x32>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a7795",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6560000 0 96>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>,
- <&cpg CPG_CORE R8A7795_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x35>, <&dmac1 0x34>,
- <&dmac2 0x35>, <&dmac2 0x34>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a7795",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66a0000 0 96>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A7795_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x37>, <&dmac0 0x36>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- hscif4: serial@e66b0000 {
- compatible = "renesas,hscif-r8a7795",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66b0000 0 96>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A7795_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x38>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 516>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a7795",
- "renesas,rcar-gen3-usbhs";
- reg = <0 0xe6590000 0 0x200>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- renesas,buswait = <11>;
- phys = <&usb2_phy0 3>;
- phy-names = "usb";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 704>, <&cpg 703>;
- status = "disabled";
- };
-
- hsusb3: usb@e659c000 {
- compatible = "renesas,usbhs-r8a7795",
- "renesas,rcar-gen3-usbhs";
- reg = <0 0xe659c000 0 0x200>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>;
- dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
- <&usb_dmac3 0>, <&usb_dmac3 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- renesas,buswait = <11>;
- phys = <&usb2_phy3 3>;
- phy-names = "usb";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 705>, <&cpg 700>;
- status = "disabled";
- };
-
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a7795-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a7795-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac2: dma-controller@e6460000 {
- compatible = "renesas,r8a7795-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe6460000 0 0x100>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 326>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 326>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac3: dma-controller@e6470000 {
- compatible = "renesas,r8a7795-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe6470000 0 0x100>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 329>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 329>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb3_phy0: usb-phy@e65ee000 {
- compatible = "renesas,r8a7795-usb3-phy",
- "renesas,rcar-gen3-usb3-phy";
- reg = <0 0xe65ee000 0 0x90>;
- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
- <&usb_extal_clk>;
- clock-names = "usb3-if", "usb3s_clk", "usb_extal";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- arm_cc630p: crypto@e6601000 {
- compatible = "arm,cryptocell-630p-ree";
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x0 0xe6601000 0 0x1000>;
- clocks = <&cpg CPG_MOD 229>;
- resets = <&cpg 229>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a7795",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x10000>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
- };
-
- dmac1: dma-controller@e7300000 {
- compatible = "renesas,dmac-r8a7795",
- "renesas,rcar-dmac";
- reg = <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
- };
-
- dmac2: dma-controller@e7310000 {
- compatible = "renesas,dmac-r8a7795",
- "renesas,rcar-dmac";
- reg = <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 217>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 217>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
- };
-
- ipmmu_ds0: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xe6740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds1: iommu@e7740000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 1>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_hc: iommu@e6570000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xe6570000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 2>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ir: iommu@ff8b0000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xff8b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 3>;
- power-domains = <&sysc R8A7795_PD_A3IR>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@e67b0000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mp0: iommu@ec670000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xec670000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 4>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv0: iommu@fd800000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xfd800000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 6>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv1: iommu@fd950000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xfd950000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 7>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv2: iommu@fd960000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xfd960000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 8>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv3: iommu@fd970000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xfd970000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 9>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_rt: iommu@ffc80000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xffc80000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 10>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: iommu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xfe6b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 12>;
- power-domains = <&sysc R8A7795_PD_A3VC>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc1: iommu@fe6f0000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xfe6f0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 13>;
- power-domains = <&sysc R8A7795_PD_A3VC>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@febd0000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 14>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi1: iommu@febe0000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xfebe0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 15>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vp0: iommu@fe990000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xfe990000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 16>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vp1: iommu@fe980000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xfe980000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 17>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- #iommu-cells = <1>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7795",
- "renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- iommus = <&ipmmu_ds0 16>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can0: can@e6c30000 {
- compatible = "renesas,can-r8a7795",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c30000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A7795_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6c38000 {
- compatible = "renesas,can-r8a7795",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c38000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A7795_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a7795-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A7795_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 914>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm5: pwm@e6e35000 {
- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
- reg = <0 0xe6e35000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm6: pwm@e6e36000 {
- compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
- reg = <0 0xe6e36000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a7795",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE R8A7795_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>,
- <&dmac2 0x51>, <&dmac2 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a7795",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE R8A7795_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>,
- <&dmac2 0x53>, <&dmac2 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scif2: serial@e6e88000 {
- compatible = "renesas,scif-r8a7795",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e88000 0 64>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>,
- <&cpg CPG_CORE R8A7795_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x13>, <&dmac1 0x12>,
- <&dmac2 0x13>, <&dmac2 0x12>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 310>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a7795",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE R8A7795_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x57>, <&dmac0 0x56>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a7795",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE R8A7795_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x59>, <&dmac0 0x58>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scif5: serial@e6f30000 {
- compatible = "renesas,scif-r8a7795",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6f30000 0 64>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>,
- <&cpg CPG_CORE R8A7795_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
- <&dmac2 0x5b>, <&dmac2 0x5a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- tpu: pwm@e6e80000 {
- compatible = "renesas,tpu-r8a7795", "renesas,tpu";
- reg = <0 0xe6e80000 0 0x148>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 304>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 304>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a7795",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6e90000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
- dmas = <&dmac1 0x41>, <&dmac1 0x40>,
- <&dmac2 0x41>, <&dmac2 0x40>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a7795",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
- dmas = <&dmac1 0x43>, <&dmac1 0x42>,
- <&dmac2 0x43>, <&dmac2 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 210>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a7795",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
- dmas = <&dmac0 0x45>, <&dmac0 0x44>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 209>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a7795",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x47>, <&dmac0 0x46>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7795";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- renesas,id = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin0csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin0>;
- };
- vin0csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin0>;
- };
- };
- };
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7795";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- renesas,id = <1>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin1csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin1>;
- };
- vin1csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin1>;
- };
- };
- };
- };
-
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a7795";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- renesas,id = <2>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin2csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin2>;
- };
- vin2csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin2>;
- };
- };
- };
- };
-
- vin3: video@e6ef3000 {
- compatible = "renesas,vin-r8a7795";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- renesas,id = <3>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin3csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin3>;
- };
- vin3csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin3>;
- };
- };
- };
- };
-
- vin4: video@e6ef4000 {
- compatible = "renesas,vin-r8a7795";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 807>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 807>;
- renesas,id = <4>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin4csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin4>;
- };
- vin4csi41: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&csi41vin4>;
- };
- };
- };
- };
-
- vin5: video@e6ef5000 {
- compatible = "renesas,vin-r8a7795";
- reg = <0 0xe6ef5000 0 0x1000>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 806>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 806>;
- renesas,id = <5>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin5csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin5>;
- };
- vin5csi41: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&csi41vin5>;
- };
- };
- };
- };
-
- vin6: video@e6ef6000 {
- compatible = "renesas,vin-r8a7795";
- reg = <0 0xe6ef6000 0 0x1000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 805>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 805>;
- renesas,id = <6>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin6csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin6>;
- };
- vin6csi41: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&csi41vin6>;
- };
- };
- };
- };
-
- vin7: video@e6ef7000 {
- compatible = "renesas,vin-r8a7795";
- reg = <0 0xe6ef7000 0 0x1000>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 804>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 804>;
- renesas,id = <7>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin7csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin7>;
- };
- vin7csi41: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&csi41vin7>;
- };
- };
- };
- };
-
- drif00: rif@e6f40000 {
- compatible = "renesas,r8a7795-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f40000 0 0x64>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 515>;
- clock-names = "fck";
- dmas = <&dmac1 0x20>, <&dmac2 0x20>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 515>;
- renesas,bonding = <&drif01>;
- status = "disabled";
- };
-
- drif01: rif@e6f50000 {
- compatible = "renesas,r8a7795-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f50000 0 0x64>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 514>;
- clock-names = "fck";
- dmas = <&dmac1 0x22>, <&dmac2 0x22>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 514>;
- renesas,bonding = <&drif00>;
- status = "disabled";
- };
-
- drif10: rif@e6f60000 {
- compatible = "renesas,r8a7795-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f60000 0 0x64>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 513>;
- clock-names = "fck";
- dmas = <&dmac1 0x24>, <&dmac2 0x24>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 513>;
- renesas,bonding = <&drif11>;
- status = "disabled";
- };
-
- drif11: rif@e6f70000 {
- compatible = "renesas,r8a7795-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f70000 0 0x64>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 512>;
- clock-names = "fck";
- dmas = <&dmac1 0x26>, <&dmac2 0x26>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 512>;
- renesas,bonding = <&drif10>;
- status = "disabled";
- };
-
- drif20: rif@e6f80000 {
- compatible = "renesas,r8a7795-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f80000 0 0x64>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 511>;
- clock-names = "fck";
- dmas = <&dmac1 0x28>, <&dmac2 0x28>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 511>;
- renesas,bonding = <&drif21>;
- status = "disabled";
- };
-
- drif21: rif@e6f90000 {
- compatible = "renesas,r8a7795-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f90000 0 0x64>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 510>;
- clock-names = "fck";
- dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 510>;
- renesas,bonding = <&drif20>;
- status = "disabled";
- };
-
- drif30: rif@e6fa0000 {
- compatible = "renesas,r8a7795-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6fa0000 0 0x64>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 509>;
- clock-names = "fck";
- dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 509>;
- renesas,bonding = <&drif31>;
- status = "disabled";
- };
-
- drif31: rif@e6fb0000 {
- compatible = "renesas,r8a7795-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6fb0000 0 0x64>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 508>;
- clock-names = "fck";
- dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 508>;
- renesas,bonding = <&drif30>;
- status = "disabled";
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- /*
- * #clock-cells is required for audio_clkout0/1/2/3
- *
- * clkout : #clock-cells = <0>; <&rcar_sound>;
- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A7795_CLK_S0D4>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6",
- "src.5", "src.4", "src.3", "src.2",
- "src.1", "src.0",
- "mix.1", "mix.0",
- "ctu.1", "ctu.0",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>,
- <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>,
- <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0";
- status = "disabled";
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma1 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma1 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssiu {
- ssiu00: ssiu-0 {
- dmas = <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx";
- };
- ssiu01: ssiu-1 {
- dmas = <&audma0 0x35>, <&audma1 0x36>;
- dma-names = "rx", "tx";
- };
- ssiu02: ssiu-2 {
- dmas = <&audma0 0x37>, <&audma1 0x38>;
- dma-names = "rx", "tx";
- };
- ssiu03: ssiu-3 {
- dmas = <&audma0 0x47>, <&audma1 0x48>;
- dma-names = "rx", "tx";
- };
- ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
- dma-names = "rx", "tx";
- };
- ssiu05: ssiu-5 {
- dmas = <&audma0 0x43>, <&audma1 0x44>;
- dma-names = "rx", "tx";
- };
- ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
- dma-names = "rx", "tx";
- };
- ssiu07: ssiu-7 {
- dmas = <&audma0 0x53>, <&audma1 0x54>;
- dma-names = "rx", "tx";
- };
- ssiu10: ssiu-8 {
- dmas = <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx";
- };
- ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
- dma-names = "rx", "tx";
- };
- ssiu12: ssiu-10 {
- dmas = <&audma0 0x57>, <&audma1 0x58>;
- dma-names = "rx", "tx";
- };
- ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
- dma-names = "rx", "tx";
- };
- ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
- dma-names = "rx", "tx";
- };
- ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
- dma-names = "rx", "tx";
- };
- ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
- dma-names = "rx", "tx";
- };
- ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
- dma-names = "rx", "tx";
- };
- ssiu20: ssiu-16 {
- dmas = <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx";
- };
- ssiu21: ssiu-17 {
- dmas = <&audma0 0x67>, <&audma1 0x68>;
- dma-names = "rx", "tx";
- };
- ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
- dma-names = "rx", "tx";
- };
- ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
- dma-names = "rx", "tx";
- };
- ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
- dma-names = "rx", "tx";
- };
- ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
- dma-names = "rx", "tx";
- };
- ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
- dma-names = "rx", "tx";
- };
- ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
- dma-names = "rx", "tx";
- };
- ssiu30: ssiu-24 {
- dmas = <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx";
- };
- ssiu31: ssiu-25 {
- dmas = <&audma0 0x21>, <&audma1 0x22>;
- dma-names = "rx", "tx";
- };
- ssiu32: ssiu-26 {
- dmas = <&audma0 0x23>, <&audma1 0x24>;
- dma-names = "rx", "tx";
- };
- ssiu33: ssiu-27 {
- dmas = <&audma0 0x25>, <&audma1 0x26>;
- dma-names = "rx", "tx";
- };
- ssiu34: ssiu-28 {
- dmas = <&audma0 0x27>, <&audma1 0x28>;
- dma-names = "rx", "tx";
- };
- ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
- dma-names = "rx", "tx";
- };
- ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
- dma-names = "rx", "tx";
- };
- ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
- dma-names = "rx", "tx";
- };
- ssiu40: ssiu-32 {
- dmas = <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx";
- };
- ssiu41: ssiu-33 {
- dmas = <&audma0 0x17>, <&audma1 0x18>;
- dma-names = "rx", "tx";
- };
- ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
- dma-names = "rx", "tx";
- };
- ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
- dma-names = "rx", "tx";
- };
- ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
- dma-names = "rx", "tx";
- };
- ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
- dma-names = "rx", "tx";
- };
- ssiu46: ssiu-38 {
- dmas = <&audma0 0x31>, <&audma1 0x32>;
- dma-names = "rx", "tx";
- };
- ssiu47: ssiu-39 {
- dmas = <&audma0 0x33>, <&audma1 0x34>;
- dma-names = "rx", "tx";
- };
- ssiu50: ssiu-40 {
- dmas = <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx";
- };
- ssiu60: ssiu-41 {
- dmas = <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx";
- };
- ssiu70: ssiu-42 {
- dmas = <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx";
- };
- ssiu80: ssiu-43 {
- dmas = <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx";
- };
- ssiu90: ssiu-44 {
- dmas = <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx";
- };
- ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
- dma-names = "rx", "tx";
- };
- ssiu92: ssiu-46 {
- dmas = <&audma0 0x81>, <&audma1 0x82>;
- dma-names = "rx", "tx";
- };
- ssiu93: ssiu-47 {
- dmas = <&audma0 0x83>, <&audma1 0x84>;
- dma-names = "rx", "tx";
- };
- ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
- dma-names = "rx", "tx";
- };
- ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
- dma-names = "rx", "tx";
- };
- ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
- dma-names = "rx", "tx";
- };
- ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>;
- dma-names = "rx", "tx";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>;
- dma-names = "rx", "tx";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>;
- dma-names = "rx", "tx";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>;
- dma-names = "rx", "tx";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>;
- dma-names = "rx", "tx";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>;
- dma-names = "rx", "tx";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>;
- dma-names = "rx", "tx";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>;
- dma-names = "rx", "tx";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>;
- dma-names = "rx", "tx";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>;
- dma-names = "rx", "tx";
- };
- };
- };
-
- mlp: mlp@ec520000 {
- compatible = "renesas,r8a7795-mlp",
- "renesas,rcar-gen3-mlp";
- reg = <0 0xec520000 0 0x800>;
- interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 802>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 802>;
- status = "disabled";
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a7795",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
- <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
- <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
- <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
- <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
- <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
- <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
- <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
- };
-
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a7795",
- "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
- <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
- <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
- <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
- <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
- <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
- <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
- <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
- };
-
- xhci0: usb@ee000000 {
- compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- usb3_peri0: usb@ee020000 {
- compatible = "renesas,r8a7795-usb3-peri",
- "renesas,rcar-gen3-usb3-peri";
- reg = <0 0xee020000 0 0x400>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- ohci0: usb@ee080000 {
- compatible = "generic-ohci";
- reg = <0 0xee080000 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ohci1: usb@ee0a0000 {
- compatible = "generic-ohci";
- reg = <0 0xee0a0000 0 0x100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>;
- phys = <&usb2_phy1 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- ohci2: usb@ee0c0000 {
- compatible = "generic-ohci";
- reg = <0 0xee0c0000 0 0x100>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 701>;
- phys = <&usb2_phy2 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 701>;
- status = "disabled";
- };
-
- ohci3: usb@ee0e0000 {
- compatible = "generic-ohci";
- reg = <0 0xee0e0000 0 0x100>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
- phys = <&usb2_phy3 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 700>, <&cpg 705>;
- status = "disabled";
- };
-
- ehci0: usb@ee080100 {
- compatible = "generic-ehci";
- reg = <0 0xee080100 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 2>;
- phy-names = "usb";
- companion = <&ohci0>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ehci1: usb@ee0a0100 {
- compatible = "generic-ehci";
- reg = <0 0xee0a0100 0 0x100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>;
- phys = <&usb2_phy1 2>;
- phy-names = "usb";
- companion = <&ohci1>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- ehci2: usb@ee0c0100 {
- compatible = "generic-ehci";
- reg = <0 0xee0c0100 0 0x100>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 701>;
- phys = <&usb2_phy2 2>;
- phy-names = "usb";
- companion = <&ohci2>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 701>;
- status = "disabled";
- };
-
- ehci3: usb@ee0e0100 {
- compatible = "generic-ehci";
- reg = <0 0xee0e0100 0 0x100>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
- phys = <&usb2_phy3 2>;
- phy-names = "usb";
- companion = <&ohci3>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 700>, <&cpg 705>;
- status = "disabled";
- };
-
- usb2_phy0: usb-phy@ee080200 {
- compatible = "renesas,usb2-phy-r8a7795",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee080200 0 0x700>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- usb2_phy1: usb-phy@ee0a0200 {
- compatible = "renesas,usb2-phy-r8a7795",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee0a0200 0 0x700>;
- clocks = <&cpg CPG_MOD 702>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- usb2_phy2: usb-phy@ee0c0200 {
- compatible = "renesas,usb2-phy-r8a7795",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee0c0200 0 0x700>;
- clocks = <&cpg CPG_MOD 701>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 701>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- usb2_phy3: usb-phy@ee0e0200 {
- compatible = "renesas,usb2-phy-r8a7795",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee0e0200 0 0x700>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 700>, <&cpg 705>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a7795",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee100000 0 0x2000>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- iommus = <&ipmmu_ds1 32>;
- status = "disabled";
- };
-
- sdhi1: mmc@ee120000 {
- compatible = "renesas,sdhi-r8a7795",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee120000 0 0x2000>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 313>;
- iommus = <&ipmmu_ds1 33>;
- status = "disabled";
- };
-
- sdhi2: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a7795",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- iommus = <&ipmmu_ds1 34>;
- status = "disabled";
- };
-
- sdhi3: mmc@ee160000 {
- compatible = "renesas,sdhi-r8a7795",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee160000 0 0x2000>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- iommus = <&ipmmu_ds1 35>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a7795-rpc-if",
- "renesas,rcar-gen3-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x04000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sata: sata@ee300000 {
- compatible = "renesas,sata-r8a7795",
- "renesas,rcar-gen3-sata";
- reg = <0 0xee300000 0 0x200000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 815>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 815>;
- status = "disabled";
- iommus = <&ipmmu_hc 2>;
- };
-
- gic: interrupt-controller@f1010000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1010000 0 0x1000>,
- <0x0 0xf1020000 0 0x20000>,
- <0x0 0xf1040000 0 0x20000>,
- <0x0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- pciec0: pcie@fe000000 {
- compatible = "renesas,pcie-r8a7795",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- iommu-map = <0 &ipmmu_hc 0 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- pciec1: pcie@ee800000 {
- compatible = "renesas,pcie-r8a7795",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xee800000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- iommu-map = <0 &ipmmu_hc 1 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- pciec0_ep: pcie-ep@fe000000 {
- compatible = "renesas,r8a7795-pcie-ep",
- "renesas,rcar-gen3-pcie-ep";
- reg = <0x0 0xfe000000 0 0x80000>,
- <0x0 0xfe100000 0 0x100000>,
- <0x0 0xfe200000 0 0x200000>,
- <0x0 0x30000000 0 0x8000000>,
- <0x0 0x38000000 0 0x8000000>;
- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>;
- clock-names = "pcie";
- resets = <&cpg 319>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pciec1_ep: pcie-ep@ee800000 {
- compatible = "renesas,r8a7795-pcie-ep",
- "renesas,rcar-gen3-pcie-ep";
- reg = <0x0 0xee800000 0 0x80000>,
- <0x0 0xee900000 0 0x100000>,
- <0x0 0xeea00000 0 0x200000>,
- <0x0 0xc0000000 0 0x8000000>,
- <0x0 0xc8000000 0 0x8000000>;
- reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- clock-names = "pcie";
- resets = <&cpg 318>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- imr-lx4@fe860000 {
- compatible = "renesas,r8a7795-imr-lx4",
- "renesas,imr-lx4";
- reg = <0 0xfe860000 0 0x2000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 823>;
- power-domains = <&sysc R8A7795_PD_A3VC>;
- resets = <&cpg 823>;
- };
-
- imr-lx4@fe870000 {
- compatible = "renesas,r8a7795-imr-lx4",
- "renesas,imr-lx4";
- reg = <0 0xfe870000 0 0x2000>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 822>;
- power-domains = <&sysc R8A7795_PD_A3VC>;
- resets = <&cpg 822>;
- };
-
- imr-lx4@fe880000 {
- compatible = "renesas,r8a7795-imr-lx4",
- "renesas,imr-lx4";
- reg = <0 0xfe880000 0 0x2000>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 821>;
- power-domains = <&sysc R8A7795_PD_A3VC>;
- resets = <&cpg 821>;
- };
-
- imr-lx4@fe890000 {
- compatible = "renesas,r8a7795-imr-lx4",
- "renesas,imr-lx4";
- reg = <0 0xfe890000 0 0x2000>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 820>;
- power-domains = <&sysc R8A7795_PD_A3VC>;
- resets = <&cpg 820>;
- };
-
- vspbc: vsp@fe920000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe920000 0 0x8000>;
- interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 624>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 624>;
-
- renesas,fcp = <&fcpvb1>;
- };
-
- vspbd: vsp@fe960000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe960000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 626>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 626>;
-
- renesas,fcp = <&fcpvb0>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x5000>;
- interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
-
- renesas,fcp = <&fcpvd0>;
- };
-
- vspd1: vsp@fea28000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x5000>;
- interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 622>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 622>;
-
- renesas,fcp = <&fcpvd1>;
- };
-
- vspd2: vsp@fea30000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea30000 0 0x5000>;
- interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 621>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 621>;
-
- renesas,fcp = <&fcpvd2>;
- };
-
- vspi0: vsp@fe9a0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9a0000 0 0x8000>;
- interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 631>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 631>;
-
- renesas,fcp = <&fcpvi0>;
- };
-
- vspi1: vsp@fe9b0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9b0000 0 0x8000>;
- interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 630>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 630>;
-
- renesas,fcp = <&fcpvi1>;
- };
-
- fdp1@fe940000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe940000 0 0x2400>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 119>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 119>;
- renesas,fcp = <&fcpf0>;
- };
-
- fdp1@fe944000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe944000 0 0x2400>;
- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 118>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 118>;
- renesas,fcp = <&fcpf1>;
- };
-
- fcpf0: fcp@fe950000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe950000 0 0x200>;
- clocks = <&cpg CPG_MOD 615>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 615>;
- iommus = <&ipmmu_vp0 0>;
- };
-
- fcpf1: fcp@fe951000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe951000 0 0x200>;
- clocks = <&cpg CPG_MOD 614>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 614>;
- iommus = <&ipmmu_vp1 1>;
- };
-
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 607>;
- iommus = <&ipmmu_vp0 5>;
- };
-
- fcpvb1: fcp@fe92f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe92f000 0 0x200>;
- clocks = <&cpg CPG_MOD 606>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 606>;
- iommus = <&ipmmu_vp1 7>;
- };
-
- fcpvi0: fcp@fe9af000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9af000 0 0x200>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 611>;
- iommus = <&ipmmu_vp0 8>;
- };
-
- fcpvi1: fcp@fe9bf000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9bf000 0 0x200>;
- clocks = <&cpg CPG_MOD 610>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 610>;
- iommus = <&ipmmu_vp1 9>;
- };
-
- fcpvd0: fcp@fea27000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea27000 0 0x200>;
- clocks = <&cpg CPG_MOD 603>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 603>;
- iommus = <&ipmmu_vi0 8>;
- };
-
- fcpvd1: fcp@fea2f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea2f000 0 0x200>;
- clocks = <&cpg CPG_MOD 602>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 602>;
- iommus = <&ipmmu_vi0 9>;
- };
-
- fcpvd2: fcp@fea37000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea37000 0 0x200>;
- clocks = <&cpg CPG_MOD 601>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 601>;
- iommus = <&ipmmu_vi1 10>;
- };
-
- cmm0: cmm@fea40000 {
- compatible = "renesas,r8a7795-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea40000 0 0x1000>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 711>;
- resets = <&cpg 711>;
- };
-
- cmm1: cmm@fea50000 {
- compatible = "renesas,r8a7795-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea50000 0 0x1000>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 710>;
- resets = <&cpg 710>;
- };
-
- cmm2: cmm@fea60000 {
- compatible = "renesas,r8a7795-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea60000 0 0x1000>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 709>;
- resets = <&cpg 709>;
- };
-
- cmm3: cmm@fea70000 {
- compatible = "renesas,r8a7795-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea70000 0 0x1000>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 708>;
- resets = <&cpg 708>;
- };
-
- csi20: csi2@fea80000 {
- compatible = "renesas,r8a7795-csi2";
- reg = <0 0xfea80000 0 0x10000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi20vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi20>;
- };
- csi20vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi20>;
- };
- csi20vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi20>;
- };
- csi20vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi20>;
- };
- csi20vin4: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&vin4csi20>;
- };
- csi20vin5: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&vin5csi20>;
- };
- csi20vin6: endpoint@6 {
- reg = <6>;
- remote-endpoint = <&vin6csi20>;
- };
- csi20vin7: endpoint@7 {
- reg = <7>;
- remote-endpoint = <&vin7csi20>;
- };
- };
- };
- };
-
- csi40: csi2@feaa0000 {
- compatible = "renesas,r8a7795-csi2";
- reg = <0 0xfeaa0000 0 0x10000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi40vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi40>;
- };
- csi40vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi40>;
- };
- csi40vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi40>;
- };
- csi40vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi40>;
- };
- };
- };
- };
-
- csi41: csi2@feab0000 {
- compatible = "renesas,r8a7795-csi2";
- reg = <0 0xfeab0000 0 0x10000>;
- interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 715>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 715>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi41vin4: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin4csi41>;
- };
- csi41vin5: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin5csi41>;
- };
- csi41vin6: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin6csi41>;
- };
- csi41vin7: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin7csi41>;
- };
- };
- };
- };
-
- hdmi0: hdmi@fead0000 {
- compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
- reg = <0 0xfead0000 0 0x10000>;
- interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
- clock-names = "iahb", "isfr";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 729>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- dw_hdmi0_in: endpoint {
- remote-endpoint = <&du_out_hdmi0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- port@2 {
- /* HDMI sound */
- reg = <2>;
- };
- };
- };
-
- hdmi1: hdmi@feae0000 {
- compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
- reg = <0 0xfeae0000 0 0x10000>;
- interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
- clock-names = "iahb", "isfr";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 728>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- dw_hdmi1_in: endpoint {
- remote-endpoint = <&du_out_hdmi1>;
- };
- };
- port@1 {
- reg = <1>;
- };
- port@2 {
- /* HDMI sound */
- reg = <2>;
- };
- };
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a7795";
- reg = <0 0xfeb00000 0 0x80000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>;
- clock-names = "du.0", "du.1", "du.2", "du.3";
- resets = <&cpg 724>, <&cpg 722>;
- reset-names = "du.0", "du.2";
-
- renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>,
- <&vspd0 1>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- du_out_hdmi0: endpoint {
- remote-endpoint = <&dw_hdmi0_in>;
- };
- };
- port@2 {
- reg = <2>;
- du_out_hdmi1: endpoint {
- remote-endpoint = <&dw_hdmi1_in>;
- };
- };
- port@3 {
- reg = <3>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
- };
- };
-
- lvds0: lvds@feb90000 {
- compatible = "renesas,r8a7795-lvds";
- reg = <0 0xfeb90000 0 0x14>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 727>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- sensor1_thermal: sensor1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 0>;
- sustainable-power = <6313>;
-
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor2_thermal: sensor2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 1>;
- sustainable-power = <6313>;
-
- trips {
- sensor2_crit: sensor2-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor3_thermal: sensor3-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 2>;
-
- trips {
- target: trip-point1 {
- temperature = <100000>;
- hysteresis = <1000>;
- type = "passive";
- };
-
- sensor3_crit: sensor3-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&a57_0 2 4>;
- contribution = <1024>;
- };
-
- map1 {
- trip = <&target>;
- cooling-device = <&a53_0 0 2>;
- contribution = <1024>;
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- /* External USB clocks - can be overridden by the board */
- usb3s0_clk: usb3s0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Salvator-X board with R-Car M3-W
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a77960.dtsi"
-#include "salvator-x.dtsi"
-
-/ {
- model = "Renesas Salvator-X board based on r8a77960";
- compatible = "renesas,salvator-x", "renesas,r8a7796";
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-
- memory@600000000 {
- device_type = "memory";
- reg = <0x6 0x00000000 0x0 0x80000000>;
- };
-};
-
-&du {
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>,
- <&versaclock5 1>,
- <&x21_clk>,
- <&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.2",
- "dclkin.0", "dclkin.1", "dclkin.2";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car M3-W
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- * Copyright (C) 2016 Cogent Embedded, Inc.
- */
-
-/dts-v1/;
-#include "r8a77960.dtsi"
-#include "ulcb.dtsi"
-
-/ {
- model = "Renesas M3ULCB board based on r8a77960";
- compatible = "renesas,m3ulcb", "renesas,r8a7796";
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x38000000>;
- };
-
- memory@600000000 {
- device_type = "memory";
- reg = <0x6 0x00000000 0x0 0x40000000>;
- };
-};
-
-&du {
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>,
- <&versaclock5 1>,
- <&versaclock5 3>,
- <&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.2",
- "dclkin.0", "dclkin.1", "dclkin.2";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car M3-W (R8A77960) SoC
- *
- * Copyright (C) 2016-2017 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a7796-sysc.h>
-
-#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
-
-/ {
- compatible = "renesas,r8a7796";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cluster0_opp: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <830000>;
- clock-latency-ns = <300000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <830000>;
- clock-latency-ns = <300000>;
- };
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <830000>;
- clock-latency-ns = <300000>;
- opp-suspend;
- };
- opp-1600000000 {
- opp-hz = /bits/ 64 <1600000000>;
- opp-microvolt = <900000>;
- clock-latency-ns = <300000>;
- };
- opp-1700000000 {
- opp-hz = /bits/ 64 <1700000000>;
- opp-microvolt = <900000>;
- clock-latency-ns = <300000>;
- };
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <960000>;
- clock-latency-ns = <300000>;
- turbo-mode;
- };
- };
-
- cluster1_opp: opp-table-1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- };
- opp-1300000000 {
- opp-hz = /bits/ 64 <1300000000>;
- opp-microvolt = <820000>;
- clock-latency-ns = <300000>;
- turbo-mode;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&a57_0>;
- };
- core1 {
- cpu = <&a57_1>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&a53_0>;
- };
- core1 {
- cpu = <&a53_1>;
- };
- core2 {
- cpu = <&a53_2>;
- };
- core3 {
- cpu = <&a53_3>;
- };
- };
- };
-
- a57_0: cpu@0 {
- compatible = "arm,cortex-a57";
- reg = <0x0>;
- device_type = "cpu";
- power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- dynamic-power-coefficient = <854>;
- clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <1024>;
- #cooling-cells = <2>;
- };
-
- a57_1: cpu@1 {
- compatible = "arm,cortex-a57";
- reg = <0x1>;
- device_type = "cpu";
- power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- capacity-dmips-mhz = <1024>;
- #cooling-cells = <2>;
- };
-
- a53_0: cpu@100 {
- compatible = "arm,cortex-a53";
- reg = <0x100>;
- device_type = "cpu";
- power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_1>;
- #cooling-cells = <2>;
- dynamic-power-coefficient = <277>;
- clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <535>;
- };
-
- a53_1: cpu@101 {
- compatible = "arm,cortex-a53";
- reg = <0x101>;
- device_type = "cpu";
- power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_1>;
- clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <535>;
- };
-
- a53_2: cpu@102 {
- compatible = "arm,cortex-a53";
- reg = <0x102>;
- device_type = "cpu";
- power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_1>;
- clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <535>;
- };
-
- a53_3: cpu@103 {
- compatible = "arm,cortex-a53";
- reg = <0x103>;
- device_type = "cpu";
- power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_1>;
- clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- capacity-dmips-mhz = <535>;
- };
-
- L2_CA57: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A7796_PD_CA57_SCU>;
- cache-unified;
- cache-level = <2>;
- };
-
- L2_CA53: cache-controller-1 {
- compatible = "cache";
- power-domains = <&sysc R8A7796_PD_CA53_SCU>;
- cache-unified;
- cache-level = <2>;
- };
-
- idle-states {
- entry-method = "psci";
-
- CPU_SLEEP_0: cpu-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- local-timer-stop;
- entry-latency-us = <400>;
- exit-latency-us = <500>;
- min-residency-us = <4000>;
- };
-
- CPU_SLEEP_1: cpu-sleep-1 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- local-timer-stop;
- entry-latency-us = <700>;
- exit-latency-us = <700>;
- min-residency-us = <5000>;
- };
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- extalr_clk: extalr {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
- };
-
- pmu_a57 {
- compatible = "arm,cortex-a57-pmu";
- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a57_0>, <&a57_1>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a7796-wdt",
- "renesas,rcar-gen3-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a7796",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a7796",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 29>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a7796",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 15>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a7796",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a7796",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 18>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a7796",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a7796",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 906>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 906>;
- };
-
- gpio7: gpio@e6055800 {
- compatible = "renesas,gpio-r8a7796",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055800 0 0x50>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 224 4>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a7796";
- reg = <0 0xe6060000 0 0x50c>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a7796-cmt0",
- "renesas,rcar-gen3-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 303>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 303>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7796-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 302>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 302>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a7796-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 301>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 301>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a7796-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7796-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7796-rst";
- reg = <0 0xe6160000 0 0x0200>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7796-sysc";
- reg = <0 0xe6180000 0 0x0400>;
- #power-domain-cells = <1>;
- };
-
- tsc: thermal@e6198000 {
- compatible = "renesas,r8a7796-thermal";
- reg = <0 0xe6198000 0 0x100>,
- <0 0xe61a0000 0 0x100>,
- <0 0xe61a8000 0 0x100>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <1>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a7796", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 125>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 125>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a7796", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a7796", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 123>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 123>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a7796", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 122>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 122>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a7796", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 121>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 121>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7796",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>,
- <&dmac2 0x91>, <&dmac2 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7796",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>,
- <&dmac2 0x93>, <&dmac2 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7796",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>,
- <&dmac2 0x95>, <&dmac2 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7796",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- dmas = <&dmac0 0x97>, <&dmac0 0x96>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7796",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- dmas = <&dmac0 0x99>, <&dmac0 0x98>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c5: i2c@e66e0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7796",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e0000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c6: i2c@e66e8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7796",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e8000 0 0x40>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c_dvfs: i2c@e60b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a7796",
- "renesas,rcar-gen3-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- dmas = <&dmac0 0x11>, <&dmac0 0x10>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a7796",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>,
- <&cpg CPG_CORE R8A7796_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>,
- <&dmac2 0x31>, <&dmac2 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a7796",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6550000 0 0x60>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>,
- <&cpg CPG_CORE R8A7796_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x33>, <&dmac1 0x32>,
- <&dmac2 0x33>, <&dmac2 0x32>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a7796",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6560000 0 0x60>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>,
- <&cpg CPG_CORE R8A7796_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x35>, <&dmac1 0x34>,
- <&dmac2 0x35>, <&dmac2 0x34>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a7796",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66a0000 0 0x60>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A7796_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x37>, <&dmac0 0x36>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- hscif4: serial@e66b0000 {
- compatible = "renesas,hscif-r8a7796",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66b0000 0 0x60>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A7796_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x38>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 516>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a7796",
- "renesas,rcar-gen3-usbhs";
- reg = <0 0xe6590000 0 0x200>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- renesas,buswait = <11>;
- phys = <&usb2_phy0 3>;
- phy-names = "usb";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 704>, <&cpg 703>;
- status = "disabled";
- };
-
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a7796-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a7796-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb3_phy0: usb-phy@e65ee000 {
- compatible = "renesas,r8a7796-usb3-phy",
- "renesas,rcar-gen3-usb3-phy";
- reg = <0 0xe65ee000 0 0x90>;
- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
- <&usb_extal_clk>;
- clock-names = "usb3-if", "usb3s_clk", "usb_extal";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- arm_cc630p: crypto@e6601000 {
- compatible = "arm,cryptocell-630p-ree";
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x0 0xe6601000 0 0x1000>;
- clocks = <&cpg CPG_MOD 229>;
- resets = <&cpg 229>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a7796",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x10000>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
- };
-
- dmac1: dma-controller@e7300000 {
- compatible = "renesas,dmac-r8a7796",
- "renesas,rcar-dmac";
- reg = <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
- };
-
- dmac2: dma-controller@e7310000 {
- compatible = "renesas,dmac-r8a7796",
- "renesas,rcar-dmac";
- reg = <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 217>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 217>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
- };
-
- ipmmu_ds0: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a7796";
- reg = <0 0xe6740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds1: iommu@e7740000 {
- compatible = "renesas,ipmmu-r8a7796";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 1>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_hc: iommu@e6570000 {
- compatible = "renesas,ipmmu-r8a7796";
- reg = <0 0xe6570000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 2>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ir: iommu@ff8b0000 {
- compatible = "renesas,ipmmu-r8a7796";
- reg = <0 0xff8b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 3>;
- power-domains = <&sysc R8A7796_PD_A3IR>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@e67b0000 {
- compatible = "renesas,ipmmu-r8a7796";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mp: iommu@ec670000 {
- compatible = "renesas,ipmmu-r8a7796";
- reg = <0 0xec670000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 4>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv0: iommu@fd800000 {
- compatible = "renesas,ipmmu-r8a7796";
- reg = <0 0xfd800000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 5>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv1: iommu@fd950000 {
- compatible = "renesas,ipmmu-r8a7796";
- reg = <0 0xfd950000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 6>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_rt: iommu@ffc80000 {
- compatible = "renesas,ipmmu-r8a7796";
- reg = <0 0xffc80000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 7>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: iommu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a7796";
- reg = <0 0xfe6b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 8>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@febd0000 {
- compatible = "renesas,ipmmu-r8a7796";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 9>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7796",
- "renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- iommus = <&ipmmu_ds0 16>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can0: can@e6c30000 {
- compatible = "renesas,can-r8a7796",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c30000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A7796_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6c38000 {
- compatible = "renesas,can-r8a7796",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c38000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A7796_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a7796-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A7796_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 914>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm5: pwm@e6e35000 {
- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
- reg = <0 0xe6e35000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm6: pwm@e6e36000 {
- compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
- reg = <0 0xe6e36000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a7796",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE R8A7796_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>,
- <&dmac2 0x51>, <&dmac2 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a7796",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE R8A7796_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>,
- <&dmac2 0x53>, <&dmac2 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scif2: serial@e6e88000 {
- compatible = "renesas,scif-r8a7796",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e88000 0 64>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>,
- <&cpg CPG_CORE R8A7796_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x13>, <&dmac1 0x12>,
- <&dmac2 0x13>, <&dmac2 0x12>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 310>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a7796",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE R8A7796_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x57>, <&dmac0 0x56>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a7796",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE R8A7796_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x59>, <&dmac0 0x58>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scif5: serial@e6f30000 {
- compatible = "renesas,scif-r8a7796",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6f30000 0 64>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>,
- <&cpg CPG_CORE R8A7796_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
- <&dmac2 0x5b>, <&dmac2 0x5a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- tpu: pwm@e6e80000 {
- compatible = "renesas,tpu-r8a7796", "renesas,tpu";
- reg = <0 0xe6e80000 0 0x148>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 304>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 304>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a7796",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6e90000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
- dmas = <&dmac1 0x41>, <&dmac1 0x40>,
- <&dmac2 0x41>, <&dmac2 0x40>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a7796",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
- dmas = <&dmac1 0x43>, <&dmac1 0x42>,
- <&dmac2 0x43>, <&dmac2 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 210>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a7796",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
- dmas = <&dmac0 0x45>, <&dmac0 0x44>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 209>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a7796",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x47>, <&dmac0 0x46>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7796";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- renesas,id = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin0csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin0>;
- };
- vin0csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin0>;
- };
- };
- };
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a7796";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- renesas,id = <1>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin1csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin1>;
- };
- vin1csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin1>;
- };
- };
- };
- };
-
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a7796";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- renesas,id = <2>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin2csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin2>;
- };
- vin2csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin2>;
- };
- };
- };
- };
-
- vin3: video@e6ef3000 {
- compatible = "renesas,vin-r8a7796";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- renesas,id = <3>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin3csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin3>;
- };
- vin3csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin3>;
- };
- };
- };
- };
-
- vin4: video@e6ef4000 {
- compatible = "renesas,vin-r8a7796";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 807>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 807>;
- renesas,id = <4>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin4csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin4>;
- };
- vin4csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin4>;
- };
- };
- };
- };
-
- vin5: video@e6ef5000 {
- compatible = "renesas,vin-r8a7796";
- reg = <0 0xe6ef5000 0 0x1000>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 806>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 806>;
- renesas,id = <5>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin5csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin5>;
- };
- vin5csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin5>;
- };
- };
- };
- };
-
- vin6: video@e6ef6000 {
- compatible = "renesas,vin-r8a7796";
- reg = <0 0xe6ef6000 0 0x1000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 805>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 805>;
- renesas,id = <6>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin6csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin6>;
- };
- vin6csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin6>;
- };
- };
- };
- };
-
- vin7: video@e6ef7000 {
- compatible = "renesas,vin-r8a7796";
- reg = <0 0xe6ef7000 0 0x1000>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 804>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 804>;
- renesas,id = <7>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin7csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin7>;
- };
- vin7csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin7>;
- };
- };
- };
- };
-
- drif00: rif@e6f40000 {
- compatible = "renesas,r8a7796-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f40000 0 0x64>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 515>;
- clock-names = "fck";
- dmas = <&dmac1 0x20>, <&dmac2 0x20>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 515>;
- renesas,bonding = <&drif01>;
- status = "disabled";
- };
-
- drif01: rif@e6f50000 {
- compatible = "renesas,r8a7796-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f50000 0 0x64>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 514>;
- clock-names = "fck";
- dmas = <&dmac1 0x22>, <&dmac2 0x22>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 514>;
- renesas,bonding = <&drif00>;
- status = "disabled";
- };
-
- drif10: rif@e6f60000 {
- compatible = "renesas,r8a7796-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f60000 0 0x64>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 513>;
- clock-names = "fck";
- dmas = <&dmac1 0x24>, <&dmac2 0x24>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 513>;
- renesas,bonding = <&drif11>;
- status = "disabled";
- };
-
- drif11: rif@e6f70000 {
- compatible = "renesas,r8a7796-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f70000 0 0x64>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 512>;
- clock-names = "fck";
- dmas = <&dmac1 0x26>, <&dmac2 0x26>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 512>;
- renesas,bonding = <&drif10>;
- status = "disabled";
- };
-
- drif20: rif@e6f80000 {
- compatible = "renesas,r8a7796-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f80000 0 0x64>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 511>;
- clock-names = "fck";
- dmas = <&dmac1 0x28>, <&dmac2 0x28>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 511>;
- renesas,bonding = <&drif21>;
- status = "disabled";
- };
-
- drif21: rif@e6f90000 {
- compatible = "renesas,r8a7796-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f90000 0 0x64>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 510>;
- clock-names = "fck";
- dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 510>;
- renesas,bonding = <&drif20>;
- status = "disabled";
- };
-
- drif30: rif@e6fa0000 {
- compatible = "renesas,r8a7796-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6fa0000 0 0x64>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 509>;
- clock-names = "fck";
- dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 509>;
- renesas,bonding = <&drif31>;
- status = "disabled";
- };
-
- drif31: rif@e6fb0000 {
- compatible = "renesas,r8a7796-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6fb0000 0 0x64>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 508>;
- clock-names = "fck";
- dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 508>;
- renesas,bonding = <&drif30>;
- status = "disabled";
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- /*
- * #clock-cells is required for audio_clkout0/1/2/3
- *
- * clkout : #clock-cells = <0>; <&rcar_sound>;
- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A7796_CLK_S0D4>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6",
- "src.5", "src.4", "src.3", "src.2",
- "src.1", "src.0",
- "mix.1", "mix.0",
- "ctu.1", "ctu.0",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>,
- <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>,
- <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0";
- status = "disabled";
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma1 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma1 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>;
- dma-names = "rx", "tx";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>;
- dma-names = "rx", "tx";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>;
- dma-names = "rx", "tx";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>;
- dma-names = "rx", "tx";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>;
- dma-names = "rx", "tx";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>;
- dma-names = "rx", "tx";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>;
- dma-names = "rx", "tx";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>;
- dma-names = "rx", "tx";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>;
- dma-names = "rx", "tx";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssiu {
- ssiu00: ssiu-0 {
- dmas = <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx";
- };
- ssiu01: ssiu-1 {
- dmas = <&audma0 0x35>, <&audma1 0x36>;
- dma-names = "rx", "tx";
- };
- ssiu02: ssiu-2 {
- dmas = <&audma0 0x37>, <&audma1 0x38>;
- dma-names = "rx", "tx";
- };
- ssiu03: ssiu-3 {
- dmas = <&audma0 0x47>, <&audma1 0x48>;
- dma-names = "rx", "tx";
- };
- ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
- dma-names = "rx", "tx";
- };
- ssiu05: ssiu-5 {
- dmas = <&audma0 0x43>, <&audma1 0x44>;
- dma-names = "rx", "tx";
- };
- ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
- dma-names = "rx", "tx";
- };
- ssiu07: ssiu-7 {
- dmas = <&audma0 0x53>, <&audma1 0x54>;
- dma-names = "rx", "tx";
- };
- ssiu10: ssiu-8 {
- dmas = <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx";
- };
- ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
- dma-names = "rx", "tx";
- };
- ssiu12: ssiu-10 {
- dmas = <&audma0 0x57>, <&audma1 0x58>;
- dma-names = "rx", "tx";
- };
- ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
- dma-names = "rx", "tx";
- };
- ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
- dma-names = "rx", "tx";
- };
- ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
- dma-names = "rx", "tx";
- };
- ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
- dma-names = "rx", "tx";
- };
- ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
- dma-names = "rx", "tx";
- };
- ssiu20: ssiu-16 {
- dmas = <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx";
- };
- ssiu21: ssiu-17 {
- dmas = <&audma0 0x67>, <&audma1 0x68>;
- dma-names = "rx", "tx";
- };
- ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
- dma-names = "rx", "tx";
- };
- ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
- dma-names = "rx", "tx";
- };
- ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
- dma-names = "rx", "tx";
- };
- ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
- dma-names = "rx", "tx";
- };
- ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
- dma-names = "rx", "tx";
- };
- ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
- dma-names = "rx", "tx";
- };
- ssiu30: ssiu-24 {
- dmas = <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx";
- };
- ssiu31: ssiu-25 {
- dmas = <&audma0 0x21>, <&audma1 0x22>;
- dma-names = "rx", "tx";
- };
- ssiu32: ssiu-26 {
- dmas = <&audma0 0x23>, <&audma1 0x24>;
- dma-names = "rx", "tx";
- };
- ssiu33: ssiu-27 {
- dmas = <&audma0 0x25>, <&audma1 0x26>;
- dma-names = "rx", "tx";
- };
- ssiu34: ssiu-28 {
- dmas = <&audma0 0x27>, <&audma1 0x28>;
- dma-names = "rx", "tx";
- };
- ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
- dma-names = "rx", "tx";
- };
- ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
- dma-names = "rx", "tx";
- };
- ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
- dma-names = "rx", "tx";
- };
- ssiu40: ssiu-32 {
- dmas = <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx";
- };
- ssiu41: ssiu-33 {
- dmas = <&audma0 0x17>, <&audma1 0x18>;
- dma-names = "rx", "tx";
- };
- ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
- dma-names = "rx", "tx";
- };
- ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
- dma-names = "rx", "tx";
- };
- ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
- dma-names = "rx", "tx";
- };
- ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
- dma-names = "rx", "tx";
- };
- ssiu46: ssiu-38 {
- dmas = <&audma0 0x31>, <&audma1 0x32>;
- dma-names = "rx", "tx";
- };
- ssiu47: ssiu-39 {
- dmas = <&audma0 0x33>, <&audma1 0x34>;
- dma-names = "rx", "tx";
- };
- ssiu50: ssiu-40 {
- dmas = <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx";
- };
- ssiu60: ssiu-41 {
- dmas = <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx";
- };
- ssiu70: ssiu-42 {
- dmas = <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx";
- };
- ssiu80: ssiu-43 {
- dmas = <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx";
- };
- ssiu90: ssiu-44 {
- dmas = <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx";
- };
- ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
- dma-names = "rx", "tx";
- };
- ssiu92: ssiu-46 {
- dmas = <&audma0 0x81>, <&audma1 0x82>;
- dma-names = "rx", "tx";
- };
- ssiu93: ssiu-47 {
- dmas = <&audma0 0x83>, <&audma1 0x84>;
- dma-names = "rx", "tx";
- };
- ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
- dma-names = "rx", "tx";
- };
- ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
- dma-names = "rx", "tx";
- };
- ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
- dma-names = "rx", "tx";
- };
- ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
- dma-names = "rx", "tx";
- };
- };
- };
-
- mlp: mlp@ec520000 {
- compatible = "renesas,r8a7796-mlp",
- "renesas,rcar-gen3-mlp";
- reg = <0 0xec520000 0 0x800>;
- interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 802>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 802>;
- status = "disabled";
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a7796",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
- <&ipmmu_mp 2>, <&ipmmu_mp 3>,
- <&ipmmu_mp 4>, <&ipmmu_mp 5>,
- <&ipmmu_mp 6>, <&ipmmu_mp 7>,
- <&ipmmu_mp 8>, <&ipmmu_mp 9>,
- <&ipmmu_mp 10>, <&ipmmu_mp 11>,
- <&ipmmu_mp 12>, <&ipmmu_mp 13>,
- <&ipmmu_mp 14>, <&ipmmu_mp 15>;
- };
-
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a7796",
- "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
- <&ipmmu_mp 18>, <&ipmmu_mp 19>,
- <&ipmmu_mp 20>, <&ipmmu_mp 21>,
- <&ipmmu_mp 22>, <&ipmmu_mp 23>,
- <&ipmmu_mp 24>, <&ipmmu_mp 25>,
- <&ipmmu_mp 26>, <&ipmmu_mp 27>,
- <&ipmmu_mp 28>, <&ipmmu_mp 29>,
- <&ipmmu_mp 30>, <&ipmmu_mp 31>;
- };
-
- xhci0: usb@ee000000 {
- compatible = "renesas,xhci-r8a7796",
- "renesas,rcar-gen3-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- usb3_peri0: usb@ee020000 {
- compatible = "renesas,r8a7796-usb3-peri",
- "renesas,rcar-gen3-usb3-peri";
- reg = <0 0xee020000 0 0x400>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- ohci0: usb@ee080000 {
- compatible = "generic-ohci";
- reg = <0 0xee080000 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ohci1: usb@ee0a0000 {
- compatible = "generic-ohci";
- reg = <0 0xee0a0000 0 0x100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>;
- phys = <&usb2_phy1 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- ehci0: usb@ee080100 {
- compatible = "generic-ehci";
- reg = <0 0xee080100 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 2>;
- phy-names = "usb";
- companion = <&ohci0>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ehci1: usb@ee0a0100 {
- compatible = "generic-ehci";
- reg = <0 0xee0a0100 0 0x100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>;
- phys = <&usb2_phy1 2>;
- phy-names = "usb";
- companion = <&ohci1>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- usb2_phy0: usb-phy@ee080200 {
- compatible = "renesas,usb2-phy-r8a7796",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee080200 0 0x700>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- usb2_phy1: usb-phy@ee0a0200 {
- compatible = "renesas,usb2-phy-r8a7796",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee0a0200 0 0x700>;
- clocks = <&cpg CPG_MOD 702>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a7796",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee100000 0 0x2000>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- iommus = <&ipmmu_ds1 32>;
- status = "disabled";
- };
-
- sdhi1: mmc@ee120000 {
- compatible = "renesas,sdhi-r8a7796",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee120000 0 0x2000>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 313>;
- iommus = <&ipmmu_ds1 33>;
- status = "disabled";
- };
-
- sdhi2: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a7796",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- iommus = <&ipmmu_ds1 34>;
- status = "disabled";
- };
-
- sdhi3: mmc@ee160000 {
- compatible = "renesas,sdhi-r8a7796",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee160000 0 0x2000>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- iommus = <&ipmmu_ds1 35>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a7796-rpc-if",
- "renesas,rcar-gen3-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x04000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1010000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1010000 0 0x1000>,
- <0x0 0xf1020000 0 0x20000>,
- <0x0 0xf1040000 0 0x20000>,
- <0x0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- pciec0: pcie@fe000000 {
- compatible = "renesas,pcie-r8a7796",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- iommu-map = <0 &ipmmu_hc 0 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- pciec1: pcie@ee800000 {
- compatible = "renesas,pcie-r8a7796",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xee800000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- iommu-map = <0 &ipmmu_hc 1 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- imr-lx4@fe860000 {
- compatible = "renesas,r8a7796-imr-lx4",
- "renesas,imr-lx4";
- reg = <0 0xfe860000 0 0x2000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 823>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 823>;
- };
-
- imr-lx4@fe870000 {
- compatible = "renesas,r8a7796-imr-lx4",
- "renesas,imr-lx4";
- reg = <0 0xfe870000 0 0x2000>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 822>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 822>;
- };
-
- fdp1@fe940000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe940000 0 0x2400>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 119>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 119>;
- renesas,fcp = <&fcpf0>;
- };
-
- fcpf0: fcp@fe950000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe950000 0 0x200>;
- clocks = <&cpg CPG_MOD 615>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 615>;
- };
-
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 607>;
- };
-
- fcpvi0: fcp@fe9af000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9af000 0 0x200>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 611>;
- iommus = <&ipmmu_vc0 19>;
- };
-
- fcpvd0: fcp@fea27000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea27000 0 0x200>;
- clocks = <&cpg CPG_MOD 603>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 603>;
- iommus = <&ipmmu_vi0 8>;
- };
-
- fcpvd1: fcp@fea2f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea2f000 0 0x200>;
- clocks = <&cpg CPG_MOD 602>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 602>;
- iommus = <&ipmmu_vi0 9>;
- };
-
- fcpvd2: fcp@fea37000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea37000 0 0x200>;
- clocks = <&cpg CPG_MOD 601>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 601>;
- iommus = <&ipmmu_vi0 10>;
- };
-
- vspb: vsp@fe960000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe960000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 626>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 626>;
-
- renesas,fcp = <&fcpvb0>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x5000>;
- interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
-
- renesas,fcp = <&fcpvd0>;
- };
-
- vspd1: vsp@fea28000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x5000>;
- interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 622>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 622>;
-
- renesas,fcp = <&fcpvd1>;
- };
-
- vspd2: vsp@fea30000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea30000 0 0x5000>;
- interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 621>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 621>;
-
- renesas,fcp = <&fcpvd2>;
- };
-
- vspi0: vsp@fe9a0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9a0000 0 0x8000>;
- interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 631>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 631>;
-
- renesas,fcp = <&fcpvi0>;
- };
-
- cmm0: cmm@fea40000 {
- compatible = "renesas,r8a7796-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea40000 0 0x1000>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 711>;
- resets = <&cpg 711>;
- };
-
- cmm1: cmm@fea50000 {
- compatible = "renesas,r8a7796-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea50000 0 0x1000>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 710>;
- resets = <&cpg 710>;
- };
-
- cmm2: cmm@fea60000 {
- compatible = "renesas,r8a7796-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea60000 0 0x1000>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 709>;
- resets = <&cpg 709>;
- };
-
- csi20: csi2@fea80000 {
- compatible = "renesas,r8a7796-csi2";
- reg = <0 0xfea80000 0 0x10000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi20vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi20>;
- };
- csi20vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi20>;
- };
- csi20vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi20>;
- };
- csi20vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi20>;
- };
- csi20vin4: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&vin4csi20>;
- };
- csi20vin5: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&vin5csi20>;
- };
- csi20vin6: endpoint@6 {
- reg = <6>;
- remote-endpoint = <&vin6csi20>;
- };
- csi20vin7: endpoint@7 {
- reg = <7>;
- remote-endpoint = <&vin7csi20>;
- };
- };
- };
- };
-
- csi40: csi2@feaa0000 {
- compatible = "renesas,r8a7796-csi2";
- reg = <0 0xfeaa0000 0 0x10000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi40vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi40>;
- };
- csi40vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi40>;
- };
- csi40vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi40>;
- };
- csi40vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi40>;
- };
- csi40vin4: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&vin4csi40>;
- };
- csi40vin5: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&vin5csi40>;
- };
- csi40vin6: endpoint@6 {
- reg = <6>;
- remote-endpoint = <&vin6csi40>;
- };
- csi40vin7: endpoint@7 {
- reg = <7>;
- remote-endpoint = <&vin7csi40>;
- };
- };
-
- };
- };
-
- hdmi0: hdmi@fead0000 {
- compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
- reg = <0 0xfead0000 0 0x10000>;
- interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
- clock-names = "iahb", "isfr";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 729>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- dw_hdmi0_in: endpoint {
- remote-endpoint = <&du_out_hdmi0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- port@2 {
- /* HDMI sound */
- reg = <2>;
- };
- };
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a7796";
- reg = <0 0xfeb00000 0 0x70000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>;
- clock-names = "du.0", "du.1", "du.2";
- resets = <&cpg 724>, <&cpg 722>;
- reset-names = "du.0", "du.2";
-
- renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- du_out_hdmi0: endpoint {
- remote-endpoint = <&dw_hdmi0_in>;
- };
- };
- port@2 {
- reg = <2>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
- };
- };
-
- lvds0: lvds@feb90000 {
- compatible = "renesas,r8a7796-lvds";
- reg = <0 0xfeb90000 0 0x14>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 727>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- sensor1_thermal: sensor1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 0>;
- sustainable-power = <3874>;
-
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor2_thermal: sensor2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 1>;
- sustainable-power = <3874>;
-
- trips {
- sensor2_crit: sensor2-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor3_thermal: sensor3-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 2>;
- sustainable-power = <3874>;
-
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&a57_0 2 4>;
- contribution = <1024>;
- };
- map1 {
- trip = <&target>;
- cooling-device = <&a53_0 0 2>;
- contribution = <1024>;
- };
- };
- trips {
- target: trip-point1 {
- temperature = <100000>;
- hysteresis = <1000>;
- type = "passive";
- };
-
- sensor3_crit: sensor3-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- /* External USB clocks - can be overridden by the board */
- usb3s0_clk: usb3s0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Salvator-X board with R-Car M3-N
- *
- * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
- */
-
-/dts-v1/;
-#include "r8a77965.dtsi"
-#include "salvator-x.dtsi"
-
-/ {
- model = "Renesas Salvator-X board based on r8a77965";
- compatible = "renesas,salvator-x", "renesas,r8a77965";
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-};
-
-&du {
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 721>,
- <&versaclock5 1>,
- <&x21_clk>,
- <&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.3",
- "dclkin.0", "dclkin.1", "dclkin.3";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board with R-Car M3-N
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
- */
-
-/dts-v1/;
-#include "r8a77965.dtsi"
-#include "ulcb.dtsi"
-
-/ {
- model = "Renesas M3NULCB board based on r8a77965";
- compatible = "renesas,m3nulcb", "renesas,r8a77965";
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-};
-
-&du {
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 721>,
- <&versaclock5 1>,
- <&versaclock5 3>,
- <&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.3",
- "dclkin.0", "dclkin.1", "dclkin.3";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car M3-N (R8A77965) SoC
- *
- * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
- *
- * Based on r8a7796.dtsi
- * Copyright (C) 2016 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/clock/r8a77965-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a77965-sysc.h>
-
-#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4
-
-#define SOC_HAS_SATA
-
-/ {
- compatible = "renesas,r8a77965";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cluster0_opp: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <830000>;
- clock-latency-ns = <300000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <830000>;
- clock-latency-ns = <300000>;
- };
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <830000>;
- clock-latency-ns = <300000>;
- opp-suspend;
- };
- opp-1600000000 {
- opp-hz = /bits/ 64 <1600000000>;
- opp-microvolt = <900000>;
- clock-latency-ns = <300000>;
- };
- opp-1700000000 {
- opp-hz = /bits/ 64 <1700000000>;
- opp-microvolt = <900000>;
- clock-latency-ns = <300000>;
- };
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <960000>;
- clock-latency-ns = <300000>;
- turbo-mode;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- a57_0: cpu@0 {
- compatible = "arm,cortex-a57";
- reg = <0x0>;
- device_type = "cpu";
- power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- #cooling-cells = <2>;
- dynamic-power-coefficient = <854>;
- clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- a57_1: cpu@1 {
- compatible = "arm,cortex-a57";
- reg = <0x1>;
- device_type = "cpu";
- power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
- next-level-cache = <&L2_CA57>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- L2_CA57: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A77965_PD_CA57_SCU>;
- cache-unified;
- cache-level = <2>;
- };
-
- idle-states {
- entry-method = "psci";
-
- CPU_SLEEP_0: cpu-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- local-timer-stop;
- entry-latency-us = <400>;
- exit-latency-us = <500>;
- min-residency-us = <4000>;
- };
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- extalr_clk: extalr {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- pmu_a57 {
- compatible = "arm,cortex-a57-pmu";
- interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a57_0>,
- <&a57_1>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a77965-wdt",
- "renesas,rcar-gen3-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a77965",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a77965",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 29>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a77965",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 15>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a77965",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a77965",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 18>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a77965",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a77965",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 906>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 906>;
- };
-
- gpio7: gpio@e6055800 {
- compatible = "renesas,gpio-r8a77965",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055800 0 0x50>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 224 4>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 905>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 905>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a77965";
- reg = <0 0xe6060000 0 0x50c>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a77965-cmt0",
- "renesas,rcar-gen3-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 303>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 303>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a77965-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 302>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 302>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a77965-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 301>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 301>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a77965-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a77965-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a77965-rst";
- reg = <0 0xe6160000 0 0x0200>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a77965-sysc";
- reg = <0 0xe6180000 0 0x0400>;
- #power-domain-cells = <1>;
- };
-
- tsc: thermal@e6198000 {
- compatible = "renesas,r8a77965-thermal";
- reg = <0 0xe6198000 0 0x100>,
- <0 0xe61a0000 0 0x100>,
- <0 0xe61a8000 0 0x100>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <1>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a77965", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 125>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 125>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a77965", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a77965", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 123>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 123>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a77965", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 122>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 122>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a77965", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 121>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 121>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77965",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>,
- <&dmac2 0x91>, <&dmac2 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77965",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>,
- <&dmac2 0x93>, <&dmac2 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77965",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>,
- <&dmac2 0x95>, <&dmac2 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77965",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- dmas = <&dmac0 0x97>, <&dmac0 0x96>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77965",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- dmas = <&dmac0 0x99>, <&dmac0 0x98>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c5: i2c@e66e0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77965",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e0000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c6: i2c@e66e8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77965",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e8000 0 0x40>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c_dvfs: i2c@e60b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a77965",
- "renesas,rcar-gen3-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- dmas = <&dmac0 0x11>, <&dmac0 0x10>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a77965",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>,
- <&cpg CPG_CORE R8A77965_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>,
- <&dmac2 0x31>, <&dmac2 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a77965",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6550000 0 0x60>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>,
- <&cpg CPG_CORE R8A77965_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x33>, <&dmac1 0x32>,
- <&dmac2 0x33>, <&dmac2 0x32>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a77965",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6560000 0 0x60>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>,
- <&cpg CPG_CORE R8A77965_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x35>, <&dmac1 0x34>,
- <&dmac2 0x35>, <&dmac2 0x34>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a77965",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66a0000 0 0x60>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A77965_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x37>, <&dmac0 0x36>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- hscif4: serial@e66b0000 {
- compatible = "renesas,hscif-r8a77965",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66b0000 0 0x60>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A77965_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x38>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 516>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a77965",
- "renesas,rcar-gen3-usbhs";
- reg = <0 0xe6590000 0 0x200>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- renesas,buswait = <11>;
- phys = <&usb2_phy0 3>;
- phy-names = "usb";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 704>, <&cpg 703>;
- status = "disabled";
- };
-
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a77965-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a77965-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb3_phy0: usb-phy@e65ee000 {
- compatible = "renesas,r8a77965-usb3-phy",
- "renesas,rcar-gen3-usb3-phy";
- reg = <0 0xe65ee000 0 0x90>;
- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
- <&usb_extal_clk>;
- clock-names = "usb3-if", "usb3s_clk", "usb_extal";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- arm_cc630p: crypto@e6601000 {
- compatible = "arm,cryptocell-630p-ree";
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x0 0xe6601000 0 0x1000>;
- clocks = <&cpg CPG_MOD 229>;
- resets = <&cpg 229>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a77965",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x10000>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
- };
-
- dmac1: dma-controller@e7300000 {
- compatible = "renesas,dmac-r8a77965",
- "renesas,rcar-dmac";
- reg = <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
- };
-
- dmac2: dma-controller@e7310000 {
- compatible = "renesas,dmac-r8a77965",
- "renesas,rcar-dmac";
- reg = <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 217>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 217>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
- };
-
- ipmmu_ds0: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a77965";
- reg = <0 0xe6740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds1: iommu@e7740000 {
- compatible = "renesas,ipmmu-r8a77965";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 1>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_hc: iommu@e6570000 {
- compatible = "renesas,ipmmu-r8a77965";
- reg = <0 0xe6570000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 2>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@e67b0000 {
- compatible = "renesas,ipmmu-r8a77965";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mp: iommu@ec670000 {
- compatible = "renesas,ipmmu-r8a77965";
- reg = <0 0xec670000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 4>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv0: iommu@fd800000 {
- compatible = "renesas,ipmmu-r8a77965";
- reg = <0 0xfd800000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 6>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_rt: iommu@ffc80000 {
- compatible = "renesas,ipmmu-r8a77965";
- reg = <0 0xffc80000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 10>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: iommu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a77965";
- reg = <0 0xfe6b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 12>;
- power-domains = <&sysc R8A77965_PD_A3VC>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@febd0000 {
- compatible = "renesas,ipmmu-r8a77965";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 14>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vp0: iommu@fe990000 {
- compatible = "renesas,ipmmu-r8a77965";
- reg = <0 0xfe990000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 16>;
- power-domains = <&sysc R8A77965_PD_A3VP>;
- #iommu-cells = <1>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a77965",
- "renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- iommus = <&ipmmu_ds0 16>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can0: can@e6c30000 {
- compatible = "renesas,can-r8a77965",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c30000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A77965_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6c38000 {
- compatible = "renesas,can-r8a77965",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c38000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A77965_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a77965-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A77965_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 914>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm5: pwm@e6e35000 {
- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
- reg = <0 0xe6e35000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- pwm6: pwm@e6e36000 {
- compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
- reg = <0 0xe6e36000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- resets = <&cpg 523>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a77965",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE R8A77965_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>,
- <&dmac2 0x51>, <&dmac2 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a77965",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE R8A77965_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>,
- <&dmac2 0x53>, <&dmac2 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scif2: serial@e6e88000 {
- compatible = "renesas,scif-r8a77965",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e88000 0 64>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>,
- <&cpg CPG_CORE R8A77965_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x13>, <&dmac1 0x12>,
- <&dmac2 0x13>, <&dmac2 0x12>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 310>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a77965",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE R8A77965_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x57>, <&dmac0 0x56>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a77965",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE R8A77965_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x59>, <&dmac0 0x58>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scif5: serial@e6f30000 {
- compatible = "renesas,scif-r8a77965",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6f30000 0 64>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>,
- <&cpg CPG_CORE R8A77965_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
- <&dmac2 0x5b>, <&dmac2 0x5a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- tpu: pwm@e6e80000 {
- compatible = "renesas,tpu-r8a77965", "renesas,tpu";
- reg = <0 0xe6e80000 0 0x148>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 304>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 304>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a77965",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6e90000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
- dmas = <&dmac1 0x41>, <&dmac1 0x40>,
- <&dmac2 0x41>, <&dmac2 0x40>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a77965",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
- dmas = <&dmac1 0x43>, <&dmac1 0x42>,
- <&dmac2 0x43>, <&dmac2 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 210>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a77965",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
- dmas = <&dmac0 0x45>, <&dmac0 0x44>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 209>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a77965",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x47>, <&dmac0 0x46>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a77965";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- renesas,id = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin0csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin0>;
- };
- vin0csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin0>;
- };
- };
- };
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a77965";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- renesas,id = <1>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin1csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin1>;
- };
- vin1csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin1>;
- };
- };
- };
- };
-
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a77965";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- renesas,id = <2>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin2csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin2>;
- };
- vin2csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin2>;
- };
- };
- };
- };
-
- vin3: video@e6ef3000 {
- compatible = "renesas,vin-r8a77965";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- renesas,id = <3>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin3csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin3>;
- };
- vin3csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin3>;
- };
- };
- };
- };
-
- vin4: video@e6ef4000 {
- compatible = "renesas,vin-r8a77965";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 807>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 807>;
- renesas,id = <4>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin4csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin4>;
- };
- vin4csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin4>;
- };
- };
- };
- };
-
- vin5: video@e6ef5000 {
- compatible = "renesas,vin-r8a77965";
- reg = <0 0xe6ef5000 0 0x1000>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 806>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 806>;
- renesas,id = <5>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin5csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin5>;
- };
- vin5csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin5>;
- };
- };
- };
- };
-
- vin6: video@e6ef6000 {
- compatible = "renesas,vin-r8a77965";
- reg = <0 0xe6ef6000 0 0x1000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 805>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 805>;
- renesas,id = <6>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin6csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin6>;
- };
- vin6csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin6>;
- };
- };
- };
- };
-
- vin7: video@e6ef7000 {
- compatible = "renesas,vin-r8a77965";
- reg = <0 0xe6ef7000 0 0x1000>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 804>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 804>;
- renesas,id = <7>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin7csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi20vin7>;
- };
- vin7csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin7>;
- };
- };
- };
- };
-
- drif00: rif@e6f40000 {
- compatible = "renesas,r8a77965-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f40000 0 0x84>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 515>;
- clock-names = "fck";
- dmas = <&dmac1 0x20>, <&dmac2 0x20>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 515>;
- renesas,bonding = <&drif01>;
- status = "disabled";
- };
-
- drif01: rif@e6f50000 {
- compatible = "renesas,r8a77965-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f50000 0 0x84>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 514>;
- clock-names = "fck";
- dmas = <&dmac1 0x22>, <&dmac2 0x22>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 514>;
- renesas,bonding = <&drif00>;
- status = "disabled";
- };
-
- drif10: rif@e6f60000 {
- compatible = "renesas,r8a77965-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f60000 0 0x84>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 513>;
- clock-names = "fck";
- dmas = <&dmac1 0x24>, <&dmac2 0x24>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 513>;
- renesas,bonding = <&drif11>;
- status = "disabled";
- };
-
- drif11: rif@e6f70000 {
- compatible = "renesas,r8a77965-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f70000 0 0x84>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 512>;
- clock-names = "fck";
- dmas = <&dmac1 0x26>, <&dmac2 0x26>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 512>;
- renesas,bonding = <&drif10>;
- status = "disabled";
- };
-
- drif20: rif@e6f80000 {
- compatible = "renesas,r8a77965-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f80000 0 0x84>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 511>;
- clock-names = "fck";
- dmas = <&dmac1 0x28>, <&dmac2 0x28>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 511>;
- renesas,bonding = <&drif21>;
- status = "disabled";
- };
-
- drif21: rif@e6f90000 {
- compatible = "renesas,r8a77965-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f90000 0 0x84>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 510>;
- clock-names = "fck";
- dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 510>;
- renesas,bonding = <&drif20>;
- status = "disabled";
- };
-
- drif30: rif@e6fa0000 {
- compatible = "renesas,r8a77965-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6fa0000 0 0x84>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 509>;
- clock-names = "fck";
- dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 509>;
- renesas,bonding = <&drif31>;
- status = "disabled";
- };
-
- drif31: rif@e6fb0000 {
- compatible = "renesas,r8a77965-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6fb0000 0 0x84>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 508>;
- clock-names = "fck";
- dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 508>;
- renesas,bonding = <&drif30>;
- status = "disabled";
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- /*
- * #clock-cells is required for audio_clkout0/1/2/3
- *
- * clkout : #clock-cells = <0>; <&rcar_sound>;
- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A77965_CLK_S0D4>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6",
- "src.5", "src.4", "src.3", "src.2",
- "src.1", "src.0",
- "mix.1", "mix.0",
- "ctu.1", "ctu.0",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>,
- <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>,
- <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0";
- status = "disabled";
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma1 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma1 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssiu {
- ssiu00: ssiu-0 {
- dmas = <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx";
- };
- ssiu01: ssiu-1 {
- dmas = <&audma0 0x35>, <&audma1 0x36>;
- dma-names = "rx", "tx";
- };
- ssiu02: ssiu-2 {
- dmas = <&audma0 0x37>, <&audma1 0x38>;
- dma-names = "rx", "tx";
- };
- ssiu03: ssiu-3 {
- dmas = <&audma0 0x47>, <&audma1 0x48>;
- dma-names = "rx", "tx";
- };
- ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
- dma-names = "rx", "tx";
- };
- ssiu05: ssiu-5 {
- dmas = <&audma0 0x43>, <&audma1 0x44>;
- dma-names = "rx", "tx";
- };
- ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
- dma-names = "rx", "tx";
- };
- ssiu07: ssiu-7 {
- dmas = <&audma0 0x53>, <&audma1 0x54>;
- dma-names = "rx", "tx";
- };
- ssiu10: ssiu-8 {
- dmas = <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx";
- };
- ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
- dma-names = "rx", "tx";
- };
- ssiu12: ssiu-10 {
- dmas = <&audma0 0x57>, <&audma1 0x58>;
- dma-names = "rx", "tx";
- };
- ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
- dma-names = "rx", "tx";
- };
- ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
- dma-names = "rx", "tx";
- };
- ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
- dma-names = "rx", "tx";
- };
- ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
- dma-names = "rx", "tx";
- };
- ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
- dma-names = "rx", "tx";
- };
- ssiu20: ssiu-16 {
- dmas = <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx";
- };
- ssiu21: ssiu-17 {
- dmas = <&audma0 0x67>, <&audma1 0x68>;
- dma-names = "rx", "tx";
- };
- ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
- dma-names = "rx", "tx";
- };
- ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
- dma-names = "rx", "tx";
- };
- ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
- dma-names = "rx", "tx";
- };
- ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
- dma-names = "rx", "tx";
- };
- ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
- dma-names = "rx", "tx";
- };
- ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
- dma-names = "rx", "tx";
- };
- ssiu30: ssiu-24 {
- dmas = <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx";
- };
- ssiu31: ssiu-25 {
- dmas = <&audma0 0x21>, <&audma1 0x22>;
- dma-names = "rx", "tx";
- };
- ssiu32: ssiu-26 {
- dmas = <&audma0 0x23>, <&audma1 0x24>;
- dma-names = "rx", "tx";
- };
- ssiu33: ssiu-27 {
- dmas = <&audma0 0x25>, <&audma1 0x26>;
- dma-names = "rx", "tx";
- };
- ssiu34: ssiu-28 {
- dmas = <&audma0 0x27>, <&audma1 0x28>;
- dma-names = "rx", "tx";
- };
- ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
- dma-names = "rx", "tx";
- };
- ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
- dma-names = "rx", "tx";
- };
- ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
- dma-names = "rx", "tx";
- };
- ssiu40: ssiu-32 {
- dmas = <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx";
- };
- ssiu41: ssiu-33 {
- dmas = <&audma0 0x17>, <&audma1 0x18>;
- dma-names = "rx", "tx";
- };
- ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
- dma-names = "rx", "tx";
- };
- ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
- dma-names = "rx", "tx";
- };
- ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
- dma-names = "rx", "tx";
- };
- ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
- dma-names = "rx", "tx";
- };
- ssiu46: ssiu-38 {
- dmas = <&audma0 0x31>, <&audma1 0x32>;
- dma-names = "rx", "tx";
- };
- ssiu47: ssiu-39 {
- dmas = <&audma0 0x33>, <&audma1 0x34>;
- dma-names = "rx", "tx";
- };
- ssiu50: ssiu-40 {
- dmas = <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx";
- };
- ssiu60: ssiu-41 {
- dmas = <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx";
- };
- ssiu70: ssiu-42 {
- dmas = <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx";
- };
- ssiu80: ssiu-43 {
- dmas = <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx";
- };
- ssiu90: ssiu-44 {
- dmas = <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx";
- };
- ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
- dma-names = "rx", "tx";
- };
- ssiu92: ssiu-46 {
- dmas = <&audma0 0x81>, <&audma1 0x82>;
- dma-names = "rx", "tx";
- };
- ssiu93: ssiu-47 {
- dmas = <&audma0 0x83>, <&audma1 0x84>;
- dma-names = "rx", "tx";
- };
- ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
- dma-names = "rx", "tx";
- };
- ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
- dma-names = "rx", "tx";
- };
- ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
- dma-names = "rx", "tx";
- };
- ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>;
- dma-names = "rx", "tx";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>;
- dma-names = "rx", "tx";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>;
- dma-names = "rx", "tx";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>;
- dma-names = "rx", "tx";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>;
- dma-names = "rx", "tx";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>;
- dma-names = "rx", "tx";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>;
- dma-names = "rx", "tx";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>;
- dma-names = "rx", "tx";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>;
- dma-names = "rx", "tx";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>;
- dma-names = "rx", "tx";
- };
- };
- };
-
- mlp: mlp@ec520000 {
- compatible = "renesas,r8a77965-mlp",
- "renesas,rcar-gen3-mlp";
- reg = <0 0xec520000 0 0x800>;
- interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 802>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 802>;
- status = "disabled";
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a77965",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <16>;
- };
-
- audma1: dma-controller@ec720000 {
- compatible = "renesas,dmac-r8a77965",
- "renesas,rcar-dmac";
- reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 501>;
- clock-names = "fck";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 501>;
- #dma-cells = <1>;
- dma-channels = <16>;
- };
-
- xhci0: usb@ee000000 {
- compatible = "renesas,xhci-r8a77965",
- "renesas,rcar-gen3-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- usb3_peri0: usb@ee020000 {
- compatible = "renesas,r8a77965-usb3-peri",
- "renesas,rcar-gen3-usb3-peri";
- reg = <0 0xee020000 0 0x400>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- ohci0: usb@ee080000 {
- compatible = "generic-ohci";
- reg = <0 0xee080000 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ohci1: usb@ee0a0000 {
- compatible = "generic-ohci";
- reg = <0 0xee0a0000 0 0x100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>;
- phys = <&usb2_phy1 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- ehci0: usb@ee080100 {
- compatible = "generic-ehci";
- reg = <0 0xee080100 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 2>;
- phy-names = "usb";
- companion = <&ohci0>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ehci1: usb@ee0a0100 {
- compatible = "generic-ehci";
- reg = <0 0xee0a0100 0 0x100>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>;
- phys = <&usb2_phy1 2>;
- phy-names = "usb";
- companion = <&ohci1>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- usb2_phy0: usb-phy@ee080200 {
- compatible = "renesas,usb2-phy-r8a77965",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee080200 0 0x700>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- usb2_phy1: usb-phy@ee0a0200 {
- compatible = "renesas,usb2-phy-r8a77965",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee0a0200 0 0x700>;
- clocks = <&cpg CPG_MOD 702>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a77965",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee100000 0 0x2000>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77965_CLK_SD0H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- iommus = <&ipmmu_ds1 32>;
- status = "disabled";
- };
-
- sdhi1: mmc@ee120000 {
- compatible = "renesas,sdhi-r8a77965",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee120000 0 0x2000>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77965_CLK_SD1H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 313>;
- iommus = <&ipmmu_ds1 33>;
- status = "disabled";
- };
-
- sdhi2: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a77965",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77965_CLK_SD2H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- iommus = <&ipmmu_ds1 34>;
- status = "disabled";
- };
-
- sdhi3: mmc@ee160000 {
- compatible = "renesas,sdhi-r8a77965",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee160000 0 0x2000>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77965_CLK_SD3H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- iommus = <&ipmmu_ds1 35>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a77965-rpc-if",
- "renesas,rcar-gen3-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x04000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sata: sata@ee300000 {
- compatible = "renesas,sata-r8a77965",
- "renesas,rcar-gen3-sata";
- reg = <0 0xee300000 0 0x200000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 815>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 815>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1010000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1010000 0 0x1000>,
- <0x0 0xf1020000 0 0x20000>,
- <0x0 0xf1040000 0 0x20000>,
- <0x0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- pciec0: pcie@fe000000 {
- compatible = "renesas,pcie-r8a77965",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- iommu-map = <0 &ipmmu_hc 0 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- pciec1: pcie@ee800000 {
- compatible = "renesas,pcie-r8a77965",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xee800000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
- <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
- <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
- <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- iommu-map = <0 &ipmmu_hc 1 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- fdp1@fe940000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe940000 0 0x2400>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 119>;
- power-domains = <&sysc R8A77965_PD_A3VP>;
- resets = <&cpg 119>;
- renesas,fcp = <&fcpf0>;
- };
-
- fcpf0: fcp@fe950000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe950000 0 0x200>;
- clocks = <&cpg CPG_MOD 615>;
- power-domains = <&sysc R8A77965_PD_A3VP>;
- resets = <&cpg 615>;
- };
-
- vspb: vsp@fe960000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe960000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 626>;
- power-domains = <&sysc R8A77965_PD_A3VP>;
- resets = <&cpg 626>;
-
- renesas,fcp = <&fcpvb0>;
- };
-
- vspi0: vsp@fe9a0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9a0000 0 0x8000>;
- interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 631>;
- power-domains = <&sysc R8A77965_PD_A3VP>;
- resets = <&cpg 631>;
-
- renesas,fcp = <&fcpvi0>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x5000>;
- interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
-
- renesas,fcp = <&fcpvd0>;
- };
-
- vspd1: vsp@fea28000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x5000>;
- interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 622>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 622>;
-
- renesas,fcp = <&fcpvd1>;
- };
-
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A77965_PD_A3VP>;
- resets = <&cpg 607>;
- };
-
- fcpvd0: fcp@fea27000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea27000 0 0x200>;
- clocks = <&cpg CPG_MOD 603>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 603>;
- };
-
- fcpvd1: fcp@fea2f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea2f000 0 0x200>;
- clocks = <&cpg CPG_MOD 602>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 602>;
- };
-
- fcpvi0: fcp@fe9af000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9af000 0 0x200>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A77965_PD_A3VP>;
- resets = <&cpg 611>;
- };
-
- cmm0: cmm@fea40000 {
- compatible = "renesas,r8a77965-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea40000 0 0x1000>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 711>;
- resets = <&cpg 711>;
- };
-
- cmm1: cmm@fea50000 {
- compatible = "renesas,r8a77965-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea50000 0 0x1000>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 710>;
- resets = <&cpg 710>;
- };
-
- cmm3: cmm@fea70000 {
- compatible = "renesas,r8a77965-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea70000 0 0x1000>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 708>;
- resets = <&cpg 708>;
- };
-
- csi20: csi2@fea80000 {
- compatible = "renesas,r8a77965-csi2";
- reg = <0 0xfea80000 0 0x10000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi20vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi20>;
- };
- csi20vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi20>;
- };
- csi20vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi20>;
- };
- csi20vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi20>;
- };
- csi20vin4: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&vin4csi20>;
- };
- csi20vin5: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&vin5csi20>;
- };
- csi20vin6: endpoint@6 {
- reg = <6>;
- remote-endpoint = <&vin6csi20>;
- };
- csi20vin7: endpoint@7 {
- reg = <7>;
- remote-endpoint = <&vin7csi20>;
- };
- };
- };
- };
-
- csi40: csi2@feaa0000 {
- compatible = "renesas,r8a77965-csi2";
- reg = <0 0xfeaa0000 0 0x10000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi40vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi40>;
- };
- csi40vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi40>;
- };
- csi40vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi40>;
- };
- csi40vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi40>;
- };
- csi40vin4: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&vin4csi40>;
- };
- csi40vin5: endpoint@5 {
- reg = <5>;
- remote-endpoint = <&vin5csi40>;
- };
- csi40vin6: endpoint@6 {
- reg = <6>;
- remote-endpoint = <&vin6csi40>;
- };
- csi40vin7: endpoint@7 {
- reg = <7>;
- remote-endpoint = <&vin7csi40>;
- };
- };
- };
- };
-
- hdmi0: hdmi@fead0000 {
- compatible = "renesas,r8a77965-hdmi",
- "renesas,rcar-gen3-hdmi";
- reg = <0 0xfead0000 0 0x10000>;
- interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 729>,
- <&cpg CPG_CORE R8A77965_CLK_HDMI>;
- clock-names = "iahb", "isfr";
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 729>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- dw_hdmi0_in: endpoint {
- remote-endpoint = <&du_out_hdmi0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- };
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a77965";
- reg = <0 0xfeb00000 0 0x80000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 721>;
- clock-names = "du.0", "du.1", "du.3";
- resets = <&cpg 724>, <&cpg 722>;
- reset-names = "du.0", "du.3";
-
- renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>;
- renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- du_out_hdmi0: endpoint {
- remote-endpoint = <&dw_hdmi0_in>;
- };
- };
- port@2 {
- reg = <2>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
- };
- };
-
- lvds0: lvds@feb90000 {
- compatible = "renesas,r8a77965-lvds";
- reg = <0 0xfeb90000 0 0x14>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 727>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- sensor1_thermal: sensor1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 0>;
- sustainable-power = <2439>;
-
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor2_thermal: sensor2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 1>;
- sustainable-power = <2439>;
-
- trips {
- sensor2_crit: sensor2-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor3_thermal: sensor3-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 2>;
- sustainable-power = <2439>;
-
- trips {
- target: trip-point1 {
- /* miliCelsius */
- temperature = <100000>;
- hysteresis = <1000>;
- type = "passive";
- };
-
- sensor3_crit: sensor3-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&a57_0 2 4>;
- contribution = <1024>;
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- /* External USB clocks - can be overridden by the board */
- usb3s0_clk: usb3s0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- usb_extal_clk: usb_extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Eagle board with R-Car V3M
- *
- * Copyright (C) 2016-2017 Renesas Electronics Corp.
- * Copyright (C) 2017 Cogent Embedded, Inc.
- */
-
-/dts-v1/;
-#include "r8a77970.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Renesas Eagle board based on r8a77970";
- compatible = "renesas,eagle", "renesas,r8a77970";
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- serial0 = &scif0;
- ethernet0 = &avb;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- d3p3: regulator-fixed {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_out: endpoint {
- remote-endpoint = <&adv7511_out>;
- };
- };
- };
-
- lvds-decoder {
- compatible = "thine,thc63lvd1024";
-
- vcc-supply = <&d3p3>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- thc63lvd1024_in: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
- };
-
- port@2 {
- reg = <2>;
- thc63lvd1024_out: endpoint {
- remote-endpoint = <&adv7511_in>;
- };
- };
- };
- };
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x38000000>;
- };
-
- x1_clk: x1-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <148500000>;
- };
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
-
- renesas,no-ether-link;
- phy-handle = <&phy0>;
- rx-internal-delay-ps = <1800>;
- tx-internal-delay-ps = <2000>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0022.1622",
- "ethernet-phy-ieee802.3-c22";
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio1>;
- interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- };
-};
-
-&canfd {
- pinctrl-0 = <&canfd0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- channel0 {
- status = "okay";
- };
-};
-
-&csi40 {
- status = "okay";
-
- ports {
- port@0 {
- csi40_in: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&max9286_out0>;
- };
- };
- };
-};
-
-&du {
- clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
- clock-names = "du.0", "dclkin.0";
- status = "okay";
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- io_expander: gpio@20 {
- compatible = "onnn,pca9654";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio1>;
- interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&thc63lvd1024_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
- };
- };
-};
-
-&i2c3 {
- pinctrl-0 = <&i2c3_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- gmsl0: gmsl-deserializer@48 {
- compatible = "maxim,max9286";
- reg = <0x48>;
-
- maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
- enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
- };
-
- port@2 {
- reg = <2>;
- };
-
- port@3 {
- reg = <3>;
- };
-
- port@4 {
- reg = <4>;
- max9286_out0: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&csi40_in>;
- };
- };
- };
-
- i2c-mux {
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- status = "disabled";
- };
-
- i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- status = "disabled";
- };
-
- i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
-
- status = "disabled";
- };
-
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
-
- status = "disabled";
- };
- };
- };
-};
-
-&lvds0 {
- status = "okay";
-
- ports {
- port@1 {
- lvds0_out: endpoint {
- remote-endpoint = <&thc63lvd1024_in>;
- };
- };
- };
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- avb_pins: avb0 {
- groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
- function = "avb0";
- };
-
- canfd0_pins: canfd0 {
- groups = "canfd0_data_a";
- function = "canfd0";
- };
-
- i2c0_pins: i2c0 {
- groups = "i2c0";
- function = "i2c0";
- };
-
- i2c3_pins: i2c3 {
- groups = "i2c3_a";
- function = "i2c3";
- };
-
- qspi0_pins: qspi0 {
- groups = "qspi0_ctrl", "qspi0_data4";
- function = "qspi0";
- };
-
- scif0_pins: scif0 {
- groups = "scif0_data";
- function = "scif0";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk_b";
- function = "scif_clk";
- };
-};
-
-&rpc {
- pinctrl-0 = <&qspi0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- flash@0 {
- compatible = "spansion,s25fs512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- spi-rx-bus-width = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootparam@0 {
- reg = <0x00000000 0x040000>;
- read-only;
- };
- cr7@40000 {
- reg = <0x00040000 0x080000>;
- read-only;
- };
- cert_header_sa3@c0000 {
- reg = <0x000c0000 0x080000>;
- read-only;
- };
- bl2@140000 {
- reg = <0x00140000 0x040000>;
- read-only;
- };
- cert_header_sa6@180000 {
- reg = <0x00180000 0x040000>;
- read-only;
- };
- bl31@1c0000 {
- reg = <0x001c0000 0x460000>;
- read-only;
- };
- uboot@640000 {
- reg = <0x00640000 0x0c0000>;
- read-only;
- };
- uboot-env@700000 {
- reg = <0x00700000 0x040000>;
- read-only;
- };
- dtb@740000 {
- reg = <0x00740000 0x080000>;
- };
- kernel@7c0000 {
- reg = <0x007c0000 0x1400000>;
- };
- user@1bc0000 {
- reg = <0x01bc0000 0x2440000>;
- };
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the V3M Starter Kit board
- *
- * Copyright (C) 2017 Renesas Electronics Corp.
- * Copyright (C) 2017 Cogent Embedded, Inc.
- */
-
-/dts-v1/;
-#include "r8a77970.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Renesas V3M Starter Kit board";
- compatible = "renesas,v3msk", "renesas,r8a77970";
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- serial0 = &scif0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con: endpoint {
- remote-endpoint = <&adv7511_out>;
- };
- };
- };
-
- lvds-decoder {
- compatible = "thine,thc63lvd1024";
- vcc-supply = <&vcc_d3_3v>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- thc63lvd1024_in: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
- };
-
- port@2 {
- reg = <2>;
- thc63lvd1024_out: endpoint {
- remote-endpoint = <&adv7511_in>;
- };
- };
- };
- };
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-
- osc5_clk: osc5-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <148500000>;
- };
-
- vcc_d1_8v: regulator-0 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_D1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_d3_3v: regulator-1 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_D3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_vddq_vin0: regulator-2 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_VDDQ_VIN0";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
-
- renesas,no-ether-link;
- phy-handle = <&phy0>;
- rx-internal-delay-ps = <1800>;
- tx-internal-delay-ps = <2000>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0022.1622",
- "ethernet-phy-ieee802.3-c22";
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio1>;
- interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- };
-};
-
-&du {
- clocks = <&cpg CPG_MOD 724>,
- <&osc5_clk>;
- clock-names = "du.0", "dclkin.0";
- status = "okay";
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- #sound-dai-cells = <0>;
- reg = <0x39>;
- interrupt-parent = <&gpio1>;
- interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
- avdd-supply = <&vcc_d1_8v>;
- dvdd-supply = <&vcc_d1_8v>;
- pvdd-supply = <&vcc_d1_8v>;
- bgvdd-supply = <&vcc_d1_8v>;
- dvdd-3v-supply = <&vcc_d3_3v>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&thc63lvd1024_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con>;
- };
- };
- };
- };
-};
-
-&lvds0 {
- status = "okay";
-
- ports {
- port@1 {
- lvds0_out: endpoint {
- remote-endpoint = <&thc63lvd1024_in>;
- };
- };
- };
-};
-
-&mmc0 {
- pinctrl-0 = <&mmc_pins>;
- pinctrl-names = "default";
-
- vmmc-supply = <&vcc_d3_3v>;
- vqmmc-supply = <&vcc_vddq_vin0>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&pfc {
- avb_pins: avb0 {
- groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
- function = "avb0";
- };
-
- i2c0_pins: i2c0 {
- groups = "i2c0";
- function = "i2c0";
- };
-
- mmc_pins: mmc_3_3v {
- groups = "mmc_data8", "mmc_ctrl";
- function = "mmc";
- power-source = <3300>;
- };
-
- qspi0_pins: qspi0 {
- groups = "qspi0_ctrl", "qspi0_data4";
- function = "qspi0";
- };
-
- scif0_pins: scif0 {
- groups = "scif0_data";
- function = "scif0";
- };
-};
-
-&rpc {
- pinctrl-0 = <&qspi0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- flash@0 {
- compatible = "spansion,s25fs512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- spi-rx-bus-width = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootparam@0 {
- reg = <0x00000000 0x040000>;
- read-only;
- };
- cr7@40000 {
- reg = <0x00040000 0x080000>;
- read-only;
- };
- cert_header_sa3@c0000 {
- reg = <0x000c0000 0x080000>;
- read-only;
- };
- bl2@140000 {
- reg = <0x00140000 0x040000>;
- read-only;
- };
- cert_header_sa6@180000 {
- reg = <0x00180000 0x040000>;
- read-only;
- };
- bl31@1c0000 {
- reg = <0x001c0000 0x460000>;
- read-only;
- };
- uboot@640000 {
- reg = <0x00640000 0x0c0000>;
- read-only;
- };
- uboot-env@700000 {
- reg = <0x00700000 0x040000>;
- read-only;
- };
- dtb@740000 {
- reg = <0x00740000 0x080000>;
- };
- kernel@7c0000 {
- reg = <0x007c0000 0x1400000>;
- };
- user@1bc0000 {
- reg = <0x01bc0000 0x2440000>;
- };
- };
- };
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car V3M (R8A77970) SoC
- *
- * Copyright (C) 2016-2017 Renesas Electronics Corp.
- * Copyright (C) 2017 Cogent Embedded, Inc.
- */
-
-#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/power/r8a77970-sysc.h>
-
-/ {
- compatible = "renesas,r8a77970";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- a53_0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0>;
- clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
- power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- };
-
- a53_1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <1>;
- clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
- power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- };
-
- L2_CA53: cache-controller {
- compatible = "cache";
- power-domains = <&sysc R8A77970_PD_CA53_SCU>;
- cache-unified;
- cache-level = <2>;
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- extalr_clk: extalr {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a53_0>, <&a53_1>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
-
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a77970-wdt",
- "renesas,rcar-gen3-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a77970",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 22>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a77970",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 28>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a77970",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 17>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a77970",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 17>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a77970",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 6>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a77970",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 15>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a77970";
- reg = <0 0xe6060000 0 0x504>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a77970-cmt0",
- "renesas,rcar-gen3-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 303>;
- clock-names = "fck";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 303>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a77970-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 302>;
- clock-names = "fck";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 302>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a77970-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 301>;
- clock-names = "fck";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 301>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a77970-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- clock-names = "fck";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a77970-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a77970-rst";
- reg = <0 0xe6160000 0 0x200>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a77970-sysc";
- reg = <0 0xe6180000 0 0x440>;
- #power-domain-cells = <1>;
- };
-
- thermal: thermal@e6190000 {
- compatible = "renesas,thermal-r8a77970";
- reg = <0 0xe6190000 0 0x10>,
- <0 0xe6190100 0 0x120>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <0>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a77970", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 125>;
- clock-names = "fck";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 125>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a77970", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a77970", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 123>;
- clock-names = "fck";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 123>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a77970", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 122>;
- clock-names = "fck";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 122>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a77970", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 121>;
- clock-names = "fck";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 121>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- compatible = "renesas,i2c-r8a77970",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>,
- <&dmac2 0x91>, <&dmac2 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- compatible = "renesas,i2c-r8a77970",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>,
- <&dmac2 0x93>, <&dmac2 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- compatible = "renesas,i2c-r8a77970",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>,
- <&dmac2 0x95>, <&dmac2 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- compatible = "renesas,i2c-r8a77970",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- dmas = <&dmac1 0x97>, <&dmac1 0x96>,
- <&dmac2 0x97>, <&dmac2 0x96>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- compatible = "renesas,i2c-r8a77970",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- dmas = <&dmac1 0x99>, <&dmac1 0x98>,
- <&dmac2 0x99>, <&dmac2 0x98>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a77970",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6540000 0 96>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>,
- <&cpg CPG_CORE R8A77970_CLK_S2D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>,
- <&dmac2 0x31>, <&dmac2 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a77970",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6550000 0 96>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>,
- <&cpg CPG_CORE R8A77970_CLK_S2D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x33>, <&dmac1 0x32>,
- <&dmac2 0x33>, <&dmac2 0x32>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a77970",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6560000 0 96>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>,
- <&cpg CPG_CORE R8A77970_CLK_S2D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x35>, <&dmac1 0x34>,
- <&dmac2 0x35>, <&dmac2 0x34>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a77970",
- "renesas,rcar-gen3-hscif", "renesas,hscif";
- reg = <0 0xe66a0000 0 96>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A77970_CLK_S2D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x37>, <&dmac1 0x36>,
- <&dmac2 0x37>, <&dmac2 0x36>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a77970-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A77970_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 914>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a77970",
- "renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- iommus = <&ipmmu_rt 3>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a77970",
- "renesas,rcar-gen3-scif",
- "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE R8A77970_CLK_S2D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>,
- <&dmac2 0x51>, <&dmac2 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a77970",
- "renesas,rcar-gen3-scif",
- "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE R8A77970_CLK_S2D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>,
- <&dmac2 0x53>, <&dmac2 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a77970",
- "renesas,rcar-gen3-scif",
- "renesas,scif";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE R8A77970_CLK_S2D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x57>, <&dmac1 0x56>,
- <&dmac2 0x57>, <&dmac2 0x56>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a77970",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE R8A77970_CLK_S2D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x59>, <&dmac1 0x58>,
- <&dmac2 0x59>, <&dmac2 0x58>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- tpu: pwm@e6e80000 {
- compatible = "renesas,tpu-r8a77970", "renesas,tpu";
- reg = <0 0xe6e80000 0 0x148>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 304>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 304>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a77970",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6e90000 0 0x64>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- dmas = <&dmac1 0x41>, <&dmac1 0x40>,
- <&dmac2 0x41>, <&dmac2 0x40>;
- dma-names = "tx", "rx", "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a77970",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 210>;
- dmas = <&dmac1 0x43>, <&dmac1 0x42>,
- <&dmac2 0x43>, <&dmac2 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a77970",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 209>;
- dmas = <&dmac1 0x45>, <&dmac1 0x44>,
- <&dmac2 0x45>, <&dmac2 0x44>;
- dma-names = "tx", "rx", "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a77970",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- dmas = <&dmac1 0x47>, <&dmac1 0x46>,
- <&dmac2 0x47>, <&dmac2 0x46>;
- dma-names = "tx", "rx", "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a77970";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- renesas,id = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin0csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin0>;
- };
- };
- };
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a77970";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- renesas,id = <1>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin1csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin1>;
- };
- };
- };
- };
-
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a77970";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- renesas,id = <2>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin2csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin2>;
- };
- };
- };
- };
-
- vin3: video@e6ef3000 {
- compatible = "renesas,vin-r8a77970";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- renesas,id = <3>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin3csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin3>;
- };
- };
- };
- };
-
- dmac1: dma-controller@e7300000 {
- compatible = "renesas,dmac-r8a77970",
- "renesas,rcar-dmac";
- reg = <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <8>;
- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
- };
-
- dmac2: dma-controller@e7310000 {
- compatible = "renesas,dmac-r8a77970",
- "renesas,rcar-dmac";
- reg = <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7";
- clocks = <&cpg CPG_MOD 217>;
- clock-names = "fck";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 217>;
- #dma-cells = <1>;
- dma-channels = <8>;
- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
- };
-
- ipmmu_ds1: iommu@e7740000 {
- compatible = "renesas,ipmmu-r8a77970";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ir: iommu@ff8b0000 {
- compatible = "renesas,ipmmu-r8a77970";
- reg = <0 0xff8b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 3>;
- power-domains = <&sysc R8A77970_PD_A3IR>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@e67b0000 {
- compatible = "renesas,ipmmu-r8a77970";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_rt: iommu@ffc80000 {
- compatible = "renesas,ipmmu-r8a77970";
- reg = <0 0xffc80000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 7>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@febd0000 {
- compatible = "renesas,ipmmu-r8a77970";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 9>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- mmc0: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a77970",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- max-frequency = <200000000>;
- iommus = <&ipmmu_ds1 32>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a77970-rpc-if",
- "renesas,rcar-gen3-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x4000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1010000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0xf1010000 0 0x1000>,
- <0 0xf1020000 0 0x20000>,
- <0 0xf1040000 0 0x20000>,
- <0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x5000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
- renesas,fcp = <&fcpvd0>;
- };
-
- fcpvd0: fcp@fea27000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea27000 0 0x200>;
- clocks = <&cpg CPG_MOD 603>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 603>;
- };
-
- csi40: csi2@feaa0000 {
- compatible = "renesas,r8a77970-csi2";
- reg = <0 0xfeaa0000 0 0x10000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi40vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi40>;
- };
- csi40vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi40>;
- };
- csi40vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi40>;
- };
- csi40vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi40>;
- };
- };
- };
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a77970";
- reg = <0 0xfeb00000 0 0x80000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>;
- clock-names = "du.0";
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 724>;
- reset-names = "du.0";
- renesas,vsps = <&vspd0 0>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
- };
- };
-
- lvds0: lvds-encoder@feb90000 {
- compatible = "renesas,r8a77970-lvds";
- reg = <0 0xfeb90000 0 0x14>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
- resets = <&cpg 727>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint =
- <&du_out_lvds0>;
- };
- };
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- cpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&thermal>;
-
- cooling-maps {
- };
-
- trips {
- cpu-crit {
- temperature = <120000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Condor board with R-Car V3H
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
- */
-
-/dts-v1/;
-#include "r8a77980.dtsi"
-#include "condor-common.dtsi"
-
-/ {
- model = "Renesas Condor board based on r8a77980";
- compatible = "renesas,condor", "renesas,r8a77980";
-};
-
-&i2c0 {
- eeprom@50 {
- compatible = "rohm,br24t01", "atmel,24c01";
- reg = <0x50>;
- pagesize = <8>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the V3H Starter Kit board
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
- */
-
-/dts-v1/;
-#include "r8a77980.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Renesas V3H Starter Kit board";
- compatible = "renesas,v3hsk", "renesas,r8a77980";
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- serial0 = &scif0;
- ethernet0 = &gether;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con: endpoint {
- remote-endpoint = <&adv7511_out>;
- };
- };
- };
-
- lvds-decoder {
- compatible = "thine,thc63lvd1024";
- vcc-supply = <&vcc3v3_d5>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- thc63lvd1024_in: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
- };
-
- port@2 {
- reg = <2>;
- thc63lvd1024_out: endpoint {
- remote-endpoint = <&adv7511_in>;
- };
- };
- };
- };
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0 0x48000000 0 0x78000000>;
- };
-
- osc1_clk: osc1-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <148500000>;
- };
-
- vcc1v8_d4: regulator-0 {
- compatible = "regulator-fixed";
- regulator-name = "VCC1V8_D4";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc3v3_d5: regulator-1 {
- compatible = "regulator-fixed";
- regulator-name = "VCC3V3_D5";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&du {
- clocks = <&cpg CPG_MOD 724>,
- <&osc1_clk>;
- clock-names = "du.0", "dclkin.0";
- status = "okay";
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&gether {
- pinctrl-0 = <&gether_pins>;
- pinctrl-names = "default";
-
- phy-mode = "rgmii";
- phy-handle = <&phy0>;
- renesas,no-ether-link;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0022.1622",
- "ethernet-phy-ieee802.3-c22";
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio4>;
- interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
- };
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- hdmi@39 {
- compatible = "adi,adv7511w";
- #sound-dai-cells = <0>;
- reg = <0x39>;
- interrupt-parent = <&gpio1>;
- interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
- avdd-supply = <&vcc1v8_d4>;
- dvdd-supply = <&vcc1v8_d4>;
- pvdd-supply = <&vcc1v8_d4>;
- bgvdd-supply = <&vcc1v8_d4>;
- dvdd-3v-supply = <&vcc3v3_d5>;
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&thc63lvd1024_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con>;
- };
- };
- };
- };
-};
-
-&lvds0 {
- status = "okay";
-
- ports {
- port@1 {
- lvds0_out: endpoint {
- remote-endpoint = <&thc63lvd1024_in>;
- };
- };
- };
-};
-
-&pfc {
- gether_pins: gether {
- groups = "gether_mdio_a", "gether_rgmii",
- "gether_txcrefclk", "gether_txcrefclk_mega";
- function = "gether";
- };
-
- i2c0_pins: i2c0 {
- groups = "i2c0";
- function = "i2c0";
- };
-
- qspi0_pins: qspi0 {
- groups = "qspi0_ctrl", "qspi0_data4";
- function = "qspi0";
- };
-
- scif0_pins: scif0 {
- groups = "scif0_data";
- function = "scif0";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk_b";
- function = "scif_clk";
- };
-};
-
-&rpc {
- pinctrl-0 = <&qspi0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- flash@0 {
- compatible = "spansion,s25fs512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- spi-rx-bus-width = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootparam@0 {
- reg = <0x00000000 0x040000>;
- read-only;
- };
- cr7@40000 {
- reg = <0x00040000 0x080000>;
- read-only;
- };
- cert_header_sa3@c0000 {
- reg = <0x000c0000 0x080000>;
- read-only;
- };
- bl2@140000 {
- reg = <0x00140000 0x040000>;
- read-only;
- };
- cert_header_sa6@180000 {
- reg = <0x00180000 0x040000>;
- read-only;
- };
- bl31@1c0000 {
- reg = <0x001c0000 0x460000>;
- read-only;
- };
- uboot@640000 {
- reg = <0x00640000 0x0c0000>;
- read-only;
- };
- uboot-env@700000 {
- reg = <0x00700000 0x040000>;
- read-only;
- };
- dtb@740000 {
- reg = <0x00740000 0x080000>;
- };
- kernel@7c0000 {
- reg = <0x007c0000 0x1400000>;
- };
- user@1bc0000 {
- reg = <0x01bc0000 0x2440000>;
- };
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car V3H (R8A77980) SoC
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- * Copyright (C) 2018 Cogent Embedded, Inc.
- */
-
-#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a77980-sysc.h>
-
-/ {
- compatible = "renesas,r8a77980";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- a53_0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0>;
- clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
- power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- };
-
- a53_1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <1>;
- clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
- power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- };
-
- a53_2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <2>;
- clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
- power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- };
-
- a53_3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <3>;
- clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
- power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- };
-
- L2_CA53: cache-controller {
- compatible = "cache";
- power-domains = <&sysc R8A77980_PD_CA53_SCU>;
- cache-unified;
- cache-level = <2>;
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- extalr_clk: extalr {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
-
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a77980-wdt",
- "renesas,rcar-gen3-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a77980",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 22>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a77980",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 28>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a77980",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 30>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a77980",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 17>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a77980",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 25>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a77980",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 15>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a77980";
- reg = <0 0xe6060000 0 0x50c>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a77980-cmt0",
- "renesas,rcar-gen3-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 303>;
- clock-names = "fck";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 303>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a77980-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 302>;
- clock-names = "fck";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 302>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a77980-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 301>;
- clock-names = "fck";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 301>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a77980-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- clock-names = "fck";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a77980-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a77980-rst";
- reg = <0 0xe6160000 0 0x200>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a77980-sysc";
- reg = <0 0xe6180000 0 0x440>;
- #power-domain-cells = <1>;
- };
-
- tsc: thermal@e6198000 {
- compatible = "renesas,r8a77980-thermal";
- reg = <0 0xe6198000 0 0x100>,
- <0 0xe61a0000 0 0x100>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <1>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a77980", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 125>;
- clock-names = "fck";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 125>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a77980", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a77980", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 123>;
- clock-names = "fck";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 123>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a77980", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 122>;
- clock-names = "fck";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 122>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a77980", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 121>;
- clock-names = "fck";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 121>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- compatible = "renesas,i2c-r8a77980",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>,
- <&dmac2 0x91>, <&dmac2 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- compatible = "renesas,i2c-r8a77980",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>,
- <&dmac2 0x93>, <&dmac2 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- compatible = "renesas,i2c-r8a77980",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>,
- <&dmac2 0x95>, <&dmac2 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- compatible = "renesas,i2c-r8a77980",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- compatible = "renesas,i2c-r8a77980",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c5: i2c@e66e0000 {
- compatible = "renesas,i2c-r8a77980",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e0000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
- <&dmac2 0x9b>, <&dmac2 0x9a>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a77980",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>,
- <&cpg CPG_CORE R8A77980_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>,
- <&dmac2 0x31>, <&dmac2 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a77980",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6550000 0 0x60>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>,
- <&cpg CPG_CORE R8A77980_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x33>, <&dmac1 0x32>,
- <&dmac2 0x33>, <&dmac2 0x32>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a77980",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6560000 0 0x60>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>,
- <&cpg CPG_CORE R8A77980_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x35>, <&dmac1 0x34>,
- <&dmac2 0x35>, <&dmac2 0x34>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a77980",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66a0000 0 0x60>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A77980_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x37>, <&dmac1 0x36>,
- <&dmac2 0x37>, <&dmac2 0x36>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- pcie_phy: pcie-phy@e65d0000 {
- compatible = "renesas,r8a77980-pcie-phy";
- reg = <0 0xe65d0000 0 0x8000>;
- #phy-cells = <0>;
- clocks = <&cpg CPG_MOD 319>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- status = "disabled";
- };
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a77980-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A77980_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 914>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a77980",
- "renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <2000>;
- iommus = <&ipmmu_ds1 33>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a77980",
- "renesas,rcar-gen3-scif",
- "renesas,scif";
- reg = <0 0xe6e60000 0 0x40>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE R8A77980_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>,
- <&dmac2 0x51>, <&dmac2 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a77980",
- "renesas,rcar-gen3-scif",
- "renesas,scif";
- reg = <0 0xe6e68000 0 0x40>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE R8A77980_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>,
- <&dmac2 0x53>, <&dmac2 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a77980",
- "renesas,rcar-gen3-scif",
- "renesas,scif";
- reg = <0 0xe6c50000 0 0x40>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE R8A77980_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x57>, <&dmac1 0x56>,
- <&dmac2 0x57>, <&dmac2 0x56>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a77980",
- "renesas,rcar-gen3-scif",
- "renesas,scif";
- reg = <0 0xe6c40000 0 0x40>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE R8A77980_CLK_S3D1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x59>, <&dmac1 0x58>,
- <&dmac2 0x59>, <&dmac2 0x58>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- tpu: pwm@e6e80000 {
- compatible = "renesas,tpu-r8a77980", "renesas,tpu";
- reg = <0 0xe6e80000 0 0x148>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 304>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 304>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a77980",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6e90000 0 0x64>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a77980",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 210>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a77980",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 209>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a77980",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- renesas,id = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin0csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin0>;
- };
- };
- };
- };
-
- vin1: video@e6ef1000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- status = "disabled";
- renesas,id = <1>;
- resets = <&cpg 810>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin1csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin1>;
- };
- };
- };
- };
-
- vin2: video@e6ef2000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- renesas,id = <2>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin2csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin2>;
- };
- };
- };
- };
-
- vin3: video@e6ef3000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- renesas,id = <3>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin3csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin3>;
- };
- };
- };
- };
-
- vin4: video@e6ef4000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 807>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 807>;
- renesas,id = <4>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin4csi41: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&csi41vin4>;
- };
- };
- };
- };
-
- vin5: video@e6ef5000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6ef5000 0 0x1000>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 806>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 806>;
- renesas,id = <5>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin5csi41: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&csi41vin5>;
- };
- };
- };
- };
-
- vin6: video@e6ef6000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6ef6000 0 0x1000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 805>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 805>;
- renesas,id = <6>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin6csi41: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&csi41vin6>;
- };
- };
- };
- };
-
- vin7: video@e6ef7000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6ef7000 0 0x1000>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 804>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 804>;
- renesas,id = <7>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin7csi41: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&csi41vin7>;
- };
- };
- };
- };
-
- vin8: video@e6ef8000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6ef8000 0 0x1000>;
- interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- renesas,id = <8>;
- status = "disabled";
- };
-
- vin9: video@e6ef9000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6ef9000 0 0x1000>;
- interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 627>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 627>;
- renesas,id = <9>;
- status = "disabled";
- };
-
- vin10: video@e6efa000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6efa000 0 0x1000>;
- interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 625>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 625>;
- renesas,id = <10>;
- status = "disabled";
- };
-
- vin11: video@e6efb000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6efb000 0 0x1000>;
- interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 618>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 618>;
- renesas,id = <11>;
- status = "disabled";
- };
-
- vin12: video@e6efc000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6efc000 0 0x1000>;
- interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 612>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 612>;
- renesas,id = <12>;
- status = "disabled";
- };
-
- vin13: video@e6efd000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6efd000 0 0x1000>;
- interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 608>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 608>;
- renesas,id = <13>;
- status = "disabled";
- };
-
- vin14: video@e6efe000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6efe000 0 0x1000>;
- interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 605>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 605>;
- renesas,id = <14>;
- status = "disabled";
- };
-
- vin15: video@e6eff000 {
- compatible = "renesas,vin-r8a77980";
- reg = <0 0xe6eff000 0 0x1000>;
- interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 604>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 604>;
- renesas,id = <15>;
- status = "disabled";
- };
-
- dmac1: dma-controller@e7300000 {
- compatible = "renesas,dmac-r8a77980",
- "renesas,rcar-dmac";
- reg = <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
- };
-
- dmac2: dma-controller@e7310000 {
- compatible = "renesas,dmac-r8a77980",
- "renesas,rcar-dmac";
- reg = <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 217>;
- clock-names = "fck";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 217>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
- };
-
- gether: ethernet@e7400000 {
- compatible = "renesas,gether-r8a77980";
- reg = <0 0xe7400000 0 0x1000>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ipmmu_ds1: iommu@e7740000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ir: iommu@ff8b0000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xff8b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 3>;
- power-domains = <&sysc R8A77980_PD_A3IR>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@e67b0000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_rt: iommu@ffc80000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xffc80000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 10>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: iommu@fe990000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xfe990000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 12>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@febd0000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 14>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vip0: iommu@e7b00000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xe7b00000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 4>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vip1: iommu@e7960000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xe7960000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 11>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- mmc0: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a77980",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>;
- clock-names = "core", "clkh";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- max-frequency = <200000000>;
- iommus = <&ipmmu_ds1 32>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a77980-rpc-if",
- "renesas,rcar-gen3-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x4000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1010000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1010000 0 0x1000>,
- <0x0 0xf1020000 0 0x20000>,
- <0x0 0xf1040000 0 0x20000>,
- <0x0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- pciec: pcie@fe000000 {
- compatible = "renesas,pcie-r8a77980",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>,
- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>,
- <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
- <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- phys = <&pcie_phy>;
- phy-names = "pcie";
- iommu-map = <0 &ipmmu_vi0 5 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x5000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
- renesas,fcp = <&fcpvd0>;
- };
-
- fcpvd0: fcp@fea27000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea27000 0 0x200>;
- clocks = <&cpg CPG_MOD 603>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 603>;
- };
-
- csi40: csi2@feaa0000 {
- compatible = "renesas,r8a77980-csi2";
- reg = <0 0xfeaa0000 0 0x10000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi40vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi40>;
- };
- csi40vin1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin1csi40>;
- };
- csi40vin2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin2csi40>;
- };
- csi40vin3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin3csi40>;
- };
- };
- };
- };
-
- csi41: csi2@feab0000 {
- compatible = "renesas,r8a77980-csi2";
- reg = <0 0xfeab0000 0 0x10000>;
- interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 715>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 715>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi41vin4: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin4csi41>;
- };
- csi41vin5: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin5csi41>;
- };
- csi41vin6: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vin6csi41>;
- };
- csi41vin7: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&vin7csi41>;
- };
- };
- };
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a77980";
- reg = <0 0xfeb00000 0 0x80000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>;
- clock-names = "du.0";
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 724>;
- reset-names = "du.0";
- renesas,vsps = <&vspd0 0>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
- };
- };
-
- lvds0: lvds-encoder@feb90000 {
- compatible = "renesas,r8a77980-lvds";
- reg = <0 0xfeb90000 0 0x14>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- resets = <&cpg 727>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint =
- <&du_out_lvds0>;
- };
- };
-
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- sensor1_thermal: sensor1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 0>;
-
- trips {
- sensor1-passive {
- temperature = <95000>;
- hysteresis = <1000>;
- type = "passive";
- };
- sensor1-critical {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor2_thermal: sensor2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 1>;
-
- trips {
- sensor2-passive {
- temperature = <95000>;
- hysteresis = <1000>;
- type = "passive";
- };
- sensor2-critical {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_LOW)>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Ebisu board with R-Car E3
- *
- * Copyright (C) 2018 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a77990.dtsi"
-#include "ebisu.dtsi"
-
-/ {
- model = "Renesas Ebisu board based on r8a77990";
- compatible = "renesas,ebisu", "renesas,r8a77990";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car E3 (R8A77990) SoC
- *
- * Copyright (C) 2018-2019 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a77990-sysc.h>
-
-/ {
- compatible = "renesas,r8a77990";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cluster1_opp: opp-table-1 {
- compatible = "operating-points-v2";
- opp-shared;
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- clock-latency-ns = <300000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- clock-latency-ns = <300000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- clock-latency-ns = <300000>;
- opp-suspend;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- a53_0: cpu@0 {
- compatible = "arm,cortex-a53";
- reg = <0>;
- device_type = "cpu";
- #cooling-cells = <2>;
- power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- dynamic-power-coefficient = <277>;
- clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- };
-
- a53_1: cpu@1 {
- compatible = "arm,cortex-a53";
- reg = <1>;
- device_type = "cpu";
- power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
- operating-points-v2 = <&cluster1_opp>;
- };
-
- L2_CA53: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A77990_PD_CA53_SCU>;
- cache-unified;
- cache-level = <2>;
- };
-
- idle-states {
- entry-method = "psci";
-
- CPU_SLEEP_0: cpu-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- local-timer-stop;
- entry-latency-us = <700>;
- exit-latency-us = <700>;
- min-residency-us = <5000>;
- };
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a53_0>, <&a53_1>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc: soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a77990-wdt",
- "renesas,rcar-gen3-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a77990",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 18>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a77990",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 23>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a77990",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 26>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a77990",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 16>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a77990",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 11>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a77990",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 20>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a77990",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 18>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 906>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 906>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a77990";
- reg = <0 0xe6060000 0 0x508>;
- };
-
- i2c_dvfs: i2c@e60b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-r8a77990",
- "renesas,rcar-gen3-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe60b0000 0 0x425>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 926>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 926>;
- dmas = <&dmac0 0x11>, <&dmac0 0x10>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a77990-cmt0",
- "renesas,rcar-gen3-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 303>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 303>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a77990-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 302>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 302>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a77990-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 301>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 301>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a77990-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a77990-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>;
- clock-names = "extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a77990-rst";
- reg = <0 0xe6160000 0 0x0200>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a77990-sysc";
- reg = <0 0xe6180000 0 0x0400>;
- #power-domain-cells = <1>;
- };
-
- thermal: thermal@e6190000 {
- compatible = "renesas,thermal-r8a77990";
- reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <0>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a77990", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 125>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 125>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a77990", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a77990", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 123>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 123>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a77990", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 122>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 122>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a77990", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 121>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 121>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77990",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>,
- <&dmac2 0x91>, <&dmac2 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77990",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>,
- <&dmac2 0x93>, <&dmac2 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77990",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>,
- <&dmac2 0x95>, <&dmac2 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77990",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- dmas = <&dmac0 0x97>, <&dmac0 0x96>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77990",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 927>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 927>;
- dmas = <&dmac0 0x99>, <&dmac0 0x98>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c5: i2c@e66e0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77990",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e0000 0 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c6: i2c@e66e8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77990",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66e8000 0 0x40>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c7: i2c@e6690000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77990",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6690000 0 0x40>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1003>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 1003>;
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a77990",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>,
- <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>,
- <&dmac2 0x31>, <&dmac2 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a77990",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6550000 0 0x60>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>,
- <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x33>, <&dmac1 0x32>,
- <&dmac2 0x33>, <&dmac2 0x32>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a77990",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6560000 0 0x60>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>,
- <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x35>, <&dmac1 0x34>,
- <&dmac2 0x35>, <&dmac2 0x34>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a77990",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66a0000 0 0x60>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x37>, <&dmac0 0x36>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- hscif4: serial@e66b0000 {
- compatible = "renesas,hscif-r8a77990",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66b0000 0 0x60>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x39>, <&dmac0 0x38>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 516>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a77990",
- "renesas,rcar-gen3-usbhs";
- reg = <0 0xe6590000 0 0x200>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- renesas,buswait = <11>;
- phys = <&usb2_phy0 3>;
- phy-names = "usb";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 704>, <&cpg 703>;
- status = "disabled";
- };
-
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a77990-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a77990-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- arm_cc630p: crypto@e6601000 {
- compatible = "arm,cryptocell-630p-ree";
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x0 0xe6601000 0 0x1000>;
- clocks = <&cpg CPG_MOD 229>;
- resets = <&cpg 229>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a77990",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x10000>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
- };
-
- dmac1: dma-controller@e7300000 {
- compatible = "renesas,dmac-r8a77990",
- "renesas,rcar-dmac";
- reg = <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
- <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
- <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
- <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
- <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
- };
-
- dmac2: dma-controller@e7310000 {
- compatible = "renesas,dmac-r8a77990",
- "renesas,rcar-dmac";
- reg = <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 217>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 217>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
- <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
- <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
- <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
- <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
- };
-
- ipmmu_ds0: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a77990";
- reg = <0 0xe6740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds1: iommu@e7740000 {
- compatible = "renesas,ipmmu-r8a77990";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 1>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_hc: iommu@e6570000 {
- compatible = "renesas,ipmmu-r8a77990";
- reg = <0 0xe6570000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 2>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@e67b0000 {
- compatible = "renesas,ipmmu-r8a77990";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mp: iommu@ec670000 {
- compatible = "renesas,ipmmu-r8a77990";
- reg = <0 0xec670000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 4>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv0: iommu@fd800000 {
- compatible = "renesas,ipmmu-r8a77990";
- reg = <0 0xfd800000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 6>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_rt: iommu@ffc80000 {
- compatible = "renesas,ipmmu-r8a77990";
- reg = <0 0xffc80000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 10>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: iommu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a77990";
- reg = <0 0xfe6b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 12>;
- power-domains = <&sysc R8A77990_PD_A3VC>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@febd0000 {
- compatible = "renesas,ipmmu-r8a77990";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 14>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vp0: iommu@fe990000 {
- compatible = "renesas,ipmmu-r8a77990";
- reg = <0 0xfe990000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 16>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a77990",
- "renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- iommus = <&ipmmu_ds0 16>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can0: can@e6c30000 {
- compatible = "renesas,can-r8a77990",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c30000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A77990_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6c38000 {
- compatible = "renesas,can-r8a77990",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c38000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A77990_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a77990-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A77990_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 914>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm5: pwm@e6e35000 {
- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
- reg = <0 0xe6e35000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm6: pwm@e6e36000 {
- compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
- reg = <0 0xe6e36000 0 0x8>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a77990",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>,
- <&dmac2 0x51>, <&dmac2 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a77990",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>,
- <&dmac2 0x53>, <&dmac2 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scif2: serial@e6e88000 {
- compatible = "renesas,scif-r8a77990",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e88000 0 64>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>,
- <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x13>, <&dmac1 0x12>,
- <&dmac2 0x13>, <&dmac2 0x12>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 310>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a77990",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x57>, <&dmac0 0x56>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a77990",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x59>, <&dmac0 0x58>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scif5: serial@e6f30000 {
- compatible = "renesas,scif-r8a77990",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6f30000 0 64>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>,
- <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a77990",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6e90000 0 0x0064>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
- dmas = <&dmac1 0x41>, <&dmac1 0x40>,
- <&dmac2 0x41>, <&dmac2 0x40>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a77990",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
- dmas = <&dmac0 0x43>, <&dmac0 0x42>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 210>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a77990",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
- dmas = <&dmac0 0x45>, <&dmac0 0x44>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 209>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a77990",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x47>, <&dmac0 0x46>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin4: video@e6ef4000 {
- compatible = "renesas,vin-r8a77990";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 807>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 807>;
- renesas,id = <4>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin4csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin4>;
- };
- };
- };
- };
-
- vin5: video@e6ef5000 {
- compatible = "renesas,vin-r8a77990";
- reg = <0 0xe6ef5000 0 0x1000>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 806>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 806>;
- renesas,id = <5>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin5csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&csi40vin5>;
- };
- };
- };
- };
-
- drif00: rif@e6f40000 {
- compatible = "renesas,r8a77990-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f40000 0 0x84>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 515>;
- clock-names = "fck";
- dmas = <&dmac1 0x20>, <&dmac2 0x20>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 515>;
- renesas,bonding = <&drif01>;
- status = "disabled";
- };
-
- drif01: rif@e6f50000 {
- compatible = "renesas,r8a77990-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f50000 0 0x84>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 514>;
- clock-names = "fck";
- dmas = <&dmac1 0x22>, <&dmac2 0x22>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 514>;
- renesas,bonding = <&drif00>;
- status = "disabled";
- };
-
- drif10: rif@e6f60000 {
- compatible = "renesas,r8a77990-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f60000 0 0x84>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 513>;
- clock-names = "fck";
- dmas = <&dmac1 0x24>, <&dmac2 0x24>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 513>;
- renesas,bonding = <&drif11>;
- status = "disabled";
- };
-
- drif11: rif@e6f70000 {
- compatible = "renesas,r8a77990-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f70000 0 0x84>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 512>;
- clock-names = "fck";
- dmas = <&dmac1 0x26>, <&dmac2 0x26>;
- dma-names = "rx", "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 512>;
- renesas,bonding = <&drif10>;
- status = "disabled";
- };
-
- drif20: rif@e6f80000 {
- compatible = "renesas,r8a77990-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f80000 0 0x84>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 511>;
- clock-names = "fck";
- dmas = <&dmac0 0x28>;
- dma-names = "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 511>;
- renesas,bonding = <&drif21>;
- status = "disabled";
- };
-
- drif21: rif@e6f90000 {
- compatible = "renesas,r8a77990-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6f90000 0 0x84>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 510>;
- clock-names = "fck";
- dmas = <&dmac0 0x2a>;
- dma-names = "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 510>;
- renesas,bonding = <&drif20>;
- status = "disabled";
- };
-
- drif30: rif@e6fa0000 {
- compatible = "renesas,r8a77990-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6fa0000 0 0x84>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 509>;
- clock-names = "fck";
- dmas = <&dmac0 0x2c>;
- dma-names = "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 509>;
- renesas,bonding = <&drif31>;
- status = "disabled";
- };
-
- drif31: rif@e6fb0000 {
- compatible = "renesas,r8a77990-drif",
- "renesas,rcar-gen3-drif";
- reg = <0 0xe6fb0000 0 0x84>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 508>;
- clock-names = "fck";
- dmas = <&dmac0 0x2e>;
- dma-names = "rx";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 508>;
- renesas,bonding = <&drif30>;
- status = "disabled";
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- /*
- * #clock-cells is required for audio_clkout0/1/2/3
- *
- * clkout : #clock-cells = <0>; <&rcar_sound>;
- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>,
- <&audio_clk_c>,
- <&cpg CPG_CORE R8A77990_CLK_ZA2>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6",
- "src.5", "src.4", "src.3", "src.2",
- "src.1", "src.0",
- "mix.1", "mix.0",
- "ctu.1", "ctu.0",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1006>, <&cpg 1007>,
- <&cpg 1008>, <&cpg 1009>,
- <&cpg 1010>, <&cpg 1011>,
- <&cpg 1012>, <&cpg 1013>,
- <&cpg 1014>, <&cpg 1015>;
- reset-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6",
- "ssi.5", "ssi.4", "ssi.3", "ssi.2",
- "ssi.1", "ssi.0";
- status = "disabled";
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma0 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma0 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,src {
- src0: src-0 {
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma0 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma0 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma0 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma0 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma0 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma0 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma0 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma0 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma0 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma0 0xba>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma0 0x02>,
- <&audma0 0x15>, <&audma0 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma0 0x04>,
- <&audma0 0x49>, <&audma0 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma0 0x06>,
- <&audma0 0x63>, <&audma0 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma0 0x08>,
- <&audma0 0x6f>, <&audma0 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma0 0x0a>,
- <&audma0 0x71>, <&audma0 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma0 0x0c>,
- <&audma0 0x73>, <&audma0 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma0 0x0e>,
- <&audma0 0x75>, <&audma0 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma0 0x10>,
- <&audma0 0x79>, <&audma0 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma0 0x12>,
- <&audma0 0x7b>, <&audma0 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma0 0x14>,
- <&audma0 0x7d>, <&audma0 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- };
- };
-
- mlp: mlp@ec520000 {
- compatible = "renesas,r8a77990-mlp",
- "renesas,rcar-gen3-mlp";
- reg = <0 0xec520000 0 0x800>;
- interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 802>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 802>;
- status = "disabled";
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a77990",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
- <&ipmmu_mp 2>, <&ipmmu_mp 3>,
- <&ipmmu_mp 4>, <&ipmmu_mp 5>,
- <&ipmmu_mp 6>, <&ipmmu_mp 7>,
- <&ipmmu_mp 8>, <&ipmmu_mp 9>,
- <&ipmmu_mp 10>, <&ipmmu_mp 11>,
- <&ipmmu_mp 12>, <&ipmmu_mp 13>,
- <&ipmmu_mp 14>, <&ipmmu_mp 15>;
- };
-
- xhci0: usb@ee000000 {
- compatible = "renesas,xhci-r8a77990",
- "renesas,rcar-gen3-xhci";
- reg = <0 0xee000000 0 0xc00>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- usb3_peri0: usb@ee020000 {
- compatible = "renesas,r8a77990-usb3-peri",
- "renesas,rcar-gen3-usb3-peri";
- reg = <0 0xee020000 0 0x400>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 328>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
- };
-
- ohci0: usb@ee080000 {
- compatible = "generic-ohci";
- reg = <0 0xee080000 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ehci0: usb@ee080100 {
- compatible = "generic-ehci";
- reg = <0 0xee080100 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 2>;
- phy-names = "usb";
- companion = <&ohci0>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- usb2_phy0: usb-phy@ee080200 {
- compatible = "renesas,usb2-phy-r8a77990",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee080200 0 0x700>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- sdhi0: mmc@ee100000 {
- compatible = "renesas,sdhi-r8a77990",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee100000 0 0x2000>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77990_CLK_SD0H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- iommus = <&ipmmu_ds1 32>;
- status = "disabled";
- };
-
- sdhi1: mmc@ee120000 {
- compatible = "renesas,sdhi-r8a77990",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee120000 0 0x2000>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77990_CLK_SD1H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 313>;
- iommus = <&ipmmu_ds1 33>;
- status = "disabled";
- };
-
- sdhi3: mmc@ee160000 {
- compatible = "renesas,sdhi-r8a77990",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee160000 0 0x2000>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77990_CLK_SD3H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- iommus = <&ipmmu_ds1 35>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a77990-rpc-if",
- "renesas,rcar-gen3-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x04000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1010000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1010000 0 0x1000>,
- <0x0 0xf1020000 0 0x20000>,
- <0x0 0xf1040000 0 0x20000>,
- <0x0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- pciec0: pcie@fe000000 {
- compatible = "renesas,pcie-r8a77990",
- "renesas,pcie-rcar-gen3";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
- <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
- <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
- <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR/IOMMU as inbound ranges */
- dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 319>;
- iommu-map = <0 &ipmmu_hc 0 1>;
- iommu-map-mask = <0>;
- status = "disabled";
- };
-
- vspb0: vsp@fe960000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe960000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 626>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 626>;
- renesas,fcp = <&fcpvb0>;
- };
-
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 607>;
- iommus = <&ipmmu_vp0 5>;
- };
-
- vspi0: vsp@fe9a0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9a0000 0 0x8000>;
- interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 631>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 631>;
- renesas,fcp = <&fcpvi0>;
- };
-
- fcpvi0: fcp@fe9af000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9af000 0 0x200>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 611>;
- iommus = <&ipmmu_vp0 8>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x7000>;
- interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
- renesas,fcp = <&fcpvd0>;
- };
-
- fcpvd0: fcp@fea27000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea27000 0 0x200>;
- clocks = <&cpg CPG_MOD 603>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 603>;
- iommus = <&ipmmu_vi0 8>;
- };
-
- vspd1: vsp@fea28000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x7000>;
- interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 622>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 622>;
- renesas,fcp = <&fcpvd1>;
- };
-
- fcpvd1: fcp@fea2f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea2f000 0 0x200>;
- clocks = <&cpg CPG_MOD 602>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 602>;
- iommus = <&ipmmu_vi0 9>;
- };
-
- cmm0: cmm@fea40000 {
- compatible = "renesas,r8a77990-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea40000 0 0x1000>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 711>;
- resets = <&cpg 711>;
- };
-
- cmm1: cmm@fea50000 {
- compatible = "renesas,r8a77990-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea50000 0 0x1000>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 710>;
- resets = <&cpg 710>;
- };
-
- csi40: csi2@feaa0000 {
- compatible = "renesas,r8a77990-csi2";
- reg = <0 0xfeaa0000 0 0x10000>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi40vin4: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin4csi40>;
- };
- csi40vin5: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vin5csi40>;
- };
- };
- };
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a77990";
- reg = <0 0xfeb00000 0 0x40000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
- clock-names = "du.0", "du.1";
- resets = <&cpg 724>;
- reset-names = "du.0";
-
- renesas,cmms = <&cmm0>, <&cmm1>;
- renesas,vsps = <&vspd0 0>, <&vspd1 0>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
-
- port@2 {
- reg = <2>;
- du_out_lvds1: endpoint {
- remote-endpoint = <&lvds1_in>;
- };
- };
- };
- };
-
- lvds0: lvds-encoder@feb90000 {
- compatible = "renesas,r8a77990-lvds";
- reg = <0 0xfeb90000 0 0x20>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 727>;
- status = "disabled";
-
- renesas,companion = <&lvds1>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
-
- port@1 {
- reg = <1>;
- };
- };
- };
-
- lvds1: lvds-encoder@feb90100 {
- compatible = "renesas,r8a77990-lvds";
- reg = <0 0xfeb90100 0 0x20>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
- resets = <&cpg 726>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds1_in: endpoint {
- remote-endpoint = <&du_out_lvds1>;
- };
- };
-
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- cpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <0>;
- thermal-sensors = <&thermal>;
- sustainable-power = <717>;
-
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&a53_0 0 2>;
- contribution = <1024>;
- };
- };
-
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <120000>;
- hysteresis = <2000>;
- type = "critical";
- };
-
- target: trip-point1 {
- temperature = <100000>;
- hysteresis = <2000>;
- type = "passive";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Draak board with R-Car D3
- *
- * Copyright (C) 2016-2018 Renesas Electronics Corp.
- * Copyright (C) 2017 Glider bvba
- */
-
-/dts-v1/;
-#include "r8a77995.dtsi"
-#include "draak.dtsi"
-
-/ {
- model = "Renesas Draak board based on r8a77995";
- compatible = "renesas,draak", "renesas,r8a77995";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car D3 (R8A77995) SoC
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- * Copyright (C) 2017 Glider bvba
- */
-
-#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a77995-sysc.h>
-
-/ {
- compatible = "renesas,r8a77995";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- a53_0: cpu@0 {
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- device_type = "cpu";
- power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
- next-level-cache = <&L2_CA53>;
- enable-method = "psci";
- };
-
- L2_CA53: cache-controller-1 {
- compatible = "cache";
- power-domains = <&sysc R8A77995_PD_CA53_SCU>;
- cache-unified;
- cache-level = <2>;
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a77995-wdt",
- "renesas,rcar-gen3-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
- };
-
- gpio0: gpio@e6050000 {
- compatible = "renesas,gpio-r8a77995",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6050000 0 0x50>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 0 9>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- };
-
- gpio1: gpio@e6051000 {
- compatible = "renesas,gpio-r8a77995",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6051000 0 0x50>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 32 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- };
-
- gpio2: gpio@e6052000 {
- compatible = "renesas,gpio-r8a77995",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6052000 0 0x50>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 64 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- };
-
- gpio3: gpio@e6053000 {
- compatible = "renesas,gpio-r8a77995",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6053000 0 0x50>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 96 10>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 909>;
- };
-
- gpio4: gpio@e6054000 {
- compatible = "renesas,gpio-r8a77995",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6054000 0 0x50>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 128 32>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 908>;
- };
-
- gpio5: gpio@e6055000 {
- compatible = "renesas,gpio-r8a77995",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055000 0 0x50>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 160 21>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- };
-
- gpio6: gpio@e6055400 {
- compatible = "renesas,gpio-r8a77995",
- "renesas,rcar-gen3-gpio";
- reg = <0 0xe6055400 0 0x50>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pfc 0 192 14>;
- #interrupt-cells = <2>;
- interrupt-controller;
- clocks = <&cpg CPG_MOD 906>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 906>;
- };
-
- pfc: pinctrl@e6060000 {
- compatible = "renesas,pfc-r8a77995";
- reg = <0 0xe6060000 0 0x508>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a77995-cmt0",
- "renesas,rcar-gen3-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 303>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 303>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a77995-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 302>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 302>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a77995-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 301>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 301>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a77995-cmt1",
- "renesas,rcar-gen3-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 300>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 300>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a77995-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>;
- clock-names = "extal";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a77995-rst";
- reg = <0 0xe6160000 0 0x0200>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a77995-sysc";
- reg = <0 0xe6180000 0 0x0400>;
- #power-domain-cells = <1>;
- };
-
- thermal: thermal@e6190000 {
- compatible = "renesas,thermal-r8a77995";
- reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <0>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a77995", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 125>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 125>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a77995", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 124>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 124>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a77995", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 123>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 123>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a77995", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 122>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 122>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a77995", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 121>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 121>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77995",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>,
- <&dmac2 0x91>, <&dmac2 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77995",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 930>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 930>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>,
- <&dmac2 0x93>, <&dmac2 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77995",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 929>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 929>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>,
- <&dmac2 0x95>, <&dmac2 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a77995",
- "renesas,rcar-gen3-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 928>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 928>;
- dmas = <&dmac0 0x97>, <&dmac0 0x96>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <6>;
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a77995",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>,
- <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>,
- <&dmac2 0x31>, <&dmac2 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a77995",
- "renesas,rcar-gen3-hscif",
- "renesas,hscif";
- reg = <0 0xe66a0000 0 0x60>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x37>, <&dmac0 0x36>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a77995",
- "renesas,rcar-gen3-usbhs";
- reg = <0 0xe6590000 0 0x200>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
- dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
- <&usb_dmac1 0>, <&usb_dmac1 1>;
- dma-names = "ch0", "ch1", "ch2", "ch3";
- renesas,buswait = <11>;
- phys = <&usb2_phy0 3>;
- phy-names = "usb";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 704>, <&cpg 703>;
- status = "disabled";
- };
-
- usb_dmac0: dma-controller@e65a0000 {
- compatible = "renesas,r8a77995-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 330>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 330>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- usb_dmac1: dma-controller@e65b0000 {
- compatible = "renesas,r8a77995-usb-dmac",
- "renesas,usb-dmac";
- reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- #dma-cells = <1>;
- dma-channels = <2>;
- };
-
- arm_cc630p: crypto@e6601000 {
- compatible = "arm,cryptocell-630p-ree";
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x0 0xe6601000 0 0x1000>;
- clocks = <&cpg CPG_MOD 229>;
- resets = <&cpg 229>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- };
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a77995-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A77995_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 914>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
- dmac0: dma-controller@e6700000 {
- compatible = "renesas,dmac-r8a77995",
- "renesas,rcar-dmac";
- reg = <0 0xe6700000 0 0x10000>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7";
- clocks = <&cpg CPG_MOD 219>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 219>;
- #dma-cells = <1>;
- dma-channels = <8>;
- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>;
- };
-
- dmac1: dma-controller@e7300000 {
- compatible = "renesas,dmac-r8a77995",
- "renesas,rcar-dmac";
- reg = <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7";
- clocks = <&cpg CPG_MOD 218>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 218>;
- #dma-cells = <1>;
- dma-channels = <8>;
- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
- };
-
- dmac2: dma-controller@e7310000 {
- compatible = "renesas,dmac-r8a77995",
- "renesas,rcar-dmac";
- reg = <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7";
- clocks = <&cpg CPG_MOD 217>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 217>;
- #dma-cells = <1>;
- dma-channels = <8>;
- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
- };
-
- ipmmu_ds0: iommu@e6740000 {
- compatible = "renesas,ipmmu-r8a77995";
- reg = <0 0xe6740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds1: iommu@e7740000 {
- compatible = "renesas,ipmmu-r8a77995";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 1>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_hc: iommu@e6570000 {
- compatible = "renesas,ipmmu-r8a77995";
- reg = <0 0xe6570000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 2>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@e67b0000 {
- compatible = "renesas,ipmmu-r8a77995";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mp: iommu@ec670000 {
- compatible = "renesas,ipmmu-r8a77995";
- reg = <0 0xec670000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 4>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_pv0: iommu@fd800000 {
- compatible = "renesas,ipmmu-r8a77995";
- reg = <0 0xfd800000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 6>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_rt: iommu@ffc80000 {
- compatible = "renesas,ipmmu-r8a77995";
- reg = <0 0xffc80000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 10>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: iommu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a77995";
- reg = <0 0xfe6b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 12>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@febd0000 {
- compatible = "renesas,ipmmu-r8a77995";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 14>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vp0: iommu@fe990000 {
- compatible = "renesas,ipmmu-r8a77995";
- reg = <0 0xfe990000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 16>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- avb: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a77995",
- "renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 812>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <1800>;
- iommus = <&ipmmu_ds0 16>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can0: can@e6c30000 {
- compatible = "renesas,can-r8a77995",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c30000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>,
- <&cpg CPG_CORE R8A77995_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- status = "disabled";
- };
-
- can1: can@e6c38000 {
- compatible = "renesas,can-r8a77995",
- "renesas,rcar-gen3-can";
- reg = <0 0xe6c38000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>,
- <&cpg CPG_CORE R8A77995_CLK_CANFD>,
- <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- status = "disabled";
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 0x8>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a77995",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>,
- <&dmac2 0x51>, <&dmac2 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 207>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a77995",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>,
- <&dmac2 0x53>, <&dmac2 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 206>;
- status = "disabled";
- };
-
- scif2: serial@e6e88000 {
- compatible = "renesas,scif-r8a77995",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6e88000 0 64>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>,
- <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x13>, <&dmac1 0x12>,
- <&dmac2 0x13>, <&dmac2 0x12>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 310>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a77995",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x57>, <&dmac0 0x56>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 204>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a77995",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x59>, <&dmac0 0x58>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 203>;
- status = "disabled";
- };
-
- scif5: serial@e6f30000 {
- compatible = "renesas,scif-r8a77995",
- "renesas,rcar-gen3-scif", "renesas,scif";
- reg = <0 0xe6f30000 0 64>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>,
- <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
- <&dmac2 0x5b>, <&dmac2 0x5a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 202>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a77995",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6e90000 0 0x64>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
- dmas = <&dmac1 0x41>, <&dmac1 0x40>,
- <&dmac2 0x41>, <&dmac2 0x40>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a77995",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6ea0000 0 0x64>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
- dmas = <&dmac1 0x43>, <&dmac1 0x42>,
- <&dmac2 0x43>, <&dmac2 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 210>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a77995",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c00000 0 0x64>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
- dmas = <&dmac0 0x45>, <&dmac0 0x44>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 209>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a77995",
- "renesas,rcar-gen3-msiof";
- reg = <0 0xe6c10000 0 0x64>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
- dmas = <&dmac0 0x47>, <&dmac0 0x46>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 208>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin4: video@e6ef4000 {
- compatible = "renesas,vin-r8a77995";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 807>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 807>;
- renesas,id = <4>;
- status = "disabled";
- };
-
- rcar_sound: sound@ec500000 {
- /*
- * #sound-dai-cells is required if simple-card
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- /*
- * #clock-cells is required for audio_clkout0/1/2/3
- *
- * clkout : #clock-cells = <0>; <&rcar_sound>;
- * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
- <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&audio_clk_b>,
- <&cpg CPG_CORE R8A77995_CLK_ZA2>;
- clock-names = "ssi-all",
- "ssi.4", "ssi.3",
- "src.6", "src.5",
- "mix.1", "mix.0",
- "ctu.1", "ctu.0",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_i";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 1005>,
- <&cpg 1011>, <&cpg 1012>;
- reset-names = "ssi-all",
- "ssi.4", "ssi.3";
- status = "disabled";
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma0 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma0 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,src {
- src5: src-5 {
- interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma0 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma0 0xb4>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma0 0x08>,
- <&audma0 0x6f>, <&audma0 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma0 0x0a>,
- <&audma0 0x71>, <&audma0 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
- };
- };
- };
-
- mlp: mlp@ec520000 {
- compatible = "renesas,r8a77995-mlp",
- "renesas,rcar-gen3-mlp";
- reg = <0 0xec520000 0 0x800>;
- interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 802>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 802>;
- status = "disabled";
- };
-
- audma0: dma-controller@ec700000 {
- compatible = "renesas,dmac-r8a77995",
- "renesas,rcar-dmac";
- reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD 502>;
- clock-names = "fck";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 502>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
- <&ipmmu_mp 2>, <&ipmmu_mp 3>,
- <&ipmmu_mp 4>, <&ipmmu_mp 5>,
- <&ipmmu_mp 6>, <&ipmmu_mp 7>,
- <&ipmmu_mp 8>, <&ipmmu_mp 9>,
- <&ipmmu_mp 10>, <&ipmmu_mp 11>,
- <&ipmmu_mp 12>, <&ipmmu_mp 13>,
- <&ipmmu_mp 14>, <&ipmmu_mp 15>;
- };
-
- ohci0: usb@ee080000 {
- compatible = "generic-ohci";
- reg = <0 0xee080000 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 1>;
- phy-names = "usb";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- ehci0: usb@ee080100 {
- compatible = "generic-ehci";
- reg = <0 0xee080100 0 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- phys = <&usb2_phy0 2>;
- phy-names = "usb";
- companion = <&ohci0>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- status = "disabled";
- };
-
- usb2_phy0: usb-phy@ee080200 {
- compatible = "renesas,usb2-phy-r8a77995",
- "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee080200 0 0x700>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- sdhi2: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a77995",
- "renesas,rcar-gen3-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77995_CLK_SD0H>;
- clock-names = "core", "clkh";
- max-frequency = <200000000>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- iommus = <&ipmmu_ds1 34>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a77995-rpc-if",
- "renesas,rcar-gen3-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x04000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1010000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1010000 0 0x1000>,
- <0x0 0xf1020000 0 0x20000>,
- <0x0 0xf1040000 0 0x20000>,
- <0x0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
- };
-
- vspbs: vsp@fe960000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe960000 0 0x8000>;
- interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 627>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 627>;
- renesas,fcp = <&fcpvb0>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x5000>;
- interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
- renesas,fcp = <&fcpvd0>;
- };
-
- vspd1: vsp@fea28000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x5000>;
- interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 622>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 622>;
- renesas,fcp = <&fcpvd1>;
- };
-
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 607>;
- iommus = <&ipmmu_vp0 5>;
- };
-
- fcpvd0: fcp@fea27000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea27000 0 0x200>;
- clocks = <&cpg CPG_MOD 603>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 603>;
- iommus = <&ipmmu_vi0 8>;
- };
-
- fcpvd1: fcp@fea2f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea2f000 0 0x200>;
- clocks = <&cpg CPG_MOD 602>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 602>;
- iommus = <&ipmmu_vi0 9>;
- };
-
- cmm0: cmm@fea40000 {
- compatible = "renesas,r8a77995-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea40000 0 0x1000>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 711>;
- resets = <&cpg 711>;
- };
-
- cmm1: cmm@fea50000 {
- compatible = "renesas,r8a77995-cmm",
- "renesas,rcar-gen3-cmm";
- reg = <0 0xfea50000 0 0x1000>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 710>;
- resets = <&cpg 710>;
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a77995";
- reg = <0 0xfeb00000 0 0x40000>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
- clock-names = "du.0", "du.1";
- resets = <&cpg 724>;
- reset-names = "du.0";
-
- renesas,cmms = <&cmm0>, <&cmm1>;
- renesas,vsps = <&vspd0 0>, <&vspd1 0>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
- du_out_lvds0: endpoint {
- remote-endpoint = <&lvds0_in>;
- };
- };
-
- port@2 {
- reg = <2>;
- du_out_lvds1: endpoint {
- remote-endpoint = <&lvds1_in>;
- };
- };
- };
- };
-
- lvds0: lvds-encoder@feb90000 {
- compatible = "renesas,r8a77995-lvds";
- reg = <0 0xfeb90000 0 0x20>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 727>;
- status = "disabled";
-
- renesas,companion = <&lvds1>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds0_in: endpoint {
- remote-endpoint = <&du_out_lvds0>;
- };
- };
-
- port@1 {
- reg = <1>;
- };
- };
- };
-
- lvds1: lvds-encoder@feb90100 {
- compatible = "renesas,r8a77995-lvds";
- reg = <0 0xfeb90100 0 0x20>;
- clocks = <&cpg CPG_MOD 727>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 726>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- lvds1_in: endpoint {
- remote-endpoint = <&du_out_lvds1>;
- };
- };
-
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&thermal>;
-
- cooling-maps {
- };
-
- trips {
- cpu-crit {
- temperature = <120000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Falcon CPU board
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-#include "r8a779a0.dtsi"
-
-/ {
- model = "Renesas Falcon CPU board";
- compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- serial0 = &scif0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&keys_pins>;
- pinctrl-names = "default";
-
- key-1 {
- gpios = <&gpio6 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_1>;
- label = "SW47";
- wakeup-source;
- debounce-interval = <20>;
- };
-
- key-2 {
- gpios = <&gpio6 19 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_2>;
- label = "SW48";
- wakeup-source;
- debounce-interval = <20>;
- };
-
- key-3 {
- gpios = <&gpio6 20 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_3>;
- label = "SW49";
- wakeup-source;
- debounce-interval = <20>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-1 {
- gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <1>;
- };
- led-2 {
- gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <2>;
- };
- led-3 {
- gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <3>;
- };
- };
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-
- memory@500000000 {
- device_type = "memory";
- reg = <0x5 0x00000000 0x0 0x80000000>;
- };
-
- memory@600000000 {
- device_type = "memory";
- reg = <0x6 0x00000000 0x0 0x80000000>;
- };
-
- memory@700000000 {
- device_type = "memory";
- reg = <0x7 0x00000000 0x0 0x80000000>;
- };
-
- mini-dp-con {
- compatible = "dp-connector";
- label = "CN5";
- type = "mini";
-
- port {
- mini_dp_con_in: endpoint {
- remote-endpoint = <&sn65dsi86_out>;
- };
- };
- };
-
- reg_1p2v: regulator-1p2v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sn65dsi86_refclk: clk-x6 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <38400000>;
- };
-};
-
-&dsi0 {
- status = "okay";
-
- ports {
- port@1 {
- dsi0_out: endpoint {
- remote-endpoint = <&sn65dsi86_in>;
- data-lanes = <1 2 3 4>;
- };
- };
- };
-};
-
-&du {
- status = "okay";
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- eeprom@50 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "cpu-board";
- reg = <0x50>;
- pagesize = <8>;
- };
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- bridge@2c {
- pinctrl-0 = <&irq0_pins>;
- pinctrl-names = "default";
-
- compatible = "ti,sn65dsi86";
- reg = <0x2c>;
-
- clocks = <&sn65dsi86_refclk>;
- clock-names = "refclk";
-
- interrupt-parent = <&intc_ex>;
- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
-
- vccio-supply = <®_1p8v>;
- vpll-supply = <®_1p8v>;
- vcca-supply = <®_1p2v>;
- vcc-supply = <®_1p2v>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- sn65dsi86_in: endpoint {
- remote-endpoint = <&dsi0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- sn65dsi86_out: endpoint {
- remote-endpoint = <&mini_dp_con_in>;
- };
- };
- };
- };
-};
-
-&i2c6 {
- pinctrl-0 = <&i2c6_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-};
-
-&mmc0 {
- pinctrl-0 = <&mmc_pins>;
- pinctrl-1 = <&mmc_pins>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- bus-width = <8>;
- no-sd;
- no-sdio;
- non-removable;
- full-pwr-cycle-in-suspend;
- status = "okay";
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- i2c0_pins: i2c0 {
- groups = "i2c0";
- function = "i2c0";
- };
-
- i2c1_pins: i2c1 {
- groups = "i2c1";
- function = "i2c1";
- };
-
- i2c6_pins: i2c6 {
- groups = "i2c6";
- function = "i2c6";
- };
-
- irq0_pins: irq0 {
- groups = "intc_ex_irq0";
- function = "intc_ex";
- };
-
- keys_pins: keys {
- pins = "GP_6_18", "GP_6_19", "GP_6_20";
- bias-pull-up;
- };
-
- mmc_pins: mmc {
- groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
- function = "mmc";
- power-source = <1800>;
- };
-
- qspi0_pins: qspi0 {
- groups = "qspi0_ctrl", "qspi0_data4";
- function = "qspi0";
- };
-
- scif0_pins: scif0 {
- groups = "scif0_data", "scif0_ctrl";
- function = "scif0";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk";
- function = "scif_clk";
- };
-};
-
-&rpc {
- pinctrl-0 = <&qspi0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- flash@0 {
- compatible = "spansion,s25fs512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
- spi-rx-bus-width = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- boot@0 {
- reg = <0x0 0xcc0000>;
- read-only;
- };
- user@cc0000 {
- reg = <0xcc0000 0x3340000>;
- };
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
-
- uart-has-rtscts;
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <24000000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Falcon CSI/DSI sub-board
- *
- * Copyright (C) 2021 Glider bv
- */
-
-#include <dt-bindings/media/video-interfaces.h>
-
-&csi40 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- csi40_in: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&max96712_out0>;
- };
- };
- };
-};
-
-&csi42 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- csi42_in: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&max96712_out1>;
- };
- };
- };
-};
-
-&csi43 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- csi43_in: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&max96712_out2>;
- };
- };
- };
-};
-
-&i2c0 {
- pca9654_a: gpio@21 {
- compatible = "onnn,pca9654";
- reg = <0x21>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- pca9654_b: gpio@22 {
- compatible = "onnn,pca9654";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- pca9654_c: gpio@23 {
- compatible = "onnn,pca9654";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- eeprom@52 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "csi-dsi-sub-board-id";
- reg = <0x52>;
- pagesize = <8>;
- };
-};
-
-&i2c1 {
- gmsl0: gmsl-deserializer@49 {
- compatible = "maxim,max96712";
- reg = <0x49>;
- enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@4 {
- reg = <4>;
- max96712_out0: endpoint {
- bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&csi40_in>;
- };
- };
- };
- };
-
- gmsl1: gmsl-deserializer@4b {
- compatible = "maxim,max96712";
- reg = <0x4b>;
- enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@4 {
- reg = <4>;
- max96712_out1: endpoint {
- bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- lane-polarities = <0 0 0 0 1>;
- remote-endpoint = <&csi42_in>;
- };
- };
- };
- };
-
- gmsl2: gmsl-deserializer@6b {
- compatible = "maxim,max96712";
- reg = <0x6b>;
- enable-gpios = <&pca9654_c 0 GPIO_ACTIVE_HIGH>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@4 {
- reg = <4>;
- max96712_out2: endpoint {
- bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- lane-polarities = <0 0 0 0 1>;
- remote-endpoint = <&csi43_in>;
- };
- };
- };
- };
-};
-
-&isp0 {
- status = "okay";
-};
-
-&isp2 {
- status = "okay";
-};
-
-&isp3 {
- status = "okay";
-};
-
-&vin00 {
- status = "okay";
-};
-
-&vin01 {
- status = "okay";
-};
-
-&vin02 {
- status = "okay";
-};
-
-&vin03 {
- status = "okay";
-};
-
-&vin04 {
- status = "okay";
-};
-
-&vin05 {
- status = "okay";
-};
-
-&vin06 {
- status = "okay";
-};
-
-&vin07 {
- status = "okay";
-};
-
-&vin16 {
- status = "okay";
-};
-
-&vin17 {
- status = "okay";
-};
-
-&vin18 {
- status = "okay";
-};
-
-&vin19 {
- status = "okay";
-};
-
-&vin20 {
- status = "okay";
-};
-
-&vin21 {
- status = "okay";
-};
-
-&vin22 {
- status = "okay";
-};
-
-&vin23 {
- status = "okay";
-};
-
-&vin24 {
- status = "okay";
-};
-
-&vin25 {
- status = "okay";
-};
-
-&vin26 {
- status = "okay";
-};
-
-&vin27 {
- status = "okay";
-};
-
-&vin28 {
- status = "okay";
-};
-
-&vin29 {
- status = "okay";
-};
-
-&vin30 {
- status = "okay";
-};
-
-&vin31 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Falcon Ethernet sub-board
- *
- * Copyright (C) 2021 Glider bv
- */
-
-&i2c0 {
- eeprom@53 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "ethernet-sub-board-id";
- reg = <0x53>;
- pagesize = <8>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a779a0-falcon-cpu.dtsi"
-#include "r8a779a0-falcon-csi-dsi.dtsi"
-#include "r8a779a0-falcon-ethernet.dtsi"
-
-/ {
- model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
- compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
-
- aliases {
- ethernet0 = &avb0;
- };
-};
-
-&avb0 {
- pinctrl-0 = <&avb0_pins>;
- pinctrl-names = "default";
- phy-handle = <&phy0>;
- tx-internal-delay-ps = <2000>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0022.1622",
- "ethernet-phy-ieee802.3-c22";
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio4>;
- interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
- };
-};
-
-&can_clk {
- clock-frequency = <40000000>;
-};
-
-&canfd {
- pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- channel0 {
- status = "okay";
- };
-
- channel1 {
- status = "okay";
- };
-};
-
-&i2c0 {
- eeprom@51 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "breakout-board";
- reg = <0x51>;
- pagesize = <8>;
- };
-};
-
-&pfc {
- avb0_pins: avb0 {
- mux {
- groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
- "avb0_txcrefclk";
- function = "avb0";
- };
-
- pins_mdio {
- groups = "avb0_mdio";
- drive-strength = <21>;
- };
-
- pins_mii {
- groups = "avb0_rgmii";
- drive-strength = <21>;
- };
-
- };
-
- can_clk_pins: can-clk {
- groups = "can_clk";
- function = "can_clk";
- };
-
- canfd0_pins: canfd0 {
- groups = "canfd0_data";
- function = "canfd0";
- };
-
- canfd1_pins: canfd1 {
- groups = "canfd1_data";
- function = "canfd1";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car V3U (R8A779A0) SoC
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a779a0-sysc.h>
-
-/ {
- compatible = "renesas,r8a779a0";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- a76_0: cpu@0 {
- compatible = "arm,cortex-a76";
- reg = <0>;
- device_type = "cpu";
- power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
- next-level-cache = <&L3_CA76_0>;
- clocks = <&cpg CPG_CORE R8A779A0_CLK_Z0>;
- };
-
- L3_CA76_0: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A779A0_PD_A2E0D0>;
- cache-unified;
- cache-level = <3>;
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- extalr_clk: extalr {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- pmu_a76 {
- compatible = "arm,cortex-a76-pmu";
- interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc: soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a779a0-wdt",
- "renesas,rcar-gen4-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- status = "disabled";
- };
-
- pfc: pinctrl@e6050000 {
- compatible = "renesas,pfc-r8a779a0";
- reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
- <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
- <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
- <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
- <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
- };
-
- gpio0: gpio@e6058180 {
- compatible = "renesas,gpio-r8a779a0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6058180 0 0x54>;
- interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 0 28>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@e6050180 {
- compatible = "renesas,gpio-r8a779a0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6050180 0 0x54>;
- interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 32 31>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@e6050980 {
- compatible = "renesas,gpio-r8a779a0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6050980 0 0x54>;
- interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 64 25>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@e6058980 {
- compatible = "renesas,gpio-r8a779a0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6058980 0 0x54>;
- interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 96 17>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@e6060180 {
- compatible = "renesas,gpio-r8a779a0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6060180 0 0x54>;
- interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 128 27>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio5: gpio@e6060980 {
- compatible = "renesas,gpio-r8a779a0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6060980 0 0x54>;
- interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 160 21>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio6: gpio@e6068180 {
- compatible = "renesas,gpio-r8a779a0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6068180 0 0x54>;
- interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 192 21>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio7: gpio@e6068980 {
- compatible = "renesas,gpio-r8a779a0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6068980 0 0x54>;
- interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 224 21>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio8: gpio@e6069180 {
- compatible = "renesas,gpio-r8a779a0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6069180 0 0x54>;
- interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 256 21>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio9: gpio@e6069980 {
- compatible = "renesas,gpio-r8a779a0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6069980 0 0x54>;
- interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 288 21>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a779a0-cmt0",
- "renesas,rcar-gen4-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 910>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a779a0-cmt1",
- "renesas,rcar-gen4-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 911>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a779a0-cmt1",
- "renesas,rcar-gen4-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 912>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a779a0-cmt1",
- "renesas,rcar-gen4-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 913>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 913>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a779a0-cpg-mssr";
- reg = <0 0xe6150000 0 0x4000>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a779a0-rst";
- reg = <0 0xe6160000 0 0x4000>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a779a0-sysc";
- reg = <0 0xe6180000 0 0x4000>;
- #power-domain-cells = <1>;
- };
-
- tsc: thermal@e6190000 {
- compatible = "renesas,r8a779a0-thermal";
- reg = <0 0xe6190000 0 0x200>,
- <0 0xe6198000 0 0x200>,
- <0 0xe61a0000 0 0x200>,
- <0 0xe61a8000 0 0x200>,
- <0 0xe61b0000 0 0x200>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- #thermal-sensor-cells = <1>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a779a0", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_CORE R8A779A0_CLK_CP>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 713>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 713>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 715>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 715>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a779a0", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 717>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 717>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- compatible = "renesas,i2c-r8a779a0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- dmas = <&dmac1 0x91>, <&dmac1 0x90>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- compatible = "renesas,i2c-r8a779a0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- dmas = <&dmac1 0x93>, <&dmac1 0x92>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- compatible = "renesas,i2c-r8a779a0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- dmas = <&dmac1 0x95>, <&dmac1 0x94>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- compatible = "renesas,i2c-r8a779a0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 521>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 521>;
- dmas = <&dmac1 0x97>, <&dmac1 0x96>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- compatible = "renesas,i2c-r8a779a0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- dmas = <&dmac1 0x99>, <&dmac1 0x98>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c5: i2c@e66e0000 {
- compatible = "renesas,i2c-r8a779a0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe66e0000 0 0x40>;
- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- dmas = <&dmac1 0x9b>, <&dmac1 0x9a>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c6: i2c@e66e8000 {
- compatible = "renesas,i2c-r8a779a0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe66e8000 0 0x40>;
- interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 524>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 524>;
- dmas = <&dmac1 0x9d>, <&dmac1 0x9c>;
- dma-names = "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a779a0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 514>,
- <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x31>, <&dmac1 0x30>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 514>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a779a0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe6550000 0 0x60>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 515>,
- <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x33>, <&dmac1 0x32>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 515>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a779a0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe6560000 0 0x60>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x35>, <&dmac1 0x34>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 516>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a779a0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe66a0000 0 0x60>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x37>, <&dmac1 0x36>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- canfd: can@e6660000 {
- compatible = "renesas,r8a779a0-canfd",
- "renesas,rcar-gen4-canfd";
- reg = <0 0xe6660000 0 0x8000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 328>,
- <&cpg CPG_CORE R8A779A0_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A779A0_CLK_CANFD>;
- assigned-clock-rates = <80000000>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
-
- channel2 {
- status = "disabled";
- };
-
- channel3 {
- status = "disabled";
- };
-
- channel4 {
- status = "disabled";
- };
-
- channel5 {
- status = "disabled";
- };
-
- channel6 {
- status = "disabled";
- };
-
- channel7 {
- status = "disabled";
- };
- };
-
- avb0: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen4";
- reg = <0 0xe6800000 0 0x800>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 211>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- avb1: ethernet@e6810000 {
- compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen4";
- reg = <0 0xe6810000 0 0x800>;
- interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 212>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 212>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- avb2: ethernet@e6820000 {
- compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen4";
- reg = <0 0xe6820000 0 0x1000>;
- interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 213>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 213>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- avb3: ethernet@e6830000 {
- compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen4";
- reg = <0 0xe6830000 0 0x1000>;
- interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 214>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 214>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- avb4: ethernet@e6840000 {
- compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen4";
- reg = <0 0xe6840000 0 0x1000>;
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 215>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 215>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- avb5: ethernet@e6850000 {
- compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen4";
- reg = <0 0xe6850000 0 0x1000>;
- interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19",
- "ch20", "ch21", "ch22", "ch23",
- "ch24";
- clocks = <&cpg CPG_MOD 216>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 216>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a779a0",
- "renesas,rcar-gen4-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>,
- <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x51>, <&dmac1 0x50>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a779a0",
- "renesas,rcar-gen4-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>,
- <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x53>, <&dmac1 0x52>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a779a0",
- "renesas,rcar-gen4-scif", "renesas,scif";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>,
- <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x57>, <&dmac1 0x56>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a779a0",
- "renesas,rcar-gen4-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 705>,
- <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x59>, <&dmac1 0x58>;
- dma-names = "tx", "rx";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 705>;
- status = "disabled";
- };
-
- tpu: pwm@e6e80000 {
- compatible = "renesas,tpu-r8a779a0", "renesas,tpu";
- reg = <0 0xe6e80000 0 0x148>;
- interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 718>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 718>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6e90000 0 0x0064>;
- interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 618>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 618>;
- dmas = <&dmac1 0x41>, <&dmac1 0x40>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 619>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 619>;
- dmas = <&dmac1 0x43>, <&dmac1 0x42>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 620>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 620>;
- dmas = <&dmac1 0x45>, <&dmac1 0x44>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 621>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 621>;
- dmas = <&dmac1 0x47>, <&dmac1 0x46>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof4: spi@e6c20000 {
- compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6c20000 0 0x0064>;
- interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 622>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 622>;
- dmas = <&dmac1 0x49>, <&dmac1 0x48>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof5: spi@e6c28000 {
- compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6c28000 0 0x0064>;
- interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
- dmas = <&dmac1 0x4b>, <&dmac1 0x4a>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin00: video@e6ef0000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 730>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 730>;
- renesas,id = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin00isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin00>;
- };
- };
- };
- };
-
- vin01: video@e6ef1000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 731>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 731>;
- renesas,id = <1>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin01isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin01>;
- };
- };
- };
- };
-
- vin02: video@e6ef2000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 800>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 800>;
- renesas,id = <2>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin02isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin02>;
- };
- };
- };
- };
-
- vin03: video@e6ef3000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 801>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 801>;
- renesas,id = <3>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin03isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin03>;
- };
- };
- };
- };
-
- vin04: video@e6ef4000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 802>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 802>;
- renesas,id = <4>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin04isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin04>;
- };
- };
- };
- };
-
- vin05: video@e6ef5000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ef5000 0 0x1000>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 803>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 803>;
- renesas,id = <5>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin05isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin05>;
- };
- };
- };
- };
-
- vin06: video@e6ef6000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ef6000 0 0x1000>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 804>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 804>;
- renesas,id = <6>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin06isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin06>;
- };
- };
- };
- };
-
- vin07: video@e6ef7000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ef7000 0 0x1000>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 805>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 805>;
- renesas,id = <7>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin07isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin07>;
- };
- };
- };
- };
-
- vin08: video@e6ef8000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ef8000 0 0x1000>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 806>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 806>;
- renesas,id = <8>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin08isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin08>;
- };
- };
- };
- };
-
- vin09: video@e6ef9000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ef9000 0 0x1000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 807>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 807>;
- renesas,id = <9>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin09isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin09>;
- };
- };
- };
- };
-
- vin10: video@e6efa000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6efa000 0 0x1000>;
- interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- renesas,id = <10>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin10isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin10>;
- };
- };
- };
- };
-
- vin11: video@e6efb000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6efb000 0 0x1000>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- renesas,id = <11>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin11isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin11>;
- };
- };
- };
- };
-
- vin12: video@e6efc000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6efc000 0 0x1000>;
- interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- renesas,id = <12>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin12isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin12>;
- };
- };
- };
- };
-
- vin13: video@e6efd000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6efd000 0 0x1000>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- renesas,id = <13>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin13isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin13>;
- };
- };
- };
- };
-
- vin14: video@e6efe000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6efe000 0 0x1000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 812>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- renesas,id = <14>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin14isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin14>;
- };
- };
- };
- };
-
- vin15: video@e6eff000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6eff000 0 0x1000>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- renesas,id = <15>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin15isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin15>;
- };
- };
- };
- };
-
- vin16: video@e6ed0000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ed0000 0 0x1000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 814>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 814>;
- renesas,id = <16>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin16isp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&isp2vin16>;
- };
- };
- };
- };
-
- vin17: video@e6ed1000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ed1000 0 0x1000>;
- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 815>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 815>;
- renesas,id = <17>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin17isp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&isp2vin17>;
- };
- };
- };
- };
-
- vin18: video@e6ed2000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ed2000 0 0x1000>;
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 816>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 816>;
- renesas,id = <18>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin18isp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&isp2vin18>;
- };
- };
- };
- };
-
- vin19: video@e6ed3000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ed3000 0 0x1000>;
- interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 817>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 817>;
- renesas,id = <19>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin19isp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&isp2vin19>;
- };
- };
- };
- };
-
- vin20: video@e6ed4000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ed4000 0 0x1000>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 818>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 818>;
- renesas,id = <20>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin20isp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&isp2vin20>;
- };
- };
- };
- };
-
- vin21: video@e6ed5000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ed5000 0 0x1000>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 819>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 819>;
- renesas,id = <21>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin21isp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&isp2vin21>;
- };
- };
- };
- };
-
- vin22: video@e6ed6000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ed6000 0 0x1000>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 820>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 820>;
- renesas,id = <22>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin22isp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&isp2vin22>;
- };
- };
- };
- };
-
- vin23: video@e6ed7000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ed7000 0 0x1000>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 821>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 821>;
- renesas,id = <23>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin23isp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&isp2vin23>;
- };
- };
- };
- };
-
- vin24: video@e6ed8000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ed8000 0 0x1000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 822>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 822>;
- renesas,id = <24>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin24isp3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&isp3vin24>;
- };
- };
- };
- };
-
- vin25: video@e6ed9000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ed9000 0 0x1000>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 823>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 823>;
- renesas,id = <25>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin25isp3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&isp3vin25>;
- };
- };
- };
- };
-
- vin26: video@e6eda000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6eda000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 824>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 824>;
- renesas,id = <26>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin26isp3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&isp3vin26>;
- };
- };
- };
- };
-
- vin27: video@e6edb000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6edb000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 825>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 825>;
- renesas,id = <27>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin27isp3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&isp3vin27>;
- };
- };
- };
- };
-
- vin28: video@e6edc000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6edc000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 826>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 826>;
- renesas,id = <28>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin28isp3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&isp3vin28>;
- };
- };
- };
- };
-
- vin29: video@e6edd000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6edd000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 827>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 827>;
- renesas,id = <29>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin29isp3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&isp3vin29>;
- };
- };
- };
- };
-
- vin30: video@e6ede000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6ede000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 828>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 828>;
- renesas,id = <30>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin30isp3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&isp3vin30>;
- };
- };
- };
- };
-
- vin31: video@e6edf000 {
- compatible = "renesas,vin-r8a779a0";
- reg = <0 0xe6edf000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 829>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 829>;
- renesas,id = <31>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin31isp3: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&isp3vin31>;
- };
- };
- };
- };
-
- dmac1: dma-controller@e7350000 {
- compatible = "renesas,dmac-r8a779a0",
- "renesas,rcar-gen4-dmac";
- reg = <0 0xe7350000 0 0x1000>,
- <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3", "ch4",
- "ch5", "ch6", "ch7", "ch8", "ch9",
- "ch10", "ch11", "ch12", "ch13",
- "ch14", "ch15";
- clocks = <&cpg CPG_MOD 709>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 709>;
- #dma-cells = <1>;
- dma-channels = <16>;
- };
-
- dmac2: dma-controller@e7351000 {
- compatible = "renesas,dmac-r8a779a0",
- "renesas,rcar-gen4-dmac";
- reg = <0 0xe7351000 0 0x1000>,
- <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3", "ch4",
- "ch5", "ch6", "ch7";
- clocks = <&cpg CPG_MOD 710>;
- clock-names = "fck";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 710>;
- #dma-cells = <1>;
- dma-channels = <8>;
- };
-
- mmc0: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a779a0",
- "renesas,rcar-gen4-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779A0_CLK_SD0H>;
- clock-names = "core", "clkh";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 706>;
- max-frequency = <200000000>;
- iommus = <&ipmmu_ds0 32>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a779a0-rpc-if",
- "renesas,rcar-gen3-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x04000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 629>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 629>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ipmmu_rt0: iommu@ee480000 {
- compatible = "renesas,ipmmu-r8a779a0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xee480000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_rt1: iommu@ee4c0000 {
- compatible = "renesas,ipmmu-r8a779a0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xee4c0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds0: iommu@eed00000 {
- compatible = "renesas,ipmmu-r8a779a0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeed00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds1: iommu@eed40000 {
- compatible = "renesas,ipmmu-r8a779a0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeed40000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ir: iommu@eed80000 {
- compatible = "renesas,ipmmu-r8a779a0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeed80000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779A0_PD_A3IR>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: iommu@eedc0000 {
- compatible = "renesas,ipmmu-r8a779a0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeedc0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@eee80000 {
- compatible = "renesas,ipmmu-r8a779a0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeee80000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi1: iommu@eeec0000 {
- compatible = "renesas,ipmmu-r8a779a0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeeec0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_3dg: iommu@eee00000 {
- compatible = "renesas,ipmmu-r8a779a0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeee00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vip0: iommu@eef00000 {
- compatible = "renesas,ipmmu-r8a779a0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeef00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vip1: iommu@eef40000 {
- compatible = "renesas,ipmmu-r8a779a0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeef40000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@eefc0000 {
- compatible = "renesas,ipmmu-r8a779a0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeefc0000 0 0x20000>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- gic: interrupt-controller@f1000000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1000000 0 0x20000>,
- <0x0 0xf1060000 0 0x110000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- fcpvd0: fcp@fea10000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea10000 0 0x200>;
- clocks = <&cpg CPG_MOD 508>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 508>;
- };
-
- fcpvd1: fcp@fea11000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea11000 0 0x200>;
- clocks = <&cpg CPG_MOD 509>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 509>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x5000>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 830>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 830>;
-
- renesas,fcp = <&fcpvd0>;
- };
-
- vspd1: vsp@fea28000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x5000>;
- interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 831>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 831>;
-
- renesas,fcp = <&fcpvd1>;
- };
-
- csi40: csi2@feaa0000 {
- compatible = "renesas,r8a779a0-csi2";
- reg = <0 0xfeaa0000 0 0x10000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
- csi40isp0: endpoint {
- remote-endpoint = <&isp0csi40>;
- };
- };
- };
- };
-
- csi41: csi2@feab0000 {
- compatible = "renesas,r8a779a0-csi2";
- reg = <0 0xfeab0000 0 0x10000>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 400>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 400>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
- csi41isp1: endpoint {
- remote-endpoint = <&isp1csi41>;
- };
- };
- };
- };
-
- csi42: csi2@fed60000 {
- compatible = "renesas,r8a779a0-csi2";
- reg = <0 0xfed60000 0 0x10000>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 401>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 401>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
- csi42isp2: endpoint {
- remote-endpoint = <&isp2csi42>;
- };
- };
- };
- };
-
- csi43: csi2@fed70000 {
- compatible = "renesas,r8a779a0-csi2";
- reg = <0 0xfed70000 0 0x10000>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 402>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 402>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
- csi43isp3: endpoint {
- remote-endpoint = <&isp3csi43>;
- };
- };
- };
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a779a0";
- reg = <0 0xfeb00000 0 0x40000>;
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 411>;
- clock-names = "du.0";
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 411>;
- reset-names = "du.0";
- renesas,vsps = <&vspd0 0>, <&vspd1 0>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- du_out_dsi0: endpoint {
- remote-endpoint = <&dsi0_in>;
- };
- };
-
- port@1 {
- reg = <1>;
- du_out_dsi1: endpoint {
- remote-endpoint = <&dsi1_in>;
- };
- };
- };
- };
-
- isp0: isp@fed00000 {
- compatible = "renesas,r8a779a0-isp";
- reg = <0 0xfed00000 0 0x10000>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 612>;
- power-domains = <&sysc R8A779A0_PD_A3ISP01>;
- resets = <&cpg 612>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <0>;
-
- isp0csi40: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi40isp0>;
- };
- };
-
- port@1 {
- reg = <1>;
- isp0vin00: endpoint {
- remote-endpoint = <&vin00isp0>;
- };
- };
-
- port@2 {
- reg = <2>;
- isp0vin01: endpoint {
- remote-endpoint = <&vin01isp0>;
- };
- };
-
- port@3 {
- reg = <3>;
- isp0vin02: endpoint {
- remote-endpoint = <&vin02isp0>;
- };
- };
-
- port@4 {
- reg = <4>;
- isp0vin03: endpoint {
- remote-endpoint = <&vin03isp0>;
- };
- };
-
- port@5 {
- reg = <5>;
- isp0vin04: endpoint {
- remote-endpoint = <&vin04isp0>;
- };
- };
-
- port@6 {
- reg = <6>;
- isp0vin05: endpoint {
- remote-endpoint = <&vin05isp0>;
- };
- };
-
- port@7 {
- reg = <7>;
- isp0vin06: endpoint {
- remote-endpoint = <&vin06isp0>;
- };
- };
-
- port@8 {
- reg = <8>;
- isp0vin07: endpoint {
- remote-endpoint = <&vin07isp0>;
- };
- };
- };
- };
-
- isp1: isp@fed20000 {
- compatible = "renesas,r8a779a0-isp";
- reg = <0 0xfed20000 0 0x10000>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 613>;
- power-domains = <&sysc R8A779A0_PD_A3ISP01>;
- resets = <&cpg 613>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <0>;
-
- isp1csi41: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csi41isp1>;
- };
- };
-
- port@1 {
- reg = <1>;
- isp1vin08: endpoint {
- remote-endpoint = <&vin08isp1>;
- };
- };
-
- port@2 {
- reg = <2>;
- isp1vin09: endpoint {
- remote-endpoint = <&vin09isp1>;
- };
- };
-
- port@3 {
- reg = <3>;
- isp1vin10: endpoint {
- remote-endpoint = <&vin10isp1>;
- };
- };
-
- port@4 {
- reg = <4>;
- isp1vin11: endpoint {
- remote-endpoint = <&vin11isp1>;
- };
- };
-
- port@5 {
- reg = <5>;
- isp1vin12: endpoint {
- remote-endpoint = <&vin12isp1>;
- };
- };
-
- port@6 {
- reg = <6>;
- isp1vin13: endpoint {
- remote-endpoint = <&vin13isp1>;
- };
- };
-
- port@7 {
- reg = <7>;
- isp1vin14: endpoint {
- remote-endpoint = <&vin14isp1>;
- };
- };
-
- port@8 {
- reg = <8>;
- isp1vin15: endpoint {
- remote-endpoint = <&vin15isp1>;
- };
- };
- };
- };
-
- isp2: isp@fed30000 {
- compatible = "renesas,r8a779a0-isp";
- reg = <0 0xfed30000 0 0x10000>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 614>;
- power-domains = <&sysc R8A779A0_PD_A3ISP23>;
- resets = <&cpg 614>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <0>;
-
- isp2csi42: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi42isp2>;
- };
- };
-
- port@1 {
- reg = <1>;
- isp2vin16: endpoint {
- remote-endpoint = <&vin16isp2>;
- };
- };
-
- port@2 {
- reg = <2>;
- isp2vin17: endpoint {
- remote-endpoint = <&vin17isp2>;
- };
- };
-
- port@3 {
- reg = <3>;
- isp2vin18: endpoint {
- remote-endpoint = <&vin18isp2>;
- };
- };
-
- port@4 {
- reg = <4>;
- isp2vin19: endpoint {
- remote-endpoint = <&vin19isp2>;
- };
- };
-
- port@5 {
- reg = <5>;
- isp2vin20: endpoint {
- remote-endpoint = <&vin20isp2>;
- };
- };
-
- port@6 {
- reg = <6>;
- isp2vin21: endpoint {
- remote-endpoint = <&vin21isp2>;
- };
- };
-
- port@7 {
- reg = <7>;
- isp2vin22: endpoint {
- remote-endpoint = <&vin22isp2>;
- };
- };
-
- port@8 {
- reg = <8>;
- isp2vin23: endpoint {
- remote-endpoint = <&vin23isp2>;
- };
- };
- };
- };
-
- isp3: isp@fed40000 {
- compatible = "renesas,r8a779a0-isp";
- reg = <0 0xfed40000 0 0x10000>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 615>;
- power-domains = <&sysc R8A779A0_PD_A3ISP23>;
- resets = <&cpg 615>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <0>;
-
- isp3csi43: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csi43isp3>;
- };
- };
-
- port@1 {
- reg = <1>;
- isp3vin24: endpoint {
- remote-endpoint = <&vin24isp3>;
- };
- };
-
- port@2 {
- reg = <2>;
- isp3vin25: endpoint {
- remote-endpoint = <&vin25isp3>;
- };
- };
-
- port@3 {
- reg = <3>;
- isp3vin26: endpoint {
- remote-endpoint = <&vin26isp3>;
- };
- };
-
- port@4 {
- reg = <4>;
- isp3vin27: endpoint {
- remote-endpoint = <&vin27isp3>;
- };
- };
-
- port@5 {
- reg = <5>;
- isp3vin28: endpoint {
- remote-endpoint = <&vin28isp3>;
- };
- };
-
- port@6 {
- reg = <6>;
- isp3vin29: endpoint {
- remote-endpoint = <&vin29isp3>;
- };
- };
-
- port@7 {
- reg = <7>;
- isp3vin30: endpoint {
- remote-endpoint = <&vin30isp3>;
- };
- };
-
- port@8 {
- reg = <8>;
- isp3vin31: endpoint {
- remote-endpoint = <&vin31isp3>;
- };
- };
- };
- };
-
- dsi0: dsi-encoder@fed80000 {
- compatible = "renesas,r8a779a0-dsi-csi2-tx";
- reg = <0 0xfed80000 0 0x10000>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 415>,
- <&cpg CPG_CORE R8A779A0_CLK_DSI>,
- <&cpg CPG_CORE R8A779A0_CLK_CL16MCK>;
- clock-names = "fck", "dsi", "pll";
- resets = <&cpg 415>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi0_in: endpoint {
- remote-endpoint = <&du_out_dsi0>;
- };
- };
-
- port@1 {
- reg = <1>;
- };
- };
- };
-
- dsi1: dsi-encoder@fed90000 {
- compatible = "renesas,r8a779a0-dsi-csi2-tx";
- reg = <0 0xfed90000 0 0x10000>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- clocks = <&cpg CPG_MOD 416>,
- <&cpg CPG_CORE R8A779A0_CLK_DSI>,
- <&cpg CPG_CORE R8A779A0_CLK_CL16MCK>;
- clock-names = "fck", "dsi", "pll";
- resets = <&cpg 416>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi1_in: endpoint {
- remote-endpoint = <&du_out_dsi1>;
- };
- };
-
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- sensor1_thermal: sensor1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 0>;
-
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor2_thermal: sensor2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 1>;
-
- trips {
- sensor2_crit: sensor2-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor3_thermal: sensor3-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 2>;
-
- trips {
- sensor3_crit: sensor3-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor4_thermal: sensor4-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 3>;
-
- trips {
- sensor4_crit: sensor4-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor5_thermal: sensor5-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 4>;
-
- trips {
- sensor5_crit: sensor5-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Device Tree Source for the Spider CPU board
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-#include "r8a779f0.dtsi"
-
-/ {
- model = "Renesas Spider CPU board";
- compatible = "renesas,spider-cpu", "renesas,r8a779f0";
-
- aliases {
- serial0 = &hscif0;
- serial1 = &scif0;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:1843200n8";
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-7 {
- gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <7>;
- };
-
- led-8 {
- gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <8>;
- };
- };
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-
- memory@480000000 {
- device_type = "memory";
- reg = <0x4 0x80000000 0x0 0x80000000>;
- };
-
- rc21012_ufs: clk-rc21012-ufs {
- compatible = "fixed-clock";
- clock-frequency = <38400000>;
- #clock-cells = <0>;
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&extal_clk {
- clock-frequency = <20000000>;
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&hscif0 {
- pinctrl-0 = <&hscif0_pins>;
- pinctrl-names = "default";
-
- uart-has-rtscts;
- status = "okay";
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- gpio_exp_20: gpio@20 {
- compatible = "ti,tca9554";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&i2c4 {
- pinctrl-0 = <&i2c4_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- eeprom@50 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "cpu-board";
- reg = <0x50>;
- pagesize = <8>;
- };
-};
-
-/*
- * This board also has a microSD slot which we will not support upstream
- * because we cannot directly switch voltages in software.
- */
-&mmc0 {
- pinctrl-0 = <&mmc_pins>;
- pinctrl-1 = <&mmc_pins>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- bus-width = <8>;
- no-sd;
- no-sdio;
- non-removable;
- full-pwr-cycle-in-suspend;
- status = "okay";
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- hscif0_pins: hscif0 {
- groups = "hscif0_data", "hscif0_ctrl";
- function = "hscif0";
- };
-
- i2c0_pins: i2c0 {
- groups = "i2c0";
- function = "i2c0";
- };
-
- i2c4_pins: i2c4 {
- groups = "i2c4";
- function = "i2c4";
- };
-
- mmc_pins: mmc {
- groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
- function = "mmc";
- power-source = <1800>;
- };
-
- scif0_pins: scif0 {
- groups = "scif0_data", "scif0_ctrl";
- function = "scif0";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk";
- function = "scif_clk";
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
-
- uart-has-rtscts;
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <24000000>;
-};
-
-&ufs {
- status = "okay";
-};
-
-&ufs30_clk {
- compatible = "gpio-gate-clock";
- clocks = <&rc21012_ufs>;
- enable-gpios = <&gpio_exp_20 4 GPIO_ACTIVE_LOW>;
- /delete-property/ clock-frequency;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Spider Ethernet sub-board
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-ð_serdes {
- status = "okay";
-};
-
-&i2c4 {
- eeprom@52 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "ethernet-sub-board";
- reg = <0x52>;
- pagesize = <8>;
- };
-};
-
-&pfc {
- tsn0_pins: tsn0 {
- groups = "tsn0_mdio_b", "tsn0_link_b";
- function = "tsn0";
- power-source = <1800>;
- };
-
- tsn1_pins: tsn1 {
- groups = "tsn1_mdio_b", "tsn1_link_b";
- function = "tsn1";
- power-source = <1800>;
- };
-
- tsn2_pins: tsn2 {
- groups = "tsn2_mdio_b", "tsn2_link_b";
- function = "tsn2";
- power-source = <1800>;
- };
-};
-
-&rswitch {
- pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- phy-handle = <&u101>;
- phy-mode = "sgmii";
- phys = <ð_serdes 0>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- u101: ethernet-phy@1 {
- reg = <1>;
- compatible = "ethernet-phy-ieee802.3-c45";
- interrupt-parent = <&gpio3>;
- interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
- };
- };
- };
- port@1 {
- reg = <1>;
- phy-handle = <&u201>;
- phy-mode = "sgmii";
- phys = <ð_serdes 1>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- u201: ethernet-phy@2 {
- reg = <2>;
- compatible = "ethernet-phy-ieee802.3-c45";
- interrupt-parent = <&gpio3>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- };
- };
- };
- port@2 {
- reg = <2>;
- phy-handle = <&u301>;
- phy-mode = "sgmii";
- phys = <ð_serdes 2>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- u301: ethernet-phy@3 {
- reg = <3>;
- compatible = "ethernet-phy-ieee802.3-c45";
- interrupt-parent = <&gpio3>;
- interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
- };
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Device Tree Source for the Spider CPU and BreakOut boards
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a779f0-spider-cpu.dtsi"
-#include "r8a779f0-spider-ethernet.dtsi"
-
-/ {
- model = "Renesas Spider CPU and Breakout boards based on r8a779f0";
- compatible = "renesas,spider-breakout", "renesas,spider-cpu", "renesas,r8a779f0";
-};
-
-&i2c4 {
- eeprom@51 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "breakout-board";
- reg = <0x51>;
- pagesize = <8>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a779f0-sysc.h>
-
-/ {
- compatible = "renesas,r8a779f0";
- #address-cells = <2>;
- #size-cells = <2>;
-
- cluster01_opp: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <880000>;
- clock-latency-ns = <500000>;
- };
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <880000>;
- clock-latency-ns = <500000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <880000>;
- clock-latency-ns = <500000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <880000>;
- clock-latency-ns = <500000>;
- opp-suspend;
- };
- };
-
- cluster23_opp: opp-table-1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <880000>;
- clock-latency-ns = <500000>;
- };
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <880000>;
- clock-latency-ns = <500000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <880000>;
- clock-latency-ns = <500000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <880000>;
- clock-latency-ns = <500000>;
- opp-suspend;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&a55_0>;
- };
- core1 {
- cpu = <&a55_1>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&a55_2>;
- };
- core1 {
- cpu = <&a55_3>;
- };
- };
-
- cluster2 {
- core0 {
- cpu = <&a55_4>;
- };
- core1 {
- cpu = <&a55_5>;
- };
- };
-
- cluster3 {
- core0 {
- cpu = <&a55_6>;
- };
- core1 {
- cpu = <&a55_7>;
- };
- };
- };
-
- a55_0: cpu@0 {
- compatible = "arm,cortex-a55";
- reg = <0>;
- device_type = "cpu";
- power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
- next-level-cache = <&L3_CA55_0>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
- operating-points-v2 = <&cluster01_opp>;
- };
-
- a55_1: cpu@100 {
- compatible = "arm,cortex-a55";
- reg = <0x100>;
- device_type = "cpu";
- power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
- next-level-cache = <&L3_CA55_0>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
- operating-points-v2 = <&cluster01_opp>;
- };
-
- a55_2: cpu@10000 {
- compatible = "arm,cortex-a55";
- reg = <0x10000>;
- device_type = "cpu";
- power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
- next-level-cache = <&L3_CA55_1>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
- operating-points-v2 = <&cluster01_opp>;
- };
-
- a55_3: cpu@10100 {
- compatible = "arm,cortex-a55";
- reg = <0x10100>;
- device_type = "cpu";
- power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
- next-level-cache = <&L3_CA55_1>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
- operating-points-v2 = <&cluster01_opp>;
- };
-
- a55_4: cpu@20000 {
- compatible = "arm,cortex-a55";
- reg = <0x20000>;
- device_type = "cpu";
- power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
- next-level-cache = <&L3_CA55_2>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
- operating-points-v2 = <&cluster23_opp>;
- };
-
- a55_5: cpu@20100 {
- compatible = "arm,cortex-a55";
- reg = <0x20100>;
- device_type = "cpu";
- power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
- next-level-cache = <&L3_CA55_2>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
- operating-points-v2 = <&cluster23_opp>;
- };
-
- a55_6: cpu@30000 {
- compatible = "arm,cortex-a55";
- reg = <0x30000>;
- device_type = "cpu";
- power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
- next-level-cache = <&L3_CA55_3>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
- operating-points-v2 = <&cluster23_opp>;
- };
-
- a55_7: cpu@30100 {
- compatible = "arm,cortex-a55";
- reg = <0x30100>;
- device_type = "cpu";
- power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
- next-level-cache = <&L3_CA55_3>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
- operating-points-v2 = <&cluster23_opp>;
- };
-
- L3_CA55_0: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A779F0_PD_A2E0D0>;
- cache-unified;
- cache-level = <3>;
- };
-
- L3_CA55_1: cache-controller-1 {
- compatible = "cache";
- power-domains = <&sysc R8A779F0_PD_A2E0D1>;
- cache-unified;
- cache-level = <3>;
- };
-
- L3_CA55_2: cache-controller-2 {
- compatible = "cache";
- power-domains = <&sysc R8A779F0_PD_A2E1D0>;
- cache-unified;
- cache-level = <3>;
- };
-
- L3_CA55_3: cache-controller-3 {
- compatible = "cache";
- power-domains = <&sysc R8A779F0_PD_A2E1D1>;
- cache-unified;
- cache-level = <3>;
- };
-
- idle-states {
- entry-method = "psci";
-
- CPU_SLEEP_0: cpu-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- local-timer-stop;
- entry-latency-us = <400>;
- exit-latency-us = <500>;
- min-residency-us = <4000>;
- };
- };
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- extalr_clk: extalr {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- pmu_a55 {
- compatible = "arm,cortex-a55-pmu";
- interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc: soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a779f0-wdt",
- "renesas,rcar-gen4-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- status = "disabled";
- };
-
- pfc: pinctrl@e6050000 {
- compatible = "renesas,pfc-r8a779f0";
- reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
- <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
- };
-
- gpio0: gpio@e6050180 {
- compatible = "renesas,gpio-r8a779f0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6050180 0 0x54>;
- interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 0 21>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@e6050980 {
- compatible = "renesas,gpio-r8a779f0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6050980 0 0x54>;
- interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 32 25>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@e6051180 {
- compatible = "renesas,gpio-r8a779f0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6051180 0 0x54>;
- interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 64 17>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@e6051980 {
- compatible = "renesas,gpio-r8a779f0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6051980 0 0x54>;
- interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 96 19>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a779f0-cmt0",
- "renesas,rcar-gen4-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 910>;
- clock-names = "fck";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a779f0-cmt1",
- "renesas,rcar-gen4-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 911>;
- clock-names = "fck";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a779f0-cmt1",
- "renesas,rcar-gen4-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 912>;
- clock-names = "fck";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a779f0-cmt1",
- "renesas,rcar-gen4-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 913>;
- clock-names = "fck";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 913>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a779f0-cpg-mssr";
- reg = <0 0xe6150000 0 0x4000>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a779f0-rst";
- reg = <0 0xe6160000 0 0x4000>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a779f0-sysc";
- reg = <0 0xe6180000 0 0x4000>;
- #power-domain-cells = <1>;
- };
-
- tsc: thermal@e6198000 {
- compatible = "renesas,r8a779f0-thermal";
- /* The 4th sensor is in control domain and not for Linux */
- reg = <0 0xe6198000 0 0x200>,
- <0 0xe61a0000 0 0x200>,
- <0 0xe61a8000 0 0x200>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- #thermal-sensor-cells = <1>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_CORE R8A779F0_CLK_CL16M>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 713>;
- clock-names = "fck";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 713>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>;
- clock-names = "fck";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 715>;
- clock-names = "fck";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 715>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- clock-names = "fck";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 717>;
- clock-names = "fck";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 717>;
- status = "disabled";
- };
-
- eth_serdes: phy@e6444000 {
- compatible = "renesas,r8a779f0-ether-serdes";
- reg = <0 0xe6444000 0 0x2800>;
- clocks = <&cpg CPG_MOD 1506>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 1506>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- compatible = "renesas,i2c-r8a779f0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- dmas = <&dmac0 0x91>, <&dmac0 0x90>,
- <&dmac1 0x91>, <&dmac1 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- compatible = "renesas,i2c-r8a779f0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- dmas = <&dmac0 0x93>, <&dmac0 0x92>,
- <&dmac1 0x93>, <&dmac1 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- compatible = "renesas,i2c-r8a779f0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- dmas = <&dmac0 0x95>, <&dmac0 0x94>,
- <&dmac1 0x95>, <&dmac1 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- compatible = "renesas,i2c-r8a779f0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 521>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 521>;
- dmas = <&dmac0 0x97>, <&dmac0 0x96>,
- <&dmac1 0x97>, <&dmac1 0x96>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- compatible = "renesas,i2c-r8a779f0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- dmas = <&dmac0 0x99>, <&dmac0 0x98>,
- <&dmac1 0x99>, <&dmac1 0x98>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c5: i2c@e66e0000 {
- compatible = "renesas,i2c-r8a779f0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe66e0000 0 0x40>;
- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 523>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
- <&dmac1 0x9b>, <&dmac1 0x9a>;
- dma-names = "tx", "rx", "tx", "rx";
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a779f0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 514>,
- <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x31>, <&dmac0 0x30>,
- <&dmac1 0x31>, <&dmac1 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 514>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a779f0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe6550000 0 0x60>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 515>,
- <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x33>, <&dmac0 0x32>,
- <&dmac1 0x33>, <&dmac1 0x32>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 515>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a779f0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe6560000 0 0x60>;
- interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x35>, <&dmac0 0x34>,
- <&dmac1 0x35>, <&dmac1 0x34>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 516>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a779f0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe66a0000 0 0x60>;
- interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x37>, <&dmac0 0x36>,
- <&dmac1 0x37>, <&dmac1 0x36>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- ufs: ufs@e6860000 {
- compatible = "renesas,r8a779f0-ufs";
- reg = <0 0xe6860000 0 0x100>;
- interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
- clock-names = "fck", "ref_clk";
- freq-table-hz = <200000000 200000000>, <38400000 38400000>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 1514>;
- status = "disabled";
- };
-
- rswitch: ethernet@e6880000 {
- compatible = "renesas,r8a779f0-ether-switch";
- reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>;
- reg-names = "base", "secure_base";
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mfwd_error", "race_error",
- "coma_error", "gwca0_error",
- "gwca1_error", "etha0_error",
- "etha1_error", "etha2_error",
- "gptp0_status", "gptp1_status",
- "mfwd_status", "race_status",
- "coma_status", "gwca0_status",
- "gwca1_status", "etha0_status",
- "etha1_status", "etha2_status",
- "rmac0_status", "rmac1_status",
- "rmac2_status",
- "gwca0_rxtx0", "gwca0_rxtx1",
- "gwca0_rxtx2", "gwca0_rxtx3",
- "gwca0_rxtx4", "gwca0_rxtx5",
- "gwca0_rxtx6", "gwca0_rxtx7",
- "gwca1_rxtx0", "gwca1_rxtx1",
- "gwca1_rxtx2", "gwca1_rxtx3",
- "gwca1_rxtx4", "gwca1_rxtx5",
- "gwca1_rxtx6", "gwca1_rxtx7",
- "gwca0_rxts0", "gwca0_rxts1",
- "gwca1_rxts0", "gwca1_rxts1",
- "rmac0_mdio", "rmac1_mdio",
- "rmac2_mdio",
- "rmac0_phy", "rmac1_phy",
- "rmac2_phy";
- clocks = <&cpg CPG_MOD 1505>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 1505>;
- status = "disabled";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- phys = <ð_serdes 0>;
- };
- port@1 {
- reg = <1>;
- phys = <ð_serdes 1>;
- };
- port@2 {
- reg = <2>;
- phys = <ð_serdes 2>;
- };
- };
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a779f0",
- "renesas,rcar-gen4-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>,
- <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x51>, <&dmac0 0x50>,
- <&dmac1 0x51>, <&dmac1 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a779f0",
- "renesas,rcar-gen4-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>,
- <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x53>, <&dmac0 0x52>,
- <&dmac1 0x53>, <&dmac1 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a779f0",
- "renesas,rcar-gen4-scif", "renesas,scif";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>,
- <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x57>, <&dmac0 0x56>,
- <&dmac1 0x57>, <&dmac1 0x56>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a779f0",
- "renesas,rcar-gen4-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 705>,
- <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x59>, <&dmac0 0x58>,
- <&dmac1 0x59>, <&dmac1 0x58>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 705>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a779f0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6e90000 0 0x0064>;
- interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 618>;
- dmas = <&dmac0 0x41>, <&dmac0 0x40>,
- <&dmac1 0x41>, <&dmac1 0x40>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 618>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a779f0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 619>;
- dmas = <&dmac0 0x43>, <&dmac0 0x42>,
- <&dmac1 0x43>, <&dmac1 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 619>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a779f0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 620>;
- dmas = <&dmac0 0x45>, <&dmac0 0x44>,
- <&dmac1 0x45>, <&dmac1 0x44>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 620>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a779f0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 621>;
- dmas = <&dmac0 0x47>, <&dmac0 0x46>,
- <&dmac1 0x47>, <&dmac1 0x46>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 621>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- dmac0: dma-controller@e7350000 {
- compatible = "renesas,dmac-r8a779f0",
- "renesas,rcar-gen4-dmac";
- reg = <0 0xe7350000 0 0x1000>,
- <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3", "ch4",
- "ch5", "ch6", "ch7", "ch8", "ch9",
- "ch10", "ch11", "ch12", "ch13",
- "ch14", "ch15";
- clocks = <&cpg CPG_MOD 709>;
- clock-names = "fck";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 709>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
- };
-
- dmac1: dma-controller@e7351000 {
- compatible = "renesas,dmac-r8a779f0",
- "renesas,rcar-gen4-dmac";
- reg = <0 0xe7351000 0 0x1000>,
- <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3", "ch4",
- "ch5", "ch6", "ch7", "ch8", "ch9",
- "ch10", "ch11", "ch12", "ch13",
- "ch14", "ch15";
- clocks = <&cpg CPG_MOD 710>;
- clock-names = "fck";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 710>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
- <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
- <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
- <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
- <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
- <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
- <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
- <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
- };
-
- mmc0: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a779f0",
- "renesas,rcar-gen4-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
- clock-names = "core", "clkh";
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- resets = <&cpg 706>;
- max-frequency = <200000000>;
- iommus = <&ipmmu_ds0 32>;
- status = "disabled";
- };
-
- ipmmu_rt0: iommu@ee480000 {
- compatible = "renesas,ipmmu-r8a779f0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xee480000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_rt1: iommu@ee4c0000 {
- compatible = "renesas,ipmmu-r8a779f0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xee4c0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds0: iommu@eed00000 {
- compatible = "renesas,ipmmu-r8a779f0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeed00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_hc: iommu@eed40000 {
- compatible = "renesas,ipmmu-r8a779f0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeed40000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@eefc0000 {
- compatible = "renesas,ipmmu-r8a779f0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeefc0000 0 0x20000>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- gic: interrupt-controller@f1000000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1000000 0 0x20000>,
- <0x0 0xf1060000 0 0x110000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- sensor_thermal_rtcore: sensor1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 0>;
-
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor_thermal_apcore0: sensor2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 1>;
-
- trips {
- sensor2_crit: sensor2-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor_thermal_apcore4: sensor3-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 2>;
-
- trips {
- sensor3_crit: sensor3-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- };
-
- ufs30_clk: ufs30-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board
- *
- * Copyright (C) 2022 Glider bv
- */
-
-#include <dt-bindings/media/video-interfaces.h>
-
-&csi40 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- csi40_in: endpoint {
- bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
- clock-lanes = <0>;
- data-lanes = <1 2 3>;
- remote-endpoint = <&max96712_out0>;
- };
- };
- };
-};
-
-&csi41 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- csi41_in: endpoint {
- bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
- clock-lanes = <0>;
- data-lanes = <1 2 3>;
- remote-endpoint = <&max96712_out1>;
- };
- };
- };
-};
-
-&i2c0 {
- pca9654_a: gpio@21 {
- compatible = "onnn,pca9654";
- reg = <0x21>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- pca9654_b: gpio@22 {
- compatible = "onnn,pca9654";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- eeprom@52 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "csi-dsi-sub-board-id";
- reg = <0x52>;
- pagesize = <8>;
- };
-};
-
-&i2c1 {
- gmsl0: gmsl-deserializer@49 {
- compatible = "maxim,max96712";
- reg = <0x49>;
- enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@4 {
- reg = <4>;
- max96712_out0: endpoint {
- bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
- clock-lanes = <0>;
- data-lanes = <1 2 3>;
- remote-endpoint = <&csi40_in>;
- };
- };
- };
- };
-
- gmsl1: gmsl-deserializer@4b {
- compatible = "maxim,max96712";
- reg = <0x4b>;
- enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@4 {
- reg = <4>;
- max96712_out1: endpoint {
- bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
- clock-lanes = <0>;
- data-lanes = <1 2 3>;
- remote-endpoint = <&csi41_in>;
- };
- };
- };
- };
-};
-
-&isp0 {
- status = "okay";
-};
-
-&isp1 {
- status = "okay";
-};
-
-&vin00 {
- status = "okay";
-};
-
-&vin01 {
- status = "okay";
-};
-
-&vin02 {
- status = "okay";
-};
-
-&vin03 {
- status = "okay";
-};
-
-&vin04 {
- status = "okay";
-};
-
-&vin05 {
- status = "okay";
-};
-
-&vin06 {
- status = "okay";
-};
-
-&vin07 {
- status = "okay";
-};
-
-&vin08 {
- status = "okay";
-};
-
-&vin09 {
- status = "okay";
-};
-
-&vin10 {
- status = "okay";
-};
-
-&vin11 {
- status = "okay";
-};
-
-&vin12 {
- status = "okay";
-};
-
-&vin13 {
- status = "okay";
-};
-
-&vin14 {
- status = "okay";
-};
-
-&vin15 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1)
- * sub-board
- *
- * Copyright (C) 2022 Glider bv
- */
-
-&i2c0 {
- eeprom@53 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "ethernet-sub-board-id";
- reg = <0x53>;
- pagesize = <8>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the R-Car V4H (R8A779G0) SoC
- *
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a779g0-sysc.h>
-
-/ {
- compatible = "renesas,r8a779g0";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /* External Audio clock - to be overridden by boards that provide it */
- audio_clkin: audio_clkin {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- cluster0_opp: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <825000>;
- clock-latency-ns = <500000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <825000>;
- clock-latency-ns = <500000>;
- };
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <825000>;
- clock-latency-ns = <500000>;
- };
- opp-1700000000 {
- opp-hz = /bits/ 64 <1700000000>;
- opp-microvolt = <825000>;
- clock-latency-ns = <500000>;
- opp-suspend;
- };
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <880000>;
- clock-latency-ns = <500000>;
- turbo-mode;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&a76_0>;
- };
- core1 {
- cpu = <&a76_1>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&a76_2>;
- };
- core1 {
- cpu = <&a76_3>;
- };
- };
- };
-
- a76_0: cpu@0 {
- compatible = "arm,cortex-a76";
- reg = <0>;
- device_type = "cpu";
- power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
- next-level-cache = <&L3_CA76_0>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- a76_1: cpu@100 {
- compatible = "arm,cortex-a76";
- reg = <0x100>;
- device_type = "cpu";
- power-domains = <&sysc R8A779G0_PD_A1E0D0C1>;
- next-level-cache = <&L3_CA76_0>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- a76_2: cpu@10000 {
- compatible = "arm,cortex-a76";
- reg = <0x10000>;
- device_type = "cpu";
- power-domains = <&sysc R8A779G0_PD_A1E0D1C0>;
- next-level-cache = <&L3_CA76_1>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- a76_3: cpu@10100 {
- compatible = "arm,cortex-a76";
- reg = <0x10100>;
- device_type = "cpu";
- power-domains = <&sysc R8A779G0_PD_A1E0D1C1>;
- next-level-cache = <&L3_CA76_1>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- idle-states {
- entry-method = "psci";
-
- CPU_SLEEP_0: cpu-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- local-timer-stop;
- entry-latency-us = <400>;
- exit-latency-us = <500>;
- min-residency-us = <4000>;
- };
- };
-
- L3_CA76_0: cache-controller-0 {
- compatible = "cache";
- power-domains = <&sysc R8A779G0_PD_A2E0D0>;
- cache-unified;
- cache-level = <3>;
- };
-
- L3_CA76_1: cache-controller-1 {
- compatible = "cache";
- power-domains = <&sysc R8A779G0_PD_A2E0D1>;
- cache-unified;
- cache-level = <3>;
- };
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- extalr_clk: extalr {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- pmu_a76 {
- compatible = "arm,cortex-a76-pmu";
- interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
- };
-
- /* External SCIF clock - to be overridden by boards that provide it */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- soc: soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- rwdt: watchdog@e6020000 {
- compatible = "renesas,r8a779g0-wdt",
- "renesas,rcar-gen4-wdt";
- reg = <0 0xe6020000 0 0x0c>;
- interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 907>;
- status = "disabled";
- };
-
- pfc: pinctrl@e6050000 {
- compatible = "renesas,pfc-r8a779g0";
- reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
- <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
- <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
- <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>,
- <0 0xe6068000 0 0x16c>;
- };
-
- gpio0: gpio@e6050180 {
- compatible = "renesas,gpio-r8a779g0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6050180 0 0x54>;
- interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 0 19>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@e6050980 {
- compatible = "renesas,gpio-r8a779g0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6050980 0 0x54>;
- interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 915>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 32 29>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@e6058180 {
- compatible = "renesas,gpio-r8a779g0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6058180 0 0x54>;
- interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 64 20>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@e6058980 {
- compatible = "renesas,gpio-r8a779g0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6058980 0 0x54>;
- interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 916>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 96 30>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@e6060180 {
- compatible = "renesas,gpio-r8a779g0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6060180 0 0x54>;
- interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 128 25>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio5: gpio@e6060980 {
- compatible = "renesas,gpio-r8a779g0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6060980 0 0x54>;
- interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 160 21>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio6: gpio@e6061180 {
- compatible = "renesas,gpio-r8a779g0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6061180 0 0x54>;
- interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 192 21>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio7: gpio@e6061980 {
- compatible = "renesas,gpio-r8a779g0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6061980 0 0x54>;
- interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 917>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 917>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 224 21>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio8: gpio@e6068180 {
- compatible = "renesas,gpio-r8a779g0",
- "renesas,rcar-gen4-gpio";
- reg = <0 0xe6068180 0 0x54>;
- interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 918>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 918>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pfc 0 256 14>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- cmt0: timer@e60f0000 {
- compatible = "renesas,r8a779g0-cmt0",
- "renesas,rcar-gen4-cmt0";
- reg = <0 0xe60f0000 0 0x1004>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 910>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 910>;
- status = "disabled";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a779g0-cmt1",
- "renesas,rcar-gen4-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 911>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 911>;
- status = "disabled";
- };
-
- cmt2: timer@e6140000 {
- compatible = "renesas,r8a779g0-cmt1",
- "renesas,rcar-gen4-cmt1";
- reg = <0 0xe6140000 0 0x1004>;
- interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 912>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 912>;
- status = "disabled";
- };
-
- cmt3: timer@e6148000 {
- compatible = "renesas,r8a779g0-cmt1",
- "renesas,rcar-gen4-cmt1";
- reg = <0 0xe6148000 0 0x1004>;
- interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 913>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 913>;
- status = "disabled";
- };
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a779g0-cpg-mssr";
- reg = <0 0xe6150000 0 0x4000>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a779g0-rst";
- reg = <0 0xe6160000 0 0x4000>;
- };
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a779g0-sysc";
- reg = <0 0xe6180000 0 0x4000>;
- #power-domain-cells = <1>;
- };
-
- tsc: thermal@e6198000 {
- compatible = "renesas,r8a779g0-thermal";
- reg = <0 0xe6198000 0 0x200>,
- <0 0xe61a0000 0 0x200>,
- <0 0xe61a8000 0 0x200>,
- <0 0xe61b0000 0 0x200>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- #thermal-sensor-cells = <1>;
- };
-
- intc_ex: interrupt-controller@e61c0000 {
- compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc";
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <0 0xe61c0000 0 0x200>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 611>;
- };
-
- tmu0: timer@e61e0000 {
- compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
- reg = <0 0xe61e0000 0 0x30>;
- interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 713>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 713>;
- status = "disabled";
- };
-
- tmu1: timer@e6fc0000 {
- compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
- reg = <0 0xe6fc0000 0 0x30>;
- interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
- status = "disabled";
- };
-
- tmu2: timer@e6fd0000 {
- compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
- reg = <0 0xe6fd0000 0 0x30>;
- interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 715>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 715>;
- status = "disabled";
- };
-
- tmu3: timer@e6fe0000 {
- compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
- reg = <0 0xe6fe0000 0 0x30>;
- interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 716>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 716>;
- status = "disabled";
- };
-
- tmu4: timer@ffc00000 {
- compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
- reg = <0 0xffc00000 0 0x30>;
- interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 717>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 717>;
- status = "disabled";
- };
-
- i2c0: i2c@e6500000 {
- compatible = "renesas,i2c-r8a779g0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe6500000 0 0x40>;
- interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>;
- dmas = <&dmac0 0x91>, <&dmac0 0x90>,
- <&dmac1 0x91>, <&dmac1 0x90>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 518>;
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@e6508000 {
- compatible = "renesas,i2c-r8a779g0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>;
- dmas = <&dmac0 0x93>, <&dmac0 0x92>,
- <&dmac1 0x93>, <&dmac1 0x92>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 519>;
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@e6510000 {
- compatible = "renesas,i2c-r8a779g0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe6510000 0 0x40>;
- interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>;
- dmas = <&dmac0 0x95>, <&dmac0 0x94>,
- <&dmac1 0x95>, <&dmac1 0x94>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 520>;
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@e66d0000 {
- compatible = "renesas,i2c-r8a779g0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe66d0000 0 0x40>;
- interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 521>;
- dmas = <&dmac0 0x97>, <&dmac0 0x96>,
- <&dmac1 0x97>, <&dmac1 0x96>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 521>;
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@e66d8000 {
- compatible = "renesas,i2c-r8a779g0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe66d8000 0 0x40>;
- interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- dma-names = "tx", "rx", "tx", "rx";
- dmas = <&dmac0 0x99>, <&dmac0 0x98>,
- <&dmac1 0x99>, <&dmac1 0x98>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c5: i2c@e66e0000 {
- compatible = "renesas,i2c-r8a779g0",
- "renesas,rcar-gen4-i2c";
- reg = <0 0xe66e0000 0 0x40>;
- interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 523>;
- dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
- <&dmac1 0x9b>, <&dmac1 0x9a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 523>;
- i2c-scl-internal-delay-ns = <110>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- hscif0: serial@e6540000 {
- compatible = "renesas,hscif-r8a779g0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe6540000 0 0x60>;
- interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 514>,
- <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x31>, <&dmac0 0x30>,
- <&dmac1 0x31>, <&dmac1 0x30>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 514>;
- status = "disabled";
- };
-
- hscif1: serial@e6550000 {
- compatible = "renesas,hscif-r8a779g0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe6550000 0 0x60>;
- interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 515>,
- <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x33>, <&dmac0 0x32>,
- <&dmac1 0x33>, <&dmac1 0x32>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 515>;
- status = "disabled";
- };
-
- hscif2: serial@e6560000 {
- compatible = "renesas,hscif-r8a779g0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe6560000 0 0x60>;
- interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x35>, <&dmac0 0x34>,
- <&dmac1 0x35>, <&dmac1 0x34>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 516>;
- status = "disabled";
- };
-
- hscif3: serial@e66a0000 {
- compatible = "renesas,hscif-r8a779g0",
- "renesas,rcar-gen4-hscif", "renesas,hscif";
- reg = <0 0xe66a0000 0 0x60>;
- interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x37>, <&dmac0 0x36>,
- <&dmac1 0x37>, <&dmac1 0x36>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 517>;
- status = "disabled";
- };
-
- canfd: can@e6660000 {
- compatible = "renesas,r8a779g0-canfd",
- "renesas,rcar-gen4-canfd";
- reg = <0 0xe6660000 0 0x8500>;
- interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch_int", "g_int";
- clocks = <&cpg CPG_MOD 328>,
- <&cpg CPG_CORE R8A779G0_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A779G0_CLK_CANFD>;
- assigned-clock-rates = <80000000>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 328>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
-
- channel2 {
- status = "disabled";
- };
-
- channel3 {
- status = "disabled";
- };
-
- channel4 {
- status = "disabled";
- };
-
- channel5 {
- status = "disabled";
- };
-
- channel6 {
- status = "disabled";
- };
-
- channel7 {
- status = "disabled";
- };
- };
-
- avb0: ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a779g0",
- "renesas,etheravb-rcar-gen4";
- reg = <0 0xe6800000 0 0x800>;
- interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
- "ch5", "ch6", "ch7", "ch8", "ch9",
- "ch10", "ch11", "ch12", "ch13",
- "ch14", "ch15", "ch16", "ch17",
- "ch18", "ch19", "ch20", "ch21",
- "ch22", "ch23", "ch24";
- clocks = <&cpg CPG_MOD 211>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 211>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- avb1: ethernet@e6810000 {
- compatible = "renesas,etheravb-r8a779g0",
- "renesas,etheravb-rcar-gen4";
- reg = <0 0xe6810000 0 0x800>;
- interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
- "ch5", "ch6", "ch7", "ch8", "ch9",
- "ch10", "ch11", "ch12", "ch13",
- "ch14", "ch15", "ch16", "ch17",
- "ch18", "ch19", "ch20", "ch21",
- "ch22", "ch23", "ch24";
- clocks = <&cpg CPG_MOD 212>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 212>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- avb2: ethernet@e6820000 {
- compatible = "renesas,etheravb-r8a779g0",
- "renesas,etheravb-rcar-gen4";
- reg = <0 0xe6820000 0 0x1000>;
- interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
- "ch5", "ch6", "ch7", "ch8", "ch9",
- "ch10", "ch11", "ch12", "ch13",
- "ch14", "ch15", "ch16", "ch17",
- "ch18", "ch19", "ch20", "ch21",
- "ch22", "ch23", "ch24";
- clocks = <&cpg CPG_MOD 213>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 213>;
- phy-mode = "rgmii";
- rx-internal-delay-ps = <0>;
- tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pwm0: pwm@e6e30000 {
- compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
- reg = <0 0xe6e30000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm1: pwm@e6e31000 {
- compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
- reg = <0 0xe6e31000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm2: pwm@e6e32000 {
- compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
- reg = <0 0xe6e32000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm3: pwm@e6e33000 {
- compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
- reg = <0 0xe6e33000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm4: pwm@e6e34000 {
- compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
- reg = <0 0xe6e34000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm5: pwm@e6e35000 {
- compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
- reg = <0 0xe6e35000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm6: pwm@e6e36000 {
- compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
- reg = <0 0xe6e36000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm7: pwm@e6e37000 {
- compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
- reg = <0 0xe6e37000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm8: pwm@e6e38000 {
- compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
- reg = <0 0xe6e38000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- pwm9: pwm@e6e39000 {
- compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
- reg = <0 0xe6e39000 0 0x10>;
- #pwm-cells = <2>;
- clocks = <&cpg CPG_MOD 628>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 628>;
- status = "disabled";
- };
-
- scif0: serial@e6e60000 {
- compatible = "renesas,scif-r8a779g0",
- "renesas,rcar-gen4-scif", "renesas,scif";
- reg = <0 0xe6e60000 0 64>;
- interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 702>,
- <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x51>, <&dmac0 0x50>,
- <&dmac1 0x51>, <&dmac1 0x50>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 702>;
- status = "disabled";
- };
-
- scif1: serial@e6e68000 {
- compatible = "renesas,scif-r8a779g0",
- "renesas,rcar-gen4-scif", "renesas,scif";
- reg = <0 0xe6e68000 0 64>;
- interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>,
- <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x53>, <&dmac0 0x52>,
- <&dmac1 0x53>, <&dmac1 0x52>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
- status = "disabled";
- };
-
- scif3: serial@e6c50000 {
- compatible = "renesas,scif-r8a779g0",
- "renesas,rcar-gen4-scif", "renesas,scif";
- reg = <0 0xe6c50000 0 64>;
- interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>,
- <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x57>, <&dmac0 0x56>,
- <&dmac1 0x57>, <&dmac1 0x56>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
- status = "disabled";
- };
-
- scif4: serial@e6c40000 {
- compatible = "renesas,scif-r8a779g0",
- "renesas,rcar-gen4-scif", "renesas,scif";
- reg = <0 0xe6c40000 0 64>;
- interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 705>,
- <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
- <&scif_clk>;
- clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac0 0x59>, <&dmac0 0x58>,
- <&dmac1 0x59>, <&dmac1 0x58>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 705>;
- status = "disabled";
- };
-
- tpu: pwm@e6e80000 {
- compatible = "renesas,tpu-r8a779g0", "renesas,tpu";
- reg = <0 0xe6e80000 0 0x148>;
- interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 718>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 718>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- msiof0: spi@e6e90000 {
- compatible = "renesas,msiof-r8a779g0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6e90000 0 0x0064>;
- interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 618>;
- dmas = <&dmac0 0x41>, <&dmac0 0x40>,
- <&dmac1 0x41>, <&dmac1 0x40>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 618>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof1: spi@e6ea0000 {
- compatible = "renesas,msiof-r8a779g0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6ea0000 0 0x0064>;
- interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 619>;
- dmas = <&dmac0 0x43>, <&dmac0 0x42>,
- <&dmac1 0x43>, <&dmac1 0x42>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 619>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof2: spi@e6c00000 {
- compatible = "renesas,msiof-r8a779g0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6c00000 0 0x0064>;
- interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 620>;
- dmas = <&dmac0 0x45>, <&dmac0 0x44>,
- <&dmac1 0x45>, <&dmac1 0x44>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 620>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof3: spi@e6c10000 {
- compatible = "renesas,msiof-r8a779g0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6c10000 0 0x0064>;
- interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 621>;
- dmas = <&dmac0 0x47>, <&dmac0 0x46>,
- <&dmac1 0x47>, <&dmac1 0x46>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 621>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof4: spi@e6c20000 {
- compatible = "renesas,msiof-r8a779g0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6c20000 0 0x0064>;
- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 622>;
- dmas = <&dmac0 0x49>, <&dmac0 0x48>,
- <&dmac1 0x49>, <&dmac1 0x48>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 622>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- msiof5: spi@e6c28000 {
- compatible = "renesas,msiof-r8a779g0",
- "renesas,rcar-gen4-msiof";
- reg = <0 0xe6c28000 0 0x0064>;
- interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
- dmas = <&dmac0 0x4b>, <&dmac0 0x4a>,
- <&dmac1 0x4b>, <&dmac1 0x4a>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vin00: video@e6ef0000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 730>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 730>;
- renesas,id = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin00isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin00>;
- };
- };
- };
- };
-
- vin01: video@e6ef1000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6ef1000 0 0x1000>;
- interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 731>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 731>;
- renesas,id = <1>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin01isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin01>;
- };
- };
- };
- };
-
- vin02: video@e6ef2000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6ef2000 0 0x1000>;
- interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 800>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 800>;
- renesas,id = <2>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin02isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin02>;
- };
- };
- };
- };
-
- vin03: video@e6ef3000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6ef3000 0 0x1000>;
- interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 801>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 801>;
- renesas,id = <3>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin03isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin03>;
- };
- };
- };
- };
-
- vin04: video@e6ef4000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6ef4000 0 0x1000>;
- interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 802>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 802>;
- renesas,id = <4>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin04isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin04>;
- };
- };
- };
- };
-
- vin05: video@e6ef5000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6ef5000 0 0x1000>;
- interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 803>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 803>;
- renesas,id = <5>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin05isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin05>;
- };
- };
- };
- };
-
- vin06: video@e6ef6000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6ef6000 0 0x1000>;
- interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 804>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 804>;
- renesas,id = <6>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin06isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin06>;
- };
- };
- };
- };
-
- vin07: video@e6ef7000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6ef7000 0 0x1000>;
- interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 805>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 805>;
- renesas,id = <7>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin07isp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&isp0vin07>;
- };
- };
- };
- };
-
- vin08: video@e6ef8000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6ef8000 0 0x1000>;
- interrupts = <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 806>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 806>;
- renesas,id = <8>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin08isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin08>;
- };
- };
- };
- };
-
- vin09: video@e6ef9000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6ef9000 0 0x1000>;
- interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 807>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 807>;
- renesas,id = <9>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin09isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin09>;
- };
- };
- };
- };
-
- vin10: video@e6efa000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6efa000 0 0x1000>;
- interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 808>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 808>;
- renesas,id = <10>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin10isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin10>;
- };
- };
- };
- };
-
- vin11: video@e6efb000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6efb000 0 0x1000>;
- interrupts = <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 809>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 809>;
- renesas,id = <11>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin11isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin11>;
- };
- };
- };
- };
-
- vin12: video@e6efc000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6efc000 0 0x1000>;
- interrupts = <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 810>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 810>;
- renesas,id = <12>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin12isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin12>;
- };
- };
- };
- };
-
- vin13: video@e6efd000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6efd000 0 0x1000>;
- interrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- renesas,id = <13>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin13isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin13>;
- };
- };
- };
- };
-
- vin14: video@e6efe000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6efe000 0 0x1000>;
- interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 812>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 812>;
- renesas,id = <14>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin14isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin14>;
- };
- };
- };
- };
-
- vin15: video@e6eff000 {
- compatible = "renesas,vin-r8a779g0";
- reg = <0 0xe6eff000 0 0x1000>;
- interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 813>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 813>;
- renesas,id = <15>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <2>;
-
- vin15isp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&isp1vin15>;
- };
- };
- };
- };
-
- dmac0: dma-controller@e7350000 {
- compatible = "renesas,dmac-r8a779g0",
- "renesas,rcar-gen4-dmac";
- reg = <0 0xe7350000 0 0x1000>,
- <0 0xe7300000 0 0x10000>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3", "ch4",
- "ch5", "ch6", "ch7", "ch8", "ch9",
- "ch10", "ch11", "ch12", "ch13",
- "ch14", "ch15";
- clocks = <&cpg CPG_MOD 709>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 709>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
- <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
- <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
- <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
- <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
- <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
- <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
- <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
- };
-
- dmac1: dma-controller@e7351000 {
- compatible = "renesas,dmac-r8a779g0",
- "renesas,rcar-gen4-dmac";
- reg = <0 0xe7351000 0 0x1000>,
- <0 0xe7310000 0 0x10000>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3", "ch4",
- "ch5", "ch6", "ch7", "ch8", "ch9",
- "ch10", "ch11", "ch12", "ch13",
- "ch14", "ch15";
- clocks = <&cpg CPG_MOD 710>;
- clock-names = "fck";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 710>;
- #dma-cells = <1>;
- dma-channels = <16>;
- iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
- <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
- <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
- <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
- <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
- <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
- <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
- <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
- };
-
- rcar_sound: sound@ec5a0000 {
- /*
- * #sound-dai-cells is required
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- /*
- * #clock-cells is required
- *
- * clkout : #clock-cells = <0>; <&rcar_sound>;
- * audio_clkout0/1/2/3 : #clock-cells = <1>; <&rcar_sound N>;
- */
- compatible = "renesas,rcar_sound-r8a779g0", "renesas,rcar_sound-gen4";
- reg = <0 0xec5a0000 0 0x020>,
- <0 0xec540000 0 0x1000>,
- <0 0xec541000 0 0x050>,
- <0 0xec400000 0 0x40000>;
- reg-names = "adg", "ssiu", "ssi", "sdmc";
-
- clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>;
- clock-names = "ssiu.0", "ssi.0", "clkin";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 2926>, <&cpg 2927>;
- reset-names = "ssiu.0", "ssi.0";
- status = "disabled";
-
- rcar_sound,ssiu {
- ssiu00: ssiu-0 {
- dmas = <&dmac0 0x6e>, <&dmac0 0x6f>;
- dma-names = "tx", "rx";
- };
- ssiu01: ssiu-1 {
- dmas = <&dmac0 0x6c>, <&dmac0 0x6d>;
- dma-names = "tx", "rx";
- };
- ssiu02: ssiu-2 {
- dmas = <&dmac0 0x6a>, <&dmac0 0x6b>;
- dma-names = "tx", "rx";
- };
- ssiu03: ssiu-3 {
- dmas = <&dmac0 0x68>, <&dmac0 0x69>;
- dma-names = "tx", "rx";
- };
- ssiu04: ssiu-4 {
- dmas = <&dmac0 0x66>, <&dmac0 0x67>;
- dma-names = "tx", "rx";
- };
- ssiu05: ssiu-5 {
- dmas = <&dmac0 0x64>, <&dmac0 0x65>;
- dma-names = "tx", "rx";
- };
- ssiu06: ssiu-6 {
- dmas = <&dmac0 0x62>, <&dmac0 0x63>;
- dma-names = "tx", "rx";
- };
- ssiu07: ssiu-7 {
- dmas = <&dmac0 0x60>, <&dmac0 0x61>;
- dma-names = "tx", "rx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
- };
-
- ipmmu_rt0: iommu@ee480000 {
- compatible = "renesas,ipmmu-r8a779g0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xee480000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_rt1: iommu@ee4c0000 {
- compatible = "renesas,ipmmu-r8a779g0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xee4c0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ds0: iommu@eed00000 {
- compatible = "renesas,ipmmu-r8a779g0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeed00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_hc: iommu@eed40000 {
- compatible = "renesas,ipmmu-r8a779g0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeed40000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ir: iommu@eed80000 {
- compatible = "renesas,ipmmu-r8a779g0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeed80000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779G0_PD_A3IR>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc: iommu@eedc0000 {
- compatible = "renesas,ipmmu-r8a779g0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeedc0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_3dg: iommu@eee00000 {
- compatible = "renesas,ipmmu-r8a779g0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeee00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: iommu@eee80000 {
- compatible = "renesas,ipmmu-r8a779g0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeee80000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi1: iommu@eeec0000 {
- compatible = "renesas,ipmmu-r8a779g0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeeec0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vip0: iommu@eef00000 {
- compatible = "renesas,ipmmu-r8a779g0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeef00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vip1: iommu@eef40000 {
- compatible = "renesas,ipmmu-r8a779g0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeef40000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: iommu@eefc0000 {
- compatible = "renesas,ipmmu-r8a779g0",
- "renesas,rcar-gen4-ipmmu-vmsa";
- reg = <0 0xeefc0000 0 0x20000>;
- interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- mmc0: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a779g0",
- "renesas,rcar-gen4-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 706>,
- <&cpg CPG_CORE R8A779G0_CLK_SD0H>;
- clock-names = "core", "clkh";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 706>;
- max-frequency = <200000000>;
- iommus = <&ipmmu_ds0 32>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a779g0-rpc-if",
- "renesas,rcar-gen4-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x04000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 629>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 629>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@f1000000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xf1000000 0 0x20000>,
- <0x0 0xf1060000 0 0x110000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- csi40: csi2@fe500000 {
- compatible = "renesas,r8a779g0-csi2";
- reg = <0 0xfe500000 0 0x40000>;
- interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 331>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 331>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
- csi40isp0: endpoint {
- remote-endpoint = <&isp0csi40>;
- };
- };
- };
- };
-
- csi41: csi2@fe540000 {
- compatible = "renesas,r8a779g0-csi2";
- reg = <0 0xfe540000 0 0x40000>;
- interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 400>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 400>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- reg = <1>;
- csi41isp1: endpoint {
- remote-endpoint = <&isp1csi41>;
- };
- };
- };
- };
-
- fcpvd0: fcp@fea10000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea10000 0 0x200>;
- clocks = <&cpg CPG_MOD 508>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 508>;
- };
-
- fcpvd1: fcp@fea11000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea11000 0 0x200>;
- clocks = <&cpg CPG_MOD 509>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 509>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x7000>;
- interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 830>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 830>;
-
- renesas,fcp = <&fcpvd0>;
- };
-
- vspd1: vsp@fea28000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x7000>;
- interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 831>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 831>;
-
- renesas,fcp = <&fcpvd1>;
- };
-
- du: display@feb00000 {
- compatible = "renesas,du-r8a779g0";
- reg = <0 0xfeb00000 0 0x40000>;
- interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 411>;
- clock-names = "du.0";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 411>;
- reset-names = "du.0";
- renesas,vsps = <&vspd0 0>, <&vspd1 0>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- du_out_dsi0: endpoint {
- remote-endpoint = <&dsi0_in>;
- };
- };
-
- port@1 {
- reg = <1>;
- du_out_dsi1: endpoint {
- remote-endpoint = <&dsi1_in>;
- };
- };
- };
- };
-
- isp0: isp@fed00000 {
- compatible = "renesas,r8a779g0-isp";
- reg = <0 0xfed00000 0 0x10000>;
- interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&cpg CPG_MOD 612>;
- power-domains = <&sysc R8A779G0_PD_A3ISP0>;
- resets = <&cpg 612>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <0>;
-
- isp0csi40: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi40isp0>;
- };
- };
-
- port@1 {
- reg = <1>;
- isp0vin00: endpoint {
- remote-endpoint = <&vin00isp0>;
- };
- };
-
- port@2 {
- reg = <2>;
- isp0vin01: endpoint {
- remote-endpoint = <&vin01isp0>;
- };
- };
-
- port@3 {
- reg = <3>;
- isp0vin02: endpoint {
- remote-endpoint = <&vin02isp0>;
- };
- };
-
- port@4 {
- reg = <4>;
- isp0vin03: endpoint {
- remote-endpoint = <&vin03isp0>;
- };
- };
-
- port@5 {
- reg = <5>;
- isp0vin04: endpoint {
- remote-endpoint = <&vin04isp0>;
- };
- };
-
- port@6 {
- reg = <6>;
- isp0vin05: endpoint {
- remote-endpoint = <&vin05isp0>;
- };
- };
-
- port@7 {
- reg = <7>;
- isp0vin06: endpoint {
- remote-endpoint = <&vin06isp0>;
- };
- };
-
- port@8 {
- reg = <8>;
- isp0vin07: endpoint {
- remote-endpoint = <&vin07isp0>;
- };
- };
- };
- };
-
- isp1: isp@fed20000 {
- compatible = "renesas,r8a779g0-isp";
- reg = <0 0xfed20000 0 0x10000>;
- interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&cpg CPG_MOD 613>;
- power-domains = <&sysc R8A779G0_PD_A3ISP1>;
- resets = <&cpg 613>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <0>;
-
- isp1csi41: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csi41isp1>;
- };
- };
-
- port@1 {
- reg = <1>;
- isp1vin08: endpoint {
- remote-endpoint = <&vin08isp1>;
- };
- };
-
- port@2 {
- reg = <2>;
- isp1vin09: endpoint {
- remote-endpoint = <&vin09isp1>;
- };
- };
-
- port@3 {
- reg = <3>;
- isp1vin10: endpoint {
- remote-endpoint = <&vin10isp1>;
- };
- };
-
- port@4 {
- reg = <4>;
- isp1vin11: endpoint {
- remote-endpoint = <&vin11isp1>;
- };
- };
-
- port@5 {
- reg = <5>;
- isp1vin12: endpoint {
- remote-endpoint = <&vin12isp1>;
- };
- };
-
- port@6 {
- reg = <6>;
- isp1vin13: endpoint {
- remote-endpoint = <&vin13isp1>;
- };
- };
-
- port@7 {
- reg = <7>;
- isp1vin14: endpoint {
- remote-endpoint = <&vin14isp1>;
- };
- };
-
- port@8 {
- reg = <8>;
- isp1vin15: endpoint {
- remote-endpoint = <&vin15isp1>;
- };
- };
- };
- };
-
- dsi0: dsi-encoder@fed80000 {
- compatible = "renesas,r8a779g0-dsi-csi2-tx";
- reg = <0 0xfed80000 0 0x10000>;
- clocks = <&cpg CPG_MOD 415>,
- <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
- <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
- clock-names = "fck", "dsi", "pll";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 415>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi0_in: endpoint {
- remote-endpoint = <&du_out_dsi0>;
- };
- };
-
- port@1 {
- reg = <1>;
- };
- };
- };
-
- dsi1: dsi-encoder@fed90000 {
- compatible = "renesas,r8a779g0-dsi-csi2-tx";
- reg = <0 0xfed90000 0 0x10000>;
- clocks = <&cpg CPG_MOD 416>,
- <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
- <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
- clock-names = "fck", "dsi", "pll";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 416>;
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi1_in: endpoint {
- remote-endpoint = <&du_out_dsi1>;
- };
- };
-
- port@1 {
- reg = <1>;
- };
- };
- };
-
- prr: chipid@fff00044 {
- compatible = "renesas,prr";
- reg = <0 0xfff00044 0 4>;
- };
- };
-
- thermal-zones {
- sensor_thermal_cr52: sensor1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 0>;
-
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor_thermal_cnn: sensor2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 1>;
-
- trips {
- sensor2_crit: sensor2-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor_thermal_ca76: sensor3-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 2>;
-
- trips {
- sensor3_crit: sensor3-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
-
- sensor_thermal_ddr1: sensor4-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 3>;
-
- trips {
- sensor4_crit: sensor4-crit {
- temperature = <120000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the R-Car V4M Gray Hawk CSI/DSI sub-board
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-&i2c0 {
- eeprom@52 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "csi-dsi-sub-board-id";
- reg = <0x52>;
- pagesize = <8>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the R-Car V4M Gray Hawk Ethernet sub-board
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-&i2c0 {
- eeprom@53 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "ethernet-sub-board-id";
- reg = <0x53>;
- pagesize = <8>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source extras for U-Boot for the Gray Hawk board
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-#include "r8a779h0-u-boot.dtsi"
-
-/ {
- aliases {
- spi0 = &rpc;
- };
-};
-
-&pfc {
- qspi0_pins: qspi0 {
- groups = "qspi0_ctrl", "qspi0_data4";
- function = "qspi0";
- };
-};
-
-&rpc {
- pinctrl-0 = <&qspi0_pins>;
- pinctrl-names = "default";
-
- #address-cells = <1>;
- #size-cells = <0>;
- spi-max-frequency = <40000000>;
- status = "okay";
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "s25fs512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the Gray Hawk CPU and BreakOut boards
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r8a779h0-gray-hawk-cpu.dtsi"
-#include "r8a779h0-gray-hawk-csi-dsi.dtsi"
-#include "r8a779h0-gray-hawk-ethernet.dtsi"
-
-/ {
- model = "Renesas Gray Hawk CPU and Breakout boards based on r8a779h0";
- compatible = "renesas,gray-hawk-breakout", "renesas,gray-hawk-cpu", "renesas,r8a779h0";
-};
-
-&i2c0 {
- eeprom@51 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "breakout-board";
- reg = <0x51>;
- pagesize = <8>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC
- *
- * Copyright (C) 2023 Renesas Electronics Corp.
- */
-
-#include "r8a779x-u-boot.dtsi"
-/ {
- soc {
- rpc: spi@ee200000 {
- compatible = "renesas,r8a779h0-rpc-if", "renesas,rcar-gen4-rpc-if";
- reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 629>;
- power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
- resets = <&cpg 629>;
- bank-width = <2>;
- num-cs = <1>;
- status = "disabled";
- };
- };
-};
-
-&extalr_clk {
- bootph-all;
-};
};
};
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ };
+};
+
&i2c5 {
status = "okay";
};
+&io_domains {
+ bb-supply = <&vcc_io>;
+ flash0-supply = <&vccio_flash>;
+ gpio1830-supply = <&vcc_18>;
+ gpio30-supply = <&vcc_io>;
+ sdcard-supply = <&vccio_sd>;
+ wifi-supply = <&vcc_wl>;
+ status = "okay";
+};
+
&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
drive-strength = <8>;
};
};
};
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
sdmmc {
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
};
};
+&sdio_pwrseq {
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */
+};
+
&usbphy {
status = "okay";
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
- *
- */
-
-/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include "rk3308.dtsi"
-
-/ {
- model = "Rockchip RK3308 EVB";
- compatible = "rockchip,rk3308-evb", "rockchip,rk3308";
-
- chosen {
- stdout-path = "serial4:1500000n8";
- };
-
- adc-keys0 {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- poll-interval = <100>;
- keyup-threshold-microvolt = <1800000>;
-
- button-func {
- linux,code = <KEY_FN>;
- label = "function";
- press-threshold-microvolt = <18000>;
- };
- };
-
- adc-keys1 {
- compatible = "adc-keys";
- io-channels = <&saradc 1>;
- io-channel-names = "buttons";
- poll-interval = <100>;
- keyup-threshold-microvolt = <1800000>;
-
- button-esc {
- linux,code = <KEY_MICMUTE>;
- label = "micmute";
- press-threshold-microvolt = <1130000>;
- };
-
- button-home {
- linux,code = <KEY_MODE>;
- label = "mode";
- press-threshold-microvolt = <901000>;
- };
-
- button-menu {
- linux,code = <KEY_PLAY>;
- label = "play";
- press-threshold-microvolt = <624000>;
- };
-
- button-down {
- linux,code = <KEY_VOLUMEDOWN>;
- label = "volume down";
- press-threshold-microvolt = <300000>;
- };
-
- button-up {
- linux,code = <KEY_VOLUMEUP>;
- label = "volume up";
- press-threshold-microvolt = <18000>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pwr_key>;
-
- key-power {
- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- label = "GPIO Key Power";
- debounce-interval = <100>;
- wakeup-source;
- };
- };
-
- vcc12v_dcin: vcc12v-dcin {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vccio_sdio: vcc_1v8: vcc-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_io>;
- };
-
- vcc_ddr: vcc-ddr {
- compatible = "regulator-fixed";
- regulator-name = "vcc_ddr";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc_io: vcc-io {
- compatible = "regulator-fixed";
- regulator-name = "vcc_io";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vccio_flash: vccio-flash {
- compatible = "regulator-fixed";
- regulator-name = "vccio_flash";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_io>;
- };
-
- vcc5v0_host: vcc5v0-host {
- compatible = "regulator-fixed";
- gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&usb_drv>;
- regulator-name = "vbus_host";
- vin-supply = <&vcc5v0_sys>;
- };
-
- vdd_core: vdd-core {
- compatible = "pwm-regulator";
- pwms = <&pwm0 0 5000 1>;
- regulator-name = "vdd_core";
- regulator-min-microvolt = <827000>;
- regulator-max-microvolt = <1340000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-settling-time-up-us = <250>;
- pwm-supply = <&vcc5v0_sys>;
- };
-
- vdd_log: vdd-log {
- compatible = "regulator-fixed";
- regulator-name = "vdd_log";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vdd_1v0: vdd-1v0 {
- compatible = "regulator-fixed";
- regulator-name = "vdd_1v0";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_core>;
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vcc_1v8>;
-};
-
-&pinctrl {
- pinctrl-names = "default";
- pinctrl-0 = <&rtc_32k>;
-
- buttons {
- pwr_key: pwr-key {
- rockchip,pins = <0 RK_PA6 0 &pcfg_pull_up>;
- };
- };
-
- usb {
- usb_drv: usb-drv {
- rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PA2 0 &pcfg_pull_none>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
- pinctrl-0 = <&pwm0_pin_pull_down>;
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_xfer>;
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-#include "rk3308.dtsi"
-
-/ {
- model = "Firefly ROC-RK3308-CC board";
- compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308";
-
- aliases {
- mmc0 = &sdmmc;
- mmc1 = &emmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&ir_recv_pin>;
- };
-
- ir_tx {
- compatible = "pwm-ir-tx";
- pwms = <&pwm5 0 25000 0>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- power_led: led-0 {
- label = "firefly:red:power";
- linux,default-trigger = "ir-power-click";
- default-state = "on";
- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- };
-
- user_led: led-1 {
- label = "firefly:blue:user";
- linux,default-trigger = "ir-user-click";
- default-state = "off";
- gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
- };
- };
-
- typec_vcc5v: typec-vcc5v {
- compatible = "regulator-fixed";
- regulator-name = "typec_vcc5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&typec_vcc5v>;
- };
-
- vcc_io: vcc-io {
- compatible = "regulator-fixed";
- regulator-name = "vcc_io";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc_sdmmc: vcc-sdmmc {
- compatible = "regulator-gpio";
- regulator-name = "vcc_sdmmc";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0>,
- <3300000 0x1>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc_sd: vcc-sd {
- compatible = "regulator-fixed";
- gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>;
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_io>;
- };
-
- vdd_core: vdd-core {
- compatible = "pwm-regulator";
- pwms = <&pwm0 0 5000 1>;
- regulator-name = "vdd_core";
- regulator-min-microvolt = <827000>;
- regulator-max-microvolt = <1340000>;
- regulator-settling-time-up-us = <250>;
- regulator-always-on;
- regulator-boot-on;
- pwm-supply = <&vcc5v0_sys>;
- };
-
- vdd_log: vdd-log {
- compatible = "regulator-fixed";
- regulator-name = "vdd_log";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_core>;
-};
-
-&emmc {
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- non-removable;
- status = "okay";
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- status = "okay";
-
- rtc: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- #clock-cells = <0>;
- };
-};
-
-&pwm5 {
- status = "okay";
- pinctrl-names = "active";
- pinctrl-0 = <&pwm5_pin_pull_down>;
-};
-
-&pinctrl {
- pinctrl-names = "default";
- pinctrl-0 = <&rtc_32k>;
-
- ir-receiver {
- ir_recv_pin: ir-recv-pin {
- rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- buttons {
- pwr_key: pwr-key {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
- pinctrl-0 = <&pwm0_pin_pull_down>;
-};
-
-&sdmmc {
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <300>;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vcc_sdmmc>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
- * Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
- */
-
-/dts-v1/;
-#include "rk3308.dtsi"
-
-/ {
- model = "Radxa ROCK Pi S";
- compatible = "radxa,rockpis", "rockchip,rk3308";
-
- aliases {
- ethernet0 = &gmac;
- mmc0 = &emmc;
- mmc1 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial0:1500000n8";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>;
-
- green-led {
- default-state = "on";
- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- label = "rockpis:green:power";
- linux,default-trigger = "default-on";
- };
-
- blue-led {
- default-state = "on";
- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
- label = "rockpis:blue:user";
- linux,default-trigger = "heartbeat";
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- pinctrl-0 = <&wifi_enable_h>;
- pinctrl-names = "default";
- reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
- };
-
- vcc_1v8: vcc-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_io>;
- };
-
- vcc_io: vcc-io {
- compatible = "regulator-fixed";
- regulator-name = "vcc_io";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc_ddr: vcc-ddr {
- compatible = "regulator-fixed";
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_otg: vcc5v0-otg {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&otg_vbus_drv>;
- regulator-name = "vcc5v0_otg";
- regulator-always-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vdd_core: vdd-core {
- compatible = "pwm-regulator";
- pwms = <&pwm0 0 5000 1>;
- pwm-supply = <&vcc5v0_sys>;
- regulator-name = "vdd_core";
- regulator-min-microvolt = <827000>;
- regulator-max-microvolt = <1340000>;
- regulator-settling-time-up-us = <250>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_log: vdd-log {
- compatible = "regulator-fixed";
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_core>;
-};
-
-&emmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- non-removable;
- vmmc-supply = <&vcc_io>;
- status = "okay";
-};
-
-&gmac {
- clock_in_out = "output";
- phy-supply = <&vcc_io>;
- snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 50000 50000>;
- status = "okay";
-};
-
-&gpio0 {
- gpio-line-names =
- /* GPIO0_A0 - A7 */
- "", "", "", "", "", "", "", "",
- /* GPIO0_B0 - B7 */
- "", "", "", "header1-pin3 [GPIO0_B3]",
- "header1-pin5 [GPIO0_B4]", "", "",
- "header1-pin11 [GPIO0_B7]",
- /* GPIO0_C0 - C7 */
- "header1-pin13 [GPIO0_C0]",
- "header1-pin15 [GPIO0_C1]", "", "", "",
- "", "", "",
- /* GPIO0_D0 - D7 */
- "", "", "", "", "", "", "", "";
-};
-
-&gpio1 {
- gpio-line-names =
- /* GPIO1_A0 - A7 */
- "", "", "", "", "", "", "", "",
- /* GPIO1_B0 - B7 */
- "", "", "", "", "", "", "", "",
- /* GPIO1_C0 - C7 */
- "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]",
- "header1-pin19 [GPIO1_C7]",
- /* GPIO1_D0 - D7 */
- "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]",
- "", "", "", "", "", "";
-};
-
-&gpio2 {
- gpio-line-names =
- /* GPIO2_A0 - A7 */
- "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]",
- "", "",
- "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]",
- "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]",
- /* GPIO2_B0 - B7 */
- "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]",
- "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]",
- "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]",
- "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]",
- /* GPIO2_C0 - C7 */
- "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "",
- /* GPIO2_D0 - D7 */
- "", "", "", "", "", "", "", "";
-};
-
-&gpio3 {
- gpio-line-names =
- /* GPIO3_A0 - A7 */
- "", "", "", "", "", "", "", "",
- /* GPIO3_B0 - B7 */
- "", "", "header2-pin42 [GPIO3_B2]",
- "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]",
- "header2-pin39 [GPIO3_B5]", "", "",
- /* GPIO3_C0 - C7 */
- "", "", "", "", "", "", "", "",
- /* GPIO3_D0 - D7 */
- "", "", "", "", "", "", "", "";
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&pinctrl {
- pinctrl-names = "default";
- pinctrl-0 = <&rtc_32k>;
-
- leds {
- green_led_gio: green-led-gpio {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- heartbeat_led_gpio: heartbeat-led-gpio {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- otg_vbus_drv: otg-vbus-drv {
- rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wifi_host_wake: wifi-host-wake {
- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
- pinctrl-0 = <&pwm0_pin_pull_down>;
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdio {
- #address-cells = <1>;
- #size-cells = <0>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- max-frequency = <1000000>;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdmmc {
- cap-sd-highspeed;
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-
- u2phy_host: host-port {
- phy-supply = <&vcc5v0_otg>;
- status = "okay";
- };
-
- u2phy_otg: otg-port {
- phy-supply = <&vcc5v0_otg>;
- status = "okay";
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&uart4 {
- status = "okay";
-
- bluetooth {
- compatible = "realtek,rtl8723bs-bt";
- device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
- host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&usb_host_ehci {
- status = "okay";
-};
-
-&usb_host_ohci {
- status = "okay";
-};
-
-&usb20_otg {
- dr_mode = "peripheral";
- status = "okay";
-};
-
-&wdt {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
- *
- */
-
-#include <dt-bindings/clock/rk3308-cru.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,boot-mode.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- compatible = "rockchip,rk3308";
-
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
- gpio3 = &gpio3;
- gpio4 = &gpio4;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- serial4 = &uart4;
- spi0 = &spi0;
- spi1 = &spi1;
- spi2 = &spi2;
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0x0 0x0>;
- enable-method = "psci";
- clocks = <&cru ARMCLK>;
- #cooling-cells = <2>;
- dynamic-power-coefficient = <90>;
- operating-points-v2 = <&cpu0_opp_table>;
- cpu-idle-states = <&CPU_SLEEP>;
- next-level-cache = <&l2>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0x0 0x1>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
- cpu-idle-states = <&CPU_SLEEP>;
- next-level-cache = <&l2>;
- };
-
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0x0 0x2>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
- cpu-idle-states = <&CPU_SLEEP>;
- next-level-cache = <&l2>;
- };
-
- cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0x0 0x3>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
- cpu-idle-states = <&CPU_SLEEP>;
- next-level-cache = <&l2>;
- };
-
- idle-states {
- entry-method = "psci";
-
- CPU_SLEEP: cpu-sleep {
- compatible = "arm,idle-state";
- local-timer-stop;
- arm,psci-suspend-param = <0x0010000>;
- entry-latency-us = <120>;
- exit-latency-us = <250>;
- min-residency-us = <900>;
- };
- };
-
- l2: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
- };
- };
-
- cpu0_opp_table: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-408000000 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <950000 950000 1340000>;
- clock-latency-ns = <40000>;
- opp-suspend;
- };
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <950000 950000 1340000>;
- clock-latency-ns = <40000>;
- };
- opp-816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1025000 1025000 1340000>;
- clock-latency-ns = <40000>;
- };
- opp-1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1125000 1125000 1340000>;
- clock-latency-ns = <40000>;
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a35-pmu";
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- mac_clkin: external-mac-clock {
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- clock-output-names = "mac_clkin";
- #clock-cells = <0>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- xin24m: xin24m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- };
-
- grf: grf@ff000000 {
- compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
- reg = <0x0 0xff000000 0x0 0x08000>;
-
- reboot-mode {
- compatible = "syscon-reboot-mode";
- offset = <0x500>;
- mode-bootloader = <BOOT_BL_DOWNLOAD>;
- mode-loader = <BOOT_BL_DOWNLOAD>;
- mode-normal = <BOOT_NORMAL>;
- mode-recovery = <BOOT_RECOVERY>;
- mode-fastboot = <BOOT_FASTBOOT>;
- };
- };
-
- usb2phy_grf: syscon@ff008000 {
- compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
- reg = <0x0 0xff008000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy: usb2phy@100 {
- compatible = "rockchip,rk3308-usb2phy";
- reg = <0x100 0x10>;
- assigned-clocks = <&cru USB480M>;
- assigned-clock-parents = <&u2phy>;
- clocks = <&cru SCLK_USBPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy";
- #clock-cells = <0>;
- status = "disabled";
-
- u2phy_otg: otg-port {
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- #phy-cells = <0>;
- status = "disabled";
- };
-
- u2phy_host: host-port {
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "linestate";
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
- detect_grf: syscon@ff00b000 {
- compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
- reg = <0x0 0xff00b000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- core_grf: syscon@ff00c000 {
- compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
- reg = <0x0 0xff00c000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- i2c0: i2c@ff040000 {
- compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xff040000 0x0 0x1000>;
- clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@ff050000 {
- compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xff050000 0x0 0x1000>;
- clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@ff060000 {
- compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xff060000 0x0 0x1000>;
- clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@ff070000 {
- compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xff070000 0x0 0x1000>;
- clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3m0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- wdt: watchdog@ff080000 {
- compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
- reg = <0x0 0xff080000 0x0 0x100>;
- clocks = <&cru PCLK_WDT>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- uart0: serial@ff0a0000 {
- compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff0a0000 0x0 0x100>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- status = "disabled";
- };
-
- uart1: serial@ff0b0000 {
- compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff0b0000 0x0 0x100>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
- status = "disabled";
- };
-
- uart2: serial@ff0c0000 {
- compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff0c0000 0x0 0x100>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart2m0_xfer>;
- status = "disabled";
- };
-
- uart3: serial@ff0d0000 {
- compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff0d0000 0x0 0x100>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_xfer>;
- status = "disabled";
- };
-
- uart4: serial@ff0e0000 {
- compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff0e0000 0x0 0x100>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
- status = "disabled";
- };
-
- spi0: spi@ff120000 {
- compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff120000 0x0 0x1000>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac0 0>, <&dmac0 1>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
- status = "disabled";
- };
-
- spi1: spi@ff130000 {
- compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff130000 0x0 0x1000>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac0 2>, <&dmac0 3>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
- status = "disabled";
- };
-
- spi2: spi@ff140000 {
- compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff140000 0x0 0x1000>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac1 16>, <&dmac1 17>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
- status = "disabled";
- };
-
- pwm8: pwm@ff160000 {
- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xff160000 0x0 0x10>;
- clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm8_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm9: pwm@ff160010 {
- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xff160010 0x0 0x10>;
- clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm9_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm10: pwm@ff160020 {
- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xff160020 0x0 0x10>;
- clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm10_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm11: pwm@ff160030 {
- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xff160030 0x0 0x10>;
- clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm11_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm4: pwm@ff170000 {
- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xff170000 0x0 0x10>;
- clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm4_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm5: pwm@ff170010 {
- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xff170010 0x0 0x10>;
- clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm5_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm6: pwm@ff170020 {
- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xff170020 0x0 0x10>;
- clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm6_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm7: pwm@ff170030 {
- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xff170030 0x0 0x10>;
- clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm7_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm0: pwm@ff180000 {
- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xff180000 0x0 0x10>;
- clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm1: pwm@ff180010 {
- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xff180010 0x0 0x10>;
- clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm1_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm2: pwm@ff180020 {
- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xff180020 0x0 0x10>;
- clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm2_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm3: pwm@ff180030 {
- compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xff180030 0x0 0x10>;
- clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- rktimer: rktimer@ff1a0000 {
- compatible = "rockchip,rk3288-timer";
- reg = <0x0 0xff1a0000 0x0 0x20>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
- clock-names = "pclk", "timer";
- };
-
- saradc: saradc@ff1e0000 {
- compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
- reg = <0x0 0xff1e0000 0x0 0x100>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
- clock-names = "saradc", "apb_pclk";
- #io-channel-cells = <1>;
- resets = <&cru SRST_SARADC_P>;
- reset-names = "saradc-apb";
- status = "disabled";
- };
-
- dmac0: dma-controller@ff2c0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff2c0000 0x0 0x4000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_DMAC0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
-
- dmac1: dma-controller@ff2d0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff2d0000 0x0 0x4000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_DMAC1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
-
- i2s_2ch_0: i2s@ff350000 {
- compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xff350000 0x0 0x1000>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
- clock-names = "i2s_clk", "i2s_hclk";
- dmas = <&dmac1 8>, <&dmac1 9>;
- dma-names = "tx", "rx";
- resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
- reset-names = "reset-m", "reset-h";
- pinctrl-names = "default";
- pinctrl-0 = <&i2s_2ch_0_sclk
- &i2s_2ch_0_lrck
- &i2s_2ch_0_sdi
- &i2s_2ch_0_sdo>;
- status = "disabled";
- };
-
- i2s_2ch_1: i2s@ff360000 {
- compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xff360000 0x0 0x1000>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
- clock-names = "i2s_clk", "i2s_hclk";
- dmas = <&dmac1 11>;
- dma-names = "rx";
- resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
- reset-names = "reset-m", "reset-h";
- status = "disabled";
- };
-
- spdif_tx: spdif-tx@ff3a0000 {
- compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
- reg = <0x0 0xff3a0000 0x0 0x1000>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
- clock-names = "mclk", "hclk";
- dmas = <&dmac1 13>;
- dma-names = "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spdif_out>;
- status = "disabled";
- };
-
- usb20_otg: usb@ff400000 {
- compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
- "snps,dwc2";
- reg = <0x0 0xff400000 0x0 0x40000>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_OTG>;
- clock-names = "otg";
- dr_mode = "otg";
- g-np-tx-fifo-size = <16>;
- g-rx-fifo-size = <280>;
- g-tx-fifo-size = <256 128 128 64 32 16>;
- phys = <&u2phy_otg>;
- phy-names = "usb2-phy";
- status = "disabled";
- };
-
- usb_host_ehci: usb@ff440000 {
- compatible = "generic-ehci";
- reg = <0x0 0xff440000 0x0 0x10000>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
- phys = <&u2phy_host>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usb_host_ohci: usb@ff450000 {
- compatible = "generic-ohci";
- reg = <0x0 0xff450000 0x0 0x10000>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
- phys = <&u2phy_host>;
- phy-names = "usb";
- status = "disabled";
- };
-
- sdmmc: mmc@ff480000 {
- compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xff480000 0x0 0x4000>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- bus-width = <4>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
- status = "disabled";
- };
-
- emmc: mmc@ff490000 {
- compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xff490000 0x0 0x4000>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- bus-width = <8>;
- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <150000000>;
- status = "disabled";
- };
-
- sdio: mmc@ff4a0000 {
- compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xff4a0000 0x0 0x4000>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- bus-width = <4>;
- clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
- status = "disabled";
- };
-
- nfc: nand-controller@ff4b0000 {
- compatible = "rockchip,rk3308-nfc",
- "rockchip,rv1108-nfc";
- reg = <0x0 0xff4b0000 0x0 0x4000>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
- clock-names = "ahb", "nfc";
- assigned-clocks = <&cru SCLK_NANDC>;
- assigned-clock-rates = <150000000>;
- pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
- &flash_rdn &flash_rdy &flash_wrn>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- gmac: ethernet@ff4e0000 {
- compatible = "rockchip,rk3308-gmac";
- reg = <0x0 0xff4e0000 0x0 0x10000>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
- <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
- <&cru SCLK_MAC>, <&cru ACLK_MAC>,
- <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
- clock-names = "stmmaceth", "mac_clk_rx",
- "mac_clk_tx", "clk_mac_ref",
- "clk_mac_refout", "aclk_mac",
- "pclk_mac", "clk_mac_speed";
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
- resets = <&cru SRST_MAC_A>;
- reset-names = "stmmaceth";
- rockchip,grf = <&grf>;
- status = "disabled";
- };
-
- sfc: spi@ff4c0000 {
- compatible = "rockchip,sfc";
- reg = <0x0 0xff4c0000 0x0 0x4000>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
- clock-names = "clk_sfc", "hclk_sfc";
- pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- cru: clock-controller@ff500000 {
- compatible = "rockchip,rk3308-cru";
- reg = <0x0 0xff500000 0x0 0x1000>;
- clocks = <&xin24m>;
- clock-names = "xin24m";
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- assigned-clocks = <&cru SCLK_RTC32K>;
- assigned-clock-rates = <32768>;
- };
-
- gic: interrupt-controller@ff580000 {
- compatible = "arm,gic-400";
- reg = <0x0 0xff581000 0x0 0x1000>,
- <0x0 0xff582000 0x0 0x2000>,
- <0x0 0xff584000 0x0 0x2000>,
- <0x0 0xff586000 0x0 0x2000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <3>;
- interrupt-controller;
- #address-cells = <0>;
- };
-
- sram: sram@fff80000 {
- compatible = "mmio-sram";
- reg = <0x0 0xfff80000 0x0 0x40000>;
- ranges = <0 0x0 0xfff80000 0x40000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* reserved for ddr dvfs and system suspend/resume */
- ddr-sram@0 {
- reg = <0x0 0x8000>;
- };
-
- /* reserved for vad audio buffer */
- vad_sram: vad-sram@8000 {
- reg = <0x8000 0x38000>;
- };
- };
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3308-pinctrl";
- rockchip,grf = <&grf>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio@ff220000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff220000 0x0 0x100>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO0>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@ff230000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff230000 0x0 0x100>;
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO1>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@ff240000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff240000 0x0 0x100>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO2>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@ff250000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff250000 0x0 0x100>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO3>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@ff260000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff260000 0x0 0x100>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO4>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- pcfg_pull_up: pcfg-pull-up {
- bias-pull-up;
- };
-
- pcfg_pull_down: pcfg-pull-down {
- bias-pull-down;
- };
-
- pcfg_pull_none: pcfg-pull-none {
- bias-disable;
- };
-
- pcfg_pull_none_2ma: pcfg-pull-none-2ma {
- bias-disable;
- drive-strength = <2>;
- };
-
- pcfg_pull_up_2ma: pcfg-pull-up-2ma {
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pcfg_pull_up_4ma: pcfg-pull-up-4ma {
- bias-pull-up;
- drive-strength = <4>;
- };
-
- pcfg_pull_none_4ma: pcfg-pull-none-4ma {
- bias-disable;
- drive-strength = <4>;
- };
-
- pcfg_pull_down_4ma: pcfg-pull-down-4ma {
- bias-pull-down;
- drive-strength = <4>;
- };
-
- pcfg_pull_none_8ma: pcfg-pull-none-8ma {
- bias-disable;
- drive-strength = <8>;
- };
-
- pcfg_pull_up_8ma: pcfg-pull-up-8ma {
- bias-pull-up;
- drive-strength = <8>;
- };
-
- pcfg_pull_none_12ma: pcfg-pull-none-12ma {
- bias-disable;
- drive-strength = <12>;
- };
-
- pcfg_pull_up_12ma: pcfg-pull-up-12ma {
- bias-pull-up;
- drive-strength = <12>;
- };
-
- pcfg_pull_none_smt: pcfg-pull-none-smt {
- bias-disable;
- input-schmitt-enable;
- };
-
- pcfg_output_high: pcfg-output-high {
- output-high;
- };
-
- pcfg_output_low: pcfg-output-low {
- output-low;
- };
-
- pcfg_input_high: pcfg-input-high {
- bias-pull-up;
- input-enable;
- };
-
- pcfg_input: pcfg-input {
- input-enable;
- };
-
- emmc {
- emmc_clk: emmc-clk {
- rockchip,pins =
- <3 RK_PB1 2 &pcfg_pull_none_8ma>;
- };
-
- emmc_cmd: emmc-cmd {
- rockchip,pins =
- <3 RK_PB0 2 &pcfg_pull_up_8ma>;
- };
-
- emmc_pwren: emmc-pwren {
- rockchip,pins =
- <3 RK_PB3 2 &pcfg_pull_none>;
- };
-
- emmc_rstn: emmc-rstn {
- rockchip,pins =
- <3 RK_PB2 2 &pcfg_pull_none>;
- };
-
- emmc_bus1: emmc-bus1 {
- rockchip,pins =
- <3 RK_PA0 2 &pcfg_pull_up_8ma>;
- };
-
- emmc_bus4: emmc-bus4 {
- rockchip,pins =
- <3 RK_PA0 2 &pcfg_pull_up_8ma>,
- <3 RK_PA1 2 &pcfg_pull_up_8ma>,
- <3 RK_PA2 2 &pcfg_pull_up_8ma>,
- <3 RK_PA3 2 &pcfg_pull_up_8ma>;
- };
-
- emmc_bus8: emmc-bus8 {
- rockchip,pins =
- <3 RK_PA0 2 &pcfg_pull_up_8ma>,
- <3 RK_PA1 2 &pcfg_pull_up_8ma>,
- <3 RK_PA2 2 &pcfg_pull_up_8ma>,
- <3 RK_PA3 2 &pcfg_pull_up_8ma>,
- <3 RK_PA4 2 &pcfg_pull_up_8ma>,
- <3 RK_PA5 2 &pcfg_pull_up_8ma>,
- <3 RK_PA6 2 &pcfg_pull_up_8ma>,
- <3 RK_PA7 2 &pcfg_pull_up_8ma>;
- };
- };
-
- flash {
- flash_csn0: flash-csn0 {
- rockchip,pins =
- <3 RK_PB5 1 &pcfg_pull_none>;
- };
-
- flash_rdy: flash-rdy {
- rockchip,pins =
- <3 RK_PB4 1 &pcfg_pull_none>;
- };
-
- flash_ale: flash-ale {
- rockchip,pins =
- <3 RK_PB3 1 &pcfg_pull_none>;
- };
-
- flash_cle: flash-cle {
- rockchip,pins =
- <3 RK_PB1 1 &pcfg_pull_none>;
- };
-
- flash_wrn: flash-wrn {
- rockchip,pins =
- <3 RK_PB0 1 &pcfg_pull_none>;
- };
-
- flash_rdn: flash-rdn {
- rockchip,pins =
- <3 RK_PB2 1 &pcfg_pull_none>;
- };
-
- flash_bus8: flash-bus8 {
- rockchip,pins =
- <3 RK_PA0 1 &pcfg_pull_up_12ma>,
- <3 RK_PA1 1 &pcfg_pull_up_12ma>,
- <3 RK_PA2 1 &pcfg_pull_up_12ma>,
- <3 RK_PA3 1 &pcfg_pull_up_12ma>,
- <3 RK_PA4 1 &pcfg_pull_up_12ma>,
- <3 RK_PA5 1 &pcfg_pull_up_12ma>,
- <3 RK_PA6 1 &pcfg_pull_up_12ma>,
- <3 RK_PA7 1 &pcfg_pull_up_12ma>;
- };
- };
-
- sfc {
- sfc_bus4: sfc-bus4 {
- rockchip,pins =
- <3 RK_PA0 3 &pcfg_pull_none>,
- <3 RK_PA1 3 &pcfg_pull_none>,
- <3 RK_PA2 3 &pcfg_pull_none>,
- <3 RK_PA3 3 &pcfg_pull_none>;
- };
-
- sfc_bus2: sfc-bus2 {
- rockchip,pins =
- <3 RK_PA0 3 &pcfg_pull_none>,
- <3 RK_PA1 3 &pcfg_pull_none>;
- };
-
- sfc_cs0: sfc-cs0 {
- rockchip,pins =
- <3 RK_PA4 3 &pcfg_pull_none>;
- };
-
- sfc_clk: sfc-clk {
- rockchip,pins =
- <3 RK_PA5 3 &pcfg_pull_none>;
- };
- };
-
- gmac {
- rmii_pins: rmii-pins {
- rockchip,pins =
- /* mac_txen */
- <1 RK_PC1 3 &pcfg_pull_none_12ma>,
- /* mac_txd1 */
- <1 RK_PC3 3 &pcfg_pull_none_12ma>,
- /* mac_txd0 */
- <1 RK_PC2 3 &pcfg_pull_none_12ma>,
- /* mac_rxd0 */
- <1 RK_PC4 3 &pcfg_pull_none>,
- /* mac_rxd1 */
- <1 RK_PC5 3 &pcfg_pull_none>,
- /* mac_rxer */
- <1 RK_PB7 3 &pcfg_pull_none>,
- /* mac_rxdv */
- <1 RK_PC0 3 &pcfg_pull_none>,
- /* mac_mdio */
- <1 RK_PB6 3 &pcfg_pull_none>,
- /* mac_mdc */
- <1 RK_PB5 3 &pcfg_pull_none>;
- };
-
- mac_refclk_12ma: mac-refclk-12ma {
- rockchip,pins =
- <1 RK_PB4 3 &pcfg_pull_none_12ma>;
- };
-
- mac_refclk: mac-refclk {
- rockchip,pins =
- <1 RK_PB4 3 &pcfg_pull_none>;
- };
- };
-
- gmac-m1 {
- rmiim1_pins: rmiim1-pins {
- rockchip,pins =
- /* mac_txen */
- <4 RK_PB7 2 &pcfg_pull_none_12ma>,
- /* mac_txd1 */
- <4 RK_PA5 2 &pcfg_pull_none_12ma>,
- /* mac_txd0 */
- <4 RK_PA4 2 &pcfg_pull_none_12ma>,
- /* mac_rxd0 */
- <4 RK_PA2 2 &pcfg_pull_none>,
- /* mac_rxd1 */
- <4 RK_PA3 2 &pcfg_pull_none>,
- /* mac_rxer */
- <4 RK_PA0 2 &pcfg_pull_none>,
- /* mac_rxdv */
- <4 RK_PA1 2 &pcfg_pull_none>,
- /* mac_mdio */
- <4 RK_PB6 2 &pcfg_pull_none>,
- /* mac_mdc */
- <4 RK_PB5 2 &pcfg_pull_none>;
- };
-
- macm1_refclk_12ma: macm1-refclk-12ma {
- rockchip,pins =
- <4 RK_PB4 2 &pcfg_pull_none_12ma>;
- };
-
- macm1_refclk: macm1-refclk {
- rockchip,pins =
- <4 RK_PB4 2 &pcfg_pull_none>;
- };
- };
-
- i2c0 {
- i2c0_xfer: i2c0-xfer {
- rockchip,pins =
- <1 RK_PD0 2 &pcfg_pull_none_smt>,
- <1 RK_PD1 2 &pcfg_pull_none_smt>;
- };
- };
-
- i2c1 {
- i2c1_xfer: i2c1-xfer {
- rockchip,pins =
- <0 RK_PB3 1 &pcfg_pull_none_smt>,
- <0 RK_PB4 1 &pcfg_pull_none_smt>;
- };
- };
-
- i2c2 {
- i2c2_xfer: i2c2-xfer {
- rockchip,pins =
- <2 RK_PA2 3 &pcfg_pull_none_smt>,
- <2 RK_PA3 3 &pcfg_pull_none_smt>;
- };
- };
-
- i2c3-m0 {
- i2c3m0_xfer: i2c3m0-xfer {
- rockchip,pins =
- <0 RK_PB7 2 &pcfg_pull_none_smt>,
- <0 RK_PC0 2 &pcfg_pull_none_smt>;
- };
- };
-
- i2c3-m1 {
- i2c3m1_xfer: i2c3m1-xfer {
- rockchip,pins =
- <3 RK_PB4 2 &pcfg_pull_none_smt>,
- <3 RK_PB5 2 &pcfg_pull_none_smt>;
- };
- };
-
- i2c3-m2 {
- i2c3m2_xfer: i2c3m2-xfer {
- rockchip,pins =
- <2 RK_PA1 3 &pcfg_pull_none_smt>,
- <2 RK_PA0 3 &pcfg_pull_none_smt>;
- };
- };
-
- i2s_2ch_0 {
- i2s_2ch_0_mclk: i2s-2ch-0-mclk {
- rockchip,pins =
- <4 RK_PB4 1 &pcfg_pull_none>;
- };
-
- i2s_2ch_0_sclk: i2s-2ch-0-sclk {
- rockchip,pins =
- <4 RK_PB5 1 &pcfg_pull_none>;
- };
-
- i2s_2ch_0_lrck: i2s-2ch-0-lrck {
- rockchip,pins =
- <4 RK_PB6 1 &pcfg_pull_none>;
- };
-
- i2s_2ch_0_sdo: i2s-2ch-0-sdo {
- rockchip,pins =
- <4 RK_PB7 1 &pcfg_pull_none>;
- };
-
- i2s_2ch_0_sdi: i2s-2ch-0-sdi {
- rockchip,pins =
- <4 RK_PC0 1 &pcfg_pull_none>;
- };
- };
-
- i2s_8ch_0 {
- i2s_8ch_0_mclk: i2s-8ch-0-mclk {
- rockchip,pins =
- <2 RK_PA4 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
- rockchip,pins =
- <2 RK_PA5 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
- rockchip,pins =
- <2 RK_PA6 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
- rockchip,pins =
- <2 RK_PA7 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
- rockchip,pins =
- <2 RK_PB0 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
- rockchip,pins =
- <2 RK_PB1 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
- rockchip,pins =
- <2 RK_PB2 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
- rockchip,pins =
- <2 RK_PB3 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
- rockchip,pins =
- <2 RK_PB4 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
- rockchip,pins =
- <2 RK_PB5 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
- rockchip,pins =
- <2 RK_PB6 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
- rockchip,pins =
- <2 RK_PB7 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
- rockchip,pins =
- <2 RK_PC0 1 &pcfg_pull_none>;
- };
- };
-
- i2s_8ch_1_m0 {
- i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
- rockchip,pins =
- <1 RK_PA2 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
- rockchip,pins =
- <1 RK_PA3 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
- rockchip,pins =
- <1 RK_PA4 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
- rockchip,pins =
- <1 RK_PA5 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
- rockchip,pins =
- <1 RK_PA6 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
- rockchip,pins =
- <1 RK_PA7 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
- rockchip,pins =
- <1 RK_PB0 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
- rockchip,pins =
- <1 RK_PB1 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
- rockchip,pins =
- <1 RK_PB2 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
- rockchip,pins =
- <1 RK_PB3 2 &pcfg_pull_none>;
- };
- };
-
- i2s_8ch_1_m1 {
- i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
- rockchip,pins =
- <1 RK_PB4 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
- rockchip,pins =
- <1 RK_PB5 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
- rockchip,pins =
- <1 RK_PB6 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
- rockchip,pins =
- <1 RK_PB7 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
- rockchip,pins =
- <1 RK_PC0 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
- rockchip,pins =
- <1 RK_PC1 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
- rockchip,pins =
- <1 RK_PC2 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
- rockchip,pins =
- <1 RK_PC3 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
- rockchip,pins =
- <1 RK_PC4 2 &pcfg_pull_none>;
- };
-
- i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
- rockchip,pins =
- <1 RK_PC5 2 &pcfg_pull_none>;
- };
- };
-
- pdm_m0 {
- pdm_m0_clk: pdm-m0-clk {
- rockchip,pins =
- <1 RK_PA4 3 &pcfg_pull_none>;
- };
-
- pdm_m0_sdi0: pdm-m0-sdi0 {
- rockchip,pins =
- <1 RK_PB3 3 &pcfg_pull_none>;
- };
-
- pdm_m0_sdi1: pdm-m0-sdi1 {
- rockchip,pins =
- <1 RK_PB2 3 &pcfg_pull_none>;
- };
-
- pdm_m0_sdi2: pdm-m0-sdi2 {
- rockchip,pins =
- <1 RK_PB1 3 &pcfg_pull_none>;
- };
-
- pdm_m0_sdi3: pdm-m0-sdi3 {
- rockchip,pins =
- <1 RK_PB0 3 &pcfg_pull_none>;
- };
- };
-
- pdm_m1 {
- pdm_m1_clk: pdm-m1-clk {
- rockchip,pins =
- <1 RK_PB6 4 &pcfg_pull_none>;
- };
-
- pdm_m1_sdi0: pdm-m1-sdi0 {
- rockchip,pins =
- <1 RK_PC5 4 &pcfg_pull_none>;
- };
-
- pdm_m1_sdi1: pdm-m1-sdi1 {
- rockchip,pins =
- <1 RK_PC4 4 &pcfg_pull_none>;
- };
-
- pdm_m1_sdi2: pdm-m1-sdi2 {
- rockchip,pins =
- <1 RK_PC3 4 &pcfg_pull_none>;
- };
-
- pdm_m1_sdi3: pdm-m1-sdi3 {
- rockchip,pins =
- <1 RK_PC2 4 &pcfg_pull_none>;
- };
- };
-
- pdm_m2 {
- pdm_m2_clkm: pdm-m2-clkm {
- rockchip,pins =
- <2 RK_PA4 3 &pcfg_pull_none>;
- };
-
- pdm_m2_clk: pdm-m2-clk {
- rockchip,pins =
- <2 RK_PA6 2 &pcfg_pull_none>;
- };
-
- pdm_m2_sdi0: pdm-m2-sdi0 {
- rockchip,pins =
- <2 RK_PB5 2 &pcfg_pull_none>;
- };
-
- pdm_m2_sdi1: pdm-m2-sdi1 {
- rockchip,pins =
- <2 RK_PB6 2 &pcfg_pull_none>;
- };
-
- pdm_m2_sdi2: pdm-m2-sdi2 {
- rockchip,pins =
- <2 RK_PB7 2 &pcfg_pull_none>;
- };
-
- pdm_m2_sdi3: pdm-m2-sdi3 {
- rockchip,pins =
- <2 RK_PC0 2 &pcfg_pull_none>;
- };
- };
-
- pwm0 {
- pwm0_pin: pwm0-pin {
- rockchip,pins =
- <0 RK_PB5 1 &pcfg_pull_none>;
- };
-
- pwm0_pin_pull_down: pwm0-pin-pull-down {
- rockchip,pins =
- <0 RK_PB5 1 &pcfg_pull_down>;
- };
- };
-
- pwm1 {
- pwm1_pin: pwm1-pin {
- rockchip,pins =
- <0 RK_PB6 1 &pcfg_pull_none>;
- };
-
- pwm1_pin_pull_down: pwm1-pin-pull-down {
- rockchip,pins =
- <0 RK_PB6 1 &pcfg_pull_down>;
- };
- };
-
- pwm2 {
- pwm2_pin: pwm2-pin {
- rockchip,pins =
- <0 RK_PB7 1 &pcfg_pull_none>;
- };
-
- pwm2_pin_pull_down: pwm2-pin-pull-down {
- rockchip,pins =
- <0 RK_PB7 1 &pcfg_pull_down>;
- };
- };
-
- pwm3 {
- pwm3_pin: pwm3-pin {
- rockchip,pins =
- <0 RK_PC0 1 &pcfg_pull_none>;
- };
-
- pwm3_pin_pull_down: pwm3-pin-pull-down {
- rockchip,pins =
- <0 RK_PC0 1 &pcfg_pull_down>;
- };
- };
-
- pwm4 {
- pwm4_pin: pwm4-pin {
- rockchip,pins =
- <0 RK_PA1 2 &pcfg_pull_none>;
- };
-
- pwm4_pin_pull_down: pwm4-pin-pull-down {
- rockchip,pins =
- <0 RK_PA1 2 &pcfg_pull_down>;
- };
- };
-
- pwm5 {
- pwm5_pin: pwm5-pin {
- rockchip,pins =
- <0 RK_PC1 2 &pcfg_pull_none>;
- };
-
- pwm5_pin_pull_down: pwm5-pin-pull-down {
- rockchip,pins =
- <0 RK_PC1 2 &pcfg_pull_down>;
- };
- };
-
- pwm6 {
- pwm6_pin: pwm6-pin {
- rockchip,pins =
- <0 RK_PC2 2 &pcfg_pull_none>;
- };
-
- pwm6_pin_pull_down: pwm6-pin-pull-down {
- rockchip,pins =
- <0 RK_PC2 2 &pcfg_pull_down>;
- };
- };
-
- pwm7 {
- pwm7_pin: pwm7-pin {
- rockchip,pins =
- <2 RK_PB0 2 &pcfg_pull_none>;
- };
-
- pwm7_pin_pull_down: pwm7-pin-pull-down {
- rockchip,pins =
- <2 RK_PB0 2 &pcfg_pull_down>;
- };
- };
-
- pwm8 {
- pwm8_pin: pwm8-pin {
- rockchip,pins =
- <2 RK_PB2 2 &pcfg_pull_none>;
- };
-
- pwm8_pin_pull_down: pwm8-pin-pull-down {
- rockchip,pins =
- <2 RK_PB2 2 &pcfg_pull_down>;
- };
- };
-
- pwm9 {
- pwm9_pin: pwm9-pin {
- rockchip,pins =
- <2 RK_PB3 2 &pcfg_pull_none>;
- };
-
- pwm9_pin_pull_down: pwm9-pin-pull-down {
- rockchip,pins =
- <2 RK_PB3 2 &pcfg_pull_down>;
- };
- };
-
- pwm10 {
- pwm10_pin: pwm10-pin {
- rockchip,pins =
- <2 RK_PB4 2 &pcfg_pull_none>;
- };
-
- pwm10_pin_pull_down: pwm10-pin-pull-down {
- rockchip,pins =
- <2 RK_PB4 2 &pcfg_pull_down>;
- };
- };
-
- pwm11 {
- pwm11_pin: pwm11-pin {
- rockchip,pins =
- <2 RK_PC0 4 &pcfg_pull_none>;
- };
-
- pwm11_pin_pull_down: pwm11-pin-pull-down {
- rockchip,pins =
- <2 RK_PC0 4 &pcfg_pull_down>;
- };
- };
-
- rtc {
- rtc_32k: rtc-32k {
- rockchip,pins =
- <0 RK_PC3 1 &pcfg_pull_none>;
- };
- };
-
- sdmmc {
- sdmmc_clk: sdmmc-clk {
- rockchip,pins =
- <4 RK_PD5 1 &pcfg_pull_none_4ma>;
- };
-
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins =
- <4 RK_PD4 1 &pcfg_pull_up_4ma>;
- };
-
- sdmmc_det: sdmmc-det {
- rockchip,pins =
- <0 RK_PA3 1 &pcfg_pull_up_4ma>;
- };
-
- sdmmc_pwren: sdmmc-pwren {
- rockchip,pins =
- <4 RK_PD6 1 &pcfg_pull_none_4ma>;
- };
-
- sdmmc_bus1: sdmmc-bus1 {
- rockchip,pins =
- <4 RK_PD0 1 &pcfg_pull_up_4ma>;
- };
-
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins =
- <4 RK_PD0 1 &pcfg_pull_up_4ma>,
- <4 RK_PD1 1 &pcfg_pull_up_4ma>,
- <4 RK_PD2 1 &pcfg_pull_up_4ma>,
- <4 RK_PD3 1 &pcfg_pull_up_4ma>;
- };
- };
-
- sdio {
- sdio_clk: sdio-clk {
- rockchip,pins =
- <4 RK_PA5 1 &pcfg_pull_none_8ma>;
- };
-
- sdio_cmd: sdio-cmd {
- rockchip,pins =
- <4 RK_PA4 1 &pcfg_pull_up_8ma>;
- };
-
- sdio_pwren: sdio-pwren {
- rockchip,pins =
- <0 RK_PA2 1 &pcfg_pull_none_8ma>;
- };
-
- sdio_wrpt: sdio-wrpt {
- rockchip,pins =
- <0 RK_PA1 1 &pcfg_pull_none_8ma>;
- };
-
- sdio_intn: sdio-intn {
- rockchip,pins =
- <0 RK_PA0 1 &pcfg_pull_none_8ma>;
- };
-
- sdio_bus1: sdio-bus1 {
- rockchip,pins =
- <4 RK_PA0 1 &pcfg_pull_up_8ma>;
- };
-
- sdio_bus4: sdio-bus4 {
- rockchip,pins =
- <4 RK_PA0 1 &pcfg_pull_up_8ma>,
- <4 RK_PA1 1 &pcfg_pull_up_8ma>,
- <4 RK_PA2 1 &pcfg_pull_up_8ma>,
- <4 RK_PA3 1 &pcfg_pull_up_8ma>;
- };
- };
-
- spdif_in {
- spdif_in: spdif-in {
- rockchip,pins =
- <0 RK_PC2 1 &pcfg_pull_none>;
- };
- };
-
- spdif_out {
- spdif_out: spdif-out {
- rockchip,pins =
- <0 RK_PC1 1 &pcfg_pull_none>;
- };
- };
-
- spi0 {
- spi0_clk: spi0-clk {
- rockchip,pins =
- <2 RK_PA2 2 &pcfg_pull_up_4ma>;
- };
-
- spi0_csn0: spi0-csn0 {
- rockchip,pins =
- <2 RK_PA3 2 &pcfg_pull_up_4ma>;
- };
-
- spi0_miso: spi0-miso {
- rockchip,pins =
- <2 RK_PA0 2 &pcfg_pull_up_4ma>;
- };
-
- spi0_mosi: spi0-mosi {
- rockchip,pins =
- <2 RK_PA1 2 &pcfg_pull_up_4ma>;
- };
- };
-
- spi1 {
- spi1_clk: spi1-clk {
- rockchip,pins =
- <3 RK_PB3 3 &pcfg_pull_up_4ma>;
- };
-
- spi1_csn0: spi1-csn0 {
- rockchip,pins =
- <3 RK_PB5 3 &pcfg_pull_up_4ma>;
- };
-
- spi1_miso: spi1-miso {
- rockchip,pins =
- <3 RK_PB2 3 &pcfg_pull_up_4ma>;
- };
-
- spi1_mosi: spi1-mosi {
- rockchip,pins =
- <3 RK_PB4 3 &pcfg_pull_up_4ma>;
- };
- };
-
- spi1-m1 {
- spi1m1_miso: spi1m1-miso {
- rockchip,pins =
- <2 RK_PA4 2 &pcfg_pull_up_4ma>;
- };
-
- spi1m1_mosi: spi1m1-mosi {
- rockchip,pins =
- <2 RK_PA5 2 &pcfg_pull_up_4ma>;
- };
-
- spi1m1_clk: spi1m1-clk {
- rockchip,pins =
- <2 RK_PA7 2 &pcfg_pull_up_4ma>;
- };
-
- spi1m1_csn0: spi1m1-csn0 {
- rockchip,pins =
- <2 RK_PB1 2 &pcfg_pull_up_4ma>;
- };
- };
-
- spi2 {
- spi2_clk: spi2-clk {
- rockchip,pins =
- <1 RK_PD0 3 &pcfg_pull_up_4ma>;
- };
-
- spi2_csn0: spi2-csn0 {
- rockchip,pins =
- <1 RK_PD1 3 &pcfg_pull_up_4ma>;
- };
-
- spi2_miso: spi2-miso {
- rockchip,pins =
- <1 RK_PC6 3 &pcfg_pull_up_4ma>;
- };
-
- spi2_mosi: spi2-mosi {
- rockchip,pins =
- <1 RK_PC7 3 &pcfg_pull_up_4ma>;
- };
- };
-
- tsadc {
- tsadc_otp_pin: tsadc-otp-pin {
- rockchip,pins =
- <0 RK_PB2 0 &pcfg_pull_none>;
- };
-
- tsadc_otp_out: tsadc-otp-out {
- rockchip,pins =
- <0 RK_PB2 1 &pcfg_pull_none>;
- };
- };
-
- uart0 {
- uart0_xfer: uart0-xfer {
- rockchip,pins =
- <2 RK_PA1 1 &pcfg_pull_up>,
- <2 RK_PA0 1 &pcfg_pull_up>;
- };
-
- uart0_cts: uart0-cts {
- rockchip,pins =
- <2 RK_PA2 1 &pcfg_pull_none>;
- };
-
- uart0_rts: uart0-rts {
- rockchip,pins =
- <2 RK_PA3 1 &pcfg_pull_none>;
- };
-
- uart0_rts_pin: uart0-rts-pin {
- rockchip,pins =
- <2 RK_PA3 0 &pcfg_pull_none>;
- };
- };
-
- uart1 {
- uart1_xfer: uart1-xfer {
- rockchip,pins =
- <1 RK_PD1 1 &pcfg_pull_up>,
- <1 RK_PD0 1 &pcfg_pull_up>;
- };
-
- uart1_cts: uart1-cts {
- rockchip,pins =
- <1 RK_PC6 1 &pcfg_pull_none>;
- };
-
- uart1_rts: uart1-rts {
- rockchip,pins =
- <1 RK_PC7 1 &pcfg_pull_none>;
- };
- };
-
- uart2-m0 {
- uart2m0_xfer: uart2m0-xfer {
- rockchip,pins =
- <1 RK_PC7 2 &pcfg_pull_up>,
- <1 RK_PC6 2 &pcfg_pull_up>;
- };
- };
-
- uart2-m1 {
- uart2m1_xfer: uart2m1-xfer {
- rockchip,pins =
- <4 RK_PD3 2 &pcfg_pull_up>,
- <4 RK_PD2 2 &pcfg_pull_up>;
- };
- };
-
- uart3 {
- uart3_xfer: uart3-xfer {
- rockchip,pins =
- <3 RK_PB5 4 &pcfg_pull_up>,
- <3 RK_PB4 4 &pcfg_pull_up>;
- };
- };
-
- uart3-m1 {
- uart3m1_xfer: uart3m1-xfer {
- rockchip,pins =
- <0 RK_PC2 3 &pcfg_pull_up>,
- <0 RK_PC1 3 &pcfg_pull_up>;
- };
- };
-
- uart4 {
- uart4_xfer: uart4-xfer {
- rockchip,pins =
- <4 RK_PB1 1 &pcfg_pull_up>,
- <4 RK_PB0 1 &pcfg_pull_up>;
- };
-
- uart4_cts: uart4-cts {
- rockchip,pins =
- <4 RK_PA6 1 &pcfg_pull_none>;
- };
-
- uart4_rts: uart4-rts {
- rockchip,pins =
- <4 RK_PA7 1 &pcfg_pull_none>;
- };
-
- uart4_rts_pin: uart4-rts-pin {
- rockchip,pins =
- <4 RK_PA7 0 &pcfg_pull_none>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-#include "rk3328.dtsi"
-
-/ {
- model = "Rockchip RK3328 EVB";
- compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
-
- aliases {
- ethernet0 = &gmac2phy;
- mmc0 = &sdmmc;
- mmc1 = &sdio;
- mmc2 = &emmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- dc_12v: dc-12v {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
-
- /*
- * On the module itself this is one of these (depending
- * on the actual card populated):
- * - SDIO_RESET_L_WL_REG_ON
- * - PDN (power down when low)
- */
- reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
- };
-
- vcc_sd: sdmmc-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0m1_pin>;
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_io>;
- };
-
- vcc_sys: vcc-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc_phy: vcc-phy-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_phy";
- regulator-always-on;
- regulator-boot-on;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
- status = "okay";
-};
-
-&gmac2phy {
- phy-supply = <&vcc_phy>;
- clock_in_out = "output";
- assigned-clock-rate = <50000000>;
- assigned-clocks = <&cru SCLK_MAC2PHY>;
- assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-
- rk805: pmic@18 {
- compatible = "rockchip,rk805";
- reg = <0x18>;
- interrupt-parent = <&gpio2>;
- interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk805-clkout2";
- gpio-controller;
- #gpio-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc5-supply = <&vcc_io>;
- vcc6-supply = <&vcc_io>;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1450000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1450000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_io: DCDC_REG4 {
- regulator-name = "vcc_io";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_18: LDO_REG1 {
- regulator-name = "vcc_18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc18_emmc: LDO_REG2 {
- regulator-name = "vcc18_emmc";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_10: LDO_REG3 {
- regulator-name = "vdd_10";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
- };
- };
-};
-
-&pinctrl {
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins =
- <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdio {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- max-frequency = <150000000>;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
- vmmc-supply = <&vcc_sd>;
- status = "okay";
-};
-
-&tsadc {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-};
-
-&u2phy_host {
- status = "okay";
-};
-
-&u2phy_otg {
- status = "okay";
-};
-
-&usb20_otg {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyarm.com)
- *
- * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
- */
-
-/dts-v1/;
-#include "rk3328-nanopi-r2c.dts"
-
-/ {
- model = "FriendlyElec NanoPi R2C Plus";
- compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
-
- aliases {
- mmc1 = &emmc;
- };
-};
-
-&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- max-frequency = <150000000>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
- vmmc-supply = <&vcc_io_33>;
- vqmmc-supply = <&vcc18_emmc>;
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyarm.com)
- *
- * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
- */
-
-/dts-v1/;
-#include "rk3328-nanopi-r2s.dts"
-
-/ {
- model = "FriendlyElec NanoPi R2C";
- compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
-};
-
-&gmac2io {
- phy-handle = <&yt8521s>;
- tx_delay = <0x22>;
- rx_delay = <0x12>;
-
- mdio {
- /delete-node/ ethernet-phy@1;
-
- yt8521s: ethernet-phy@3 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <3>;
-
- motorcomm,clk-out-frequency-hz = <125000000>;
- motorcomm,keep-pll-enabled;
- motorcomm,auto-sleep-disabled;
-
- pinctrl-0 = <ð_phy_reset_pin>;
- pinctrl-names = "default";
- reset-assert-us = <10000>;
- reset-deassert-us = <50000>;
- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- };
- };
-};
};
&sdio_vcc_pin {
- bootph-all;
+ bootph-pre-ram;
};
&usb20_otg {
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include "rk3328.dtsi"
-
-/ {
- model = "FriendlyElec NanoPi R2S";
- compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
-
- aliases {
- ethernet0 = &gmac2io;
- ethernet1 = &rtl8153;
- mmc0 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- gmac_clk: gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "gmac_clkin";
- #clock-cells = <0>;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&reset_button_pin>;
- pinctrl-names = "default";
-
- key-reset {
- label = "reset";
- gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <50>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
- pinctrl-names = "default";
-
- lan_led: led-0 {
- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
- label = "nanopi-r2s:green:lan";
- };
-
- sys_led: led-1 {
- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
- label = "nanopi-r2s:red:sys";
- default-state = "on";
- };
-
- wan_led: led-2 {
- gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
- label = "nanopi-r2s:green:wan";
- };
- };
-
- vcc_io_sdio: sdmmcio-regulator {
- compatible = "regulator-gpio";
- enable-active-high;
- gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&sdio_vcc_pin>;
- pinctrl-names = "default";
- regulator-name = "vcc_io_sdio";
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-settling-time-us = <5000>;
- regulator-type = "voltage";
- startup-delay-us = <2000>;
- states = <1800000 0x1>,
- <3300000 0x0>;
- vin-supply = <&vcc_io_33>;
- };
-
- vcc_sd: sdmmc-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&sdmmc0m1_pin>;
- pinctrl-names = "default";
- regulator-name = "vcc_sd";
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_io_33>;
- };
-
- vdd_5v: vdd-5v {
- compatible = "regulator-fixed";
- regulator-name = "vdd_5v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vdd_5v_lan: vdd-5v-lan {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&lan_vdd_pin>;
- pinctrl-names = "default";
- regulator-name = "vdd_5v_lan";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_5v>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&display_subsystem {
- status = "disabled";
-};
-
-&gmac2io {
- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
- assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
- clock_in_out = "input";
- phy-handle = <&rtl8211e>;
- phy-mode = "rgmii";
- phy-supply = <&vcc_io_33>;
- pinctrl-0 = <&rgmiim1_pins>;
- pinctrl-names = "default";
- rx_delay = <0x18>;
- snps,aal;
- tx_delay = <0x24>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtl8211e: ethernet-phy@1 {
- reg = <1>;
- pinctrl-0 = <ð_phy_reset_pin>;
- pinctrl-names = "default";
- reset-assert-us = <10000>;
- reset-deassert-us = <50000>;
- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&i2c1 {
- status = "okay";
-
- rk805: pmic@18 {
- compatible = "rockchip,rk805";
- reg = <0x18>;
- interrupt-parent = <&gpio1>;
- interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk805-clkout2";
- gpio-controller;
- #gpio-cells = <2>;
- pinctrl-0 = <&pmic_int_l>;
- pinctrl-names = "default";
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vdd_5v>;
- vcc2-supply = <&vdd_5v>;
- vcc3-supply = <&vdd_5v>;
- vcc4-supply = <&vdd_5v>;
- vcc5-supply = <&vcc_io_33>;
- vcc6-supply = <&vdd_5v>;
-
- regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1450000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1450000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_io_33: DCDC_REG4 {
- regulator-name = "vcc_io_33";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_18: LDO_REG1 {
- regulator-name = "vcc_18";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc18_emmc: LDO_REG2 {
- regulator-name = "vcc18_emmc";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_10: LDO_REG3 {
- regulator-name = "vdd_10";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
- };
- };
-};
-
-&io_domains {
- pmuio-supply = <&vcc_io_33>;
- vccio1-supply = <&vcc_io_33>;
- vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_io_sdio>;
- vccio4-supply = <&vcc_18>;
- vccio5-supply = <&vcc_io_33>;
- vccio6-supply = <&vcc_io_33>;
- status = "okay";
-};
-
-&pinctrl {
- button {
- reset_button_pin: reset-button-pin {
- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- gmac2io {
- eth_phy_reset_pin: eth-phy-reset-pin {
- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- leds {
- lan_led_pin: lan-led-pin {
- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- sys_led_pin: sys-led-pin {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wan_led_pin: wan-led-pin {
- rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- lan {
- lan_vdd_pin: lan-vdd-pin {
- rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- sd {
- sdio_vcc_pin: sdio-vcc-pin {
- rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- disable-wp;
- pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
- pinctrl-names = "default";
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vcc_io_sdio>;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <0>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-};
-
-&u2phy_host {
- status = "okay";
-};
-
-&u2phy_otg {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb20_otg {
- status = "okay";
- dr_mode = "host";
-};
-
-&usbdrd3 {
- dr_mode = "host";
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* Second port is for USB 3.0 */
- rtl8153: device@2 {
- compatible = "usbbda,8153";
- reg = <2>;
- };
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
#include "rk3328-sdram-lpddr3-666.dtsi"
&spi0 {
- bootph-pre-ram;
- bootph-some-ram;
-
flash@0 {
bootph-pre-ram;
bootph-some-ram;
&spi0m2_clk {
bootph-pre-ram;
+ bootph-some-ram;
};
&spi0m2_cs0 {
bootph-pre-ram;
+ bootph-some-ram;
};
&spi0m2_rx {
bootph-pre-ram;
+ bootph-some-ram;
};
&spi0m2_tx {
bootph-pre-ram;
+ bootph-some-ram;
};
&usb20_otg {
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright (c) 2016 Xunlong Software. Co., Ltd.
- * (http://www.orangepi.org)
- *
- * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
- */
-
-/dts-v1/;
-#include "rk3328-orangepi-r1-plus.dts"
-
-/ {
- model = "Xunlong Orange Pi R1 Plus LTS";
- compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
-};
-
-&gmac2io {
- phy-handle = <&yt8531c>;
- tx_delay = <0x19>;
- rx_delay = <0x05>;
-
- mdio {
- /delete-node/ ethernet-phy@1;
-
- yt8531c: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
-
- motorcomm,auto-sleep-disabled;
- motorcomm,clk-out-frequency-hz = <125000000>;
- motorcomm,keep-pll-enabled;
- motorcomm,rx-clk-drv-microamp = <5020>;
- motorcomm,rx-data-drv-microamp = <5020>;
-
- pinctrl-0 = <ð_phy_reset_pin>;
- pinctrl-names = "default";
- reset-assert-us = <15000>;
- reset-deassert-us = <50000>;
- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- };
- };
-};
#include "rk3328-sdram-ddr4-666.dtsi"
&spi0 {
- bootph-pre-ram;
- bootph-some-ram;
-
flash@0 {
bootph-pre-ram;
bootph-some-ram;
&spi0m2_clk {
bootph-pre-ram;
+ bootph-some-ram;
};
&spi0m2_cs0 {
bootph-pre-ram;
+ bootph-some-ram;
};
&spi0m2_rx {
bootph-pre-ram;
+ bootph-some-ram;
};
&spi0m2_tx {
bootph-pre-ram;
+ bootph-some-ram;
};
&usb20_otg {
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Based on rk3328-nanopi-r2s.dts, which is:
- * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include "rk3328.dtsi"
-
-/ {
- model = "Xunlong Orange Pi R1 Plus";
- compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
-
- aliases {
- ethernet0 = &gmac2io;
- ethernet1 = &rtl8153;
- mmc0 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- gmac_clk: gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "gmac_clkin";
- #clock-cells = <0>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
- pinctrl-names = "default";
-
- led-0 {
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
-
- led-2 {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
- };
- };
-
- vcc_sd: sdmmc-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&sdmmc0m1_pin>;
- pinctrl-names = "default";
- regulator-name = "vcc_sd";
- regulator-boot-on;
- vin-supply = <&vcc_io>;
- };
-
- vcc_sys: vcc-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vdd_5v_lan: vdd-5v-lan-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&lan_vdd_pin>;
- pinctrl-names = "default";
- regulator-name = "vdd_5v_lan";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_sys>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&display_subsystem {
- status = "disabled";
-};
-
-&gmac2io {
- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
- assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
- clock_in_out = "input";
- phy-handle = <&rtl8211e>;
- phy-mode = "rgmii";
- phy-supply = <&vcc_io>;
- pinctrl-0 = <&rgmiim1_pins>;
- pinctrl-names = "default";
- snps,aal;
- rx_delay = <0x18>;
- tx_delay = <0x24>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtl8211e: ethernet-phy@1 {
- reg = <1>;
- pinctrl-0 = <ð_phy_reset_pin>;
- pinctrl-names = "default";
- reset-assert-us = <10000>;
- reset-deassert-us = <50000>;
- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&i2c1 {
- status = "okay";
-
- rk805: pmic@18 {
- compatible = "rockchip,rk805";
- reg = <0x18>;
- interrupt-parent = <&gpio1>;
- interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk805-clkout2";
- gpio-controller;
- #gpio-cells = <2>;
- pinctrl-0 = <&pmic_int_l>;
- pinctrl-names = "default";
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc5-supply = <&vcc_io>;
- vcc6-supply = <&vcc_sys>;
-
- regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1450000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1450000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_io: DCDC_REG4 {
- regulator-name = "vcc_io";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_18: LDO_REG1 {
- regulator-name = "vcc_18";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc18_emmc: LDO_REG2 {
- regulator-name = "vcc18_emmc";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_10: LDO_REG3 {
- regulator-name = "vdd_10";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
- };
- };
-};
-
-&io_domains {
- pmuio-supply = <&vcc_io>;
- vccio1-supply = <&vcc_io>;
- vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_io>;
- vccio4-supply = <&vcc_io>;
- vccio5-supply = <&vcc_io>;
- vccio6-supply = <&vcc_io>;
- status = "okay";
-};
-
-&pinctrl {
- gmac2io {
- eth_phy_reset_pin: eth-phy-reset-pin {
- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- leds {
- lan_led_pin: lan-led-pin {
- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- sys_led_pin: sys-led-pin {
- rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wan_led_pin: wan-led-pin {
- rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- lan {
- lan_vdd_pin: lan-vdd-pin {
- rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- disable-wp;
- pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
- pinctrl-names = "default";
- vmmc-supply = <&vcc_sd>;
- status = "okay";
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- };
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <0>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-};
-
-&u2phy_host {
- status = "okay";
-};
-
-&u2phy_otg {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb20_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbdrd3 {
- dr_mode = "host";
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* Second port is for USB 3.0 */
- rtl8153: device@2 {
- compatible = "usbbda,8153";
- reg = <2>;
- };
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
- */
-
-/dts-v1/;
-#include "rk3328.dtsi"
-
-/ {
- model = "Firefly roc-rk3328-cc";
- compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
-
- aliases {
- ethernet0 = &gmac2io;
- mmc0 = &sdmmc;
- mmc1 = &emmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- gmac_clkin: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "gmac_clkin";
- #clock-cells = <0>;
- };
-
- dc_12v: dc-12v {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc_sd: sdmmc-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0m1_pin>;
- regulator-boot-on;
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_io>;
- };
-
- vcc_sdio: sdmmcio-regulator {
- compatible = "regulator-gpio";
- gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x1>,
- <3300000 0x0>;
- regulator-name = "vcc_sdio";
- regulator-type = "voltage";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- vin-supply = <&vcc_sys>;
- };
-
- vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb20_host_drv>;
- regulator-name = "vcc_host1_5v";
- regulator-always-on;
- vin-supply = <&vcc_sys>;
- };
-
- vcc_sys: vcc-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc_phy: vcc-phy-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_phy";
- regulator-always-on;
- regulator-boot-on;
- };
-
- leds {
- compatible = "gpio-leds";
-
- power_led: led-0 {
- label = "firefly:blue:power";
- linux,default-trigger = "heartbeat";
- gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
- default-state = "on";
- };
-
- user_led: led-1 {
- label = "firefly:yellow:user";
- linux,default-trigger = "mmc1";
- gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-};
-
-&analog_sound {
- status = "okay";
-};
-
-&codec {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- max-frequency = <150000000>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
- vmmc-supply = <&vcc_io>;
- vqmmc-supply = <&vcc18_emmc>;
- status = "okay";
-};
-
-&gmac2io {
- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
- assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
- clock_in_out = "input";
- phy-supply = <&vcc_phy>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_pins>;
- snps,aal;
- snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- snps,rxpbl = <0x4>;
- snps,txpbl = <0x4>;
- tx_delay = <0x24>;
- rx_delay = <0x18>;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmiphy {
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-
- rk805: pmic@18 {
- compatible = "rockchip,rk805";
- reg = <0x18>;
- interrupt-parent = <&gpio1>;
- interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk805-clkout2";
- gpio-controller;
- #gpio-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc5-supply = <&vcc_io>;
- vcc6-supply = <&vcc_io>;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1450000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1450000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_io: DCDC_REG4 {
- regulator-name = "vcc_io";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_18: LDO_REG1 {
- regulator-name = "vcc_18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc18_emmc: LDO_REG2 {
- regulator-name = "vcc18_emmc";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_10: LDO_REG3 {
- regulator-name = "vdd_10";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
- };
- };
-};
-
-&i2s0 {
- status = "okay";
-};
-
-&i2s1 {
- status = "okay";
-};
-
-&io_domains {
- status = "okay";
-
- vccio1-supply = <&vcc_io>;
- vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_sdio>;
- vccio4-supply = <&vcc_18>;
- vccio5-supply = <&vcc_io>;
- vccio6-supply = <&vcc_io>;
- pmuio-supply = <&vcc_io>;
-};
-
-&pinctrl {
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- usb20_host_drv: usb20-host-drv {
- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vcc_sdio>;
- status = "okay";
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-};
-
-&u2phy_host {
- status = "okay";
-};
-
-&u2phy_otg {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb20_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbdrd3 {
- dr_mode = "host";
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&vop {
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * (C) Copyright 2020 Chen-Yu Tsai <wens@csie.org>
- *
- * Based on ./rk3328-rock64.dts, which is
- *
- * Copyright (c) 2017 PINE64
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-
-#include "rk3328.dtsi"
-
-/ {
- model = "Radxa ROCK Pi E";
- compatible = "radxa,rockpi-e", "rockchip,rk3328";
-
- aliases {
- ethernet0 = &gmac2io;
- ethernet1 = &gmac2phy;
- mmc0 = &sdmmc;
- mmc1 = &emmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1750000>;
-
- /* This button is unpopulated out of the factory. */
- button-recovery {
- label = "Recovery";
- linux,code = <KEY_VENDOR>;
- press-threshold-microvolt = <10000>;
- };
- };
-
- gmac_clkin: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "gmac_clkin";
- #clock-cells = <0>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pin>;
- pinctrl-names = "default";
-
- led-0 {
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- vcc_sd: sdmmc-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0m1_pin>;
- regulator-name = "vcc_sd";
- regulator-boot-on;
- vin-supply = <&vcc_io>;
- };
-
- vcc_host_5v: vcc-host-5v-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb30_host_drv>;
- enable-active-high;
- regulator-name = "vcc_host_5v";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_sys>;
- };
-
- vcc_sys: vcc-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc_wifi: vcc-wifi-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_en>;
- regulator-name = "vcc_wifi";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_io>;
- };
-};
-
-&analog_sound {
- status = "okay";
-};
-
-&codec {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
- vmmc-supply = <&vcc_io>;
- vqmmc-supply = <&vcc18_emmc>;
- status = "okay";
-};
-
-&gmac2io {
- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
- assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
- clock_in_out = "input";
- phy-handle = <&rtl8211e>;
- phy-mode = "rgmii";
- phy-supply = <&vcc_io>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_pins>;
- snps,aal;
- snps,rxpbl = <0x4>;
- snps,txpbl = <0x4>;
- tx_delay = <0x26>;
- rx_delay = <0x11>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtl8211e: ethernet-phy@1 {
- reg = <1>;
- pinctrl-0 = <ð_phy_int_pin>, <ð_phy_reset_pin>;
- pinctrl-names = "default";
- interrupt-parent = <&gpio1>;
- interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <50000>;
- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&gmac2phy {
- status = "okay";
-};
-
-&gpio0 {
- gpio-line-names =
- /* GPIO0_A0 - A7 */
- "", "", "", "", "", "", "", "",
- /* GPIO0_B0 - B7 */
- "", "", "", "", "", "", "", "",
- /* GPIO0_C0 - C7 */
- "", "", "", "", "", "", "", "",
- /* GPIO0_D0 - D7 */
- "", "", "", "pin-15 [GPIO0_D3]", "", "", "", "";
-};
-
-&gpio1 {
- gpio-line-names =
- /* GPIO1_A0 - A7 */
- "", "", "", "", "", "", "", "",
- /* GPIO1_B0 - B7 */
- "", "", "", "", "", "", "", "",
- /* GPIO1_C0 - C7 */
- "", "", "", "", "", "", "", "",
- /* GPIO1_D0 - D7 */
- "", "", "", "", "pin-07 [GPIO1_D4]", "", "", "";
-};
-
-&gpio2 {
- gpio-line-names =
- /* GPIO2_A0 - A7 */
- "pin-08 [GPIO2_A0]", "pin-10 [GPIO2_A1]", "pin-11 [GPIO2_A2]",
- "pin-13 [GPIO2-A3]", "pin-27 [GPIO2_A4]", "pin-28 [GPIO2_A5]",
- "pin-33 [GPIO2_A6]", "",
- /* GPIO2_B0 - B7 */
- "", "", "", "", "pin-26 [GPIO2_B4]", "", "", "pin-36 [GPIO2_B7]",
- /* GPIO2_C0 - C7 */
- "pin-32 [GPIO2_C0]", "pin-35 [GPIO2_C1]", "pin-12 [GPIO2_C2]",
- "pin-38 [GPIO2_C3]", "pin-29 [GPIO2_C4]", "pin-31 [GPIO2_C5]",
- "pin-37 [GPIO2_C6]", "pin-40 [GPIO2_C7]",
- /* GPIO2_D0 - D7 */
- "", "", "", "", "", "", "", "";
-};
-
-&gpio3 {
- gpio-line-names =
- /* GPIO3_A0 - A7 */
- "pin-23 [GPIO3_A0]", "pin-19 [GPIO3_A1]", "pin-21 [GPIO3_A2]",
- "", "pin-03 [GPIO3_A4]", "", "pin-05 [GPIO3_A6]", "",
- /* GPIO3_B0 - B7 */
- "pin-24 [GPIO3_B0]", "", "", "", "", "", "", "",
- /* GPIO3_C0 - C7 */
- "", "", "", "", "", "", "", "",
- /* GPIO3_D0 - D7 */
- "", "", "", "", "", "", "", "";
-};
-
-&i2c1 {
- status = "okay";
-
- rk805: pmic@18 {
- compatible = "rockchip,rk805";
- reg = <0x18>;
- interrupt-parent = <&gpio2>;
- interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk805-clkout2";
- gpio-controller;
- #gpio-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc5-supply = <&vcc_io>;
- vcc6-supply = <&vcc_sys>;
-
- regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1450000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1450000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_io: DCDC_REG4 {
- regulator-name = "vcc_io";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_18: LDO_REG1 {
- regulator-name = "vcc_18";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc18_emmc: LDO_REG2 {
- regulator-name = "vcc18_emmc";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_10: LDO_REG3 {
- regulator-name = "vdd_10";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
- };
- };
-};
-
-&i2s1 {
- status = "okay";
-};
-
-&io_domains {
- pmuio-supply = <&vcc_io>;
- vccio1-supply = <&vcc_io>;
- vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_io>;
- vccio4-supply = <&vcc_io>;
- vccio5-supply = <&vcc_io>;
- vccio6-supply = <&vcc_io>;
- status = "okay";
-};
-
-&pinctrl {
- ephy {
- eth_phy_int_pin: eth-phy-int-pin {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- eth_phy_reset_pin: eth-phy-reset-pin {
- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- leds {
- led_pin: led-pin {
- rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb3 {
- usb30_host_drv: usb30-host-drv {
- rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wifi {
- wifi_en: wifi-en {
- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
- vmmc-supply = <&vcc_sd>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_18>;
- status = "okay";
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-};
-
-&u2phy_host {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usbdrd3 {
- dr_mode = "host";
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
};
&spi0 {
- bootph-pre-ram;
- bootph-some-ram;
-
flash@0 {
bootph-pre-ram;
bootph-some-ram;
&spi0m2_clk {
bootph-pre-ram;
+ bootph-some-ram;
};
&spi0m2_cs0 {
bootph-pre-ram;
+ bootph-some-ram;
};
&spi0m2_rx {
bootph-pre-ram;
+ bootph-some-ram;
};
&spi0m2_tx {
bootph-pre-ram;
+ bootph-some-ram;
};
&usb20_otg {
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 PINE64
- */
-
-/dts-v1/;
-#include "rk3328.dtsi"
-
-/ {
- model = "Pine64 Rock64";
- compatible = "pine64,rock64", "rockchip,rk3328";
-
- aliases {
- ethernet0 = &gmac2io;
- mmc0 = &sdmmc;
- mmc1 = &emmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- gmac_clkin: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "gmac_clkin";
- #clock-cells = <0>;
- };
-
- vcc_sd: sdmmc-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0m1_pin>;
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_io>;
- };
-
- /* Common enable line for all of the rails mentioned in the labels */
- vcc_host_5v: vcc_host1_5v: vcc_otg_5v: vcc-host-5v-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb20_host_drv>;
- regulator-name = "vcc_host_5v";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_sys>;
- };
-
- vcc_sys: vcc-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&ir_int>;
- pinctrl-names = "default";
- };
-
- leds {
- compatible = "gpio-leds";
-
- power_led: led-0 {
- gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "mmc0";
- };
-
- standby_led: led-1 {
- gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- spdif_sound: spdif-sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "SPDIF";
-
- simple-audio-card,cpu {
- sound-dai = <&spdif>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&spdif_dit>;
- };
- };
-
- spdif_dit: spdif-dit {
- compatible = "linux,spdif-dit";
- #sound-dai-cells = <0>;
- };
-};
-
-&analog_sound {
- status = "okay";
-};
-
-&codec {
- mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
- vmmc-supply = <&vcc_io>;
- vqmmc-supply = <&vcc18_emmc>;
- status = "okay";
-};
-
-&gmac2io {
- assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
- assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
- clock_in_out = "input";
- phy-supply = <&vcc_io>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_pins>;
- snps,force_thresh_dma_mode;
- snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x24>;
- rx_delay = <0x18>;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&hdmiphy {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-
- rk805: pmic@18 {
- compatible = "rockchip,rk805";
- reg = <0x18>;
- interrupt-parent = <&gpio2>;
- interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk805-clkout2";
- gpio-controller;
- #gpio-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc5-supply = <&vcc_io>;
- vcc6-supply = <&vcc_sys>;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1450000>;
- regulator-ramp-delay = <12500>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1450000>;
- regulator-ramp-delay = <12500>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_io: DCDC_REG4 {
- regulator-name = "vcc_io";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_18: LDO_REG1 {
- regulator-name = "vcc_18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc18_emmc: LDO_REG2 {
- regulator-name = "vcc18_emmc";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_10: LDO_REG3 {
- regulator-name = "vdd_10";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
- };
- };
-};
-
-&i2s0 {
- status = "okay";
-};
-
-&i2s1 {
- status = "okay";
-};
-
-&io_domains {
- status = "okay";
-
- vccio1-supply = <&vcc_io>;
- vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_io>;
- vccio4-supply = <&vcc_18>;
- vccio5-supply = <&vcc_io>;
- vccio6-supply = <&vcc_io>;
- pmuio-supply = <&vcc_io>;
-};
-
-&pinctrl {
- ir {
- ir_int: ir-int {
- rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- usb20_host_drv: usb20-host-drv {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
- vmmc-supply = <&vcc_sd>;
- status = "okay";
-};
-
-&spdif {
- pinctrl-0 = <&spdifm0_tx>;
- status = "okay";
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
-
- /* maximum speed for Rockchip SPI */
- spi-max-frequency = <50000000>;
- };
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <0>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-
- u2phy_host: host-port {
- status = "okay";
- };
-
- u2phy_otg: otg-port {
- status = "okay";
- };
-};
-
-&usb20_otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbdrd3 {
- dr_mode = "host";
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&vop {
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
};
dmc: dmc {
- bootph-all;
compatible = "rockchip,rk3328-dmc";
reg = <0x0 0xff400000 0x0 0x1000
0x0 0xff780000 0x0 0x3000
0x0 0xff440000 0x0 0x1000
0x0 0xff720000 0x0 0x1000
0x0 0xff798000 0x0 0x1000>;
+ bootph-all;
};
};
&emmc_bus8 {
bootph-pre-ram;
+ bootph-some-ram;
};
&emmc_clk {
bootph-pre-ram;
+ bootph-some-ram;
};
&emmc_cmd {
bootph-pre-ram;
+ bootph-some-ram;
};
&gpio0 {
&pcfg_pull_none_8ma {
bootph-pre-ram;
+ bootph-some-ram;
};
&pcfg_pull_none_12ma {
bootph-pre-ram;
+ bootph-some-ram;
};
&pcfg_pull_up {
&pcfg_pull_up_4ma {
bootph-pre-ram;
+ bootph-some-ram;
};
&pcfg_pull_up_8ma {
bootph-pre-ram;
+ bootph-some-ram;
};
&pcfg_pull_up_12ma {
bootph-pre-ram;
+ bootph-some-ram;
};
&pinctrl {
- bootph-pre-ram;
- bootph-some-ram;
+ bootph-all;
};
&sdmmc {
&sdmmc0_bus4 {
bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0_clk {
bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0_cmd {
bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0_dectn {
bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0m1_pin {
};
&uart2m1_xfer {
- bootph-all;
+ bootph-pre-sram;
+ bootph-pre-ram;
};
&vop {
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-#include <dt-bindings/clock/rk3328-cru.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/power/rk3328-power.h>
-#include <dt-bindings/soc/rockchip,boot-mode.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- compatible = "rockchip,rk3328";
-
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
- gpio3 = &gpio3;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x0>;
- clocks = <&cru ARMCLK>;
- #cooling-cells = <2>;
- cpu-idle-states = <&CPU_SLEEP>;
- dynamic-power-coefficient = <120>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x1>;
- clocks = <&cru ARMCLK>;
- #cooling-cells = <2>;
- cpu-idle-states = <&CPU_SLEEP>;
- dynamic-power-coefficient = <120>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x2>;
- clocks = <&cru ARMCLK>;
- #cooling-cells = <2>;
- cpu-idle-states = <&CPU_SLEEP>;
- dynamic-power-coefficient = <120>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x3>;
- clocks = <&cru ARMCLK>;
- #cooling-cells = <2>;
- cpu-idle-states = <&CPU_SLEEP>;
- dynamic-power-coefficient = <120>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- idle-states {
- entry-method = "psci";
-
- CPU_SLEEP: cpu-sleep {
- compatible = "arm,idle-state";
- local-timer-stop;
- arm,psci-suspend-param = <0x0010000>;
- entry-latency-us = <120>;
- exit-latency-us = <250>;
- min-residency-us = <900>;
- };
- };
-
- l2: l2-cache0 {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
- };
- };
-
- cpu0_opp_table: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-408000000 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <950000>;
- clock-latency-ns = <40000>;
- opp-suspend;
- };
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <950000>;
- clock-latency-ns = <40000>;
- };
- opp-816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1000000>;
- clock-latency-ns = <40000>;
- };
- opp-1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1100000>;
- clock-latency-ns = <40000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1225000>;
- clock-latency-ns = <40000>;
- };
- opp-1296000000 {
- opp-hz = /bits/ 64 <1296000000>;
- opp-microvolt = <1300000>;
- clock-latency-ns = <40000>;
- };
- };
-
- analog_sound: analog-sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,name = "Analog";
- status = "disabled";
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&codec>;
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- display_subsystem: display-subsystem {
- compatible = "rockchip,display-subsystem";
- ports = <&vop_out>;
- };
-
- hdmi_sound: hdmi-sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <128>;
- simple-audio-card,name = "HDMI";
- status = "disabled";
-
- simple-audio-card,cpu {
- sound-dai = <&i2s0>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&hdmi>;
- };
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- xin24m: xin24m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- };
-
- i2s0: i2s@ff000000 {
- compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xff000000 0x0 0x1000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
- clock-names = "i2s_clk", "i2s_hclk";
- dmas = <&dmac 11>, <&dmac 12>;
- dma-names = "tx", "rx";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s1: i2s@ff010000 {
- compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xff010000 0x0 0x1000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
- clock-names = "i2s_clk", "i2s_hclk";
- dmas = <&dmac 14>, <&dmac 15>;
- dma-names = "tx", "rx";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s2: i2s@ff020000 {
- compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xff020000 0x0 0x1000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
- clock-names = "i2s_clk", "i2s_hclk";
- dmas = <&dmac 0>, <&dmac 1>;
- dma-names = "tx", "rx";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- spdif: spdif@ff030000 {
- compatible = "rockchip,rk3328-spdif";
- reg = <0x0 0xff030000 0x0 0x1000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
- clock-names = "mclk", "hclk";
- dmas = <&dmac 10>;
- dma-names = "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spdifm2_tx>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- pdm: pdm@ff040000 {
- compatible = "rockchip,pdm";
- reg = <0x0 0xff040000 0x0 0x1000>;
- clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
- clock-names = "pdm_clk", "pdm_hclk";
- dmas = <&dmac 16>;
- dma-names = "rx";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pdmm0_clk
- &pdmm0_sdi0
- &pdmm0_sdi1
- &pdmm0_sdi2
- &pdmm0_sdi3>;
- pinctrl-1 = <&pdmm0_clk_sleep
- &pdmm0_sdi0_sleep
- &pdmm0_sdi1_sleep
- &pdmm0_sdi2_sleep
- &pdmm0_sdi3_sleep>;
- status = "disabled";
- };
-
- grf: syscon@ff100000 {
- compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
- reg = <0x0 0xff100000 0x0 0x1000>;
-
- io_domains: io-domains {
- compatible = "rockchip,rk3328-io-voltage-domain";
- status = "disabled";
- };
-
- grf_gpio: gpio {
- compatible = "rockchip,rk3328-grf-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- power: power-controller {
- compatible = "rockchip,rk3328-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- power-domain@RK3328_PD_HEVC {
- reg = <RK3328_PD_HEVC>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3328_PD_VIDEO {
- reg = <RK3328_PD_VIDEO>;
- clocks = <&cru ACLK_RKVDEC>,
- <&cru HCLK_RKVDEC>,
- <&cru SCLK_VDEC_CABAC>,
- <&cru SCLK_VDEC_CORE>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3328_PD_VPU {
- reg = <RK3328_PD_VPU>;
- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
- #power-domain-cells = <0>;
- };
- };
-
- reboot-mode {
- compatible = "syscon-reboot-mode";
- offset = <0x5c8>;
- mode-normal = <BOOT_NORMAL>;
- mode-recovery = <BOOT_RECOVERY>;
- mode-bootloader = <BOOT_FASTBOOT>;
- mode-loader = <BOOT_BL_DOWNLOAD>;
- };
- };
-
- uart0: serial@ff110000 {
- compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff110000 0x0 0x100>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 2>, <&dmac 3>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart1: serial@ff120000 {
- compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff120000 0x0 0x100>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 4>, <&dmac 5>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart2: serial@ff130000 {
- compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff130000 0x0 0x100>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 6>, <&dmac 7>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2m1_xfer>;
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- i2c0: i2c@ff150000 {
- compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xff150000 0x0 0x1000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
- clock-names = "i2c", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_xfer>;
- status = "disabled";
- };
-
- i2c1: i2c@ff160000 {
- compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xff160000 0x0 0x1000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
- clock-names = "i2c", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_xfer>;
- status = "disabled";
- };
-
- i2c2: i2c@ff170000 {
- compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xff170000 0x0 0x1000>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
- clock-names = "i2c", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_xfer>;
- status = "disabled";
- };
-
- i2c3: i2c@ff180000 {
- compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xff180000 0x0 0x1000>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
- clock-names = "i2c", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_xfer>;
- status = "disabled";
- };
-
- spi0: spi@ff190000 {
- compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff190000 0x0 0x1000>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac 8>, <&dmac 9>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
- status = "disabled";
- };
-
- wdt: watchdog@ff1a0000 {
- compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
- reg = <0x0 0xff1a0000 0x0 0x100>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_WDT>;
- };
-
- pwm0: pwm@ff1b0000 {
- compatible = "rockchip,rk3328-pwm";
- reg = <0x0 0xff1b0000 0x0 0x10>;
- clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm1: pwm@ff1b0010 {
- compatible = "rockchip,rk3328-pwm";
- reg = <0x0 0xff1b0010 0x0 0x10>;
- clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm1_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm2: pwm@ff1b0020 {
- compatible = "rockchip,rk3328-pwm";
- reg = <0x0 0xff1b0020 0x0 0x10>;
- clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm2_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm3: pwm@ff1b0030 {
- compatible = "rockchip,rk3328-pwm";
- reg = <0x0 0xff1b0030 0x0 0x10>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
- clock-names = "pwm", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&pwmir_pin>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- dmac: dma-controller@ff1f0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff1f0000 0x0 0x4000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
-
- thermal-zones {
- soc_thermal: soc-thermal {
- polling-delay-passive = <20>;
- polling-delay = <1000>;
- sustainable-power = <1000>;
-
- thermal-sensors = <&tsadc 0>;
-
- trips {
- threshold: trip-point0 {
- temperature = <70000>;
- hysteresis = <2000>;
- type = "passive";
- };
- target: trip-point1 {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
- soc_crit: soc-crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <4096>;
- };
- };
- };
-
- };
-
- tsadc: tsadc@ff250000 {
- compatible = "rockchip,rk3328-tsadc";
- reg = <0x0 0xff250000 0x0 0x100>;
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- assigned-clocks = <&cru SCLK_TSADC>;
- assigned-clock-rates = <50000>;
- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
- clock-names = "tsadc", "apb_pclk";
- pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_pin>;
- pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_pin>;
- resets = <&cru SRST_TSADC>;
- reset-names = "tsadc-apb";
- rockchip,grf = <&grf>;
- rockchip,hw-tshut-temp = <100000>;
- #thermal-sensor-cells = <1>;
- status = "disabled";
- };
-
- efuse: efuse@ff260000 {
- compatible = "rockchip,rk3328-efuse";
- reg = <0x0 0xff260000 0x0 0x50>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&cru SCLK_EFUSE>;
- clock-names = "pclk_efuse";
- rockchip,efuse-size = <0x20>;
-
- /* Data cells */
- efuse_id: id@7 {
- reg = <0x07 0x10>;
- };
- cpu_leakage: cpu-leakage@17 {
- reg = <0x17 0x1>;
- };
- logic_leakage: logic-leakage@19 {
- reg = <0x19 0x1>;
- };
- efuse_cpu_version: cpu-version@1a {
- reg = <0x1a 0x1>;
- bits = <3 3>;
- };
- };
-
- saradc: adc@ff280000 {
- compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
- reg = <0x0 0xff280000 0x0 0x100>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- #io-channel-cells = <1>;
- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
- clock-names = "saradc", "apb_pclk";
- resets = <&cru SRST_SARADC_P>;
- reset-names = "saradc-apb";
- status = "disabled";
- };
-
- gpu: gpu@ff300000 {
- compatible = "rockchip,rk3328-mali", "arm,mali-450";
- reg = <0x0 0xff300000 0x0 0x30000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gp",
- "gpmmu",
- "pp",
- "pp0",
- "ppmmu0",
- "pp1",
- "ppmmu1";
- clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
- clock-names = "bus", "core";
- resets = <&cru SRST_GPU_A>;
- };
-
- h265e_mmu: iommu@ff330200 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff330200 0 0x100>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- vepu_mmu: iommu@ff340800 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff340800 0x0 0x40>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- vpu: video-codec@ff350000 {
- compatible = "rockchip,rk3328-vpu";
- reg = <0x0 0xff350000 0x0 0x800>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vdpu";
- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
- clock-names = "aclk", "hclk";
- iommus = <&vpu_mmu>;
- power-domains = <&power RK3328_PD_VPU>;
- };
-
- vpu_mmu: iommu@ff350800 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff350800 0x0 0x40>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- power-domains = <&power RK3328_PD_VPU>;
- };
-
- vdec: video-codec@ff360000 {
- compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
- reg = <0x0 0xff360000 0x0 0x480>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
- <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
- clock-names = "axi", "ahb", "cabac", "core";
- assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
- <&cru SCLK_VDEC_CORE>;
- assigned-clock-rates = <400000000>, <400000000>, <300000000>;
- iommus = <&vdec_mmu>;
- power-domains = <&power RK3328_PD_VIDEO>;
- };
-
- vdec_mmu: iommu@ff360480 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- power-domains = <&power RK3328_PD_VIDEO>;
- };
-
- vop: vop@ff370000 {
- compatible = "rockchip,rk3328-vop";
- reg = <0x0 0xff370000 0x0 0x3efc>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
- clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
- resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
- reset-names = "axi", "ahb", "dclk";
- iommus = <&vop_mmu>;
- status = "disabled";
-
- vop_out: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- vop_out_hdmi: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&hdmi_in_vop>;
- };
- };
- };
-
- vop_mmu: iommu@ff373f00 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff373f00 0x0 0x100>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- hdmi: hdmi@ff3c0000 {
- compatible = "rockchip,rk3328-dw-hdmi";
- reg = <0x0 0xff3c0000 0x0 0x20000>;
- reg-io-width = <4>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMI>,
- <&cru SCLK_HDMI_SFC>,
- <&cru SCLK_RTC32K>;
- clock-names = "iahb",
- "isfr",
- "cec";
- phys = <&hdmiphy>;
- phy-names = "hdmi";
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
- rockchip,grf = <&grf>;
- #sound-dai-cells = <0>;
- status = "disabled";
-
- ports {
- hdmi_in: port {
- hdmi_in_vop: endpoint {
- remote-endpoint = <&vop_out_hdmi>;
- };
- };
- };
- };
-
- codec: codec@ff410000 {
- compatible = "rockchip,rk3328-codec";
- reg = <0x0 0xff410000 0x0 0x1000>;
- clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
- clock-names = "pclk", "mclk";
- rockchip,grf = <&grf>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- hdmiphy: phy@ff430000 {
- compatible = "rockchip,rk3328-hdmi-phy";
- reg = <0x0 0xff430000 0x0 0x10000>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
- clock-names = "sysclk", "refoclk", "refpclk";
- clock-output-names = "hdmi_phy";
- #clock-cells = <0>;
- nvmem-cells = <&efuse_cpu_version>;
- nvmem-cell-names = "cpu-version";
- #phy-cells = <0>;
- status = "disabled";
- };
-
- cru: clock-controller@ff440000 {
- compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
- reg = <0x0 0xff440000 0x0 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- assigned-clocks =
- /*
- * CPLL should run at 1200, but that is to high for
- * the initial dividers of most of its children.
- * We need set cpll child clk div first,
- * and then set the cpll frequency.
- */
- <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
- <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
- <&cru SCLK_UART1>, <&cru SCLK_UART2>,
- <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
- <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
- <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
- <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
- <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
- <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
- <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
- <&cru SCLK_WIFI>, <&cru ARMCLK>,
- <&cru PLL_GPLL>, <&cru PLL_CPLL>,
- <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
- <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
- <&cru HCLK_PERI>, <&cru PCLK_PERI>,
- <&cru SCLK_RTC32K>;
- assigned-clock-parents =
- <&cru HDMIPHY>, <&cru PLL_APLL>,
- <&cru PLL_GPLL>, <&xin24m>,
- <&xin24m>, <&xin24m>;
- assigned-clock-rates =
- <0>, <61440000>,
- <0>, <24000000>,
- <24000000>, <24000000>,
- <15000000>, <15000000>,
- <100000000>, <100000000>,
- <100000000>, <100000000>,
- <50000000>, <100000000>,
- <100000000>, <100000000>,
- <50000000>, <50000000>,
- <50000000>, <50000000>,
- <24000000>, <600000000>,
- <491520000>, <1200000000>,
- <150000000>, <75000000>,
- <75000000>, <150000000>,
- <75000000>, <75000000>,
- <32768>;
- };
-
- usb2phy_grf: syscon@ff450000 {
- compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
- "simple-mfd";
- reg = <0x0 0xff450000 0x0 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy: usb2phy@100 {
- compatible = "rockchip,rk3328-usb2phy";
- reg = <0x100 0x10>;
- clocks = <&xin24m>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy";
- #clock-cells = <0>;
- assigned-clocks = <&cru USB480M>;
- assigned-clock-parents = <&u2phy>;
- status = "disabled";
-
- u2phy_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
-
- u2phy_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "linestate";
- status = "disabled";
- };
- };
- };
-
- sdmmc: mmc@ff500000 {
- compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xff500000 0x0 0x4000>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <150000000>;
- status = "disabled";
- };
-
- sdio: mmc@ff510000 {
- compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xff510000 0x0 0x4000>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <150000000>;
- status = "disabled";
- };
-
- emmc: mmc@ff520000 {
- compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xff520000 0x0 0x4000>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <150000000>;
- status = "disabled";
- };
-
- gmac2io: ethernet@ff540000 {
- compatible = "rockchip,rk3328-gmac";
- reg = <0x0 0xff540000 0x0 0x10000>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
- <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
- <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
- <&cru PCLK_MAC2IO>;
- clock-names = "stmmaceth", "mac_clk_rx",
- "mac_clk_tx", "clk_mac_ref",
- "clk_mac_refout", "aclk_mac",
- "pclk_mac";
- resets = <&cru SRST_GMAC2IO_A>;
- reset-names = "stmmaceth";
- rockchip,grf = <&grf>;
- tx-fifo-depth = <2048>;
- rx-fifo-depth = <4096>;
- snps,txpbl = <0x4>;
- status = "disabled";
- };
-
- gmac2phy: ethernet@ff550000 {
- compatible = "rockchip,rk3328-gmac";
- reg = <0x0 0xff550000 0x0 0x10000>;
- rockchip,grf = <&grf>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
- <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
- <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
- <&cru SCLK_MAC2PHY_OUT>;
- clock-names = "stmmaceth", "mac_clk_rx",
- "mac_clk_tx", "clk_mac_ref",
- "aclk_mac", "pclk_mac",
- "clk_macphy";
- resets = <&cru SRST_GMAC2PHY_A>;
- reset-names = "stmmaceth";
- phy-mode = "rmii";
- phy-handle = <&phy>;
- tx-fifo-depth = <2048>;
- rx-fifo-depth = <4096>;
- snps,txpbl = <0x4>;
- clock_in_out = "output";
- status = "disabled";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy: ethernet-phy@0 {
- compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- clocks = <&cru SCLK_MAC2PHY_OUT>;
- resets = <&cru SRST_MACPHY>;
- pinctrl-names = "default";
- pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
- phy-is-integrated;
- };
- };
- };
-
- usb20_otg: usb@ff580000 {
- compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
- "snps,dwc2";
- reg = <0x0 0xff580000 0x0 0x40000>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_OTG>;
- clock-names = "otg";
- dr_mode = "otg";
- g-np-tx-fifo-size = <16>;
- g-rx-fifo-size = <280>;
- g-tx-fifo-size = <256 128 128 64 32 16>;
- phys = <&u2phy_otg>;
- phy-names = "usb2-phy";
- status = "disabled";
- };
-
- usb_host0_ehci: usb@ff5c0000 {
- compatible = "generic-ehci";
- reg = <0x0 0xff5c0000 0x0 0x10000>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST0>, <&u2phy>;
- phys = <&u2phy_host>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usb_host0_ohci: usb@ff5d0000 {
- compatible = "generic-ohci";
- reg = <0x0 0xff5d0000 0x0 0x10000>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST0>, <&u2phy>;
- phys = <&u2phy_host>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usbdrd3: usb@ff600000 {
- compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
- reg = <0x0 0xff600000 0x0 0x100000>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
- <&cru ACLK_USB3OTG>;
- clock-names = "ref_clk", "suspend_clk",
- "bus_clk";
- dr_mode = "otg";
- phy_type = "utmi_wide";
- snps,dis-del-phy-power-chg-quirk;
- snps,dis_enblslpm_quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis_u2_susphy_quirk;
- snps,dis_u3_susphy_quirk;
- status = "disabled";
- };
-
- gic: interrupt-controller@ff811000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0xff811000 0 0x1000>,
- <0x0 0xff812000 0 0x2000>,
- <0x0 0xff814000 0 0x2000>,
- <0x0 0xff816000 0 0x2000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- crypto: crypto@ff060000 {
- compatible = "rockchip,rk3328-crypto";
- reg = <0x0 0xff060000 0x0 0x4000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
- <&cru SCLK_CRYPTO>;
- clock-names = "hclk_master", "hclk_slave", "sclk";
- resets = <&cru SRST_CRYPTO>;
- reset-names = "crypto-rst";
- };
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3328-pinctrl";
- rockchip,grf = <&grf>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio@ff210000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff210000 0x0 0x100>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO0>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@ff220000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff220000 0x0 0x100>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO1>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@ff230000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff230000 0x0 0x100>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO2>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@ff240000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff240000 0x0 0x100>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO3>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- pcfg_pull_up: pcfg-pull-up {
- bias-pull-up;
- };
-
- pcfg_pull_down: pcfg-pull-down {
- bias-pull-down;
- };
-
- pcfg_pull_none: pcfg-pull-none {
- bias-disable;
- };
-
- pcfg_pull_none_2ma: pcfg-pull-none-2ma {
- bias-disable;
- drive-strength = <2>;
- };
-
- pcfg_pull_up_2ma: pcfg-pull-up-2ma {
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pcfg_pull_up_4ma: pcfg-pull-up-4ma {
- bias-pull-up;
- drive-strength = <4>;
- };
-
- pcfg_pull_none_4ma: pcfg-pull-none-4ma {
- bias-disable;
- drive-strength = <4>;
- };
-
- pcfg_pull_down_4ma: pcfg-pull-down-4ma {
- bias-pull-down;
- drive-strength = <4>;
- };
-
- pcfg_pull_none_8ma: pcfg-pull-none-8ma {
- bias-disable;
- drive-strength = <8>;
- };
-
- pcfg_pull_up_8ma: pcfg-pull-up-8ma {
- bias-pull-up;
- drive-strength = <8>;
- };
-
- pcfg_pull_none_12ma: pcfg-pull-none-12ma {
- bias-disable;
- drive-strength = <12>;
- };
-
- pcfg_pull_up_12ma: pcfg-pull-up-12ma {
- bias-pull-up;
- drive-strength = <12>;
- };
-
- pcfg_output_high: pcfg-output-high {
- output-high;
- };
-
- pcfg_output_low: pcfg-output-low {
- output-low;
- };
-
- pcfg_input_high: pcfg-input-high {
- bias-pull-up;
- input-enable;
- };
-
- pcfg_input: pcfg-input {
- input-enable;
- };
-
- i2c0 {
- i2c0_xfer: i2c0-xfer {
- rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
- <2 RK_PD1 1 &pcfg_pull_none>;
- };
- };
-
- i2c1 {
- i2c1_xfer: i2c1-xfer {
- rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
- <2 RK_PA5 2 &pcfg_pull_none>;
- };
- };
-
- i2c2 {
- i2c2_xfer: i2c2-xfer {
- rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
- <2 RK_PB6 1 &pcfg_pull_none>;
- };
- };
-
- i2c3 {
- i2c3_xfer: i2c3-xfer {
- rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
- <0 RK_PA6 2 &pcfg_pull_none>;
- };
- i2c3_pins: i2c3-pins {
- rockchip,pins =
- <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
- <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- hdmi_i2c {
- hdmii2c_xfer: hdmii2c-xfer {
- rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
- <0 RK_PA6 1 &pcfg_pull_none>;
- };
- };
-
- pdm-0 {
- pdmm0_clk: pdmm0-clk {
- rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
- };
-
- pdmm0_fsync: pdmm0-fsync {
- rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
- };
-
- pdmm0_sdi0: pdmm0-sdi0 {
- rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
- };
-
- pdmm0_sdi1: pdmm0-sdi1 {
- rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
- };
-
- pdmm0_sdi2: pdmm0-sdi2 {
- rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
- };
-
- pdmm0_sdi3: pdmm0-sdi3 {
- rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
- };
-
- pdmm0_clk_sleep: pdmm0-clk-sleep {
- rockchip,pins =
- <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
- };
-
- pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
- rockchip,pins =
- <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
- };
-
- pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
- rockchip,pins =
- <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
- };
-
- pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
- rockchip,pins =
- <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
- };
-
- pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
- rockchip,pins =
- <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
- };
-
- pdmm0_fsync_sleep: pdmm0-fsync-sleep {
- rockchip,pins =
- <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
- };
- };
-
- tsadc {
- otp_pin: otp-pin {
- rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- otp_out: otp-out {
- rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
- };
- };
-
- uart0 {
- uart0_xfer: uart0-xfer {
- rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
- <1 RK_PB0 1 &pcfg_pull_up>;
- };
-
- uart0_cts: uart0-cts {
- rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
- };
-
- uart0_rts: uart0-rts {
- rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
- };
-
- uart0_rts_pin: uart0-rts-pin {
- rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- uart1 {
- uart1_xfer: uart1-xfer {
- rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
- <3 RK_PA6 4 &pcfg_pull_up>;
- };
-
- uart1_cts: uart1-cts {
- rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
- };
-
- uart1_rts: uart1-rts {
- rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
- };
-
- uart1_rts_pin: uart1-rts-pin {
- rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- uart2-0 {
- uart2m0_xfer: uart2m0-xfer {
- rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
- <1 RK_PA1 2 &pcfg_pull_up>;
- };
- };
-
- uart2-1 {
- uart2m1_xfer: uart2m1-xfer {
- rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
- <2 RK_PA1 1 &pcfg_pull_up>;
- };
- };
-
- spi0-0 {
- spi0m0_clk: spi0m0-clk {
- rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
- };
-
- spi0m0_cs0: spi0m0-cs0 {
- rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
- };
-
- spi0m0_tx: spi0m0-tx {
- rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
- };
-
- spi0m0_rx: spi0m0-rx {
- rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
- };
-
- spi0m0_cs1: spi0m0-cs1 {
- rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
- };
- };
-
- spi0-1 {
- spi0m1_clk: spi0m1-clk {
- rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
- };
-
- spi0m1_cs0: spi0m1-cs0 {
- rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
- };
-
- spi0m1_tx: spi0m1-tx {
- rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
- };
-
- spi0m1_rx: spi0m1-rx {
- rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
- };
-
- spi0m1_cs1: spi0m1-cs1 {
- rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
- };
- };
-
- spi0-2 {
- spi0m2_clk: spi0m2-clk {
- rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
- };
-
- spi0m2_cs0: spi0m2-cs0 {
- rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
- };
-
- spi0m2_tx: spi0m2-tx {
- rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
- };
-
- spi0m2_rx: spi0m2-rx {
- rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
- };
- };
-
- i2s1 {
- i2s1_mclk: i2s1-mclk {
- rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
- };
-
- i2s1_sclk: i2s1-sclk {
- rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
- };
-
- i2s1_lrckrx: i2s1-lrckrx {
- rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
- };
-
- i2s1_lrcktx: i2s1-lrcktx {
- rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
- };
-
- i2s1_sdi: i2s1-sdi {
- rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
- };
-
- i2s1_sdo: i2s1-sdo {
- rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
- };
-
- i2s1_sdio1: i2s1-sdio1 {
- rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
- };
-
- i2s1_sdio2: i2s1-sdio2 {
- rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
- };
-
- i2s1_sdio3: i2s1-sdio3 {
- rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
- };
-
- i2s1_sleep: i2s1-sleep {
- rockchip,pins =
- <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
- <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
- <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
- <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
- <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
- <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
- <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
- <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
- <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
- };
- };
-
- i2s2-0 {
- i2s2m0_mclk: i2s2m0-mclk {
- rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
- };
-
- i2s2m0_sclk: i2s2m0-sclk {
- rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
- };
-
- i2s2m0_lrckrx: i2s2m0-lrckrx {
- rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
- };
-
- i2s2m0_lrcktx: i2s2m0-lrcktx {
- rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
- };
-
- i2s2m0_sdi: i2s2m0-sdi {
- rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
- };
-
- i2s2m0_sdo: i2s2m0-sdo {
- rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
- };
-
- i2s2m0_sleep: i2s2m0-sleep {
- rockchip,pins =
- <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
- <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
- <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
- <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
- <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
- <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
- };
- };
-
- i2s2-1 {
- i2s2m1_mclk: i2s2m1-mclk {
- rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
- };
-
- i2s2m1_sclk: i2s2m1-sclk {
- rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
- };
-
- i2s2m1_lrckrx: i2sm1-lrckrx {
- rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
- };
-
- i2s2m1_lrcktx: i2s2m1-lrcktx {
- rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
- };
-
- i2s2m1_sdi: i2s2m1-sdi {
- rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
- };
-
- i2s2m1_sdo: i2s2m1-sdo {
- rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
- };
-
- i2s2m1_sleep: i2s2m1-sleep {
- rockchip,pins =
- <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
- <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
- <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
- <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
- <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
- };
- };
-
- spdif-0 {
- spdifm0_tx: spdifm0-tx {
- rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
- };
- };
-
- spdif-1 {
- spdifm1_tx: spdifm1-tx {
- rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
- };
- };
-
- spdif-2 {
- spdifm2_tx: spdifm2-tx {
- rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
- };
- };
-
- sdmmc0-0 {
- sdmmc0m0_pwren: sdmmc0m0-pwren {
- rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
- };
-
- sdmmc0m0_pin: sdmmc0m0-pin {
- rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
- };
- };
-
- sdmmc0-1 {
- sdmmc0m1_pwren: sdmmc0m1-pwren {
- rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
- };
-
- sdmmc0m1_pin: sdmmc0m1-pin {
- rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
- };
- };
-
- sdmmc0 {
- sdmmc0_clk: sdmmc0-clk {
- rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
- };
-
- sdmmc0_cmd: sdmmc0-cmd {
- rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
- };
-
- sdmmc0_dectn: sdmmc0-dectn {
- rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
- };
-
- sdmmc0_wrprt: sdmmc0-wrprt {
- rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
- };
-
- sdmmc0_bus1: sdmmc0-bus1 {
- rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
- };
-
- sdmmc0_bus4: sdmmc0-bus4 {
- rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
- <1 RK_PA1 1 &pcfg_pull_up_8ma>,
- <1 RK_PA2 1 &pcfg_pull_up_8ma>,
- <1 RK_PA3 1 &pcfg_pull_up_8ma>;
- };
-
- sdmmc0_pins: sdmmc0-pins {
- rockchip,pins =
- <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
- };
- };
-
- sdmmc0ext {
- sdmmc0ext_clk: sdmmc0ext-clk {
- rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
- };
-
- sdmmc0ext_cmd: sdmmc0ext-cmd {
- rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
- };
-
- sdmmc0ext_wrprt: sdmmc0ext-wrprt {
- rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
- };
-
- sdmmc0ext_dectn: sdmmc0ext-dectn {
- rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
- };
-
- sdmmc0ext_bus1: sdmmc0ext-bus1 {
- rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
- };
-
- sdmmc0ext_bus4: sdmmc0ext-bus4 {
- rockchip,pins =
- <3 RK_PA4 3 &pcfg_pull_up_4ma>,
- <3 RK_PA5 3 &pcfg_pull_up_4ma>,
- <3 RK_PA6 3 &pcfg_pull_up_4ma>,
- <3 RK_PA7 3 &pcfg_pull_up_4ma>;
- };
-
- sdmmc0ext_pins: sdmmc0ext-pins {
- rockchip,pins =
- <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
- };
- };
-
- sdmmc1 {
- sdmmc1_clk: sdmmc1-clk {
- rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
- };
-
- sdmmc1_cmd: sdmmc1-cmd {
- rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
- };
-
- sdmmc1_pwren: sdmmc1-pwren {
- rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
- };
-
- sdmmc1_wrprt: sdmmc1-wrprt {
- rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
- };
-
- sdmmc1_dectn: sdmmc1-dectn {
- rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
- };
-
- sdmmc1_bus1: sdmmc1-bus1 {
- rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
- };
-
- sdmmc1_bus4: sdmmc1-bus4 {
- rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
- <1 RK_PB7 1 &pcfg_pull_up_8ma>,
- <1 RK_PC0 1 &pcfg_pull_up_8ma>,
- <1 RK_PC1 1 &pcfg_pull_up_8ma>;
- };
-
- sdmmc1_pins: sdmmc1-pins {
- rockchip,pins =
- <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
- };
- };
-
- emmc {
- emmc_clk: emmc-clk {
- rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
- };
-
- emmc_cmd: emmc-cmd {
- rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
- };
-
- emmc_pwren: emmc-pwren {
- rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
- };
-
- emmc_rstnout: emmc-rstnout {
- rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
- };
-
- emmc_bus1: emmc-bus1 {
- rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
- };
-
- emmc_bus4: emmc-bus4 {
- rockchip,pins =
- <0 RK_PA7 2 &pcfg_pull_up_12ma>,
- <2 RK_PD4 2 &pcfg_pull_up_12ma>,
- <2 RK_PD5 2 &pcfg_pull_up_12ma>,
- <2 RK_PD6 2 &pcfg_pull_up_12ma>;
- };
-
- emmc_bus8: emmc-bus8 {
- rockchip,pins =
- <0 RK_PA7 2 &pcfg_pull_up_12ma>,
- <2 RK_PD4 2 &pcfg_pull_up_12ma>,
- <2 RK_PD5 2 &pcfg_pull_up_12ma>,
- <2 RK_PD6 2 &pcfg_pull_up_12ma>,
- <2 RK_PD7 2 &pcfg_pull_up_12ma>,
- <3 RK_PC0 2 &pcfg_pull_up_12ma>,
- <3 RK_PC1 2 &pcfg_pull_up_12ma>,
- <3 RK_PC2 2 &pcfg_pull_up_12ma>;
- };
- };
-
- pwm0 {
- pwm0_pin: pwm0-pin {
- rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
- };
- };
-
- pwm1 {
- pwm1_pin: pwm1-pin {
- rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
- };
- };
-
- pwm2 {
- pwm2_pin: pwm2-pin {
- rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
- };
- };
-
- pwmir {
- pwmir_pin: pwmir-pin {
- rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
- };
- };
-
- gmac-1 {
- rgmiim1_pins: rgmiim1-pins {
- rockchip,pins =
- /* mac_txclk */
- <1 RK_PB4 2 &pcfg_pull_none_8ma>,
- /* mac_rxclk */
- <1 RK_PB5 2 &pcfg_pull_none_4ma>,
- /* mac_mdio */
- <1 RK_PC3 2 &pcfg_pull_none_4ma>,
- /* mac_txen */
- <1 RK_PD1 2 &pcfg_pull_none_8ma>,
- /* mac_clk */
- <1 RK_PC5 2 &pcfg_pull_none_4ma>,
- /* mac_rxdv */
- <1 RK_PC6 2 &pcfg_pull_none_4ma>,
- /* mac_mdc */
- <1 RK_PC7 2 &pcfg_pull_none_4ma>,
- /* mac_rxd1 */
- <1 RK_PB2 2 &pcfg_pull_none_4ma>,
- /* mac_rxd0 */
- <1 RK_PB3 2 &pcfg_pull_none_4ma>,
- /* mac_txd1 */
- <1 RK_PB0 2 &pcfg_pull_none_8ma>,
- /* mac_txd0 */
- <1 RK_PB1 2 &pcfg_pull_none_8ma>,
- /* mac_rxd3 */
- <1 RK_PB6 2 &pcfg_pull_none_4ma>,
- /* mac_rxd2 */
- <1 RK_PB7 2 &pcfg_pull_none_4ma>,
- /* mac_txd3 */
- <1 RK_PC0 2 &pcfg_pull_none_8ma>,
- /* mac_txd2 */
- <1 RK_PC1 2 &pcfg_pull_none_8ma>,
-
- /* mac_txclk */
- <0 RK_PB0 1 &pcfg_pull_none_8ma>,
- /* mac_txen */
- <0 RK_PB4 1 &pcfg_pull_none_8ma>,
- /* mac_clk */
- <0 RK_PD0 1 &pcfg_pull_none_4ma>,
- /* mac_txd1 */
- <0 RK_PC0 1 &pcfg_pull_none_8ma>,
- /* mac_txd0 */
- <0 RK_PC1 1 &pcfg_pull_none_8ma>,
- /* mac_txd3 */
- <0 RK_PC7 1 &pcfg_pull_none_8ma>,
- /* mac_txd2 */
- <0 RK_PC6 1 &pcfg_pull_none_8ma>;
- };
-
- rmiim1_pins: rmiim1-pins {
- rockchip,pins =
- /* mac_mdio */
- <1 RK_PC3 2 &pcfg_pull_none_2ma>,
- /* mac_txen */
- <1 RK_PD1 2 &pcfg_pull_none_12ma>,
- /* mac_clk */
- <1 RK_PC5 2 &pcfg_pull_none_2ma>,
- /* mac_rxer */
- <1 RK_PD0 2 &pcfg_pull_none_2ma>,
- /* mac_rxdv */
- <1 RK_PC6 2 &pcfg_pull_none_2ma>,
- /* mac_mdc */
- <1 RK_PC7 2 &pcfg_pull_none_2ma>,
- /* mac_rxd1 */
- <1 RK_PB2 2 &pcfg_pull_none_2ma>,
- /* mac_rxd0 */
- <1 RK_PB3 2 &pcfg_pull_none_2ma>,
- /* mac_txd1 */
- <1 RK_PB0 2 &pcfg_pull_none_12ma>,
- /* mac_txd0 */
- <1 RK_PB1 2 &pcfg_pull_none_12ma>,
-
- /* mac_mdio */
- <0 RK_PB3 1 &pcfg_pull_none>,
- /* mac_txen */
- <0 RK_PB4 1 &pcfg_pull_none>,
- /* mac_clk */
- <0 RK_PD0 1 &pcfg_pull_none>,
- /* mac_mdc */
- <0 RK_PC3 1 &pcfg_pull_none>,
- /* mac_txd1 */
- <0 RK_PC0 1 &pcfg_pull_none>,
- /* mac_txd0 */
- <0 RK_PC1 1 &pcfg_pull_none>;
- };
- };
-
- gmac2phy {
- fephyled_speed10: fephyled-speed10 {
- rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
- };
-
- fephyled_duplex: fephyled-duplex {
- rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
- };
-
- fephyled_rxm1: fephyled-rxm1 {
- rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
- };
-
- fephyled_txm1: fephyled-txm1 {
- rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
- };
-
- fephyled_linkm1: fephyled-linkm1 {
- rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
- };
- };
-
- tsadc_pin {
- tsadc_int: tsadc-int {
- rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
- };
- tsadc_pin: tsadc-pin {
- rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- hdmi_pin {
- hdmi_cec: hdmi-cec {
- rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
- };
-
- hdmi_hpd: hdmi-hpd {
- rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
- };
- };
-
- cif-0 {
- dvp_d2d9_m0:dvp-d2d9-m0 {
- rockchip,pins =
- /* cif_d0 */
- <3 RK_PA4 2 &pcfg_pull_none>,
- /* cif_d1 */
- <3 RK_PA5 2 &pcfg_pull_none>,
- /* cif_d2 */
- <3 RK_PA6 2 &pcfg_pull_none>,
- /* cif_d3 */
- <3 RK_PA7 2 &pcfg_pull_none>,
- /* cif_d4 */
- <3 RK_PB0 2 &pcfg_pull_none>,
- /* cif_d5m0 */
- <3 RK_PB1 2 &pcfg_pull_none>,
- /* cif_d6m0 */
- <3 RK_PB2 2 &pcfg_pull_none>,
- /* cif_d7m0 */
- <3 RK_PB3 2 &pcfg_pull_none>,
- /* cif_href */
- <3 RK_PA1 2 &pcfg_pull_none>,
- /* cif_vsync */
- <3 RK_PA0 2 &pcfg_pull_none>,
- /* cif_clkoutm0 */
- <3 RK_PA3 2 &pcfg_pull_none>,
- /* cif_clkin */
- <3 RK_PA2 2 &pcfg_pull_none>;
- };
- };
-
- cif-1 {
- dvp_d2d9_m1:dvp-d2d9-m1 {
- rockchip,pins =
- /* cif_d0 */
- <3 RK_PA4 2 &pcfg_pull_none>,
- /* cif_d1 */
- <3 RK_PA5 2 &pcfg_pull_none>,
- /* cif_d2 */
- <3 RK_PA6 2 &pcfg_pull_none>,
- /* cif_d3 */
- <3 RK_PA7 2 &pcfg_pull_none>,
- /* cif_d4 */
- <3 RK_PB0 2 &pcfg_pull_none>,
- /* cif_d5m1 */
- <2 RK_PC0 4 &pcfg_pull_none>,
- /* cif_d6m1 */
- <2 RK_PC1 4 &pcfg_pull_none>,
- /* cif_d7m1 */
- <2 RK_PC2 4 &pcfg_pull_none>,
- /* cif_href */
- <3 RK_PA1 2 &pcfg_pull_none>,
- /* cif_vsync */
- <3 RK_PA0 2 &pcfg_pull_none>,
- /* cif_clkoutm1 */
- <2 RK_PB7 4 &pcfg_pull_none>,
- /* cif_clkin */
- <3 RK_PA2 2 &pcfg_pull_none>;
- };
- };
- };
-};
/ {
chosen {
stdout-path = "serial2:1500000n8";
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd.
- */
-
-/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/usb/pd.h>
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- model = "OPEN AI LAB EAIDK-610";
- compatible = "openailab,eaidk-610", "rockchip,rk3399";
-
- aliases {
- mmc0 = &sdio0;
- mmc1 = &sdmmc;
- mmc2 = &sdhci;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm0 0 25000 0>;
- brightness-levels = <
- 0 1 2 3 4 5 6 7
- 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23
- 24 25 26 27 28 29 30 31
- 32 33 34 35 36 37 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255>;
- default-brightness-level = <200>;
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- dc_12v: dc-12v {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&pwrbtn>;
-
- key-power {
- debounce-interval = <100>;
- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "GPIO Key Power";
- linux,code = <KEY_POWER>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&work_led_pin>, <&user_led_pin>,
- <&heartbeat_led_pin>, <&wlan_active_led_pin>,
- <&bt_active_led_pin>;
-
- work_led: led-0 {
- label = "blue:work";
- default-state = "on";
- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
- };
-
- user_led: led-1 {
- label = "read:user";
- default-state = "off";
- gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
- };
-
- heartbeat_led: led-2 {
- label = "green:heartbeat";
- linux,default-trigger = "heartbeat";
- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
- };
-
- wlan_active_led: led-3 {
- label = "yellow:wlan";
- gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tx";
- default-state = "off";
- };
-
- bt_active_led: led-4 {
- label = "blue:bt";
- gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "hci0-power";
- default-state = "off";
- };
- };
-
- rt5651-sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "realtek,rt5651-codec";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Headphone", "Headphone Jack";
- simple-audio-card,routing =
- "Mic Jack", "MICBIAS1",
- "IN1P", "Mic Jack",
- "Headphone Jack", "HPOL",
- "Headphone Jack", "HPOR";
- simple-audio-card,cpu {
- sound-dai = <&i2s1>;
- };
- simple-audio-card,codec {
- sound-dai = <&rt5651>;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
-
- /*
- * On the module itself this is one of these (depending
- * on the actual card populated):
- * - SDIO_RESET_L_WL_REG_ON
- * - PDN (power down when low)
- */
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-
- /* switched by pmic_sleep */
- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_1v8>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- /* For USB3.0 Port1/2 */
- vcc5v0_host1: vcc5v0-host1-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host1_en>;
- regulator-name = "vcc5v0_host1";
- regulator-always-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- /* For USB2.0 Port1/2 */
- vcc5v0_host3: vcc5v0-host3-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host3_en>;
- regulator-name = "vcc5v0_host3";
- regulator-always-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_typec: vcc5v0-typec-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_typec_en>;
- regulator-name = "vcc5v0_typec";
- regulator-always-on;
- vin-supply = <&vcc3v3_sys>;
- };
-
- vdd_log: vdd-log {
- compatible = "regulator-fixed";
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc_lan>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c3>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio1>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
-
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- vcc10-supply = <&vcc3v3_sys>;
- vcc11-supply = <&vcc3v3_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_3v0>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v8_dvp: LDO_REG1 {
- regulator-name = "vcc1v8_dvp";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc2v8_dvp: LDO_REG2 {
- regulator-name = "vcc2v8_dvp";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_pmu: LDO_REG3 {
- regulator-name = "vcc1v8_pmu";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sdio: LDO_REG4 {
- regulator-name = "vcc_sdio";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-name = "vcca3v0_codec";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcca1v8_codec: LDO_REG7 {
- regulator-name = "vcca1v8_codec";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_s3: vcc_lan: SWITCH_REG1 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_b";
- pinctrl-names = "default";
- pinctrl-0 = <&vsel1_pin>;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_gpu";
- pinctrl-names = "default";
- pinctrl-0 = <&vsel2_pin>;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c1 {
- i2c-scl-rising-time-ns = <300>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-
- rt5651: audio-codec@1a {
- compatible = "rockchip,rt5651";
- reg = <0x1a>;
- clocks = <&cru SCLK_I2S_8CH_OUT>;
- clock-names = "mclk";
- hp-det-gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
- spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
- #sound-dai-cells = <0>;
- };
-
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c4 {
- i2c-scl-rising-time-ns = <600>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- fusb0: typec-portc@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&fusb0_int>;
- vbus-supply = <&vcc5v0_typec>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usbc0_role_sw: endpoint@0 {
- remote-endpoint = <&dwc3_0_role_switch>;
- };
- };
- };
-
- connector {
- compatible = "usb-c-connector";
- data-role = "dual";
- label = "USB-C";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- usbc_hs: endpoint {
- remote-endpoint = <&u2phy0_typec_hs>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- usbc_ss: endpoint {
- remote-endpoint = <&tcphy0_typec_ss>;
- };
- };
- };
- };
- };
-};
-
-&i2s1 {
- rockchip,playback-channels = <2>;
- rockchip,capture-channels = <2>;
- status = "okay";
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- status = "okay";
-
- audio-supply = <&vcca1v8_codec>;
- bt656-supply = <&vcc_3v0>;
- gpio1830-supply = <&vcc_3v0>;
- sdmmc-supply = <&vcc_sdio>;
-};
-
-&pmu_io_domains {
- status = "okay";
-
- pmu1830-supply = <&vcc_3v0>;
-};
-
-&pinctrl {
- buttons {
- pwrbtn: pwrbtn {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- bt {
- bt_enable_h: bt-enable-h {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- fusb302x {
- fusb0_int: fusb0-int {
- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- lcd-panel {
- lcd_panel_reset: lcd-panel-reset {
- rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- leds {
- work_led_pin: work-led-pin {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- user_led_pin: user-led-pin {
- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- heartbeat_led_pin: heartbeat-led-pin {
- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wlan_active_led_pin: wlan-led-pin {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_active_led_pin: bt-led-pin {
- rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
-
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- vsel1_pin: vsel1-pin {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- vsel2_pin: vsel2-pin {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- rt5651 {
- rt5651_hpcon: rt5640-hpcon {
- rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb-typec {
- vcc5v0_typec_en: vcc5v0_typec_en {
- rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- vcc5v0_host3_en: vcc5v0-host3-en {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc5v0_host1_en: vcc5v0-host1-en {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wifi {
- wifi_host_wake_l: wifi-host-wake-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
-};
-
-&sdio0 {
- /* WiFi & BT combo module AMPAK AP6255 */
- #address-cells = <1>;
- #size-cells = <0>;
- bus-width = <4>;
- clock-frequency = <50000000>;
- cap-sdio-irq;
- cap-sd-highspeed;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
- interrupt-names = "host-wake";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_l>;
- };
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy0_usb3 {
- orientation-switch;
- port {
- tcphy0_typec_ss: endpoint {
- remote-endpoint = <&usbc_ss>;
- };
- };
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vcc5v0_host3>;
- status = "okay";
- };
-
- port {
- u2phy0_typec_hs: endpoint {
- remote-endpoint = <&usbc_hs>;
- };
- };
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_host3>;
- status = "okay";
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4345c5";
- clocks = <&rk808 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- max-speed = <1500000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
- vbat-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- usb-role-switch;
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- dwc3_0_role_switch: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&usbc0_role_sw>;
- };
- };
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
/ {
chosen {
stdout-path = "serial2:1500000n8";
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
};
-&i2c0 {
- bootph-all;
-};
-
-&rk808 {
- bootph-all;
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
};
&tcphy1 {
&vdd_center {
regulator-init-microvolt = <900000>;
};
-
-&sdmmc {
- bootph-all;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-#include <dt-bindings/pwm/pwm.h>
-#include "rk3399.dtsi"
-
-/ {
- model = "Rockchip RK3399 Evaluation Board";
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
-
- aliases {
- mmc0 = &sdhci;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- brightness-levels = <
- 0 1 2 3 4 5 6 7
- 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23
- 24 25 26 27 28 29 30 31
- 32 33 34 35 36 37 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255>;
- default-brightness-level = <200>;
- pwms = <&pwm0 0 25000 0>;
- };
-
- edp_panel: edp-panel {
- compatible ="lg,lp079qx1-sp0v";
- backlight = <&backlight>;
- enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
- power-supply = <&vcc3v3_s0>;
-
- port {
- panel_in_edp: endpoint {
- remote-endpoint = <&edp_out_panel>;
- };
- };
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- vdd_center: vdd-center {
- compatible = "pwm-regulator";
- pwms = <&pwm3 0 25000 0>;
- regulator-name = "vdd_center";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-always-on;
- regulator-boot-on;
- status = "okay";
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- regulator-name = "vcc5v0_host";
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc_phy: vcc-phy-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_phy";
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc_phy: vcc-phy-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_phy";
- regulator-always-on;
- regulator-boot-on;
- };
-
-};
-
-&edp {
- status = "okay";
- force-hpd;
-
- ports {
- edp_out: port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- edp_out_panel: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&panel_in_edp>;
- };
- };
- };
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc_phy>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio1>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
- #clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
-
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- vcc10-supply = <&vcc3v3_sys>;
- vcc11-supply = <&vcc3v3_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc1v8_pmu>;
-
- regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v8_dvp: LDO_REG1 {
- regulator-name = "vcc1v8_dvp";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v0_tp: LDO_REG2 {
- regulator-name = "vcc3v0_tp";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_pmu: LDO_REG3 {
- regulator-name = "vcc1v8_pmu";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sd: LDO_REG4 {
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-name = "vcca3v0_codec";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcca1v8_codec: LDO_REG7 {
- regulator-name = "vcca1v8_codec";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_s3: SWITCH_REG1 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&pwm3 {
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- non-removable;
- status = "okay";
-};
-
-&pcie_phy {
- status = "disabled";
-};
-
-&pcie0 {
- ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn_cpm>;
- status = "disabled";
-};
-
-&u2phy0 {
- status = "okay";
-};
-
-&u2phy0_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&u2phy1 {
- status = "okay";
-};
-
-&u2phy1_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&pinctrl {
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins =
- <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins =
- <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
- };
+&pcfg_pull_none_18ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pcfg_pull_up_8ma {
+ bootph-pre-ram;
+ bootph-some-ram;
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2018 Collabora Ltd.
- * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
- *
- * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw
- */
-
-/dts-v1/;
-#include "rk3399-rock960.dtsi"
-
-/ {
- model = "96boards RK3399 Ficus";
- compatible = "vamrs,ficus", "rockchip,rk3399";
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>,
- <&user_led3_pin>, <&user_led4_pin>,
- <&wlan_led_pin>, <&bt_led_pin>;
-
- user_led1: led-1 {
- label = "red:user1";
- gpios = <&gpio4 25 0>;
- linux,default-trigger = "heartbeat";
- };
-
- user_led2: led-2 {
- label = "red:user2";
- gpios = <&gpio4 26 0>;
- linux,default-trigger = "mmc0";
- };
-
- user_led3: led-3 {
- label = "red:user3";
- gpios = <&gpio4 30 0>;
- linux,default-trigger = "mmc1";
- };
-
- user_led4: led-4 {
- label = "red:user4";
- gpios = <&gpio1 0 0>;
- panic-indicator;
- linux,default-trigger = "none";
- };
-
- wlan_active_led: led-5 {
- label = "red:wlan";
- gpios = <&gpio1 1 0>;
- linux,default-trigger = "phy0tx";
- default-state = "off";
- };
-
- bt_active_led: led-6 {
- label = "red:bt";
- gpios = <&gpio1 4 0>;
- linux,default-trigger = "hci0-power";
- default-state = "off";
- };
- };
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc3v3_sys>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
-&pcie0 {
- ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
-};
-
-&pinctrl {
- gmac {
- rgmii_sleep_pins: rgmii-sleep-pins {
- rockchip,pins =
- <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
- };
- };
-
- pcie {
- pcie_drv: pcie-drv {
- rockchip,pins =
- <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb2 {
- host_vbus_drv: host-vbus-drv {
- rockchip,pins =
- <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- leds {
- user_led1_pin: user-led1-pin {
- rockchip,pins =
- <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- user_led2_pin: user-led2-pin {
- rockchip,pins =
- <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- user_led3_pin: user-led3-pin {
- rockchip,pins =
- <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- user_led4_pin: user-led4-pin {
- rockchip,pins =
- <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wlan_led_pin: wlan-led-pin {
- rockchip,pins =
- <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_led_pin: bt-led-pin {
- rockchip,pins =
- <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&spi1 {
- /* On both Low speed and High speed expansion */
- cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>;
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- dr_mode = "host";
-};
-
-&usbdrd_dwc3_1 {
- dr_mode = "host";
-};
-
-&vcc3v3_pcie {
- gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
-};
-
-&vcc5v0_host {
- gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
-};
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
- };
-};
-
&vdd_log {
regulator-init-microvolt = <950000>;
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
- */
-
-/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/usb/pd.h>
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- model = "Firefly-RK3399 Board";
- compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
-
- aliases {
- mmc0 = &sdio0;
- mmc1 = &sdmmc;
- mmc2 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
- pwms = <&pwm0 0 25000 0>;
- brightness-levels = <
- 0 1 2 3 4 5 6 7
- 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23
- 24 25 26 27 28 29 30 31
- 32 33 34 35 36 37 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255>;
- default-brightness-level = <200>;
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- dc_12v: dc-12v {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&pwrbtn>;
-
- power {
- debounce-interval = <100>;
- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "GPIO Key Power";
- linux,code = <KEY_POWER>;
- wakeup-source;
- };
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&ir_int>;
- pinctrl-names = "default";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&work_led_pin>, <&diy_led_pin>;
-
- work_led: led-0 {
- label = "work";
- default-state = "on";
- gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
- };
-
- diy_led: led-1 {
- label = "diy";
- default-state = "off";
- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
- };
- };
-
- rt5640-sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "rockchip,rt5640-codec";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Headphone", "Headphone Jack";
- simple-audio-card,routing =
- "Mic Jack", "MICBIAS1",
- "IN1P", "Mic Jack",
- "Headphone Jack", "HPOL",
- "Headphone Jack", "HPOR";
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&rt5640>;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
-
- /*
- * On the module itself this is one of these (depending
- * on the actual card populated):
- * - SDIO_RESET_L_WL_REG_ON
- * - PDN (power down when low)
- */
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-
- sound-dit {
- compatible = "audio-graph-card";
- label = "SPDIF";
- dais = <&spdif_p0>;
- };
-
- spdif-dit {
- compatible = "linux,spdif-dit";
- #sound-dai-cells = <0>;
-
- port {
- dit_p0_0: endpoint {
- remote-endpoint = <&spdif_p0_0>;
- };
- };
- };
-
- /* switched by pmic_sleep */
- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_1v8>;
- };
-
- vcc3v3_pcie: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pwr_en>;
- regulator-name = "vcc3v3_pcie";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&dc_12v>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_sys>;
- };
-
- /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- vin-supply = <&vcc_sys>;
- };
-
- vcc5v0_typec: vcc5v0-typec-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_typec_en>;
- regulator-name = "vcc5v0_typec";
- regulator-always-on;
- vin-supply = <&vcc_sys>;
- };
-
- vcc_sys: vcc-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <430000>;
- regulator-max-microvolt = <1400000>;
- vin-supply = <&vcc_sys>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc_lan>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c3>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- status = "okay";
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio1>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc6-supply = <&vcc_sys>;
- vcc7-supply = <&vcc_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc_sys>;
- vcc10-supply = <&vcc_sys>;
- vcc11-supply = <&vcc_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc1v8_pmu>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v8_dvp: LDO_REG1 {
- regulator-name = "vcc1v8_dvp";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc2v8_dvp: LDO_REG2 {
- regulator-name = "vcc2v8_dvp";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_pmu: LDO_REG3 {
- regulator-name = "vcc1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sdio: LDO_REG4 {
- regulator-name = "vcc_sdio";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-name = "vcca3v0_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcca1v8_codec: LDO_REG7 {
- regulator-name = "vcca1v8_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_s3: vcc_lan: SWITCH_REG1 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <0>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c1 {
- i2c-scl-rising-time-ns = <300>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-
- rt5640: rt5640@1c {
- compatible = "realtek,rt5640";
- reg = <0x1c>;
- clocks = <&cru SCLK_I2S_8CH_OUT>;
- clock-names = "mclk";
- realtek,in1-differential;
- #sound-dai-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&rt5640_hpcon>;
- };
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c4 {
- i2c-scl-rising-time-ns = <600>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- fusb0: typec-portc@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&fusb0_int>;
- vbus-supply = <&vcc5v0_typec>;
- status = "okay";
-
- connector {
- compatible = "usb-c-connector";
- data-role = "host";
- label = "USB-C";
- op-sink-microwatt = <1000000>;
- power-role = "dual";
- sink-pdos =
- <PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
- source-pdos =
- <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
- try-power-role = "sink";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- usbc_hs: endpoint {
- remote-endpoint =
- <&u2phy0_typec_hs>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- usbc_ss: endpoint {
- remote-endpoint =
- <&tcphy0_typec_ss>;
- };
- };
- };
- };
- };
-
- accelerometer@68 {
- compatible = "invensense,mpu6500";
- reg = <0x68>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
- };
-};
-
-&i2s0 {
- rockchip,playback-channels = <8>;
- rockchip,capture-channels = <8>;
- status = "okay";
-};
-
-&i2s1 {
- rockchip,playback-channels = <2>;
- rockchip,capture-channels = <2>;
- status = "okay";
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- status = "okay";
-
- bt656-supply = <&vcc1v8_dvp>;
- audio-supply = <&vcca1v8_codec>;
- sdmmc-supply = <&vcc_sdio>;
- gpio1830-supply = <&vcc_3v0>;
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn_cpm>;
- status = "okay";
-};
-
-&pmu_io_domains {
- pmu1830-supply = <&vcc_3v0>;
- status = "okay";
-};
-
-&pinctrl {
- buttons {
- pwrbtn: pwrbtn {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- fusb302x {
- fusb0_int: fusb0-int {
- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- ir {
- ir_int: ir-int {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- lcd-panel {
- lcd_panel_reset: lcd-panel-reset {
- rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- leds {
- work_led_pin: work-led-pin {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- diy_led_pin: diy-led-pin {
- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- pcie_pwr_en: pcie-pwr-en {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_3g_drv: pcie-3g-drv {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- vsel1_pin: vsel1-pin {
- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- vsel2_pin: vsel2-pin {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- rt5640 {
- rt5640_hpcon: rt5640-hpcon {
- rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb-typec {
- vcc5v0_typec_en: vcc5v0_typec_en {
- rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wifi {
- wifi_host_wake_l: wifi-host-wake-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
-};
-
-&sdio0 {
- /* WiFi & BT combo module Ampak AP6356S */
- bus-width = <4>;
- cap-sdio-irq;
- cap-sd-highspeed;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
-
- /* Power supply */
- vqmmc-supply = &vcc1v8_s3; /* IO line */
- vmmc-supply = &vcc_sdio; /* card's power */
-
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
- interrupt-names = "host-wake";
- brcm,drive-strength = <5>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_l>;
- };
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- non-removable;
- status = "okay";
-};
-
-&spdif {
- pinctrl-0 = <&spdif_bus_1>;
- status = "okay";
-
- spdif_p0: port {
- spdif_p0_0: endpoint {
- remote-endpoint = <&dit_p0_0>;
- };
- };
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy0_usb3 {
- port {
- tcphy0_typec_ss: endpoint {
- remote-endpoint = <&usbc_ss>;
- };
- };
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-
- port {
- u2phy0_typec_hs: endpoint {
- remote-endpoint = <&usbc_hs>;
- };
- };
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "otg";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Google Gru-Bob Rev 4+ board device tree source
- *
- * Copyright 2018 Google, Inc
- */
-
-/dts-v1/;
-#include "rk3399-gru-chromebook.dtsi"
-
-/ {
- model = "Google Bob";
- compatible = "google,bob-rev13", "google,bob-rev12",
- "google,bob-rev11", "google,bob-rev10",
- "google,bob-rev9", "google,bob-rev8",
- "google,bob-rev7", "google,bob-rev6",
- "google,bob-rev5", "google,bob-rev4",
- "google,bob", "google,gru", "rockchip,rk3399";
-
- edp_panel: edp-panel {
- compatible = "boe,nv101wxmn51";
- backlight = <&backlight>;
- power-supply = <&pp3300_disp>;
-
- port {
- panel_in_edp: endpoint {
- remote-endpoint = <&edp_out_panel>;
- };
- };
- };
-};
-
-&ap_i2c_ts {
- touchscreen: touchscreen@10 {
- compatible = "elan,ekth3500";
- reg = <0x10>;
- interrupt-parent = <&gpio3>;
- interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&touch_int_l &touch_reset_l>;
- reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
- };
-};
-
-&ap_i2c_tp {
- trackpad: trackpad@15 {
- compatible = "elan,ekth3000";
- reg = <0x15>;
- interrupt-parent = <&gpio1>;
- interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&trackpad_int_l>;
- wakeup-source;
- };
-};
-
-&backlight {
- pwms = <&cros_ec_pwm 0>;
-};
-
-&cpu_alert0 {
- temperature = <65000>;
-};
-
-&cpu_alert1 {
- temperature = <70000>;
-};
-
-&spi0 {
- status = "okay";
-
- cr50@0 {
- compatible = "google,cr50";
- reg = <0>;
- interrupt-parent = <&gpio0>;
- interrupts = <5 IRQ_TYPE_EDGE_RISING>;
- pinctrl-names = "default";
- pinctrl-0 = <&h1_int_od_l>;
- spi-max-frequency = <800000>;
- };
-};
-
-&pinctrl {
- tpm {
- h1_int_od_l: h1-int-od-l {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Google Gru-Chromebook shared properties
- *
- * Copyright 2018 Google, Inc
- */
-
-#include "rk3399-gru.dtsi"
-
-/ {
- pp900_ap: pp900-ap {
- compatible = "regulator-fixed";
- regulator-name = "pp900_ap";
-
- /* EC turns on w/ pp900_ap_en; always on for AP */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- vin-supply = <&ppvar_sys>;
- };
-
- /* EC turns on w/ pp900_usb_en */
- pp900_usb: pp900-ap {
- };
-
- /* EC turns on w/ pp900_pcie_en */
- pp900_pcie: pp900-ap {
- };
-
- pp3000: pp3000 {
- compatible = "regulator-fixed";
- regulator-name = "pp3000";
- pinctrl-names = "default";
- pinctrl-0 = <&pp3000_en>;
-
- enable-active-high;
- gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
-
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
-
- vin-supply = <&ppvar_sys>;
- };
-
- ppvar_centerlogic_pwm: ppvar-centerlogic-pwm {
- compatible = "pwm-regulator";
- regulator-name = "ppvar_centerlogic_pwm";
-
- pwms = <&pwm3 0 3337 0>;
- pwm-supply = <&ppvar_sys>;
- pwm-dutycycle-range = <100 0>;
- pwm-dutycycle-unit = <100>;
-
- /* EC turns on w/ ppvar_centerlogic_en; always on for AP */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <799434>;
- regulator-max-microvolt = <1049925>;
- };
-
- ppvar_centerlogic: ppvar-centerlogic {
- compatible = "vctrl-regulator";
- regulator-name = "ppvar_centerlogic";
-
- regulator-min-microvolt = <799434>;
- regulator-max-microvolt = <1049925>;
-
- ctrl-supply = <&ppvar_centerlogic_pwm>;
- ctrl-voltage-range = <799434 1049925>;
-
- regulator-settling-time-up-us = <378>;
- min-slew-down-rate = <225>;
- ovp-threshold-percent = <16>;
- };
-
- /* Schematics call this PPVAR even though it's fixed */
- ppvar_logic: ppvar-logic {
- compatible = "regulator-fixed";
- regulator-name = "ppvar_logic";
-
- /* EC turns on w/ ppvar_logic_en; always on for AP */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- vin-supply = <&ppvar_sys>;
- };
-
- pp1800_audio: pp1800-audio {
- compatible = "regulator-fixed";
- regulator-name = "pp1800_audio";
- pinctrl-names = "default";
- pinctrl-0 = <&pp1800_audio_en>;
-
- enable-active-high;
- gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
-
- regulator-always-on;
- regulator-boot-on;
-
- vin-supply = <&pp1800>;
- };
-
- /* gpio is shared with pp3300_wifi_bt */
- pp1800_pcie: pp1800-pcie {
- compatible = "regulator-fixed";
- regulator-name = "pp1800_pcie";
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_module_pd_l>;
-
- enable-active-high;
- gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
-
- /*
- * Need to wait 1ms + ramp-up time before we can power on WiFi.
- * This has been approximated as 8ms total.
- */
- regulator-enable-ramp-delay = <8000>;
-
- vin-supply = <&pp1800>;
- };
-
- /* Always on; plain and simple */
- pp3000_ap: pp3000_emmc: pp3000 {
- };
-
- pp1500_ap_io: pp1500-ap-io {
- compatible = "regulator-fixed";
- regulator-name = "pp1500_ap_io";
- pinctrl-names = "default";
- pinctrl-0 = <&pp1500_en>;
-
- enable-active-high;
- gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
-
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
-
- vin-supply = <&pp1800>;
- };
-
- pp3300_disp: pp3300-disp {
- compatible = "regulator-fixed";
- regulator-name = "pp3300_disp";
- pinctrl-names = "default";
- pinctrl-0 = <&pp3300_disp_en>;
-
- enable-active-high;
- gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
-
- startup-delay-us = <2000>;
- vin-supply = <&pp3300>;
- };
-
- /* EC turns on w/ pp3300_usb_en_l */
- pp3300_usb: pp3300 {
- };
-
- /* gpio is shared with pp1800_pcie and pinctrl is set there */
- pp3300_wifi_bt: pp3300-wifi-bt {
- compatible = "regulator-fixed";
- regulator-name = "pp3300_wifi_bt";
-
- enable-active-high;
- gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
-
- vin-supply = <&pp3300>;
- };
-
- /*
- * This is a bit of a hack. The WiFi module should be reset at least
- * 1ms after its regulators have ramped up (max rampup time is ~7ms).
- * With some stretching of the imagination, we can call the 1.8V
- * regulator a supply.
- */
- wlan_pd_n: wlan-pd-n {
- compatible = "regulator-fixed";
- regulator-name = "wlan_pd_n";
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_module_reset_l>;
-
- enable-active-high;
- gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
-
- vin-supply = <&pp1800_pcie>;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
- power-supply = <&pp3300_disp>;
- pinctrl-names = "default";
- pinctrl-0 = <&bl_en>;
- pwm-delay-us = <10000>;
- };
-
- gpio_keys: gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l>;
-
- wake_on_bt: wake-on-bt {
- label = "Wake-on-Bluetooth";
- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WAKEUP>;
- wakeup-source;
- };
- };
-};
-
-&ppvar_bigcpu {
- min-slew-down-rate = <225>;
- ovp-threshold-percent = <16>;
-};
-
-&ppvar_litcpu {
- min-slew-down-rate = <225>;
- ovp-threshold-percent = <16>;
-};
-
-&ppvar_gpu {
- min-slew-down-rate = <225>;
- ovp-threshold-percent = <16>;
-};
-
-&cdn_dp {
- extcon = <&usbc_extcon0>, <&usbc_extcon1>;
-};
-
-&edp {
- status = "okay";
-
- ports {
- edp_out: port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- edp_out_panel: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&panel_in_edp>;
- };
- };
- };
-};
-
-ap_i2c_mic: &i2c1 {
- status = "okay";
-
- clock-frequency = <400000>;
-
- /* These are relatively safe rise/fall times */
- i2c-scl-falling-time-ns = <50>;
- i2c-scl-rising-time-ns = <300>;
-
- headsetcodec: rt5514@57 {
- compatible = "realtek,rt5514";
- reg = <0x57>;
- realtek,dmic-init-delay-ms = <20>;
- };
-};
-
-ap_i2c_tp: &i2c5 {
- status = "okay";
-
- clock-frequency = <400000>;
-
- /* These are relatively safe rise/fall times */
- i2c-scl-falling-time-ns = <50>;
- i2c-scl-rising-time-ns = <300>;
-
- /*
- * Note strange pullup enable. Apparently this avoids leakage but
- * still allows us to get nice 4.7K pullups for high speed i2c
- * transfers. Basically we want the pullup on whenever the ap is
- * alive, so the "en" pin just gets set to output high.
- */
- pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>;
-};
-
-&cros_ec {
- cros_ec_pwm: ec-pwm {
- compatible = "google,cros-ec-pwm";
- #pwm-cells = <1>;
- };
-
- usbc_extcon1: extcon1 {
- compatible = "google,extcon-usbc-cros-ec";
- google,usb-port-id = <1>;
- };
-};
-
-&sound {
- rockchip,codec = <&max98357a &headsetcodec
- &codec &wacky_spi_audio &cdn_dp>;
-};
-
-&spi2 {
- wacky_spi_audio: spi2@0 {
- compatible = "realtek,rt5514";
- reg = <0>;
- interrupt-parent = <&gpio1>;
- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&mic_int>;
- /* May run faster once verified. */
- spi-max-frequency = <10000000>;
- wakeup-source;
- };
-};
-
-&pci_rootport {
- mvl_wifi: wifi@0,0 {
- compatible = "pci1b4b,2b42";
- reg = <0x83010000 0x0 0x00000000 0x0 0x00100000
- 0x83010000 0x0 0x00100000 0x0 0x00100000>;
- interrupt-parent = <&gpio0>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_host_wake_l>;
- wakeup-source;
- };
-};
-
-&tcphy1 {
- status = "okay";
- extcon = <&usbc_extcon1>;
-};
-
-&u2phy1 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_1 {
- status = "okay";
- extcon = <&usbc_extcon1>;
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&pinctrl {
- discrete-regulators {
- pp1500_en: pp1500-en {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO
- &pcfg_pull_none>;
- };
-
- pp1800_audio_en: pp1800-audio-en {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO
- &pcfg_pull_down>;
- };
-
- pp3000_en: pp3000-en {
- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO
- &pcfg_pull_none>;
- };
-
- pp3300_disp_en: pp3300-disp-en {
- rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO
- &pcfg_pull_none>;
- };
-
- wlan_module_pd_l: wlan-module-pd-l {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO
- &pcfg_pull_down>;
- };
- };
-};
-
-&wifi {
- wifi_perst_l: wifi-perst-l {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wlan_host_wake_l: wlan-host-wake-l {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Google Gru-Kevin Rev 6+ board device tree source
- *
- * Copyright 2016-2017 Google, Inc
- */
-
-/dts-v1/;
-#include "rk3399-gru-chromebook.dtsi"
-#include <dt-bindings/input/linux-event-codes.h>
-
-/*
- * Kevin-specific things
- *
- * Things in this section should use names from Kevin schematic since no
- * equivalent exists in Gru schematic. If referring to signals that exist
- * in Gru we use the Gru names, though. Confusing enough for you?
- */
-/ {
- model = "Google Kevin";
- compatible = "google,kevin-rev15", "google,kevin-rev14",
- "google,kevin-rev13", "google,kevin-rev12",
- "google,kevin-rev11", "google,kevin-rev10",
- "google,kevin-rev9", "google,kevin-rev8",
- "google,kevin-rev7", "google,kevin-rev6",
- "google,kevin", "google,gru", "rockchip,rk3399";
-
- /* Power tree */
-
- p3_3v_dig: p3-3v-dig {
- compatible = "regulator-fixed";
- regulator-name = "p3.3v_dig";
- pinctrl-names = "default";
- pinctrl-0 = <&cpu3_pen_pwr_en>;
-
- enable-active-high;
- gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
- vin-supply = <&pp3300>;
- };
-
- edp_panel: edp-panel {
- compatible = "sharp,lq123p1jx31";
- backlight = <&backlight>;
- power-supply = <&pp3300_disp>;
-
- panel-timing {
- clock-frequency = <266666667>;
- hactive = <2400>;
- hfront-porch = <48>;
- hback-porch = <84>;
- hsync-len = <32>;
- hsync-active = <0>;
- vactive = <1600>;
- vfront-porch = <3>;
- vback-porch = <120>;
- vsync-len = <10>;
- vsync-active = <0>;
- };
-
- port {
- panel_in_edp: endpoint {
- remote-endpoint = <&edp_out_panel>;
- };
- };
- };
-
- thermistor_ppvar_bigcpu: thermistor-ppvar-bigcpu {
- compatible = "murata,ncp15wb473";
- pullup-uv = <1800000>;
- pullup-ohm = <25500>;
- pulldown-ohm = <0>;
- io-channels = <&saradc 2>;
- #thermal-sensor-cells = <0>;
- };
-
- thermistor_ppvar_litcpu: thermistor-ppvar-litcpu {
- compatible = "murata,ncp15wb473";
- pullup-uv = <1800000>;
- pullup-ohm = <25500>;
- pulldown-ohm = <0>;
- io-channels = <&saradc 3>;
- #thermal-sensor-cells = <0>;
- };
-};
-
-&backlight {
- pwms = <&cros_ec_pwm 1>;
-};
-
-&gpio_keys {
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>;
-
- pen-insert {
- label = "Pen Insert";
- /* Insert = low, eject = high */
- gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
- linux,code = <SW_PEN_INSERTED>;
- linux,input-type = <EV_SW>;
- wakeup-source;
- };
-};
-
-&thermal_zones {
- bigcpu_reg_thermal: bigcpu-reg-thermal {
- polling-delay-passive = <100>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
- thermal-sensors = <&thermistor_ppvar_bigcpu 0>;
- sustainable-power = <4000>;
-
- ppvar_bigcpu_trips: trips {
- ppvar_bigcpu_on: ppvar-bigcpu-on {
- temperature = <40000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
-
- ppvar_bigcpu_alert: ppvar-bigcpu-alert {
- temperature = <50000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
-
- ppvar_bigcpu_crit: ppvar-bigcpu-crit {
- temperature = <90000>; /* millicelsius */
- hysteresis = <0>; /* millicelsius */
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&ppvar_bigcpu_alert>;
- cooling-device =
- <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <4096>;
- };
- map1 {
- trip = <&ppvar_bigcpu_alert>;
- cooling-device =
- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <1024>;
- };
- };
- };
-
- litcpu_reg_thermal: litcpu-reg-thermal {
- polling-delay-passive = <100>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
- thermal-sensors = <&thermistor_ppvar_litcpu 0>;
- sustainable-power = <4000>;
-
- ppvar_litcpu_trips: trips {
- ppvar_litcpu_on: ppvar-litcpu-on {
- temperature = <40000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
-
- ppvar_litcpu_alert: ppvar-litcpu-alert {
- temperature = <50000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
-
- ppvar_litcpu_crit: ppvar-litcpu-crit {
- temperature = <90000>; /* millicelsius */
- hysteresis = <0>; /* millicelsius */
- type = "critical";
- };
- };
- };
-};
-
-ap_i2c_tpm: &i2c0 {
- status = "okay";
-
- clock-frequency = <400000>;
-
- /* These are relatively safe rise/fall times. */
- i2c-scl-falling-time-ns = <50>;
- i2c-scl-rising-time-ns = <300>;
-
- tpm: tpm@20 {
- compatible = "infineon,slb9645tt";
- reg = <0x20>;
- powered-while-suspended;
- };
-};
-
-ap_i2c_dig: &i2c2 {
- status = "okay";
-
- clock-frequency = <400000>;
-
- /* These are relatively safe rise/fall times. */
- i2c-scl-falling-time-ns = <50>;
- i2c-scl-rising-time-ns = <300>;
-
- digitizer: digitizer@9 {
- /* wacom,w9013 */
- compatible = "hid-over-i2c";
- reg = <0x9>;
- pinctrl-names = "default";
- pinctrl-0 = <&cpu1_dig_irq_l &cpu1_dig_pdct_l>;
-
- vdd-supply = <&p3_3v_dig>;
- post-power-on-delay-ms = <100>;
-
- interrupt-parent = <&gpio2>;
- interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
-
- hid-descr-addr = <0x1>;
- };
-};
-
-/* Adjustments to things in the gru baseboard */
-
-&ap_i2c_tp {
- trackpad@4a {
- compatible = "atmel,maxtouch";
- reg = <0x4a>;
- pinctrl-names = "default";
- pinctrl-0 = <&trackpad_int_l>;
- interrupt-parent = <&gpio1>;
- interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
- linux,gpio-keymap = <KEY_RESERVED
- KEY_RESERVED
- KEY_RESERVED
- BTN_LEFT>;
- wakeup-source;
- };
-};
-
-&ap_i2c_ts {
- touchscreen@4b {
- compatible = "atmel,maxtouch";
- reg = <0x4b>;
- pinctrl-names = "default";
- pinctrl-0 = <&touch_int_l>;
- interrupt-parent = <&gpio3>;
- interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&ppvar_bigcpu_pwm {
- regulator-min-microvolt = <798674>;
- regulator-max-microvolt = <1302172>;
-};
-
-&ppvar_bigcpu {
- regulator-min-microvolt = <798674>;
- regulator-max-microvolt = <1302172>;
- ctrl-voltage-range = <798674 1302172>;
-};
-
-&ppvar_litcpu_pwm {
- regulator-min-microvolt = <799065>;
- regulator-max-microvolt = <1303738>;
-};
-
-&ppvar_litcpu {
- regulator-min-microvolt = <799065>;
- regulator-max-microvolt = <1303738>;
- ctrl-voltage-range = <799065 1303738>;
-};
-
-&ppvar_gpu_pwm {
- regulator-min-microvolt = <785782>;
- regulator-max-microvolt = <1217729>;
-};
-
-&ppvar_gpu {
- regulator-min-microvolt = <785782>;
- regulator-max-microvolt = <1217729>;
- ctrl-voltage-range = <785782 1217729>;
-};
-
-&ppvar_centerlogic_pwm {
- regulator-min-microvolt = <800069>;
- regulator-max-microvolt = <1049692>;
-};
-
-&ppvar_centerlogic {
- regulator-min-microvolt = <800069>;
- regulator-max-microvolt = <1049692>;
- ctrl-voltage-range = <800069 1049692>;
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&pp1800_ap_io>;
-};
-
-&mvl_wifi {
- marvell,wakeup-pin = <14>; /* GPIO_14 on Marvell */
-};
-
-&pinctrl {
- digitizer {
- /* Has external pullup */
- cpu1_dig_irq_l: cpu1-dig-irq-l {
- rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- /* Has external pullup */
- cpu1_dig_pdct_l: cpu1-dig-pdct-l {
- rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- discrete-regulators {
- cpu3_pen_pwr_en: cpu3-pen-pwr-en {
- rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pen {
- cpu1_pen_eject: cpu1-pen-eject {
- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
};
+&sdhci {
+ /delete-property/ bootph-pre-ram;
+};
+
+&sdmmc {
+ /delete-property/ bootph-pre-ram;
+};
+
+&sdmmc_bus4 {
+ /delete-property/ bootph-pre-ram;
+};
+
+&sdmmc_cd {
+ /delete-property/ bootph-pre-ram;
+};
+
+&sdmmc_clk {
+ /delete-property/ bootph-pre-ram;
+};
+
+&sdmmc_cmd {
+ /delete-property/ bootph-pre-ram;
+};
+
+&spi1 {
+ spi_flash: flash@0 {
+ bootph-all;
+ };
+};
+
&spi5 {
spi-activate-delay = <100>;
spi-max-frequency = <3000000>;
spi-deactivate-delay = <200>;
};
-
-&spi_flash {
- bootph-all;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Google Gru (and derivatives) board device tree source
- *
- * Copyright 2016-2017 Google, Inc
- */
-
-#include <dt-bindings/input/input.h>
-#include "rk3399.dtsi"
-#include "rk3399-op1-opp.dtsi"
-
-/ {
- aliases {
- mmc0 = &sdmmc;
- mmc1 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- /*
- * Power Tree
- *
- * In general an attempt is made to include all rails called out by
- * the schematic as long as those rails interact in some way with
- * the AP. AKA:
- * - Rails that only connect to the EC (or devices that the EC talks to)
- * are not included.
- * - Rails _are_ included if the rails go to the AP even if the AP
- * doesn't currently care about them / they are always on. The idea
- * here is that it makes it easier to map to the schematic or extend
- * later.
- *
- * If two rails are substantially the same from the AP's point of
- * view, though, we won't create a full fixed regulator. We'll just
- * put the child rail as an alias of the parent rail. Sometimes rails
- * look the same to the AP because one of these is true:
- * - The EC controls the enable and the EC always enables a rail as
- * long as the AP is running.
- * - The rails are actually connected to each other by a jumper and
- * the distinction is just there to add clarity/flexibility to the
- * schematic.
- */
-
- ppvar_sys: ppvar-sys {
- compatible = "regulator-fixed";
- regulator-name = "ppvar_sys";
- regulator-always-on;
- regulator-boot-on;
- };
-
- pp1200_lpddr: pp1200-lpddr {
- compatible = "regulator-fixed";
- regulator-name = "pp1200_lpddr";
-
- /* EC turns on w/ lpddr_pwr_en; always on for AP */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
-
- vin-supply = <&ppvar_sys>;
- };
-
- pp1800: pp1800 {
- compatible = "regulator-fixed";
- regulator-name = "pp1800";
-
- /* Always on when ppvar_sys shows power good */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- vin-supply = <&ppvar_sys>;
- };
-
- pp3300: pp3300 {
- compatible = "regulator-fixed";
- regulator-name = "pp3300";
-
- /* Always on; plain and simple */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- vin-supply = <&ppvar_sys>;
- };
-
- pp5000: pp5000 {
- compatible = "regulator-fixed";
- regulator-name = "pp5000";
-
- /* EC turns on w/ pp5000_en; always on for AP */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- vin-supply = <&ppvar_sys>;
- };
-
- ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
- compatible = "pwm-regulator";
- regulator-name = "ppvar_bigcpu_pwm";
-
- pwms = <&pwm1 0 3337 0>;
- pwm-supply = <&ppvar_sys>;
- pwm-dutycycle-range = <100 0>;
- pwm-dutycycle-unit = <100>;
-
- /* EC turns on w/ ap_core_en; always on for AP */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800107>;
- regulator-max-microvolt = <1302232>;
- };
-
- ppvar_bigcpu: ppvar-bigcpu {
- compatible = "vctrl-regulator";
- regulator-name = "ppvar_bigcpu";
-
- regulator-min-microvolt = <800107>;
- regulator-max-microvolt = <1302232>;
-
- ctrl-supply = <&ppvar_bigcpu_pwm>;
- ctrl-voltage-range = <800107 1302232>;
-
- regulator-settling-time-up-us = <322>;
- };
-
- ppvar_litcpu_pwm: ppvar-litcpu-pwm {
- compatible = "pwm-regulator";
- regulator-name = "ppvar_litcpu_pwm";
-
- pwms = <&pwm2 0 3337 0>;
- pwm-supply = <&ppvar_sys>;
- pwm-dutycycle-range = <100 0>;
- pwm-dutycycle-unit = <100>;
-
- /* EC turns on w/ ap_core_en; always on for AP */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <797743>;
- regulator-max-microvolt = <1307837>;
- };
-
- ppvar_litcpu: ppvar-litcpu {
- compatible = "vctrl-regulator";
- regulator-name = "ppvar_litcpu";
-
- regulator-min-microvolt = <797743>;
- regulator-max-microvolt = <1307837>;
-
- ctrl-supply = <&ppvar_litcpu_pwm>;
- ctrl-voltage-range = <797743 1307837>;
-
- regulator-settling-time-up-us = <384>;
- };
-
- ppvar_gpu_pwm: ppvar-gpu-pwm {
- compatible = "pwm-regulator";
- regulator-name = "ppvar_gpu_pwm";
-
- pwms = <&pwm0 0 3337 0>;
- pwm-supply = <&ppvar_sys>;
- pwm-dutycycle-range = <100 0>;
- pwm-dutycycle-unit = <100>;
-
- /* EC turns on w/ ap_core_en; always on for AP */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <786384>;
- regulator-max-microvolt = <1217747>;
- };
-
- ppvar_gpu: ppvar-gpu {
- compatible = "vctrl-regulator";
- regulator-name = "ppvar_gpu";
-
- regulator-min-microvolt = <786384>;
- regulator-max-microvolt = <1217747>;
-
- ctrl-supply = <&ppvar_gpu_pwm>;
- ctrl-voltage-range = <786384 1217747>;
-
- regulator-settling-time-up-us = <390>;
- };
-
- /* EC turns on w/ pp900_ddrpll_en */
- pp900_ddrpll: pp900-ap {
- };
-
- /* EC turns on w/ pp900_pll_en */
- pp900_pll: pp900-ap {
- };
-
- /* EC turns on w/ pp900_pmu_en */
- pp900_pmu: pp900-ap {
- };
-
- /* EC turns on w/ pp1800_s0_en_l */
- pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
- };
-
- /* EC turns on w/ pp1800_avdd_en_l */
- pp1800_avdd: pp1800 {
- };
-
- /* EC turns on w/ pp1800_lid_en_l */
- pp1800_lid: pp1800_mic: pp1800 {
- };
-
- /* EC turns on w/ lpddr_pwr_en */
- pp1800_lpddr: pp1800 {
- };
-
- /* EC turns on w/ pp1800_pmu_en_l */
- pp1800_pmu: pp1800 {
- };
-
- /* EC turns on w/ pp1800_usb_en_l */
- pp1800_usb: pp1800 {
- };
-
- pp3000_sd_slot: pp3000-sd-slot {
- compatible = "regulator-fixed";
- regulator-name = "pp3000_sd_slot";
- pinctrl-names = "default";
- pinctrl-0 = <&sd_slot_pwr_en>;
-
- enable-active-high;
- gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
-
- vin-supply = <&pp3000>;
- };
-
- /*
- * Technically, this is a small abuse of 'regulator-gpio'; this
- * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are
- * always on though, so it is sufficient to simply control the mux
- * here.
- */
- ppvar_sd_card_io: ppvar-sd-card-io {
- compatible = "regulator-gpio";
- regulator-name = "ppvar_sd_card_io";
- pinctrl-names = "default";
- pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
-
- enable-active-high;
- enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
- gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x1>,
- <3000000 0x0>;
-
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- };
-
- /* EC turns on w/ pp3300_trackpad_en_l */
- pp3300_trackpad: pp3300-trackpad {
- };
-
- /* EC turns on w/ usb_a_en */
- pp5000_usb_a_vbus: pp5000 {
- };
-
- ap_rtc_clk: ap-rtc-clk {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- #clock-cells = <0>;
- };
-
- max98357a: max98357a {
- compatible = "maxim,max98357a";
- pinctrl-names = "default";
- pinctrl-0 = <&sdmode_en>;
- sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
- sdmode-delay = <2>;
- #sound-dai-cells = <0>;
- status = "okay";
- };
-
- sound: sound {
- compatible = "rockchip,rk3399-gru-sound";
- rockchip,cpu = <&i2s0 &i2s2>;
- };
-};
-
-&cdn_dp {
- status = "okay";
-};
-
-/*
- * Set some suspend operating points to avoid OVP in suspend
- *
- * When we go into S3 ARM Trusted Firmware will transition our PWM regulators
- * from wherever they're at back to the "default" operating point (whatever
- * voltage we get when we set the PWM pins to "input").
- *
- * This quick transition under light load has the possibility to trigger the
- * regulator "over voltage protection" (OVP).
- *
- * To make extra certain that we don't hit this OVP at suspend time, we'll
- * transition to a voltage that's much closer to the default (~1.0 V) so that
- * there will not be a big jump. Technically we only need to get within 200 mV
- * of the default voltage, but the speed here should be fast enough and we need
- * suspend/resume to be rock solid.
- */
-
-&cluster0_opp {
- opp05 {
- opp-suspend;
- };
-};
-
-&cluster1_opp {
- opp06 {
- opp-suspend;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&ppvar_litcpu>;
-};
-
-&cpu_l1 {
- cpu-supply = <&ppvar_litcpu>;
-};
-
-&cpu_l2 {
- cpu-supply = <&ppvar_litcpu>;
-};
-
-&cpu_l3 {
- cpu-supply = <&ppvar_litcpu>;
-};
-
-&cpu_b0 {
- cpu-supply = <&ppvar_bigcpu>;
-};
-
-&cpu_b1 {
- cpu-supply = <&ppvar_bigcpu>;
-};
-
-
-&cru {
- assigned-clocks =
- <&cru PLL_GPLL>, <&cru PLL_CPLL>,
- <&cru PLL_NPLL>,
- <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
- <&cru PCLK_PERIHP>,
- <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
- <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
- <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
- <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
- <&cru ACLK_GIC_PRE>,
- <&cru PCLK_DDR>;
- assigned-clock-rates =
- <600000000>, <800000000>,
- <1000000000>,
- <150000000>, <75000000>,
- <37500000>,
- <100000000>, <100000000>,
- <50000000>, <800000000>,
- <100000000>, <50000000>,
- <400000000>, <400000000>,
- <200000000>,
- <200000000>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&ppvar_gpu>;
- status = "okay";
-};
-
-ap_i2c_ts: &i2c3 {
- status = "okay";
-
- clock-frequency = <400000>;
-
- /* These are relatively safe rise/fall times */
- i2c-scl-falling-time-ns = <50>;
- i2c-scl-rising-time-ns = <300>;
-};
-
-ap_i2c_audio: &i2c8 {
- status = "okay";
-
- clock-frequency = <400000>;
-
- /* These are relatively safe rise/fall times */
- i2c-scl-falling-time-ns = <50>;
- i2c-scl-rising-time-ns = <300>;
-
- codec: da7219@1a {
- compatible = "dlg,da7219";
- reg = <0x1a>;
- interrupt-parent = <&gpio1>;
- interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&cru SCLK_I2S_8CH_OUT>;
- clock-names = "mclk";
- dlg,micbias-lvl = <2600>;
- dlg,mic-amp-in-sel = "diff";
- pinctrl-names = "default";
- pinctrl-0 = <&headset_int_l>;
- VDD-supply = <&pp1800>;
- VDDMIC-supply = <&pp3300>;
- VDDIO-supply = <&pp1800>;
-
- da7219_aad {
- dlg,adc-1bit-rpt = <1>;
- dlg,btn-avg = <4>;
- dlg,btn-cfg = <50>;
- dlg,mic-det-thr = <500>;
- dlg,jack-ins-deb = <20>;
- dlg,jack-det-rate = "32ms_64ms";
- dlg,jack-rem-deb = <1>;
-
- dlg,a-d-btn-thr = <0xa>;
- dlg,d-b-btn-thr = <0x16>;
- dlg,b-c-btn-thr = <0x21>;
- dlg,c-mic-btn-thr = <0x3E>;
- };
- };
-};
-
-&i2s0 {
- status = "okay";
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- status = "okay";
-
- audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */
- bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */
- gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */
- sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */
-};
-
-&pcie0 {
- status = "okay";
-
- ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>;
- vpcie3v3-supply = <&pp3300_wifi_bt>;
- vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */
- vpcie0v9-supply = <&pp900_pcie>;
-
- pci_rootport: pcie@0,0 {
- reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- };
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pmu_io_domains {
- status = "okay";
-
- pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&pwm3 {
- status = "okay";
-};
-
-&sdhci {
- /*
- * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
- * same (or nearly the same) performance for all eMMC that are intended
- * to be used.
- */
- assigned-clock-rates = <150000000>;
-
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- non-removable;
- status = "okay";
-};
-
-&sdmmc {
- status = "okay";
-
- /*
- * Note: configure "sdmmc_cd" as card detect even though it's actually
- * hooked to ground. Because we specified "cd-gpios" below dw_mmc
- * should be ignoring card detect anyway. Specifying the pin as
- * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag)
- * turned on that the system will still make sure the port is
- * configured as SDMMC and not JTAG.
- */
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin
- &sdmmc_bus4>;
-
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
- disable-wp;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- vmmc-supply = <&pp3000_sd_slot>;
- vqmmc-supply = <&ppvar_sd_card_io>;
-};
-
-&spi1 {
- status = "okay";
-
- pinctrl-names = "default", "sleep";
- pinctrl-1 = <&spi1_sleep>;
-
- spi_flash: spiflash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
-
- /* May run faster once verified. */
- spi-max-frequency = <10000000>;
- };
-};
-
-&spi2 {
- status = "okay";
-};
-
-&spi5 {
- status = "okay";
-
- cros_ec: ec@0 {
- compatible = "google,cros-ec-spi";
- reg = <0>;
- interrupt-parent = <&gpio0>;
- interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&ec_ap_int_l>;
- spi-max-frequency = <3000000>;
-
- i2c_tunnel: i2c-tunnel {
- compatible = "google,cros-ec-i2c-tunnel";
- google,remote-bus = <4>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- usbc_extcon0: extcon0 {
- compatible = "google,extcon-usbc-cros-ec";
- google,usb-port-id = <0>;
- };
- };
-};
-
-&tsadc {
- status = "okay";
-
- rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
-};
-
-&tcphy0 {
- status = "okay";
- extcon = <&usbc_extcon0>;
-};
-
-&u2phy0 {
- status = "okay";
-};
-
-&u2phy0_host {
- status = "okay";
-};
-
-&u2phy1_host {
- status = "okay";
-};
-
-&u2phy0_otg {
- status = "okay";
-};
-
-&u2phy1_otg {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
- extcon = <&usbc_extcon0>;
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "host";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
-
-#include <cros-ec-keyboard.dtsi>
-#include <cros-ec-sbs.dtsi>
-
-&pinctrl {
- /*
- * pinctrl settings for pins that have no real owners.
- *
- * At the moment settings are identical for S0 and S3, but if we later
- * need to configure things differently for S3 we'll adjust here.
- */
- pinctrl-names = "default";
- pinctrl-0 = <
- &ap_pwroff /* AP will auto-assert this when in S3 */
- &clk_32k /* This pin is always 32k on gru boards */
- >;
-
- pcfg_output_low: pcfg-output-low {
- output-low;
- };
-
- pcfg_output_high: pcfg-output-high {
- output-high;
- };
-
- pcfg_pull_none_8ma: pcfg-pull-none-8ma {
- bias-disable;
- drive-strength = <8>;
- };
-
- backlight-enable {
- bl_en: bl-en {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- cros-ec {
- ec_ap_int_l: ec-ap-int-l {
- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- discrete-regulators {
- sd_io_pwr_en: sd-io-pwr-en {
- rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO
- &pcfg_pull_none>;
- };
-
- sd_pwr_1800_sel: sd-pwr-1800-sel {
- rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO
- &pcfg_pull_none>;
- };
-
- sd_slot_pwr_en: sd-slot-pwr-en {
- rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO
- &pcfg_pull_none>;
- };
- };
-
- codec {
- /* Has external pullup */
- headset_int_l: headset-int-l {
- rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- mic_int: mic-int {
- rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- max98357a {
- sdmode_en: sdmode-en {
- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- pcie {
- pcie_clkreqn_cpm: pci-clkreqn-cpm {
- /*
- * Since our pcie doesn't support ClockPM(CPM), we want
- * to hack this as gpio, so the EP could be able to
- * de-assert it along and make ClockPM(CPM) work.
- */
- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdmmc {
- /*
- * We run sdmmc at max speed; bump up drive strength.
- * We also have external pulls, so disable the internal ones.
- */
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins =
- <4 RK_PB0 1 &pcfg_pull_none_8ma>,
- <4 RK_PB1 1 &pcfg_pull_none_8ma>,
- <4 RK_PB2 1 &pcfg_pull_none_8ma>,
- <4 RK_PB3 1 &pcfg_pull_none_8ma>;
- };
-
- sdmmc_clk: sdmmc-clk {
- rockchip,pins =
- <4 RK_PB4 1 &pcfg_pull_none_8ma>;
- };
-
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins =
- <4 RK_PB5 1 &pcfg_pull_none_8ma>;
- };
-
- /*
- * In our case the official card detect is hooked to ground
- * to avoid getting access to JTAG just by sticking something
- * in the SD card slot (see the force_jtag bit in the TRM).
- *
- * We still configure it as card detect because it doesn't
- * hurt and dw_mmc will ignore it. We make sure to disable
- * the pull though so we don't burn needless power.
- */
- sdmmc_cd: sdmmc-cd {
- rockchip,pins =
- <0 RK_PA7 1 &pcfg_pull_none>;
- };
-
- /* This is where we actually hook up CD; has external pull */
- sdmmc_cd_pin: sdmmc-cd-pin {
- rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- spi1 {
- spi1_sleep: spi1-sleep {
- /*
- * Pull down SPI1 CLK/CS/RX/TX during suspend, to
- * prevent leakage.
- */
- rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
- <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>,
- <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
- <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- touchscreen {
- touch_int_l: touch-int-l {
- rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- touch_reset_l: touch-reset-l {
- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- trackpad {
- ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
- rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
- };
-
- trackpad_int_l: trackpad-int-l {
- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- wifi: wifi {
- wlan_module_reset_l: wlan-module-reset-l {
- rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_l: bt-host-wake-l {
- /* Kevin has an external pull up, but Gru does not */
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- write-protect {
- ap_fw_wp: ap-fw-wp {
- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
- * (https://www.khadas.com)
- */
-
-/dts-v1/;
-#include "rk3399-khadas-edge.dtsi"
-
-/ {
- model = "Khadas Edge-Captain";
- compatible = "khadas,edge-captain", "rockchip,rk3399";
-};
-
-&gmac {
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- status = "okay";
-};
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
- };
+&spiflash {
+ bootph-pre-ram;
+ bootph-some-ram;
};
&vdd_log {
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
- * (https://www.khadas.com)
- */
-
-/dts-v1/;
-#include "rk3399-khadas-edge.dtsi"
-
-/ {
- model = "Khadas Edge-V";
- compatible = "khadas,edge-v", "rockchip,rk3399";
-};
-
-&gmac {
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
- * (https://www.khadas.com)
- */
-
-/dts-v1/;
-#include "rk3399-khadas-edge.dtsi"
-
-/ {
- model = "Khadas Edge";
- compatible = "khadas,edge", "rockchip,rk3399";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
- * (https://www.khadas.com)
- */
-
-/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/pwm/pwm.h>
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- aliases {
- mmc0 = &sdio0;
- mmc1 = &sdmmc;
- mmc2 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
-
- /*
- * On the module itself this is one of these (depending
- * on the actual card populated):
- * - SDIO_RESET_L_WL_REG_ON
- * - PDN (power down when low)
- */
- reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
- };
-
- /* switched by pmic_sleep */
- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_1v8>;
- };
-
- vcc3v3_pcie: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vsys_3v3>;
- };
-
- /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- vin-supply = <&vsys_5v0>;
- };
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- vin-supply = <&vsys_3v3>;
- };
-
- vsys: vsys {
- compatible = "regulator-fixed";
- regulator-name = "vsys";
- regulator-always-on;
- regulator-boot-on;
- };
-
- vsys_3v3: vsys-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vsys_3v3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vsys>;
- };
-
- vsys_5v0: vsys-5v0 {
- compatible = "regulator-fixed";
- regulator-name = "vsys_5v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vsys>;
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 1>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- recovery {
- label = "Recovery";
- linux,code = <KEY_VENDOR>;
- press-threshold-microvolt = <18000>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&pwrbtn>;
-
- power {
- debounce-interval = <100>;
- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "GPIO Key Power";
- linux,code = <KEY_POWER>;
- wakeup-source;
- };
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
- linux,rc-map-name = "rc-khadas";
- pinctrl-names = "default";
- pinctrl-0 = <&ir_rx>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&sys_led_pin>, <&user_led_pin>;
-
- sys_led: led-0 {
- label = "sys_led";
- linux,default-trigger = "heartbeat";
- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- };
-
- user_led: led-1 {
- label = "user_led";
- default-state = "off";
- gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- fan: pwm-fan {
- compatible = "pwm-fan";
- cooling-levels = <0 150 200 255>;
- #cooling-cells = <2>;
- fan-supply = <&vsys_5v0>;
- pwms = <&pwm0 0 40000 0>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_thermal {
- trips {
- cpu_warm: cpu_warm {
- temperature = <55000>;
- hysteresis = <2000>;
- type = "active";
- };
-
- cpu_hot: cpu_hot {
- temperature = <65000>;
- hysteresis = <2000>;
- type = "active";
- };
- };
-
- cooling-maps {
- map2 {
- trip = <&cpu_warm>;
- cooling-device = <&fan THERMAL_NO_LIMIT 1>;
- };
-
- map3 {
- trip = <&cpu_hot>;
- cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
- };
- };
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc_lan>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&gpu_thermal {
- trips {
- gpu_warm: gpu_warm {
- temperature = <55000>;
- hysteresis = <2000>;
- type = "active";
- };
-
- gpu_hot: gpu_hot {
- temperature = <65000>;
- hysteresis = <2000>;
- type = "active";
- };
- };
-
- cooling-maps {
- map1 {
- trip = <&gpu_warm>;
- cooling-device = <&fan THERMAL_NO_LIMIT 1>;
- };
-
- map2 {
- trip = <&gpu_hot>;
- cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
- };
- };
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c3>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- status = "okay";
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vsys_3v3>;
- vcc2-supply = <&vsys_3v3>;
- vcc3-supply = <&vsys_3v3>;
- vcc4-supply = <&vsys_3v3>;
- vcc6-supply = <&vsys_3v3>;
- vcc7-supply = <&vsys_3v3>;
- vcc8-supply = <&vsys_3v3>;
- vcc9-supply = <&vsys_3v3>;
- vcc10-supply = <&vsys_3v3>;
- vcc11-supply = <&vsys_3v3>;
- vcc12-supply = <&vsys_3v3>;
- vddio-supply = <&vcc_1v8>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v8_apio2: LDO_REG1 {
- regulator-name = "vcc1v8_apio2";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_vldo2: LDO_REG2 {
- regulator-name = "vcc_vldo2";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_pmupll: LDO_REG3 {
- regulator-name = "vcc1v8_pmupll";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vccio_sd: LDO_REG4 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc_vldo5: LDO_REG5 {
- regulator-name = "vcc_vldo5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcc1v8_codec: LDO_REG7 {
- regulator-name = "vcc1v8_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_s3: vcc_lan: SWITCH_REG1 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&cpu_b_sleep>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vsys_3v3>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&gpu_sleep>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vsys_3v3>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c8 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <160>;
- i2c-scl-falling-time-ns = <30>;
- status = "okay";
-};
-
-&i2s0 {
- rockchip,playback-channels = <8>;
- rockchip,capture-channels = <8>;
- status = "okay";
-};
-
-&i2s1 {
- rockchip,playback-channels = <2>;
- rockchip,capture-channels = <2>;
- status = "okay";
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- bt656-supply = <&vcc1v8_apio2>;
- audio-supply = <&vcc1v8_codec>;
- sdmmc-supply = <&vccio_sd>;
- gpio1830-supply = <&vcc_3v0>;
- status = "okay";
-};
-
-&pmu_io_domains {
- pmu1830-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&pinctrl {
- bt {
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_reg_on_h: bt-reg-on-h {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- buttons {
- pwrbtn: pwrbtn {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- ir {
- ir_rx: ir-rx {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- leds {
- sys_led_pin: sys-led-pin {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- user_led_pin: user-led-pin {
- rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- cpu_b_sleep: cpu-b-sleep {
- rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- gpu_sleep: gpu-sleep {
- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb2 {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wifi {
- wifi_host_wake_l: wifi-host-wake-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
-};
-
-&sdio0 {
- /* WiFi & BT combo module Ampak AP6356S */
- bus-width = <4>;
- cap-sdio-irq;
- cap-sd-highspeed;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- vqmmc-supply = <&vcc1v8_s3>;
- vmmc-supply = <&vccio_sd>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
- interrupt-names = "host-wake";
- brcm,drive-strength = <5>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_l>;
- };
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- non-removable;
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-
- spiflash: flash@0 {
- compatible = "winbond,w25q128fw", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <104000000>;
- };
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- clocks = <&rk808 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
- max-speed = <4000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
- vbat-supply = <&vsys_3v3>;
- vddio-supply = <&vcc_1v8>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "otg";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
- };
-};
-
&vdd_log {
regulator-init-microvolt = <950000>;
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Andy Yan <andy.yan@gmail.com>
- */
-
-/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/pwm/pwm.h>
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- model = "Leez RK3399 P710";
- compatible = "leez,p710", "rockchip,rk3399";
-
- aliases {
- mmc0 = &sdio0;
- mmc1 = &sdmmc;
- mmc2 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_reg_on_h>;
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-
- dc5v_adp: dc5v-adp {
- compatible = "regulator-fixed";
- regulator-name = "dc5v_adapter";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc3v3_lan: vcc3v3-lan {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_lan";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vim-supply = <&vcc3v3_sys>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_host0: vcc5v0_host1: vcc5v0-host {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <5500000>;
- regulator-max-microvolt = <5500000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_host3: vcc5v0-host3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host3";
- enable-active-high;
- gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host3_en>;
- regulator-always-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc5v_adp>;
- };
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc3v3_lan>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c7>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- status = "okay";
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio1>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc5v0_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v8_dvp: LDO_REG1 {
- regulator-name = "vcc1v8_dvp";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_hdmi: LDO_REG2 {
- regulator-name = "vcc1v8_hdmi";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca_1v8: LDO_REG3 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vccio_sd: LDO_REG4 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-name = "vcca3v0_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcc0v9_hdmi: LDO_REG7 {
- regulator-name = "vcc0v9_hdmi";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel1_pin>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel2_pin>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c1 {
- i2c-scl-rising-time-ns = <300>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c4 {
- i2c-scl-rising-time-ns = <600>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-&i2c7 {
- status = "okay";
-};
-
-&i2s0 {
- rockchip,playback-channels = <8>;
- rockchip,capture-channels = <8>;
- status = "okay";
-};
-
-&i2s1 {
- rockchip,playback-channels = <2>;
- rockchip,capture-channels = <2>;
- status = "okay";
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- status = "okay";
-
- bt656-supply = <&vcc1v8_dvp>;
- audio-supply = <&vcc_1v8>;
- sdmmc-supply = <&vccio_sd>;
- gpio1830-supply = <&vcc_3v0>;
-};
-
-&pmu_io_domains {
- status = "okay";
- pmu1830-supply = <&vcc_3v0>;
-};
-
-&pinctrl {
- bt {
- bt_reg_on_h: bt-reg-on-h {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- vsel1_pin: vsel1-pin {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- vsel2_pin: vsel2-pin {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- usb2 {
- vcc5v0_host3_en: vcc5v0-host3-en {
- rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wifi {
- wifi_reg_on_h: wifi-reg-on-h {
- rockchip,pins =
- <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wifi_host_wake_l: wifi-host-wake-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-
- vref-supply = <&vcc_1v8>;
-};
-
-&sdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- bus-width = <4>;
- clock-frequency = <50000000>;
- cap-sdio-irq;
- cap-sd-highspeed;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
- interrupt-names = "host-wake";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_l>;
- };
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- non-removable;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
- status = "okay";
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- status = "okay";
-
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vcc5v0_host0>;
- status = "okay";
- };
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_host1>;
- status = "okay";
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "otg";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * FriendlyElec NanoPC-T4 board device tree source
- *
- * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyarm.com)
- *
- * Copyright (c) 2018 Collabora Ltd.
- */
-
-/dts-v1/;
-#include "rk3399-nanopi4.dtsi"
-
-/ {
- model = "FriendlyElec NanoPC-T4";
- compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
-
- vcc12v0_sys: vcc12v0-sys {
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <12000000>;
- regulator-min-microvolt = <12000000>;
- regulator-name = "vcc12v0_sys";
- };
-
- vcc5v0_host0: vcc5v0-host0 {
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vcc5v0_host0";
- vin-supply = <&vcc5v0_sys>;
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 1>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- recovery {
- label = "Recovery";
- linux,code = <KEY_VENDOR>;
- press-threshold-microvolt = <18000>;
- };
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&ir_rx>;
- };
-
- fan: pwm-fan {
- compatible = "pwm-fan";
- /*
- * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels
- * work out to 0, ~1200, ~3000, and 5000RPM respectively.
- */
- cooling-levels = <0 12 18 255>;
- #cooling-cells = <2>;
- fan-supply = <&vcc12v0_sys>;
- pwms = <&pwm1 0 50000 0>;
- };
-};
-
-&cpu_thermal {
- trips {
- cpu_warm: cpu_warm {
- temperature = <55000>;
- hysteresis = <2000>;
- type = "active";
- };
-
- cpu_hot: cpu_hot {
- temperature = <65000>;
- hysteresis = <2000>;
- type = "active";
- };
- };
-
- cooling-maps {
- map2 {
- trip = <&cpu_warm>;
- cooling-device = <&fan THERMAL_NO_LIMIT 1>;
- };
-
- map3 {
- trip = <&cpu_hot>;
- cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
- };
- };
-};
-
-&pcie0 {
- ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- vpcie3v3-supply = <&vcc3v3_sys>;
-};
-
-&pinctrl {
- ir {
- ir_rx: ir-rx {
- /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */
- rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>;
- };
- };
-};
-
-&sdhci {
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
-};
-
-&u2phy0_host {
- phy-supply = <&vcc5v0_host0>;
-};
-
-&u2phy1_host {
- phy-supply = <&vcc5v0_host0>;
-};
-
-&vcc5v0_sys {
- vin-supply = <&vcc12v0_sys>;
-};
-
-&vcc3v3_sys {
- vin-supply = <&vcc12v0_sys>;
-};
-
-&vbus_typec {
- enable-active-high;
- gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vcc5v0_sys>;
-};
*/
/dts-v1/;
-#include "rk3399-nanopi4.dtsi"
-
-/ {
- model = "FriendlyElec NanoPi M4";
- compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
-
- vdd_5v: vdd-5v {
- compatible = "regulator-fixed";
- regulator-name = "vdd_5v";
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc5v0_core: vcc5v0-core {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_core";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_5v>;
- };
-
- vcc5v0_usb1: vcc5v0-usb1 {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb1";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_usb2: vcc5v0-usb2 {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb2";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&vcc3v3_sys {
- vin-supply = <&vcc5v0_core>;
-};
-
-&u2phy0_host {
- phy-supply = <&vcc5v0_usb1>;
-};
-
-&u2phy1_host {
- phy-supply = <&vcc5v0_usb2>;
-};
-
-&vbus_typec {
- regulator-always-on;
- vin-supply = <&vdd_5v>;
-};
+#include "rk3399-nanopi-m4.dts"
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * FriendlyElec NanoPi M4 board device tree source
- *
- * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyarm.com)
- *
- * Copyright (c) 2018 Collabora Ltd.
- * Copyright (c) 2019 Arm Ltd.
- */
-
-/dts-v1/;
-#include "rk3399-nanopi4.dtsi"
-
-/ {
- model = "FriendlyElec NanoPi M4";
- compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
-
- vdd_5v: vdd-5v {
- compatible = "regulator-fixed";
- regulator-name = "vdd_5v";
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc5v0_core: vcc5v0-core {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_core";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_5v>;
- };
-
- vcc5v0_usb1: vcc5v0-usb1 {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb1";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_usb2: vcc5v0-usb2 {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb2";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&vcc3v3_sys {
- vin-supply = <&vcc5v0_core>;
-};
-
-&u2phy0_host {
- phy-supply = <&vcc5v0_usb1>;
-};
-
-&u2phy1_host {
- phy-supply = <&vcc5v0_usb2>;
-};
-
-&vbus_typec {
- regulator-always-on;
- vin-supply = <&vdd_5v>;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * FriendlyElec NanoPi M4B board device tree source
- *
- * Copyright (c) 2020 Chen-Yu Tsai <wens@csie.org>
- */
-
-/dts-v1/;
-#include "rk3399-nanopi-m4.dts"
-
-/ {
- model = "FriendlyElec NanoPi M4B";
- compatible = "friendlyarm,nanopi-m4b", "rockchip,rk3399";
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 1>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1500000>;
- poll-interval = <100>;
-
- recovery {
- label = "Recovery";
- linux,code = <KEY_VENDOR>;
- press-threshold-microvolt = <18000>;
- };
- };
-};
-
-/* No USB type-C PD power manager */
-/delete-node/ &fusb0;
-
-&i2c4 {
- status = "disabled";
-};
-
-&u2phy0_host {
- phy-supply = <&vcc5v0_usb2>;
-};
-
-&u2phy0_otg {
- phy-supply = <&vbus_typec>;
-};
-
-&u2phy1_otg {
- phy-supply = <&vcc5v0_usb1>;
-};
-
-&vbus_typec {
- enable-active-high;
- gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019 Amarula Solutions B.V.
- * Author: Jagan Teki <jagan@amarulasolutions.com>
- */
-
-/dts-v1/;
-
-#include "rk3399-nanopi4.dtsi"
-
-/ {
- model = "FriendlyARM NanoPi NEO4";
- compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399";
-
- vdd_5v: vdd-5v {
- compatible = "regulator-fixed";
- regulator-name = "vdd_5v";
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc5v0_core: vcc5v0-core {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_core";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_5v>;
- };
-
- vcc5v0_usb1: vcc5v0-usb1 {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb1";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&vcc3v3_sys {
- vin-supply = <&vcc5v0_core>;
-};
-
-&u2phy0_host {
- phy-supply = <&vcc5v0_usb1>;
-};
-
-&vbus_typec {
- regulator-always-on;
- vin-supply = <&vdd_5v>;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * FriendlyElec NanoPC-T4 board device tree source
- *
- * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyarm.com)
- *
- * Copyright (c) 2018 Collabora Ltd.
- *
- * Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
- * Copyright (c) 2020 Marty Jones <mj8263788@gmail.com>
- * Copyright (c) 2021 Tianling Shen <cnsztl@gmail.com>
- */
-
-/dts-v1/;
-#include "rk3399-nanopi4.dtsi"
-
-/ {
- model = "FriendlyElec NanoPi R4S";
- compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
-
- /delete-node/ display-subsystem;
-
- gpio-leds {
- pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
-
- /delete-node/ led-0;
-
- lan_led: led-lan {
- gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
- label = "green:lan";
- };
-
- sys_led: led-sys {
- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
- label = "red:power";
- default-state = "on";
- };
-
- wan_led: led-wan {
- gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
- label = "green:wan";
- };
- };
-
- gpio-keys {
- pinctrl-0 = <&reset_button_pin>;
-
- /delete-node/ power;
-
- reset {
- debounce-interval = <50>;
- gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
- label = "reset";
- linux,code = <KEY_RESTART>;
- };
- };
-
- vdd_5v: vdd-5v {
- compatible = "regulator-fixed";
- regulator-name = "vdd_5v";
- regulator-always-on;
- regulator-boot-on;
- };
-};
-
-&emmc_phy {
- status = "disabled";
-};
-
-&i2c4 {
- status = "disabled";
-};
-
-&pcie0 {
- max-link-speed = <1>;
- num-lanes = <1>;
- vpcie3v3-supply = <&vcc3v3_sys>;
-};
-
-&pinctrl {
- gpio-leds {
- /delete-node/ status-led-pin;
-
- lan_led_pin: lan-led-pin {
- rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- sys_led_pin: sys-led-pin {
- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wan_led_pin: wan-led-pin {
- rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- rockchip-key {
- /delete-node/ power-key;
-
- reset_button_pin: reset-button-pin {
- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&sdhci {
- status = "disabled";
-};
-
-&sdio0 {
- status = "disabled";
-};
-
-&u2phy0_host {
- phy-supply = <&vdd_5v>;
-};
-
-&u2phy1_host {
- status = "disabled";
-};
-
-&uart0 {
- status = "disabled";
-};
-
-&usbdrd_dwc3_0 {
- dr_mode = "host";
-};
-
-&vcc3v3_sys {
- vin-supply = <&vcc5v0_sys>;
-};
#include "rk3399-u-boot.dtsi"
-/{
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
- };
+&gpio0 {
+ bootph-pre-ram;
};
&sdmmc {
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
};
+
+&sdmmc0_pwr_h {
+ bootph-pre-ram;
+};
+
+&vcc3v0_sd {
+ bootph-pre-ram;
+};
+
+&vcc_sdio {
+ regulator-init-microvolt = <3000000>;
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * RK3399-based FriendlyElec boards device tree source
- *
- * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
- *
- * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyarm.com)
- *
- * Copyright (c) 2018 Collabora Ltd.
- * Copyright (c) 2019 Arm Ltd.
- */
-
-/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- aliases {
- mmc0 = &sdio0;
- mmc1 = &sdmmc;
- mmc2 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3_sys";
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-name = "vcc5v0_sys";
- vin-supply = <&vdd_5v>;
- };
-
- /* switched by pmic_sleep */
- vcc1v8_s3: vcc1v8-s3 {
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8_s3";
- vin-supply = <&vcc_1v8>;
- };
-
- vcc3v0_sd: vcc3v0-sd {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_pwr_h>;
- regulator-always-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "vcc3v0_sd";
- vin-supply = <&vcc3v3_sys>;
- };
-
- /*
- * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only
- * drives the enable pin, but we can't quite model that.
- */
- vcca0v9_s3: vcca0v9-s3 {
- compatible = "regulator-fixed";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vcca0v9_s3";
- vin-supply = <&vcc1v8_s3>;
- };
-
- /* As above, actually supplied by vcc3v3_sys */
- vcca1v8_s3: vcca1v8-s3 {
- compatible = "regulator-fixed";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcca1v8_s3";
- vin-supply = <&vcc1v8_s3>;
- };
-
- vbus_typec: vbus-typec {
- compatible = "regulator-fixed";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-name = "vbus_typec";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&power_key>;
-
- power {
- debounce-interval = <100>;
- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "GPIO Key Power";
- linux,code = <KEY_POWER>;
- wakeup-source;
- };
- };
-
- leds: gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&status_led_pin>;
-
- status_led: led-0 {
- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
- label = "status_led";
- linux,default-trigger = "heartbeat";
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_reg_on_h>;
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clock-parents = <&clkin_gmac>;
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- clock_in_out = "input";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
- phy-handle = <&rtl8211e>;
- phy-mode = "rgmii";
- phy-supply = <&vcc3v3_s3>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtl8211e: ethernet-phy@1 {
- reg = <1>;
- interrupt-parent = <&gpio3>;
- interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
- reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c7>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <160>;
- i2c-scl-falling-time-ns = <30>;
- status = "okay";
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&cpu_b_sleep>;
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vdd_cpu_b";
- regulator-ramp-delay = <1000>;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&gpu_sleep>;
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vdd_gpu";
- regulator-ramp-delay = <1000>;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- clock-output-names = "xin32k", "rtc_clko_wifi";
- #clock-cells = <1>;
- interrupt-parent = <&gpio1>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- vcc10-supply = <&vcc3v3_sys>;
- vcc11-supply = <&vcc3v3_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_3v0>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-name = "vdd_center";
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-name = "vdd_cpu_l";
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vcc_ddr";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v8_cam: LDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8_cam";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v0_touch: LDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "vcc3v0_touch";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_pmupll: LDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8_pmupll";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sdio: LDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-init-microvolt = <3000000>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_sdio";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "vcca3v0_codec";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc_1v5";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcca1v8_codec: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcca1v8_codec";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "vcc_3v0";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_s3: SWITCH_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vcc3v3_s3";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vcc3v3_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <200000>;
- i2c-scl-rising-time-ns = <150>;
- i2c-scl-falling-time-ns = <30>;
- status = "okay";
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <160>;
- i2c-scl-falling-time-ns = <30>;
- status = "okay";
-
- fusb0: typec-portc@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&fusb0_int>;
- vbus-supply = <&vbus_typec>;
- };
-};
-
-&i2c7 {
- status = "okay";
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- bt656-supply = <&vcc_1v8>;
- audio-supply = <&vcca1v8_codec>;
- sdmmc-supply = <&vcc_sdio>;
- gpio1830-supply = <&vcc_3v0>;
- status = "okay";
-};
-
-&pcie_phy {
- assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
- assigned-clock-rates = <100000000>;
- assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
- status = "okay";
-};
-
-&pcie0 {
- num-lanes = <2>;
- vpcie0v9-supply = <&vcca0v9_s3>;
- vpcie1v8-supply = <&vcca1v8_s3>;
- status = "okay";
-};
-
-&pinctrl {
- fusb30x {
- fusb0_int: fusb0-int {
- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- gpio-leds {
- status_led_pin: status-led-pin {
- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- gmac {
- phy_intb: phy-intb {
- rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- phy_rstb: phy-rstb {
- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- cpu_b_sleep: cpu-b-sleep {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- gpu_sleep: gpu-sleep {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- rockchip-key {
- power_key: power-key {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- sdio {
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_reg_on_h: bt-reg-on-h {
- /* external pullup to VCC1V8_PMUPLL */
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wifi_reg_on_h: wifi-reg_on-h {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdmmc {
- sdmmc0_det_l: sdmmc0-det-l {
- rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- sdmmc0_pwr_h: sdmmc0-pwr-h {
- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmu1830-supply = <&vcc_3v0>;
- status = "okay";
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&pwm2 {
- pinctrl-names = "active";
- pinctrl-0 = <&pwm2_pin_pull_down>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- status = "okay";
-};
-
-&sdio0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v0_sd>;
- vqmmc-supply = <&vcc_sdio>;
- status = "okay";
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-};
-
-&u2phy0_host {
- status = "okay";
-};
-
-&u2phy0_otg {
- status = "okay";
-};
-
-&u2phy1 {
- status = "okay";
-};
-
-&u2phy1_host {
- status = "okay";
-};
-
-&u2phy1_otg {
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- clocks = <&rk808 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- max-speed = <4000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
- vbat-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-/ {
- cluster0_opp: opp-table0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <800000>;
- clock-latency-ns = <40000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <825000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <850000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <900000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <975000>;
- };
- opp05 {
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <1100000>;
- };
- opp06 {
- opp-hz = /bits/ 64 <1512000000>;
- opp-microvolt = <1150000>;
- };
- };
-
- cluster1_opp: opp-table1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <800000>;
- clock-latency-ns = <40000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <800000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <825000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <850000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <900000>;
- };
- opp05 {
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <975000>;
- };
- opp06 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <1050000>;
- };
- opp07 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1150000>;
- };
- opp08 {
- opp-hz = /bits/ 64 <2016000000>;
- opp-microvolt = <1250000>;
- };
- };
-
- gpu_opp_table: opp-table2 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <800000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <297000000>;
- opp-microvolt = <800000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <825000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <850000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <925000>;
- };
- opp05 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <1075000>;
- };
- };
-};
-
-&cpu_l0 {
- operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_l1 {
- operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_l2 {
- operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_l3 {
- operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_b0 {
- operating-points-v2 = <&cluster1_opp>;
-};
-
-&cpu_b1 {
- operating-points-v2 = <&cluster1_opp>;
-};
-
-&gpu {
- operating-points-v2 = <&gpu_opp_table>;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-/ {
- cluster0_opp: opp-table0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <825000 825000 1250000>;
- clock-latency-ns = <40000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <825000 825000 1250000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <850000 850000 1250000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <925000 925000 1250000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1000000 1000000 1250000>;
- };
- opp05 {
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <1125000 1125000 1250000>;
- };
- };
-
- cluster1_opp: opp-table1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <825000 825000 1250000>;
- clock-latency-ns = <40000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <825000 825000 1250000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <825000 825000 1250000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <875000 875000 1250000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <950000 950000 1250000>;
- };
- opp05 {
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <1025000 1025000 1250000>;
- };
- opp06 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <1100000 1100000 1250000>;
- };
- opp07 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1200000 1200000 1250000>;
- };
- };
-
- gpu_opp_table: opp-table2 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <825000 825000 1150000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <297000000>;
- opp-microvolt = <825000 825000 1150000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <825000 825000 1150000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <875000 875000 1150000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <925000 925000 1150000>;
- };
- opp05 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <1100000 1100000 1150000>;
- };
- };
-};
-
-&cpu_l0 {
- operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_l1 {
- operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_l2 {
- operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_l3 {
- operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_b0 {
- operating-points-v2 = <&cluster1_opp>;
-};
-
-&cpu_b1 {
- operating-points-v2 = <&cluster1_opp>;
-};
-
-&gpu {
- operating-points-v2 = <&gpu_opp_table>;
-};
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1333.dtsi"
+&gpio0 {
+ bootph-pre-ram;
+};
+
+&sdmmc0_pwr_h {
+ bootph-pre-ram;
+};
+
+&vcc3v0_sd {
+ bootph-pre-ram;
+};
+
&vdd_log {
regulator-init-microvolt = <950000>;
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
- */
-
-/dts-v1/;
-
-#include "dt-bindings/pwm/pwm.h"
-#include "dt-bindings/input/input.h"
-#include "dt-bindings/usb/pd.h"
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- model = "Orange Pi RK3399 Board";
- compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
-
- aliases {
- mmc0 = &sdio0;
- mmc1 = &sdmmc;
- mmc2 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 1>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- button-up {
- label = "Volume Up";
- linux,code = <KEY_VOLUMEUP>;
- press-threshold-microvolt = <100000>;
- };
-
- button-down {
- label = "Volume Down";
- linux,code = <KEY_VOLUMEDOWN>;
- press-threshold-microvolt = <300000>;
- };
-
- back {
- label = "Back";
- linux,code = <KEY_BACK>;
- press-threshold-microvolt = <985000>;
- };
-
- menu {
- label = "Menu";
- linux,code = <KEY_MENU>;
- press-threshold-microvolt = <1314000>;
- };
- };
-
- dc_12v: dc-12v {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- keys: gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
-
- power {
- debounce-interval = <100>;
- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "GPIO Power";
- linux,code = <KEY_POWER>;
- linux,input-type = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwr_btn>;
- wakeup-source;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_reg_on_h>;
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-
- /* switched by pmic_sleep */
- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_1v8>;
- };
-
- vcc3v0_sd: vcc3v0-sd {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_pwr_h>;
- regulator-boot-on;
- regulator-max-microvolt = <3000000>;
- regulator-min-microvolt = <3000000>;
- regulator-name = "vcc3v0_sd";
- vin-supply = <&vcc3v3_sys>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_sys>;
- };
-
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- vin-supply = <&vcc_sys>;
- };
-
- vbus_typec: vbus-typec-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_typec_en>;
- regulator-name = "vbus_typec";
- vin-supply = <&vcc_sys>;
- };
-
- vcc_sys: vcc-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- vin-supply = <&vcc_sys>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc3v3_s3>;
- phy-mode = "rgmii";
- phy-handle = <&rtl8211e>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtl8211e: ethernet-phy@1 {
- reg = <1>;
- interrupt-parent = <&gpio3>;
- interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
- reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c3>;
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- status = "okay";
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio1>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "rtc_clko_soc", "rtc_clko_wifi";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- vcc10-supply = <&vcc3v3_sys>;
- vcc11-supply = <&vcc3v3_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_3v0>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v8_dvp: LDO_REG1 {
- regulator-name = "vcc1v8_dvp";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3400000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v0_tp: LDO_REG2 {
- regulator-name = "vcc3v0_tp";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3400000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_pmupll: LDO_REG3 {
- regulator-name = "vcc1v8_pmupll";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <2500000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sdio: LDO_REG4 {
- regulator-name = "vcc_sdio";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3400000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-name = "vcca3v0_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3400000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <2500000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcca1v8_codec: LDO_REG7 {
- regulator-name = "vcca1v8_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <2500000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3400000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_s3: SWITCH_REG1 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&cpu_b_sleep>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&gpu_sleep>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c1 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-
- ak09911@c {
- compatible = "asahi-kasei,ak09911";
- reg = <0x0c>;
- vdd-supply = <&vcc3v3_s3>;
- vid-supply = <&vcc3v3_s3>;
- };
-
- mpu6500@68 {
- compatible = "invensense,mpu6500";
- reg = <0x68>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
- pinctrl-names = "default";
- pinctrl-0 = <&gsensor_int_l>;
- vddio-supply = <&vcc3v3_s3>;
- };
-
- lsm6ds3@6a {
- compatible = "st,lsm6ds3";
- reg = <0x6a>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>;
- pinctrl-names = "default";
- pinctrl-0 = <&gyr_int_l>;
- vdd-supply = <&vcc3v3_s3>;
- vddio-supply = <&vcc3v3_s3>;
- };
-
- cm32181@10 {
- compatible = "capella,cm32181";
- reg = <0x10>;
- interrupt-parent = <&gpio4>;
- interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>;
- pinctrl-names = "default";
- pinctrl-0 = <&light_int_l>;
- vdd-supply = <&vcc3v3_s3>;
- };
-
- fusb302@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&chg_cc_int_l>;
- vbus-supply = <&vbus_typec>;
-
- typec_con: connector {
- compatible = "usb-c-connector";
- data-role = "host";
- label = "USB-C";
- op-sink-microwatt = <1000000>;
- power-role = "dual";
- sink-pdos =
- <PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
- source-pdos =
- <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
- try-power-role = "sink";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- typec_hs: endpoint {
- remote-endpoint = <&u2phy0_typec_hs>;
- };
- };
- port@1 {
- reg = <1>;
- typec_ss: endpoint {
- remote-endpoint = <&tcphy0_typec_ss>;
- };
- };
- port@2 {
- reg = <2>;
- typec_dp: endpoint {
- remote-endpoint = <&tcphy0_typec_dp>;
- };
- };
- };
- };
- };
-};
-
-&io_domains {
- status = "okay";
- bt656-supply = <&vcc_3v0>;
- audio-supply = <&vcca1v8_codec>;
- sdmmc-supply = <&vcc_sdio>;
- gpio1830-supply = <&vcc_3v0>;
-};
-
-&pmu_io_domains {
- status = "okay";
- pmu1830-supply = <&vcc_3v0>;
-};
-
-&pinctrl {
- buttons {
- pwr_btn: pwr-btn {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- gmac {
- phy_intb: phy-intb {
- rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- phy_rstb: phy-rstb {
- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- cpu_b_sleep: cpu-b-sleep {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- gpu_sleep: gpu-sleep {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- pmic_int_l: pmic-int-l {
- rockchip,pins =
- <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- sd {
- sdmmc0_pwr_h: sdmmc0-pwr-h {
- rockchip,pins =
- <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb2 {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins =
- <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc5v0_typec_en: vcc5v0-typec-en {
- rockchip,pins =
- <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_reg_on_h: wifi-reg-on-h {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wifi {
- wifi_host_wake_l: wifi-host-wake-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- bluetooth {
- bt_reg_on_h: bt-enable-h {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- mpu6500 {
- gsensor_int_l: gsensor-int-l {
- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- lsm6ds3 {
- gyr_int_l: gyr-int-l {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- cm32181 {
- light_int_l: light-int-l {
- rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- fusb302 {
- chg_cc_int_l: chg-cc-int-l {
- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- non-removable;
- status = "okay";
-};
-
-&sdio0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- clock-frequency = <50000000>;
- disable-wp;
- keep-power-in-suspend;
- max-frequency = <50000000>;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
- interrupt-names = "host-wake";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_l>;
- };
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- clock-frequency = <150000000>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
- vmmc-supply = <&vcc3v0_sd>;
- vqmmc-supply = <&vcc_sdio>;
- status = "okay";
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy0_dp {
- port {
- tcphy0_typec_dp: endpoint {
- remote-endpoint = <&typec_dp>;
- };
- };
-};
-
-&tcphy0_usb3 {
- port {
- tcphy0_typec_ss: endpoint {
- remote-endpoint = <&typec_ss>;
- };
- };
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- phy-supply = <&vbus_typec>;
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-
- port {
- u2phy0_typec_hs: endpoint {
- remote-endpoint = <&typec_hs>;
- };
- };
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- clocks = <&rk808 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
- vbat-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "host";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc;
- };
-};
-
&edp {
rockchip,panel = <&edp_panel>;
};
+&gpio0 {
+ bootph-pre-ram;
+};
+
&sdhci {
max-frequency = <25000000>;
- bootph-all;
};
&sdmmc {
max-frequency = <20000000>;
- bootph-all;
+};
+
+&sdmmc0_pwr_h_pin {
+ bootph-pre-ram;
};
&spiflash {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&vcc3v0_sd {
+ bootph-pre-ram;
};
&vdd_log {
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
- * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
- * Copyright (c) 2020 Tobias Schramm <t.schramm@manjaro.org>
- */
-
-/dts-v1/;
-#include <dt-bindings/input/gpio-keys.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/usb/pd.h>
-#include <dt-bindings/leds/common.h>
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- model = "Pine64 Pinebook Pro";
- compatible = "pine64,pinebook-pro", "rockchip,rk3399";
- chassis-type = "laptop";
-
- aliases {
- mmc0 = &sdio0;
- mmc1 = &sdmmc;
- mmc2 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- backlight: edp-backlight {
- compatible = "pwm-backlight";
- power-supply = <&vcc_12v>;
- pwms = <&pwm0 0 740740 0>;
- };
-
- bat: battery {
- compatible = "simple-battery";
- charge-full-design-microamp-hours = <9800000>;
- voltage-max-design-microvolt = <4350000>;
- voltage-min-design-microvolt = <3000000>;
- };
-
- edp_panel: edp-panel {
- compatible = "boe,nv140fhmn49";
- backlight = <&backlight>;
- enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&panel_en_pin>;
- power-supply = <&vcc3v3_panel>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- panel_in_edp: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&edp_out_panel>;
- };
- };
- };
- };
-
- /*
- * Use separate nodes for gpio-keys to allow for selective deactivation
- * of wakeup sources via sysfs without disabling the whole key
- */
- gpio-key-lid {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&lidbtn_pin>;
-
- lid {
- debounce-interval = <20>;
- gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
- label = "Lid";
- linux,code = <SW_LID>;
- linux,input-type = <EV_SW>;
- wakeup-event-action = <EV_ACT_DEASSERTED>;
- wakeup-source;
- };
- };
-
- gpio-key-power {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pwrbtn_pin>;
-
- power {
- debounce-interval = <20>;
- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "Power";
- linux,code = <KEY_POWER>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pwr_led_pin &slp_led_pin>;
-
- green_led: led-0 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "on";
- function = LED_FUNCTION_POWER;
- gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
- label = "green:power";
- };
-
- red_led: led-1 {
- color = <LED_COLOR_ID_RED>;
- default-state = "off";
- function = LED_FUNCTION_STANDBY;
- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
- label = "red:standby";
- panic-indicator;
- retain-state-suspended;
- };
- };
-
- /* Power sequence for SDIO WiFi module */
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h_pin>;
- post-power-on-delay-ms = <100>;
- power-off-delay-us = <500000>;
-
- /* WL_REG_ON on module */
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-
- /* Audio components */
- es8316-sound {
- compatible = "simple-audio-card";
- pinctrl-names = "default";
- pinctrl-0 = <&hp_det_pin>;
- simple-audio-card,name = "rockchip,es8316-codec";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
-
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Headphone", "Headphones",
- "Speaker", "Speaker";
- simple-audio-card,routing =
- "MIC1", "Mic Jack",
- "Headphones", "HPOL",
- "Headphones", "HPOR",
- "Speaker Amplifier INL", "HPOL",
- "Speaker Amplifier INR", "HPOR",
- "Speaker", "Speaker Amplifier OUTL",
- "Speaker", "Speaker Amplifier OUTR";
-
- simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
- simple-audio-card,aux-devs = <&speaker_amp>;
- simple-audio-card,pin-switches = "Speaker";
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&es8316>;
- };
- };
-
- speaker_amp: speaker-amplifier {
- compatible = "simple-audio-amplifier";
- enable-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
- sound-name-prefix = "Speaker Amplifier";
- VCC-supply = <&pa_5v>;
- };
-
- /* Power tree */
- /* Root power source */
- vcc_sysin: vcc-sysin {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sysin";
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* Regulators supplied by vcc_sysin */
- /* LCD backlight supply */
- vcc_12v: vcc-12v {
- compatible = "regulator-fixed";
- regulator-name = "vcc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- vin-supply = <&vcc_sysin>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- /* Main 3.3 V supply */
- vcc3v3_sys: wifi_bat: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_sysin>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- /* 5 V USB power supply */
- vcc5v0_usb: pa_5v: vcc5v0-usb-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwr_5v_pin>;
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_sysin>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- /* RK3399 logic supply */
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- pwm-supply = <&vcc_sysin>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- /* Regulators supplied by vcc3v3_sys */
- /* 0.9 V supply, always on */
- vcc_0v9: vcc-0v9 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- /* S3 1.8 V supply, switched by vcc1v8_s3 */
- vcca1v8_s3: vcc1v8-s3 {
- compatible = "regulator-fixed";
- regulator-name = "vcca1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- /* micro SD card power */
- vcc3v0_sd: vcc3v0-sd {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_pwr_h_pin>;
- regulator-name = "vcc3v0_sd";
- regulator-always-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- /* LCD panel power, called VCC3V3_S0 in schematic */
- vcc3v3_panel: vcc3v3-panel {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&lcdvcc_en_pin>;
- regulator-name = "vcc3v3_panel";
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-enable-ramp-delay = <100000>;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- /* M.2 adapter power, switched by vcc1v8_s3 */
- vcc3v3_ssd: vcc3v3-ssd {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_ssd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- /* Regulators supplied by vcc5v0_usb */
- /* USB 3 port power supply regulator */
- vcc5v0_otg: vcc5v0-otg {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en_pin>;
- regulator-name = "vcc5v0_otg";
- regulator-always-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- /* Regulators supplied by vcc5v0_usb */
- /* Type C port power supply regulator */
- vbus_5vout: vbus_typec: vbus-5vout {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_typec0_en_pin>;
- regulator-name = "vbus_5vout";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- /* Regulators supplied by vcc_1v8 */
- /* Primary 0.9 V LDO */
- vcca0v9_s3: vcca0v9-s3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc0v9_s3";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_1v8>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- mains_charger: dc-charger {
- compatible = "gpio-charger";
- charger-type = "mains";
- gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
-
- /* Also triggered by USB charger */
- pinctrl-names = "default";
- pinctrl-0 = <&dc_det_pin>;
- };
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&edp {
- force-hpd;
- pinctrl-names = "default";
- pinctrl-0 = <&edp_hpd>;
- status = "okay";
-
- ports {
- edp_out: port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- edp_out_panel: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&panel_in_edp>;
- };
- };
- };
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-falling-time-ns = <4>;
- i2c-scl-rising-time-ns = <168>;
- status = "okay";
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- interrupt-parent = <&gpio3>;
- interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l_pin>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc_sysin>;
- vcc2-supply = <&vcc_sysin>;
- vcc3-supply = <&vcc_sysin>;
- vcc4-supply = <&vcc_sysin>;
- vcc6-supply = <&vcc_sysin>;
- vcc7-supply = <&vcc_sysin>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc_sysin>;
- vcc10-supply = <&vcc_sysin>;
- vcc11-supply = <&vcc_sysin>;
- vcc12-supply = <&vcc3v3_sys>;
-
- regulators {
- /* rk3399 center logic supply */
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: vcc_wl: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- /* not used */
- LDO_REG1 {
- };
-
- /* not used */
- LDO_REG2 {
- };
-
- vcc1v8_pmupll: LDO_REG3 {
- regulator-name = "vcc1v8_pmupll";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sdio: LDO_REG4 {
- regulator-name = "vcc_sdio";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-name = "vcca3v0_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcca1v8_codec: LDO_REG7 {
- regulator-name = "vcca1v8_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_s3: SWITCH_REG1 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel1_pin>;
- regulator-name = "vdd_cpu_b";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- vin-supply = <&vcc_1v8>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel2_pin>;
- regulator-name = "vdd_gpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- vin-supply = <&vcc_1v8>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- i2c-scl-falling-time-ns = <4>;
- i2c-scl-rising-time-ns = <168>;
- status = "okay";
-
- es8316: es8316@11 {
- compatible = "everest,es8316";
- reg = <0x11>;
- clocks = <&cru SCLK_I2S_8CH_OUT>;
- clock-names = "mclk";
- #sound-dai-cells = <0>;
- };
-};
-
-&i2c3 {
- i2c-scl-falling-time-ns = <15>;
- i2c-scl-rising-time-ns = <450>;
- status = "okay";
-};
-
-&i2c4 {
- i2c-scl-falling-time-ns = <20>;
- i2c-scl-rising-time-ns = <600>;
- status = "okay";
-
- fusb0: fusb30x@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&fusb0_int_pin>;
- vbus-supply = <&vbus_typec>;
-
- connector {
- compatible = "usb-c-connector";
- data-role = "dual";
- label = "USB-C";
- op-sink-microwatt = <1000000>;
- power-role = "dual";
- sink-pdos =
- <PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
- source-pdos =
- <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
- try-power-role = "sink";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- usbc_hs: endpoint {
- remote-endpoint =
- <&u2phy0_typec_hs>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- usbc_ss: endpoint {
- remote-endpoint =
- <&tcphy0_typec_ss>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- usbc_dp: endpoint {
- remote-endpoint =
- <&tcphy0_typec_dp>;
- };
- };
- };
- };
- };
-
- cw2015@62 {
- compatible = "cellwise,cw2015";
- reg = <0x62>;
- cellwise,battery-profile = /bits/ 8 <
- 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63
- 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36
- 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69
- 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59
- 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17
- 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D
- 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB
- 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11
- >;
- cellwise,monitor-interval-ms = <5000>;
- monitored-battery = <&bat>;
- power-supplies = <&mains_charger>, <&fusb0>;
- };
-};
-
-&i2s1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s1_2ch_bus>;
- rockchip,capture-channels = <8>;
- rockchip,playback-channels = <8>;
- status = "okay";
-};
-
-&io_domains {
- audio-supply = <&vcc_3v0>;
- gpio1830-supply = <&vcc_3v0>;
- sdmmc-supply = <&vcc_sdio>;
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- bus-scan-delay-ms = <1000>;
- ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn_cpm>;
- vpcie0v9-supply = <&vcca0v9_s3>;
- vpcie1v8-supply = <&vcca1v8_s3>;
- vpcie3v3-supply = <&vcc3v3_ssd>;
- status = "okay";
-};
-
-&pinctrl {
- buttons {
- pwrbtn_pin: pwrbtn-pin {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- lidbtn_pin: lidbtn-pin {
- rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- dc-charger {
- dc_det_pin: dc-det-pin {
- rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- es8316 {
- hp_det_pin: hp-det-pin {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- fusb302x {
- fusb0_int_pin: fusb0-int-pin {
- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- i2s1 {
- i2s_8ch_mclk_pin: i2s-8ch-mclk-pin {
- rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
- };
- };
-
- lcd-panel {
- lcdvcc_en_pin: lcdvcc-en-pin {
- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- panel_en_pin: panel-en-pin {
- rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- lcd_panel_reset_pin: lcd-panel-reset-pin {
- rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- leds {
- pwr_led_pin: pwr-led-pin {
- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- slp_led_pin: slp-led-pin {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l_pin: pmic-int-l-pin {
- rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- vsel1_pin: vsel1-pin {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- vsel2_pin: vsel2-pin {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- sdcard {
- sdmmc0_pwr_h_pin: sdmmc0-pwr-h-pin {
- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- };
-
- sdio-pwrseq {
- wifi_enable_h_pin: wifi-enable-h-pin {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb-typec {
- vcc5v0_typec0_en_pin: vcc5v0-typec0-en-pin {
- rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- pwr_5v_pin: pwr-5v-pin {
- rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc5v0_host_en_pin: vcc5v0-host-en-pin {
- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wireless-bluetooth {
- bt_wake_pin: bt-wake-pin {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_pin: bt-host-wake-pin {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_reset_pin: bt-reset-pin {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmu1830-supply = <&vcc_3v0>;
- status = "okay";
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v0_sd>;
- vqmmc-supply = <&vcc_sdio>;
- status = "okay";
-};
-
-&sdio0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- status = "okay";
-};
-
-&spi1 {
- max-freq = <10000000>;
- status = "okay";
-
- spiflash: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- m25p,fast-read;
- spi-max-frequency = <10000000>;
- };
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy0_dp {
- port {
- tcphy0_typec_dp: endpoint {
- remote-endpoint = <&usbc_dp>;
- };
- };
-};
-
-&tcphy0_usb3 {
- port {
- tcphy0_typec_ss: endpoint {
- remote-endpoint = <&usbc_ss>;
- };
- };
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vcc5v0_otg>;
- status = "okay";
- };
-
- port {
- u2phy0_typec_hs: endpoint {
- remote-endpoint = <&usbc_hs>;
- };
- };
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_otg>;
- status = "okay";
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4345c5";
- clocks = <&rk808 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- max-speed = <1500000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>;
- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- vbat-supply = <&wifi_bat>;
- vddio-supply = <&vcc_wl>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- dr_mode = "host";
- status = "okay";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
- };
-};
-
-&rng {
- status = "okay";
-};
-
&sdhci {
max-frequency = <25000000>;
- bootph-all;
};
&sdmmc {
max-frequency = <20000000>;
- bootph-all;
+};
+
+&spi1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ spi-max-frequency = <10000000>;
+ };
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Martijn Braam <martijn@brixit.nl>
- * Copyright (c) 2021 Kamil Trzciński <ayufan@ayufan.eu>
- */
-
-/*
- * PinePhone Pro datasheet:
- * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf
- */
-
-/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- model = "Pine64 PinePhonePro";
- compatible = "pine64,pinephone-pro", "rockchip,rk3399";
- chassis-type = "handset";
-
- aliases {
- mmc0 = &sdio0;
- mmc1 = &sdmmc;
- mmc2 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pwrbtn_pin>;
-
- key-power {
- debounce-interval = <20>;
- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "Power";
- linux,code = <KEY_POWER>;
- wakeup-source;
- };
- };
-
- vcc_sys: vcc-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc3v3_sys: vcc3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_sys>;
- };
-
- vcca1v8_s3: vcc1v8-s3-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcca1v8_s3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc3v3_sys>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc1v8_codec: vcc1v8-codec-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc1v8_codec_en>;
- regulator-name = "vcc1v8_codec";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- wifi_pwrseq: sdio-wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk818 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h_pin>;
- /*
- * Wait between power-on and SDIO access for CYP43455
- * POR circuit.
- */
- post-power-on-delay-ms = <110>;
- /*
- * Wait between consecutive toggles for CYP43455 CBUCK
- * regulator discharge.
- */
- power-off-delay-us = <10000>;
-
- /* WL_REG_ON on module */
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- status = "okay";
-
- rk818: pmic@1c {
- compatible = "rockchip,rk818";
- reg = <0x1c>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc6-supply = <&vcc_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc_sys>;
- vcc9-supply = <&vcc3v3_sys>;
-
- regulators {
- vdd_cpu_l: DCDC_REG1 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <875000>;
- regulator-max-microvolt = <975000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_center: DCDC_REG2 {
- regulator-name = "vdd_center";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1000000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcca3v0_codec: LDO_REG1 {
- regulator-name = "vcca3v0_codec";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- vcc3v0_touch: LDO_REG2 {
- regulator-name = "vcc3v0_touch";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- vcca1v8_codec: LDO_REG3 {
- regulator-name = "vcca1v8_codec";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- rk818_pwr_on: LDO_REG4 {
- regulator-name = "rk818_pwr_on";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG5 {
- regulator-name = "vcc_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc1v8_dvp: LDO_REG7 {
- regulator-name = "vcc1v8_dvp";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vcc3v3_s3: LDO_REG8 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG9 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vcc3v3_s0: SWITCH_REG {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel1_pin>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <875000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel2_pin>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <875000>;
- regulator-max-microvolt = <975000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&cluster0_opp {
- opp04 {
- status = "disabled";
- };
-
- opp05 {
- status = "disabled";
- };
-};
-
-&cluster1_opp {
- opp06 {
- opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <1100000 1100000 1150000>;
- };
-
- opp07 {
- status = "disabled";
- };
-};
-
-&io_domains {
- bt656-supply = <&vcc1v8_dvp>;
- audio-supply = <&vcca1v8_codec>;
- sdmmc-supply = <&vccio_sd>;
- gpio1830-supply = <&vcc_3v0>;
- status = "okay";
-};
-
-&pmu_io_domains {
- pmu1830-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&pinctrl {
- buttons {
- pwrbtn_pin: pwrbtn-pin {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- vsel1_pin: vsel1-pin {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- vsel2_pin: vsel2-pin {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h_pin: wifi-enable-h-pin {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sound {
- vcc1v8_codec_en: vcc1v8-codec-en {
- rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- wireless-bluetooth {
- bt_wake_pin: bt-wake-pin {
- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_pin: bt-host-wake-pin {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_reset_pin: bt-reset-pin {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdio0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- disable-wp;
- keep-power-in-suspend;
- mmc-pwrseq = <&wifi_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
- vmmc-supply = <&vcc3v3_sys>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4345c5";
- clocks = <&rk818 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- max-speed = <1500000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>;
- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- vbat-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
aliases {
spi5 = &spi5;
};
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-init-microvolt = <950000>;
- vin-supply = <&vcc5v0_sys>;
- };
};
&binman {
};
&norflash {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
-&pcfg_pull_none {
+&uart0 {
bootph-all;
+ clock-frequency = <24000000>;
};
-&pcfg_pull_up {
- bootph-all;
+&uart0_cts {
+ bootph-pre-sram;
+ bootph-pre-ram;
};
-&sdmmc_bus4 {
- bootph-all;
+&uart0_rts {
+ bootph-pre-sram;
+ bootph-pre-ram;
};
-&sdmmc_clk {
- bootph-all;
+&uart0_xfer {
+ bootph-pre-sram;
+ bootph-pre-ram;
};
-&sdmmc_cmd {
- bootph-all;
+&vdd_log {
+ regulator-init-microvolt = <950000>;
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-/dts-v1/;
-#include "rk3399-puma.dtsi"
-
-/ {
- model = "Theobroma Systems RK3399-Q7 SoM";
- compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399";
-
- aliases {
- mmc1 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
-
- sd_card_led: led-1 {
- label = "sd_card_led";
- gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- };
- };
-
- i2s0-sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,name = "Haikou,I2S-codec";
- simple-audio-card,mclk-fs = <512>;
-
- simple-audio-card,codec {
- clocks = <&sgtl5000_clk>;
- sound-dai = <&sgtl5000>;
- };
-
- simple-audio-card,cpu {
- bitclock-master;
- frame-master;
- sound-dai = <&i2s0>;
- };
- };
-
- sgtl5000_clk: sgtl5000-oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- dc_12v: dc-12v {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc3v3_baseboard: vcc3v3-baseboard {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_baseboard";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_baseboard: vcc5v0-baseboard {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_baseboard";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_otg: vcc5v0-otg-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&otg_vbus_drv>;
- regulator-name = "vcc5v0_otg";
- regulator-always-on;
- };
-
- vdda_codec: vdda-codec {
- compatible = "regulator-fixed";
- regulator-name = "vdda_codec";
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_baseboard>;
- };
-
- vddd_codec: vddd-codec {
- compatible = "regulator-fixed";
- regulator-name = "vddd_codec";
- regulator-boot-on;
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <1600000>;
- vin-supply = <&vcc5v0_baseboard>;
- };
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c3>;
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
- clock-frequency = <400000>;
-};
-
-&i2c2 {
- status = "okay";
- clock-frequency = <400000>;
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c4 {
- status = "okay";
- clock-frequency = <400000>;
-
- sgtl5000: codec@a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- clocks = <&sgtl5000_clk>;
- #sound-dai-cells = <0>;
- VDDA-supply = <&vdda_codec>;
- VDDIO-supply = <&vdda_codec>;
- VDDD-supply = <&vddd_codec>;
- status = "okay";
- };
-};
-
-&i2c6 {
- status = "okay";
- clock-frequency = <400000>;
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn_cpm>;
- status = "okay";
-};
-
-&pinctrl {
- pinctrl-names = "default";
- pinctrl-0 = <&haikou_pin_hog>;
-
- hog {
- haikou_pin_hog: haikou-pin-hog {
- rockchip,pins =
- /* LID_BTN */
- <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
- /* BATLOW# */
- <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
- /* SLP_BTN# */
- <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
- /* BIOS_DISABLE# */
- <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- leds {
- sd_card_led_pin: sd-card-led-pin {
- rockchip,pins =
- <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb2 {
- otg_vbus_drv: otg-vbus-drv {
- rockchip,pins =
- <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <40000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
- vmmc-supply = <&vcc3v3_baseboard>;
- status = "okay";
-};
-
-&spi5 {
- status = "okay";
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- dr_mode = "otg";
- extcon = <&extcon_usb3>;
- status = "okay";
-};
-
-&u2phy0_host {
- phy-supply = <&vcc5v0_otg>;
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-#include <dt-bindings/pwm/pwm.h>
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- aliases {
- mmc0 = &sdhci;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&module_led_pin>;
-
- module_led: led-0 {
- label = "module_led";
- gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- panic-indicator;
- };
- };
-
- extcon_usb3: extcon-usb3 {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb3_id>;
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- vcc1v2_phy: vcc1v2-phy {
- compatible = "regulator-fixed";
- regulator-name = "vcc1v2_phy";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- pwm-supply = <&vcc5v0_sys>;
- regulator-name = "vdd_log";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-always-on;
- regulator-boot-on;
- };
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&emmc_phy {
- status = "okay";
- drive-impedance-ohm = <33>;
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc1v2_phy>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x10>;
- rx_delay = <0x10>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- clock-frequency = <400000>;
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio1>;
- interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc5v0_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc1v8_pmu>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_ldo1: LDO_REG1 {
- regulator-name = "vcc_ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_hdmi: LDO_REG2 {
- regulator-name = "vcc1v8_hdmi";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_pmu: LDO_REG3 {
- regulator-name = "vcc1v8_pmu";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sd: LDO_REG4 {
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc_ldo5: LDO_REG5 {
- regulator-name = "vcc_ldo5";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ldo6: LDO_REG6 {
- regulator-name = "vcc_ldo6";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc0v9_hdmi: LDO_REG7 {
- regulator-name = "vcc0v9_hdmi";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_efuse: LDO_REG8 {
- regulator-name = "vcc_efuse";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_s3: SWITCH_REG1 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_gpu: regulator@60 {
- compatible = "fcs,fan53555";
- reg = <0x60>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1230000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&i2c7 {
- status = "okay";
- clock-frequency = <400000>;
-
- fan: fan@18 {
- compatible = "ti,amc6821";
- reg = <0x18>;
- #cooling-cells = <2>;
- };
-
- rtc_twi: rtc@6f {
- compatible = "isil,isl1208";
- reg = <0x6f>;
- };
-};
-
-&i2c8 {
- status = "okay";
- clock-frequency = <400000>;
-
- vdd_cpu_b: regulator@60 {
- compatible = "fcs,fan53555";
- reg = <0x60>;
- vin-supply = <&vcc5v0_sys>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1230000>;
- regulator-ramp-delay = <1000>;
- fcs,suspend-voltage-selector = <1>;
- regulator-always-on;
- regulator-boot-on;
- };
-};
-
-&i2s0 {
- pinctrl-0 = <&i2s0_2ch_bus>;
- rockchip,playback-channels = <2>;
- rockchip,capture-channels = <2>;
- status = "okay";
-};
-
-/*
- * As Q7 does not specify neither a global nor a RX clock for I2S these
- * signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO.
- * Therefore we have to redefine the i2s0_2ch_bus definition to prevent
- * conflicts.
- */
-&i2s0_2ch_bus {
- rockchip,pins =
- <3 RK_PD0 1 &pcfg_pull_none>,
- <3 RK_PD2 1 &pcfg_pull_none>,
- <3 RK_PD3 1 &pcfg_pull_none>,
- <3 RK_PD7 1 &pcfg_pull_none>;
-};
-
-&io_domains {
- status = "okay";
- bt656-supply = <&vcc_1v8>;
- audio-supply = <&vcc_1v8>;
- sdmmc-supply = <&vcc_sd>;
- gpio1830-supply = <&vcc_1v8>;
-};
-
-&pmu_io_domains {
- status = "okay";
- pmu1830-supply = <&vcc_1v8>;
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&pinctrl {
- i2c8 {
- i2c8_xfer_a: i2c8-xfer {
- rockchip,pins =
- <1 RK_PC4 1 &pcfg_pull_up>,
- <1 RK_PC5 1 &pcfg_pull_up>;
- };
- };
-
- leds {
- module_led_pin: module-led-pin {
- rockchip,pins =
- <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins =
- <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins =
- <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb3 {
- usb3_id: usb3-id {
- rockchip,pins =
- <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdhci {
- /*
- * Signal integrity isn't great at 200MHz but 100MHz has proven stable
- * enough.
- */
- max-frequency = <100000000>;
-
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- non-removable;
- status = "okay";
-};
-
-&sdmmc {
- vqmmc-supply = <&vcc_sd>;
-};
-
-&spi1 {
- status = "okay";
-
- norflash: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- };
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
- * Copyright (c) 2019 Markus Reichl <m.reichl@fivetechno.de>
- */
-
-/dts-v1/;
-#include "rk3399-roc-pc.dtsi"
-
-/ {
- model = "Firefly ROC-RK3399-PC Mezzanine Board";
- compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
-
- aliases {
- mmc2 = &sdio0;
- };
-
- /* MP8009 PoE PD */
- poe_12v: poe-12v {
- compatible = "regulator-fixed";
- regulator-name = "poe_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc3v3_ngff: vcc3v3-ngff {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_ngff";
- enable-active-high;
- gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc3v3_ngff_en>;
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&sys_12v>;
- };
-
- vcc3v3_pcie: vcc3v3-pcie {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie";
- enable-active-high;
- gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc3v3_pcie_en>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&sys_12v>;
- };
-};
-
-&sys_12v {
- vin-supply = <&poe_12v>;
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_perst>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
- vpcie1v8-supply = <&vcc1v8_pmu>;
- vpcie0v9-supply = <&vcca_0v9>;
- status = "okay";
-};
-
-&pinctrl {
- ngff {
- vcc3v3_ngff_en: vcc3v3-ngff-en {
- rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- vcc3v3_pcie_en: vcc3v3-pcie-en {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_perst: pcie-perst {
- rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdio0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_ngff>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- status = "okay";
-};
#include "rk3399-sdram-lpddr4-100.dtsi"
/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdhci, &sdmmc;
- };
-
vcc_hub_en: vcc_hub_en-regulator {
compatible = "regulator-fixed";
enable-active-high;
vin-supply = <&vcc_vbus_typec0>;
};
+&gpio4 {
+ bootph-pre-ram;
+};
+
&spi1 {
- spi_flash: flash@0 {
- bootph-all;
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
};
};
-&vdd_log {
- regulator-min-microvolt = <430000>;
- regulator-init-microvolt = <950000>;
+&vcc3v0_sd {
+ bootph-pre-ram;
+};
+
+&vcc3v0_sd_en {
+ bootph-pre-ram;
};
&vcc5v0_host {
regulator-always-on;
};
-&vcc_sys {
+&vcc_sdio {
regulator-always-on;
};
-&vcc_sdio {
+&vcc_sys {
regulator-always-on;
};
+
+&vdd_log {
+ regulator-min-microvolt = <430000>;
+ regulator-init-microvolt = <950000>;
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
- */
-
-/dts-v1/;
-#include "rk3399-roc-pc.dtsi"
-
-/ {
- model = "Firefly ROC-RK3399-PC Board";
- compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
- */
-
-/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/pwm/pwm.h>
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- model = "Firefly ROC-RK3399-PC Board";
- compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
-
- aliases {
- mmc0 = &sdmmc;
- mmc1 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm0 0 25000 0>;
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 1>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1500000>;
- poll-interval = <100>;
-
- recovery {
- label = "Recovery";
- linux,code = <KEY_VENDOR>;
- press-threshold-microvolt = <18000>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&pwr_key_l>;
-
- power {
- debounce-interval = <100>;
- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "GPIO Key Power";
- linux,code = <KEY_POWER>;
- wakeup-source;
- };
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&ir_int>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&work_led_pin>, <&diy_led_pin>, <&yellow_led_pin>;
-
- work_led: led-0 {
- label = "green:work";
- gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- diy_led: led-1 {
- label = "red:diy";
- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- linux,default-trigger = "mmc2";
- };
-
- yellow_led: led-2 {
- label = "yellow:yellow-led";
- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- linux,default-trigger = "mmc1";
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
-
- /*
- * On the module itself this is one of these (depending
- * on the actual card populated):
- * - SDIO_RESET_L_WL_REG_ON
- * - PDN (power down when low)
- */
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-
- vcc_vbus_typec0: vcc-vbus-typec0 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_vbus_typec0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- sys_12v: sys-12v {
- compatible = "regulator-fixed";
- regulator-name = "sys_12v";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&dc_12v>;
- };
-
- /* switched by pmic_sleep */
- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_1v8>;
- };
-
- vcc3v0_sd: vcc3v0-sd {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc3v0_sd_en>;
- regulator-name = "vcc3v0_sd";
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&sys_12v>;
- };
-
- vcca_0v9: vcca-0v9 {
- compatible = "regulator-fixed";
- regulator-name = "vcca_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en &hub_rst>;
- regulator-name = "vcc5v0_host";
- vin-supply = <&vcc_sys>;
- };
-
- vcc_vbus_typec1: vcc-vbus-typec1 {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc_vbus_typec1_en>;
- regulator-name = "vcc_vbus_typec1";
- regulator-always-on;
- vin-supply = <&vcc_sys>;
- };
-
- vcc_sys: vcc-sys {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc_sys_en>;
- regulator-name = "vcc_sys";
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&sys_12v>;
- };
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <450000>;
- regulator-max-microvolt = <1400000>;
- pwm-supply = <&vcc3v3_sys>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc_lan>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c3>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- status = "okay";
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio1>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- vcc10-supply = <&vcc3v3_sys>;
- vcc11-supply = <&vcc3v3_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vcc13-supply = <&vcc3v3_sys>;
- vcc14-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_3v0>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_codec: LDO_REG1 {
- regulator-name = "vcca1v8_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_hdmi: LDO_REG2 {
- regulator-name = "vcc1v8_hdmi";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_pmu: LDO_REG3 {
- regulator-name = "vcc1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sdio: LDO_REG4 {
- regulator-name = "vcc_sdio";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-name = "vcca3v0_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcca0v9_hdmi: LDO_REG7 {
- regulator-name = "vcca0v9_hdmi";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_s3: vcc_lan: SWITCH_REG1 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel1_pin>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel2_pin>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c1 {
- i2c-scl-rising-time-ns = <300>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c4 {
- i2c-scl-rising-time-ns = <600>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- fusb1: usb-typec@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio1>;
- interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&fusb1_int>;
- vbus-supply = <&vcc_vbus_typec1>;
- status = "okay";
- };
-};
-
-&i2c7 {
- i2c-scl-rising-time-ns = <600>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- fusb0: usb-typec@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio1>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&fusb0_int>;
- vbus-supply = <&vcc_vbus_typec0>;
- status = "okay";
- };
-
- mp8859: regulator@66 {
- compatible = "mps,mp8859";
- reg = <0x66>;
- dc_12v: mp8859_dcdc {
- regulator-name = "dc_12v";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_vbus_typec0>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <12000000>;
- };
- };
- };
-};
-
-&i2s0 {
- rockchip,playback-channels = <8>;
- rockchip,capture-channels = <8>;
- status = "okay";
-};
-
-&i2s1 {
- rockchip,playback-channels = <2>;
- rockchip,capture-channels = <2>;
- status = "okay";
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- audio-supply = <&vcca1v8_codec>;
- bt656-supply = <&vcc_3v0>;
- gpio1830-supply = <&vcc_3v0>;
- sdmmc-supply = <&vcc_sdio>;
- status = "okay";
-};
-
-&pmu_io_domains {
- pmu1830-supply = <&vcc_3v0>;
- status = "okay";
-};
-
-&pinctrl {
- buttons {
- pwr_key_l: pwr-key-l {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- ir {
- ir_int: ir-int {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- lcd-panel {
- lcd_panel_reset: lcd-panel-reset {
- rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- leds {
- diy_led_pin: diy-led-pin {
- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- work_led_pin: work-led-pin {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- yellow_led_pin: yellow-led-pin {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- vsel1_pin: vsel1-pin {
- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- vsel2_pin: vsel2-pin {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdmmc {
- vcc3v0_sd_en: vcc3v0-sd-en {
- rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc_sys_en: vcc-sys-en {
- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- hub_rst: hub-rst {
- rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>;
- };
- };
-
- usb-typec {
- vcc_vbus_typec1_en: vcc-vbus-typec1-en {
- rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- fusb30x {
- fusb0_int: fusb0-int {
- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- fusb1_int: fusb1-int {
- rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v0_sd>;
- vqmmc-supply = <&vcc_sdio>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
- };
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- phy-supply = <&vcc_vbus_typec0>;
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- phy-supply = <&vcc_vbus_typec1>;
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
* Copyright (c) 2023 Radxa Limited
*/
#include "rk3399-rock-pi-4-u-boot.dtsi"
+
+&pcfg_pull_none_18ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pcfg_pull_up_8ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&spi1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ spi-max-frequency = <10000000>;
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2019 Radxa Limited
- * Copyright (c) 2022 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include <dt-bindings/leds/common.h>
-#include "rk3399.dtsi"
-#include "rk3399-t-opp.dtsi"
-
-/ {
- model = "Radxa ROCK 4C+";
- compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
-
- aliases {
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&user_led1 &user_led2>;
-
- /* USER_LED1 */
- led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "default-on";
- };
-
- /* USER_LED2 */
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk809 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-
- vcc_3v3: vcc-3v3-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- vcc3v3_phy1: vcc3v3-phy1-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_phy1";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_3v3>;
- };
-
- vcc5v0_host1: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- regulator-name = "vcc5v0_host1";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_host0_s0>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc5v0_typec: vcc5v0-typec-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_typec0_en>;
- regulator-name = "vcc5v0_typec";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vdd_log: vdd-log-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <950000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc3v3_phy1>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x2a>;
- rx_delay = <0x21>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vcc_0v9_s0>;
- avdd-1v8-supply = <&vcc_1v8_s0>;
- ddc-i2c-bus = <&i2c3>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
- i2c-scl-falling-time-ns = <30>;
- i2c-scl-rising-time-ns = <180>;
- clock-frequency = <400000>;
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc_buck5_s3>;
- vcc6-supply = <&vcc_buck5_s3>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-initial-mode = <0x2>;
- regulator-name = "vdd_center";
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-initial-mode = <0x2>;
- regulator-name = "vdd_cpu_l";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vcc_ddr";
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc3v3_sys: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-initial-mode = <0x2>;
- regulator-name = "vcc3v3_sys";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_buck5_s3: DCDC_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_buck5_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_0v9_s3: LDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vcc_0v9_s3";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s3: LDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_0v9_s0: LDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vcc_0v9_s0";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vcc_1v8_s0: LDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_mipi: LDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "vcc_mipi";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5_s0: LDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vcc_1v5_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0_s0: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "vcc_3v0_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_sdio_s0: LDO_REG8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_sdio_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_cam: LDO_REG9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_cam";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc5v0_host0_s0: SWITCH_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vcc5v0_host0_s0";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- lcd_3v3: SWITCH_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "lcd_3v3";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- regulator-compatible = "fan53555-reg";
- pinctrl-0 = <&vsel1_gpio>;
- vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- regulator-compatible = "fan53555-reg";
- pinctrl-0 = <&vsel2_gpio>;
- vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- regulator-initial-mode = <1>; /* 1:force PWM 2:auto */
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- audio-supply = <&vcc_1v8_s0>;
- bt656-supply = <&vcc_3v0_s0>;
- gpio1830-supply = <&vcc_3v0_s0>;
- sdmmc-supply = <&vcc_sdio_s0>;
- status = "okay";
-};
-
-&pinctrl {
- bt {
- bt_enable_h: bt-enable-h {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- leds {
- user_led1: user-led1 {
- rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- user_led2: user-led2 {
- rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- vsel1_gpio: vsel1-gpio {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- vsel2_gpio: vsel2-gpio {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- sdmmc {
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins = <4 8 1 &pcfg_pull_up_8ma>,
- <4 9 1 &pcfg_pull_up_8ma>,
- <4 10 1 &pcfg_pull_up_8ma>,
- <4 11 1 &pcfg_pull_up_8ma>;
- };
-
- sdmmc_clk: sdmmc-clk {
- rockchip,pins = <4 12 1 &pcfg_pull_none_18ma>;
- };
-
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins = <4 13 1 &pcfg_pull_up_8ma>;
- };
- };
-
- usb-typec {
- vcc5v0_typec0_en: vcc5v0-typec-en {
- rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- wifi {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wifi_host_wake_l: wifi-host-wake-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmu1830-supply = <&vcc_3v0_s0>;
- status = "okay";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vcc_1v8_s3>;
-};
-
-&sdhci {
- max-frequency = <150000000>;
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- status = "okay";
-};
-
-&sdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- bus-width = <4>;
- clock-frequency = <50000000>;
- cap-sdio-irq;
- cap-sd-highspeed;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_l>;
- };
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <800>;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&vcc_sdio_s0>;
- status = "okay";
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vcc5v0_host1>;
- status = "okay";
- };
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_host1>;
- status = "okay";
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4345c5";
- clocks = <&rk809 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- max-speed = <1500000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
- vbat-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8_s3>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- extcon = <&u2phy0>;
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "host";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
*/
#include "rk3399-rock-pi-4-u-boot.dtsi"
+
+&spi1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ spi-max-frequency = <10000000>;
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
- * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
- */
-
-/dts-v1/;
-#include "rk3399-rock-pi-4.dtsi"
-#include "rk3399-t-opp.dtsi"
-
-/ {
- model = "Radxa ROCK 4SE";
- compatible = "radxa,rock-4se", "rockchip,rk3399";
-
- aliases {
- mmc2 = &sdio0;
- };
-};
-
-&pinctrl {
- usb2 {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdio0 {
- status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_l>;
- };
-};
-
-&uart0 {
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4345c5";
- clocks = <&rk808 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- max-speed = <1500000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
- vbat-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
- };
-};
-
-&vcc5v0_host {
- enable-active-high;
- gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
-};
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
- };
-};
-
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
- * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
- */
-
-/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pwm/pwm.h>
-#include "rk3399.dtsi"
-
-/ {
- aliases {
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&user_led2>;
-
- /* USER_LED2 */
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-
- sound: sound {
- compatible = "audio-graph-card";
- label = "Analog";
- dais = <&i2s0_p0>;
- };
-
- sound-dit {
- compatible = "audio-graph-card";
- label = "SPDIF";
- dais = <&spdif_p0>;
- };
-
- spdif-dit {
- compatible = "linux,spdif-dit";
- #sound-dai-cells = <0>;
-
- port {
- dit_p0_0: endpoint {
- remote-endpoint = <&spdif_p0_0>;
- };
- };
- };
-
- vbus_typec: vbus-typec-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_typec_en>;
- regulator-name = "vbus_typec";
- regulator-always-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc12v_dcin: dc-12v {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc3v3_lan: vcc3v3-lan-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_lan";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- vcc3v3_pcie: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pwr_en>;
- regulator-name = "vcc3v3_pcie";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_sys: vcc-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc_0v9: vcc-0v9 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- pwm-supply = <&vcc5v0_sys>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc3v3_lan>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vcca0v9_hdmi>;
- avdd-1v8-supply = <&vcca1v8_hdmi>;
- ddc-i2c-bus = <&i2c3>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- status = "okay";
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio1>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc5v0_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_codec: LDO_REG1 {
- regulator-name = "vcca1v8_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_hdmi: LDO_REG2 {
- regulator-name = "vcca1v8_hdmi";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca_1v8: LDO_REG3 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sdio: LDO_REG4 {
- regulator-name = "vcc_sdio";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-name = "vcca3v0_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcca0v9_hdmi: LDO_REG7 {
- regulator-name = "vcca0v9_hdmi";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc_cam: SWITCH_REG1 {
- regulator-name = "vcc_cam";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_mipi: SWITCH_REG2 {
- regulator-name = "vcc_mipi";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel1_pin>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel2_pin>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c1 {
- i2c-scl-rising-time-ns = <300>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-
- es8316: codec@11 {
- compatible = "everest,es8316";
- reg = <0x11>;
- clocks = <&cru SCLK_I2S_8CH_OUT>;
- clock-names = "mclk";
- #sound-dai-cells = <0>;
-
- port {
- es8316_p0_0: endpoint {
- remote-endpoint = <&i2s0_p0_0>;
- };
- };
- };
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c4 {
- i2c-scl-rising-time-ns = <600>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-};
-
-&i2s0 {
- pinctrl-0 = <&i2s0_2ch_bus>;
- rockchip,capture-channels = <2>;
- rockchip,playback-channels = <2>;
- status = "okay";
-
- i2s0_p0: port {
- i2s0_p0_0: endpoint {
- dai-format = "i2s";
- mclk-fs = <256>;
- remote-endpoint = <&es8316_p0_0>;
- };
- };
-};
-
-&i2s1 {
- rockchip,playback-channels = <2>;
- rockchip,capture-channels = <2>;
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- audio-supply = <&vcca1v8_codec>;
- bt656-supply = <&vcc_3v0>;
- gpio1830-supply = <&vcc_3v0>;
- sdmmc-supply = <&vcc_sdio>;
- status = "okay";
-};
-
-&pcie0 {
- ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-0 = <&pcie_clkreqnb_cpm>;
- pinctrl-names = "default";
- vpcie0v9-supply = <&vcc_0v9>;
- vpcie1v8-supply = <&vcc_1v8>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pinctrl {
- bt {
- bt_enable_h: bt-enable-h {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- es8316 {
- hp_detect: hp-detect {
- rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- hp_int: hp-int {
- rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- leds {
- user_led2: user-led2 {
- rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- pcie_pwr_en: pcie-pwr-en {
- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- vsel1_pin: vsel1-pin {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- vsel2_pin: vsel2-pin {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- sdio0 {
- sdio0_bus4: sdio0-bus4 {
- rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>,
- <2 RK_PC5 1 &pcfg_pull_up_20ma>,
- <2 RK_PC6 1 &pcfg_pull_up_20ma>,
- <2 RK_PC7 1 &pcfg_pull_up_20ma>;
- };
-
- sdio0_cmd: sdio0-cmd {
- rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>;
- };
-
- sdio0_clk: sdio0-clk {
- rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>;
- };
- };
-
- usb-typec {
- vcc5v0_typec_en: vcc5v0-typec-en {
- rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wifi {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wifi_host_wake_l: wifi-host-wake-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmu1830-supply = <&vcc_3v0>;
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-
- vref-supply = <&vcc_1v8>;
-};
-
-&sdhci {
- max-frequency = <150000000>;
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- status = "okay";
-};
-
-&sdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- bus-width = <4>;
- clock-frequency = <50000000>;
- cap-sdio-irq;
- cap-sd-highspeed;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
- status = "okay";
-};
-
-&spdif {
-
- spdif_p0: port {
- spdif_p0_0: endpoint {
- remote-endpoint = <&dit_p0_0>;
- };
- };
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- status = "okay";
-
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "host";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
- * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
- */
-
-/dts-v1/;
-#include "rk3399-rock-pi-4.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- model = "Radxa ROCK Pi 4A";
- compatible = "radxa,rockpi4a", "radxa,rockpi4", "rockchip,rk3399";
-};
-
-&spi1 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
- };
-};
*/
#include "rk3399-rock-pi-4-u-boot.dtsi"
+
+&spi1 {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2019 Radxa Limited
- * Copyright (c) 2019 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include "rk3399-rock-pi-4.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- model = "Radxa ROCK Pi 4C";
- compatible = "radxa,rockpi4c", "radxa,rockpi4", "rockchip,rk3399";
-
- aliases {
- mmc2 = &sdio0;
- };
-};
-
-&es8316 {
- pinctrl-0 = <&hp_detect &hp_int>;
- pinctrl-names = "default";
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PA1 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&sdio0 {
- status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_l>;
- };
-};
-
-&sound {
- hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
-};
-
-&uart0 {
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4345c5";
- clocks = <&rk808 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- max-speed = <1500000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
- vbat-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
- };
-};
-
-&vcc5v0_host {
- gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
-};
-
-&vcc5v0_host_en {
- rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-};
#include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
- };
-
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-init-microvolt = <950000>;
vin-supply = <&vcc5v0_sys>;
};
+};
+
+&pcfg_pull_none_18ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+&pcfg_pull_up_8ma {
+ bootph-pre-ram;
+ bootph-some-ram;
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2018 Linaro Ltd.
- */
-
-/dts-v1/;
-#include "rk3399-rock960.dtsi"
-
-/ {
- model = "96boards Rock960";
- compatible = "vamrs,rock960", "rockchip,rk3399";
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>,
- <&user_led3_pin>, <&user_led4_pin>,
- <&wlan_led_pin>, <&bt_led_pin>;
-
- user_led1: led-1 {
- label = "green:user1";
- gpios = <&gpio4 RK_PC2 0>;
- linux,default-trigger = "heartbeat";
- };
-
- user_led2: led-2 {
- label = "green:user2";
- gpios = <&gpio4 RK_PC6 0>;
- linux,default-trigger = "mmc0";
- };
-
- user_led3: led-3 {
- label = "green:user3";
- gpios = <&gpio4 RK_PD0 0>;
- linux,default-trigger = "mmc1";
- };
-
- user_led4: led-4 {
- label = "green:user4";
- gpios = <&gpio4 RK_PD4 0>;
- panic-indicator;
- linux,default-trigger = "none";
- };
-
- wlan_active_led: led-5 {
- label = "yellow:wlan";
- gpios = <&gpio4 RK_PD5 0>;
- linux,default-trigger = "phy0tx";
- default-state = "off";
- };
-
- bt_active_led: led-6 {
- label = "blue:bt";
- gpios = <&gpio4 RK_PD6 0>;
- linux,default-trigger = "hci0-power";
- default-state = "off";
- };
- };
-
-};
-
-&cpu_alert0 {
- temperature = <65000>;
-};
-
-&cpu_thermal {
- sustainable-power = <1550>;
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert1>;
- };
- };
-};
-
-&pcie0 {
- ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
-};
-
-&pinctrl {
- leds {
- user_led1_pin: user-led1-pin {
- rockchip,pins =
- <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- user_led2_pin: user-led2-pin {
- rockchip,pins =
- <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- user_led3_pin: user-led3-pin {
- rockchip,pins =
- <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- user_led4_pin: user-led4-pin {
- rockchip,pins =
- <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wlan_led_pin: wlan-led-pin {
- rockchip,pins =
- <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_led_pin: bt-led-pin {
- rockchip,pins =
- <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- pcie_drv: pcie-drv {
- rockchip,pins =
- <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb2 {
- host_vbus_drv: host-vbus-drv {
- rockchip,pins =
- <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&spi0 {
- /* On Low speed expansion (LS-SPI0) */
- status = "okay";
-};
-
-&spi4 {
- /* On High speed expansion (HS-SPI1) */
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- dr_mode = "otg";
-};
-
-&usbdrd_dwc3_1 {
- dr_mode = "host";
-};
-
-&vcc3v3_pcie {
- gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
-};
-
-&vcc5v0_host {
- gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2018 Collabora Ltd.
- * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
- * Copyright (c) 2018 Linaro Ltd.
- */
-
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- aliases {
- mmc0 = &sdio0;
- mmc1 = &sdmmc;
- mmc2 = &sdhci;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-
- vcc12v_dcin: vcc12v-dcin {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc1v8_s0: vcc1v8-s0 {
- compatible = "regulator-fixed";
- regulator-name = "vcc1v8_s0";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_pcie: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_drv>;
- regulator-boot-on;
- regulator-name = "vcc3v3_pcie";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&host_vbus_drv>;
- regulator-name = "vcc5v0_host";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc_0v9: vcc-0v9 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_0v9";
- regulator-always-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- vin-supply = <&vcc3v3_sys>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c3>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- status = "okay";
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- status = "okay";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio1>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc5v0_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v8_dvp: LDO_REG1 {
- regulator-name = "vcc1v8_dvp";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_hdmi: LDO_REG2 {
- regulator-name = "vcca1v8_hdmi";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca_1v8: LDO_REG3 {
- regulator-name = "vcca_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sd: LDO_REG4 {
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc3v0_sd: LDO_REG5 {
- regulator-name = "vcc3v0_sd";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcca0v9_hdmi: LDO_REG7 {
- regulator-name = "vcca0v9_hdmi";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_s3: SWITCH_REG1 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
- };
- };
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
-};
-
-&i2c4 {
- status = "okay";
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
- audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
- sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
- gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- num-lanes = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn_cpm>;
- vpcie0v9-supply = <&vcc_0v9>;
- vpcie1v8-supply = <&vcca_1v8>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&pmu_io_domains {
- pmu1830-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&pinctrl {
- bt {
- bt_enable_h: bt-enable-h {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdmmc {
- sdmmc_bus1: sdmmc-bus1 {
- rockchip,pins =
- <4 RK_PB0 1 &pcfg_pull_up_8ma>;
- };
-
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins =
- <4 RK_PB0 1 &pcfg_pull_up_8ma>,
- <4 RK_PB1 1 &pcfg_pull_up_8ma>,
- <4 RK_PB2 1 &pcfg_pull_up_8ma>,
- <4 RK_PB3 1 &pcfg_pull_up_8ma>;
- };
-
- sdmmc_clk: sdmmc-clk {
- rockchip,pins =
- <4 RK_PB4 1 &pcfg_pull_none_18ma>;
- };
-
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins =
- <4 RK_PB5 1 &pcfg_pull_up_8ma>;
- };
- };
-
- sdio0 {
- sdio0_bus4: sdio0-bus4 {
- rockchip,pins =
- <2 RK_PC4 1 &pcfg_pull_up_20ma>,
- <2 RK_PC5 1 &pcfg_pull_up_20ma>,
- <2 RK_PC6 1 &pcfg_pull_up_20ma>,
- <2 RK_PC7 1 &pcfg_pull_up_20ma>;
- };
-
- sdio0_cmd: sdio0-cmd {
- rockchip,pins =
- <2 RK_PD0 1 &pcfg_pull_up_20ma>;
- };
-
- sdio0_clk: sdio0-clk {
- rockchip,pins =
- <2 RK_PD1 1 &pcfg_pull_none_20ma>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins =
- <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- vsel1_pin: vsel1-pin {
- rockchip,pins =
- <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- vsel2_pin: vsel2-pin {
- rockchip,pins =
- <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins =
- <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wifi {
- wifi_host_wake_l: wifi-host-wake-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&pwm3 {
- status = "okay";
-};
-
-&sdio0 {
- bus-width = <4>;
- clock-frequency = <50000000>;
- cap-sdio-irq;
- cap-sd-highspeed;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
- interrupt-names = "host-wake";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_l>;
- };
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- non-removable;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- clock-frequency = <100000000>;
- max-frequency = <100000000>;
- cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
- disable-wp;
- sd-uhs-sdr104;
- vqmmc-supply = <&vcc_sd>;
- card-detect-delay = <800>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <1>;
- rockchip,hw-tshut-temp = <110000>;
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-};
-
-&u2phy1 {
- status = "okay";
-};
-
-&u2phy0_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&u2phy1_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&u2phy0_otg {
- status = "okay";
-};
-
-&u2phy1_otg {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci;
- };
+/ {
smbios {
compatible = "u-boot,sysinfo-smbios";
smbios {
};
};
};
+};
-
+&gpio0 {
+ bootph-pre-ram;
};
&sdhci {
mmc-ddr-1_8v;
};
+&sdmmc0_pwr_h {
+ bootph-pre-ram;
+};
+
&spi1 {
- spi_flash: flash@0 {
- bootph-all;
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
};
};
+&vcc3v0_sd {
+ bootph-pre-ram;
+};
+
&vdd_center {
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
- * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
- * Copyright (c) 2019 Katsuhiro Suzuki <katsuhiro@katsuster.net>
- */
-
-/dts-v1/;
-#include "rk3399-rockpro64.dtsi"
-
-/ {
- model = "Pine64 RockPro64 v2.1";
- compatible = "pine64,rockpro64-v2.1", "pine64,rockpro64", "rockchip,rk3399";
-};
-
-&i2c1 {
- es8316: codec@11 {
- compatible = "everest,es8316";
- reg = <0x11>;
- clocks = <&cru SCLK_I2S_8CH_OUT>;
- clock-names = "mclk";
- #sound-dai-cells = <0>;
-
- port {
- es8316_p0_0: endpoint {
- remote-endpoint = <&i2s1_p0_0>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
- * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
- */
-
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/pwm/pwm.h>
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-
-/ {
- aliases {
- mmc0 = &sdio0;
- mmc1 = &sdmmc;
- mmc2 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&pwrbtn>;
-
- power {
- debounce-interval = <100>;
- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "GPIO Key Power";
- linux,code = <KEY_POWER>;
- wakeup-source;
- };
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&ir_int>;
- pinctrl-names = "default";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&work_led_pin>, <&diy_led_pin>;
-
- work_led: led-0 {
- label = "work";
- default-state = "on";
- gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
- };
-
- diy_led: led-1 {
- label = "diy";
- default-state = "off";
- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
- };
- };
-
- fan: pwm-fan {
- compatible = "pwm-fan";
- #cooling-cells = <2>;
- fan-supply = <&vcc12v_dcin>;
- pwms = <&pwm1 0 50000 0>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk808 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-
- sound {
- compatible = "audio-graph-card";
- label = "Analog";
- dais = <&i2s1_p0>;
- };
-
- sound-dit {
- compatible = "audio-graph-card";
- label = "SPDIF";
- dais = <&spdif_p0>;
- };
-
- spdif-dit {
- compatible = "linux,spdif-dit";
- #sound-dai-cells = <0>;
-
- port {
- dit_p0_0: endpoint {
- remote-endpoint = <&spdif_p0_0>;
- };
- };
- };
-
- vcc12v_dcin: vcc12v-dcin {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- /* switched by pmic_sleep */
- vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_1v8>;
- };
-
- /* micro SD card power */
- vcc3v0_sd: vcc3v0-sd {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_pwr_h>;
- regulator-name = "vcc3v0_sd";
- regulator-always-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pcie: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pwr_en>;
- regulator-name = "vcc3v3_pcie";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_typec: vcc5v0-typec-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_typec_en>;
- regulator-name = "vcc5v0_typec";
- regulator-always-on;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usb: vcc5v0-usb {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 1>;
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1700000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
- phy-supply = <&vcc_lan>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c3>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
- status = "okay";
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <168>;
- i2c-scl-falling-time-ns = <4>;
- status = "okay";
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio3>;
- interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc5v0_sys>;
- vcc12-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcca_1v8>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v8_dvp: LDO_REG1 {
- regulator-name = "vcc1v8_dvp";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v0_touch: LDO_REG2 {
- regulator-name = "vcc3v0_touch";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca_1v8: LDO_REG3 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sdio: LDO_REG4 {
- regulator-name = "vcc_sdio";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-name = "vcca3v0_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcca1v8_codec: LDO_REG7 {
- regulator-name = "vcca1v8_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_s3: vcc_lan: SWITCH_REG1 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu_b: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel1_pin>;
- regulator-name = "vdd_cpu_b";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: regulator@41 {
- compatible = "silergy,syr828";
- reg = <0x41>;
- fcs,suspend-voltage-selector = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&vsel2_pin>;
- regulator-name = "vdd_gpu";
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1500000>;
- regulator-ramp-delay = <1000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c1 {
- i2c-scl-rising-time-ns = <300>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&i2c4 {
- i2c-scl-rising-time-ns = <600>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
-
- fusb0: typec-portc@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&fusb0_int>;
- vbus-supply = <&vcc5v0_typec>;
- status = "okay";
- };
-};
-
-&i2s0 {
- rockchip,playback-channels = <8>;
- rockchip,capture-channels = <8>;
- status = "okay";
-};
-
-&i2s1 {
- rockchip,playback-channels = <2>;
- rockchip,capture-channels = <2>;
- status = "okay";
-
- i2s1_p0: port {
- i2s1_p0_0: endpoint {
- dai-format = "i2s";
- mclk-fs = <256>;
- remote-endpoint = <&es8316_p0_0>;
- };
- };
-};
-
-&i2s2 {
- status = "okay";
-};
-
-&io_domains {
- status = "okay";
-
- bt656-supply = <&vcc1v8_dvp>;
- audio-supply = <&vcc_3v0>;
- sdmmc-supply = <&vcc_sdio>;
- gpio1830-supply = <&vcc_3v0>;
-};
-
-&pcie0 {
- ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_perst>;
- vpcie12v-supply = <&vcc12v_dcin>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pmu_io_domains {
- pmu1830-supply = <&vcc_3v0>;
- status = "okay";
-};
-
-&pinctrl {
- bt {
- bt_enable_h: bt-enable-h {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- buttons {
- pwrbtn: pwrbtn {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- fusb302x {
- fusb0_int: fusb0-int {
- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- ir {
- ir_int: ir-int {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- leds {
- work_led_pin: work-led-pin {
- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- diy_led_pin: diy-led-pin {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- pcie_perst: pcie-perst {
- rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_pwr_en: pcie-pwr-en {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- vsel1_pin: vsel1-pin {
- rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- vsel2_pin: vsel2-pin {
- rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- sdcard {
- sdmmc0_pwr_h: sdmmc0-pwr-h {
- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb-typec {
- vcc5v0_typec_en: vcc5v0_typec_en {
- rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
-};
-
-&sdio0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- disable-wp;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- vmmc-supply = <&vcc3v0_sd>;
- vqmmc-supply = <&vcc_sdio>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- status = "okay";
-};
-
-&spdif {
- pinctrl-0 = <&spdif_bus_1>;
-
- spdif_p0: port {
- spdif_p0_0: endpoint {
- remote-endpoint = <&dit_p0_0>;
- };
- };
-};
-
-&spi1 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
- };
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tcphy1 {
- status = "okay";
-};
-
-&tsadc {
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_otg: otg-port {
- status = "okay";
- };
-
- u2phy1_host: host-port {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- clocks = <&rk808 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
- vbat-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
- dr_mode = "host";
-};
-
-&usbdrd3_1 {
- status = "okay";
-};
-
-&usbdrd_dwc3_1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2022 Radxa Limited
- */
-
-/ {
- cluster0_opp: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <875000 875000 1250000>;
- clock-latency-ns = <40000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <875000 875000 1250000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <900000 900000 1250000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <975000 975000 1250000>;
- };
- };
-
- cluster1_opp: opp-table-1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <875000 875000 1250000>;
- clock-latency-ns = <40000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <875000 875000 1250000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <875000 875000 1250000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <925000 925000 1250000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1000000 1000000 1250000>;
- };
- opp05 {
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <1075000 1075000 1250000>;
- };
- opp06 {
- opp-hz = /bits/ 64 <1512000000>;
- opp-microvolt = <1150000 1150000 1250000>;
- };
- };
-
- gpu_opp_table: opp-table-2 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <875000 875000 1150000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <875000 875000 1150000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <875000 875000 1150000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <975000 975000 1150000>;
- };
- };
-};
-
-&cpu_l0 {
- operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_l1 {
- operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_l2 {
- operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_l3 {
- operating-points-v2 = <&cluster0_opp>;
-};
-
-&cpu_b0 {
- operating-points-v2 = <&cluster1_opp>;
-};
-
-&cpu_b1 {
- operating-points-v2 = <&cluster1_opp>;
-};
-
-&gpu {
- operating-points-v2 = <&gpu_opp_table>;
-};
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
-#define USB_CLASS_HUB 9
-
#include "rockchip-u-boot.dtsi"
/ {
spi1 = &spi1;
};
- cic: syscon@ff620000 {
- bootph-all;
- compatible = "rockchip,rk3399-cic", "syscon";
- reg = <0x0 0xff620000 0x0 0x100>;
- };
-
- dfi: dfi@ff630000 {
- bootph-all;
- reg = <0x00 0xff630000 0x00 0x4000>;
- compatible = "rockchip,rk3399-dfi";
- rockchip,pmu = <&pmugrf>;
- clocks = <&cru PCLK_DDR_MON>;
- clock-names = "pclk_ddr_mon";
- };
-
- rng: rng@ff8b8000 {
- compatible = "rockchip,rk3399-crypto";
- reg = <0x0 0xff8b8000 0x0 0x1000>;
- status = "okay";
- };
-
- dmc: dmc {
- bootph-all;
- compatible = "rockchip,rk3399-dmc";
- devfreq-events = <&dfi>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_DDRCLK>;
- clock-names = "dmc_clk";
- reg = <0x0 0xffa80000 0x0 0x0800
- 0x0 0xffa80800 0x0 0x1800
- 0x0 0xffa82000 0x0 0x2000
- 0x0 0xffa84000 0x0 0x1000
- 0x0 0xffa88000 0x0 0x0800
- 0x0 0xffa88800 0x0 0x1800
- 0x0 0xffa8a000 0x0 0x2000
- 0x0 0xffa8c000 0x0 0x1000>;
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
pmusgrf: syscon@ff330000 {
- bootph-all;
compatible = "rockchip,rk3399-pmusgrf", "syscon";
reg = <0x0 0xff330000 0x0 0xe3d4>;
+ bootph-all;
};
+ cic: syscon@ff620000 {
+ compatible = "rockchip,rk3399-cic", "syscon";
+ reg = <0x0 0xff620000 0x0 0x100>;
+ bootph-all;
+ };
};
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
bootph-all;
};
-&emmc_phy {
+&dfi {
+ bootph-all;
+};
+
+&dmc {
+ reg = <0x0 0xffa80000 0x0 0x0800
+ 0x0 0xffa80800 0x0 0x1800
+ 0x0 0xffa82000 0x0 0x2000
+ 0x0 0xffa84000 0x0 0x1000
+ 0x0 0xffa88000 0x0 0x0800
+ 0x0 0xffa88800 0x0 0x1800
+ 0x0 0xffa8a000 0x0 0x2000
+ 0x0 0xffa8c000 0x0 0x1000>;
bootph-all;
+ status = "okay";
+};
+
+&emmc_phy {
+ bootph-pre-ram;
+ bootph-some-ram;
};
&grf {
bootph-all;
};
-&pinctrl {
+&pcfg_pull_none {
bootph-all;
};
-&pmu {
+&pcfg_pull_up {
bootph-all;
};
-&pmugrf {
+&pinctrl {
bootph-all;
};
bootph-all;
};
+&pmugrf {
+ bootph-all;
+};
+
&sdhci {
+ bootph-pre-ram;
+ bootph-some-ram;
max-frequency = <200000000>;
- bootph-all;
+
+ /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&sdmmc {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
-&spi1 {
- bootph-all;
+&sdmmc_bus4 {
+ bootph-pre-ram;
+ bootph-some-ram;
};
-&uart0 {
- bootph-all;
+&sdmmc_cd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&spi1_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&spi1_cs0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&spi1_rx {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&spi1_tx {
+ bootph-pre-ram;
+ bootph-some-ram;
};
&uart2 {
bootph-all;
+ clock-frequency = <24000000>;
+};
+
+&uart2c_xfer {
+ bootph-pre-sram;
+ bootph-pre-ram;
};
&vopb {
- bootph-all;
+ bootph-some-ram;
};
&vopl {
+ bootph-some-ram;
+};
+
+&xin24m {
bootph-all;
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-#include <dt-bindings/clock/rk3399-cru.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/power/rk3399-power.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- compatible = "rockchip,rk3399";
-
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- ethernet0 = &gmac;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &i2c7;
- i2c8 = &i2c8;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- serial4 = &uart4;
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu_l0>;
- };
- core1 {
- cpu = <&cpu_l1>;
- };
- core2 {
- cpu = <&cpu_l2>;
- };
- core3 {
- cpu = <&cpu_l3>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&cpu_b0>;
- };
- core1 {
- cpu = <&cpu_b1>;
- };
- };
- };
-
- cpu_l0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x0>;
- enable-method = "psci";
- capacity-dmips-mhz = <485>;
- clocks = <&cru ARMCLKL>;
- #cooling-cells = <2>; /* min followed by max */
- dynamic-power-coefficient = <100>;
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
- };
-
- cpu_l1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x1>;
- enable-method = "psci";
- capacity-dmips-mhz = <485>;
- clocks = <&cru ARMCLKL>;
- #cooling-cells = <2>; /* min followed by max */
- dynamic-power-coefficient = <100>;
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
- };
-
- cpu_l2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x2>;
- enable-method = "psci";
- capacity-dmips-mhz = <485>;
- clocks = <&cru ARMCLKL>;
- #cooling-cells = <2>; /* min followed by max */
- dynamic-power-coefficient = <100>;
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
- };
-
- cpu_l3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x3>;
- enable-method = "psci";
- capacity-dmips-mhz = <485>;
- clocks = <&cru ARMCLKL>;
- #cooling-cells = <2>; /* min followed by max */
- dynamic-power-coefficient = <100>;
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
- };
-
- cpu_b0: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a72";
- reg = <0x0 0x100>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- clocks = <&cru ARMCLKB>;
- #cooling-cells = <2>; /* min followed by max */
- dynamic-power-coefficient = <436>;
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
- };
-
- cpu_b1: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a72";
- reg = <0x0 0x101>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- clocks = <&cru ARMCLKB>;
- #cooling-cells = <2>; /* min followed by max */
- dynamic-power-coefficient = <436>;
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
- };
-
- idle-states {
- entry-method = "psci";
-
- CPU_SLEEP: cpu-sleep {
- compatible = "arm,idle-state";
- local-timer-stop;
- arm,psci-suspend-param = <0x0010000>;
- entry-latency-us = <120>;
- exit-latency-us = <250>;
- min-residency-us = <900>;
- };
-
- CLUSTER_SLEEP: cluster-sleep {
- compatible = "arm,idle-state";
- local-timer-stop;
- arm,psci-suspend-param = <0x1010000>;
- entry-latency-us = <400>;
- exit-latency-us = <500>;
- min-residency-us = <2000>;
- };
- };
- };
-
- display-subsystem {
- compatible = "rockchip,display-subsystem";
- ports = <&vopl_out>, <&vopb_out>;
- };
-
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
- };
-
- pmu_a72 {
- compatible = "arm,cortex-a72-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
- arm,no-tick-in-suspend;
- };
-
- xin24m: xin24m {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- #clock-cells = <0>;
- };
-
- pcie0: pcie@f8000000 {
- compatible = "rockchip,rk3399-pcie";
- reg = <0x0 0xf8000000 0x0 0x2000000>,
- <0x0 0xfd000000 0x0 0x1000000>;
- reg-names = "axi-base", "apb-base";
- device_type = "pci";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- aspm-no-l0s;
- bus-range = <0x0 0x1f>;
- clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
- <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
- clock-names = "aclk", "aclk-perf",
- "hclk", "pm";
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "sys", "legacy", "client";
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie0_intc 0>,
- <0 0 0 2 &pcie0_intc 1>,
- <0 0 0 3 &pcie0_intc 2>,
- <0 0 0 4 &pcie0_intc 3>;
- max-link-speed = <1>;
- msi-map = <0x0 &its 0x0 0x1000>;
- phys = <&pcie_phy 0>, <&pcie_phy 1>,
- <&pcie_phy 2>, <&pcie_phy 3>;
- phy-names = "pcie-phy-0", "pcie-phy-1",
- "pcie-phy-2", "pcie-phy-3";
- ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
- <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
- resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
- <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
- <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
- <&cru SRST_A_PCIE>;
- reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
- "pm", "pclk", "aclk";
- status = "disabled";
-
- pcie0_intc: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
- };
-
- gmac: ethernet@fe300000 {
- compatible = "rockchip,rk3399-gmac";
- reg = <0x0 0xfe300000 0x0 0x10000>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "macirq";
- clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
- <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
- <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
- <&cru PCLK_GMAC>;
- clock-names = "stmmaceth", "mac_clk_rx",
- "mac_clk_tx", "clk_mac_ref",
- "clk_mac_refout", "aclk_mac",
- "pclk_mac";
- power-domains = <&power RK3399_PD_GMAC>;
- resets = <&cru SRST_A_GMAC>;
- reset-names = "stmmaceth";
- rockchip,grf = <&grf>;
- snps,txpbl = <0x4>;
- status = "disabled";
- };
-
- sdio0: mmc@fe310000 {
- compatible = "rockchip,rk3399-dw-mshc",
- "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xfe310000 0x0 0x4000>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
- max-frequency = <150000000>;
- clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- power-domains = <&power RK3399_PD_SDIOAUDIO>;
- resets = <&cru SRST_SDIO0>;
- reset-names = "reset";
- status = "disabled";
- };
-
- sdmmc: mmc@fe320000 {
- compatible = "rockchip,rk3399-dw-mshc",
- "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xfe320000 0x0 0x4000>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
- max-frequency = <150000000>;
- assigned-clocks = <&cru HCLK_SD>;
- assigned-clock-rates = <200000000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- power-domains = <&power RK3399_PD_SD>;
- resets = <&cru SRST_SDMMC>;
- reset-names = "reset";
- status = "disabled";
- };
-
- sdhci: mmc@fe330000 {
- compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
- reg = <0x0 0xfe330000 0x0 0x10000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
- arasan,soc-ctl-syscon = <&grf>;
- assigned-clocks = <&cru SCLK_EMMC>;
- assigned-clock-rates = <200000000>;
- clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
- clock-names = "clk_xin", "clk_ahb";
- clock-output-names = "emmc_cardclock";
- #clock-cells = <0>;
- phys = <&emmc_phy>;
- phy-names = "phy_arasan";
- power-domains = <&power RK3399_PD_EMMC>;
- disable-cqe-dcmd;
- status = "disabled";
- };
-
- usb_host0_ehci: usb@fe380000 {
- compatible = "generic-ehci";
- reg = <0x0 0xfe380000 0x0 0x20000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
- <&u2phy0>;
- phys = <&u2phy0_host>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usb_host0_ohci: usb@fe3a0000 {
- compatible = "generic-ohci";
- reg = <0x0 0xfe3a0000 0x0 0x20000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
- <&u2phy0>;
- phys = <&u2phy0_host>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usb_host1_ehci: usb@fe3c0000 {
- compatible = "generic-ehci";
- reg = <0x0 0xfe3c0000 0x0 0x20000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
- <&u2phy1>;
- phys = <&u2phy1_host>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usb_host1_ohci: usb@fe3e0000 {
- compatible = "generic-ohci";
- reg = <0x0 0xfe3e0000 0x0 0x20000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
- <&u2phy1>;
- phys = <&u2phy1_host>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usbdrd3_0: usb@fe800000 {
- compatible = "rockchip,rk3399-dwc3";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
- <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
- <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
- clock-names = "ref_clk", "suspend_clk",
- "bus_clk", "aclk_usb3_rksoc_axi_perf",
- "aclk_usb3", "grf_clk";
- resets = <&cru SRST_A_USB3_OTG0>;
- reset-names = "usb3-otg";
- status = "disabled";
-
- usbdrd_dwc3_0: usb@fe800000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfe800000 0x0 0x100000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
- <&cru SCLK_USB3OTG0_SUSPEND>;
- clock-names = "ref", "bus_early", "suspend";
- dr_mode = "otg";
- phys = <&u2phy0_otg>, <&tcphy0_usb3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis_u2_susphy_quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- power-domains = <&power RK3399_PD_USB3>;
- status = "disabled";
- };
- };
-
- usbdrd3_1: usb@fe900000 {
- compatible = "rockchip,rk3399-dwc3";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
- <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
- <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
- clock-names = "ref_clk", "suspend_clk",
- "bus_clk", "aclk_usb3_rksoc_axi_perf",
- "aclk_usb3", "grf_clk";
- resets = <&cru SRST_A_USB3_OTG1>;
- reset-names = "usb3-otg";
- status = "disabled";
-
- usbdrd_dwc3_1: usb@fe900000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfe900000 0x0 0x100000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
- <&cru SCLK_USB3OTG1_SUSPEND>;
- clock-names = "ref", "bus_early", "suspend";
- dr_mode = "otg";
- phys = <&u2phy1_otg>, <&tcphy1_usb3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis_u2_susphy_quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- power-domains = <&power RK3399_PD_USB3>;
- status = "disabled";
- };
- };
-
- cdn_dp: dp@fec00000 {
- compatible = "rockchip,rk3399-cdn-dp";
- reg = <0x0 0xfec00000 0x0 0x100000>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
- assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
- assigned-clock-rates = <100000000>, <200000000>;
- clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
- <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
- clock-names = "core-clk", "pclk", "spdif", "grf";
- phys = <&tcphy0_dp>, <&tcphy1_dp>;
- power-domains = <&power RK3399_PD_HDCP>;
- resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
- <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
- reset-names = "spdif", "dptx", "apb", "core";
- rockchip,grf = <&grf>;
- #sound-dai-cells = <1>;
- status = "disabled";
-
- ports {
- dp_in: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- dp_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vopb_out_dp>;
- };
-
- dp_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_dp>;
- };
- };
- };
- };
-
- gic: interrupt-controller@fee00000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- interrupt-controller;
-
- reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
- <0x0 0xfef00000 0 0xc0000>, /* GICR */
- <0x0 0xfff00000 0 0x10000>, /* GICC */
- <0x0 0xfff10000 0 0x10000>, /* GICH */
- <0x0 0xfff20000 0 0x10000>; /* GICV */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
- its: interrupt-controller@fee20000 {
- compatible = "arm,gic-v3-its";
- msi-controller;
- #msi-cells = <1>;
- reg = <0x0 0xfee20000 0x0 0x20000>;
- };
-
- ppi-partitions {
- ppi_cluster0: interrupt-partition-0 {
- affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
- };
-
- ppi_cluster1: interrupt-partition-1 {
- affinity = <&cpu_b0 &cpu_b1>;
- };
- };
- };
-
- saradc: saradc@ff100000 {
- compatible = "rockchip,rk3399-saradc";
- reg = <0x0 0xff100000 0x0 0x100>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
- #io-channel-cells = <1>;
- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
- clock-names = "saradc", "apb_pclk";
- resets = <&cru SRST_P_SARADC>;
- reset-names = "saradc-apb";
- status = "disabled";
- };
-
- i2c1: i2c@ff110000 {
- compatible = "rockchip,rk3399-i2c";
- reg = <0x0 0xff110000 0x0 0x1000>;
- assigned-clocks = <&cru SCLK_I2C1>;
- assigned-clock-rates = <200000000>;
- clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@ff120000 {
- compatible = "rockchip,rk3399-i2c";
- reg = <0x0 0xff120000 0x0 0x1000>;
- assigned-clocks = <&cru SCLK_I2C2>;
- assigned-clock-rates = <200000000>;
- clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@ff130000 {
- compatible = "rockchip,rk3399-i2c";
- reg = <0x0 0xff130000 0x0 0x1000>;
- assigned-clocks = <&cru SCLK_I2C3>;
- assigned-clock-rates = <200000000>;
- clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c5: i2c@ff140000 {
- compatible = "rockchip,rk3399-i2c";
- reg = <0x0 0xff140000 0x0 0x1000>;
- assigned-clocks = <&cru SCLK_I2C5>;
- assigned-clock-rates = <200000000>;
- clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c6: i2c@ff150000 {
- compatible = "rockchip,rk3399-i2c";
- reg = <0x0 0xff150000 0x0 0x1000>;
- assigned-clocks = <&cru SCLK_I2C6>;
- assigned-clock-rates = <200000000>;
- clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c7: i2c@ff160000 {
- compatible = "rockchip,rk3399-i2c";
- reg = <0x0 0xff160000 0x0 0x1000>;
- assigned-clocks = <&cru SCLK_I2C7>;
- assigned-clock-rates = <200000000>;
- clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c7_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart0: serial@ff180000 {
- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff180000 0x0 0x100>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
- reg-shift = <2>;
- reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer>;
- status = "disabled";
- };
-
- uart1: serial@ff190000 {
- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff190000 0x0 0x100>;
- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
- reg-shift = <2>;
- reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer>;
- status = "disabled";
- };
-
- uart2: serial@ff1a0000 {
- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff1a0000 0x0 0x100>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
- reg-shift = <2>;
- reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart2c_xfer>;
- status = "disabled";
- };
-
- uart3: serial@ff1b0000 {
- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff1b0000 0x0 0x100>;
- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
- clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
- reg-shift = <2>;
- reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_xfer>;
- status = "disabled";
- };
-
- spi0: spi@ff1c0000 {
- compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff1c0000 0x0 0x1000>;
- clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
- clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
- dmas = <&dmac_peri 10>, <&dmac_peri 11>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@ff1d0000 {
- compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff1d0000 0x0 0x1000>;
- clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
- clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
- dmas = <&dmac_peri 12>, <&dmac_peri 13>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi2: spi@ff1e0000 {
- compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff1e0000 0x0 0x1000>;
- clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
- clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
- dmas = <&dmac_peri 14>, <&dmac_peri 15>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi4: spi@ff1f0000 {
- compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff1f0000 0x0 0x1000>;
- clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
- clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
- dmas = <&dmac_peri 18>, <&dmac_peri 19>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi5: spi@ff200000 {
- compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff200000 0x0 0x1000>;
- clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
- clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
- dmas = <&dmac_bus 8>, <&dmac_bus 9>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
- power-domains = <&power RK3399_PD_SDIOAUDIO>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- thermal_zones: thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <100>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsadc 0>;
-
- trips {
- cpu_alert0: cpu_alert0 {
- temperature = <70000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_alert1: cpu_alert1 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit: cpu_crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert0>;
- cooling-device =
- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu_alert1>;
- cooling-device =
- <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
-
- gpu_thermal: gpu-thermal {
- polling-delay-passive = <100>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsadc 1>;
-
- trips {
- gpu_alert0: gpu_alert0 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- gpu_crit: gpu_crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&gpu_alert0>;
- cooling-device =
- <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
- tsadc: tsadc@ff260000 {
- compatible = "rockchip,rk3399-tsadc";
- reg = <0x0 0xff260000 0x0 0x100>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
- assigned-clocks = <&cru SCLK_TSADC>;
- assigned-clock-rates = <750000>;
- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
- clock-names = "tsadc", "apb_pclk";
- resets = <&cru SRST_TSADC>;
- reset-names = "tsadc-apb";
- rockchip,grf = <&grf>;
- rockchip,hw-tshut-temp = <95000>;
- pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_pin>;
- pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_pin>;
- #thermal-sensor-cells = <1>;
- status = "disabled";
- };
-
- qos_emmc: qos@ffa58000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffa58000 0x0 0x20>;
- };
-
- qos_gmac: qos@ffa5c000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffa5c000 0x0 0x20>;
- };
-
- qos_pcie: qos@ffa60080 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffa60080 0x0 0x20>;
- };
-
- qos_usb_host0: qos@ffa60100 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffa60100 0x0 0x20>;
- };
-
- qos_usb_host1: qos@ffa60180 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffa60180 0x0 0x20>;
- };
-
- qos_usb_otg0: qos@ffa70000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffa70000 0x0 0x20>;
- };
-
- qos_usb_otg1: qos@ffa70080 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffa70080 0x0 0x20>;
- };
-
- qos_sd: qos@ffa74000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffa74000 0x0 0x20>;
- };
-
- qos_sdioaudio: qos@ffa76000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffa76000 0x0 0x20>;
- };
-
- qos_hdcp: qos@ffa90000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffa90000 0x0 0x20>;
- };
-
- qos_iep: qos@ffa98000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffa98000 0x0 0x20>;
- };
-
- qos_isp0_m0: qos@ffaa0000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffaa0000 0x0 0x20>;
- };
-
- qos_isp0_m1: qos@ffaa0080 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffaa0080 0x0 0x20>;
- };
-
- qos_isp1_m0: qos@ffaa8000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffaa8000 0x0 0x20>;
- };
-
- qos_isp1_m1: qos@ffaa8080 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffaa8080 0x0 0x20>;
- };
-
- qos_rga_r: qos@ffab0000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffab0000 0x0 0x20>;
- };
-
- qos_rga_w: qos@ffab0080 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffab0080 0x0 0x20>;
- };
-
- qos_video_m0: qos@ffab8000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffab8000 0x0 0x20>;
- };
-
- qos_video_m1_r: qos@ffac0000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffac0000 0x0 0x20>;
- };
-
- qos_video_m1_w: qos@ffac0080 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffac0080 0x0 0x20>;
- };
-
- qos_vop_big_r: qos@ffac8000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffac8000 0x0 0x20>;
- };
-
- qos_vop_big_w: qos@ffac8080 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffac8080 0x0 0x20>;
- };
-
- qos_vop_little: qos@ffad0000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffad0000 0x0 0x20>;
- };
-
- qos_perihp: qos@ffad8080 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffad8080 0x0 0x20>;
- };
-
- qos_gpu: qos@ffae0000 {
- compatible = "rockchip,rk3399-qos", "syscon";
- reg = <0x0 0xffae0000 0x0 0x20>;
- };
-
- pmu: power-management@ff310000 {
- compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
- reg = <0x0 0xff310000 0x0 0x1000>;
-
- /*
- * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
- * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
- * Some of the power domains are grouped together for every
- * voltage domain.
- * The detail contents as below.
- */
- power: power-controller {
- compatible = "rockchip,rk3399-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* These power domains are grouped by VD_CENTER */
- power-domain@RK3399_PD_IEP {
- reg = <RK3399_PD_IEP>;
- clocks = <&cru ACLK_IEP>,
- <&cru HCLK_IEP>;
- pm_qos = <&qos_iep>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_RGA {
- reg = <RK3399_PD_RGA>;
- clocks = <&cru ACLK_RGA>,
- <&cru HCLK_RGA>;
- pm_qos = <&qos_rga_r>,
- <&qos_rga_w>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_VCODEC {
- reg = <RK3399_PD_VCODEC>;
- clocks = <&cru ACLK_VCODEC>,
- <&cru HCLK_VCODEC>;
- pm_qos = <&qos_video_m0>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_VDU {
- reg = <RK3399_PD_VDU>;
- clocks = <&cru ACLK_VDU>,
- <&cru HCLK_VDU>;
- pm_qos = <&qos_video_m1_r>,
- <&qos_video_m1_w>;
- #power-domain-cells = <0>;
- };
-
- /* These power domains are grouped by VD_GPU */
- power-domain@RK3399_PD_GPU {
- reg = <RK3399_PD_GPU>;
- clocks = <&cru ACLK_GPU>;
- pm_qos = <&qos_gpu>;
- #power-domain-cells = <0>;
- };
-
- /* These power domains are grouped by VD_LOGIC */
- power-domain@RK3399_PD_EDP {
- reg = <RK3399_PD_EDP>;
- clocks = <&cru PCLK_EDP_CTRL>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_EMMC {
- reg = <RK3399_PD_EMMC>;
- clocks = <&cru ACLK_EMMC>;
- pm_qos = <&qos_emmc>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_GMAC {
- reg = <RK3399_PD_GMAC>;
- clocks = <&cru ACLK_GMAC>,
- <&cru PCLK_GMAC>;
- pm_qos = <&qos_gmac>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_SD {
- reg = <RK3399_PD_SD>;
- clocks = <&cru HCLK_SDMMC>,
- <&cru SCLK_SDMMC>;
- pm_qos = <&qos_sd>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_SDIOAUDIO {
- reg = <RK3399_PD_SDIOAUDIO>;
- clocks = <&cru HCLK_SDIO>;
- pm_qos = <&qos_sdioaudio>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_TCPD0 {
- reg = <RK3399_PD_TCPD0>;
- clocks = <&cru SCLK_UPHY0_TCPDCORE>,
- <&cru SCLK_UPHY0_TCPDPHY_REF>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_TCPD1 {
- reg = <RK3399_PD_TCPD1>;
- clocks = <&cru SCLK_UPHY1_TCPDCORE>,
- <&cru SCLK_UPHY1_TCPDPHY_REF>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_USB3 {
- reg = <RK3399_PD_USB3>;
- clocks = <&cru ACLK_USB3>;
- pm_qos = <&qos_usb_otg0>,
- <&qos_usb_otg1>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_VIO {
- reg = <RK3399_PD_VIO>;
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- power-domain@RK3399_PD_HDCP {
- reg = <RK3399_PD_HDCP>;
- clocks = <&cru ACLK_HDCP>,
- <&cru HCLK_HDCP>,
- <&cru PCLK_HDCP>;
- pm_qos = <&qos_hdcp>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_ISP0 {
- reg = <RK3399_PD_ISP0>;
- clocks = <&cru ACLK_ISP0>,
- <&cru HCLK_ISP0>;
- pm_qos = <&qos_isp0_m0>,
- <&qos_isp0_m1>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_ISP1 {
- reg = <RK3399_PD_ISP1>;
- clocks = <&cru ACLK_ISP1>,
- <&cru HCLK_ISP1>;
- pm_qos = <&qos_isp1_m0>,
- <&qos_isp1_m1>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_VO {
- reg = <RK3399_PD_VO>;
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- power-domain@RK3399_PD_VOPB {
- reg = <RK3399_PD_VOPB>;
- clocks = <&cru ACLK_VOP0>,
- <&cru HCLK_VOP0>;
- pm_qos = <&qos_vop_big_r>,
- <&qos_vop_big_w>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3399_PD_VOPL {
- reg = <RK3399_PD_VOPL>;
- clocks = <&cru ACLK_VOP1>,
- <&cru HCLK_VOP1>;
- pm_qos = <&qos_vop_little>;
- #power-domain-cells = <0>;
- };
- };
- };
- };
- };
-
- pmugrf: syscon@ff320000 {
- compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
- reg = <0x0 0xff320000 0x0 0x1000>;
-
- pmu_io_domains: io-domains {
- compatible = "rockchip,rk3399-pmu-io-voltage-domain";
- status = "disabled";
- };
- };
-
- spi3: spi@ff350000 {
- compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff350000 0x0 0x1000>;
- clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
- clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart4: serial@ff370000 {
- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff370000 0x0 0x100>;
- clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
- clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
- reg-shift = <2>;
- reg-io-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_xfer>;
- status = "disabled";
- };
-
- i2c0: i2c@ff3c0000 {
- compatible = "rockchip,rk3399-i2c";
- reg = <0x0 0xff3c0000 0x0 0x1000>;
- assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
- assigned-clock-rates = <200000000>;
- clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@ff3d0000 {
- compatible = "rockchip,rk3399-i2c";
- reg = <0x0 0xff3d0000 0x0 0x1000>;
- assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
- assigned-clock-rates = <200000000>;
- clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c8: i2c@ff3e0000 {
- compatible = "rockchip,rk3399-i2c";
- reg = <0x0 0xff3e0000 0x0 0x1000>;
- assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
- assigned-clock-rates = <200000000>;
- clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c8_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pwm0: pwm@ff420000 {
- compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
- reg = <0x0 0xff420000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pin>;
- clocks = <&pmucru PCLK_RKPWM_PMU>;
- status = "disabled";
- };
-
- pwm1: pwm@ff420010 {
- compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
- reg = <0x0 0xff420010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm1_pin>;
- clocks = <&pmucru PCLK_RKPWM_PMU>;
- status = "disabled";
- };
-
- pwm2: pwm@ff420020 {
- compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
- reg = <0x0 0xff420020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm2_pin>;
- clocks = <&pmucru PCLK_RKPWM_PMU>;
- status = "disabled";
- };
-
- pwm3: pwm@ff420030 {
- compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
- reg = <0x0 0xff420030 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3a_pin>;
- clocks = <&pmucru PCLK_RKPWM_PMU>;
- status = "disabled";
- };
-
- vpu: video-codec@ff650000 {
- compatible = "rockchip,rk3399-vpu";
- reg = <0x0 0xff650000 0x0 0x800>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vepu", "vdpu";
- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
- clock-names = "aclk", "hclk";
- iommus = <&vpu_mmu>;
- power-domains = <&power RK3399_PD_VCODEC>;
- };
-
- vpu_mmu: iommu@ff650800 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff650800 0x0 0x40>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vpu_mmu";
- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- power-domains = <&power RK3399_PD_VCODEC>;
- };
-
- vdec: video-codec@ff660000 {
- compatible = "rockchip,rk3399-vdec";
- reg = <0x0 0xff660000 0x0 0x400>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
- <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
- clock-names = "axi", "ahb", "cabac", "core";
- iommus = <&vdec_mmu>;
- power-domains = <&power RK3399_PD_VDU>;
- };
-
- vdec_mmu: iommu@ff660480 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vdec_mmu";
- clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3399_PD_VDU>;
- #iommu-cells = <0>;
- };
-
- iep_mmu: iommu@ff670800 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff670800 0x0 0x40>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "iep_mmu";
- clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- rga: rga@ff680000 {
- compatible = "rockchip,rk3399-rga";
- reg = <0x0 0xff680000 0x0 0x10000>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
- clock-names = "aclk", "hclk", "sclk";
- resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
- reset-names = "core", "axi", "ahb";
- power-domains = <&power RK3399_PD_RGA>;
- };
-
- efuse0: efuse@ff690000 {
- compatible = "rockchip,rk3399-efuse";
- reg = <0x0 0xff690000 0x0 0x80>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&cru PCLK_EFUSE1024NS>;
- clock-names = "pclk_efuse";
-
- /* Data cells */
- cpu_id: cpu-id@7 {
- reg = <0x07 0x10>;
- };
- cpub_leakage: cpu-leakage@17 {
- reg = <0x17 0x1>;
- };
- gpu_leakage: gpu-leakage@18 {
- reg = <0x18 0x1>;
- };
- center_leakage: center-leakage@19 {
- reg = <0x19 0x1>;
- };
- cpul_leakage: cpu-leakage@1a {
- reg = <0x1a 0x1>;
- };
- logic_leakage: logic-leakage@1b {
- reg = <0x1b 0x1>;
- };
- wafer_info: wafer-info@1c {
- reg = <0x1c 0x1>;
- };
- };
-
- dmac_bus: dma-controller@ff6d0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff6d0000 0x0 0x4000>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
- #dma-cells = <1>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_DMAC0_PERILP>;
- clock-names = "apb_pclk";
- };
-
- dmac_peri: dma-controller@ff6e0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff6e0000 0x0 0x4000>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
- #dma-cells = <1>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_DMAC1_PERILP>;
- clock-names = "apb_pclk";
- };
-
- pmucru: pmu-clock-controller@ff750000 {
- compatible = "rockchip,rk3399-pmucru";
- reg = <0x0 0xff750000 0x0 0x1000>;
- rockchip,grf = <&pmugrf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- assigned-clocks = <&pmucru PLL_PPLL>;
- assigned-clock-rates = <676000000>;
- };
-
- cru: clock-controller@ff760000 {
- compatible = "rockchip,rk3399-cru";
- reg = <0x0 0xff760000 0x0 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- assigned-clocks =
- <&cru PLL_GPLL>, <&cru PLL_CPLL>,
- <&cru PLL_NPLL>,
- <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
- <&cru PCLK_PERIHP>,
- <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
- <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
- <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
- <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
- <&cru ACLK_GIC_PRE>,
- <&cru PCLK_DDR>;
- assigned-clock-rates =
- <594000000>, <800000000>,
- <1000000000>,
- <150000000>, <75000000>,
- <37500000>,
- <100000000>, <100000000>,
- <50000000>, <600000000>,
- <100000000>, <50000000>,
- <400000000>, <400000000>,
- <200000000>,
- <200000000>;
- };
-
- grf: syscon@ff770000 {
- compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
- reg = <0x0 0xff770000 0x0 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- io_domains: io-domains {
- compatible = "rockchip,rk3399-io-voltage-domain";
- status = "disabled";
- };
-
- mipi_dphy_rx0: mipi-dphy-rx0 {
- compatible = "rockchip,rk3399-mipi-dphy-rx0";
- clocks = <&cru SCLK_MIPIDPHY_REF>,
- <&cru SCLK_DPHY_RX0_CFG>,
- <&cru PCLK_VIO_GRF>;
- clock-names = "dphy-ref", "dphy-cfg", "grf";
- power-domains = <&power RK3399_PD_VIO>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- u2phy0: usb2phy@e450 {
- compatible = "rockchip,rk3399-usb2phy";
- reg = <0xe450 0x10>;
- clocks = <&cru SCLK_USB2PHY0_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "clk_usbphy0_480m";
- status = "disabled";
-
- u2phy0_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "linestate";
- status = "disabled";
- };
-
- u2phy0_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
- };
-
- u2phy1: usb2phy@e460 {
- compatible = "rockchip,rk3399-usb2phy";
- reg = <0xe460 0x10>;
- clocks = <&cru SCLK_USB2PHY1_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "clk_usbphy1_480m";
- status = "disabled";
-
- u2phy1_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "linestate";
- status = "disabled";
- };
-
- u2phy1_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
- };
-
- emmc_phy: phy@f780 {
- compatible = "rockchip,rk3399-emmc-phy";
- reg = <0xf780 0x24>;
- clocks = <&sdhci>;
- clock-names = "emmcclk";
- #phy-cells = <0>;
- status = "disabled";
- };
-
- pcie_phy: pcie-phy {
- compatible = "rockchip,rk3399-pcie-phy";
- clocks = <&cru SCLK_PCIEPHY_REF>;
- clock-names = "refclk";
- #phy-cells = <1>;
- resets = <&cru SRST_PCIEPHY>;
- drive-impedance-ohm = <50>;
- reset-names = "phy";
- status = "disabled";
- };
- };
-
- tcphy0: phy@ff7c0000 {
- compatible = "rockchip,rk3399-typec-phy";
- reg = <0x0 0xff7c0000 0x0 0x40000>;
- clocks = <&cru SCLK_UPHY0_TCPDCORE>,
- <&cru SCLK_UPHY0_TCPDPHY_REF>;
- clock-names = "tcpdcore", "tcpdphy-ref";
- assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
- assigned-clock-rates = <50000000>;
- power-domains = <&power RK3399_PD_TCPD0>;
- resets = <&cru SRST_UPHY0>,
- <&cru SRST_UPHY0_PIPE_L00>,
- <&cru SRST_P_UPHY0_TCPHY>;
- reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
- rockchip,grf = <&grf>;
- status = "disabled";
-
- tcphy0_dp: dp-port {
- #phy-cells = <0>;
- };
-
- tcphy0_usb3: usb3-port {
- #phy-cells = <0>;
- };
- };
-
- tcphy1: phy@ff800000 {
- compatible = "rockchip,rk3399-typec-phy";
- reg = <0x0 0xff800000 0x0 0x40000>;
- clocks = <&cru SCLK_UPHY1_TCPDCORE>,
- <&cru SCLK_UPHY1_TCPDPHY_REF>;
- clock-names = "tcpdcore", "tcpdphy-ref";
- assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
- assigned-clock-rates = <50000000>;
- power-domains = <&power RK3399_PD_TCPD1>;
- resets = <&cru SRST_UPHY1>,
- <&cru SRST_UPHY1_PIPE_L00>,
- <&cru SRST_P_UPHY1_TCPHY>;
- reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
- rockchip,grf = <&grf>;
- status = "disabled";
-
- tcphy1_dp: dp-port {
- #phy-cells = <0>;
- };
-
- tcphy1_usb3: usb3-port {
- #phy-cells = <0>;
- };
- };
-
- watchdog@ff848000 {
- compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
- reg = <0x0 0xff848000 0x0 0x100>;
- clocks = <&cru PCLK_WDT>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
- };
-
- rktimer: rktimer@ff850000 {
- compatible = "rockchip,rk3399-timer";
- reg = <0x0 0xff850000 0x0 0x1000>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
- clock-names = "pclk", "timer";
- };
-
- spdif: spdif@ff870000 {
- compatible = "rockchip,rk3399-spdif";
- reg = <0x0 0xff870000 0x0 0x1000>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
- dmas = <&dmac_bus 7>;
- dma-names = "tx";
- clock-names = "mclk", "hclk";
- clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
- pinctrl-names = "default";
- pinctrl-0 = <&spdif_bus>;
- power-domains = <&power RK3399_PD_SDIOAUDIO>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s0: i2s@ff880000 {
- compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xff880000 0x0 0x1000>;
- rockchip,grf = <&grf>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
- dmas = <&dmac_bus 0>, <&dmac_bus 1>;
- dma-names = "tx", "rx";
- clock-names = "i2s_clk", "i2s_hclk";
- clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_8ch_bus>;
- power-domains = <&power RK3399_PD_SDIOAUDIO>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s1: i2s@ff890000 {
- compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xff890000 0x0 0x1000>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
- dmas = <&dmac_bus 2>, <&dmac_bus 3>;
- dma-names = "tx", "rx";
- clock-names = "i2s_clk", "i2s_hclk";
- clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1_2ch_bus>;
- power-domains = <&power RK3399_PD_SDIOAUDIO>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s2: i2s@ff8a0000 {
- compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xff8a0000 0x0 0x1000>;
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
- dmas = <&dmac_bus 4>, <&dmac_bus 5>;
- dma-names = "tx", "rx";
- clock-names = "i2s_clk", "i2s_hclk";
- clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
- power-domains = <&power RK3399_PD_SDIOAUDIO>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- vopl: vop@ff8f0000 {
- compatible = "rockchip,rk3399-vop-lit";
- reg = <0x0 0xff8f0000 0x0 0x3efc>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
- assigned-clock-rates = <400000000>, <100000000>;
- clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
- clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
- iommus = <&vopl_mmu>;
- power-domains = <&power RK3399_PD_VOPL>;
- resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
- reset-names = "axi", "ahb", "dclk";
- status = "disabled";
-
- vopl_out: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- vopl_out_mipi: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi_in_vopl>;
- };
-
- vopl_out_edp: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&edp_in_vopl>;
- };
-
- vopl_out_hdmi: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&hdmi_in_vopl>;
- };
-
- vopl_out_mipi1: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&mipi1_in_vopl>;
- };
-
- vopl_out_dp: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&dp_in_vopl>;
- };
- };
- };
-
- vopl_mmu: iommu@ff8f3f00 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff8f3f00 0x0 0x100>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vopl_mmu";
- clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3399_PD_VOPL>;
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- vopb: vop@ff900000 {
- compatible = "rockchip,rk3399-vop-big";
- reg = <0x0 0xff900000 0x0 0x3efc>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
- assigned-clock-rates = <400000000>, <100000000>;
- clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
- clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
- iommus = <&vopb_mmu>;
- power-domains = <&power RK3399_PD_VOPB>;
- resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
- reset-names = "axi", "ahb", "dclk";
- status = "disabled";
-
- vopb_out: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- vopb_out_edp: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&edp_in_vopb>;
- };
-
- vopb_out_mipi: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&mipi_in_vopb>;
- };
-
- vopb_out_hdmi: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&hdmi_in_vopb>;
- };
-
- vopb_out_mipi1: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&mipi1_in_vopb>;
- };
-
- vopb_out_dp: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&dp_in_vopb>;
- };
- };
- };
-
- vopb_mmu: iommu@ff903f00 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff903f00 0x0 0x100>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vopb_mmu";
- clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3399_PD_VOPB>;
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- isp0: isp0@ff910000 {
- compatible = "rockchip,rk3399-cif-isp";
- reg = <0x0 0xff910000 0x0 0x4000>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_ISP0>,
- <&cru ACLK_ISP0_WRAPPER>,
- <&cru HCLK_ISP0_WRAPPER>;
- clock-names = "isp", "aclk", "hclk";
- iommus = <&isp0_mmu>;
- phys = <&mipi_dphy_rx0>;
- phy-names = "dphy";
- power-domains = <&power RK3399_PD_ISP0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
- };
-
- isp0_mmu: iommu@ff914000 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "isp0_mmu";
- clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- power-domains = <&power RK3399_PD_ISP0>;
- rockchip,disable-mmu-reset;
- };
-
- isp1_mmu: iommu@ff924000 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "isp1_mmu";
- clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- power-domains = <&power RK3399_PD_ISP1>;
- rockchip,disable-mmu-reset;
- };
-
- hdmi_sound: hdmi-sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,name = "hdmi-sound";
- status = "disabled";
-
- simple-audio-card,cpu {
- sound-dai = <&i2s2>;
- };
- simple-audio-card,codec {
- sound-dai = <&hdmi>;
- };
- };
-
- hdmi: hdmi@ff940000 {
- compatible = "rockchip,rk3399-dw-hdmi";
- reg = <0x0 0xff940000 0x0 0x20000>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru PCLK_HDMI_CTRL>,
- <&cru SCLK_HDMI_SFR>,
- <&cru PLL_VPLL>,
- <&cru PCLK_VIO_GRF>,
- <&cru SCLK_HDMI_CEC>;
- clock-names = "iahb", "isfr", "vpll", "grf", "cec";
- power-domains = <&power RK3399_PD_HDCP>;
- reg-io-width = <4>;
- rockchip,grf = <&grf>;
- #sound-dai-cells = <0>;
- status = "disabled";
-
- ports {
- hdmi_in: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- hdmi_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vopb_out_hdmi>;
- };
- hdmi_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_hdmi>;
- };
- };
- };
- };
-
- mipi_dsi: mipi@ff960000 {
- compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
- reg = <0x0 0xff960000 0x0 0x8000>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
- <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
- clock-names = "ref", "pclk", "phy_cfg", "grf";
- power-domains = <&power RK3399_PD_VIO>;
- resets = <&cru SRST_P_MIPI_DSI0>;
- reset-names = "apb";
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vopb_out_mipi>;
- };
- mipi_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_mipi>;
- };
- };
- };
- };
-
- mipi_dsi1: mipi@ff968000 {
- compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
- reg = <0x0 0xff968000 0x0 0x8000>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
- <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
- clock-names = "ref", "pclk", "phy_cfg", "grf";
- power-domains = <&power RK3399_PD_VIO>;
- resets = <&cru SRST_P_MIPI_DSI1>;
- reset-names = "apb";
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi1_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi1_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vopb_out_mipi1>;
- };
-
- mipi1_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_mipi1>;
- };
- };
- };
- };
-
- edp: edp@ff970000 {
- compatible = "rockchip,rk3399-edp";
- reg = <0x0 0xff970000 0x0 0x8000>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
- clock-names = "dp", "pclk", "grf";
- pinctrl-names = "default";
- pinctrl-0 = <&edp_hpd>;
- power-domains = <&power RK3399_PD_EDP>;
- resets = <&cru SRST_P_EDP_CTRL>;
- reset-names = "dp";
- rockchip,grf = <&grf>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- edp_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- edp_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vopb_out_edp>;
- };
-
- edp_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_edp>;
- };
- };
- };
- };
-
- gpu: gpu@ff9a0000 {
- compatible = "rockchip,rk3399-mali", "arm,mali-t860";
- reg = <0x0 0xff9a0000 0x0 0x10000>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "job", "mmu", "gpu";
- clocks = <&cru ACLK_GPU>;
- #cooling-cells = <2>;
- power-domains = <&power RK3399_PD_GPU>;
- status = "disabled";
- };
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3399-pinctrl";
- rockchip,grf = <&grf>;
- rockchip,pmu = <&pmugrf>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio0@ff720000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff720000 0x0 0x100>;
- clocks = <&pmucru PCLK_GPIO0_PMU>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
-
- gpio-controller;
- #gpio-cells = <0x2>;
-
- interrupt-controller;
- #interrupt-cells = <0x2>;
- };
-
- gpio1: gpio1@ff730000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff730000 0x0 0x100>;
- clocks = <&pmucru PCLK_GPIO1_PMU>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
-
- gpio-controller;
- #gpio-cells = <0x2>;
-
- interrupt-controller;
- #interrupt-cells = <0x2>;
- };
-
- gpio2: gpio2@ff780000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff780000 0x0 0x100>;
- clocks = <&cru PCLK_GPIO2>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
-
- gpio-controller;
- #gpio-cells = <0x2>;
-
- interrupt-controller;
- #interrupt-cells = <0x2>;
- };
-
- gpio3: gpio3@ff788000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff788000 0x0 0x100>;
- clocks = <&cru PCLK_GPIO3>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
-
- gpio-controller;
- #gpio-cells = <0x2>;
-
- interrupt-controller;
- #interrupt-cells = <0x2>;
- };
-
- gpio4: gpio4@ff790000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff790000 0x0 0x100>;
- clocks = <&cru PCLK_GPIO4>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
-
- gpio-controller;
- #gpio-cells = <0x2>;
-
- interrupt-controller;
- #interrupt-cells = <0x2>;
- };
-
- pcfg_pull_up: pcfg-pull-up {
- bias-pull-up;
- };
-
- pcfg_pull_down: pcfg-pull-down {
- bias-pull-down;
- };
-
- pcfg_pull_none: pcfg-pull-none {
- bias-disable;
- };
-
- pcfg_pull_none_12ma: pcfg-pull-none-12ma {
- bias-disable;
- drive-strength = <12>;
- };
-
- pcfg_pull_none_13ma: pcfg-pull-none-13ma {
- bias-disable;
- drive-strength = <13>;
- };
-
- pcfg_pull_none_18ma: pcfg-pull-none-18ma {
- bias-disable;
- drive-strength = <18>;
- };
-
- pcfg_pull_none_20ma: pcfg-pull-none-20ma {
- bias-disable;
- drive-strength = <20>;
- };
-
- pcfg_pull_up_2ma: pcfg-pull-up-2ma {
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pcfg_pull_up_8ma: pcfg-pull-up-8ma {
- bias-pull-up;
- drive-strength = <8>;
- };
-
- pcfg_pull_up_18ma: pcfg-pull-up-18ma {
- bias-pull-up;
- drive-strength = <18>;
- };
-
- pcfg_pull_up_20ma: pcfg-pull-up-20ma {
- bias-pull-up;
- drive-strength = <20>;
- };
-
- pcfg_pull_down_4ma: pcfg-pull-down-4ma {
- bias-pull-down;
- drive-strength = <4>;
- };
-
- pcfg_pull_down_8ma: pcfg-pull-down-8ma {
- bias-pull-down;
- drive-strength = <8>;
- };
-
- pcfg_pull_down_12ma: pcfg-pull-down-12ma {
- bias-pull-down;
- drive-strength = <12>;
- };
-
- pcfg_pull_down_18ma: pcfg-pull-down-18ma {
- bias-pull-down;
- drive-strength = <18>;
- };
-
- pcfg_pull_down_20ma: pcfg-pull-down-20ma {
- bias-pull-down;
- drive-strength = <20>;
- };
-
- pcfg_output_high: pcfg-output-high {
- output-high;
- };
-
- pcfg_output_low: pcfg-output-low {
- output-low;
- };
-
- clock {
- clk_32k: clk-32k {
- rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
- };
- };
-
- edp {
- edp_hpd: edp-hpd {
- rockchip,pins =
- <4 RK_PC7 2 &pcfg_pull_none>;
- };
- };
-
- gmac {
- rgmii_pins: rgmii-pins {
- rockchip,pins =
- /* mac_txclk */
- <3 RK_PC1 1 &pcfg_pull_none_13ma>,
- /* mac_rxclk */
- <3 RK_PB6 1 &pcfg_pull_none>,
- /* mac_mdio */
- <3 RK_PB5 1 &pcfg_pull_none>,
- /* mac_txen */
- <3 RK_PB4 1 &pcfg_pull_none_13ma>,
- /* mac_clk */
- <3 RK_PB3 1 &pcfg_pull_none>,
- /* mac_rxdv */
- <3 RK_PB1 1 &pcfg_pull_none>,
- /* mac_mdc */
- <3 RK_PB0 1 &pcfg_pull_none>,
- /* mac_rxd1 */
- <3 RK_PA7 1 &pcfg_pull_none>,
- /* mac_rxd0 */
- <3 RK_PA6 1 &pcfg_pull_none>,
- /* mac_txd1 */
- <3 RK_PA5 1 &pcfg_pull_none_13ma>,
- /* mac_txd0 */
- <3 RK_PA4 1 &pcfg_pull_none_13ma>,
- /* mac_rxd3 */
- <3 RK_PA3 1 &pcfg_pull_none>,
- /* mac_rxd2 */
- <3 RK_PA2 1 &pcfg_pull_none>,
- /* mac_txd3 */
- <3 RK_PA1 1 &pcfg_pull_none_13ma>,
- /* mac_txd2 */
- <3 RK_PA0 1 &pcfg_pull_none_13ma>;
- };
-
- rmii_pins: rmii-pins {
- rockchip,pins =
- /* mac_mdio */
- <3 RK_PB5 1 &pcfg_pull_none>,
- /* mac_txen */
- <3 RK_PB4 1 &pcfg_pull_none_13ma>,
- /* mac_clk */
- <3 RK_PB3 1 &pcfg_pull_none>,
- /* mac_rxer */
- <3 RK_PB2 1 &pcfg_pull_none>,
- /* mac_rxdv */
- <3 RK_PB1 1 &pcfg_pull_none>,
- /* mac_mdc */
- <3 RK_PB0 1 &pcfg_pull_none>,
- /* mac_rxd1 */
- <3 RK_PA7 1 &pcfg_pull_none>,
- /* mac_rxd0 */
- <3 RK_PA6 1 &pcfg_pull_none>,
- /* mac_txd1 */
- <3 RK_PA5 1 &pcfg_pull_none_13ma>,
- /* mac_txd0 */
- <3 RK_PA4 1 &pcfg_pull_none_13ma>;
- };
- };
-
- i2c0 {
- i2c0_xfer: i2c0-xfer {
- rockchip,pins =
- <1 RK_PB7 2 &pcfg_pull_none>,
- <1 RK_PC0 2 &pcfg_pull_none>;
- };
- };
-
- i2c1 {
- i2c1_xfer: i2c1-xfer {
- rockchip,pins =
- <4 RK_PA2 1 &pcfg_pull_none>,
- <4 RK_PA1 1 &pcfg_pull_none>;
- };
- };
-
- i2c2 {
- i2c2_xfer: i2c2-xfer {
- rockchip,pins =
- <2 RK_PA1 2 &pcfg_pull_none_12ma>,
- <2 RK_PA0 2 &pcfg_pull_none_12ma>;
- };
- };
-
- i2c3 {
- i2c3_xfer: i2c3-xfer {
- rockchip,pins =
- <4 RK_PC1 1 &pcfg_pull_none>,
- <4 RK_PC0 1 &pcfg_pull_none>;
- };
- };
-
- i2c4 {
- i2c4_xfer: i2c4-xfer {
- rockchip,pins =
- <1 RK_PB4 1 &pcfg_pull_none>,
- <1 RK_PB3 1 &pcfg_pull_none>;
- };
- };
-
- i2c5 {
- i2c5_xfer: i2c5-xfer {
- rockchip,pins =
- <3 RK_PB3 2 &pcfg_pull_none>,
- <3 RK_PB2 2 &pcfg_pull_none>;
- };
- };
-
- i2c6 {
- i2c6_xfer: i2c6-xfer {
- rockchip,pins =
- <2 RK_PB2 2 &pcfg_pull_none>,
- <2 RK_PB1 2 &pcfg_pull_none>;
- };
- };
-
- i2c7 {
- i2c7_xfer: i2c7-xfer {
- rockchip,pins =
- <2 RK_PB0 2 &pcfg_pull_none>,
- <2 RK_PA7 2 &pcfg_pull_none>;
- };
- };
-
- i2c8 {
- i2c8_xfer: i2c8-xfer {
- rockchip,pins =
- <1 RK_PC5 1 &pcfg_pull_none>,
- <1 RK_PC4 1 &pcfg_pull_none>;
- };
- };
-
- i2s0 {
- i2s0_2ch_bus: i2s0-2ch-bus {
- rockchip,pins =
- <3 RK_PD0 1 &pcfg_pull_none>,
- <3 RK_PD1 1 &pcfg_pull_none>,
- <3 RK_PD2 1 &pcfg_pull_none>,
- <3 RK_PD3 1 &pcfg_pull_none>,
- <3 RK_PD7 1 &pcfg_pull_none>,
- <4 RK_PA0 1 &pcfg_pull_none>;
- };
-
- i2s0_8ch_bus: i2s0-8ch-bus {
- rockchip,pins =
- <3 RK_PD0 1 &pcfg_pull_none>,
- <3 RK_PD1 1 &pcfg_pull_none>,
- <3 RK_PD2 1 &pcfg_pull_none>,
- <3 RK_PD3 1 &pcfg_pull_none>,
- <3 RK_PD4 1 &pcfg_pull_none>,
- <3 RK_PD5 1 &pcfg_pull_none>,
- <3 RK_PD6 1 &pcfg_pull_none>,
- <3 RK_PD7 1 &pcfg_pull_none>,
- <4 RK_PA0 1 &pcfg_pull_none>;
- };
- };
-
- i2s1 {
- i2s1_2ch_bus: i2s1-2ch-bus {
- rockchip,pins =
- <4 RK_PA3 1 &pcfg_pull_none>,
- <4 RK_PA4 1 &pcfg_pull_none>,
- <4 RK_PA5 1 &pcfg_pull_none>,
- <4 RK_PA6 1 &pcfg_pull_none>,
- <4 RK_PA7 1 &pcfg_pull_none>;
- };
- };
-
- sdio0 {
- sdio0_bus1: sdio0-bus1 {
- rockchip,pins =
- <2 RK_PC4 1 &pcfg_pull_up>;
- };
-
- sdio0_bus4: sdio0-bus4 {
- rockchip,pins =
- <2 RK_PC4 1 &pcfg_pull_up>,
- <2 RK_PC5 1 &pcfg_pull_up>,
- <2 RK_PC6 1 &pcfg_pull_up>,
- <2 RK_PC7 1 &pcfg_pull_up>;
- };
-
- sdio0_cmd: sdio0-cmd {
- rockchip,pins =
- <2 RK_PD0 1 &pcfg_pull_up>;
- };
-
- sdio0_clk: sdio0-clk {
- rockchip,pins =
- <2 RK_PD1 1 &pcfg_pull_none>;
- };
-
- sdio0_cd: sdio0-cd {
- rockchip,pins =
- <2 RK_PD2 1 &pcfg_pull_up>;
- };
-
- sdio0_pwr: sdio0-pwr {
- rockchip,pins =
- <2 RK_PD3 1 &pcfg_pull_up>;
- };
-
- sdio0_bkpwr: sdio0-bkpwr {
- rockchip,pins =
- <2 RK_PD4 1 &pcfg_pull_up>;
- };
-
- sdio0_wp: sdio0-wp {
- rockchip,pins =
- <0 RK_PA3 1 &pcfg_pull_up>;
- };
-
- sdio0_int: sdio0-int {
- rockchip,pins =
- <0 RK_PA4 1 &pcfg_pull_up>;
- };
- };
-
- sdmmc {
- sdmmc_bus1: sdmmc-bus1 {
- rockchip,pins =
- <4 RK_PB0 1 &pcfg_pull_up>;
- };
-
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins =
- <4 RK_PB0 1 &pcfg_pull_up>,
- <4 RK_PB1 1 &pcfg_pull_up>,
- <4 RK_PB2 1 &pcfg_pull_up>,
- <4 RK_PB3 1 &pcfg_pull_up>;
- };
-
- sdmmc_clk: sdmmc-clk {
- rockchip,pins =
- <4 RK_PB4 1 &pcfg_pull_none>;
- };
-
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins =
- <4 RK_PB5 1 &pcfg_pull_up>;
- };
-
- sdmmc_cd: sdmmc-cd {
- rockchip,pins =
- <0 RK_PA7 1 &pcfg_pull_up>;
- };
-
- sdmmc_wp: sdmmc-wp {
- rockchip,pins =
- <0 RK_PB0 1 &pcfg_pull_up>;
- };
- };
-
- suspend {
- ap_pwroff: ap-pwroff {
- rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
- };
-
- ddrio_pwroff: ddrio-pwroff {
- rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
- };
- };
-
- spdif {
- spdif_bus: spdif-bus {
- rockchip,pins =
- <4 RK_PC5 1 &pcfg_pull_none>;
- };
-
- spdif_bus_1: spdif-bus-1 {
- rockchip,pins =
- <3 RK_PC0 3 &pcfg_pull_none>;
- };
- };
-
- spi0 {
- spi0_clk: spi0-clk {
- rockchip,pins =
- <3 RK_PA6 2 &pcfg_pull_up>;
- };
- spi0_cs0: spi0-cs0 {
- rockchip,pins =
- <3 RK_PA7 2 &pcfg_pull_up>;
- };
- spi0_cs1: spi0-cs1 {
- rockchip,pins =
- <3 RK_PB0 2 &pcfg_pull_up>;
- };
- spi0_tx: spi0-tx {
- rockchip,pins =
- <3 RK_PA5 2 &pcfg_pull_up>;
- };
- spi0_rx: spi0-rx {
- rockchip,pins =
- <3 RK_PA4 2 &pcfg_pull_up>;
- };
- };
-
- spi1 {
- spi1_clk: spi1-clk {
- rockchip,pins =
- <1 RK_PB1 2 &pcfg_pull_up>;
- };
- spi1_cs0: spi1-cs0 {
- rockchip,pins =
- <1 RK_PB2 2 &pcfg_pull_up>;
- };
- spi1_rx: spi1-rx {
- rockchip,pins =
- <1 RK_PA7 2 &pcfg_pull_up>;
- };
- spi1_tx: spi1-tx {
- rockchip,pins =
- <1 RK_PB0 2 &pcfg_pull_up>;
- };
- };
-
- spi2 {
- spi2_clk: spi2-clk {
- rockchip,pins =
- <2 RK_PB3 1 &pcfg_pull_up>;
- };
- spi2_cs0: spi2-cs0 {
- rockchip,pins =
- <2 RK_PB4 1 &pcfg_pull_up>;
- };
- spi2_rx: spi2-rx {
- rockchip,pins =
- <2 RK_PB1 1 &pcfg_pull_up>;
- };
- spi2_tx: spi2-tx {
- rockchip,pins =
- <2 RK_PB2 1 &pcfg_pull_up>;
- };
- };
-
- spi3 {
- spi3_clk: spi3-clk {
- rockchip,pins =
- <1 RK_PC1 1 &pcfg_pull_up>;
- };
- spi3_cs0: spi3-cs0 {
- rockchip,pins =
- <1 RK_PC2 1 &pcfg_pull_up>;
- };
- spi3_rx: spi3-rx {
- rockchip,pins =
- <1 RK_PB7 1 &pcfg_pull_up>;
- };
- spi3_tx: spi3-tx {
- rockchip,pins =
- <1 RK_PC0 1 &pcfg_pull_up>;
- };
- };
-
- spi4 {
- spi4_clk: spi4-clk {
- rockchip,pins =
- <3 RK_PA2 2 &pcfg_pull_up>;
- };
- spi4_cs0: spi4-cs0 {
- rockchip,pins =
- <3 RK_PA3 2 &pcfg_pull_up>;
- };
- spi4_rx: spi4-rx {
- rockchip,pins =
- <3 RK_PA0 2 &pcfg_pull_up>;
- };
- spi4_tx: spi4-tx {
- rockchip,pins =
- <3 RK_PA1 2 &pcfg_pull_up>;
- };
- };
-
- spi5 {
- spi5_clk: spi5-clk {
- rockchip,pins =
- <2 RK_PC6 2 &pcfg_pull_up>;
- };
- spi5_cs0: spi5-cs0 {
- rockchip,pins =
- <2 RK_PC7 2 &pcfg_pull_up>;
- };
- spi5_rx: spi5-rx {
- rockchip,pins =
- <2 RK_PC4 2 &pcfg_pull_up>;
- };
- spi5_tx: spi5-tx {
- rockchip,pins =
- <2 RK_PC5 2 &pcfg_pull_up>;
- };
- };
-
- testclk {
- test_clkout0: test-clkout0 {
- rockchip,pins =
- <0 RK_PA0 1 &pcfg_pull_none>;
- };
-
- test_clkout1: test-clkout1 {
- rockchip,pins =
- <2 RK_PD1 2 &pcfg_pull_none>;
- };
-
- test_clkout2: test-clkout2 {
- rockchip,pins =
- <0 RK_PB0 3 &pcfg_pull_none>;
- };
- };
-
- tsadc {
- otp_pin: otp-pin {
- rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- otp_out: otp-out {
- rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
- };
- };
-
- uart0 {
- uart0_xfer: uart0-xfer {
- rockchip,pins =
- <2 RK_PC0 1 &pcfg_pull_up>,
- <2 RK_PC1 1 &pcfg_pull_none>;
- };
-
- uart0_cts: uart0-cts {
- rockchip,pins =
- <2 RK_PC2 1 &pcfg_pull_none>;
- };
-
- uart0_rts: uart0-rts {
- rockchip,pins =
- <2 RK_PC3 1 &pcfg_pull_none>;
- };
- };
-
- uart1 {
- uart1_xfer: uart1-xfer {
- rockchip,pins =
- <3 RK_PB4 2 &pcfg_pull_up>,
- <3 RK_PB5 2 &pcfg_pull_none>;
- };
- };
-
- uart2a {
- uart2a_xfer: uart2a-xfer {
- rockchip,pins =
- <4 RK_PB0 2 &pcfg_pull_up>,
- <4 RK_PB1 2 &pcfg_pull_none>;
- };
- };
-
- uart2b {
- uart2b_xfer: uart2b-xfer {
- rockchip,pins =
- <4 RK_PC0 2 &pcfg_pull_up>,
- <4 RK_PC1 2 &pcfg_pull_none>;
- };
- };
-
- uart2c {
- uart2c_xfer: uart2c-xfer {
- rockchip,pins =
- <4 RK_PC3 1 &pcfg_pull_up>,
- <4 RK_PC4 1 &pcfg_pull_none>;
- };
- };
-
- uart3 {
- uart3_xfer: uart3-xfer {
- rockchip,pins =
- <3 RK_PB6 2 &pcfg_pull_up>,
- <3 RK_PB7 2 &pcfg_pull_none>;
- };
-
- uart3_cts: uart3-cts {
- rockchip,pins =
- <3 RK_PC0 2 &pcfg_pull_none>;
- };
-
- uart3_rts: uart3-rts {
- rockchip,pins =
- <3 RK_PC1 2 &pcfg_pull_none>;
- };
- };
-
- uart4 {
- uart4_xfer: uart4-xfer {
- rockchip,pins =
- <1 RK_PA7 1 &pcfg_pull_up>,
- <1 RK_PB0 1 &pcfg_pull_none>;
- };
- };
-
- uarthdcp {
- uarthdcp_xfer: uarthdcp-xfer {
- rockchip,pins =
- <4 RK_PC5 2 &pcfg_pull_up>,
- <4 RK_PC6 2 &pcfg_pull_none>;
- };
- };
-
- pwm0 {
- pwm0_pin: pwm0-pin {
- rockchip,pins =
- <4 RK_PC2 1 &pcfg_pull_none>;
- };
-
- pwm0_pin_pull_down: pwm0-pin-pull-down {
- rockchip,pins =
- <4 RK_PC2 1 &pcfg_pull_down>;
- };
-
- vop0_pwm_pin: vop0-pwm-pin {
- rockchip,pins =
- <4 RK_PC2 2 &pcfg_pull_none>;
- };
-
- vop1_pwm_pin: vop1-pwm-pin {
- rockchip,pins =
- <4 RK_PC2 3 &pcfg_pull_none>;
- };
- };
-
- pwm1 {
- pwm1_pin: pwm1-pin {
- rockchip,pins =
- <4 RK_PC6 1 &pcfg_pull_none>;
- };
-
- pwm1_pin_pull_down: pwm1-pin-pull-down {
- rockchip,pins =
- <4 RK_PC6 1 &pcfg_pull_down>;
- };
- };
-
- pwm2 {
- pwm2_pin: pwm2-pin {
- rockchip,pins =
- <1 RK_PC3 1 &pcfg_pull_none>;
- };
-
- pwm2_pin_pull_down: pwm2-pin-pull-down {
- rockchip,pins =
- <1 RK_PC3 1 &pcfg_pull_down>;
- };
- };
-
- pwm3a {
- pwm3a_pin: pwm3a-pin {
- rockchip,pins =
- <0 RK_PA6 1 &pcfg_pull_none>;
- };
- };
-
- pwm3b {
- pwm3b_pin: pwm3b-pin {
- rockchip,pins =
- <1 RK_PB6 1 &pcfg_pull_none>;
- };
- };
-
- hdmi {
- hdmi_i2c_xfer: hdmi-i2c-xfer {
- rockchip,pins =
- <4 RK_PC1 3 &pcfg_pull_none>,
- <4 RK_PC0 3 &pcfg_pull_none>;
- };
-
- hdmi_cec: hdmi-cec {
- rockchip,pins =
- <4 RK_PC7 1 &pcfg_pull_none>;
- };
- };
-
- pcie {
- pcie_clkreqn_cpm: pci-clkreqn-cpm {
- rockchip,pins =
- <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
- rockchip,pins =
- <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- };
-};
#include "rk3399pro-u-boot.dtsi"
#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
-
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2019 Radxa Limited
- * Copyright (c) 2019 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
-#include <rockchip-radxa-dalang-carrier.dtsi>
-#include "rk3399pro-vmarc-som.dtsi"
-
-/ {
- model = "Radxa ROCK Pi N10";
- compatible = "radxa,rockpi-n10", "vamrs,rk3399pro-vmarc-som",
- "rockchip,rk3399pro";
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2019 Vamrs Limited
- * Copyright (c) 2019 Amarula Solutions(India)
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
- compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
-
- aliases {
- mmc0 = &sdmmc;
- mmc1 = &sdhci;
- };
-
- vcc3v3_pcie: vcc-pcie-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pwr>;
- regulator-name = "vcc3v3_pcie";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_l>;
-};
-
-&emmc_phy {
- status = "okay";
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_RMII_SRC>;
- phy-supply = <&vcc_lan>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c3>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_cec>;
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-falling-time-ns = <30>;
- i2c-scl-rising-time-ns = <180>;
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PC2 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc_buck5>;
- vcc6-supply = <&vcc_buck5>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
-
- regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc3v3_sys: DCDC_REG4 {
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_buck5: DCDC_REG5 {
- regulator-name = "vcc_buck5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2200000>;
- regulator-max-microvolt = <2200000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2200000>;
- };
- };
-
- vcca_0v9: LDO_REG1 {
- regulator-name = "vcca_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vcc_1v8: LDO_REG2 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_0v9: LDO_REG3 {
- regulator-name = "vcc_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vcca_1v8: LDO_REG4 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1850000>;
- regulator-max-microvolt = <1850000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1850000>;
- };
- };
-
- /*
- * As per BSP, but schematic not showing any regulator
- * pin for LD05.
- */
- vdd1v5_dvp: LDO_REG5 {
- regulator-name = "vdd1v5_dvp";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_3v0: LDO_REG7 {
- regulator-name = "vccio_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG8 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- /*
- * As per BSP, but schematic not showing any regulator
- * pin for LD09.
- */
- vcc_sd: LDO_REG9 {
- regulator-name = "vcc_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc5v0_usb2: SWITCH_REG1 {
- regulator-name = "vcc5v0_usb2";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <5000000>;
- };
- };
-
- vccio_3v3: vcc_lan: SWITCH_REG2 {
- regulator-name = "vccio_3v3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&i2c1 {
- i2c-scl-falling-time-ns = <30>;
- i2c-scl-rising-time-ns = <140>;
- status = "okay";
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- status = "okay";
-
- hym8563: hym8563@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- interrupt-parent = <&gpio4>;
- interrupts = <RK_PD6 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
-};
-
-&io_domains {
- status = "okay";
- bt656-supply = <&vcca_1v8>;
- gpio1830-supply = <&vccio_3v0>;
- sdmmc-supply = <&vccio_sd>;
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-0 = <&pcie_clkreqnb_cpm>;
- pinctrl-names = "default";
- vpcie0v9-supply = <&vcca_0v9>; /* VCC_0V9_S0 */
- vpcie1v8-supply = <&vcca_1v8>; /* VCC_1V8_S0 */
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <4 RK_PD6 0 &pcfg_pull_up>;
- };
- };
-
- pcie {
- pcie_pwr: pcie-pwr {
- rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- vbus_host {
- usb1_en_oc: usb1-en-oc {
- rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- vbus_typec {
- usb0_en_oc: usb0-en-oc {
- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pmu_io_domains {
- status = "okay";
- pmu1830-supply = <&vcc_1v8>;
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- non-removable;
- status = "okay";
-};
-
-&sdmmc {
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
- max-frequency = <150000000>;
-};
-
-&tcphy0 {
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy0 {
- status = "okay";
-
- u2phy0_otg: otg-port {
- phy-supply = <&vbus_typec>;
- status = "okay";
- };
-
- u2phy0_host: host-port {
- phy-supply = <&vbus_host>;
- status = "okay";
- };
-};
-
-
-&u2phy1 {
- status = "okay";
-
- u2phy1_host: host-port {
- phy-supply = <&vbus_host>;
- status = "okay";
- };
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usbdrd3_0 {
- status = "okay";
-};
-
-&usbdrd_dwc3_0 {
- status = "okay";
-};
-
-&vbus_host {
- enable-active-high;
- gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_en_oc>;
-};
-
-&vbus_typec {
- enable-active-high;
- gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_en_oc>;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
-
-#include "rk3399.dtsi"
-
-/ {
- compatible = "rockchip,rk3399pro";
-};
-
-/* Default to enabled since AP talk to NPU part over pcie */
-&pcie_phy {
- status = "okay";
-};
-
-/* Default to enabled since AP talk to NPU part over pcie */
-&pcie0 {
- ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn_cpm>;
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3566.dtsi"
-
-/ {
- chosen: chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- adc-joystick {
- compatible = "adc-joystick";
- io-channels = <&adc_mux 0>,
- <&adc_mux 1>,
- <&adc_mux 2>,
- <&adc_mux 3>;
- pinctrl-0 = <&joy_mux_en>;
- pinctrl-names = "default";
- poll-interval = <60>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- axis@0 {
- reg = <0>;
- abs-flat = <32>;
- abs-fuzz = <32>;
- abs-range = <1023 15>;
- linux,code = <ABS_X>;
- };
-
- axis@1 {
- reg = <1>;
- abs-flat = <32>;
- abs-fuzz = <32>;
- abs-range = <15 1023>;
- linux,code = <ABS_RX>;
- };
-
- axis@2 {
- reg = <2>;
- abs-flat = <32>;
- abs-fuzz = <32>;
- abs-range = <15 1023>;
- linux,code = <ABS_Y>;
- };
-
- axis@3 {
- reg = <3>;
- abs-flat = <32>;
- abs-fuzz = <32>;
- abs-range = <1023 15>;
- linux,code = <ABS_RY>;
- };
- };
-
- adc_keys: adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <60>;
-
- /*
- * Button is mapped to F key in BSP kernel, but
- * according to input guidelines it should be mode.
- */
- button-mode {
- label = "MODE";
- linux,code = <BTN_MODE>;
- press-threshold-microvolt = <1750>;
- };
- };
-
- adc_mux: adc-mux {
- compatible = "io-channel-mux";
- channels = "left_x", "right_x", "left_y", "right_y";
- #io-channel-cells = <1>;
- io-channels = <&saradc 3>;
- io-channel-names = "parent";
- mux-controls = <&gpio_mux>;
- settle-time-us = <100>;
- };
-
- gpio_keys_control: gpio-keys-control {
- compatible = "gpio-keys";
- pinctrl-0 = <&btn_pins_ctrl>;
- pinctrl-names = "default";
-
- button-b {
- gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>;
- label = "SOUTH";
- linux,code = <BTN_SOUTH>;
- };
-
- button-down {
- gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
- label = "DPAD-DOWN";
- linux,code = <BTN_DPAD_DOWN>;
- };
-
- button-l1 {
- gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
- label = "TL";
- linux,code = <BTN_TL>;
- };
-
- button-l2 {
- gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
- label = "TL2";
- linux,code = <BTN_TL2>;
- };
-
- button-select {
- gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>;
- label = "SELECT";
- linux,code = <BTN_SELECT>;
- };
-
- button-start {
- gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;
- label = "START";
- linux,code = <BTN_START>;
- };
-
- button-thumbl {
- gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
- label = "THUMBL";
- linux,code = <BTN_THUMBL>;
- };
-
- button-thumbr {
- gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
- label = "THUMBR";
- linux,code = <BTN_THUMBR>;
- };
-
- button-up {
- gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
- label = "DPAD-UP";
- linux,code = <BTN_DPAD_UP>;
- };
-
- button-x {
- gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
- label = "NORTH";
- linux,code = <BTN_NORTH>;
- };
- };
-
- gpio_keys_vol: gpio-keys-vol {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-0 = <&btn_pins_vol>;
- pinctrl-names = "default";
-
- button-vol-down {
- gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
- label = "VOLUMEDOWN";
- linux,code = <KEY_VOLUMEDOWN>;
- };
-
- button-vol-up {
- gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
- label = "VOLUMEUP";
- linux,code = <KEY_VOLUMEUP>;
- };
- };
-
- gpio_mux: mux-controller {
- compatible = "gpio-mux";
- mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>,
- <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
- #mux-control-cells = <0>;
- };
-
- hdmi-con {
- compatible = "hdmi-connector";
- ddc-i2c-bus = <&i2c5>;
- type = "c";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- leds: pwm-leds {
- compatible = "pwm-leds";
-
- green_led: led-0 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "on";
- function = LED_FUNCTION_POWER;
- max-brightness = <255>;
- pwms = <&pwm6 0 25000 0>;
- };
-
- amber_led: led-1 {
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_CHARGING;
- max-brightness = <255>;
- pwms = <&pwm7 0 25000 0>;
- };
-
- red_led: led-2 {
- color = <LED_COLOR_ID_RED>;
- default-state = "off";
- function = LED_FUNCTION_STATUS;
- max-brightness = <255>;
- pwms = <&pwm0 0 25000 0>;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk817 1>;
- clock-names = "ext_clock";
- pinctrl-0 = <&wifi_enable_h>;
- pinctrl-names = "default";
- post-power-on-delay-ms = <200>;
- reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
- };
-
- vcc3v3_lcd0_n: regulator-vcc3v3-lcd0 {
- compatible = "regulator-fixed";
- gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- pinctrl-0 = <&vcc_lcd_h>;
- pinctrl-names = "default";
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3_lcd0_n";
- vin-supply = <&vcc_3v3>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_sys: regulator-vcc-sys {
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3800000>;
- regulator-max-microvolt = <3800000>;
- regulator-name = "vcc_sys";
- };
-
- vcc_wifi: regulator-vcc-wifi {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&vcc_wifi_h>;
- pinctrl-names = "default";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_wifi";
- };
-
- vibrator: pwm-vibrator {
- compatible = "pwm-vibrator";
- pwm-names = "enable";
- pwms = <&pwm5 0 1000000000 0>;
- };
-};
-
-&combphy1 {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c5>;
- pinctrl-0 = <&hdmitxm0_cec>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&hdmi_in {
- hdmi_in_vp0: endpoint {
- remote-endpoint = <&vp0_out_hdmi>;
- };
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- rk817: pmic@20 {
- compatible = "rockchip,rk817";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
- clock-names = "mclk";
- clocks = <&cru I2S1_MCLKOUT_TX>;
- assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
- assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
- #clock-cells = <1>;
- #sound-dai-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_mclk>, <&pmic_int_l>;
- wakeup-source;
-
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc5-supply = <&vcc_sys>;
- vcc6-supply = <&vcc_sys>;
- vcc7-supply = <&vcc_sys>;
- vcc8-supply = <&vcc_sys>;
- vcc9-supply = <&dcdc_boost>;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-initial-mode = <0x2>;
- regulator-name = "vdd_logic";
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-initial-mode = <0x2>;
- regulator-name = "vdd_gpu";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-name = "vcc_ddr";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_3v3: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-initial-mode = <0x2>;
- regulator-name = "vcc_3v3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca1v8_pmu: LDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcca1v8_pmu";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vdda_0v9";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vdda0v9_pmu";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_acodec";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_sd";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3_pmu";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_1v8: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_dvp: LDO_REG8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc1v8_dvp";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc2v8_dvp: LDO_REG9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-name = "vcc2v8_dvp";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- dcdc_boost: BOOST {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <4700000>;
- regulator-max-microvolt = <5400000>;
- regulator-name = "boost";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- otg_switch: OTG_SWITCH {
- regulator-name = "otg_switch";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu: regulator@40 {
- compatible = "fcs,fan53555";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1390000>;
- regulator-name = "vdd_cpu";
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc_sys>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c1 {
- /* Unknown/unused device at 0x3c */
- status = "disabled";
-};
-
-&i2c5 {
- pinctrl-0 = <&i2c5m1_xfer>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&i2s0_8ch {
- status = "okay";
-};
-
-&i2s1_8ch {
- pinctrl-0 = <&i2s1m0_sclktx
- &i2s1m0_lrcktx
- &i2s1m0_sdi0
- &i2s1m0_sdo0>;
- pinctrl-names = "default";
- rockchip,trcm-sync-tx-only;
- status = "okay";
-};
-
-&pinctrl {
- gpio-btns {
- btn_pins_ctrl: btn-pins-ctrl {
- rockchip,pins =
- <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- btn_pins_vol: btn-pins-vol {
- rockchip,pins =
- <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
- <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- joy-mux {
- joy_mux_en: joy-mux-en {
- rockchip,pins =
- <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_low>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins =
- <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins =
- <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- vcc3v3-lcd {
- vcc_lcd_h: vcc-lcd-h {
- rockchip,pins =
- <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- vcc-wifi {
- vcc_wifi_h: vcc-wifi-h {
- rockchip,pins =
- <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- status = "okay";
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc1v8_dvp>;
- vccio7-supply = <&vcc_3v3>;
-};
-
-&pwm0 {
- pinctrl-0 = <&pwm0m1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&pwm5 {
- status = "okay";
-};
-
-&pwm6 {
- status = "okay";
-};
-
-&pwm7 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- pinctrl-names = "default";
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&sdmmc1 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &sdmmc1_det>;
- pinctrl-names = "default";
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc1v8_dvp>;
- status = "okay";
-};
-
-&sdmmc2 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
- pinctrl-names = "default";
- vmmc-supply = <&vcc_wifi>;
- vqmmc-supply = <&vcca1v8_pmu>;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>;
- pinctrl-names = "default";
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt";
- device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
- enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
- host-wake-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-/*
- * Lack the schematics to verify, but port works as a peripheral
- * (and not a host or OTG port).
- */
-&usb_host0_xhci {
- dr_mode = "peripheral";
- phys = <&usb2phy0_otg>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usb_host1_xhci {
- phy-names = "usb2-phy", "usb3-phy";
- phys = <&usb2phy1_host>, <&combphy1 PHY_TYPE_USB3>;
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy0_otg {
- status = "okay";
-};
-
-&usb2phy1 {
- status = "okay";
-};
-
-&usb2phy1_host {
- status = "okay";
-};
-
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
- remote-endpoint = <&hdmi_in_vp0>;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = &sdmmc0, &sdhci;
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3566.dtsi"
-
-/ {
- model = "Pine64 RK3566 Quartz64-A Board";
- compatible = "pine64,quartz64-a", "rockchip,rk3566";
-
- aliases {
- ethernet0 = &gmac1;
- mmc0 = &sdmmc0;
- mmc1 = &sdhci;
- };
-
- chosen: chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- gmac1_clkin: external-gmac1-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "gmac1_clkin";
- #clock-cells = <0>;
- };
-
- fan: gpio_fan {
- compatible = "gpio-fan";
- gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map =
- < 0 0>,
- <4500 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&fan_en_h>;
- #cooling-cells = <2>;
- };
-
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-work {
- label = "work-led";
- default-state = "off";
- gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&work_led_enable_h>;
- retain-state-suspended;
- };
-
- led-diy {
- label = "diy-led";
- default-state = "on";
- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- pinctrl-names = "default";
- pinctrl-0 = <&diy_led_enable_h>;
- retain-state-suspended;
- };
- };
-
- rk817-sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,name = "Analog RK817";
- simple-audio-card,mclk-fs = <256>;
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1_8ch>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&rk817>;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk817 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- post-power-on-delay-ms = <100>;
- power-off-delay-us = <5000000>;
- reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
- };
-
- spdif_dit: spdif-dit {
- compatible = "linux,spdif-dit";
- #sound-dai-cells = <0>;
- };
-
- spdif_sound: spdif-sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "SPDIF";
-
- simple-audio-card,cpu {
- sound-dai = <&spdif>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&spdif_dit>;
- };
- };
-
- vcc12v_dcin: vcc12v_dcin {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- /* vbus feeds the rk817 usb input.
- * With no battery attached, also feeds vcc_bat+
- * via ON/OFF_BAT jumper
- */
- vbus: vbus {
- compatible = "regulator-fixed";
- regulator-name = "vbus";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_enable_h>;
- regulator-name = "vcc3v3_pcie_p";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_3v3>;
- };
-
- vcc5v0_usb: vcc5v0_usb {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- /* all four ports are controlled by one gpio
- * the host ports are sourced from vcc5v0_usb
- * the otg port is sourced from vcc5v0_midu
- */
- vcc5v0_usb20_host: vcc5v0_usb20_host {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb20_host_en>;
- regulator-name = "vcc5v0_usb20_host";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_usb20_otg: vcc5v0_usb20_otg {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc5v0_usb20_otg";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dcdc_boost>;
- };
-
- vcc3v3_sd: vcc3v3_sd {
- compatible = "regulator-fixed";
- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc_sd_h>;
- regulator-boot-on;
- regulator-name = "vcc3v3_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_3v3>;
- };
-
- /* sourced from vbus and vcc_bat+ via rk817 sw5 */
- vcc_sys: vcc_sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <4400000>;
- regulator-max-microvolt = <4400000>;
- vin-supply = <&vbus>;
- };
-
- /* sourced from vcc_sys, sdio module operates internally at 3.3v */
- vcc_wl: vcc_wl {
- compatible = "regulator-fixed";
- regulator-name = "vcc_wl";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_sys>;
- };
-};
-
-&combphy1 {
- status = "okay";
-};
-
-&combphy2 {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu_thermal {
- trips {
- cpu_hot: cpu_hot {
- temperature = <55000>;
- hysteresis = <2000>;
- type = "active";
- };
- };
-
- cooling-maps {
- map1 {
- trip = <&cpu_hot>;
- cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
-};
-
-&gmac1 {
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
- clock_in_out = "input";
- phy-supply = <&vcc_3v3>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1m0_miim
- &gmac1m0_tx_bus2
- &gmac1m0_rx_bus2
- &gmac1m0_rgmii_clk
- &gmac1m0_clkinout
- &gmac1m0_rgmii_bus>;
- snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f */
- snps,reset-delays-us = <0 20000 100000>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
- phy-handle = <&rgmii_phy1>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vdda_0v9>;
- avdd-1v8-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&hdmi_in {
- hdmi_in_vp0: endpoint {
- remote-endpoint = <&vp0_out_hdmi>;
- };
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <2300>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk817: pmic@20 {
- compatible = "rockchip,rk817";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
- assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
- clock-names = "mclk";
- clocks = <&cru I2S1_MCLKOUT_TX>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
- #clock-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
- rockchip,system-power-controller;
- #sound-dai-cells = <0>;
- wakeup-source;
-
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc5-supply = <&vcc_sys>;
- vcc6-supply = <&vcc_sys>;
- vcc7-supply = <&vcc_sys>;
- vcc8-supply = <&vcc_sys>;
- vcc9-supply = <&dcdc_boost>;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-initial-mode = <0x2>;
- regulator-name = "vdd_logic";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-initial-mode = <0x2>;
- regulator-name = "vdd_gpu";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-name = "vcc_ddr";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_3v3: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-initial-mode = <0x2>;
- regulator-name = "vcc_3v3";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_pmu: LDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcca1v8_pmu";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vdda_0v9";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vdda0v9_pmu";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_acodec";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_sd";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3_pmu";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_1v8: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_dvp: LDO_REG8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc1v8_dvp";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc2v8_dvp: LDO_REG9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-name = "vcc2v8_dvp";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- dcdc_boost: BOOST {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-name = "boost";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- otg_switch: OTG_SWITCH {
- regulator-name = "otg_switch";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-/* i2c3 is exposed on con40
- * pin 3 - i2c3_sda_m0, pullup to vcc_3v3
- * pin 5 - i2c3_scl_m0, pullup to vcc_3v3
- */
-&i2c3 {
- status = "okay";
-};
-
-&i2s0_8ch {
- status = "okay";
-};
-
-&i2s1_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_sclktx
- &i2s1m0_lrcktx
- &i2s1m0_sdi0
- &i2s1m0_sdo0>;
- rockchip,trcm-sync-tx-only;
- status = "okay";
-};
-
-&mdio1 {
- rgmii_phy1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
-};
-
-&pcie2x1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_reset_h>;
- reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie_p>;
- status = "okay";
-};
-
-&pinctrl {
- bt {
- bt_enable_h: bt-enable-h {
- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- fan {
- fan_en_h: fan-en-h {
- rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- leds {
- work_led_enable_h: work-led-enable-h {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- diy_led_enable_h: diy-led-enable-h {
- rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- pcie_enable_h: pcie-enable-h {
- rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_reset_h: pcie-reset-h {
- rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb2 {
- vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
- rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- vcc_sd {
- vcc_sd_h: vcc-sd-h {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio2-supply = <&vcc_1v8>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc1v8_dvp>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&sdmmc1 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_wl>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sfc {
- pinctrl-0 = <&fspi_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <1>;
- };
-};
-
-/* spdif is exposed on con40 pin 18 */
-&spdif {
- status = "okay";
-};
-
-/* spi1 is exposed on con40
- * pin 11 - spi1_mosi_m1
- * pin 13 - spi1_miso_m1
- * pin 15 - spi1_clk_m1
- * pin 17 - spi1_cs0_m1
- */
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
-};
-
-&tsadc {
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-/* uart0 is exposed on con40
- * pin 12 - uart0_tx
- * pin 14 - uart0_rx
- */
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
- status = "okay";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- clocks = <&rk817 1>;
- clock-names = "lpo";
- host-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
- device-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
- vbat-supply = <&vcc_sys>;
- vddio-supply = <&vcca1v8_pmu>;
- max-speed = <3000000>;
- };
-};
-
-/* uart2 is exposed on con40
- * pin 8 - uart2_tx_m0_debug
- * pin 10 - uart2_rx_m0_debug
- */
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usb_host0_xhci {
- dr_mode = "host";
- status = "okay";
-};
-
-/* usb3 controller is muxed with sata1 */
-&usb_host1_xhci {
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy0_host {
- phy-supply = <&vcc5v0_usb20_host>;
- status = "okay";
-};
-
-&usb2phy0_otg {
- phy-supply = <&vcc5v0_usb20_otg>;
- status = "okay";
-};
-
-&usb2phy1 {
- status = "okay";
-};
-
-&usb2phy1_host {
- phy-supply = <&vcc5v0_usb20_host>;
- status = "okay";
-};
-
-&usb2phy1_otg {
- phy-supply = <&vcc5v0_usb20_host>;
- status = "okay";
-};
-
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
- remote-endpoint = <&hdmi_in_vp0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3566.dtsi"
-
-/ {
- model = "Pine64 RK3566 Quartz64-B Board";
- compatible = "pine64,quartz64-b", "rockchip,rk3566";
-
- aliases {
- ethernet0 = &gmac1;
- mmc0 = &sdmmc0;
- mmc1 = &sdhci;
- mmc2 = &sdmmc1;
- };
-
- chosen: chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- gmac1_clkin: external-gmac1-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "gmac1_clkin";
- #clock-cells = <0>;
- };
-
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-user {
- label = "user-led";
- default-state = "on";
- gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- pinctrl-names = "default";
- pinctrl-0 = <&user_led_enable_h>;
- retain-state-suspended;
- };
- };
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,name = "Analog RK809";
- simple-audio-card,mclk-fs = <256>;
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1_8ch>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&rk809>;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- status = "okay";
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk809 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <100>;
- power-off-delay-us = <5000000>;
- };
-
- vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_enable_h>;
- regulator-name = "vcc3v3_pcie_p";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_3v3>;
- };
-
- vcc5v0_in: vcc5v0-in-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_in";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_in>;
- };
-
- vcc3v3_sys: vcc3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb30_host";
- enable-active-high;
- gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb30_host_en_h>;
- regulator-always-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb_otg";
- enable-active-high;
- gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_otg_en_h>;
- regulator-always-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&combphy1 {
- status = "okay";
-};
-
-&combphy2 {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&gmac1 {
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
- clock_in_out = "input";
- phy-mode = "rgmii";
- phy-supply = <&vcc_3v3>;
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1m1_miim
- &gmac1m1_tx_bus2
- &gmac1m1_rx_bus2
- &gmac1m1_rgmii_clk
- &gmac1m1_clkinout
- &gmac1m1_rgmii_bus>;
- snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f, also works well here */
- snps,reset-delays-us = <0 20000 100000>;
- tx_delay = <0x4f>;
- rx_delay = <0x24>;
- phy-handle = <&rgmii_phy1>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
- status = "okay";
-};
-
-&hdmi_in {
- hdmi_in_vp0: endpoint {
- remote-endpoint = <&vp0_out_hdmi>;
- };
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <2300>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
- assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
- clock-names = "mclk";
- clocks = <&cru I2S1_MCLKOUT_TX>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
- rockchip,system-power-controller;
- #sound-dai-cells = <0>;
- wakeup-source;
- #clock-cells = <1>;
-
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
-
- regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-name = "vdd_gpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vdd_npu: DCDC_REG4 {
- regulator-name = "vdd_npu";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1350000>;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdda0v9_image: LDO_REG1 {
- regulator-name = "vdda0v9_image";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-name = "vdda_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-name = "vdda0v9_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
-
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-name = "vcc3v3_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_1v8: LDO_REG7 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_pmu: LDO_REG8 {
- regulator-name = "vcca1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_image: LDO_REG9 {
- regulator-name = "vcca1v8_image";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_3v3: SWITCH_REG1 {
- regulator-boot-on;
- regulator-name = "vcc_3v3";
- };
-
- vcc3v3_sd: SWITCH_REG2 {
- regulator-name = "vcc3v3_sd";
- };
- };
- };
-};
-
-/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2m1_xfer>;
- status = "okay";
-};
-
-/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3m1_xfer>;
- status = "okay";
-};
-
-/*
- * i2c4_m0 is exposed on PI40, pulled up to vcc_3v3
- * pin 27 - i2c4_sda_m0
- * pin 28 - i2c4_scl_m0
- */
-&i2c4 {
- status = "okay";
-};
-
-/*
- * i2c5_m0 is exposed on PI40
- * pin 29 - i2c5_scl_m0
- * pin 31 - i2c5_sda_m0
- */
-&i2c5 {
- status = "disabled";
-};
-
-&i2s0_8ch {
- status = "okay";
-};
-
-&i2s1_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_sclktx
- &i2s1m0_lrcktx
- &i2s1m0_sdi0
- &i2s1m0_sdo0>;
- rockchip,trcm-sync-tx-only;
- status = "okay";
-};
-
-&mdio1 {
- rgmii_phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x1>;
- };
-};
-
-&pcie2x1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_reset_h>;
- reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie_p>;
- status = "okay";
-};
-
-&pinctrl {
- bt {
- bt_enable_h: bt-enable-h {
- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- leds {
- user_led_enable_h: user-led-enable-h {
- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- pcie_enable_h: pcie-enable-h {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_reset_h: pcie-reset-h {
- rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int: pmic_int {
- rockchip,pins =
- <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
- rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
- rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- status = "okay";
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcca1v8_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio2-supply = <&vcc_1v8>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcca1v8_pmu>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_3v3>;
- vccio7-supply = <&vcc_3v3>;
-};
-
-&saradc {
- vref-supply = <&vcca_1v8>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- sd-uhs-sdr50;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&sdmmc1 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
- vmmc-supply = <&vcc3v3_sys>;
- vqmmc-supply = <&vcca1v8_pmu>;
- status = "okay";
-};
-
-&sfc {
- pinctrl-0 = <&fspi_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <1>;
- };
-};
-
-&tsadc {
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
- status = "okay";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm4345c5";
- clocks = <&rk809 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
- vbat-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcca1v8_pmu>;
- };
-};
-
-/*
- * uart2_m0 is exposed on PI40
- * pin 8 - uart2_tx_m0
- * pin 10 - uart2_rx_m0
- */
-&uart2 {
- status = "okay";
-};
-
-&usb2phy0_host {
- phy-supply = <&vcc5v0_usb30_host>;
- status = "okay";
-};
-
-&usb2phy0_otg {
- phy-supply = <&vcc5v0_usb_otg>;
- status = "okay";
-};
-
-&usb2phy1_otg {
- phy-supply = <&vcc5v0_usb30_host>;
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy1 {
- status = "okay";
-};
-
-&usb_host0_xhci {
- status = "okay";
-};
-
-&usb_host1_xhci {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
- remote-endpoint = <&hdmi_in_vp0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Radxa Limited
- * Copyright (c) 2022 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3566.dtsi"
-#include "rk3566-radxa-cm3.dtsi"
-
-/ {
- model = "Radxa Compute Module 3(CM3) IO Board";
- compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
-
- aliases {
- ethernet0 = &gmac1;
- mmc1 = &sdmmc0;
- };
-
- chosen: chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- gmac1_clkin: external-gmac1-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "gmac1_clkin";
- #clock-cells = <0>;
- };
-
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-1 {
- gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_ACTIVITY;
- linux,default-trigger = "heartbeat";
- pinctrl-names = "default";
- pinctrl-0 = <&pi_nled_activity>;
- };
- };
-
- vcc5v0_usb30: vcc5v0-usb30-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb30";
- enable-active-high;
- gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb30_en_h>;
- regulator-always-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_sys>;
- };
-
- vcca1v8_image: vcca1v8-image-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcca1v8_image";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_1v8_p>;
- };
-
- vdda0v9_image: vdda0v9-image-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcca0v9_image";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- vin-supply = <&vdda_0v9>;
- };
-};
-
-&combphy1 {
- status = "okay";
-};
-
-&gmac1 {
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
- assigned-clock-rates = <0>, <125000000>;
- clock_in_out = "input";
- phy-handle = <&rgmii_phy1>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1m0_miim
- &gmac1m0_tx_bus2
- &gmac1m0_rx_bus2
- &gmac1m0_rgmii_clk
- &gmac1m0_rgmii_bus
- &gmac1m0_clkinout>;
- snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f */
- snps,reset-delays-us = <0 20000 100000>;
- tx_delay = <0x46>;
- rx_delay = <0x2e>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
- status = "okay";
-};
-
-&hdmi_in {
- hdmi_in_vp0: endpoint {
- remote-endpoint = <&vp0_out_hdmi>;
- };
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&mdio1 {
- rgmii_phy1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- };
-};
-
-&pinctrl {
- gmac1 {
- gmac1m0_miim: gmac1m0-miim {
- rockchip,pins =
- /* gmac1_mdcm0 */
- <3 RK_PC4 3 &pcfg_pull_none_drv_level_15>,
- /* gmac1_mdiom0 */
- <3 RK_PC5 3 &pcfg_pull_none_drv_level_15>;
- };
-
- gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
- rockchip,pins =
- /* gmac1_rxd0m0 */
- <3 RK_PB1 3 &pcfg_pull_none_drv_level_15>,
- /* gmac1_rxd1m0 */
- <3 RK_PB2 3 &pcfg_pull_none_drv_level_15>,
- /* gmac1_rxdvcrsm0 */
- <3 RK_PB3 3 &pcfg_pull_none_drv_level_15>;
- };
-
- gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
- rockchip,pins =
- /* gmac1_txd0m0 */
- <3 RK_PB5 3 &pcfg_pull_none_drv_level_15>,
- /* gmac1_txd1m0 */
- <3 RK_PB6 3 &pcfg_pull_none_drv_level_15>,
- /* gmac1_txenm0 */
- <3 RK_PB7 3 &pcfg_pull_none_drv_level_15>;
- };
-
- gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
- rockchip,pins =
- /* gmac1_rxclkm0 */
- <3 RK_PA7 3 &pcfg_pull_none_drv_level_15>,
- /* gmac1_txclkm0 */
- <3 RK_PA6 3 &pcfg_pull_none_drv_level_15>;
- };
-
- gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
- rockchip,pins =
- /* gmac1_rxd2m0 */
- <3 RK_PA4 3 &pcfg_pull_none_drv_level_15>,
- /* gmac1_rxd3m0 */
- <3 RK_PA5 3 &pcfg_pull_none_drv_level_15>,
- /* gmac1_txd2m0 */
- <3 RK_PA2 3 &pcfg_pull_none_drv_level_15>,
- /* gmac1_txd3m0 */
- <3 RK_PA3 3 &pcfg_pull_none_drv_level_15>;
- };
-
- gmac1m0_clkinout: gmac1m0-clkinout {
- rockchip,pins =
- /* gmac1_mclkinoutm0 */
- <3 RK_PC0 3 &pcfg_pull_none_drv_level_15>;
- };
- };
-
- leds {
- pi_nled_activity: pi-nled-activity {
- rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdcard {
- sdmmc_pwren: sdmmc-pwren {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- vcc5v0_usb30_en_h: vcc5v0-host-en-h {
- rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdmmc0 {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- vqmmc-supply = <&vccio_sd>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_pwren>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb2phy0_host {
- phy-supply = <&vcc5v0_usb30>;
- status = "okay";
-};
-
-&usb2phy1_host {
- status = "okay";
-};
-
-&usb2phy1_otg {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host1_xhci {
- status = "okay";
-};
-
-&usb2phy0_otg {
- status = "okay";
-};
-
-&usb_host0_xhci {
- status = "okay";
-};
-
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
- remote-endpoint = <&hdmi_in_vp0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Radxa Limited
- * Copyright (c) 2022 Amarula Solutions(India)
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- compatible = "radxa,cm3", "rockchip,rk3566";
-
- aliases {
- mmc0 = &sdhci;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- linux,default-trigger = "timer";
- default-state = "on";
- pinctrl-names = "default";
- pinctrl-0 = <&user_led2>;
- };
- };
-
- vcc_sys: vcc-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc_1v8: vcc-1v8-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_1v8_p>;
- };
-
- vcc_3v3: vcc-3v3-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- vcca_1v8: vcca-1v8-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_1v8_p>;
- };
-
- sdio_pwrseq: pwrseq-sdio {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk817 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_reg_on_h>;
- reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&gpu {
- mali-supply = <&vdd_gpu_npu>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1390000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk817: pmic@20 {
- compatible = "rockchip,rk817";
- reg = <0x20>;
- #clock-cells = <1>;
- clock-output-names = "rk817-clkout1", "rk817-clkout2";
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc5-supply = <&vcc_sys>;
- vcc6-supply = <&vcc_sys>;
- vcc7-supply = <&vcc_sys>;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdd_gpu_npu: DCDC_REG2 {
- regulator-name = "vdd_gpu_npu";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc3v3_sys: DCDC_REG4 {
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca1v8_pmu: LDO_REG1 {
- regulator-name = "vcca1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-name = "vdda_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-name = "vdda0v9_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-name = "vcc3v3_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_1v8_p: LDO_REG7 {
- regulator-name = "vcc_1v8_p";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_dvp: LDO_REG8 {
- regulator-name = "vcc1v8_dvp";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc2v8_dvp: LDO_REG9 {
- regulator-name = "vcc2v8_dvp";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- };
- };
-};
-
-&pinctrl {
- bluetooth {
- bt_host_wake_h: bt-host-wake-h {
- rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_reg_on_h: bt-reg-on-h {
- rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_host_h: bt-wake-host-h {
- rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- leds {
- user_led2: user-led2 {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wifi {
- wifi_reg_on_h: wifi-reg-on-h {
- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wifi_host_wake_h: wifi-host-wake-h {
- rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc_3v3>;
- vccio1-supply = <&vccio_acodec>;
- vccio2-supply = <&vcc_1v8>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_3v3>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca_1v8>;
- status = "okay";
-};
-
-&sdmmc1 {
- #address-cells = <1>;
- #size-cells = <0>;
- bus-width = <4>;
- disable-wp;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-
- wifi@1 {
- compatible = "brcm,bcm43455-fmac";
- reg = <1>;
- interrupt-parent = <&gpio2>;
- interrupts = <RK_PC1 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_h>;
- };
-};
-
-&sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4345c5";
- clocks = <&rk817 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>;
- vbat-supply = <&vcc_3v3>;
- vddio-supply = <&vcc_1v8>;
- };
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy1 {
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-
-#include "rk3566-soquartz.dtsi"
-
-/ {
- model = "PINE64 RK3566 SOQuartz on Blade carrier board";
- compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566";
-
- aliases {
- ethernet0 = &gmac1;
- };
-
- /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */
- vcc3v0_sd: vcc3v0-sd-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v0_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- /* labeled VCC_SSD in schematic */
- vcc3v3_pcie_p: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie_p";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vbus>;
- };
-
- vcc5v_dcin: vcc5v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-};
-
-&combphy2 {
- phy-supply = <&vcc3v3_sys>;
- status = "okay";
-};
-
-&gmac1 {
- status = "okay";
-};
-
-/*
- * i2c1 is exposed on CM1 / Module1A
- * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
- * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
- */
-&i2c1 {
- status = "okay";
-
-};
-
-/*
- * i2c2 is exposed on CM1 / Module1A - to PI40
- * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
- * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
- */
-&i2c2 {
- status = "disabled";
-};
-
-/*
- * i2c3 is exposed on CM1 / Module1A - to PI40
- * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
- * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
- */
-&i2c3 {
- status = "disabled";
-};
-
-/*
- * i2c4 is exposed on CM2 / Module1B - to PI40
- * pin 45 - GPIO24 - i2c4_scl_m1
- * pin 47 - GPIO23 - i2c4_sda_m1
- */
-&i2c4 {
- status = "disabled";
-};
-
-/*
- * i2s1_8ch is exposed on CM1 / Module1A - to PI40
- * pin 24 - GPIO26 - i2s1_sdi1_m1
- * pin 25 - GPIO21 - i2s1_sdo0_m1
- * pin 26 - GPIO19 - i2s1_lrck_tx_m1
- * pin 27 - GPIO20 - i2s1_sdi0_m1
- * pin 29 - GPIO16 - i2s1_sdi3_m1
- * pin 30 - GPIO6 - i2s1_sdi2_m1
- * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
- * pin 41 - GPIO25 - i2s1_sdo2_m1
- * pin 49 - GPIO18 - i2s1_sclk_tx_m1
- * pin 50 - GPIO17 - i2s1_mclk_m1
- * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
- */
-&i2s1_8ch {
- status = "disabled";
-};
-
-&led_diy {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_DISK_ACTIVITY;
- linux,default-trigger = "disk-activity";
- status = "okay";
-};
-
-&led_work {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- linux,default-trigger = "heartbeat";
- status = "okay";
-};
-
-&pcie2x1 {
- vpcie3v3-supply = <&vcc3v3_pcie_p>;
- status = "okay";
-};
-
-&rgmii_phy1 {
- status = "okay";
-};
-
-/*
- * saradc is exposed on CM1 / Module1A - to J2
- * pin 94 - AIN1 - saradc_vin3
- * pin 96 - AIN0 - saradc_vin2
- */
-&saradc {
- status = "disabled";
-};
-
-&sdmmc0 {
- vmmc-supply = <&vcc3v0_sd>;
- status = "okay";
-};
-
-/*
- * spi3 is exposed on CM1 / Module1A - to PI40
- * pin 37 - GPIO7 - spi3_cs1_m0
- * pin 38 - GPIO11 - spi3_clk_m0
- * pin 39 - GPIO8 - spi3_cs0_m0
- * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
- * pin 44 - GPIO10 - spi3_mosi_m0
- */
-&spi3 {
- status = "disabled";
-};
-
-/*
- * uart2 is exposed on CM1 / Module1A - to PI40
- * pin 51 - GPIO15 - uart2_rx_m0
- * pin 55 - GPIO14 - uart2_tx_m0
- */
-&uart2 {
- status = "okay";
-};
-
-/*
- * uart7 is exposed on CM1 / Module1A - to PI40
- * pin 46 - GPIO22 - uart7_tx_m2
- * pin 47 - GPIO23 - uart7_rx_m2
- */
-&uart7 {
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy0_otg {
- phy-supply = <&vbus>;
- status = "okay";
-};
-
-&usb_host0_xhci {
- status = "okay";
-};
-
-&vbus {
- vin-supply = <&vcc5v_dcin>;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include "rk3566-soquartz.dtsi"
-
-/ {
- model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
- compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566";
-
- aliases {
- ethernet0 = &gmac1;
- };
-
- /* labeled +12v in schematic */
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- /* labeled +5v in schematic */
- vcc_5v: vcc-5v-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_5v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc_sd_pwr: vcc-sd-pwr-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sd_pwr";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc3v3_sys>;
- };
-};
-
-/* phy for pcie */
-&combphy2 {
- phy-supply = <&vcc3v3_sys>;
- status = "okay";
-};
-
-&gmac1 {
- status = "okay";
-};
-
-/*
- * i2c1 is exposed on CM1 / Module1A
- * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
- * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
- */
-&i2c1 {
- status = "okay";
-
- /*
- * the rtc interrupt is tied to PMIC_PWRON,
- * it will force reset the board if triggered.
- */
- pcf85063: rtc@51 {
- compatible = "nxp,pcf85063";
- reg = <0x51>;
- };
-};
-
-/*
- * i2c2 is exposed on CM1 / Module1A - to PI40
- * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
- * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
- */
-&i2c2 {
- status = "disabled";
-};
-
-/*
- * i2c3 is exposed on CM1 / Module1A - to PI40
- * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
- * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
- */
-&i2c3 {
- status = "disabled";
-};
-
-/*
- * i2c4 is exposed on CM2 / Module1B - to PI40
- * pin 45 - GPIO24 - i2c4_scl_m1
- * pin 47 - GPIO23 - i2c4_sda_m1
- */
-&i2c4 {
- status = "disabled";
-};
-
-/*
- * i2s1_8ch is exposed on CM1 / Module1A - to PI40
- * pin 24 - GPIO26 - i2s1_sdi1_m1
- * pin 25 - GPIO21 - i2s1_sdo0_m1
- * pin 26 - GPIO19 - i2s1_lrck_tx_m1
- * pin 27 - GPIO20 - i2s1_sdi0_m1
- * pin 29 - GPIO16 - i2s1_sdi3_m1
- * pin 30 - GPIO6 - i2s1_sdi2_m1
- * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
- * pin 41 - GPIO25 - i2s1_sdo2_m1
- * pin 49 - GPIO18 - i2s1_sclk_tx_m1
- * pin 50 - GPIO17 - i2s1_mclk_m1
- * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
- */
-&i2s1_8ch {
- status = "disabled";
-};
-
-&led_diy {
- status = "okay";
-};
-
-&led_work {
- status = "okay";
-};
-
-&pcie2x1 {
- vpcie3v3-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&rgmii_phy1 {
- status = "okay";
-};
-
-/*
- * saradc is exposed on CM1 / Module1A - to J2
- * pin 94 - AIN1 - saradc_vin3
- * pin 96 - AIN0 - saradc_vin2
- */
-&saradc {
- status = "disabled";
-};
-
-&sdmmc0 {
- vmmc-supply = <&vcc_sd_pwr>;
- status = "okay";
-};
-
-/*
- * spi3 is exposed on CM1 / Module1A - to PI40
- * pin 37 - GPIO7 - spi3_cs1_m0
- * pin 38 - GPIO11 - spi3_clk_m0
- * pin 39 - GPIO8 - spi3_cs0_m0
- * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
- * pin 44 - GPIO10 - spi3_mosi_m0
- */
-&spi3 {
- status = "disabled";
-};
-
-/*
- * uart2 is exposed on CM1 / Module1A - to PI40
- * pin 51 - GPIO15 - uart2_rx_m0
- * pin 55 - GPIO14 - uart2_tx_m0
- */
-&uart2 {
- status = "okay";
-};
-
-/*
- * uart7 is exposed on CM1 / Module1A - to PI40
- * pin 46 - GPIO22 - uart7_tx_m2
- * pin 47 - GPIO23 - uart7_rx_m2
- */
-&uart7 {
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy0_otg {
- phy-supply = <&vcc_5v>;
- status = "okay";
-};
-
-&usb_host0_xhci {
- status = "okay";
-};
-
-&vbus {
- vin-supply = <&vcc_5v>;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include "rk3566-soquartz.dtsi"
-
-/ {
- model = "PINE64 RK3566 SOQuartz on Model A carrier board";
- compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566";
-
- aliases {
- ethernet0 = &gmac1;
- };
-
- /* labeled DCIN_12V in schematic */
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc5v0_usb: vcc5v0-usb-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- /*
- * Labelled VCC3V0_SD in schematic to not conflict with PMIC
- * regulator, it's 3.3v in actuality
- */
- vcc3v0_sd: vcc3v0-sd-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v0_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- vcc3v3_pcie: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc12v_pcie: vcc12v-pcie-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_pcie";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-};
-
-/* phy for pcie */
-&combphy2 {
- phy-supply = <&vcc3v3_sys>;
- status = "okay";
-};
-
-&gmac1 {
- status = "okay";
-};
-
-/*
- * i2c1 is exposed on CM1 / Module1A
- * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
- * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
- */
-&i2c1 {
- status = "okay";
-
- /*
- * the rtc interrupt is tied to PMIC_PWRON,
- * it will force reset the board if triggered.
- */
- pcf85063: rtc@51 {
- compatible = "nxp,pcf85063";
- reg = <0x51>;
- };
-};
-
-/*
- * i2c2 is exposed on CM1 / Module1A - to PI40
- * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
- * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
- */
-&i2c2 {
- status = "disabled";
-};
-
-/*
- * i2c3 is exposed on CM1 / Module1A - to PI40
- * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
- * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
- */
-&i2c3 {
- status = "disabled";
-};
-
-/*
- * i2c4 is exposed on CM2 / Module1B - to PI40
- * pin 45 - GPIO24 - i2c4_scl_m1
- * pin 47 - GPIO23 - i2c4_sda_m1
- */
-&i2c4 {
- status = "disabled";
-};
-
-/*
- * i2s1_8ch is exposed on CM1 / Module1A - to PI40
- * pin 24 - GPIO26 - i2s1_sdi1_m1
- * pin 25 - GPIO21 - i2s1_sdo0_m1
- * pin 26 - GPIO19 - i2s1_lrck_tx_m1
- * pin 27 - GPIO20 - i2s1_sdi0_m1
- * pin 29 - GPIO16 - i2s1_sdi3_m1
- * pin 30 - GPIO6 - i2s1_sdi2_m1
- * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
- * pin 41 - GPIO25 - i2s1_sdo2_m1
- * pin 49 - GPIO18 - i2s1_sclk_tx_m1
- * pin 50 - GPIO17 - i2s1_mclk_m1
- * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
- */
-&i2s1_8ch {
- status = "disabled";
-};
-
-&led_diy {
- status = "okay";
-};
-
-&led_work {
- status = "okay";
-};
-
-&pcie2x1 {
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&rgmii_phy1 {
- status = "okay";
-};
-
-&rgmii_phy1 {
- status = "okay";
-};
-
-/*
- * saradc is exposed on CM1 / Module1A - to J2
- * pin 94 - AIN1 - saradc_vin3
- * pin 96 - AIN0 - saradc_vin2
- */
-&saradc {
- status = "disabled";
-};
-
-/*
- * vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+
- * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys,
- * so we use vcc3v3_sd here to ensure the regulator is enabled on older boards.
- */
-&sdmmc0 {
- vmmc-supply = <&vcc3v3_sd>;
- status = "okay";
-};
-
-/*
- * spi3 is exposed on CM1 / Module1A - to PI40
- * pin 37 - GPIO7 - spi3_cs1_m0
- * pin 38 - GPIO11 - spi3_clk_m0
- * pin 39 - GPIO8 - spi3_cs0_m0
- * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
- * pin 44 - GPIO10 - spi3_mosi_m0
- */
-&spi3 {
- status = "disabled";
-};
-
-/*
- * uart2 is exposed on CM1 / Module1A - to PI40
- * pin 51 - GPIO15 - uart2_rx_m0
- * pin 55 - GPIO14 - uart2_tx_m0
- */
-&uart2 {
- status = "okay";
-};
-
-/*
- * uart7 is exposed on CM1 / Module1A - to PI40
- * pin 46 - GPIO22 - uart7_tx_m2
- * pin 47 - GPIO23 - uart7_rx_m2
- */
-&uart7 {
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy0_otg {
- phy-supply = <&vcc5v0_usb>;
- status = "okay";
-};
-
-&usb_host0_xhci {
- status = "okay";
-};
-
-&vbus {
- vin-supply = <&vcc5v0_usb>;
-};
-
-&vcc3v3_sd {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3566.dtsi"
-
-/ {
- model = "Pine64 RK3566 SoQuartz SOM";
- compatible = "pine64,soquartz", "rockchip,rk3566";
-
- aliases {
- mmc0 = &sdmmc0;
- mmc1 = &sdhci;
- mmc2 = &sdmmc1;
- };
-
- chosen: chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- gmac1_clkin: external-gmac1-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "gmac1_clkin";
- #clock-cells = <0>;
- };
-
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_diy: led-diy {
- label = "diy-led";
- default-state = "on";
- gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- pinctrl-names = "default";
- pinctrl-0 = <&diy_led_enable_h>;
- retain-state-suspended;
- status = "disabled";
- };
-
- led_work: led-work {
- label = "work-led";
- default-state = "off";
- gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&work_led_enable_h>;
- retain-state-suspended;
- status = "disabled";
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- status = "okay";
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk809 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
- };
-
- vbus: vbus-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vbus";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- /* sourced from vbus, vbus is provided by the carrier board */
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vbus>;
- };
-
- vcc3v3_sys: vcc3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&gmac1 {
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
- clock_in_out = "input";
- phy-supply = <&vcc_3v3>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1m0_miim
- &gmac1m0_tx_bus2
- &gmac1m0_rx_bus2
- &gmac1m0_rgmii_clk
- &gmac1m0_clkinout
- &gmac1m0_rgmii_bus>;
- snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f, also works well here */
- snps,reset-delays-us = <0 20000 100000>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
- phy-handle = <&rgmii_phy1>;
- status = "disabled";
-};
-
-&gpio0 {
- nextrst-hog {
- gpio-hog;
- /*
- * GPIO_ACTIVE_LOW + output-low here means that the pin is set
- * to high, because output-low decides the value pre-inversion.
- */
- gpios = <RK_PA5 GPIO_ACTIVE_LOW>;
- line-name = "nEXTRST";
- output-low;
- };
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
- status = "okay";
-};
-
-&hdmi_in {
- hdmi_in_vp0: endpoint {
- remote-endpoint = <&vp0_out_hdmi>;
- };
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <2300>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-name = "vdd_gpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-name = "vcc_ddr";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vdd_npu: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-initial-mode = <0x2>;
- regulator-name = "vdd_npu";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdda0v9_image: LDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vdda0v9_image";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vdda_0v9";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vdda0v9_pmu";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_acodec";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_sd";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc3v3_pmu";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_1v8: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcca_1v8";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_pmu: LDO_REG8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcca1v8_pmu";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_image: LDO_REG9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcca1v8_image";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3: SWITCH_REG1 {
- regulator-name = "vcc_3v3";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: SWITCH_REG2 {
- regulator-name = "vcc3v3_sd";
- status = "disabled";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- };
- };
-};
-
-/*
- * i2c1 is exposed on CM1 / Module1A
- * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu
- * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu
- */
-&i2c1 {
- status = "disabled";
-};
-
-/*
- * i2c2 is exposed on CM1 / Module1A
- * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
- * pin 58 - i2c2_sda_m1, pullup to vcc_3v3
- */
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2m1_xfer>;
- status = "disabled";
-};
-
-/*
- * i2c3 is exposed on CM1 / Module1A
- * pin 35 - i2c3_scl_m0, pullup to vcc_3v3
- * pin 36 - i2c3_sda_m0, pullup to vcc_3v3
- */
-&i2c3 {
- status = "disabled";
-};
-
-/*
- * i2c4 is exposed on CM2 / Module1B
- * pin 45 - i2c4_scl_m1
- * pin 47 - i2c4_sda_m1
- */
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4m1_xfer>;
- status = "disabled";
-};
-
-&i2s0_8ch {
- status = "okay";
-};
-
-/*
- * i2s1_8ch is exposed on CM1 / Module1A
- * pin 24 - i2s1_sdi1_m1
- * pin 25 - i2s1_sdo0_m1
- * pin 26 - i2s1_lrck_tx_m1
- * pin 27 - i2s1_sdi0_m1
- * pin 29 - i2s1_sdi3_m1
- * pin 30 - i2s1_sdi2_m1
- * pin 40 - i2s1_sdo1_m1, shared with spi3
- * pin 41 - i2s1_sdo2_m1
- * pin 49 - i2s1_sclk_tx_m1
- * pin 50 - i2s1_mclk_m1
- * pin 56 - i2s1_sdo3_m1, shared with i2c2
- */
-&i2s1_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx
- &i2s1m1_lrcktx &i2s1m1_lrckrx
- &i2s1m1_sdi0 &i2s1m1_sdi1
- &i2s1m1_sdi2 &i2s1m1_sdi3
- &i2s1m1_sdo0 &i2s1m1_sdo1
- &i2s1m1_sdo2 &i2s1m1_sdo3>;
- status = "disabled";
-};
-
-&mdio1 {
- rgmii_phy1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- status = "disabled";
- };
-};
-
-&pcie2x1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_reset_h>;
- reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
-};
-
-&pinctrl {
- bt {
- bt_enable_h: bt-enable-h {
- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake_l: bt-host-wake-l {
- rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- bt_wake_l: bt-wake-l {
- rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- leds {
- work_led_enable_h: work-led-enable-h {
- rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- diy_led_enable_h: diy-led-enable-h {
- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- pcie_clkreq_h: pcie-clkreq-h {
- rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- pcie_reset_h: pcie-reset-h {
- rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vcc_3v3>;
- vccio2-supply = <&vcc_1v8>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_3v3>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-/*
- * saradc is exposed on CM1 / Module1A
- * pin 94 - saradc_vin3
- * pin 96 - saradc_vin2
- */
-&saradc {
- vref-supply = <&vcca_1v8>;
- status = "disabled";
-};
-
-&sdhci {
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc0 {
- broken-cd;
- bus-width = <4>;
- cap-sd-highspeed;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- vqmmc-supply = <&vccio_sd>;
- status = "disabled";
-};
-
-&sdmmc1 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
- sd-uhs-sdr50;
- vmmc-supply = <&vcc3v3_sys>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-/*
- * spi3 is exposed on CM1 / Module1A
- * pin 37 - spi3_cs1_m0
- * pin 38 - spi3_clk_m0
- * pin 39 - spi3_cs0_m0
- * pin 40 - spi3_miso_m0, shared with i2s1_8ch
- * pin 44 - spi3_mosi_m0
- */
-&spi3 {
- status = "disabled";
-};
-
-&tsadc {
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- clocks = <&rk809 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
- vbat-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcca1v8_pmu>;
- };
-};
-
-/*
- * uart2 is exposed on CM1 / Module1A
- * pin 51 - uart2_rx_m0
- * pin 55 - uart2_tx_m0
- */
-&uart2 {
- status = "disabled";
-};
-
-/*
- * uart7 is exposed on CM1 / Module1A
- * pin 46 - uart7_tx_m2
- * pin 47 - uart7_rx_m2
- */
-&uart7 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart7m2_xfer>;
- status = "disabled";
-};
-
-/* dwc3_otg is the only usb port available */
-&usb2phy0 {
- status = "disabled";
-};
-
-&usb2phy0_otg {
- status = "disabled";
-};
-
-&usb_host0_xhci {
- status = "disabled";
-};
-
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
- remote-endpoint = <&hdmi_in_vp0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-#include "rk356x.dtsi"
-
-/ {
- compatible = "rockchip,rk3566";
-};
-
-&pipegrf {
- compatible = "rockchip,rk3566-pipe-grf", "syscon";
-};
-
-&power {
- power-domain@RK3568_PD_PIPE {
- reg = <RK3568_PD_PIPE>;
- clocks = <&cru PCLK_PIPE>;
- pm_qos = <&qos_pcie2x1>,
- <&qos_sata1>,
- <&qos_sata2>,
- <&qos_usb3_0>,
- <&qos_usb3_1>;
- #power-domain-cells = <0>;
- };
-};
-
-&usb_host0_xhci {
- phys = <&usb2phy0_otg>;
- phy-names = "usb2-phy";
- extcon = <&usb2phy0>;
- maximum-speed = "high-speed";
-};
-
-&vop {
- compatible = "rockchip,rk3566-vop";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Author: Frank Wunderlich <frank-w@public-files.de>
- *
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
- model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
-
- aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- mmc0 = &sdmmc0;
- mmc1 = &sdhci;
- };
-
- chosen: chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&blue_led_pin &green_led_pin>;
-
- blue_led: led-0 {
- color = <LED_COLOR_ID_BLUE>;
- default-state = "off";
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
- };
-
- green_led: led-1 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "on";
- function = LED_FUNCTION_POWER;
- gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
- };
- };
-
- dc_12v: dc-12v-regulator {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&ir_receiver_pin>;
- };
-
- vcc3v3_sys: vcc3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- pcie30_avdd0v9: pcie30-avdd0v9-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- pcie30_avdd1v8: pcie30-avdd1v8-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- /* pi6c pcie clock generator feeds both ports */
- vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <200000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
- vcc3v3_minipcie: vcc3v3-minipcie-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_minipcie";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&minipcie_enable_h>;
- startup-delay-us = <50000>;
- vin-supply = <&vcc3v3_pi6c_05>;
- };
-
- /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
- vcc3v3_ngff: vcc3v3-ngff-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_ngff";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&ngffpcie_enable_h>;
- startup-delay-us = <50000>;
- vin-supply = <&vcc3v3_pi6c_05>;
- };
-
- vcc5v0_usb: vcc5v0-usb-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_usb_host: vcc5v0-usb-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_host_en>;
- regulator-name = "vcc5v0_usb_host";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_otg_en>;
- regulator-name = "vcc5v0_usb_otg";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-};
-
-&combphy0 {
- /* used for USB3 */
- status = "okay";
-};
-
-&combphy1 {
- /* used for USB3 */
- status = "okay";
-};
-
-&combphy2 {
- /* used for SATA */
- status = "okay";
-};
-
-&gmac0 {
- assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
- assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
- clock_in_out = "input";
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac0_miim
- &gmac0_tx_bus2
- &gmac0_rx_bus2
- &gmac0_rgmii_clk
- &gmac0_rgmii_bus>;
- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f */
- snps,reset-delays-us = <0 20000 100000>;
- tx_delay = <0x4f>;
- rx_delay = <0x0f>;
- status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
-};
-
-&gmac1 {
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
- clock_in_out = "output";
- phy-handle = <&rgmii_phy1>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1m1_miim
- &gmac1m1_tx_bus2
- &gmac1m1_rx_bus2
- &gmac1m1_rgmii_clk
- &gmac1m1_rgmii_bus>;
-
- snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f */
- snps,reset-delays-us = <0 20000 100000>;
-
- tx_delay = <0x3c>;
- rx_delay = <0x2f>;
-
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
- status = "okay";
-};
-
-&hdmi_in {
- hdmi_in_vp0: endpoint {
- remote-endpoint = <&vp0_out_hdmi>;
- };
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
- rockchip,system-power-controller;
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- wakeup-source;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-name = "vdd_gpu";
- regulator-always-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vdd_npu: DCDC_REG4 {
- regulator-name = "vdd_npu";
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_image: LDO_REG1 {
- regulator-name = "vdda0v9_image";
- regulator-always-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-name = "vdda_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-name = "vdda0v9_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-name = "vcc3v3_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_1v8: LDO_REG7 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_pmu: LDO_REG8 {
- regulator-name = "vcca1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_image: LDO_REG9 {
- regulator-name = "vcca1v8_image";
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3: SWITCH_REG1 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: SWITCH_REG2 {
- regulator-name = "vcc3v3_sd";
- regulator-always-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&i2c3 {
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
- #clock-cells = <0>;
- clock-output-names = "rtcic_32kout";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- wakeup-source;
- };
-};
-
-&i2c5 {
- /* pin 3 (SDA) + 4 (SCL) of header con2 */
- status = "disabled";
-};
-
-&i2s0_8ch {
- /* hdmi sound */
- status = "okay";
-};
-
-&mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- switch@0 {
- compatible = "mediatek,mt7531";
- reg = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- label = "lan0";
- };
-
- port@2 {
- reg = <2>;
- label = "lan1";
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- };
-
- port@4 {
- reg = <4>;
- label = "lan3";
- };
-
- port@5 {
- reg = <5>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "rgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
- };
- };
-};
-
-&mdio1 {
- rgmii_phy1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- };
-};
-
-&pcie30phy {
- data-lanes = <1 2>;
- phy-supply = <&vcc3v3_pi6c_05>;
- status = "okay";
-};
-
-&pcie3x1 {
- /* M.2 slot */
- num-lanes = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&ngffpcie_reset_h>;
- reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_ngff>;
- status = "okay";
-};
-
-&pcie3x2 {
- /* mPCIe slot */
- num-lanes = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&minipcie_reset_h>;
- reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_minipcie>;
- status = "okay";
-};
-
-&pinctrl {
- leds {
- blue_led_pin: blue-led-pin {
- rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- green_led_pin: green-led-pin {
- rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- ir-receiver {
- ir_receiver_pin: ir-receiver-pin {
- rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- minipcie_enable_h: minipcie-enable-h {
- rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
- };
-
- ngffpcie_enable_h: ngffpcie-enable-h {
- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
- };
-
- minipcie_reset_h: minipcie-reset-h {
- rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
- };
-
- ngffpcie_reset_h: ngffpcie-reset-h {
- rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
- };
- };
-
- pmic {
- pmic_int: pmic_int {
- rockchip,pins =
- <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb {
- vcc5v0_usb_host_en: vcc5v0_usb_host_en {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_3v3>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_1v8>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&pwm8 {
- /* fan 5v - gnd - pwm */
- status = "okay";
-};
-
-&pwm10 {
- /* pin 7 of header con2 */
- status = "disabled";
-};
-
-&pwm11 {
- /* pin 15 of header con2 */
- status = "disabled";
-};
-
-&pwm12 {
- /* pin 21 of header con2 */
- /* shared with uart9 + spi3 */
- pinctrl-0 = <&pwm12m1_pins>;
- status = "disabled";
-};
-
-&pwm13 {
- /* pin 24 of header con2 */
- /* shared with uart9 */
- pinctrl-0 = <&pwm13m1_pins>;
- status = "disabled";
-};
-
-&pwm14 {
- /* pin 23 of header con2 */
- /* shared with spi3 */
- pinctrl-0 = <&pwm14m1_pins>;
- status = "disabled";
-};
-
-&pwm15 {
- /* pin 19 of header con2 */
- /* shared with spi3 */
- pinctrl-0 = <&pwm15m1_pins>;
- status = "disabled";
-};
-
-&saradc {
- vref-supply = <&vcca_1v8>;
- status = "okay";
-};
-
-&sata2 {
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
- status = "okay";
-};
-
-&sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&spi3 {
- /* pin 19 (MO) + 21 (MI) + 23 (CK) of header con2 */
- /* shared with pwm12/14/15 and uart9 */
- pinctrl-0 = <&spi3m1_pins>;
- status = "disabled";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-&uart0 {
- /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */
- status = "disabled";
-};
-
-&uart2 {
- /* debug-uart */
- status = "okay";
-};
-
-&uart7 {
- /* pin 11 (TX) + 13 (RX) of header con2 */
- pinctrl-0 = <&uart7m1_xfer>;
- status = "disabled";
-};
-
-&uart9 {
- /* pin 21 (TX) + 24 (RX) of header con2 */
- /* shared with pwm13 and pwm12/spi3 */
- pinctrl-0 = <&uart9m1_xfer>;
- status = "disabled";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host0_xhci {
- dr_mode = "host";
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usb_host1_xhci {
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy0_host {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&usb2phy0_otg {
- phy-supply = <&vcc5v0_usb_otg>;
- status = "okay";
-};
-
-&usb2phy1 {
- /* USB for PCIe/M2 */
- status = "okay";
-};
-
-&usb2phy1_host {
- status = "okay";
-};
-
-&usb2phy1_otg {
- status = "okay";
-};
-
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
- remote-endpoint = <&hdmi_in_vp0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
- model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
- compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
-
- aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- mmc0 = &sdmmc0;
- mmc1 = &sdhci;
- };
-
- chosen: chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- dc_12v: dc-12v {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_work: led-0 {
- gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_BLUE>;
- linux,default-trigger = "heartbeat";
- pinctrl-names = "default";
- pinctrl-0 = <&led_work_en>;
- };
- };
-
- rk809-sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,name = "Analog RK809";
- simple-audio-card,mclk-fs = <256>;
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1_8ch>;
- };
- simple-audio-card,codec {
- sound-dai = <&rk809>;
- };
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_usb: vcc5v0-usb {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_usb_host: vcc5v0-usb-host {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_host_en>;
- regulator-name = "vcc5v0_usb_host";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_usb_otg: vcc5v0-usb-otg {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_otg_en>;
- regulator-name = "vcc5v0_usb_otg";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc3v3_lcd0_n: vcc3v3-lcd0-n {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_lcd0_n";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vcc3v3_sys>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc3v3_lcd0_n_en>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_lcd1_n: vcc3v3-lcd1-n {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_lcd1_n";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vcc3v3_sys>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc3v3_lcd1_n_en>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&combphy0 {
- status = "okay";
-};
-
-&combphy1 {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&gmac0 {
- assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
- assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
- assigned-clock-rates = <0>, <125000000>;
- clock_in_out = "output";
- phy-handle = <&rgmii_phy0>;
- phy-mode = "rgmii-id";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac0_miim
- &gmac0_tx_bus2
- &gmac0_rx_bus2
- &gmac0_rgmii_clk
- &gmac0_rgmii_bus>;
- status = "okay";
-};
-
-&gmac1 {
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
- assigned-clock-rates = <0>, <125000000>;
- clock_in_out = "output";
- phy-handle = <&rgmii_phy1>;
- phy-mode = "rgmii-id";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1m1_miim
- &gmac1m1_tx_bus2
- &gmac1m1_rx_bus2
- &gmac1m1_rgmii_clk
- &gmac1m1_rgmii_bus>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
- status = "okay";
-};
-
-&hdmi_in {
- hdmi_in_vp0: endpoint {
- remote-endpoint = <&vp0_out_hdmi>;
- };
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
- assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
- #clock-cells = <1>;
- clock-names = "mclk";
- clocks = <&cru I2S1_MCLKOUT_TX>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
- rockchip,system-power-controller;
- #sound-dai-cells = <0>;
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- wakeup-source;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-name = "vdd_gpu";
- regulator-always-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vdd_npu: DCDC_REG4 {
- regulator-name = "vdd_npu";
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_image: LDO_REG1 {
- regulator-name = "vdda0v9_image";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-name = "vdda_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-name = "vdda0v9_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-name = "vcc3v3_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_1v8: LDO_REG7 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_pmu: LDO_REG8 {
- regulator-name = "vcca1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_image: LDO_REG9 {
- regulator-name = "vcca1v8_image";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3: SWITCH_REG1 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: SWITCH_REG2 {
- regulator-name = "vcc3v3_sd";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
-
- codec {
- mic-in-differential;
- };
- };
-};
-
-&i2c1 {
- status = "okay";
-
- touchscreen0: goodix@14 {
- compatible = "goodix,gt1151";
- reg = <0x14>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>;
- AVDD28-supply = <&vcc3v3_lcd0_n>;
- irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&touch_int &touch_rst>;
- reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
- VDDIO-supply = <&vcc3v3_lcd0_n>;
- };
-};
-
-&i2s0_8ch {
- status = "okay";
-};
-
-&i2s1_8ch {
- rockchip,trcm-sync-tx-only;
- status = "okay";
-};
-
-&mdio0 {
- rgmii_phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
- };
-};
-
-&mdio1 {
- rgmii_phy1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
- };
-};
-
-&pinctrl {
- display {
- vcc3v3_lcd0_n_en: vcc3v3_lcd0_n_en {
- rockchip,pins = <0 RK_PC7 0 &pcfg_pull_none>;
- };
- vcc3v3_lcd1_n_en: vcc3v3_lcd1_n_en {
- rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>;
- };
- };
-
- leds {
- led_work_en: led_work_en {
- rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int: pmic_int {
- rockchip,pins =
- <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- touchscreen {
- touch_int: touch_int {
- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- touch_rst: touch_rst {
- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- vcc5v0_usb_host_en: vcc5v0_usb_host_en {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio2-supply = <&vcc_1v8>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_1v8>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca_1v8>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
- status = "okay";
-};
-
-&sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host0_xhci {
- extcon = <&usb2phy0>;
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usb_host1_xhci {
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy0_host {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&usb2phy0_otg {
- phy-supply = <&vcc5v0_usb_otg>;
- status = "okay";
-};
-
-&usb2phy1 {
- status = "okay";
-};
-
-&usb2phy1_host {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&usb2phy1_otg {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
- remote-endpoint = <&hdmi_in_vp0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
- model = "EmbedFire LubanCat 2";
- compatible = "embedfire,lubancat-2", "rockchip,rk3568";
-
- aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- mmc0 = &sdmmc0;
- mmc1 = &sdhci;
- };
-
- chosen: chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- leds {
- compatible = "gpio-leds";
-
- user_led: user-led {
- label = "user_led";
- linux,default-trigger = "heartbeat";
- default-state = "on";
- gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&user_led_pin>;
- };
- };
-
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- dc_5v: dc-5v-regulator {
- compatible = "regulator-fixed";
- regulator-name = "dc_5v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc3v3_sys: vcc3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_5v>;
- };
-
- vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator {
- compatible = "regulator-fixed";
- regulator-name = "m2_pcie_3v3";
- enable-active-high;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&vcc3v3_m2_pcie_en>;
- pinctrl-names = "default";
- startup-delay-us = <200000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator {
- compatible = "regulator-fixed";
- regulator-name = "minipcie_3v3";
- enable-active-high;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&vcc3v3_mini_pcie_en>;
- pinctrl-names = "default";
- startup-delay-us = <5000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb20_host";
- enable-active-high;
- gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&vcc5v0_usb20_host_en>;
- pinctrl-names = "default";
- };
-
- vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb30_host";
- enable-active-high;
- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&vcc5v0_usb30_host_en>;
- pinctrl-names = "default";
- };
-
- vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_otg_vbus";
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&vcc5v0_otg_vbus_en>;
- pinctrl-names = "default";
- };
-};
-
-&combphy0 {
- status = "okay";
-};
-
-&combphy1 {
- status = "okay";
-};
-
-&combphy2 {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
- status = "okay";
-};
-
-&hdmi_in {
- hdmi_in_vp0: endpoint {
- remote-endpoint = <&vp0_out_hdmi>;
- };
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
- assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
- #clock-cells = <1>;
- clock-names = "mclk";
- clocks = <&cru I2S1_MCLKOUT_TX>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
- rockchip,system-power-controller;
- #sound-dai-cells = <0>;
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- wakeup-source;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-name = "vdd_gpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vdd_npu: DCDC_REG4 {
- regulator-name = "vdd_npu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_image: LDO_REG1 {
- regulator-name = "vdda0v9_image";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-name = "vdda_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-name = "vdda0v9_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-name = "vcc3v3_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_1v8: LDO_REG7 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_pmu: LDO_REG8 {
- regulator-name = "vcca1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_image: LDO_REG9 {
- regulator-name = "vcca1v8_image";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3: SWITCH_REG1 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: SWITCH_REG2 {
- regulator-name = "vcc3v3_sd";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&i2s1_8ch {
- rockchip,trcm-sync-tx-only;
- status = "okay";
-};
-
-&gmac0 {
- phy-mode = "rgmii";
- clock_in_out = "output";
-
- snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f */
- snps,reset-delays-us = <0 20000 100000>;
-
- assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
- assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&gmac0_miim
- &gmac0_tx_bus2
- &gmac0_rx_bus2
- &gmac0_rgmii_clk
- &gmac0_rgmii_bus>;
-
- tx_delay = <0x22>;
- rx_delay = <0x0e>;
-
- phy-handle = <&rgmii_phy0>;
- status = "okay";
-};
-
-&mdio0 {
- rgmii_phy0: phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- };
-};
-
-&gmac1 {
- phy-mode = "rgmii";
- clock_in_out = "output";
-
- snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f */
- snps,reset-delays-us = <0 20000 100000>;
-
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1m1_miim
- &gmac1m1_tx_bus2
- &gmac1m1_rx_bus2
- &gmac1m1_rgmii_clk
- &gmac1m1_rgmii_bus>;
-
- tx_delay = <0x21>;
- rx_delay = <0x0e>;
-
- phy-handle = <&rgmii_phy1>;
- status = "okay";
-};
-
-&mdio1 {
- rgmii_phy1: phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- };
-};
-
-&gic {
- mbi-ranges = <94 31>, <229 31>, <289 31>;
-};
-
-&pcie30phy {
- status = "okay";
-};
-
-&pcie3x2 {
- reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_m2_pcie>;
- status = "okay";
-};
-
-&pcie2x1 {
- reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
- disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_mini_pcie>;
- status = "okay";
-};
-
-&pmu_io_domains {
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_1v8>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&pwm8 {
- status = "okay";
-};
-
-&pwm9 {
- status = "disabled";
-};
-
-&pwm10 {
- status = "disabled";
-};
-
-&pwm14 {
- status = "disabled";
-};
-
-&spi3 {
- pinctrl-0 = <&spi3m1_pins>;
- status = "disabled";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart3m1_xfer>;
- status = "disabled";
-};
-
-&saradc {
- vref-supply = <&vcca_1v8>;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-&sdhci {
- assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
- assigned-clock-rates = <200000000>, <24000000>, <200000000>;
- bus-width = <8>;
- max-frequency = <200000000>;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
- supports-emmc;
- status = "okay";
-};
-
-&sdmmc0 {
- max-frequency = <150000000>;
- no-sdio;
- no-mmc;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- status = "okay";
-};
-
-/* USB OTG/USB Host_1 USB 2.0 Comb */
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy0_host {
- phy-supply = <&vcc5v0_usb30_host>;
- status = "okay";
-};
-
-&usb2phy0_otg {
- phy-supply = <&vcc5v0_otg_vbus>;
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-/* USB Host_2/USB Host_3 USB 2.0 Comb */
-&usb2phy1 {
- status = "okay";
-};
-
-&usb2phy1_host {
- status = "okay";
-};
-
-&usb2phy1_otg {
- phy-supply = <&vcc5v0_usb20_host>;
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */
-&usb_host0_xhci {
- phys = <&usb2phy0_otg>;
- phy-names = "usb2-phy";
- extcon = <&usb2phy0>;
- maximum-speed = "high-speed";
- dr_mode = "host";
- status = "okay";
-};
-
-&sata0 {
- status = "okay";
-};
-
-/* USB3.0 Host */
-&usb_host1_xhci {
- status = "okay";
-};
-
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
- remote-endpoint = <&hdmi_in_vp0>;
- };
-};
-
-&pinctrl {
- leds {
- user_led_pin: user-status-led-pin {
- rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
- rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
- rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en {
- rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en {
- rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int: pmic-int {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyelec.com)
- *
- * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
- */
-
-/dts-v1/;
-#include "rk3568-nanopi-r5s.dtsi"
-
-/ {
- model = "FriendlyElec NanoPi R5C";
- compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&reset_button_pin>;
-
- button-reset {
- debounce-interval = <50>;
- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
- label = "reset";
- linux,code = <KEY_RESTART>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
-
- led-lan {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
- };
-
- power_led: led-power {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_POWER;
- linux,default-trigger = "heartbeat";
- gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
- };
-
- led-wan {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN;
- gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
- };
-
- led-wlan {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WLAN;
- gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&pcie2x1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie20_reset_pin>;
- reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&pcie3x1 {
- num-lanes = <1>;
- reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&pcie3x2 {
- num-lanes = <1>;
- reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&pinctrl {
- gpio-leds {
- lan_led_pin: lan-led-pin {
- rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- power_led_pin: power-led-pin {
- rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wan_led_pin: wan-led-pin {
- rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wlan_led_pin: wlan-led-pin {
- rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- pcie20_reset_pin: pcie20-reset-pin {
- rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- rockchip-key {
- reset_button_pin: reset-button-pin {
- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyelec.com)
- *
- * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
- */
-
-/dts-v1/;
-#include "rk3568-nanopi-r5s.dtsi"
-
-/ {
- model = "FriendlyElec NanoPi R5S";
- compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
-
- aliases {
- ethernet0 = &gmac0;
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
-
- led-lan1 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
- };
-
- led-lan2 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
- };
-
- power_led: led-power {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_POWER;
- linux,default-trigger = "heartbeat";
- gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
- };
-
- led-wan {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN;
- gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&gmac0 {
- assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
- assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
- assigned-clock-rates = <0>, <125000000>;
- clock_in_out = "output";
- phy-handle = <&rgmii_phy0>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac0_miim
- &gmac0_tx_bus2
- &gmac0_rx_bus2
- &gmac0_rgmii_clk
- &gmac0_rgmii_bus>;
- snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 15ms, 50ms for rtl8211f */
- snps,reset-delays-us = <0 15000 50000>;
- tx_delay = <0x3c>;
- rx_delay = <0x2f>;
- status = "okay";
-};
-
-&mdio0 {
- rgmii_phy0: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- pinctrl-0 = <ð_phy0_reset_pin>;
- pinctrl-names = "default";
- };
-};
-
-&pcie2x1 {
- num-lanes = <1>;
- reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&pcie30phy {
- data-lanes = <1 2>;
- status = "okay";
-};
-
-&pcie3x1 {
- num-lanes = <1>;
- reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&pcie3x2 {
- num-lanes = <1>;
- num-ib-windows = <8>;
- num-ob-windows = <8>;
- reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&pinctrl {
- gmac0 {
- eth_phy0_reset_pin: eth-phy0-reset-pin {
- rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- gpio-leds {
- lan1_led_pin: lan1-led-pin {
- rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- lan2_led_pin: lan2-led-pin {
- rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- power_led_pin: power-led-pin {
- rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- wan_led_pin: wan-led-pin {
- rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyelec.com)
- *
- * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
- aliases {
- mmc0 = &sdmmc0;
- mmc1 = &sdhci;
- };
-
- chosen: chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- vdd_usbc: vdd-usbc-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vdd_usbc";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc3v3_sys: vcc3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vdd_usbc>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vdd_usbc>;
- };
-
- vcc3v3_pcie: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <200000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_usb: vcc5v0-usb-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vdd_usbc>;
- };
-
- vcc5v0_usb_host: vcc5v0-usb-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_host_en>;
- regulator-name = "vcc5v0_usb_host";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_otg_en>;
- regulator-name = "vcc5v0_usb_otg";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- pcie30_avdd0v9: pcie30-avdd0v9-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- pcie30_avdd1v8: pcie30-avdd1v8-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc3v3_sys>;
- };
-};
-
-&combphy0 {
- status = "okay";
-};
-
-&combphy1 {
- status = "okay";
-};
-
-&combphy2 {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
- status = "okay";
-};
-
-&hdmi_in {
- hdmi_in_vp0: endpoint {
- remote-endpoint = <&vp0_out_hdmi>;
- };
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
- rockchip,system-power-controller;
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- wakeup-source;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-name = "vdd_gpu";
- regulator-always-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vdd_npu: DCDC_REG4 {
- regulator-name = "vdd_npu";
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_image: LDO_REG1 {
- regulator-name = "vdda0v9_image";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <950000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-name = "vdda_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-name = "vdda0v9_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-name = "vcc3v3_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_1v8: LDO_REG7 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_pmu: LDO_REG8 {
- regulator-name = "vcca1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_image: LDO_REG9 {
- regulator-name = "vcca1v8_image";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3: SWITCH_REG1 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: SWITCH_REG2 {
- regulator-name = "vcc3v3_sd";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
-
- };
-};
-
-&i2c5 {
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <0>;
- clock-output-names = "rtcic_32kout";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- wakeup-source;
- };
-};
-
-&i2s0_8ch {
- status = "okay";
-};
-
-&pcie30phy {
- data-lanes = <1 2>;
- status = "okay";
-};
-
-&pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- pmic {
- pmic_int: pmic-int {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb {
- vcc5v0_usb_host_en: vcc5v0-usb-host-en {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_1v8>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca_1v8>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
- status = "okay";
-};
-
-&sdmmc0 {
- max-frequency = <150000000>;
- no-sdio;
- no-mmc;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host0_xhci {
- extcon = <&usb2phy0>;
- dr_mode = "host";
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usb_host1_xhci {
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy0_host {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&usb2phy0_otg {
- status = "okay";
-};
-
-&usb2phy1 {
- status = "okay";
-};
-
-&usb2phy1_host {
- phy-supply = <&vcc5v0_usb_otg>;
- status = "okay";
-};
-
-&usb2phy1_otg {
- status = "okay";
-};
-
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
- remote-endpoint = <&hdmi_in_vp0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Hardkernel Co., Ltd.
- *
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
- model = "Hardkernel ODROID-M1";
- compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568";
-
- aliases {
- ethernet0 = &gmac0;
- i2c0 = &i2c3;
- i2c3 = &i2c0;
- mmc0 = &sdhci;
- mmc1 = &sdmmc0;
- serial0 = &uart1;
- serial1 = &uart0;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- dc_12v: dc-12v-regulator {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&ir_receiver_pin>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: led-0 {
- gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- default-state = "keep";
- linux,default-trigger = "default-on";
- pinctrl-names = "default";
- pinctrl-0 = <&led_power_pin>;
- };
- led_work: led-1 {
- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_BLUE>;
- linux,default-trigger = "heartbeat";
- pinctrl-names = "default";
- pinctrl-0 = <&led_work_pin>;
- };
- };
-
- rk809-sound {
- compatible = "simple-audio-card";
- pinctrl-names = "default";
- pinctrl-0 = <&hp_det_pin>;
- simple-audio-card,name = "Analog RK817";
- simple-audio-card,format = "i2s";
- simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,widgets =
- "Headphone", "Headphones",
- "Speaker", "Speaker";
- simple-audio-card,routing =
- "Headphones", "HPOL",
- "Headphones", "HPOR",
- "Speaker", "SPKO";
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1_8ch>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&rk809>;
- };
- };
-
- vcc3v3_pcie: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie";
- enable-active-high;
- gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc3v3_pcie_en_pin>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <5000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- vcc3v3_sys: vcc3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_usb_host: vcc5v0-usb-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb_host";
- enable-active-high;
- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_host_en_pin>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb_otg";
- enable-active-high;
- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_otg_en_pin>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&combphy0 {
- /* Used for USB3 */
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&combphy1 {
- /* Used for USB3 */
- phy-supply = <&vcc5v0_usb_otg>;
- status = "okay";
-};
-
-&combphy2 {
- /* used for SATA */
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&gmac0 {
- assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
- assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
- assigned-clock-rates = <0>, <125000000>;
- clock_in_out = "output";
- phy-handle = <&rgmii_phy0>;
- phy-mode = "rgmii";
- phy-supply = <&vcc3v3_sys>;
- pinctrl-names = "default";
- pinctrl-0 = <&gmac0_miim
- &gmac0_tx_bus2
- &gmac0_rx_bus2
- &gmac0_rgmii_clk
- &gmac0_rgmii_bus>;
- status = "okay";
-
- tx_delay = <0x4f>;
- rx_delay = <0x2d>;
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
- status = "okay";
-};
-
-&hdmi_in {
- hdmi_in_vp0: endpoint {
- remote-endpoint = <&vp0_out_hdmi>;
- };
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
- assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
- #clock-cells = <1>;
- clock-names = "mclk";
- clocks = <&cru I2S1_MCLKOUT_TX>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
- rockchip,system-power-controller;
- #sound-dai-cells = <0>;
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- wakeup-source;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-name = "vdd_gpu";
- regulator-always-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vdd_npu: DCDC_REG4 {
- regulator-name = "vdd_npu";
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_image: LDO_REG1 {
- regulator-name = "vdda0v9_image";
- regulator-always-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-name = "vdda_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-name = "vdda0v9_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-name = "vcc3v3_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_1v8: LDO_REG7 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_pmu: LDO_REG8 {
- regulator-name = "vcca1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_image: LDO_REG9 {
- regulator-name = "vcca1v8_image";
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3: SWITCH_REG1 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: SWITCH_REG2 {
- regulator-name = "vcc3v3_sd";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&i2s0_8ch {
- status = "okay";
-};
-
-&i2s1_8ch {
- rockchip,trcm-sync-tx-only;
- status = "okay";
-};
-
-&mdio0 {
- rgmii_phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- };
-};
-
-&pcie30phy {
- status = "okay";
-};
-
-&pcie3x2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_reset_pin>;
- reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&pinctrl {
- fspi {
- fspi_dual_io_pins: fspi-dual-io-pins {
- rockchip,pins =
- /* fspi_clk */
- <1 RK_PD0 1 &pcfg_pull_none>,
- /* fspi_cs0n */
- <1 RK_PD3 1 &pcfg_pull_none>,
- /* fspi_d0 */
- <1 RK_PD1 1 &pcfg_pull_none>,
- /* fspi_d1 */
- <1 RK_PD2 1 &pcfg_pull_none>;
- };
- };
-
- ir-receiver {
- ir_receiver_pin: ir-receiver-pin {
- /* external pullup to VCC3V3_SYS */
- rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- leds {
- led_power_pin: led-power-pin {
- rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- led_work_pin: led-work-pin {
- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- pcie_reset_pin: pcie-reset-pin {
- rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
- rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- rk809 {
- hp_det_pin: hp-det-pin {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio2-supply = <&vcc_1v8>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_3v3>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca_1v8>;
- status = "okay";
-};
-
-&sata2 {
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- sd-uhs-sdr50;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&sfc {
- /* Dual I/O mode as the D2 pin conflicts with the eMMC */
- pinctrl-0 = <&fspi_dual_io_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <100000000>;
- spi-rx-bus-width = <2>;
- spi-tx-bus-width = <1>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SPL";
- reg = <0x0 0xe0000>;
- };
- partition@e0000 {
- label = "U-Boot Env";
- reg = <0xe0000 0x20000>;
- };
- partition@100000 {
- label = "U-Boot";
- reg = <0x100000 0x200000>;
- };
- partition@300000 {
- label = "splash";
- reg = <0x300000 0x100000>;
- };
- partition@400000 {
- label = "Filesystem";
- reg = <0x400000 0xc00000>;
- };
- };
- };
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host0_xhci {
- dr_mode = "host";
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usb_host1_xhci {
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy0_host {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&usb2phy0_otg {
- phy-supply = <&vcc5v0_usb_otg>;
- status = "okay";
-};
-
-&usb2phy1 {
- status = "okay";
-};
-
-&usb2phy1_host {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&usb2phy1_otg {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
- remote-endpoint = <&hdmi_in_vp0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rockchip-pinconf.dtsi"
-
-/*
- * This file is auto generated by pin2dts tool, please keep these code
- * by adding changes at end of this file.
- */
-&pinctrl {
- acodec {
- /omit-if-no-ref/
- acodec_pins: acodec-pins {
- rockchip,pins =
- /* acodec_adc_sync */
- <1 RK_PB1 5 &pcfg_pull_none>,
- /* acodec_adcclk */
- <1 RK_PA1 5 &pcfg_pull_none>,
- /* acodec_adcdata */
- <1 RK_PA0 5 &pcfg_pull_none>,
- /* acodec_dac_datal */
- <1 RK_PA7 5 &pcfg_pull_none>,
- /* acodec_dac_datar */
- <1 RK_PB0 5 &pcfg_pull_none>,
- /* acodec_dacclk */
- <1 RK_PA3 5 &pcfg_pull_none>,
- /* acodec_dacsync */
- <1 RK_PA5 5 &pcfg_pull_none>;
- };
- };
-
- audiopwm {
- /omit-if-no-ref/
- audiopwm_lout: audiopwm-lout {
- rockchip,pins =
- /* audiopwm_lout */
- <1 RK_PA0 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- audiopwm_loutn: audiopwm-loutn {
- rockchip,pins =
- /* audiopwm_loutn */
- <1 RK_PA1 6 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- audiopwm_loutp: audiopwm-loutp {
- rockchip,pins =
- /* audiopwm_loutp */
- <1 RK_PA0 6 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- audiopwm_rout: audiopwm-rout {
- rockchip,pins =
- /* audiopwm_rout */
- <1 RK_PA1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- audiopwm_routn: audiopwm-routn {
- rockchip,pins =
- /* audiopwm_routn */
- <1 RK_PA7 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- audiopwm_routp: audiopwm-routp {
- rockchip,pins =
- /* audiopwm_routp */
- <1 RK_PA6 4 &pcfg_pull_none>;
- };
- };
-
- bt656 {
- /omit-if-no-ref/
- bt656m0_pins: bt656m0-pins {
- rockchip,pins =
- /* bt656_clkm0 */
- <3 RK_PA0 2 &pcfg_pull_none>,
- /* bt656_d0m0 */
- <2 RK_PD0 2 &pcfg_pull_none>,
- /* bt656_d1m0 */
- <2 RK_PD1 2 &pcfg_pull_none>,
- /* bt656_d2m0 */
- <2 RK_PD2 2 &pcfg_pull_none>,
- /* bt656_d3m0 */
- <2 RK_PD3 2 &pcfg_pull_none>,
- /* bt656_d4m0 */
- <2 RK_PD4 2 &pcfg_pull_none>,
- /* bt656_d5m0 */
- <2 RK_PD5 2 &pcfg_pull_none>,
- /* bt656_d6m0 */
- <2 RK_PD6 2 &pcfg_pull_none>,
- /* bt656_d7m0 */
- <2 RK_PD7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- bt656m1_pins: bt656m1-pins {
- rockchip,pins =
- /* bt656_clkm1 */
- <4 RK_PB4 5 &pcfg_pull_none>,
- /* bt656_d0m1 */
- <3 RK_PC6 5 &pcfg_pull_none>,
- /* bt656_d1m1 */
- <3 RK_PC7 5 &pcfg_pull_none>,
- /* bt656_d2m1 */
- <3 RK_PD0 5 &pcfg_pull_none>,
- /* bt656_d3m1 */
- <3 RK_PD1 5 &pcfg_pull_none>,
- /* bt656_d4m1 */
- <3 RK_PD2 5 &pcfg_pull_none>,
- /* bt656_d5m1 */
- <3 RK_PD3 5 &pcfg_pull_none>,
- /* bt656_d6m1 */
- <3 RK_PD4 5 &pcfg_pull_none>,
- /* bt656_d7m1 */
- <3 RK_PD5 5 &pcfg_pull_none>;
- };
- };
-
- bt1120 {
- /omit-if-no-ref/
- bt1120_pins: bt1120-pins {
- rockchip,pins =
- /* bt1120_clk */
- <3 RK_PA6 2 &pcfg_pull_none>,
- /* bt1120_d0 */
- <3 RK_PA1 2 &pcfg_pull_none>,
- /* bt1120_d1 */
- <3 RK_PA2 2 &pcfg_pull_none>,
- /* bt1120_d2 */
- <3 RK_PA3 2 &pcfg_pull_none>,
- /* bt1120_d3 */
- <3 RK_PA4 2 &pcfg_pull_none>,
- /* bt1120_d4 */
- <3 RK_PA5 2 &pcfg_pull_none>,
- /* bt1120_d5 */
- <3 RK_PA7 2 &pcfg_pull_none>,
- /* bt1120_d6 */
- <3 RK_PB0 2 &pcfg_pull_none>,
- /* bt1120_d7 */
- <3 RK_PB1 2 &pcfg_pull_none>,
- /* bt1120_d8 */
- <3 RK_PB2 2 &pcfg_pull_none>,
- /* bt1120_d9 */
- <3 RK_PB3 2 &pcfg_pull_none>,
- /* bt1120_d10 */
- <3 RK_PB4 2 &pcfg_pull_none>,
- /* bt1120_d11 */
- <3 RK_PB5 2 &pcfg_pull_none>,
- /* bt1120_d12 */
- <3 RK_PB6 2 &pcfg_pull_none>,
- /* bt1120_d13 */
- <3 RK_PC1 2 &pcfg_pull_none>,
- /* bt1120_d14 */
- <3 RK_PC2 2 &pcfg_pull_none>,
- /* bt1120_d15 */
- <3 RK_PC3 2 &pcfg_pull_none>;
- };
- };
-
- cam {
- /omit-if-no-ref/
- cam_clkout0: cam-clkout0 {
- rockchip,pins =
- /* cam_clkout0 */
- <4 RK_PA7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- cam_clkout1: cam-clkout1 {
- rockchip,pins =
- /* cam_clkout1 */
- <4 RK_PB0 1 &pcfg_pull_none>;
- };
- };
-
- can0 {
- /omit-if-no-ref/
- can0m0_pins: can0m0-pins {
- rockchip,pins =
- /* can0_rxm0 */
- <0 RK_PB4 2 &pcfg_pull_none>,
- /* can0_txm0 */
- <0 RK_PB3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- can0m1_pins: can0m1-pins {
- rockchip,pins =
- /* can0_rxm1 */
- <2 RK_PA2 4 &pcfg_pull_none>,
- /* can0_txm1 */
- <2 RK_PA1 4 &pcfg_pull_none>;
- };
- };
-
- can1 {
- /omit-if-no-ref/
- can1m0_pins: can1m0-pins {
- rockchip,pins =
- /* can1_rxm0 */
- <1 RK_PA0 3 &pcfg_pull_none>,
- /* can1_txm0 */
- <1 RK_PA1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- can1m1_pins: can1m1-pins {
- rockchip,pins =
- /* can1_rxm1 */
- <4 RK_PC2 3 &pcfg_pull_none>,
- /* can1_txm1 */
- <4 RK_PC3 3 &pcfg_pull_none>;
- };
- };
-
- can2 {
- /omit-if-no-ref/
- can2m0_pins: can2m0-pins {
- rockchip,pins =
- /* can2_rxm0 */
- <4 RK_PB4 3 &pcfg_pull_none>,
- /* can2_txm0 */
- <4 RK_PB5 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- can2m1_pins: can2m1-pins {
- rockchip,pins =
- /* can2_rxm1 */
- <2 RK_PB1 4 &pcfg_pull_none>,
- /* can2_txm1 */
- <2 RK_PB2 4 &pcfg_pull_none>;
- };
- };
-
- cif {
- /omit-if-no-ref/
- cif_clk: cif-clk {
- rockchip,pins =
- /* cif_clkout */
- <4 RK_PC0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- cif_dvp_clk: cif-dvp-clk {
- rockchip,pins =
- /* cif_clkin */
- <4 RK_PC1 1 &pcfg_pull_none>,
- /* cif_href */
- <4 RK_PB6 1 &pcfg_pull_none>,
- /* cif_vsync */
- <4 RK_PB7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- cif_dvp_bus16: cif-dvp-bus16 {
- rockchip,pins =
- /* cif_d8 */
- <3 RK_PD6 1 &pcfg_pull_none>,
- /* cif_d9 */
- <3 RK_PD7 1 &pcfg_pull_none>,
- /* cif_d10 */
- <4 RK_PA0 1 &pcfg_pull_none>,
- /* cif_d11 */
- <4 RK_PA1 1 &pcfg_pull_none>,
- /* cif_d12 */
- <4 RK_PA2 1 &pcfg_pull_none>,
- /* cif_d13 */
- <4 RK_PA3 1 &pcfg_pull_none>,
- /* cif_d14 */
- <4 RK_PA4 1 &pcfg_pull_none>,
- /* cif_d15 */
- <4 RK_PA5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- cif_dvp_bus8: cif-dvp-bus8 {
- rockchip,pins =
- /* cif_d0 */
- <3 RK_PC6 1 &pcfg_pull_none>,
- /* cif_d1 */
- <3 RK_PC7 1 &pcfg_pull_none>,
- /* cif_d2 */
- <3 RK_PD0 1 &pcfg_pull_none>,
- /* cif_d3 */
- <3 RK_PD1 1 &pcfg_pull_none>,
- /* cif_d4 */
- <3 RK_PD2 1 &pcfg_pull_none>,
- /* cif_d5 */
- <3 RK_PD3 1 &pcfg_pull_none>,
- /* cif_d6 */
- <3 RK_PD4 1 &pcfg_pull_none>,
- /* cif_d7 */
- <3 RK_PD5 1 &pcfg_pull_none>;
- };
- };
-
- clk32k {
- /omit-if-no-ref/
- clk32k_in: clk32k-in {
- rockchip,pins =
- /* clk32k_in */
- <0 RK_PB0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- clk32k_out0: clk32k-out0 {
- rockchip,pins =
- /* clk32k_out0 */
- <0 RK_PB0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- clk32k_out1: clk32k-out1 {
- rockchip,pins =
- /* clk32k_out1 */
- <2 RK_PC6 1 &pcfg_pull_none>;
- };
- };
-
- cpu {
- /omit-if-no-ref/
- cpu_pins: cpu-pins {
- rockchip,pins =
- /* cpu_avs */
- <0 RK_PB7 2 &pcfg_pull_none>;
- };
- };
-
- ebc {
- /omit-if-no-ref/
- ebc_extern: ebc-extern {
- rockchip,pins =
- /* ebc_sdce1 */
- <4 RK_PA7 2 &pcfg_pull_none>,
- /* ebc_sdce2 */
- <4 RK_PB0 2 &pcfg_pull_none>,
- /* ebc_sdce3 */
- <4 RK_PB1 2 &pcfg_pull_none>,
- /* ebc_sdshr */
- <4 RK_PB5 2 &pcfg_pull_none>,
- /* ebc_vcom */
- <4 RK_PB2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- ebc_pins: ebc-pins {
- rockchip,pins =
- /* ebc_gdclk */
- <4 RK_PC0 2 &pcfg_pull_none>,
- /* ebc_gdoe */
- <4 RK_PB3 2 &pcfg_pull_none>,
- /* ebc_gdsp */
- <4 RK_PB4 2 &pcfg_pull_none>,
- /* ebc_sdce0 */
- <4 RK_PA6 2 &pcfg_pull_none>,
- /* ebc_sdclk */
- <4 RK_PC1 2 &pcfg_pull_none>,
- /* ebc_sddo0 */
- <3 RK_PC6 2 &pcfg_pull_none>,
- /* ebc_sddo1 */
- <3 RK_PC7 2 &pcfg_pull_none>,
- /* ebc_sddo2 */
- <3 RK_PD0 2 &pcfg_pull_none>,
- /* ebc_sddo3 */
- <3 RK_PD1 2 &pcfg_pull_none>,
- /* ebc_sddo4 */
- <3 RK_PD2 2 &pcfg_pull_none>,
- /* ebc_sddo5 */
- <3 RK_PD3 2 &pcfg_pull_none>,
- /* ebc_sddo6 */
- <3 RK_PD4 2 &pcfg_pull_none>,
- /* ebc_sddo7 */
- <3 RK_PD5 2 &pcfg_pull_none>,
- /* ebc_sddo8 */
- <3 RK_PD6 2 &pcfg_pull_none>,
- /* ebc_sddo9 */
- <3 RK_PD7 2 &pcfg_pull_none>,
- /* ebc_sddo10 */
- <4 RK_PA0 2 &pcfg_pull_none>,
- /* ebc_sddo11 */
- <4 RK_PA1 2 &pcfg_pull_none>,
- /* ebc_sddo12 */
- <4 RK_PA2 2 &pcfg_pull_none>,
- /* ebc_sddo13 */
- <4 RK_PA3 2 &pcfg_pull_none>,
- /* ebc_sddo14 */
- <4 RK_PA4 2 &pcfg_pull_none>,
- /* ebc_sddo15 */
- <4 RK_PA5 2 &pcfg_pull_none>,
- /* ebc_sdle */
- <4 RK_PB6 2 &pcfg_pull_none>,
- /* ebc_sdoe */
- <4 RK_PB7 2 &pcfg_pull_none>;
- };
- };
-
- edpdp {
- /omit-if-no-ref/
- edpdpm0_pins: edpdpm0-pins {
- rockchip,pins =
- /* edpdp_hpdinm0 */
- <4 RK_PC4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- edpdpm1_pins: edpdpm1-pins {
- rockchip,pins =
- /* edpdp_hpdinm1 */
- <0 RK_PC2 2 &pcfg_pull_none>;
- };
- };
-
- emmc {
- /omit-if-no-ref/
- emmc_rstnout: emmc-rstnout {
- rockchip,pins =
- /* emmc_rstn */
- <1 RK_PC7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- emmc_bus8: emmc-bus8 {
- rockchip,pins =
- /* emmc_d0 */
- <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d1 */
- <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d2 */
- <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d3 */
- <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d4 */
- <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d5 */
- <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d6 */
- <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d7 */
- <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- emmc_clk: emmc-clk {
- rockchip,pins =
- /* emmc_clkout */
- <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- emmc_cmd: emmc-cmd {
- rockchip,pins =
- /* emmc_cmd */
- <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- emmc_datastrobe: emmc-datastrobe {
- rockchip,pins =
- /* emmc_datastrobe */
- <1 RK_PC6 1 &pcfg_pull_none>;
- };
- };
-
- eth0 {
- /omit-if-no-ref/
- eth0_pins: eth0-pins {
- rockchip,pins =
- /* eth0_refclko25m */
- <2 RK_PC1 2 &pcfg_pull_none>;
- };
- };
-
- eth1 {
- /omit-if-no-ref/
- eth1m0_pins: eth1m0-pins {
- rockchip,pins =
- /* eth1_refclko25mm0 */
- <3 RK_PB0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- eth1m1_pins: eth1m1-pins {
- rockchip,pins =
- /* eth1_refclko25mm1 */
- <4 RK_PB3 3 &pcfg_pull_none>;
- };
- };
-
- flash {
- /omit-if-no-ref/
- flash_pins: flash-pins {
- rockchip,pins =
- /* flash_ale */
- <1 RK_PD0 2 &pcfg_pull_none>,
- /* flash_cle */
- <1 RK_PC6 3 &pcfg_pull_none>,
- /* flash_cs0n */
- <1 RK_PD3 2 &pcfg_pull_none>,
- /* flash_cs1n */
- <1 RK_PD4 2 &pcfg_pull_none>,
- /* flash_d0 */
- <1 RK_PB4 2 &pcfg_pull_none>,
- /* flash_d1 */
- <1 RK_PB5 2 &pcfg_pull_none>,
- /* flash_d2 */
- <1 RK_PB6 2 &pcfg_pull_none>,
- /* flash_d3 */
- <1 RK_PB7 2 &pcfg_pull_none>,
- /* flash_d4 */
- <1 RK_PC0 2 &pcfg_pull_none>,
- /* flash_d5 */
- <1 RK_PC1 2 &pcfg_pull_none>,
- /* flash_d6 */
- <1 RK_PC2 2 &pcfg_pull_none>,
- /* flash_d7 */
- <1 RK_PC3 2 &pcfg_pull_none>,
- /* flash_dqs */
- <1 RK_PC5 2 &pcfg_pull_none>,
- /* flash_rdn */
- <1 RK_PD2 2 &pcfg_pull_none>,
- /* flash_rdy */
- <1 RK_PD1 2 &pcfg_pull_none>,
- /* flash_volsel */
- <0 RK_PA7 1 &pcfg_pull_none>,
- /* flash_wpn */
- <1 RK_PC7 3 &pcfg_pull_none>,
- /* flash_wrn */
- <1 RK_PC4 2 &pcfg_pull_none>;
- };
- };
-
- fspi {
- /omit-if-no-ref/
- fspi_pins: fspi-pins {
- rockchip,pins =
- /* fspi_clk */
- <1 RK_PD0 1 &pcfg_pull_none>,
- /* fspi_cs0n */
- <1 RK_PD3 1 &pcfg_pull_none>,
- /* fspi_d0 */
- <1 RK_PD1 1 &pcfg_pull_none>,
- /* fspi_d1 */
- <1 RK_PD2 1 &pcfg_pull_none>,
- /* fspi_d2 */
- <1 RK_PC7 2 &pcfg_pull_none>,
- /* fspi_d3 */
- <1 RK_PD4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- fspi_cs1: fspi-cs1 {
- rockchip,pins =
- /* fspi_cs1n */
- <1 RK_PC6 2 &pcfg_pull_up>;
- };
- };
-
- gmac0 {
- /omit-if-no-ref/
- gmac0_miim: gmac0-miim {
- rockchip,pins =
- /* gmac0_mdc */
- <2 RK_PC3 2 &pcfg_pull_none>,
- /* gmac0_mdio */
- <2 RK_PC4 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_clkinout: gmac0-clkinout {
- rockchip,pins =
- /* gmac0_mclkinout */
- <2 RK_PC2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_rx_er: gmac0-rx-er {
- rockchip,pins =
- /* gmac0_rxer */
- <2 RK_PC5 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_rx_bus2: gmac0-rx-bus2 {
- rockchip,pins =
- /* gmac0_rxd0 */
- <2 RK_PB6 1 &pcfg_pull_none>,
- /* gmac0_rxd1 */
- <2 RK_PB7 2 &pcfg_pull_none>,
- /* gmac0_rxdvcrs */
- <2 RK_PC0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_tx_bus2: gmac0-tx-bus2 {
- rockchip,pins =
- /* gmac0_txd0 */
- <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>,
- /* gmac0_txd1 */
- <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
- /* gmac0_txen */
- <2 RK_PB5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_rgmii_clk: gmac0-rgmii-clk {
- rockchip,pins =
- /* gmac0_rxclk */
- <2 RK_PA5 2 &pcfg_pull_none>,
- /* gmac0_txclk */
- <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>;
- };
-
- /omit-if-no-ref/
- gmac0_rgmii_bus: gmac0-rgmii-bus {
- rockchip,pins =
- /* gmac0_rxd2 */
- <2 RK_PA3 2 &pcfg_pull_none>,
- /* gmac0_rxd3 */
- <2 RK_PA4 2 &pcfg_pull_none>,
- /* gmac0_txd2 */
- <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
- /* gmac0_txd3 */
- <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
- };
- };
-
- gmac1 {
- /omit-if-no-ref/
- gmac1m0_miim: gmac1m0-miim {
- rockchip,pins =
- /* gmac1_mdcm0 */
- <3 RK_PC4 3 &pcfg_pull_none>,
- /* gmac1_mdiom0 */
- <3 RK_PC5 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1m0_clkinout: gmac1m0-clkinout {
- rockchip,pins =
- /* gmac1_mclkinoutm0 */
- <3 RK_PC0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1m0_rx_er: gmac1m0-rx-er {
- rockchip,pins =
- /* gmac1_rxerm0 */
- <3 RK_PB4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
- rockchip,pins =
- /* gmac1_rxd0m0 */
- <3 RK_PB1 3 &pcfg_pull_none>,
- /* gmac1_rxd1m0 */
- <3 RK_PB2 3 &pcfg_pull_none>,
- /* gmac1_rxdvcrsm0 */
- <3 RK_PB3 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
- rockchip,pins =
- /* gmac1_txd0m0 */
- <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>,
- /* gmac1_txd1m0 */
- <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>,
- /* gmac1_txenm0 */
- <3 RK_PB7 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
- rockchip,pins =
- /* gmac1_rxclkm0 */
- <3 RK_PA7 3 &pcfg_pull_none>,
- /* gmac1_txclkm0 */
- <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>;
- };
-
- /omit-if-no-ref/
- gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
- rockchip,pins =
- /* gmac1_rxd2m0 */
- <3 RK_PA4 3 &pcfg_pull_none>,
- /* gmac1_rxd3m0 */
- <3 RK_PA5 3 &pcfg_pull_none>,
- /* gmac1_txd2m0 */
- <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>,
- /* gmac1_txd3m0 */
- <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>;
- };
-
- /omit-if-no-ref/
- gmac1m1_miim: gmac1m1-miim {
- rockchip,pins =
- /* gmac1_mdcm1 */
- <4 RK_PB6 3 &pcfg_pull_none>,
- /* gmac1_mdiom1 */
- <4 RK_PB7 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1m1_clkinout: gmac1m1-clkinout {
- rockchip,pins =
- /* gmac1_mclkinoutm1 */
- <4 RK_PC1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1m1_rx_er: gmac1m1-rx-er {
- rockchip,pins =
- /* gmac1_rxerm1 */
- <4 RK_PB2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1m1_rx_bus2: gmac1m1-rx-bus2 {
- rockchip,pins =
- /* gmac1_rxd0m1 */
- <4 RK_PA7 3 &pcfg_pull_none>,
- /* gmac1_rxd1m1 */
- <4 RK_PB0 3 &pcfg_pull_none>,
- /* gmac1_rxdvcrsm1 */
- <4 RK_PB1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1m1_tx_bus2: gmac1m1-tx-bus2 {
- rockchip,pins =
- /* gmac1_txd0m1 */
- <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>,
- /* gmac1_txd1m1 */
- <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>,
- /* gmac1_txenm1 */
- <4 RK_PA6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1m1_rgmii_clk: gmac1m1-rgmii-clk {
- rockchip,pins =
- /* gmac1_rxclkm1 */
- <4 RK_PA3 3 &pcfg_pull_none>,
- /* gmac1_txclkm1 */
- <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>;
- };
-
- /omit-if-no-ref/
- gmac1m1_rgmii_bus: gmac1m1-rgmii-bus {
- rockchip,pins =
- /* gmac1_rxd2m1 */
- <4 RK_PA1 3 &pcfg_pull_none>,
- /* gmac1_rxd3m1 */
- <4 RK_PA2 3 &pcfg_pull_none>,
- /* gmac1_txd2m1 */
- <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>,
- /* gmac1_txd3m1 */
- <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>;
- };
- };
-
- gpu {
- /omit-if-no-ref/
- gpu_pins: gpu-pins {
- rockchip,pins =
- /* gpu_avs */
- <0 RK_PC0 2 &pcfg_pull_none>,
- /* gpu_pwren */
- <0 RK_PA6 4 &pcfg_pull_none>;
- };
- };
-
- hdmitx {
- /omit-if-no-ref/
- hdmitxm0_cec: hdmitxm0-cec {
- rockchip,pins =
- /* hdmitxm0_cec */
- <4 RK_PD1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmitxm1_cec: hdmitxm1-cec {
- rockchip,pins =
- /* hdmitxm1_cec */
- <0 RK_PC7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmitx_scl: hdmitx-scl {
- rockchip,pins =
- /* hdmitx_scl */
- <4 RK_PC7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmitx_sda: hdmitx-sda {
- rockchip,pins =
- /* hdmitx_sda */
- <4 RK_PD0 1 &pcfg_pull_none>;
- };
- };
-
- i2c0 {
- /omit-if-no-ref/
- i2c0_xfer: i2c0-xfer {
- rockchip,pins =
- /* i2c0_scl */
- <0 RK_PB1 1 &pcfg_pull_none_smt>,
- /* i2c0_sda */
- <0 RK_PB2 1 &pcfg_pull_none_smt>;
- };
- };
-
- i2c1 {
- /omit-if-no-ref/
- i2c1_xfer: i2c1-xfer {
- rockchip,pins =
- /* i2c1_scl */
- <0 RK_PB3 1 &pcfg_pull_none_smt>,
- /* i2c1_sda */
- <0 RK_PB4 1 &pcfg_pull_none_smt>;
- };
- };
-
- i2c2 {
- /omit-if-no-ref/
- i2c2m0_xfer: i2c2m0-xfer {
- rockchip,pins =
- /* i2c2_sclm0 */
- <0 RK_PB5 1 &pcfg_pull_none_smt>,
- /* i2c2_sdam0 */
- <0 RK_PB6 1 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c2m1_xfer: i2c2m1-xfer {
- rockchip,pins =
- /* i2c2_sclm1 */
- <4 RK_PB5 1 &pcfg_pull_none_smt>,
- /* i2c2_sdam1 */
- <4 RK_PB4 1 &pcfg_pull_none_smt>;
- };
- };
-
- i2c3 {
- /omit-if-no-ref/
- i2c3m0_xfer: i2c3m0-xfer {
- rockchip,pins =
- /* i2c3_sclm0 */
- <1 RK_PA1 1 &pcfg_pull_none_smt>,
- /* i2c3_sdam0 */
- <1 RK_PA0 1 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c3m1_xfer: i2c3m1-xfer {
- rockchip,pins =
- /* i2c3_sclm1 */
- <3 RK_PB5 4 &pcfg_pull_none_smt>,
- /* i2c3_sdam1 */
- <3 RK_PB6 4 &pcfg_pull_none_smt>;
- };
- };
-
- i2c4 {
- /omit-if-no-ref/
- i2c4m0_xfer: i2c4m0-xfer {
- rockchip,pins =
- /* i2c4_sclm0 */
- <4 RK_PB3 1 &pcfg_pull_none_smt>,
- /* i2c4_sdam0 */
- <4 RK_PB2 1 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c4m1_xfer: i2c4m1-xfer {
- rockchip,pins =
- /* i2c4_sclm1 */
- <2 RK_PB2 2 &pcfg_pull_none_smt>,
- /* i2c4_sdam1 */
- <2 RK_PB1 2 &pcfg_pull_none_smt>;
- };
- };
-
- i2c5 {
- /omit-if-no-ref/
- i2c5m0_xfer: i2c5m0-xfer {
- rockchip,pins =
- /* i2c5_sclm0 */
- <3 RK_PB3 4 &pcfg_pull_none_smt>,
- /* i2c5_sdam0 */
- <3 RK_PB4 4 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c5m1_xfer: i2c5m1-xfer {
- rockchip,pins =
- /* i2c5_sclm1 */
- <4 RK_PC7 2 &pcfg_pull_none_smt>,
- /* i2c5_sdam1 */
- <4 RK_PD0 2 &pcfg_pull_none_smt>;
- };
- };
-
- i2s1 {
- /omit-if-no-ref/
- i2s1m0_lrckrx: i2s1m0-lrckrx {
- rockchip,pins =
- /* i2s1m0_lrckrx */
- <1 RK_PA6 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_lrcktx: i2s1m0-lrcktx {
- rockchip,pins =
- /* i2s1m0_lrcktx */
- <1 RK_PA5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_mclk: i2s1m0-mclk {
- rockchip,pins =
- /* i2s1m0_mclk */
- <1 RK_PA2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sclkrx: i2s1m0-sclkrx {
- rockchip,pins =
- /* i2s1m0_sclkrx */
- <1 RK_PA4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sclktx: i2s1m0-sclktx {
- rockchip,pins =
- /* i2s1m0_sclktx */
- <1 RK_PA3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdi0: i2s1m0-sdi0 {
- rockchip,pins =
- /* i2s1m0_sdi0 */
- <1 RK_PB3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdi1: i2s1m0-sdi1 {
- rockchip,pins =
- /* i2s1m0_sdi1 */
- <1 RK_PB2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdi2: i2s1m0-sdi2 {
- rockchip,pins =
- /* i2s1m0_sdi2 */
- <1 RK_PB1 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdi3: i2s1m0-sdi3 {
- rockchip,pins =
- /* i2s1m0_sdi3 */
- <1 RK_PB0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdo0: i2s1m0-sdo0 {
- rockchip,pins =
- /* i2s1m0_sdo0 */
- <1 RK_PA7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdo1: i2s1m0-sdo1 {
- rockchip,pins =
- /* i2s1m0_sdo1 */
- <1 RK_PB0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdo2: i2s1m0-sdo2 {
- rockchip,pins =
- /* i2s1m0_sdo2 */
- <1 RK_PB1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdo3: i2s1m0-sdo3 {
- rockchip,pins =
- /* i2s1m0_sdo3 */
- <1 RK_PB2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_lrckrx: i2s1m1-lrckrx {
- rockchip,pins =
- /* i2s1m1_lrckrx */
- <4 RK_PA7 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_lrcktx: i2s1m1-lrcktx {
- rockchip,pins =
- /* i2s1m1_lrcktx */
- <3 RK_PD0 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_mclk: i2s1m1-mclk {
- rockchip,pins =
- /* i2s1m1_mclk */
- <3 RK_PC6 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sclkrx: i2s1m1-sclkrx {
- rockchip,pins =
- /* i2s1m1_sclkrx */
- <4 RK_PA6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sclktx: i2s1m1-sclktx {
- rockchip,pins =
- /* i2s1m1_sclktx */
- <3 RK_PC7 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdi0: i2s1m1-sdi0 {
- rockchip,pins =
- /* i2s1m1_sdi0 */
- <3 RK_PD2 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdi1: i2s1m1-sdi1 {
- rockchip,pins =
- /* i2s1m1_sdi1 */
- <3 RK_PD3 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdi2: i2s1m1-sdi2 {
- rockchip,pins =
- /* i2s1m1_sdi2 */
- <3 RK_PD4 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdi3: i2s1m1-sdi3 {
- rockchip,pins =
- /* i2s1m1_sdi3 */
- <3 RK_PD5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdo0: i2s1m1-sdo0 {
- rockchip,pins =
- /* i2s1m1_sdo0 */
- <3 RK_PD1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdo1: i2s1m1-sdo1 {
- rockchip,pins =
- /* i2s1m1_sdo1 */
- <4 RK_PB0 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdo2: i2s1m1-sdo2 {
- rockchip,pins =
- /* i2s1m1_sdo2 */
- <4 RK_PB1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdo3: i2s1m1-sdo3 {
- rockchip,pins =
- /* i2s1m1_sdo3 */
- <4 RK_PB5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_lrckrx: i2s1m2-lrckrx {
- rockchip,pins =
- /* i2s1m2_lrckrx */
- <3 RK_PC5 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_lrcktx: i2s1m2-lrcktx {
- rockchip,pins =
- /* i2s1m2_lrcktx */
- <2 RK_PD2 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_mclk: i2s1m2-mclk {
- rockchip,pins =
- /* i2s1m2_mclk */
- <2 RK_PD0 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_sclkrx: i2s1m2-sclkrx {
- rockchip,pins =
- /* i2s1m2_sclkrx */
- <3 RK_PC3 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_sclktx: i2s1m2-sclktx {
- rockchip,pins =
- /* i2s1m2_sclktx */
- <2 RK_PD1 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_sdi0: i2s1m2-sdi0 {
- rockchip,pins =
- /* i2s1m2_sdi0 */
- <2 RK_PD3 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_sdi1: i2s1m2-sdi1 {
- rockchip,pins =
- /* i2s1m2_sdi1 */
- <2 RK_PD4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_sdi2: i2s1m2-sdi2 {
- rockchip,pins =
- /* i2s1m2_sdi2 */
- <2 RK_PD5 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_sdi3: i2s1m2-sdi3 {
- rockchip,pins =
- /* i2s1m2_sdi3 */
- <2 RK_PD6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_sdo0: i2s1m2-sdo0 {
- rockchip,pins =
- /* i2s1m2_sdo0 */
- <2 RK_PD7 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_sdo1: i2s1m2-sdo1 {
- rockchip,pins =
- /* i2s1m2_sdo1 */
- <3 RK_PA0 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_sdo2: i2s1m2-sdo2 {
- rockchip,pins =
- /* i2s1m2_sdo2 */
- <3 RK_PC1 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m2_sdo3: i2s1m2-sdo3 {
- rockchip,pins =
- /* i2s1m2_sdo3 */
- <3 RK_PC2 5 &pcfg_pull_none>;
- };
- };
-
- i2s2 {
- /omit-if-no-ref/
- i2s2m0_lrckrx: i2s2m0-lrckrx {
- rockchip,pins =
- /* i2s2m0_lrckrx */
- <2 RK_PC0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_lrcktx: i2s2m0-lrcktx {
- rockchip,pins =
- /* i2s2m0_lrcktx */
- <2 RK_PC3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_mclk: i2s2m0-mclk {
- rockchip,pins =
- /* i2s2m0_mclk */
- <2 RK_PC1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sclkrx: i2s2m0-sclkrx {
- rockchip,pins =
- /* i2s2m0_sclkrx */
- <2 RK_PB7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sclktx: i2s2m0-sclktx {
- rockchip,pins =
- /* i2s2m0_sclktx */
- <2 RK_PC2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sdi: i2s2m0-sdi {
- rockchip,pins =
- /* i2s2m0_sdi */
- <2 RK_PC5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sdo: i2s2m0-sdo {
- rockchip,pins =
- /* i2s2m0_sdo */
- <2 RK_PC4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_lrckrx: i2s2m1-lrckrx {
- rockchip,pins =
- /* i2s2m1_lrckrx */
- <4 RK_PA5 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_lrcktx: i2s2m1-lrcktx {
- rockchip,pins =
- /* i2s2m1_lrcktx */
- <4 RK_PA4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_mclk: i2s2m1-mclk {
- rockchip,pins =
- /* i2s2m1_mclk */
- <4 RK_PB6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_sclkrx: i2s2m1-sclkrx {
- rockchip,pins =
- /* i2s2m1_sclkrx */
- <4 RK_PC1 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_sclktx: i2s2m1-sclktx {
- rockchip,pins =
- /* i2s2m1_sclktx */
- <4 RK_PB7 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_sdi: i2s2m1-sdi {
- rockchip,pins =
- /* i2s2m1_sdi */
- <4 RK_PB2 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_sdo: i2s2m1-sdo {
- rockchip,pins =
- /* i2s2m1_sdo */
- <4 RK_PB3 5 &pcfg_pull_none>;
- };
- };
-
- i2s3 {
- /omit-if-no-ref/
- i2s3m0_lrck: i2s3m0-lrck {
- rockchip,pins =
- /* i2s3m0_lrck */
- <3 RK_PA4 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3m0_mclk: i2s3m0-mclk {
- rockchip,pins =
- /* i2s3m0_mclk */
- <3 RK_PA2 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3m0_sclk: i2s3m0-sclk {
- rockchip,pins =
- /* i2s3m0_sclk */
- <3 RK_PA3 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3m0_sdi: i2s3m0-sdi {
- rockchip,pins =
- /* i2s3m0_sdi */
- <3 RK_PA6 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3m0_sdo: i2s3m0-sdo {
- rockchip,pins =
- /* i2s3m0_sdo */
- <3 RK_PA5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3m1_lrck: i2s3m1-lrck {
- rockchip,pins =
- /* i2s3m1_lrck */
- <4 RK_PC4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3m1_mclk: i2s3m1-mclk {
- rockchip,pins =
- /* i2s3m1_mclk */
- <4 RK_PC2 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3m1_sclk: i2s3m1-sclk {
- rockchip,pins =
- /* i2s3m1_sclk */
- <4 RK_PC3 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3m1_sdi: i2s3m1-sdi {
- rockchip,pins =
- /* i2s3m1_sdi */
- <4 RK_PC6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3m1_sdo: i2s3m1-sdo {
- rockchip,pins =
- /* i2s3m1_sdo */
- <4 RK_PC5 5 &pcfg_pull_none>;
- };
- };
-
- isp {
- /omit-if-no-ref/
- isp_pins: isp-pins {
- rockchip,pins =
- /* isp_flashtrigin */
- <4 RK_PB4 4 &pcfg_pull_none>,
- /* isp_flashtrigout */
- <4 RK_PA6 1 &pcfg_pull_none>,
- /* isp_prelighttrig */
- <4 RK_PB1 1 &pcfg_pull_none>;
- };
- };
-
- jtag {
- /omit-if-no-ref/
- jtag_pins: jtag-pins {
- rockchip,pins =
- /* jtag_tck */
- <1 RK_PD7 2 &pcfg_pull_none>,
- /* jtag_tms */
- <2 RK_PA0 2 &pcfg_pull_none>;
- };
- };
-
- lcdc {
- /omit-if-no-ref/
- lcdc_ctl: lcdc-ctl {
- rockchip,pins =
- /* lcdc_clk */
- <3 RK_PA0 1 &pcfg_pull_none>,
- /* lcdc_d0 */
- <2 RK_PD0 1 &pcfg_pull_none>,
- /* lcdc_d1 */
- <2 RK_PD1 1 &pcfg_pull_none>,
- /* lcdc_d2 */
- <2 RK_PD2 1 &pcfg_pull_none>,
- /* lcdc_d3 */
- <2 RK_PD3 1 &pcfg_pull_none>,
- /* lcdc_d4 */
- <2 RK_PD4 1 &pcfg_pull_none>,
- /* lcdc_d5 */
- <2 RK_PD5 1 &pcfg_pull_none>,
- /* lcdc_d6 */
- <2 RK_PD6 1 &pcfg_pull_none>,
- /* lcdc_d7 */
- <2 RK_PD7 1 &pcfg_pull_none>,
- /* lcdc_d8 */
- <3 RK_PA1 1 &pcfg_pull_none>,
- /* lcdc_d9 */
- <3 RK_PA2 1 &pcfg_pull_none>,
- /* lcdc_d10 */
- <3 RK_PA3 1 &pcfg_pull_none>,
- /* lcdc_d11 */
- <3 RK_PA4 1 &pcfg_pull_none>,
- /* lcdc_d12 */
- <3 RK_PA5 1 &pcfg_pull_none>,
- /* lcdc_d13 */
- <3 RK_PA6 1 &pcfg_pull_none>,
- /* lcdc_d14 */
- <3 RK_PA7 1 &pcfg_pull_none>,
- /* lcdc_d15 */
- <3 RK_PB0 1 &pcfg_pull_none>,
- /* lcdc_d16 */
- <3 RK_PB1 1 &pcfg_pull_none>,
- /* lcdc_d17 */
- <3 RK_PB2 1 &pcfg_pull_none>,
- /* lcdc_d18 */
- <3 RK_PB3 1 &pcfg_pull_none>,
- /* lcdc_d19 */
- <3 RK_PB4 1 &pcfg_pull_none>,
- /* lcdc_d20 */
- <3 RK_PB5 1 &pcfg_pull_none>,
- /* lcdc_d21 */
- <3 RK_PB6 1 &pcfg_pull_none>,
- /* lcdc_d22 */
- <3 RK_PB7 1 &pcfg_pull_none>,
- /* lcdc_d23 */
- <3 RK_PC0 1 &pcfg_pull_none>,
- /* lcdc_den */
- <3 RK_PC3 1 &pcfg_pull_none>,
- /* lcdc_hsync */
- <3 RK_PC1 1 &pcfg_pull_none>,
- /* lcdc_vsync */
- <3 RK_PC2 1 &pcfg_pull_none>;
- };
- };
-
- mcu {
- /omit-if-no-ref/
- mcu_pins: mcu-pins {
- rockchip,pins =
- /* mcu_jtagtck */
- <0 RK_PB4 4 &pcfg_pull_none>,
- /* mcu_jtagtdi */
- <0 RK_PC1 4 &pcfg_pull_none>,
- /* mcu_jtagtdo */
- <0 RK_PB3 4 &pcfg_pull_none>,
- /* mcu_jtagtms */
- <0 RK_PC2 4 &pcfg_pull_none>,
- /* mcu_jtagtrstn */
- <0 RK_PC3 4 &pcfg_pull_none>;
- };
- };
-
- npu {
- /omit-if-no-ref/
- npu_pins: npu-pins {
- rockchip,pins =
- /* npu_avs */
- <0 RK_PC1 2 &pcfg_pull_none>;
- };
- };
-
- pcie20 {
- /omit-if-no-ref/
- pcie20m0_pins: pcie20m0-pins {
- rockchip,pins =
- /* pcie20_clkreqnm0 */
- <0 RK_PA5 3 &pcfg_pull_none>,
- /* pcie20_perstnm0 */
- <0 RK_PB6 3 &pcfg_pull_none>,
- /* pcie20_wakenm0 */
- <0 RK_PB5 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie20m1_pins: pcie20m1-pins {
- rockchip,pins =
- /* pcie20_clkreqnm1 */
- <2 RK_PD0 4 &pcfg_pull_none>,
- /* pcie20_perstnm1 */
- <3 RK_PC1 4 &pcfg_pull_none>,
- /* pcie20_wakenm1 */
- <2 RK_PD1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie20m2_pins: pcie20m2-pins {
- rockchip,pins =
- /* pcie20_clkreqnm2 */
- <1 RK_PB0 4 &pcfg_pull_none>,
- /* pcie20_perstnm2 */
- <1 RK_PB2 4 &pcfg_pull_none>,
- /* pcie20_wakenm2 */
- <1 RK_PB1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie20_buttonrstn: pcie20-buttonrstn {
- rockchip,pins =
- /* pcie20_buttonrstn */
- <0 RK_PB4 3 &pcfg_pull_none>;
- };
- };
-
- pcie30x1 {
- /omit-if-no-ref/
- pcie30x1m0_pins: pcie30x1m0-pins {
- rockchip,pins =
- /* pcie30x1_clkreqnm0 */
- <0 RK_PA4 3 &pcfg_pull_none>,
- /* pcie30x1_perstnm0 */
- <0 RK_PC3 3 &pcfg_pull_none>,
- /* pcie30x1_wakenm0 */
- <0 RK_PC2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x1m1_pins: pcie30x1m1-pins {
- rockchip,pins =
- /* pcie30x1_clkreqnm1 */
- <2 RK_PD2 4 &pcfg_pull_none>,
- /* pcie30x1_perstnm1 */
- <3 RK_PA1 4 &pcfg_pull_none>,
- /* pcie30x1_wakenm1 */
- <2 RK_PD3 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x1m2_pins: pcie30x1m2-pins {
- rockchip,pins =
- /* pcie30x1_clkreqnm2 */
- <1 RK_PA5 4 &pcfg_pull_none>,
- /* pcie30x1_perstnm2 */
- <1 RK_PA2 4 &pcfg_pull_none>,
- /* pcie30x1_wakenm2 */
- <1 RK_PA3 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x1_buttonrstn: pcie30x1-buttonrstn {
- rockchip,pins =
- /* pcie30x1_buttonrstn */
- <0 RK_PB3 3 &pcfg_pull_none>;
- };
- };
-
- pcie30x2 {
- /omit-if-no-ref/
- pcie30x2m0_pins: pcie30x2m0-pins {
- rockchip,pins =
- /* pcie30x2_clkreqnm0 */
- <0 RK_PA6 2 &pcfg_pull_none>,
- /* pcie30x2_perstnm0 */
- <0 RK_PC6 3 &pcfg_pull_none>,
- /* pcie30x2_wakenm0 */
- <0 RK_PC5 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x2m1_pins: pcie30x2m1-pins {
- rockchip,pins =
- /* pcie30x2_clkreqnm1 */
- <2 RK_PD4 4 &pcfg_pull_none>,
- /* pcie30x2_perstnm1 */
- <2 RK_PD6 4 &pcfg_pull_none>,
- /* pcie30x2_wakenm1 */
- <2 RK_PD5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x2m2_pins: pcie30x2m2-pins {
- rockchip,pins =
- /* pcie30x2_clkreqnm2 */
- <4 RK_PC2 4 &pcfg_pull_none>,
- /* pcie30x2_perstnm2 */
- <4 RK_PC4 4 &pcfg_pull_none>,
- /* pcie30x2_wakenm2 */
- <4 RK_PC3 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x2_buttonrstn: pcie30x2-buttonrstn {
- rockchip,pins =
- /* pcie30x2_buttonrstn */
- <0 RK_PB0 3 &pcfg_pull_none>;
- };
- };
-
- pdm {
- /omit-if-no-ref/
- pdmm0_clk: pdmm0-clk {
- rockchip,pins =
- /* pdm_clk0m0 */
- <1 RK_PA6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm0_clk1: pdmm0-clk1 {
- rockchip,pins =
- /* pdmm0_clk1 */
- <1 RK_PA4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm0_sdi0: pdmm0-sdi0 {
- rockchip,pins =
- /* pdmm0_sdi0 */
- <1 RK_PB3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm0_sdi1: pdmm0-sdi1 {
- rockchip,pins =
- /* pdmm0_sdi1 */
- <1 RK_PB2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm0_sdi2: pdmm0-sdi2 {
- rockchip,pins =
- /* pdmm0_sdi2 */
- <1 RK_PB1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm0_sdi3: pdmm0-sdi3 {
- rockchip,pins =
- /* pdmm0_sdi3 */
- <1 RK_PB0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm1_clk: pdmm1-clk {
- rockchip,pins =
- /* pdm_clk0m1 */
- <3 RK_PD6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm1_clk1: pdmm1-clk1 {
- rockchip,pins =
- /* pdmm1_clk1 */
- <4 RK_PA0 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm1_sdi0: pdmm1-sdi0 {
- rockchip,pins =
- /* pdmm1_sdi0 */
- <3 RK_PD7 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm1_sdi1: pdmm1-sdi1 {
- rockchip,pins =
- /* pdmm1_sdi1 */
- <4 RK_PA1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm1_sdi2: pdmm1-sdi2 {
- rockchip,pins =
- /* pdmm1_sdi2 */
- <4 RK_PA2 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm1_sdi3: pdmm1-sdi3 {
- rockchip,pins =
- /* pdmm1_sdi3 */
- <4 RK_PA3 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm2_clk1: pdmm2-clk1 {
- rockchip,pins =
- /* pdmm2_clk1 */
- <3 RK_PC4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm2_sdi0: pdmm2-sdi0 {
- rockchip,pins =
- /* pdmm2_sdi0 */
- <3 RK_PB3 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm2_sdi1: pdmm2-sdi1 {
- rockchip,pins =
- /* pdmm2_sdi1 */
- <3 RK_PB4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm2_sdi2: pdmm2-sdi2 {
- rockchip,pins =
- /* pdmm2_sdi2 */
- <3 RK_PB7 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdmm2_sdi3: pdmm2-sdi3 {
- rockchip,pins =
- /* pdmm2_sdi3 */
- <3 RK_PC0 5 &pcfg_pull_none>;
- };
- };
-
- pmic {
- /omit-if-no-ref/
- pmic_pins: pmic-pins {
- rockchip,pins =
- /* pmic_sleep */
- <0 RK_PA2 1 &pcfg_pull_none>;
- };
- };
-
- pmu {
- /omit-if-no-ref/
- pmu_pins: pmu-pins {
- rockchip,pins =
- /* pmu_debug0 */
- <0 RK_PA5 4 &pcfg_pull_none>,
- /* pmu_debug1 */
- <0 RK_PA6 3 &pcfg_pull_none>,
- /* pmu_debug2 */
- <0 RK_PC4 4 &pcfg_pull_none>,
- /* pmu_debug3 */
- <0 RK_PC5 4 &pcfg_pull_none>,
- /* pmu_debug4 */
- <0 RK_PC6 4 &pcfg_pull_none>,
- /* pmu_debug5 */
- <0 RK_PC7 4 &pcfg_pull_none>;
- };
- };
-
- pwm0 {
- /omit-if-no-ref/
- pwm0m0_pins: pwm0m0-pins {
- rockchip,pins =
- /* pwm0_m0 */
- <0 RK_PB7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm0m1_pins: pwm0m1-pins {
- rockchip,pins =
- /* pwm0_m1 */
- <0 RK_PC7 2 &pcfg_pull_none>;
- };
- };
-
- pwm1 {
- /omit-if-no-ref/
- pwm1m0_pins: pwm1m0-pins {
- rockchip,pins =
- /* pwm1_m0 */
- <0 RK_PC0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm1m1_pins: pwm1m1-pins {
- rockchip,pins =
- /* pwm1_m1 */
- <0 RK_PB5 4 &pcfg_pull_none>;
- };
- };
-
- pwm2 {
- /omit-if-no-ref/
- pwm2m0_pins: pwm2m0-pins {
- rockchip,pins =
- /* pwm2_m0 */
- <0 RK_PC1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm2m1_pins: pwm2m1-pins {
- rockchip,pins =
- /* pwm2_m1 */
- <0 RK_PB6 4 &pcfg_pull_none>;
- };
- };
-
- pwm3 {
- /omit-if-no-ref/
- pwm3_pins: pwm3-pins {
- rockchip,pins =
- /* pwm3_ir */
- <0 RK_PC2 1 &pcfg_pull_none>;
- };
- };
-
- pwm4 {
- /omit-if-no-ref/
- pwm4_pins: pwm4-pins {
- rockchip,pins =
- /* pwm4 */
- <0 RK_PC3 1 &pcfg_pull_none>;
- };
- };
-
- pwm5 {
- /omit-if-no-ref/
- pwm5_pins: pwm5-pins {
- rockchip,pins =
- /* pwm5 */
- <0 RK_PC4 1 &pcfg_pull_none>;
- };
- };
-
- pwm6 {
- /omit-if-no-ref/
- pwm6_pins: pwm6-pins {
- rockchip,pins =
- /* pwm6 */
- <0 RK_PC5 1 &pcfg_pull_none>;
- };
- };
-
- pwm7 {
- /omit-if-no-ref/
- pwm7_pins: pwm7-pins {
- rockchip,pins =
- /* pwm7_ir */
- <0 RK_PC6 1 &pcfg_pull_none>;
- };
- };
-
- pwm8 {
- /omit-if-no-ref/
- pwm8m0_pins: pwm8m0-pins {
- rockchip,pins =
- /* pwm8_m0 */
- <3 RK_PB1 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm8m1_pins: pwm8m1-pins {
- rockchip,pins =
- /* pwm8_m1 */
- <1 RK_PD5 4 &pcfg_pull_none>;
- };
- };
-
- pwm9 {
- /omit-if-no-ref/
- pwm9m0_pins: pwm9m0-pins {
- rockchip,pins =
- /* pwm9_m0 */
- <3 RK_PB2 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm9m1_pins: pwm9m1-pins {
- rockchip,pins =
- /* pwm9_m1 */
- <1 RK_PD6 4 &pcfg_pull_none>;
- };
- };
-
- pwm10 {
- /omit-if-no-ref/
- pwm10m0_pins: pwm10m0-pins {
- rockchip,pins =
- /* pwm10_m0 */
- <3 RK_PB5 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm10m1_pins: pwm10m1-pins {
- rockchip,pins =
- /* pwm10_m1 */
- <2 RK_PA1 2 &pcfg_pull_none>;
- };
- };
-
- pwm11 {
- /omit-if-no-ref/
- pwm11m0_pins: pwm11m0-pins {
- rockchip,pins =
- /* pwm11_irm0 */
- <3 RK_PB6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm11m1_pins: pwm11m1-pins {
- rockchip,pins =
- /* pwm11_irm1 */
- <4 RK_PC0 3 &pcfg_pull_none>;
- };
- };
-
- pwm12 {
- /omit-if-no-ref/
- pwm12m0_pins: pwm12m0-pins {
- rockchip,pins =
- /* pwm12_m0 */
- <3 RK_PB7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm12m1_pins: pwm12m1-pins {
- rockchip,pins =
- /* pwm12_m1 */
- <4 RK_PC5 1 &pcfg_pull_none>;
- };
- };
-
- pwm13 {
- /omit-if-no-ref/
- pwm13m0_pins: pwm13m0-pins {
- rockchip,pins =
- /* pwm13_m0 */
- <3 RK_PC0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm13m1_pins: pwm13m1-pins {
- rockchip,pins =
- /* pwm13_m1 */
- <4 RK_PC6 1 &pcfg_pull_none>;
- };
- };
-
- pwm14 {
- /omit-if-no-ref/
- pwm14m0_pins: pwm14m0-pins {
- rockchip,pins =
- /* pwm14_m0 */
- <3 RK_PC4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm14m1_pins: pwm14m1-pins {
- rockchip,pins =
- /* pwm14_m1 */
- <4 RK_PC2 1 &pcfg_pull_none>;
- };
- };
-
- pwm15 {
- /omit-if-no-ref/
- pwm15m0_pins: pwm15m0-pins {
- rockchip,pins =
- /* pwm15_irm0 */
- <3 RK_PC5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm15m1_pins: pwm15m1-pins {
- rockchip,pins =
- /* pwm15_irm1 */
- <4 RK_PC3 1 &pcfg_pull_none>;
- };
- };
-
- refclk {
- /omit-if-no-ref/
- refclk_pins: refclk-pins {
- rockchip,pins =
- /* refclk_ou */
- <0 RK_PA0 1 &pcfg_pull_none>;
- };
- };
-
- sata {
- /omit-if-no-ref/
- sata_pins: sata-pins {
- rockchip,pins =
- /* sata_cpdet */
- <0 RK_PA4 2 &pcfg_pull_none>,
- /* sata_cppod */
- <0 RK_PA6 1 &pcfg_pull_none>,
- /* sata_mpswitch */
- <0 RK_PA5 2 &pcfg_pull_none>;
- };
- };
-
- sata0 {
- /omit-if-no-ref/
- sata0_pins: sata0-pins {
- rockchip,pins =
- /* sata0_actled */
- <4 RK_PC6 3 &pcfg_pull_none>;
- };
- };
-
- sata1 {
- /omit-if-no-ref/
- sata1_pins: sata1-pins {
- rockchip,pins =
- /* sata1_actled */
- <4 RK_PC5 3 &pcfg_pull_none>;
- };
- };
-
- sata2 {
- /omit-if-no-ref/
- sata2_pins: sata2-pins {
- rockchip,pins =
- /* sata2_actled */
- <4 RK_PC4 3 &pcfg_pull_none>;
- };
- };
-
- scr {
- /omit-if-no-ref/
- scr_pins: scr-pins {
- rockchip,pins =
- /* scr_clk */
- <1 RK_PA2 3 &pcfg_pull_none>,
- /* scr_det */
- <1 RK_PA7 3 &pcfg_pull_up>,
- /* scr_io */
- <1 RK_PA3 3 &pcfg_pull_up>,
- /* scr_rst */
- <1 RK_PA5 3 &pcfg_pull_none>;
- };
- };
-
- sdmmc0 {
- /omit-if-no-ref/
- sdmmc0_bus4: sdmmc0-bus4 {
- rockchip,pins =
- /* sdmmc0_d0 */
- <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc0_d1 */
- <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc0_d2 */
- <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc0_d3 */
- <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc0_clk: sdmmc0-clk {
- rockchip,pins =
- /* sdmmc0_clk */
- <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc0_cmd: sdmmc0-cmd {
- rockchip,pins =
- /* sdmmc0_cmd */
- <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc0_det: sdmmc0-det {
- rockchip,pins =
- /* sdmmc0_det */
- <0 RK_PA4 1 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- sdmmc0_pwren: sdmmc0-pwren {
- rockchip,pins =
- /* sdmmc0_pwren */
- <0 RK_PA5 1 &pcfg_pull_none>;
- };
- };
-
- sdmmc1 {
- /omit-if-no-ref/
- sdmmc1_bus4: sdmmc1-bus4 {
- rockchip,pins =
- /* sdmmc1_d0 */
- <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc1_d1 */
- <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc1_d2 */
- <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc1_d3 */
- <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc1_clk: sdmmc1-clk {
- rockchip,pins =
- /* sdmmc1_clk */
- <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc1_cmd: sdmmc1-cmd {
- rockchip,pins =
- /* sdmmc1_cmd */
- <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc1_det: sdmmc1-det {
- rockchip,pins =
- /* sdmmc1_det */
- <2 RK_PB2 1 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- sdmmc1_pwren: sdmmc1-pwren {
- rockchip,pins =
- /* sdmmc1_pwren */
- <2 RK_PB1 1 &pcfg_pull_none>;
- };
- };
-
- sdmmc2 {
- /omit-if-no-ref/
- sdmmc2m0_bus4: sdmmc2m0-bus4 {
- rockchip,pins =
- /* sdmmc2_d0m0 */
- <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>,
- /* sdmmc2_d1m0 */
- <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>,
- /* sdmmc2_d2m0 */
- <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>,
- /* sdmmc2_d3m0 */
- <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc2m0_clk: sdmmc2m0-clk {
- rockchip,pins =
- /* sdmmc2_clkm0 */
- <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc2m0_cmd: sdmmc2m0-cmd {
- rockchip,pins =
- /* sdmmc2_cmdm0 */
- <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc2m0_det: sdmmc2m0-det {
- rockchip,pins =
- /* sdmmc2_detm0 */
- <3 RK_PD4 3 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- sdmmc2m0_pwren: sdmmc2m0-pwren {
- rockchip,pins =
- /* sdmmc2m0_pwren */
- <3 RK_PD5 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- sdmmc2m1_bus4: sdmmc2m1-bus4 {
- rockchip,pins =
- /* sdmmc2_d0m1 */
- <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
- /* sdmmc2_d1m1 */
- <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
- /* sdmmc2_d2m1 */
- <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>,
- /* sdmmc2_d3m1 */
- <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc2m1_clk: sdmmc2m1-clk {
- rockchip,pins =
- /* sdmmc2_clkm1 */
- <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc2m1_cmd: sdmmc2m1-cmd {
- rockchip,pins =
- /* sdmmc2_cmdm1 */
- <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc2m1_det: sdmmc2m1-det {
- rockchip,pins =
- /* sdmmc2_detm1 */
- <3 RK_PA7 4 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- sdmmc2m1_pwren: sdmmc2m1-pwren {
- rockchip,pins =
- /* sdmmc2m1_pwren */
- <3 RK_PB0 4 &pcfg_pull_none>;
- };
- };
-
- spdif {
- /omit-if-no-ref/
- spdifm0_tx: spdifm0-tx {
- rockchip,pins =
- /* spdifm0_tx */
- <1 RK_PA4 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spdifm1_tx: spdifm1-tx {
- rockchip,pins =
- /* spdifm1_tx */
- <3 RK_PC5 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spdifm2_tx: spdifm2-tx {
- rockchip,pins =
- /* spdifm2_tx */
- <4 RK_PC4 2 &pcfg_pull_none>;
- };
- };
-
- spi0 {
- /omit-if-no-ref/
- spi0m0_pins: spi0m0-pins {
- rockchip,pins =
- /* spi0_clkm0 */
- <0 RK_PB5 2 &pcfg_pull_none>,
- /* spi0_misom0 */
- <0 RK_PC5 2 &pcfg_pull_none>,
- /* spi0_mosim0 */
- <0 RK_PB6 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi0m0_cs0: spi0m0-cs0 {
- rockchip,pins =
- /* spi0_cs0m0 */
- <0 RK_PC6 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi0m0_cs1: spi0m0-cs1 {
- rockchip,pins =
- /* spi0_cs1m0 */
- <0 RK_PC4 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi0m1_pins: spi0m1-pins {
- rockchip,pins =
- /* spi0_clkm1 */
- <2 RK_PD3 3 &pcfg_pull_none>,
- /* spi0_misom1 */
- <2 RK_PD0 3 &pcfg_pull_none>,
- /* spi0_mosim1 */
- <2 RK_PD1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi0m1_cs0: spi0m1-cs0 {
- rockchip,pins =
- /* spi0_cs0m1 */
- <2 RK_PD2 3 &pcfg_pull_none>;
- };
- };
-
- spi1 {
- /omit-if-no-ref/
- spi1m0_pins: spi1m0-pins {
- rockchip,pins =
- /* spi1_clkm0 */
- <2 RK_PB5 3 &pcfg_pull_none>,
- /* spi1_misom0 */
- <2 RK_PB6 3 &pcfg_pull_none>,
- /* spi1_mosim0 */
- <2 RK_PB7 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi1m0_cs0: spi1m0-cs0 {
- rockchip,pins =
- /* spi1_cs0m0 */
- <2 RK_PC0 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi1m0_cs1: spi1m0-cs1 {
- rockchip,pins =
- /* spi1_cs1m0 */
- <2 RK_PC6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi1m1_pins: spi1m1-pins {
- rockchip,pins =
- /* spi1_clkm1 */
- <3 RK_PC3 3 &pcfg_pull_none>,
- /* spi1_misom1 */
- <3 RK_PC2 3 &pcfg_pull_none>,
- /* spi1_mosim1 */
- <3 RK_PC1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi1m1_cs0: spi1m1-cs0 {
- rockchip,pins =
- /* spi1_cs0m1 */
- <3 RK_PA1 3 &pcfg_pull_none>;
- };
- };
-
- spi2 {
- /omit-if-no-ref/
- spi2m0_pins: spi2m0-pins {
- rockchip,pins =
- /* spi2_clkm0 */
- <2 RK_PC1 4 &pcfg_pull_none>,
- /* spi2_misom0 */
- <2 RK_PC2 4 &pcfg_pull_none>,
- /* spi2_mosim0 */
- <2 RK_PC3 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi2m0_cs0: spi2m0-cs0 {
- rockchip,pins =
- /* spi2_cs0m0 */
- <2 RK_PC4 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi2m0_cs1: spi2m0-cs1 {
- rockchip,pins =
- /* spi2_cs1m0 */
- <2 RK_PC5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi2m1_pins: spi2m1-pins {
- rockchip,pins =
- /* spi2_clkm1 */
- <3 RK_PA0 3 &pcfg_pull_none>,
- /* spi2_misom1 */
- <2 RK_PD7 3 &pcfg_pull_none>,
- /* spi2_mosim1 */
- <2 RK_PD6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi2m1_cs0: spi2m1-cs0 {
- rockchip,pins =
- /* spi2_cs0m1 */
- <2 RK_PD5 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi2m1_cs1: spi2m1-cs1 {
- rockchip,pins =
- /* spi2_cs1m1 */
- <2 RK_PD4 3 &pcfg_pull_none>;
- };
- };
-
- spi3 {
- /omit-if-no-ref/
- spi3m0_pins: spi3m0-pins {
- rockchip,pins =
- /* spi3_clkm0 */
- <4 RK_PB3 4 &pcfg_pull_none>,
- /* spi3_misom0 */
- <4 RK_PB0 4 &pcfg_pull_none>,
- /* spi3_mosim0 */
- <4 RK_PB2 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi3m0_cs0: spi3m0-cs0 {
- rockchip,pins =
- /* spi3_cs0m0 */
- <4 RK_PA6 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi3m0_cs1: spi3m0-cs1 {
- rockchip,pins =
- /* spi3_cs1m0 */
- <4 RK_PA7 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi3m1_pins: spi3m1-pins {
- rockchip,pins =
- /* spi3_clkm1 */
- <4 RK_PC2 2 &pcfg_pull_none>,
- /* spi3_misom1 */
- <4 RK_PC5 2 &pcfg_pull_none>,
- /* spi3_mosim1 */
- <4 RK_PC3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi3m1_cs0: spi3m1-cs0 {
- rockchip,pins =
- /* spi3_cs0m1 */
- <4 RK_PC6 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spi3m1_cs1: spi3m1-cs1 {
- rockchip,pins =
- /* spi3_cs1m1 */
- <4 RK_PD1 2 &pcfg_pull_none>;
- };
- };
-
- tsadc {
- /omit-if-no-ref/
- tsadcm0_shut: tsadcm0-shut {
- rockchip,pins =
- /* tsadcm0_shut */
- <0 RK_PA1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- tsadcm1_shut: tsadcm1-shut {
- rockchip,pins =
- /* tsadcm1_shut */
- <0 RK_PA2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- tsadc_shutorg: tsadc-shutorg {
- rockchip,pins =
- /* tsadc_shutorg */
- <0 RK_PA1 2 &pcfg_pull_none>;
- };
- };
-
- uart0 {
- /omit-if-no-ref/
- uart0_xfer: uart0-xfer {
- rockchip,pins =
- /* uart0_rx */
- <0 RK_PC0 3 &pcfg_pull_up>,
- /* uart0_tx */
- <0 RK_PC1 3 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart0_ctsn: uart0-ctsn {
- rockchip,pins =
- /* uart0_ctsn */
- <0 RK_PC7 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart0_rtsn: uart0-rtsn {
- rockchip,pins =
- /* uart0_rtsn */
- <0 RK_PC4 3 &pcfg_pull_none>;
- };
- };
-
- uart1 {
- /omit-if-no-ref/
- uart1m0_xfer: uart1m0-xfer {
- rockchip,pins =
- /* uart1_rxm0 */
- <2 RK_PB3 2 &pcfg_pull_up>,
- /* uart1_txm0 */
- <2 RK_PB4 2 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart1m0_ctsn: uart1m0-ctsn {
- rockchip,pins =
- /* uart1m0_ctsn */
- <2 RK_PB6 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart1m0_rtsn: uart1m0-rtsn {
- rockchip,pins =
- /* uart1m0_rtsn */
- <2 RK_PB5 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart1m1_xfer: uart1m1-xfer {
- rockchip,pins =
- /* uart1_rxm1 */
- <3 RK_PD7 4 &pcfg_pull_up>,
- /* uart1_txm1 */
- <3 RK_PD6 4 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart1m1_ctsn: uart1m1-ctsn {
- rockchip,pins =
- /* uart1m1_ctsn */
- <4 RK_PC1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart1m1_rtsn: uart1m1-rtsn {
- rockchip,pins =
- /* uart1m1_rtsn */
- <4 RK_PB6 4 &pcfg_pull_none>;
- };
- };
-
- uart2 {
- /omit-if-no-ref/
- uart2m0_xfer: uart2m0-xfer {
- rockchip,pins =
- /* uart2_rxm0 */
- <0 RK_PD0 1 &pcfg_pull_up>,
- /* uart2_txm0 */
- <0 RK_PD1 1 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart2m1_xfer: uart2m1-xfer {
- rockchip,pins =
- /* uart2_rxm1 */
- <1 RK_PD6 2 &pcfg_pull_up>,
- /* uart2_txm1 */
- <1 RK_PD5 2 &pcfg_pull_up>;
- };
- };
-
- uart3 {
- /omit-if-no-ref/
- uart3m0_xfer: uart3m0-xfer {
- rockchip,pins =
- /* uart3_rxm0 */
- <1 RK_PA0 2 &pcfg_pull_up>,
- /* uart3_txm0 */
- <1 RK_PA1 2 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart3m0_ctsn: uart3m0-ctsn {
- rockchip,pins =
- /* uart3m0_ctsn */
- <1 RK_PA3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart3m0_rtsn: uart3m0-rtsn {
- rockchip,pins =
- /* uart3m0_rtsn */
- <1 RK_PA2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart3m1_xfer: uart3m1-xfer {
- rockchip,pins =
- /* uart3_rxm1 */
- <3 RK_PC0 4 &pcfg_pull_up>,
- /* uart3_txm1 */
- <3 RK_PB7 4 &pcfg_pull_up>;
- };
- };
-
- uart4 {
- /omit-if-no-ref/
- uart4m0_xfer: uart4m0-xfer {
- rockchip,pins =
- /* uart4_rxm0 */
- <1 RK_PA4 2 &pcfg_pull_up>,
- /* uart4_txm0 */
- <1 RK_PA6 2 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart4m0_ctsn: uart4m0-ctsn {
- rockchip,pins =
- /* uart4m0_ctsn */
- <1 RK_PA7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart4m0_rtsn: uart4m0-rtsn {
- rockchip,pins =
- /* uart4m0_rtsn */
- <1 RK_PA5 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart4m1_xfer: uart4m1-xfer {
- rockchip,pins =
- /* uart4_rxm1 */
- <3 RK_PB1 4 &pcfg_pull_up>,
- /* uart4_txm1 */
- <3 RK_PB2 4 &pcfg_pull_up>;
- };
- };
-
- uart5 {
- /omit-if-no-ref/
- uart5m0_xfer: uart5m0-xfer {
- rockchip,pins =
- /* uart5_rxm0 */
- <2 RK_PA1 3 &pcfg_pull_up>,
- /* uart5_txm0 */
- <2 RK_PA2 3 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart5m0_ctsn: uart5m0-ctsn {
- rockchip,pins =
- /* uart5m0_ctsn */
- <1 RK_PD7 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart5m0_rtsn: uart5m0-rtsn {
- rockchip,pins =
- /* uart5m0_rtsn */
- <2 RK_PA0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart5m1_xfer: uart5m1-xfer {
- rockchip,pins =
- /* uart5_rxm1 */
- <3 RK_PC3 4 &pcfg_pull_up>,
- /* uart5_txm1 */
- <3 RK_PC2 4 &pcfg_pull_up>;
- };
- };
-
- uart6 {
- /omit-if-no-ref/
- uart6m0_xfer: uart6m0-xfer {
- rockchip,pins =
- /* uart6_rxm0 */
- <2 RK_PA3 3 &pcfg_pull_up>,
- /* uart6_txm0 */
- <2 RK_PA4 3 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart6m0_ctsn: uart6m0-ctsn {
- rockchip,pins =
- /* uart6m0_ctsn */
- <2 RK_PC0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart6m0_rtsn: uart6m0-rtsn {
- rockchip,pins =
- /* uart6m0_rtsn */
- <2 RK_PB7 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart6m1_xfer: uart6m1-xfer {
- rockchip,pins =
- /* uart6_rxm1 */
- <1 RK_PD6 3 &pcfg_pull_up>,
- /* uart6_txm1 */
- <1 RK_PD5 3 &pcfg_pull_up>;
- };
- };
-
- uart7 {
- /omit-if-no-ref/
- uart7m0_xfer: uart7m0-xfer {
- rockchip,pins =
- /* uart7_rxm0 */
- <2 RK_PA5 3 &pcfg_pull_up>,
- /* uart7_txm0 */
- <2 RK_PA6 3 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart7m0_ctsn: uart7m0-ctsn {
- rockchip,pins =
- /* uart7m0_ctsn */
- <2 RK_PC2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart7m0_rtsn: uart7m0-rtsn {
- rockchip,pins =
- /* uart7m0_rtsn */
- <2 RK_PC1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart7m1_xfer: uart7m1-xfer {
- rockchip,pins =
- /* uart7_rxm1 */
- <3 RK_PC5 4 &pcfg_pull_up>,
- /* uart7_txm1 */
- <3 RK_PC4 4 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart7m2_xfer: uart7m2-xfer {
- rockchip,pins =
- /* uart7_rxm2 */
- <4 RK_PA3 4 &pcfg_pull_up>,
- /* uart7_txm2 */
- <4 RK_PA2 4 &pcfg_pull_up>;
- };
- };
-
- uart8 {
- /omit-if-no-ref/
- uart8m0_xfer: uart8m0-xfer {
- rockchip,pins =
- /* uart8_rxm0 */
- <2 RK_PC6 2 &pcfg_pull_up>,
- /* uart8_txm0 */
- <2 RK_PC5 3 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart8m0_ctsn: uart8m0-ctsn {
- rockchip,pins =
- /* uart8m0_ctsn */
- <2 RK_PB2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart8m0_rtsn: uart8m0-rtsn {
- rockchip,pins =
- /* uart8m0_rtsn */
- <2 RK_PB1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart8m1_xfer: uart8m1-xfer {
- rockchip,pins =
- /* uart8_rxm1 */
- <3 RK_PA0 4 &pcfg_pull_up>,
- /* uart8_txm1 */
- <2 RK_PD7 4 &pcfg_pull_up>;
- };
- };
-
- uart9 {
- /omit-if-no-ref/
- uart9m0_xfer: uart9m0-xfer {
- rockchip,pins =
- /* uart9_rxm0 */
- <2 RK_PA7 3 &pcfg_pull_up>,
- /* uart9_txm0 */
- <2 RK_PB0 3 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart9m0_ctsn: uart9m0-ctsn {
- rockchip,pins =
- /* uart9m0_ctsn */
- <2 RK_PC4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart9m0_rtsn: uart9m0-rtsn {
- rockchip,pins =
- /* uart9m0_rtsn */
- <2 RK_PC3 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart9m1_xfer: uart9m1-xfer {
- rockchip,pins =
- /* uart9_rxm1 */
- <4 RK_PC6 4 &pcfg_pull_up>,
- /* uart9_txm1 */
- <4 RK_PC5 4 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart9m2_xfer: uart9m2-xfer {
- rockchip,pins =
- /* uart9_rxm2 */
- <4 RK_PA5 4 &pcfg_pull_up>,
- /* uart9_txm2 */
- <4 RK_PA4 4 &pcfg_pull_up>;
- };
- };
-
- vop {
- /omit-if-no-ref/
- vopm0_pins: vopm0-pins {
- rockchip,pins =
- /* vop_pwmm0 */
- <0 RK_PC3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- vopm1_pins: vopm1-pins {
- rockchip,pins =
- /* vop_pwmm1 */
- <3 RK_PC4 2 &pcfg_pull_none>;
- };
- };
-};
-
-/*
- * This part is edited handly.
- */
-&pinctrl {
- spi0-hs {
- /omit-if-no-ref/
- spi0m0_pins_hs: spi0m0-pins {
- rockchip,pins =
- /* spi0_clkm0 */
- <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>,
- /* spi0_misom0 */
- <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>,
- /* spi0_mosim0 */
- <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi0m0_cs0_hs: spi0m0-cs0 {
- rockchip,pins =
- /* spi0_cs0m0 */
- <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi0m0_cs1_hs: spi0m0-cs1 {
- rockchip,pins =
- /* spi0_cs1m0 */
- <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi0m1_pins_hs: spi0m1-pins {
- rockchip,pins =
- /* spi0_clkm1 */
- <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>,
- /* spi0_misom1 */
- <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>,
- /* spi0_mosim1 */
- <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi0m1_cs0_hs: spi0m1-cs0 {
- rockchip,pins =
- /* spi0_cs0m1 */
- <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- spi1-hs {
- /omit-if-no-ref/
- spi1m0_pins_hs: spi1m0-pins {
- rockchip,pins =
- /* spi1_clkm0 */
- <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>,
- /* spi1_misom0 */
- <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>,
- /* spi1_mosim0 */
- <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m0_cs0_hs: spi1m0-cs0 {
- rockchip,pins =
- /* spi1_cs0m0 */
- <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m0_cs1_hs: spi1m0-cs1 {
- rockchip,pins =
- /* spi1_cs1m0 */
- <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m1_pins_hs: spi1m1-pins {
- rockchip,pins =
- /* spi1_clkm1 */
- <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>,
- /* spi1_misom1 */
- <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>,
- /* spi1_mosim1 */
- <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m1_cs0_hs: spi1m1-cs0 {
- rockchip,pins =
- /* spi1_cs0m1 */
- <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- spi2-hs {
- /omit-if-no-ref/
- spi2m0_pins_hs: spi2m0-pins {
- rockchip,pins =
- /* spi2_clkm0 */
- <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>,
- /* spi2_misom0 */
- <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>,
- /* spi2_mosim0 */
- <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m0_cs0_hs: spi2m0-cs0 {
- rockchip,pins =
- /* spi2_cs0m0 */
- <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m0_cs1_hs: spi2m0-cs1 {
- rockchip,pins =
- /* spi2_cs1m0 */
- <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m1_pins_hs: spi2m1-pins {
- rockchip,pins =
- /* spi2_clkm1 */
- <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>,
- /* spi2_misom1 */
- <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>,
- /* spi2_mosim1 */
- <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m1_cs0_hs: spi2m1-cs0 {
- rockchip,pins =
- /* spi2_cs0m1 */
- <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m1_cs1_hs: spi2m1-cs1 {
- rockchip,pins =
- /* spi2_cs1m1 */
- <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- spi3-hs {
- /omit-if-no-ref/
- spi3m0_pins_hs: spi3m0-pins {
- rockchip,pins =
- /* spi3_clkm0 */
- <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>,
- /* spi3_misom0 */
- <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>,
- /* spi3_mosim0 */
- <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m0_cs0_hs: spi3m0-cs0 {
- rockchip,pins =
- /* spi3_cs0m0 */
- <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m0_cs1_hs: spi3m0-cs1 {
- rockchip,pins =
- /* spi3_cs1m0 */
- <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m1_pins_hs: spi3m1-pins {
- rockchip,pins =
- /* spi3_clkm1 */
- <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>,
- /* spi3_misom1 */
- <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>,
- /* spi3_mosim1 */
- <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m1_cs0_hs: spi3m1-cs0 {
- rockchip,pins =
- /* spi3_cs0m1 */
- <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m1_cs1_hs: spi3m1-cs1 {
- rockchip,pins =
- /* spi3_cs1m1 */
- <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- gmac-txd-level3 {
- /omit-if-no-ref/
- gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 {
- rockchip,pins =
- /* gmac0_txd0 */
- <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
- /* gmac0_txd1 */
- <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
- /* gmac0_txen */
- <2 RK_PB5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 {
- rockchip,pins =
- /* gmac0_rxd2 */
- <2 RK_PA3 2 &pcfg_pull_none>,
- /* gmac0_rxd3 */
- <2 RK_PA4 2 &pcfg_pull_none>,
- /* gmac0_txd2 */
- <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>,
- /* gmac0_txd3 */
- <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>;
- };
-
- /omit-if-no-ref/
- gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 {
- rockchip,pins =
- /* gmac1_txd0m0 */
- <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>,
- /* gmac1_txd1m0 */
- <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>,
- /* gmac1_txenm0 */
- <3 RK_PB7 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 {
- rockchip,pins =
- /* gmac1_rxd2m0 */
- <3 RK_PA4 3 &pcfg_pull_none>,
- /* gmac1_rxd3m0 */
- <3 RK_PA5 3 &pcfg_pull_none>,
- /* gmac1_txd2m0 */
- <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>,
- /* gmac1_txd3m0 */
- <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>;
- };
-
- /omit-if-no-ref/
- gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 {
- rockchip,pins =
- /* gmac1_txd0m1 */
- <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>,
- /* gmac1_txd1m1 */
- <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>,
- /* gmac1_txenm1 */
- <4 RK_PA6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 {
- rockchip,pins =
- /* gmac1_rxd2m1 */
- <4 RK_PA1 3 &pcfg_pull_none>,
- /* gmac1_rxd3m1 */
- <4 RK_PA2 3 &pcfg_pull_none>,
- /* gmac1_txd2m1 */
- <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>,
- /* gmac1_txd3m1 */
- <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>;
- };
- };
-
- gmac-txc-level2 {
- /omit-if-no-ref/
- gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 {
- rockchip,pins =
- /* gmac0_rxclk */
- <2 RK_PA5 2 &pcfg_pull_none>,
- /* gmac0_txclk */
- <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>;
- };
-
- /omit-if-no-ref/
- gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 {
- rockchip,pins =
- /* gmac1_rxclkm0 */
- <3 RK_PA7 3 &pcfg_pull_none>,
- /* gmac1_txclkm0 */
- <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>;
- };
-
- /omit-if-no-ref/
- gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 {
- rockchip,pins =
- /* gmac1_rxclkm1 */
- <4 RK_PA3 3 &pcfg_pull_none>,
- /* gmac1_txclkm1 */
- <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
- };
- };
-
- tsadc {
- /omit-if-no-ref/
- tsadc_pin: tsadc-pin {
- rockchip,pins =
- /* tsadc_pin */
- <0 RK_PA1 0 &pcfg_pull_none>;
- };
- };
-
- lcdc {
- /omit-if-no-ref/
- lcdc_clock: lcdc-clock {
- rockchip,pins =
- /* lcdc_clk */
- <3 RK_PA0 1 &pcfg_pull_none>,
- /* lcdc_den */
- <3 RK_PC3 1 &pcfg_pull_none>,
- /* lcdc_hsync */
- <3 RK_PC1 1 &pcfg_pull_none>,
- /* lcdc_vsync */
- <3 RK_PC2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- lcdc_data16: lcdc-data16 {
- rockchip,pins =
- /* lcdc_d3 */
- <2 RK_PD3 1 &pcfg_pull_none>,
- /* lcdc_d4 */
- <2 RK_PD4 1 &pcfg_pull_none>,
- /* lcdc_d5 */
- <2 RK_PD5 1 &pcfg_pull_none>,
- /* lcdc_d6 */
- <2 RK_PD6 1 &pcfg_pull_none>,
- /* lcdc_d7 */
- <2 RK_PD7 1 &pcfg_pull_none>,
- /* lcdc_d10 */
- <3 RK_PA3 1 &pcfg_pull_none>,
- /* lcdc_d11 */
- <3 RK_PA4 1 &pcfg_pull_none>,
- /* lcdc_d12 */
- <3 RK_PA5 1 &pcfg_pull_none>,
- /* lcdc_d13 */
- <3 RK_PA6 1 &pcfg_pull_none>,
- /* lcdc_d14 */
- <3 RK_PA7 1 &pcfg_pull_none>,
- /* lcdc_d15 */
- <3 RK_PB0 1 &pcfg_pull_none>,
- /* lcdc_d19 */
- <3 RK_PB4 1 &pcfg_pull_none>,
- /* lcdc_d20 */
- <3 RK_PB5 1 &pcfg_pull_none>,
- /* lcdc_d21 */
- <3 RK_PB6 1 &pcfg_pull_none>,
- /* lcdc_d22 */
- <3 RK_PB7 1 &pcfg_pull_none>,
- /* lcdc_d23 */
- <3 RK_PC0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- lcdc_data18: lcdc-data18 {
- rockchip,pins =
- /* lcdc_d2 */
- <2 RK_PD2 1 &pcfg_pull_none>,
- /* lcdc_d3 */
- <2 RK_PD3 1 &pcfg_pull_none>,
- /* lcdc_d4 */
- <2 RK_PD4 1 &pcfg_pull_none>,
- /* lcdc_d5 */
- <2 RK_PD5 1 &pcfg_pull_none>,
- /* lcdc_d6 */
- <2 RK_PD6 1 &pcfg_pull_none>,
- /* lcdc_d7 */
- <2 RK_PD7 1 &pcfg_pull_none>,
- /* lcdc_d10 */
- <3 RK_PA3 1 &pcfg_pull_none>,
- /* lcdc_d11 */
- <3 RK_PA4 1 &pcfg_pull_none>,
- /* lcdc_d12 */
- <3 RK_PA5 1 &pcfg_pull_none>,
- /* lcdc_d13 */
- <3 RK_PA6 1 &pcfg_pull_none>,
- /* lcdc_d14 */
- <3 RK_PA7 1 &pcfg_pull_none>,
- /* lcdc_d15 */
- <3 RK_PB0 1 &pcfg_pull_none>,
- /* lcdc_d18 */
- <3 RK_PB3 1 &pcfg_pull_none>,
- /* lcdc_d19 */
- <3 RK_PB4 1 &pcfg_pull_none>,
- /* lcdc_d20 */
- <3 RK_PB5 1 &pcfg_pull_none>,
- /* lcdc_d21 */
- <3 RK_PB6 1 &pcfg_pull_none>,
- /* lcdc_d22 */
- <3 RK_PB7 1 &pcfg_pull_none>,
- /* lcdc_d23 */
- <3 RK_PC0 1 &pcfg_pull_none>;
- };
- };
-
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3568.dtsi"
-
-/ {
- compatible = "radxa,cm3i", "rockchip,rk3568";
-
- aliases {
- mmc0 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- led_user: led-0 {
- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "heartbeat";
- pinctrl-names = "default";
- pinctrl-0 = <&led_user_en>;
- };
- };
-
- pcie30_avdd0v9: pcie30-avdd0v9-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- pcie30_avdd1v8: pcie30-avdd1v8-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- vcc3v3_sys: vcc3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v_input>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v_input>;
- };
-
- /* labeled +5v_input in schematic */
- vcc5v_input: vcc5v-input-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v_input";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-};
-
-&combphy0 {
- status = "okay";
-};
-
-&combphy1 {
- status = "okay";
-};
-
-&combphy2 {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&display_subsystem {
- status = "disabled";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v_input>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-name = "vdd_gpu";
- regulator-always-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vdd_npu: DCDC_REG4 {
- regulator-name = "vdd_npu";
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_image: LDO_REG1 {
- regulator-name = "vdda0v9_image";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-name = "vdda_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-name = "vdda0v9_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-name = "vcc3v3_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_1v8: LDO_REG7 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_pmu: LDO_REG8 {
- regulator-name = "vcca1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_image: LDO_REG9 {
- regulator-name = "vcca1v8_image";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3: SWITCH_REG1 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: SWITCH_REG2 {
- regulator-name = "vcc3v3_sd";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&pinctrl {
- leds {
- led_user_en: led_user_en {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int: pmic_int {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio2-supply = <&vcc_1v8>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_1v8>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca_1v8>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy1 {
- status = "okay";
-};
-
-&usb_host0_xhci {
- extcon = <&usb2phy0>;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-#include "rk3568-radxa-cm3i.dtsi"
-
-/ {
- model = "Radxa E25 Carrier Board";
- compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
-
- aliases {
- mmc1 = &sdmmc0;
- };
-
- pwm-leds {
- compatible = "pwm-leds-multicolor";
-
- multi-led {
- color = <LED_COLOR_ID_RGB>;
- max-brightness = <255>;
-
- led-red {
- color = <LED_COLOR_ID_RED>;
- pwms = <&pwm1 0 1000000 0>;
- };
-
- led-green {
- color = <LED_COLOR_ID_GREEN>;
- pwms = <&pwm2 0 1000000 0>;
- };
-
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- pwms = <&pwm12 0 1000000 0>;
- };
- };
- };
-
- vbus_typec: vbus-typec-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vbus_typec_en>;
- regulator-name = "vbus_typec";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- /* actually fed by vcc5v0_sys, dependent
- * on pi6c clock generator
- */
- vcc3v3_minipcie: vcc3v3-minipcie-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&minipcie_enable_h>;
- regulator-name = "vcc3v3_minipcie";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc3v3_pi6c_05>;
- };
-
- vcc3v3_ngff: vcc3v3-ngff-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&ngffpcie_enable_h>;
- regulator-name = "vcc3v3_ngff";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie30x1_enable_h>;
- regulator-name = "vcc3v3_pcie30x1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_enable_h>;
- regulator-name = "vcc3v3_pcie";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&combphy1 {
- phy-supply = <&vcc3v3_pcie30x1>;
-};
-
-&pcie2x1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie20_reset_h>;
- reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pi6c_05>;
- status = "okay";
-};
-
-&pcie30phy {
- data-lanes = <1 2>;
- status = "okay";
-};
-
-&pcie3x1 {
- num-lanes = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie30x1m0_pins>;
- reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_minipcie>;
- status = "okay";
-};
-
-&pcie3x2 {
- num-lanes = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie30x2_reset_h>;
- reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pi6c_05>;
- status = "okay";
-};
-
-&pinctrl {
- pcie {
- pcie20_reset_h: pcie20-reset-h {
- rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie30x1_enable_h: pcie30x1-enable-h {
- rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie30x2_reset_h: pcie30x2-reset-h {
- rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_enable_h: pcie-enable-h {
- rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- minipcie_enable_h: minipcie-enable-h {
- rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- ngffpcie_enable_h: ngffpcie-enable-h {
- rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vbus_typec_en: vbus_typec_en {
- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&pwm12 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm12m1_pins>;
- status = "okay";
-};
-
-&sata1 {
- status = "okay";
-};
-
-&sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- /* Also used in pcie30x1_clkreqnm0 */
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host0_xhci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usb2phy0_otg {
- phy-supply = <&vbus_typec>;
- status = "okay";
-};
-
-&usb2phy1_host {
- phy-supply = <&vcc3v3_minipcie>;
- status = "okay";
-};
-
-&usb2phy1_otg {
- phy-supply = <&vcc3v3_ngff>;
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
-
-/ {
- model = "Radxa ROCK3 Model A";
- compatible = "radxa,rock3a", "rockchip,rk3568";
-
- aliases {
- ethernet0 = &gmac1;
- mmc0 = &sdhci;
- mmc1 = &sdmmc0;
- mmc2 = &sdmmc2;
- };
-
- chosen: chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- gmac1_clkin: external-gmac1-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "gmac1_clkin";
- #clock-cells = <0>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_user: led-0 {
- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_BLUE>;
- linux,default-trigger = "heartbeat";
- pinctrl-names = "default";
- pinctrl-0 = <&led_user_en>;
- };
- };
-
- rk809-sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,name = "Analog RK809";
- simple-audio-card,mclk-fs = <256>;
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1_8ch>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&rk809>;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk809 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable>;
- post-power-on-delay-ms = <100>;
- power-off-delay-us = <5000000>;
- reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- };
-
- pcie30_avdd0v9: pcie30-avdd0v9-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- pcie30_avdd1v8: pcie30-avdd1v8-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- /* pi6c pcie clock generator */
- vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pi6c_03";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_pcie: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_enable_h>;
- regulator-name = "vcc3v3_pcie";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_sys: vcc3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usb: vcc5v0-usb-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usb_host: vcc5v0-usb-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_host_en>;
- regulator-name = "vcc5v0_usb_host";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_usb_hub: vcc5v0-usb-hub-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_hub_en>;
- regulator-name = "vcc5v0_usb_hub";
- regulator-always-on;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_otg_en>;
- regulator-name = "vcc5v0_usb_otg";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc_cam: vcc-cam-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc_cam_en>;
- regulator-name = "vcc_cam";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_mipi: vcc-mipi-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc_mipi_en>;
- regulator-name = "vcc_mipi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc3v3_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&combphy0 {
- status = "okay";
-};
-
-&combphy1 {
- status = "okay";
-};
-
-&combphy2 {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&gmac1 {
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
- clock_in_out = "input";
- phy-handle = <&rgmii_phy1>;
- phy-mode = "rgmii-id";
- phy-supply = <&vcc_3v3>;
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1m1_miim
- &gmac1m1_tx_bus2
- &gmac1m1_rx_bus2
- &gmac1m1_rgmii_clk
- &gmac1m1_clkinout
- &gmac1m1_rgmii_bus>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm1_cec>;
- status = "okay";
-};
-
-&hdmi_in {
- hdmi_in_vp0: endpoint {
- remote-endpoint = <&vp0_out_hdmi>;
- };
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
- assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
- #clock-cells = <1>;
- clock-names = "mclk";
- clocks = <&cru I2S1_MCLKOUT_TX>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
- rockchip,system-power-controller;
- #sound-dai-cells = <0>;
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- wakeup-source;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-name = "vdd_gpu";
- regulator-always-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vdd_npu: DCDC_REG4 {
- regulator-name = "vdd_npu";
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_image: LDO_REG1 {
- regulator-name = "vdda0v9_image";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-name = "vdda_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-name = "vdda0v9_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-name = "vcc3v3_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_1v8: LDO_REG7 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_pmu: LDO_REG8 {
- regulator-name = "vcca1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_image: LDO_REG9 {
- regulator-name = "vcca1v8_image";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3: SWITCH_REG1 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: SWITCH_REG2 {
- regulator-name = "vcc3v3_sd";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
-
- codec {
- mic-in-differential;
- };
- };
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3m1_xfer>;
- status = "disabled";
-};
-
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4m1_xfer>;
- status = "disabled";
-};
-
-&i2c5 {
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <0>;
- clock-output-names = "rtcic_32kout";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- wakeup-source;
- };
-};
-
-&i2s0_8ch {
- status = "okay";
-};
-
-&i2s1_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
- rockchip,trcm-sync-tx-only;
- status = "okay";
-};
-
-&i2s2_2ch {
- rockchip,trcm-sync-tx-only;
- status = "okay";
-};
-
-&mdio1 {
- rgmii_phy1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- pinctrl-names = "default";
- pinctrl-0 = <ð_phy_rst>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
- };
-};
-
-&pcie2x1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_reset_h>;
- reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&pcie30phy {
- phy-supply = <&vcc3v3_pi6c_03>;
- status = "okay";
-};
-
-&pcie3x2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie30x2m1_pins>;
- reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
-};
-
-&pinctrl {
- cam {
- vcc_cam_en: vcc_cam_en {
- rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- display {
- vcc_mipi_en: vcc_mipi_en {
- rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- ethernet {
- eth_phy_rst: eth_phy_rst {
- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- leds {
- led_user_en: led_user_en {
- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie {
- pcie_enable_h: pcie-enable-h {
- rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_reset_h: pcie-reset-h {
- rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int: pmic_int {
- rockchip,pins =
- <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb {
- vcc5v0_usb_host_en: vcc5v0_usb_host_en {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
- rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- bt {
- bt_enable: bt-enable {
- rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_host_wake: bt-host-wake {
- rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- bt_wake: bt-wake {
- rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable: wifi-enable {
- rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio2-supply = <&vcc_1v8>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_1v8>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca_1v8>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- sd-uhs-sdr50;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&sdmmc2 {
- bus-width = <4>;
- disable-wp;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sys>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- clocks = <&rk809 1>;
- clock-names = "lpo";
- device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>;
- vbat-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
- /* vddio comes from regulator on module, use IO bank voltage instead */
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host0_xhci {
- extcon = <&usb2phy0>;
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usb_host1_xhci {
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy0_host {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&usb2phy0_otg {
- phy-supply = <&vcc5v0_usb_otg>;
- status = "okay";
-};
-
-&usb2phy1 {
- status = "okay";
-};
-
-&usb2phy1_host {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&usb2phy1_otg {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
- remote-endpoint = <&hdmi_in_vp0>;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include "rk356x.dtsi"
-
-/ {
- compatible = "rockchip,rk3568";
-
- sata0: sata@fc000000 {
- compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
- reg = <0 0xfc000000 0 0x1000>;
- clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
- <&cru CLK_SATA0_RXOOB>;
- clock-names = "sata", "pmalive", "rxoob";
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&combphy0 PHY_TYPE_SATA>;
- phy-names = "sata-phy";
- ports-implemented = <0x1>;
- power-domains = <&power RK3568_PD_PIPE>;
- status = "disabled";
- };
-
- pipe_phy_grf0: syscon@fdc70000 {
- compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
- reg = <0x0 0xfdc70000 0x0 0x1000>;
- };
-
- qos_pcie3x1: qos@fe190080 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe190080 0x0 0x20>;
- };
-
- qos_pcie3x2: qos@fe190100 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe190100 0x0 0x20>;
- };
-
- qos_sata0: qos@fe190200 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe190200 0x0 0x20>;
- };
-
- pcie30_phy_grf: syscon@fdcb8000 {
- compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
- reg = <0x0 0xfdcb8000 0x0 0x10000>;
- };
-
- pcie30phy: phy@fe8c0000 {
- compatible = "rockchip,rk3568-pcie3-phy";
- reg = <0x0 0xfe8c0000 0x0 0x20000>;
- #phy-cells = <0>;
- clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
- <&cru PCLK_PCIE30PHY>;
- clock-names = "refclk_m", "refclk_n", "pclk";
- resets = <&cru SRST_PCIE30PHY>;
- reset-names = "phy";
- rockchip,phy-grf = <&pcie30_phy_grf>;
- status = "disabled";
- };
-
- pcie3x1: pcie@fe270000 {
- compatible = "rockchip,rk3568-pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x0 0xf>;
- clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
- <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
- <&cru CLK_PCIE30X1_AUX_NDFT>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk", "aux";
- device_type = "pci";
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
- <0 0 0 2 &pcie3x1_intc 1>,
- <0 0 0 3 &pcie3x1_intc 2>,
- <0 0 0 4 &pcie3x1_intc 3>;
- linux,pci-domain = <1>;
- num-ib-windows = <6>;
- num-ob-windows = <2>;
- max-link-speed = <3>;
- msi-map = <0x0 &gic 0x1000 0x1000>;
- num-lanes = <1>;
- phys = <&pcie30phy>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3568_PD_PIPE>;
- reg = <0x3 0xc0400000 0x0 0x00400000>,
- <0x0 0xfe270000 0x0 0x00010000>,
- <0x0 0xf2000000 0x0 0x00100000>;
- ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
- <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
- <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
- reg-names = "dbi", "apb", "config";
- resets = <&cru SRST_PCIE30X1_POWERUP>;
- reset-names = "pipe";
- /* bifurcation; lane1 when using 1+1 */
- status = "disabled";
-
- pcie3x1_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- pcie3x2: pcie@fe280000 {
- compatible = "rockchip,rk3568-pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x0 0xf>;
- clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
- <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
- <&cru CLK_PCIE30X2_AUX_NDFT>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk", "aux";
- device_type = "pci";
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
- <0 0 0 2 &pcie3x2_intc 1>,
- <0 0 0 3 &pcie3x2_intc 2>,
- <0 0 0 4 &pcie3x2_intc 3>;
- linux,pci-domain = <2>;
- num-ib-windows = <6>;
- num-ob-windows = <2>;
- max-link-speed = <3>;
- msi-map = <0x0 &gic 0x2000 0x1000>;
- num-lanes = <2>;
- phys = <&pcie30phy>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3568_PD_PIPE>;
- reg = <0x3 0xc0800000 0x0 0x00400000>,
- <0x0 0xfe280000 0x0 0x00010000>,
- <0x0 0xf0000000 0x0 0x00100000>;
- ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
- <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
- <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
- reg-names = "dbi", "apb", "config";
- resets = <&cru SRST_PCIE30X2_POWERUP>;
- reset-names = "pipe";
- /* bifurcation; lane0 when using 1+1 */
- status = "disabled";
-
- pcie3x2_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- gmac0: ethernet@fe2a0000 {
- compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
- reg = <0x0 0xfe2a0000 0x0 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq", "eth_wake_irq";
- clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
- <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
- <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
- <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
- clock-names = "stmmaceth", "mac_clk_rx",
- "mac_clk_tx", "clk_mac_refout",
- "aclk_mac", "pclk_mac",
- "clk_mac_speed", "ptp_ref";
- resets = <&cru SRST_A_GMAC0>;
- reset-names = "stmmaceth";
- rockchip,grf = <&grf>;
- snps,axi-config = <&gmac0_stmmac_axi_setup>;
- snps,mixed-burst;
- snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
- snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
- snps,tso;
- status = "disabled";
-
- mdio0: mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- };
-
- gmac0_stmmac_axi_setup: stmmac-axi-config {
- snps,blen = <0 0 0 0 16 8 4>;
- snps,rd_osr_lmt = <8>;
- snps,wr_osr_lmt = <4>;
- };
-
- gmac0_mtl_rx_setup: rx-queues-config {
- snps,rx-queues-to-use = <1>;
- queue0 {};
- };
-
- gmac0_mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <1>;
- queue0 {};
- };
- };
-
- combphy0: phy@fe820000 {
- compatible = "rockchip,rk3568-naneng-combphy";
- reg = <0x0 0xfe820000 0x0 0x100>;
- clocks = <&pmucru CLK_PCIEPHY0_REF>,
- <&cru PCLK_PIPEPHY0>,
- <&cru PCLK_PIPE>;
- clock-names = "ref", "apb", "pipe";
- assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_PIPEPHY0>;
- rockchip,pipe-grf = <&pipegrf>;
- rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
- #phy-cells = <1>;
- status = "disabled";
- };
-};
-
-&cpu0_opp_table {
- opp-1992000000 {
- opp-hz = /bits/ 64 <1992000000>;
- opp-microvolt = <1150000 1150000 1150000>;
- };
-};
-
-&pipegrf {
- compatible = "rockchip,rk3568-pipe-grf", "syscon";
-};
-
-&power {
- power-domain@RK3568_PD_PIPE {
- reg = <RK3568_PD_PIPE>;
- clocks = <&cru PCLK_PIPE>;
- pm_qos = <&qos_pcie2x1>,
- <&qos_pcie3x1>,
- <&qos_pcie3x2>,
- <&qos_sata0>,
- <&qos_sata1>,
- <&qos_sata2>,
- <&qos_usb3_0>,
- <&qos_usb3_1>;
- #power-domain-cells = <0>;
- };
-};
-
-&usb_host0_xhci {
- phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
-};
-
-&vop {
- compatible = "rockchip,rk3568-vop";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/clock/rk3568-cru.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/power/rk3568-power.h>
-#include <dt-bindings/soc/rockchip,boot-mode.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
- gpio3 = &gpio3;
- gpio4 = &gpio4;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- serial4 = &uart4;
- serial5 = &uart5;
- serial6 = &uart6;
- serial7 = &uart7;
- serial8 = &uart8;
- serial9 = &uart9;
- spi0 = &spi0;
- spi1 = &spi1;
- spi2 = &spi2;
- spi3 = &spi3;
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0 0x0>;
- clocks = <&scmi_clk 0>;
- #cooling-cells = <2>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu1: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0 0x100>;
- #cooling-cells = <2>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu2: cpu@200 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0 0x200>;
- #cooling-cells = <2>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu3: cpu@300 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0 0x300>;
- #cooling-cells = <2>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
- };
- };
-
- cpu0_opp_table: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-408000000 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <900000 900000 1150000>;
- clock-latency-ns = <40000>;
- };
-
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <900000 900000 1150000>;
- };
-
- opp-816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <900000 900000 1150000>;
- opp-suspend;
- };
-
- opp-1104000000 {
- opp-hz = /bits/ 64 <1104000000>;
- opp-microvolt = <900000 900000 1150000>;
- };
-
- opp-1416000000 {
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <900000 900000 1150000>;
- };
-
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <975000 975000 1150000>;
- };
-
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1050000 1050000 1150000>;
- };
- };
-
- display_subsystem: display-subsystem {
- compatible = "rockchip,display-subsystem";
- ports = <&vop_out>;
- };
-
- firmware {
- scmi: scmi {
- compatible = "arm,scmi-smc";
- arm,smc-id = <0x82000010>;
- shmem = <&scmi_shmem>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
- };
- };
- };
-
- gpu_opp_table: opp-table-1 {
- compatible = "operating-points-v2";
-
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <825000>;
- };
-
- opp-300000000 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <825000>;
- };
-
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <825000>;
- };
-
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <825000>;
- };
-
- opp-700000000 {
- opp-hz = /bits/ 64 <700000000>;
- opp-microvolt = <900000>;
- };
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <1000000>;
- };
- };
-
- hdmi_sound: hdmi-sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "HDMI";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
- status = "disabled";
-
- simple-audio-card,codec {
- sound-dai = <&hdmi>;
- };
-
- simple-audio-card,cpu {
- sound-dai = <&i2s0_8ch>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a55-pmu";
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
- arm,no-tick-in-suspend;
- };
-
- xin24m: xin24m {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- #clock-cells = <0>;
- };
-
- xin32k: xin32k {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- pinctrl-0 = <&clk32k_out0>;
- pinctrl-names = "default";
- #clock-cells = <0>;
- };
-
- sram@10f000 {
- compatible = "mmio-sram";
- reg = <0x0 0x0010f000 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x0010f000 0x100>;
-
- scmi_shmem: sram@0 {
- compatible = "arm,scmi-shmem";
- reg = <0x0 0x100>;
- };
- };
-
- sata1: sata@fc400000 {
- compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
- reg = <0 0xfc400000 0 0x1000>;
- clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
- <&cru CLK_SATA1_RXOOB>;
- clock-names = "sata", "pmalive", "rxoob";
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&combphy1 PHY_TYPE_SATA>;
- phy-names = "sata-phy";
- ports-implemented = <0x1>;
- power-domains = <&power RK3568_PD_PIPE>;
- status = "disabled";
- };
-
- sata2: sata@fc800000 {
- compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
- reg = <0 0xfc800000 0 0x1000>;
- clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
- <&cru CLK_SATA2_RXOOB>;
- clock-names = "sata", "pmalive", "rxoob";
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&combphy2 PHY_TYPE_SATA>;
- phy-names = "sata-phy";
- ports-implemented = <0x1>;
- power-domains = <&power RK3568_PD_PIPE>;
- status = "disabled";
- };
-
- usb_host0_xhci: usb@fcc00000 {
- compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
- reg = <0x0 0xfcc00000 0x0 0x400000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
- <&cru ACLK_USB3OTG0>;
- clock-names = "ref_clk", "suspend_clk",
- "bus_clk";
- dr_mode = "otg";
- phy_type = "utmi_wide";
- power-domains = <&power RK3568_PD_PIPE>;
- resets = <&cru SRST_USB3OTG0>;
- snps,dis_u2_susphy_quirk;
- status = "disabled";
- };
-
- usb_host1_xhci: usb@fd000000 {
- compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
- reg = <0x0 0xfd000000 0x0 0x400000>;
- interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
- <&cru ACLK_USB3OTG1>;
- clock-names = "ref_clk", "suspend_clk",
- "bus_clk";
- dr_mode = "host";
- phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- power-domains = <&power RK3568_PD_PIPE>;
- resets = <&cru SRST_USB3OTG1>;
- snps,dis_u2_susphy_quirk;
- status = "disabled";
- };
-
- gic: interrupt-controller@fd400000 {
- compatible = "arm,gic-v3";
- reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
- <0x0 0xfd460000 0 0x80000>; /* GICR */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <3>;
- mbi-alias = <0x0 0xfd410000>;
- mbi-ranges = <296 24>;
- msi-controller;
- };
-
- usb_host0_ehci: usb@fd800000 {
- compatible = "generic-ehci";
- reg = <0x0 0xfd800000 0x0 0x40000>;
- interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
- <&cru PCLK_USB>;
- phys = <&usb2phy1_otg>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usb_host0_ohci: usb@fd840000 {
- compatible = "generic-ohci";
- reg = <0x0 0xfd840000 0x0 0x40000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
- <&cru PCLK_USB>;
- phys = <&usb2phy1_otg>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usb_host1_ehci: usb@fd880000 {
- compatible = "generic-ehci";
- reg = <0x0 0xfd880000 0x0 0x40000>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
- <&cru PCLK_USB>;
- phys = <&usb2phy1_host>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usb_host1_ohci: usb@fd8c0000 {
- compatible = "generic-ohci";
- reg = <0x0 0xfd8c0000 0x0 0x40000>;
- interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
- <&cru PCLK_USB>;
- phys = <&usb2phy1_host>;
- phy-names = "usb";
- status = "disabled";
- };
-
- pmugrf: syscon@fdc20000 {
- compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
- reg = <0x0 0xfdc20000 0x0 0x10000>;
-
- pmu_io_domains: io-domains {
- compatible = "rockchip,rk3568-pmu-io-voltage-domain";
- status = "disabled";
- };
- };
-
- pipegrf: syscon@fdc50000 {
- reg = <0x0 0xfdc50000 0x0 0x1000>;
- };
-
- grf: syscon@fdc60000 {
- compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
- reg = <0x0 0xfdc60000 0x0 0x10000>;
- };
-
- pipe_phy_grf1: syscon@fdc80000 {
- compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
- reg = <0x0 0xfdc80000 0x0 0x1000>;
- };
-
- pipe_phy_grf2: syscon@fdc90000 {
- compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
- reg = <0x0 0xfdc90000 0x0 0x1000>;
- };
-
- usb2phy0_grf: syscon@fdca0000 {
- compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
- reg = <0x0 0xfdca0000 0x0 0x8000>;
- };
-
- usb2phy1_grf: syscon@fdca8000 {
- compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
- reg = <0x0 0xfdca8000 0x0 0x8000>;
- };
-
- pmucru: clock-controller@fdd00000 {
- compatible = "rockchip,rk3568-pmucru";
- reg = <0x0 0xfdd00000 0x0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- cru: clock-controller@fdd20000 {
- compatible = "rockchip,rk3568-cru";
- reg = <0x0 0xfdd20000 0x0 0x1000>;
- clocks = <&xin24m>;
- clock-names = "xin24m";
- #clock-cells = <1>;
- #reset-cells = <1>;
- assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
- assigned-clock-rates = <32768>, <1200000000>, <200000000>;
- assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
- rockchip,grf = <&grf>;
- };
-
- i2c0: i2c@fdd40000 {
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfdd40000 0x0 0x1000>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart0: serial@fdd50000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfdd50000 0x0 0x100>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 0>, <&dmac0 1>;
- pinctrl-0 = <&uart0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- pwm0: pwm@fdd70000 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfdd70000 0x0 0x10>;
- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm0m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm1: pwm@fdd70010 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfdd70010 0x0 0x10>;
- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm1m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm2: pwm@fdd70020 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfdd70020 0x0 0x10>;
- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm2m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm3: pwm@fdd70030 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfdd70030 0x0 0x10>;
- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm3_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pmu: power-management@fdd90000 {
- compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
- reg = <0x0 0xfdd90000 0x0 0x1000>;
-
- power: power-controller {
- compatible = "rockchip,rk3568-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* These power domains are grouped by VD_GPU */
- power-domain@RK3568_PD_GPU {
- reg = <RK3568_PD_GPU>;
- clocks = <&cru ACLK_GPU_PRE>,
- <&cru PCLK_GPU_PRE>;
- pm_qos = <&qos_gpu>;
- #power-domain-cells = <0>;
- };
-
- /* These power domains are grouped by VD_LOGIC */
- power-domain@RK3568_PD_VI {
- reg = <RK3568_PD_VI>;
- clocks = <&cru HCLK_VI>,
- <&cru PCLK_VI>;
- pm_qos = <&qos_isp>,
- <&qos_vicap0>,
- <&qos_vicap1>;
- #power-domain-cells = <0>;
- };
-
- power-domain@RK3568_PD_VO {
- reg = <RK3568_PD_VO>;
- clocks = <&cru HCLK_VO>,
- <&cru PCLK_VO>,
- <&cru ACLK_VOP_PRE>;
- pm_qos = <&qos_hdcp>,
- <&qos_vop_m0>,
- <&qos_vop_m1>;
- #power-domain-cells = <0>;
- };
-
- power-domain@RK3568_PD_RGA {
- reg = <RK3568_PD_RGA>;
- clocks = <&cru HCLK_RGA_PRE>,
- <&cru PCLK_RGA_PRE>;
- pm_qos = <&qos_ebc>,
- <&qos_iep>,
- <&qos_jpeg_dec>,
- <&qos_jpeg_enc>,
- <&qos_rga_rd>,
- <&qos_rga_wr>;
- #power-domain-cells = <0>;
- };
-
- power-domain@RK3568_PD_VPU {
- reg = <RK3568_PD_VPU>;
- clocks = <&cru HCLK_VPU_PRE>;
- pm_qos = <&qos_vpu>;
- #power-domain-cells = <0>;
- };
-
- power-domain@RK3568_PD_RKVDEC {
- clocks = <&cru HCLK_RKVDEC_PRE>;
- reg = <RK3568_PD_RKVDEC>;
- pm_qos = <&qos_rkvdec>;
- #power-domain-cells = <0>;
- };
-
- power-domain@RK3568_PD_RKVENC {
- reg = <RK3568_PD_RKVENC>;
- clocks = <&cru HCLK_RKVENC_PRE>;
- pm_qos = <&qos_rkvenc_rd_m0>,
- <&qos_rkvenc_rd_m1>,
- <&qos_rkvenc_wr_m0>;
- #power-domain-cells = <0>;
- };
- };
- };
-
- gpu: gpu@fde60000 {
- compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
- reg = <0x0 0xfde60000 0x0 0x4000>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "job", "mmu", "gpu";
- clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
- clock-names = "gpu", "bus";
- #cooling-cells = <2>;
- operating-points-v2 = <&gpu_opp_table>;
- power-domains = <&power RK3568_PD_GPU>;
- status = "disabled";
- };
-
- vpu: video-codec@fdea0400 {
- compatible = "rockchip,rk3568-vpu";
- reg = <0x0 0xfdea0000 0x0 0x800>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
- clock-names = "aclk", "hclk";
- iommus = <&vdpu_mmu>;
- power-domains = <&power RK3568_PD_VPU>;
- };
-
- vdpu_mmu: iommu@fdea0800 {
- compatible = "rockchip,rk3568-iommu";
- reg = <0x0 0xfdea0800 0x0 0x40>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "aclk", "iface";
- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
- power-domains = <&power RK3568_PD_VPU>;
- #iommu-cells = <0>;
- };
-
- rga: rga@fdeb0000 {
- compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
- reg = <0x0 0xfdeb0000 0x0 0x180>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
- clock-names = "aclk", "hclk", "sclk";
- resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
- reset-names = "core", "axi", "ahb";
- power-domains = <&power RK3568_PD_RGA>;
- };
-
- vepu: video-codec@fdee0000 {
- compatible = "rockchip,rk3568-vepu";
- reg = <0x0 0xfdee0000 0x0 0x800>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
- clock-names = "aclk", "hclk";
- iommus = <&vepu_mmu>;
- power-domains = <&power RK3568_PD_RGA>;
- };
-
- vepu_mmu: iommu@fdee0800 {
- compatible = "rockchip,rk3568-iommu";
- reg = <0x0 0xfdee0800 0x0 0x40>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
- clock-names = "aclk", "iface";
- power-domains = <&power RK3568_PD_RGA>;
- #iommu-cells = <0>;
- };
-
- sdmmc2: mmc@fe000000 {
- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xfe000000 0x0 0x4000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
- <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <150000000>;
- resets = <&cru SRST_SDMMC2>;
- reset-names = "reset";
- status = "disabled";
- };
-
- gmac1: ethernet@fe010000 {
- compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
- reg = <0x0 0xfe010000 0x0 0x10000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq", "eth_wake_irq";
- clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
- <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
- <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
- <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
- clock-names = "stmmaceth", "mac_clk_rx",
- "mac_clk_tx", "clk_mac_refout",
- "aclk_mac", "pclk_mac",
- "clk_mac_speed", "ptp_ref";
- resets = <&cru SRST_A_GMAC1>;
- reset-names = "stmmaceth";
- rockchip,grf = <&grf>;
- snps,axi-config = <&gmac1_stmmac_axi_setup>;
- snps,mixed-burst;
- snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
- snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
- snps,tso;
- status = "disabled";
-
- mdio1: mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- };
-
- gmac1_stmmac_axi_setup: stmmac-axi-config {
- snps,blen = <0 0 0 0 16 8 4>;
- snps,rd_osr_lmt = <8>;
- snps,wr_osr_lmt = <4>;
- };
-
- gmac1_mtl_rx_setup: rx-queues-config {
- snps,rx-queues-to-use = <1>;
- queue0 {};
- };
-
- gmac1_mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <1>;
- queue0 {};
- };
- };
-
- vop: vop@fe040000 {
- reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
- reg-names = "vop", "gamma-lut";
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
- <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
- clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
- iommus = <&vop_mmu>;
- power-domains = <&power RK3568_PD_VO>;
- rockchip,grf = <&grf>;
- status = "disabled";
-
- vop_out: ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- vp0: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- vp1: port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- vp2: port@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
- };
-
- vop_mmu: iommu@fe043e00 {
- compatible = "rockchip,rk3568-iommu";
- reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- status = "disabled";
- };
-
- dsi0: dsi@fe060000 {
- compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
- reg = <0x00 0xfe060000 0x00 0x10000>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "pclk";
- clocks = <&cru PCLK_DSITX_0>;
- phy-names = "dphy";
- phys = <&dsi_dphy0>;
- power-domains = <&power RK3568_PD_VO>;
- reset-names = "apb";
- resets = <&cru SRST_P_DSITX_0>;
- rockchip,grf = <&grf>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsi0_in: port@0 {
- reg = <0>;
- };
-
- dsi0_out: port@1 {
- reg = <1>;
- };
- };
- };
-
- dsi1: dsi@fe070000 {
- compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
- reg = <0x0 0xfe070000 0x0 0x10000>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "pclk";
- clocks = <&cru PCLK_DSITX_1>;
- phy-names = "dphy";
- phys = <&dsi_dphy1>;
- power-domains = <&power RK3568_PD_VO>;
- reset-names = "apb";
- resets = <&cru SRST_P_DSITX_1>;
- rockchip,grf = <&grf>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsi1_in: port@0 {
- reg = <0>;
- };
-
- dsi1_out: port@1 {
- reg = <1>;
- };
- };
- };
-
- hdmi: hdmi@fe0a0000 {
- compatible = "rockchip,rk3568-dw-hdmi";
- reg = <0x0 0xfe0a0000 0x0 0x20000>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMI_HOST>,
- <&cru CLK_HDMI_SFR>,
- <&cru CLK_HDMI_CEC>,
- <&pmucru CLK_HDMI_REF>,
- <&cru HCLK_VO>;
- clock-names = "iahb", "isfr", "cec", "ref";
- pinctrl-names = "default";
- pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
- power-domains = <&power RK3568_PD_VO>;
- reg-io-width = <4>;
- rockchip,grf = <&grf>;
- #sound-dai-cells = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- hdmi_in: port@0 {
- reg = <0>;
- };
-
- hdmi_out: port@1 {
- reg = <1>;
- };
- };
- };
-
- qos_gpu: qos@fe128000 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe128000 0x0 0x20>;
- };
-
- qos_rkvenc_rd_m0: qos@fe138080 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe138080 0x0 0x20>;
- };
-
- qos_rkvenc_rd_m1: qos@fe138100 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe138100 0x0 0x20>;
- };
-
- qos_rkvenc_wr_m0: qos@fe138180 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe138180 0x0 0x20>;
- };
-
- qos_isp: qos@fe148000 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe148000 0x0 0x20>;
- };
-
- qos_vicap0: qos@fe148080 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe148080 0x0 0x20>;
- };
-
- qos_vicap1: qos@fe148100 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe148100 0x0 0x20>;
- };
-
- qos_vpu: qos@fe150000 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe150000 0x0 0x20>;
- };
-
- qos_ebc: qos@fe158000 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe158000 0x0 0x20>;
- };
-
- qos_iep: qos@fe158100 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe158100 0x0 0x20>;
- };
-
- qos_jpeg_dec: qos@fe158180 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe158180 0x0 0x20>;
- };
-
- qos_jpeg_enc: qos@fe158200 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe158200 0x0 0x20>;
- };
-
- qos_rga_rd: qos@fe158280 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe158280 0x0 0x20>;
- };
-
- qos_rga_wr: qos@fe158300 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe158300 0x0 0x20>;
- };
-
- qos_npu: qos@fe180000 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe180000 0x0 0x20>;
- };
-
- qos_pcie2x1: qos@fe190000 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe190000 0x0 0x20>;
- };
-
- qos_sata1: qos@fe190280 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe190280 0x0 0x20>;
- };
-
- qos_sata2: qos@fe190300 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe190300 0x0 0x20>;
- };
-
- qos_usb3_0: qos@fe190380 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe190380 0x0 0x20>;
- };
-
- qos_usb3_1: qos@fe190400 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe190400 0x0 0x20>;
- };
-
- qos_rkvdec: qos@fe198000 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe198000 0x0 0x20>;
- };
-
- qos_hdcp: qos@fe1a8000 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe1a8000 0x0 0x20>;
- };
-
- qos_vop_m0: qos@fe1a8080 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe1a8080 0x0 0x20>;
- };
-
- qos_vop_m1: qos@fe1a8100 {
- compatible = "rockchip,rk3568-qos", "syscon";
- reg = <0x0 0xfe1a8100 0x0 0x20>;
- };
-
- dfi: dfi@fe230000 {
- compatible = "rockchip,rk3568-dfi";
- reg = <0x00 0xfe230000 0x00 0x400>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,pmu = <&pmugrf>;
- };
-
- pcie2x1: pcie@fe260000 {
- compatible = "rockchip,rk3568-pcie";
- reg = <0x3 0xc0000000 0x0 0x00400000>,
- <0x0 0xfe260000 0x0 0x00010000>,
- <0x0 0xf4000000 0x0 0x00100000>;
- reg-names = "dbi", "apb", "config";
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- bus-range = <0x0 0xf>;
- clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
- <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
- <&cru CLK_PCIE20_AUX_NDFT>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk", "aux";
- device_type = "pci";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc 0>,
- <0 0 0 2 &pcie_intc 1>,
- <0 0 0 3 &pcie_intc 2>,
- <0 0 0 4 &pcie_intc 3>;
- linux,pci-domain = <0>;
- num-ib-windows = <6>;
- num-ob-windows = <2>;
- max-link-speed = <2>;
- msi-map = <0x0 &gic 0x0 0x1000>;
- num-lanes = <1>;
- phys = <&combphy2 PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3568_PD_PIPE>;
- ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
- <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
- <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
- resets = <&cru SRST_PCIE20_POWERUP>;
- reset-names = "pipe";
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie_intc: legacy-interrupt-controller {
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- sdmmc0: mmc@fe2b0000 {
- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xfe2b0000 0x0 0x4000>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
- <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <150000000>;
- resets = <&cru SRST_SDMMC0>;
- reset-names = "reset";
- status = "disabled";
- };
-
- sdmmc1: mmc@fe2c0000 {
- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xfe2c0000 0x0 0x4000>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
- <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <150000000>;
- resets = <&cru SRST_SDMMC1>;
- reset-names = "reset";
- status = "disabled";
- };
-
- sfc: spi@fe300000 {
- compatible = "rockchip,sfc";
- reg = <0x0 0xfe300000 0x0 0x4000>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
- clock-names = "clk_sfc", "hclk_sfc";
- pinctrl-0 = <&fspi_pins>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- sdhci: mmc@fe310000 {
- compatible = "rockchip,rk3568-dwcmshc";
- reg = <0x0 0xfe310000 0x0 0x10000>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
- assigned-clock-rates = <200000000>, <24000000>;
- clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
- <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
- <&cru TCLK_EMMC>;
- clock-names = "core", "bus", "axi", "block", "timer";
- status = "disabled";
- };
-
- i2s0_8ch: i2s@fe400000 {
- compatible = "rockchip,rk3568-i2s-tdm";
- reg = <0x0 0xfe400000 0x0 0x1000>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
- assigned-clock-rates = <1188000000>, <1188000000>;
- clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- dmas = <&dmac1 0>;
- dma-names = "tx";
- resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
- reset-names = "tx-m", "rx-m";
- rockchip,grf = <&grf>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s1_8ch: i2s@fe410000 {
- compatible = "rockchip,rk3568-i2s-tdm";
- reg = <0x0 0xfe410000 0x0 0x1000>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
- assigned-clock-rates = <1188000000>, <1188000000>;
- clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
- <&cru HCLK_I2S1_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- dmas = <&dmac1 3>, <&dmac1 2>;
- dma-names = "rx", "tx";
- resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
- reset-names = "tx-m", "rx-m";
- rockchip,grf = <&grf>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
- &i2s1m0_lrcktx &i2s1m0_lrckrx
- &i2s1m0_sdi0 &i2s1m0_sdi1
- &i2s1m0_sdi2 &i2s1m0_sdi3
- &i2s1m0_sdo0 &i2s1m0_sdo1
- &i2s1m0_sdo2 &i2s1m0_sdo3>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s2_2ch: i2s@fe420000 {
- compatible = "rockchip,rk3568-i2s-tdm";
- reg = <0x0 0xfe420000 0x0 0x1000>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
- assigned-clock-rates = <1188000000>;
- clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- dmas = <&dmac1 4>, <&dmac1 5>;
- dma-names = "tx", "rx";
- resets = <&cru SRST_M_I2S2_2CH>;
- reset-names = "m";
- rockchip,grf = <&grf>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s2m0_sclktx
- &i2s2m0_lrcktx
- &i2s2m0_sdi
- &i2s2m0_sdo>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s3_2ch: i2s@fe430000 {
- compatible = "rockchip,rk3568-i2s-tdm";
- reg = <0x0 0xfe430000 0x0 0x1000>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>,
- <&cru HCLK_I2S3_2CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- dmas = <&dmac1 6>, <&dmac1 7>;
- dma-names = "tx", "rx";
- resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
- reset-names = "tx-m", "rx-m";
- rockchip,grf = <&grf>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- pdm: pdm@fe440000 {
- compatible = "rockchip,rk3568-pdm";
- reg = <0x0 0xfe440000 0x0 0x1000>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
- clock-names = "pdm_clk", "pdm_hclk";
- dmas = <&dmac1 9>;
- dma-names = "rx";
- pinctrl-0 = <&pdmm0_clk
- &pdmm0_clk1
- &pdmm0_sdi0
- &pdmm0_sdi1
- &pdmm0_sdi2
- &pdmm0_sdi3>;
- pinctrl-names = "default";
- resets = <&cru SRST_M_PDM>;
- reset-names = "pdm-m";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- spdif: spdif@fe460000 {
- compatible = "rockchip,rk3568-spdif";
- reg = <0x0 0xfe460000 0x0 0x1000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "mclk", "hclk";
- clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
- dmas = <&dmac1 1>;
- dma-names = "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spdifm0_tx>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- dmac0: dma-controller@fe530000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xfe530000 0x0 0x4000>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_BUS>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
-
- dmac1: dma-controller@fe550000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xfe550000 0x0 0x4000>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_BUS>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
-
- i2c1: i2c@fe5a0000 {
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfe5a0000 0x0 0x1000>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c1_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@fe5b0000 {
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfe5b0000 0x0 0x1000>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c2m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@fe5c0000 {
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfe5c0000 0x0 0x1000>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c3m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@fe5d0000 {
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfe5d0000 0x0 0x1000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c4m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c5: i2c@fe5e0000 {
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfe5e0000 0x0 0x1000>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c5m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- wdt: watchdog@fe600000 {
- compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
- reg = <0x0 0xfe600000 0x0 0x100>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
- clock-names = "tclk", "pclk";
- };
-
- spi0: spi@fe610000 {
- compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xfe610000 0x0 0x1000>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac0 20>, <&dmac0 21>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@fe620000 {
- compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xfe620000 0x0 0x1000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac0 22>, <&dmac0 23>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi2: spi@fe630000 {
- compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xfe630000 0x0 0x1000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac0 24>, <&dmac0 25>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi3: spi@fe640000 {
- compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xfe640000 0x0 0x1000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac0 26>, <&dmac0 27>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart1: serial@fe650000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe650000 0x0 0x100>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 2>, <&dmac0 3>;
- pinctrl-0 = <&uart1m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart2: serial@fe660000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe660000 0x0 0x100>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 4>, <&dmac0 5>;
- pinctrl-0 = <&uart2m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart3: serial@fe670000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe670000 0x0 0x100>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 6>, <&dmac0 7>;
- pinctrl-0 = <&uart3m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart4: serial@fe680000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe680000 0x0 0x100>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 8>, <&dmac0 9>;
- pinctrl-0 = <&uart4m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart5: serial@fe690000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe690000 0x0 0x100>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 10>, <&dmac0 11>;
- pinctrl-0 = <&uart5m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart6: serial@fe6a0000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe6a0000 0x0 0x100>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 12>, <&dmac0 13>;
- pinctrl-0 = <&uart6m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart7: serial@fe6b0000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe6b0000 0x0 0x100>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 14>, <&dmac0 15>;
- pinctrl-0 = <&uart7m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart8: serial@fe6c0000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe6c0000 0x0 0x100>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 16>, <&dmac0 17>;
- pinctrl-0 = <&uart8m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart9: serial@fe6d0000 {
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfe6d0000 0x0 0x100>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 18>, <&dmac0 19>;
- pinctrl-0 = <&uart9m0_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- thermal_zones: thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <100>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsadc 0>;
-
- trips {
- cpu_alert0: cpu_alert0 {
- temperature = <70000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_alert1: cpu_alert1 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit: cpu_crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert0>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
-
- gpu_thermal: gpu-thermal {
- polling-delay-passive = <20>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
-
- thermal-sensors = <&tsadc 1>;
-
- trips {
- gpu_threshold: gpu-threshold {
- temperature = <70000>;
- hysteresis = <2000>;
- type = "passive";
- };
- gpu_target: gpu-target {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- gpu_crit: gpu-crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&gpu_target>;
- cooling-device =
- <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
- tsadc: tsadc@fe710000 {
- compatible = "rockchip,rk3568-tsadc";
- reg = <0x0 0xfe710000 0x0 0x100>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
- assigned-clock-rates = <17000000>, <700000>;
- clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
- clock-names = "tsadc", "apb_pclk";
- resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
- <&cru SRST_TSADCPHY>;
- rockchip,grf = <&grf>;
- rockchip,hw-tshut-temp = <95000>;
- pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&tsadc_pin>;
- pinctrl-1 = <&tsadc_shutorg>;
- pinctrl-2 = <&tsadc_pin>;
- #thermal-sensor-cells = <1>;
- status = "disabled";
- };
-
- saradc: saradc@fe720000 {
- compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
- reg = <0x0 0xfe720000 0x0 0x100>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
- clock-names = "saradc", "apb_pclk";
- resets = <&cru SRST_P_SARADC>;
- reset-names = "saradc-apb";
- #io-channel-cells = <1>;
- status = "disabled";
- };
-
- pwm4: pwm@fe6e0000 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfe6e0000 0x0 0x10>;
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm4_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm5: pwm@fe6e0010 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfe6e0010 0x0 0x10>;
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm5_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm6: pwm@fe6e0020 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfe6e0020 0x0 0x10>;
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm6_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm7: pwm@fe6e0030 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfe6e0030 0x0 0x10>;
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm7_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm8: pwm@fe6f0000 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfe6f0000 0x0 0x10>;
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm8m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm9: pwm@fe6f0010 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfe6f0010 0x0 0x10>;
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm9m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm10: pwm@fe6f0020 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfe6f0020 0x0 0x10>;
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm10m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm11: pwm@fe6f0030 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfe6f0030 0x0 0x10>;
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm11m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm12: pwm@fe700000 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfe700000 0x0 0x10>;
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm12m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm13: pwm@fe700010 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfe700010 0x0 0x10>;
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm13m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm14: pwm@fe700020 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfe700020 0x0 0x10>;
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm14m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm15: pwm@fe700030 {
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfe700030 0x0 0x10>;
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm15m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- combphy1: phy@fe830000 {
- compatible = "rockchip,rk3568-naneng-combphy";
- reg = <0x0 0xfe830000 0x0 0x100>;
- clocks = <&pmucru CLK_PCIEPHY1_REF>,
- <&cru PCLK_PIPEPHY1>,
- <&cru PCLK_PIPE>;
- clock-names = "ref", "apb", "pipe";
- assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_PIPEPHY1>;
- rockchip,pipe-grf = <&pipegrf>;
- rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- combphy2: phy@fe840000 {
- compatible = "rockchip,rk3568-naneng-combphy";
- reg = <0x0 0xfe840000 0x0 0x100>;
- clocks = <&pmucru CLK_PCIEPHY2_REF>,
- <&cru PCLK_PIPEPHY2>,
- <&cru PCLK_PIPE>;
- clock-names = "ref", "apb", "pipe";
- assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_PIPEPHY2>;
- rockchip,pipe-grf = <&pipegrf>;
- rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
- #phy-cells = <1>;
- status = "disabled";
- };
-
- csi_dphy: phy@fe870000 {
- compatible = "rockchip,rk3568-csi-dphy";
- reg = <0x0 0xfe870000 0x0 0x10000>;
- clocks = <&cru PCLK_MIPICSIPHY>;
- clock-names = "pclk";
- #phy-cells = <0>;
- resets = <&cru SRST_P_MIPICSIPHY>;
- reset-names = "apb";
- rockchip,grf = <&grf>;
- status = "disabled";
- };
-
- dsi_dphy0: mipi-dphy@fe850000 {
- compatible = "rockchip,rk3568-dsi-dphy";
- reg = <0x0 0xfe850000 0x0 0x10000>;
- clock-names = "ref", "pclk";
- clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
- #phy-cells = <0>;
- power-domains = <&power RK3568_PD_VO>;
- reset-names = "apb";
- resets = <&cru SRST_P_MIPIDSIPHY0>;
- status = "disabled";
- };
-
- dsi_dphy1: mipi-dphy@fe860000 {
- compatible = "rockchip,rk3568-dsi-dphy";
- reg = <0x0 0xfe860000 0x0 0x10000>;
- clock-names = "ref", "pclk";
- clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
- #phy-cells = <0>;
- power-domains = <&power RK3568_PD_VO>;
- reset-names = "apb";
- resets = <&cru SRST_P_MIPIDSIPHY1>;
- status = "disabled";
- };
-
- usb2phy0: usb2phy@fe8a0000 {
- compatible = "rockchip,rk3568-usb2phy";
- reg = <0x0 0xfe8a0000 0x0 0x10000>;
- clocks = <&pmucru CLK_USBPHY0_REF>;
- clock-names = "phyclk";
- clock-output-names = "clk_usbphy0_480m";
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,usbgrf = <&usb2phy0_grf>;
- #clock-cells = <0>;
- status = "disabled";
-
- usb2phy0_host: host-port {
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usb2phy0_otg: otg-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
-
- usb2phy1: usb2phy@fe8b0000 {
- compatible = "rockchip,rk3568-usb2phy";
- reg = <0x0 0xfe8b0000 0x0 0x10000>;
- clocks = <&pmucru CLK_USBPHY1_REF>;
- clock-names = "phyclk";
- clock-output-names = "clk_usbphy1_480m";
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,usbgrf = <&usb2phy1_grf>;
- #clock-cells = <0>;
- status = "disabled";
-
- usb2phy1_host: host-port {
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usb2phy1_otg: otg-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3568-pinctrl";
- rockchip,grf = <&grf>;
- rockchip,pmu = <&pmugrf>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio@fdd60000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfdd60000 0x0 0x100>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 32>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@fe740000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfe740000 0x0 0x100>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 32 32>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@fe750000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfe750000 0x0 0x100>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 64 32>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@fe760000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfe760000 0x0 0x100>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 96 32>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@fe770000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfe770000 0x0 0x100>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 128 32>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-};
-
-#include "rk3568-pinctrl.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
- *
- */
-
-/dts-v1/;
-
-#include <dt-bindings/leds/common.h>
-#include "rk3588-coolpi-cm5.dtsi"
-
-/ {
- model = "RK3588 CoolPi CM5 EVB";
- compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588";
-
- backlight: backlight {
- compatible = "pwm-backlight";
- enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&bl_en>;
- power-supply = <&vcc12v_dcin>;
- pwms = <&pwm2 0 25000 0>;
- };
-
- leds: leds {
- compatible = "gpio-leds";
-
- green_led: led-0 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc3v3_sys: vcc3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc3v3_lcd: vcc3v3-lcd-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_lcd";
- enable-active-high;
- gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&lcdpwr_en>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- vcc5v0_usb_host1: vcc5v0_usb_host2: vcc5v0-usb-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
- regulator-boot-on;
- regulator-always-on;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb_host_pwren>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_otg";
- regulator-boot-on;
- regulator-always-on;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb_otg_pwren>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-/* M.2 E-Key */
-&pcie2x1l1 {
- reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_sys>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreq &pcie_wake &pcie_rst &wifi_pwron &bt_pwron>;
- status = "okay";
-};
-
-&pcie30phy {
- status = "okay";
-};
-
-/* Standard pcie */
-&pcie3x2 {
- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_sys>;
- status = "okay";
-};
-
-/* M.2 M-Key ssd */
-&pcie3x4 {
- num-lanes = <2>;
- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_sys>;
- status = "okay";
-};
-
-&pinctrl {
- lcd {
- lcdpwr_en: lcdpwr-en {
- rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- bl_en: bl-en {
- rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- usb_host_pwren: usb-host-pwren {
- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- usb_otg_pwren: usb-otg-pwren {
- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- wifi {
- bt_pwron: bt-pwron {
- rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- pcie_clkreq: pcie-clkreq {
- rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- pcie_rst: pcie-rst {
- rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- wifi_pwron: wifi-pwron {
- rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- pcie_wake: pcie-wake {
- rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&sata1 {
- status = "okay";
-};
-
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-&u2phy2_host {
- phy-supply = <&vcc5v0_usb_host1>;
- status = "okay";
-};
-
-&u2phy3_host {
- phy-supply = <&vcc5v0_usb_host2>;
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/dts-v1/;
-#include "rk3588.dtsi"
-#include "rk3588-edgeble-neu6a.dtsi"
-
-/ {
- model = "Edgeble Neu6A IO Board";
- compatible = "edgeble,neural-compute-module-6a-io",
- "edgeble,neural-compute-module-6a", "rockchip,rk3588";
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/ {
- compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588";
-
- aliases {
- mmc0 = &sdhci;
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/dts-v1/;
-#include "rk3588j.dtsi"
-#include "rk3588-edgeble-neu6b.dtsi"
-
-/ {
- model = "Edgeble Neu6B IO Board";
- compatible = "edgeble,neural-compute-module-6a-io",
- "edgeble,neural-compute-module-6b", "rockchip,rk3588";
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&i2c6 {
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <0>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- wakeup-source;
- };
-};
-
-&pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-/* FAN */
-&pwm2 {
- pinctrl-0 = <&pwm2m1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&sata0 {
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- no-sdio;
- no-mmc;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
-/* RS232 */
-&uart6 {
- pinctrl-0 = <&uart6m0_xfer>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-/* RS485 */
-&uart7 {
- pinctrl-0 = <&uart7m2_xfer>;
- pinctrl-names = "default";
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- *
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3588.dtsi"
-
-/ {
- model = "Rockchip RK3588 EVB1 V10 Board";
- compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588";
-
- aliases {
- ethernet0 = &gmac0;
- mmc0 = &sdhci;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 1>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- button-vol-up {
- label = "Volume Up";
- linux,code = <KEY_VOLUMEUP>;
- press-threshold-microvolt = <17000>;
- };
-
- button-vol-down {
- label = "Volume Down";
- linux,code = <KEY_VOLUMEDOWN>;
- press-threshold-microvolt = <417000>;
- };
-
- button-menu {
- label = "Menu";
- linux,code = <KEY_MENU>;
- press-threshold-microvolt = <890000>;
- };
-
- button-escape {
- label = "Escape";
- linux,code = <KEY_ESC>;
- press-threshold-microvolt = <1235000>;
- };
- };
-
- analog-sound {
- compatible = "simple-audio-card";
- pinctrl-names = "default";
- pinctrl-0 = <&hp_detect>;
- simple-audio-card,name = "RK3588 EVB1 Audio";
- simple-audio-card,aux-devs = <&_headphone>, <&_speaker>;
- simple-audio-card,bitclock-master = <&masterdai>;
- simple-audio-card,format = "i2s";
- simple-audio-card,frame-master = <&masterdai>;
- simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,pin-switches = "Headphones", "Speaker";
- simple-audio-card,routing =
- "Speaker Amplifier INL", "LOUT2",
- "Speaker Amplifier INR", "ROUT2",
- "Speaker", "Speaker Amplifier OUTL",
- "Speaker", "Speaker Amplifier OUTR",
- "Headphones Amplifier INL", "LOUT1",
- "Headphones Amplifier INR", "ROUT1",
- "Headphones", "Headphones Amplifier OUTL",
- "Headphones", "Headphones Amplifier OUTR",
- "LINPUT1", "Onboard Microphone",
- "RINPUT1", "Onboard Microphone",
- "LINPUT2", "Microphone Jack",
- "RINPUT2", "Microphone Jack";
- simple-audio-card,widgets =
- "Microphone", "Microphone Jack",
- "Microphone", "Onboard Microphone",
- "Headphone", "Headphones",
- "Speaker", "Speaker";
-
- simple-audio-card,cpu {
- sound-dai = <&i2s0_8ch>;
- };
-
- masterdai: simple-audio-card,codec {
- sound-dai = <&es8388>;
- system-clock-frequency = <12288000>;
- };
- };
-
- amp_headphone: headphone-amplifier {
- compatible = "simple-audio-amplifier";
- enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&headphone_amplifier_en>;
- sound-name-prefix = "Headphones Amplifier";
- };
-
- amp_speaker: speaker-amplifier {
- compatible = "simple-audio-amplifier";
- enable-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&speaker_amplifier_en>;
- sound-name-prefix = "Speaker Amplifier";
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- power-supply = <&vcc12v_dcin>;
- pwms = <&pwm2 0 25000 0>;
- };
-
- pcie20_avdd0v85: pcie20-avdd0v85-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie20_avdd0v85";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- vin-supply = <&avdd_0v85_s0>;
- };
-
- pcie20_avdd1v8: pcie20-avdd1v8-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie20_avdd1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&avcc_1v8_s0>;
- };
-
- pcie30_avdd0v75: pcie30-avdd0v75-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd0v75";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- vin-supply = <&avdd_0v75_s0>;
- };
-
- pcie30_avdd1v8: pcie30-avdd1v8-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&avcc_1v8_s0>;
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc3v3_pcie30: vcc3v3-pcie30-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie30";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <5000>;
- vin-supply = <&vcc12v_dcin>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc3v3_pcie30_en>;
- };
-
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usbdcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usb: vcc5v0-usb-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usbdcin>;
- };
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&combphy2_psu {
- status = "okay";
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_b3 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&gmac0 {
- clock_in_out = "output";
- phy-handle = <&rgmii_phy>;
- phy-mode = "rgmii-rxid";
- pinctrl-0 = <&gmac0_miim
- &gmac0_tx_bus2
- &gmac0_rx_bus2
- &gmac0_rgmii_clk
- &gmac0_rgmii_bus>;
- pinctrl-names = "default";
- rx_delay = <0x00>;
- tx_delay = <0x43>;
- status = "okay";
-};
-
-&i2c2 {
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
- wakeup-source;
- };
-};
-
-&i2c7 {
- status = "okay";
-
- es8388: audio-codec@11 {
- compatible = "everest,es8388";
- reg = <0x11>;
- clocks = <&cru I2S0_8CH_MCLKOUT>;
- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
- AVDD-supply = <&avcc_1v8_codec_s0>;
- DVDD-supply = <&avcc_1v8_codec_s0>;
- HPVDD-supply = <&vcc_3v3_s0>;
- PVDD-supply = <&vcc_3v3_s0>;
- #sound-dai-cells = <0>;
- };
-};
-
-&i2s0_8ch {
- pinctrl-0 = <&i2s0_lrck
- &i2s0_mclk
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdo0>;
- status = "okay";
-};
-
-&mdio0 {
- rgmii_phy: ethernet-phy@1 {
- /* RTL8211F */
- compatible = "ethernet-phy-id001c.c916";
- reg = <0x1>;
- pinctrl-names = "default";
- pinctrl-0 = <&rtl8211f_rst>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
- };
-};
-
-&pcie2x1l1 {
- reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>;
- status = "okay";
-};
-
-&pcie30phy {
- status = "okay";
-};
-
-&pcie3x4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie3_reset>;
- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie30>;
- status = "okay";
-};
-
-&pinctrl {
- audio {
- hp_detect: headphone-detect {
- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- headphone_amplifier_en: headphone-amplifier-en {
- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- speaker_amplifier_en: speaker-amplifier-en {
- rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- rtl8111 {
- rtl8111_isolate: rtl8111-isolate {
- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- rtl8211f {
- rtl8211f_rst: rtl8211f-rst {
- rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- };
-
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- pcie2 {
- pcie2_1_rst: pcie2-1-rst {
- rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie3 {
- pcie3_reset: pcie3-reset {
- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc3v3_pcie30_en: vcc3v3-pcie30-en {
- rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8_s0>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
-};
-
-&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <2>;
-
- pmic@0 {
- compatible = "rockchip,rk806";
- reg = <0x0>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
- pinctrl-names = "default";
- spi-max-frequency = <1000000>;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc5v0_sys>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl1";
- function = "pin_fun0";
- };
-
- rk806_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
-
- regulators {
- vdd_gpu_s0: dcdc-reg1 {
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_gpu_s0";
- regulator-enable-ramp-delay = <400>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_npu_s0: dcdc-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_npu_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: dcdc-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_log_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: dcdc-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_vdenc_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
-
- };
-
- vdd_gpu_mem_s0: dcdc-reg5 {
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-enable-ramp-delay = <400>;
- regulator-name = "vdd_gpu_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
-
- };
-
- vdd_npu_mem_s0: dcdc-reg6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_npu_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
-
- };
-
- vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_2v0_pldo_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vdd_vdenc_mem_s0: dcdc-reg8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_vdenc_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd2_ddr_s3: dcdc-reg9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vdd2_ddr_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v1_nldo_s3: dcdc-reg10 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1100000>;
- };
- };
-
- avcc_1v8_s0: pldo-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avcc_1v8_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd1_1v8_ddr_s3: pldo-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd1_1v8_ddr_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_codec_s0: pldo-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avcc_1v8_codec_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s3: pldo-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vccio_sd_s0: pldo-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vccio_sd_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_1v8_s3: pldo-reg6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vccio_1v8_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: nldo-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_0v75_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd2l_0v9_ddr_s3: nldo-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-name = "vdd2l_0v9_ddr_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdd_0v75_hdmi_edp_s0: nldo-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_hdmi_edp_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_0v75_s0: nldo-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "avdd_0v75_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: nldo-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_0v85_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- pmic@1 {
- compatible = "rockchip,rk806";
- reg = <0x01>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>,
- <&rk806_slave_dvs3_null>;
- pinctrl-names = "default";
- spi-max-frequency = <1000000>;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_2v0_pldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- rk806_slave_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl1";
- function = "pin_fun0";
- };
-
- rk806_slave_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_slave_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- regulators {
- vdd_cpu_big1_s0: dcdc-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_big1_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big0_s0: dcdc-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_big0_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: dcdc-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_lit_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: dcdc-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big1_mem_s0: dcdc-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_big1_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
-
- vdd_cpu_big0_mem_s0: dcdc-reg6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_big0_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: dcdc-reg7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_1v8_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_mem_s0: dcdc-reg8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_lit_mem_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vddq_ddr_s0: dcdc-reg9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vddq_ddr_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: dcdc-reg10 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_ddr_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_cam_s0: pldo-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_1v8_cam_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd1v8_ddr_pll_s0: pldo-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avdd1v8_ddr_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_1v8_pll_s0: pldo-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_1v8_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_sd_s0: pldo-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_sd_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_2v8_cam_s0: pldo-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_2v8_cam_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: pldo-reg6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "pldo6_s3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_pll_s0: nldo-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_0v75_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_pll_s0: nldo-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_ddr_pll_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_0v85_s0: nldo-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avdd_0v85_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_1v2_cam_s0: nldo-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avdd_1v2_cam_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_1v2_s0: nldo-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "avdd_1v2_s0";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&sata0 {
- status = "okay";
-};
-
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy2_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
status = "okay";
};
-&usbdp_phy0_u3 {
- status = "okay";
-};
-
&usb_host0_xhci {
dr_mode = "peripheral";
maximum-speed = "high-speed";
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2023 Thomas McKahan
- *
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/usb/pd.h>
-#include "rk3588.dtsi"
-
-/ {
- model = "FriendlyElec NanoPC-T6";
- compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
-
- aliases {
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- leds {
- compatible = "gpio-leds";
-
- sys_led: led-0 {
- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
- label = "system-led";
- linux,default-trigger = "heartbeat";
- pinctrl-names = "default";
- pinctrl-0 = <&sys_led_pin>;
- };
-
- usr_led: led-1 {
- gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
- label = "user-led";
- pinctrl-names = "default";
- pinctrl-0 = <&usr_led_pin>;
- };
- };
-
- sound {
- compatible = "simple-audio-card";
- pinctrl-names = "default";
- pinctrl-0 = <&hp_det>;
-
- simple-audio-card,name = "realtek,rt5616-codec";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
-
- simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
- simple-audio-card,hp-pin-name = "Headphones";
-
- simple-audio-card,widgets =
- "Headphone", "Headphones",
- "Microphone", "Microphone Jack";
- simple-audio-card,routing =
- "Headphones", "HPOL",
- "Headphones", "HPOR",
- "MIC1", "Microphone Jack",
- "Microphone Jack", "micbias1";
-
- simple-audio-card,cpu {
- sound-dai = <&i2s0_8ch>;
- };
- simple-audio-card,codec {
- sound-dai = <&rt5616>;
- };
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- /* vcc5v0_sys powers peripherals */
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- /* vcc4v0_sys powers the RK806, RK860's */
- vcc4v0_sys: vcc4v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc4v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <4000000>;
- regulator-max-microvolt = <4000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc-1v1-nldo-s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc4v0_sys>;
- };
-
- vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_pcie20";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_3v3_s3>;
- };
-
- vbus5v0_typec: vbus5v0-typec-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&typec5v_pwren>;
- regulator-name = "vbus5v0_typec";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_m2_1_pwren>;
- regulator-name = "vcc3v3_pcie2x1l0";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_pcie30: vcc3v3-pcie30-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_m2_0_pwren>;
- regulator-name = "vcc3v3_pcie30";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&combphy1_ps {
- status = "okay";
-};
-
-&combphy2_psu {
- status = "okay";
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_b0{
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b1{
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b2{
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_b3{
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&gpio0 {
- gpio-line-names = /* GPIO0 A0-A7 */
- "", "", "", "",
- "", "", "", "",
- /* GPIO0 B0-B7 */
- "", "", "", "",
- "", "", "", "",
- /* GPIO0 C0-C7 */
- "", "", "", "",
- "HEADER_10", "HEADER_08", "HEADER_32", "",
- /* GPIO0 D0-D7 */
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpio1 {
- gpio-line-names = /* GPIO1 A0-A7 */
- "HEADER_27", "HEADER_28", "", "",
- "", "", "", "HEADER_15",
- /* GPIO1 B0-B7 */
- "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23",
- "HEADER_24", "HEADER_22", "", "",
- /* GPIO1 C0-C7 */
- "", "", "", "",
- "", "", "", "",
- /* GPIO1 D0-D7 */
- "", "", "", "",
- "", "", "HEADER_05", "HEADER_03";
-};
-
-&gpio2 {
- gpio-line-names = /* GPIO2 A0-A7 */
- "", "", "", "",
- "", "", "", "",
- /* GPIO2 B0-B7 */
- "", "", "", "",
- "", "", "", "",
- /* GPIO2 C0-C7 */
- "", "CSI1_11", "CSI1_12", "",
- "", "", "", "",
- /* GPIO2 D0-D7 */
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpio3 {
- gpio-line-names = /* GPIO3 A0-A7 */
- "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36",
- "HEADER_37", "", "DSI0_12", "",
- /* GPIO3 B0-B7 */
- "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16",
- "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12",
- /* GPIO3 C0-C7 */
- "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13",
- "", "", "", "",
- /* GPIO3 D0-D7 */
- "", "", "", "",
- "", "DSI1_10", "", "";
-};
-
-&gpio4 {
- gpio-line-names = /* GPIO4 A0-A7 */
- "DSI1_08", "DSI1_14", "", "DSI1_12",
- "", "", "", "",
- /* GPIO4 B0-B7 */
- "", "", "", "",
- "", "", "", "",
- /* GPIO4 C0-C7 */
- "", "", "", "",
- "CSI0_11", "CSI0_12", "", "",
- /* GPIO4 D0-D7 */
- "", "", "", "",
- "", "", "", "";
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
- status = "okay";
-
- vdd_cpu_big0_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big0_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc4v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big1_s0: regulator@43 {
- compatible = "rockchip,rk8603", "rockchip,rk8602";
- reg = <0x43>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big1_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc4v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c2 {
- status = "okay";
-
- vdd_npu_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- rockchip,suspend-voltage-selector = <1>;
- regulator-name = "vdd_npu_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc4v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c6 {
- clock-frequency = <200000>;
- status = "okay";
-
- fusb302: typec-portc@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-0 = <&usbc0_int>;
- pinctrl-names = "default";
- vbus-supply = <&vbus5v0_typec>;
-
- connector {
- compatible = "usb-c-connector";
- data-role = "dual";
- label = "USB-C";
- power-role = "dual";
- try-power-role = "sink";
- source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- op-sink-microwatt = <1000000>;
- };
- };
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
- wakeup-source;
- };
-};
-
-&i2c7 {
- clock-frequency = <200000>;
- status = "okay";
-
- rt5616: codec@1b {
- compatible = "realtek,rt5616";
- reg = <0x1b>;
- clocks = <&cru I2S0_8CH_MCLKOUT>;
- clock-names = "mclk";
- #sound-dai-cells = <0>;
- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
-
- port {
- rt5616_p0_0: endpoint {
- remote-endpoint = <&i2s0_8ch_p0_0>;
- };
- };
- };
-
- /* connected with MIPI-CSI1 */
-};
-
-&i2c8 {
- pinctrl-0 = <&i2c8m2_xfer>;
-};
-
-&i2s0_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_lrck
- &i2s0_mclk
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdo0>;
- status = "okay";
-
- i2s0_8ch_p0: port {
- i2s0_8ch_p0_0: endpoint {
- dai-format = "i2s";
- mclk-fs = <256>;
- remote-endpoint = <&rt5616_p0_0>;
- };
- };
-};
-
-&pcie2x1l0 {
- reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc_3v3_pcie20>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_0_rst>;
- status = "okay";
-};
-
-&pcie2x1l1 {
- reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_1_rst>;
- status = "okay";
-};
-
-&pcie2x1l2 {
- reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc_3v3_pcie20>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_2_rst>;
- status = "okay";
-};
-
-&pcie30phy {
- status = "okay";
-};
-
-&pcie3x4 {
- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie30>;
- status = "okay";
-};
-
-&pinctrl {
- gpio-leds {
- sys_led_pin: sys-led-pin {
- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- usr_led_pin: usr-led-pin {
- rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- headphone {
- hp_det: hp-det {
- rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- pcie {
- pcie2_0_rst: pcie2-0-rst {
- rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie2_1_rst: pcie2-1-rst {
- rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie2_2_rst: pcie2-2-rst {
- rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_m2_0_pwren: pcie-m20-pwren {
- rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie_m2_1_pwren: pcie-m21-pwren {
- rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- typec5v_pwren: typec5v-pwren {
- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- usbc0_int: usbc0-int {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pwm1 {
- pinctrl-0 = <&pwm1m1_pins>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&avcc_1v8_s0>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- max-frequency = <200000000>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- no-mmc;
- no-sdio;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
-&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- num-cs = <1>;
-
- pmic@0 {
- compatible = "rockchip,rk806";
- spi-max-frequency = <1000000>;
- reg = <0x0>;
-
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-
- system-power-controller;
-
- vcc1-supply = <&vcc4v0_sys>;
- vcc2-supply = <&vcc4v0_sys>;
- vcc3-supply = <&vcc4v0_sys>;
- vcc4-supply = <&vcc4v0_sys>;
- vcc5-supply = <&vcc4v0_sys>;
- vcc6-supply = <&vcc4v0_sys>;
- vcc7-supply = <&vcc4v0_sys>;
- vcc8-supply = <&vcc4v0_sys>;
- vcc9-supply = <&vcc4v0_sys>;
- vcc10-supply = <&vcc4v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc4v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc4v0_sys>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl1";
- function = "pin_fun0";
- };
-
- rk806_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- regulators {
- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_gpu_s0";
- regulator-enable-ramp-delay = <400>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_lit_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: dcdc-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_log_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-init-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_vdenc_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: dcdc-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_ddr_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- vdd2_ddr_s3: dcdc-reg6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vdd2_ddr_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_2v0_pldo_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vcc_3v3_s3: dcdc-reg8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_3v3_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vddq_ddr_s0: dcdc-reg9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vddq_ddr_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s3: dcdc-reg10 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_s0: pldo-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "avcc_1v8_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: pldo-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avdd_1v2_s0: pldo-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-name = "avdd_1v2_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: pldo-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd_s0: pldo-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vccio_sd_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: pldo-reg6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "pldo6_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: nldo-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_ddr_pll_s0: nldo-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_ddr_pll_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- avdd_0v75_s0: nldo-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "avdd_0v75_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: nldo-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_0v85_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v75_s0: nldo-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&tsadc {
- status = "okay";
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
-&u2phy2_host {
- status = "okay";
-};
-
-&u2phy3_host {
- status = "okay";
-};
-
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2023 Ondřej Jirman <megi@xff.cz>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/usb/pd.h>
-#include "rk3588.dtsi"
-
-/ {
- model = "Xunlong Orange Pi 5 Plus";
- compatible = "xunlong,orangepi-5-plus", "rockchip,rk3588";
-
- aliases {
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- adc-keys-0 {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- button-maskrom {
- label = "Mask Rom";
- linux,code = <KEY_SETUP>;
- press-threshold-microvolt = <2000>;
- };
- };
-
- adc-keys-1 {
- compatible = "adc-keys";
- io-channels = <&saradc 1>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- button-recovery {
- label = "Recovery";
- linux,code = <KEY_VENDOR>;
- press-threshold-microvolt = <2000>;
- };
- };
-
- speaker_amp: speaker-audio-amplifier {
- compatible = "simple-audio-amplifier";
- enable-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
- sound-name-prefix = "Speaker Amp";
- };
-
- headphone_amp: headphones-audio-amplifier {
- compatible = "simple-audio-amplifier";
- enable-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
- sound-name-prefix = "Headphones Amp";
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&ir_receiver_pin>;
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&blue_led_pin>;
-
- led {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <1>;
- gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
- };
- };
-
- fan: pwm-fan {
- compatible = "pwm-fan";
- cooling-levels = <0 70 75 80 100>;
- fan-supply = <&vcc5v0_sys>;
- pwms = <&pwm3 0 50000 0>;
- #cooling-cells = <2>;
- };
-
- pwm-leds {
- compatible = "pwm-leds";
-
- led {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <2>;
- max-brightness = <255>;
- pwms = <&pwm2 0 25000 0>;
- };
- };
-
- sound {
- compatible = "simple-audio-card";
- pinctrl-names = "default";
- pinctrl-0 = <&hp_detect>;
- simple-audio-card,name = "Analog";
- simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>;
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
- simple-audio-card,bitclock-master = <&daicpu>;
- simple-audio-card,frame-master = <&daicpu>;
- /*TODO: SARADC_IN3 is used as MIC detection / key input */
-
- simple-audio-card,widgets =
- "Microphone", "Onboard Microphone",
- "Microphone", "Microphone Jack",
- "Speaker", "Speaker",
- "Headphone", "Headphones";
-
- simple-audio-card,routing =
- "Headphones", "LOUT1",
- "Headphones", "ROUT1",
- "Speaker", "LOUT2",
- "Speaker", "ROUT2",
-
- "Headphones", "Headphones Amp OUTL",
- "Headphones", "Headphones Amp OUTR",
- "Headphones Amp INL", "LOUT1",
- "Headphones Amp INR", "ROUT1",
-
- "Speaker", "Speaker Amp OUTL",
- "Speaker", "Speaker Amp OUTR",
- "Speaker Amp INL", "LOUT2",
- "Speaker Amp INR", "ROUT2",
-
- /* single ended signal to LINPUT1 */
- "LINPUT1", "Microphone Jack",
- "RINPUT1", "Microphone Jack",
- /* differential signal */
- "LINPUT2", "Onboard Microphone",
- "RINPUT2", "Onboard Microphone";
-
- daicpu: simple-audio-card,cpu {
- sound-dai = <&i2s0_8ch>;
- system-clock-frequency = <12288000>;
- };
-
- daicodec: simple-audio-card,codec {
- sound-dai = <&es8388>;
- system-clock-frequency = <12288000>;
- };
- };
-
- vcc3v3_pcie30: vcc3v3-pcie30-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc3v3_pcie30";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <5000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_pcie_eth: vcc3v3-pcie-eth-regulator {
- compatible = "regulator-fixed";
- gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
- regulator-name = "vcc3v3_pcie_eth";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <50000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_wf: vcc3v3-wf-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc3v3_wf";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <50000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc5v0_usb20: vcc5v0-usb20-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb20_en>;
- regulator-name = "vcc5v0_usb20";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&combphy1_ps {
- status = "okay";
-};
-
-&combphy2_psu {
- status = "okay";
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_b3 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
- status = "okay";
-
- vdd_cpu_big0_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big0_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big1_s0: regulator@43 {
- compatible = "rockchip,rk8603", "rockchip,rk8602";
- reg = <0x43>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big1_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c6 {
- clock-frequency = <400000>;
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <0>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- wakeup-source;
- };
-};
-
-&i2c7 {
- status = "okay";
-
- /* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */
- es8388: audio-codec@11 {
- compatible = "everest,es8388";
- reg = <0x11>;
- clocks = <&cru I2S0_8CH_MCLKOUT>;
- clock-names = "mclk";
- AVDD-supply = <&vcc_1v8_s0>;
- DVDD-supply = <&vcc_1v8_s0>;
- HPVDD-supply = <&vcc_3v3_s0>;
- PVDD-supply = <&vcc_3v3_s0>;
- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
- #sound-dai-cells = <0>;
- };
-};
-
-&i2s0_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_lrck
- &i2s0_mclk
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdo0>;
- status = "okay";
-};
-
-&i2s2_2ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s2m0_lrck
- &i2s2m0_sclk
- &i2s2m0_sdi
- &i2s2m0_sdo>;
- status = "okay";
-};
-
-/* phy1 - M.KEY socket */
-&pcie2x1l0 {
- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_wf>;
- status = "okay";
-};
-
-/* phy2 - right ethernet port */
-&pcie2x1l1 {
- reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie_eth>;
- status = "okay";
-};
-
-/* phy0 - left ethernet port */
-&pcie2x1l2 {
- reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie_eth>;
- status = "okay";
-};
-
-&pcie30phy {
- status = "okay";
-};
-
-&pcie3x4 {
- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie30>;
- status = "okay";
-};
-
-&pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- leds {
- blue_led_pin: blue-led {
- rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- ir-receiver {
- ir_receiver_pin: ir-receiver-pin {
- rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sound {
- hp_detect: hp-detect {
- rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- vcc5v0_usb20_en: vcc5v0-usb20-en {
- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm2 {
- pinctrl-0 = <&pwm2m1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&pwm3 {
- pinctrl-0 = <&pwm3m1_pins>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8_s0>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- max-frequency = <200000000>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- no-sdio;
- no-mmc;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
-&sfc {
- pinctrl-names = "default";
- pinctrl-0 = <&fspim1_pins>;
- status = "okay";
-
- spi_flash: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-max-frequency = <100000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <1>;
- };
-};
-
-&spi2 {
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- status = "okay";
-
- pmic@0 {
- compatible = "rockchip,rk806";
- reg = <0x0>;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
- spi-max-frequency = <1000000>;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vdd2_ddr_s3>;
- vcc14-supply = <&vdd2_ddr_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- regulators {
- vdd_gpu_s0: dcdc-reg1 {
- regulator-name = "vdd_gpu_s0";
- regulator-boot-on;
- regulator-enable-ramp-delay = <400>;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: dcdc-reg2 {
- regulator-name = "vdd_cpu_lit_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: dcdc-reg3 {
- regulator-name = "vdd_log_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <825000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: dcdc-reg4 {
- regulator-name = "vdd_vdenc_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <825000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: dcdc-reg5 {
- regulator-name = "vdd_ddr_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- vdd2_ddr_s3: dcdc-reg6 {
- regulator-name = "vdd2_ddr_s3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-name = "vdd_2v0_pldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vcc_3v3_s3: dcdc-reg8 {
- regulator-name = "vcc_3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vddq_ddr_s0: dcdc-reg9 {
- regulator-name = "vddq_ddr_s0";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s3: dcdc-reg10 {
- regulator-name = "vcc_1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_s0: pldo-reg1 {
- regulator-name = "avcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- /* shorted to avcc_1v8_s0 on the board */
- vcc_1v8_s0: pldo-reg2 {
- regulator-name = "vcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avdd_1v2_s0: pldo-reg3 {
- regulator-name = "avdd_1v2_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: pldo-reg4 {
- regulator-name = "vcc_3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd_s0: pldo-reg5 {
- regulator-name = "vccio_sd_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: pldo-reg6 {
- regulator-name = "pldo6_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: nldo-reg1 {
- regulator-name = "vdd_0v75_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_ddr_pll_s0: nldo-reg2 {
- regulator-name = "vdd_ddr_pll_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- avdd_0v75_s0: nldo-reg3 {
- regulator-name = "avdd_0v75_s0";
- regulator-always-on;
- regulator-boot-on;
- /*
- * The schematic mentions that actual setting
- * should be 0.8375V. RK3588 datasheet specifies
- * maximum as 0.825V. So we set datasheet max
- * here.
- */
- regulator-min-microvolt = <825000>;
- regulator-max-microvolt = <825000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: nldo-reg4 {
- regulator-name = "vdd_0v85_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v75_s0: nldo-reg5 {
- regulator-name = "vdd_0v75_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-&u2phy2_host {
- phy-supply = <&vcc5v0_usb20>;
- status = "okay";
-};
-
-&u2phy3_host {
- phy-supply = <&vcc5v0_usb20>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
-&uart9 {
- pinctrl-0 = <&uart9m0_xfer>;
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rockchip-pinconf.dtsi"
-
-/*
- * This file is auto generated by pin2dts tool, please keep these code
- * by adding changes at end of this file.
- */
-&pinctrl {
- clk32k {
- /omit-if-no-ref/
- clk32k_out1: clk32k-out1 {
- rockchip,pins =
- /* clk32k_out1 */
- <2 RK_PC5 1 &pcfg_pull_none>;
- };
-
- };
-
- eth0 {
- /omit-if-no-ref/
- eth0_pins: eth0-pins {
- rockchip,pins =
- /* eth0_refclko_25m */
- <2 RK_PC3 1 &pcfg_pull_none>;
- };
-
- };
-
- fspi {
- /omit-if-no-ref/
- fspim1_pins: fspim1-pins {
- rockchip,pins =
- /* fspi_clk_m1 */
- <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
- /* fspi_cs0n_m1 */
- <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
- /* fspi_d0_m1 */
- <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
- /* fspi_d1_m1 */
- <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
- /* fspi_d2_m1 */
- <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
- /* fspi_d3_m1 */
- <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- fspim1_cs1: fspim1-cs1 {
- rockchip,pins =
- /* fspi_cs1n_m1 */
- <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
- };
- };
-
- gmac0 {
- /omit-if-no-ref/
- gmac0_miim: gmac0-miim {
- rockchip,pins =
- /* gmac0_mdc */
- <4 RK_PC4 1 &pcfg_pull_none>,
- /* gmac0_mdio */
- <4 RK_PC5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_clkinout: gmac0-clkinout {
- rockchip,pins =
- /* gmac0_mclkinout */
- <4 RK_PC3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_rx_bus2: gmac0-rx-bus2 {
- rockchip,pins =
- /* gmac0_rxd0 */
- <2 RK_PC1 1 &pcfg_pull_none>,
- /* gmac0_rxd1 */
- <2 RK_PC2 1 &pcfg_pull_none>,
- /* gmac0_rxdv_crs */
- <4 RK_PC2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_tx_bus2: gmac0-tx-bus2 {
- rockchip,pins =
- /* gmac0_txd0 */
- <2 RK_PB6 1 &pcfg_pull_none>,
- /* gmac0_txd1 */
- <2 RK_PB7 1 &pcfg_pull_none>,
- /* gmac0_txen */
- <2 RK_PC0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_rgmii_clk: gmac0-rgmii-clk {
- rockchip,pins =
- /* gmac0_rxclk */
- <2 RK_PB0 1 &pcfg_pull_none>,
- /* gmac0_txclk */
- <2 RK_PB3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_rgmii_bus: gmac0-rgmii-bus {
- rockchip,pins =
- /* gmac0_rxd2 */
- <2 RK_PA6 1 &pcfg_pull_none>,
- /* gmac0_rxd3 */
- <2 RK_PA7 1 &pcfg_pull_none>,
- /* gmac0_txd2 */
- <2 RK_PB1 1 &pcfg_pull_none>,
- /* gmac0_txd3 */
- <2 RK_PB2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_ppsclk: gmac0-ppsclk {
- rockchip,pins =
- /* gmac0_ppsclk */
- <2 RK_PC4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_ppstring: gmac0-ppstring {
- rockchip,pins =
- /* gmac0_ppstring */
- <2 RK_PB5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_ptp_refclk: gmac0-ptp-refclk {
- rockchip,pins =
- /* gmac0_ptp_refclk */
- <2 RK_PB4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac0_txer: gmac0-txer {
- rockchip,pins =
- /* gmac0_txer */
- <4 RK_PC6 1 &pcfg_pull_none>;
- };
-
- };
-
- hdmi {
- /omit-if-no-ref/
- hdmim0_tx1_cec: hdmim0-tx1-cec {
- rockchip,pins =
- /* hdmim0_tx1_cec */
- <2 RK_PC4 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx1_scl: hdmim0-tx1-scl {
- rockchip,pins =
- /* hdmim0_tx1_scl */
- <2 RK_PB5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx1_sda: hdmim0-tx1-sda {
- rockchip,pins =
- /* hdmim0_tx1_sda */
- <2 RK_PB4 4 &pcfg_pull_none>;
- };
- };
-
- i2c0 {
- /omit-if-no-ref/
- i2c0m1_xfer: i2c0m1-xfer {
- rockchip,pins =
- /* i2c0_scl_m1 */
- <4 RK_PC5 9 &pcfg_pull_none_smt>,
- /* i2c0_sda_m1 */
- <4 RK_PC6 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c2 {
- /omit-if-no-ref/
- i2c2m1_xfer: i2c2m1-xfer {
- rockchip,pins =
- /* i2c2_scl_m1 */
- <2 RK_PC1 9 &pcfg_pull_none_smt>,
- /* i2c2_sda_m1 */
- <2 RK_PC0 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c3 {
- /omit-if-no-ref/
- i2c3m3_xfer: i2c3m3-xfer {
- rockchip,pins =
- /* i2c3_scl_m3 */
- <2 RK_PB2 9 &pcfg_pull_none_smt>,
- /* i2c3_sda_m3 */
- <2 RK_PB3 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c4 {
- /omit-if-no-ref/
- i2c4m1_xfer: i2c4m1-xfer {
- rockchip,pins =
- /* i2c4_scl_m1 */
- <2 RK_PB5 9 &pcfg_pull_none_smt>,
- /* i2c4_sda_m1 */
- <2 RK_PB4 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c5 {
- /omit-if-no-ref/
- i2c5m4_xfer: i2c5m4-xfer {
- rockchip,pins =
- /* i2c5_scl_m4 */
- <2 RK_PB6 9 &pcfg_pull_none_smt>,
- /* i2c5_sda_m4 */
- <2 RK_PB7 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c6 {
- /omit-if-no-ref/
- i2c6m2_xfer: i2c6m2-xfer {
- rockchip,pins =
- /* i2c6_scl_m2 */
- <2 RK_PC3 9 &pcfg_pull_none_smt>,
- /* i2c6_sda_m2 */
- <2 RK_PC2 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c7 {
- /omit-if-no-ref/
- i2c7m1_xfer: i2c7m1-xfer {
- rockchip,pins =
- /* i2c7_scl_m1 */
- <4 RK_PC3 9 &pcfg_pull_none_smt>,
- /* i2c7_sda_m1 */
- <4 RK_PC4 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c8 {
- /omit-if-no-ref/
- i2c8m1_xfer: i2c8m1-xfer {
- rockchip,pins =
- /* i2c8_scl_m1 */
- <2 RK_PB0 9 &pcfg_pull_none_smt>,
- /* i2c8_sda_m1 */
- <2 RK_PB1 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2s2 {
- /omit-if-no-ref/
- i2s2m0_lrck: i2s2m0-lrck {
- rockchip,pins =
- /* i2s2m0_lrck */
- <2 RK_PC0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_mclk: i2s2m0-mclk {
- rockchip,pins =
- /* i2s2m0_mclk */
- <2 RK_PB6 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sclk: i2s2m0-sclk {
- rockchip,pins =
- /* i2s2m0_sclk */
- <2 RK_PB7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sdi: i2s2m0-sdi {
- rockchip,pins =
- /* i2s2m0_sdi */
- <2 RK_PC3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sdo: i2s2m0-sdo {
- rockchip,pins =
- /* i2s2m0_sdo */
- <4 RK_PC3 2 &pcfg_pull_none>;
- };
- };
-
- pwm2 {
- /omit-if-no-ref/
- pwm2m2_pins: pwm2m2-pins {
- rockchip,pins =
- /* pwm2_m2 */
- <4 RK_PC2 11 &pcfg_pull_none>;
- };
- };
-
- pwm4 {
- /omit-if-no-ref/
- pwm4m1_pins: pwm4m1-pins {
- rockchip,pins =
- /* pwm4_m1 */
- <4 RK_PC3 11 &pcfg_pull_none>;
- };
- };
-
- pwm5 {
- /omit-if-no-ref/
- pwm5m2_pins: pwm5m2-pins {
- rockchip,pins =
- /* pwm5_m2 */
- <4 RK_PC4 11 &pcfg_pull_none>;
- };
- };
-
- pwm6 {
- /omit-if-no-ref/
- pwm6m2_pins: pwm6m2-pins {
- rockchip,pins =
- /* pwm6_m2 */
- <4 RK_PC5 11 &pcfg_pull_none>;
- };
- };
-
- pwm7 {
- /omit-if-no-ref/
- pwm7m3_pins: pwm7m3-pins {
- rockchip,pins =
- /* pwm7_ir_m3 */
- <4 RK_PC6 11 &pcfg_pull_none>;
- };
- };
-
- sdio {
- /omit-if-no-ref/
- sdiom0_pins: sdiom0-pins {
- rockchip,pins =
- /* sdio_clk_m0 */
- <2 RK_PB3 2 &pcfg_pull_none>,
- /* sdio_cmd_m0 */
- <2 RK_PB2 2 &pcfg_pull_none>,
- /* sdio_d0_m0 */
- <2 RK_PA6 2 &pcfg_pull_none>,
- /* sdio_d1_m0 */
- <2 RK_PA7 2 &pcfg_pull_none>,
- /* sdio_d2_m0 */
- <2 RK_PB0 2 &pcfg_pull_none>,
- /* sdio_d3_m0 */
- <2 RK_PB1 2 &pcfg_pull_none>;
- };
- };
-
- spi1 {
- /omit-if-no-ref/
- spi1m0_pins: spi1m0-pins {
- rockchip,pins =
- /* spi1_clk_m0 */
- <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
- /* spi1_miso_m0 */
- <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
- /* spi1_mosi_m0 */
- <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m0_cs0: spi1m0-cs0 {
- rockchip,pins =
- /* spi1_cs0_m0 */
- <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m0_cs1: spi1m0-cs1 {
- rockchip,pins =
- /* spi1_cs1_m0 */
- <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- spi3 {
- /omit-if-no-ref/
- spi3m0_pins: spi3m0-pins {
- rockchip,pins =
- /* spi3_clk_m0 */
- <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
- /* spi3_miso_m0 */
- <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
- /* spi3_mosi_m0 */
- <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m0_cs0: spi3m0-cs0 {
- rockchip,pins =
- /* spi3_cs0_m0 */
- <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m0_cs1: spi3m0-cs1 {
- rockchip,pins =
- /* spi3_cs1_m0 */
- <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- uart1 {
- /omit-if-no-ref/
- uart1m0_xfer: uart1m0-xfer {
- rockchip,pins =
- /* uart1_rx_m0 */
- <2 RK_PB6 10 &pcfg_pull_up>,
- /* uart1_tx_m0 */
- <2 RK_PB7 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart1m0_ctsn: uart1m0-ctsn {
- rockchip,pins =
- /* uart1m0_ctsn */
- <2 RK_PC1 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart1m0_rtsn: uart1m0-rtsn {
- rockchip,pins =
- /* uart1m0_rtsn */
- <2 RK_PC0 10 &pcfg_pull_none>;
- };
- };
-
- uart6 {
- /omit-if-no-ref/
- uart6m0_xfer: uart6m0-xfer {
- rockchip,pins =
- /* uart6_rx_m0 */
- <2 RK_PA6 10 &pcfg_pull_up>,
- /* uart6_tx_m0 */
- <2 RK_PA7 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart6m0_ctsn: uart6m0-ctsn {
- rockchip,pins =
- /* uart6m0_ctsn */
- <2 RK_PB1 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart6m0_rtsn: uart6m0-rtsn {
- rockchip,pins =
- /* uart6m0_rtsn */
- <2 RK_PB0 10 &pcfg_pull_none>;
- };
- };
-
- uart7 {
- /omit-if-no-ref/
- uart7m0_xfer: uart7m0-xfer {
- rockchip,pins =
- /* uart7_rx_m0 */
- <2 RK_PB4 10 &pcfg_pull_up>,
- /* uart7_tx_m0 */
- <2 RK_PB5 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart7m0_ctsn: uart7m0-ctsn {
- rockchip,pins =
- /* uart7m0_ctsn */
- <4 RK_PC6 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart7m0_rtsn: uart7m0-rtsn {
- rockchip,pins =
- /* uart7m0_rtsn */
- <4 RK_PC2 10 &pcfg_pull_none>;
- };
- };
-
- uart9 {
- /omit-if-no-ref/
- uart9m0_xfer: uart9m0-xfer {
- rockchip,pins =
- /* uart9_rx_m0 */
- <2 RK_PC4 10 &pcfg_pull_up>,
- /* uart9_tx_m0 */
- <2 RK_PC2 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart9m0_ctsn: uart9m0-ctsn {
- rockchip,pins =
- /* uart9m0_ctsn */
- <4 RK_PC5 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart9m0_rtsn: uart9m0-rtsn {
- rockchip,pins =
- /* uart9m0_rtsn */
- <4 RK_PC4 10 &pcfg_pull_none>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2023 Ondřej Jirman <megi@xff.cz>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/usb/pd.h>
-#include "rk3588.dtsi"
-
-/ {
- model = "PINE64 QuartzPro64";
- compatible = "pine64,quartzpro64", "rockchip,rk3588";
-
- aliases {
- ethernet0 = &gmac0;
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- adc-keys-0 {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- button-maskrom {
- label = "Mask Rom";
- linux,code = <KEY_SETUP>;
- press-threshold-microvolt = <393>;
- };
- };
-
- adc-keys-1 {
- compatible = "adc-keys";
- io-channels = <&saradc 1>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- button-volume-up {
- label = "V+/REC";
- linux,code = <KEY_VOLUMEUP>;
- press-threshold-microvolt = <17821>;
- };
-
- button-volume-down {
- label = "V-";
- linux,code = <KEY_VOLUMEDOWN>;
- press-threshold-microvolt = <415384>;
- };
-
- button-menu {
- label = "MENU";
- linux,code = <KEY_MENU>;
- press-threshold-microvolt = <890909>;
- };
-
- button-esc {
- label = "ESC";
- linux,code = <KEY_ESC>;
- press-threshold-microvolt = <1233962>;
- };
- };
-
- headphone_amp: audio-amplifier-headphone {
- compatible = "simple-audio-amplifier";
- enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
- sound-name-prefix = "Headphones Amp";
- };
-
- speaker_amp: audio-amplifier-speaker {
- compatible = "simple-audio-amplifier";
- enable-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
- sound-name-prefix = "Speaker Amp";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins>;
-
- led-1 {
- color = <LED_COLOR_ID_ORANGE>;
- function = LED_FUNCTION_INDICATOR;
- gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
- };
- };
-
- sound {
- compatible = "simple-audio-card";
- pinctrl-names = "default";
- pinctrl-0 = <&hp_detect>;
- simple-audio-card,name = "Analog";
- simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>;
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
- simple-audio-card,bitclock-master = <&daicpu>;
- simple-audio-card,frame-master = <&daicpu>;
- /* SARADC_IN3 is used as MIC detection / key input */
-
- simple-audio-card,widgets =
- "Microphone", "Onboard Microphone",
- "Microphone", "Microphone Jack",
- "Speaker", "Speaker",
- "Headphone", "Headphones";
-
- simple-audio-card,routing =
- "Headphones", "LOUT1",
- "Headphones", "ROUT1",
- "Speaker", "LOUT2",
- "Speaker", "ROUT2",
-
- "Headphones", "Headphones Amp OUTL",
- "Headphones", "Headphones Amp OUTR",
- "Headphones Amp INL", "LOUT1",
- "Headphones Amp INR", "ROUT1",
-
- "Speaker", "Speaker Amp OUTL",
- "Speaker", "Speaker Amp OUTR",
- "Speaker Amp INL", "LOUT2",
- "Speaker Amp INR", "ROUT2",
-
- /* single ended signal to LINPUT1 */
- "LINPUT1", "Microphone Jack",
- "RINPUT1", "Microphone Jack",
- /* differential signal */
- "LINPUT2", "Onboard Microphone",
- "RINPUT2", "Onboard Microphone";
-
- daicpu: simple-audio-card,cpu {
- sound-dai = <&i2s0_8ch>;
- system-clock-frequency = <12288000>;
- };
-
- daicodec: simple-audio-card,codec {
- sound-dai = <&es8388>;
- system-clock-frequency = <12288000>;
- };
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc3v3_bt: vcc3v3-bt-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc3v3_bt";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <50000>;
- vin-supply = <&vcc_3v3_s0>;
- };
-
- vcc3v3_pcie30: vcc3v3-pcie30-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc3v3_pcie30";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <5000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc3v3_wf: vcc3v3-wf-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc3v3_wf";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <50000>;
- vin-supply = <&vcc_3v3_s0>;
- };
-
- vcc4v0_sys: vcc4v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc4v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <4000000>;
- regulator-max-microvolt = <4000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_usb: vcc5v0-usb-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&combphy1_ps {
- status = "okay";
-};
-
-&combphy2_psu {
- status = "okay";
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_b3 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&gmac0 {
- clock_in_out = "output";
- phy-handle = <&rgmii_phy>;
- phy-mode = "rgmii-rxid";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac0_miim
- &gmac0_tx_bus2
- &gmac0_rx_bus2
- &gmac0_rgmii_clk
- &gmac0_rgmii_bus>;
- rx_delay = <0x00>;
- tx_delay = <0x43>;
- status = "okay";
-};
-
-&i2c2 {
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-output-names = "hym8563";
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- wakeup-source;
- };
-};
-
-&i2c7 {
- status = "okay";
-
- es8388: audio-codec@11 {
- compatible = "everest,es8388";
- reg = <0x11>;
- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
- clocks = <&cru I2S0_8CH_MCLKOUT>;
- clock-names = "mclk";
- AVDD-supply = <&avcc_1v8_codec_s0>;
- DVDD-supply = <&avcc_1v8_codec_s0>;
- HPVDD-supply = <&vcc_3v3_s0>;
- PVDD-supply = <&vcc_3v3_s0>;
- #sound-dai-cells = <0>;
- };
-};
-
-&i2s0_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_lrck
- &i2s0_mclk
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdo0>;
- status = "okay";
-};
-
-&mdio0 {
- rgmii_phy: ethernet-phy@1 {
- /* RTL8211F */
- compatible = "ethernet-phy-id001c.c916";
- reg = <0x1>;
- pinctrl-names = "default";
- pinctrl-0 = <&rtl8211f_rst>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
- };
-};
-
-&pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- leds {
- led_pins: led-pins {
- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- rtl8111 {
- rtl8111_isolate: rtl8111-isolate {
- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- rtl8211f {
- rtl8211f_rst: rtl8211f-rst {
- rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- };
-
- sound {
- hp_detect: hp-detect {
- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-/* WIFI */
-&pcie2x1l0 {
- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_wf>;
- status = "okay";
-};
-
-/* GMAC1 */
-&pcie2x1l1 {
- pinctrl-names = "default";
- pinctrl-0 = <&rtl8111_isolate>;
- reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&pcie30phy {
- status = "okay";
-};
-
-&pcie3x4 {
- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie30>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8_s0>;
- status = "okay";
-};
-
-&sata0 {
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- max-frequency = <150000000>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- no-sdio;
- no-mmc;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
-&spi2 {
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <2>;
- status = "okay";
-
- pmic@0 {
- compatible = "rockchip,rk806";
- reg = <0x0>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
- pinctrl-names = "default";
- spi-max-frequency = <1000000>;
-
- vcc1-supply = <&vcc4v0_sys>;
- vcc2-supply = <&vcc4v0_sys>;
- vcc3-supply = <&vcc4v0_sys>;
- vcc4-supply = <&vcc4v0_sys>;
- vcc5-supply = <&vcc4v0_sys>;
- vcc6-supply = <&vcc4v0_sys>;
- vcc7-supply = <&vcc4v0_sys>;
- vcc8-supply = <&vcc4v0_sys>;
- vcc9-supply = <&vcc4v0_sys>;
- vcc10-supply = <&vcc4v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc4v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc4v0_sys>;
-
- rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl1";
- function = "pin_fun0";
- };
-
- rk806_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- regulators {
- vdd_gpu_s0: dcdc-reg1 {
- regulator-name = "vdd_gpu_s0";
- regulator-boot-on;
- regulator-enable-ramp-delay = <400>;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_npu_s0: dcdc-reg2 {
- regulator-name = "vdd_npu_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: dcdc-reg3 {
- regulator-name = "vdd_log_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: dcdc-reg4 {
- regulator-name = "vdd_vdenc_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
-
- };
-
- vdd_gpu_mem_s0: dcdc-reg5 {
- regulator-name = "vdd_gpu_mem_s0";
- regulator-boot-on;
- regulator-enable-ramp-delay = <400>;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
-
- };
-
- vdd_npu_mem_s0: dcdc-reg6 {
- regulator-name = "vdd_npu_mem_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
-
- };
-
- vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-name = "vdd_2v0_pldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vdd_vdenc_mem_s0: dcdc-reg8 {
- regulator-name = "vdd_vdenc_mem_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd2_ddr_s3: dcdc-reg9 {
- regulator-name = "vdd2_ddr_s3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v1_nldo_s3: dcdc-reg10 {
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1100000>;
- };
- };
-
- avcc_1v8_s0: pldo-reg1 {
- regulator-name = "avcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd1_1v8_ddr_s3: pldo-reg2 {
- regulator-name = "vdd1_1v8_ddr_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_codec_s0: pldo-reg3 {
- regulator-name = "avcc_1v8_codec_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s3: pldo-reg4 {
- regulator-name = "vcc_3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vccio_sd_s0: pldo-reg5 {
- regulator-name = "vccio_sd_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s3: pldo-reg6 {
- regulator-name = "vcc_1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: nldo-reg1 {
- regulator-name = "vdd_0v75_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- /* reserved for LPDDR5, unused? */
- vdd2l_0v9_ddr_s3: nldo-reg2 {
- regulator-name = "vdd2l_0v9_ddr_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vdd_0v75_hdmi_edp_s0: nldo-reg3 {
- regulator-name = "vdd_0v75_hdmi_edp_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_0v75_s0: nldo-reg4 {
- regulator-name = "avdd_0v75_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: nldo-reg5 {
- regulator-name = "vdd_0v85_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- pmic@1 {
- compatible = "rockchip,rk806";
- reg = <0x01>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>,
- <&rk806_slave_dvs3_null>;
- pinctrl-names = "default";
- spi-max-frequency = <1000000>;
-
- vcc1-supply = <&vcc4v0_sys>;
- vcc2-supply = <&vcc4v0_sys>;
- vcc3-supply = <&vcc4v0_sys>;
- vcc4-supply = <&vcc4v0_sys>;
- vcc5-supply = <&vcc4v0_sys>;
- vcc6-supply = <&vcc4v0_sys>;
- vcc7-supply = <&vcc4v0_sys>;
- vcc8-supply = <&vcc4v0_sys>;
- vcc9-supply = <&vcc4v0_sys>;
- vcc10-supply = <&vcc4v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc4v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_2v0_pldo_s3>;
- vcca-supply = <&vcc4v0_sys>;
-
- rk806_slave_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl1";
- function = "pin_fun0";
- };
-
- rk806_slave_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_slave_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- regulators {
- vdd_cpu_big1_s0: dcdc-reg1 {
- regulator-name = "vdd_cpu_big1_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big0_s0: dcdc-reg2 {
- regulator-name = "vdd_cpu_big0_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: dcdc-reg3 {
- regulator-name = "vdd_cpu_lit_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: dcdc-reg4 {
- regulator-name = "vcc_3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big1_mem_s0: dcdc-reg5 {
- regulator-name = "vdd_cpu_big1_mem_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
-
- vdd_cpu_big0_mem_s0: dcdc-reg6 {
- regulator-name = "vdd_cpu_big0_mem_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: dcdc-reg7 {
- regulator-name = "vcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_mem_s0: dcdc-reg8 {
- regulator-name = "vdd_cpu_lit_mem_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vddq_ddr_s0: dcdc-reg9 {
- regulator-name = "vddq_ddr_s0";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: dcdc-reg10 {
- regulator-name = "vdd_ddr_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- /* reserved, unused? */
- vcc_1v8_cam_s0: pldo-reg1 {
- regulator-name = "vcc_1v8_cam_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd1v8_ddr_pll_s0: pldo-reg2 {
- regulator-name = "avdd1v8_ddr_pll_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_1v8_pll_s0: pldo-reg3 {
- regulator-name = "vdd_1v8_pll_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- /* reserved, unused? */
- vcc_3v3_sd_s0: pldo-reg4 {
- regulator-name = "vcc_3v3_sd_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- /* reserved, unused? */
- vcc_2v8_cam_s0: pldo-reg5 {
- regulator-name = "vcc_2v8_cam_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- /* unused */
- pldo6_s3: pldo-reg6 {
- regulator-name = "pldo6_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_pll_s0: nldo-reg1 {
- regulator-name = "vdd_0v75_pll_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_pll_s0: nldo-reg2 {
- regulator-name = "vdd_ddr_pll_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_0v85_s0: nldo-reg3 {
- regulator-name = "avdd_0v85_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- /* reserved, unused */
- avdd_1v2_cam_s0: nldo-reg4 {
- regulator-name = "avdd_1v2_cam_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- avdd_1v2_s0: nldo-reg5 {
- regulator-name = "avdd_1v2_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy2_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
*/
#include "rk3588-u-boot.dtsi"
-#include <dt-bindings/usb/pd.h>
-
-/ {
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-};
&fspim2_pins {
bootph-pre-ram;
bootph-some-ram;
};
-&pinctrl {
- usb {
- usbc0_int: usbc0-int {
- rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
&sdhci {
cap-mmc-highspeed;
mmc-hs200-1_8v;
status = "okay";
};
-&usbdp_phy1_u3 {
- status = "okay";
-};
-
&usbdp_phy0 {
- orientation-switch;
- mode-switch;
- sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
- sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usbdp_phy0_typec_ss: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&usbc0_ss>;
- };
-
- usbdp_phy0_typec_sbu: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&usbc0_sbu>;
- };
- };
-};
-
-&usbdp_phy0_u3 {
status = "okay";
};
&usb_host0_xhci {
- usb-role-switch;
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
status = "okay";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb_host0_xhci_drd_sw: endpoint {
- remote-endpoint = <&usbc0_hs>;
- };
- };
};
&usb_host1_xhci {
+ dr_mode = "host";
status = "okay";
};
-
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4m1_xfer>;
- status = "okay";
-
- usbc0: usb-typec@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio3>;
- interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&usbc0_int>;
- vbus-supply = <&vcc12v_dcin>;
- status = "okay";
-
- usb_con: connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- data-role = "dual";
- power-role = "sink";
- try-power-role = "sink";
- op-sink-microwatt = <1000000>;
- sink-pdos =
- <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>,
- <PDO_VAR(5000, 20000, 5000)>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usbc0_hs: endpoint {
- remote-endpoint = <&usb_host0_xhci_drd_sw>;
- };
- };
-
- port@1 {
- reg = <1>;
- usbc0_ss: endpoint {
- remote-endpoint = <&usbdp_phy0_typec_ss>;
- };
- };
-
- port@2 {
- reg = <2>;
- usbc0_sbu: endpoint {
- remote-endpoint = <&usbdp_phy0_typec_sbu>;
- };
- };
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include "rk3588.dtsi"
-
-/ {
- model = "Radxa ROCK 5 Model B";
- compatible = "radxa,rock-5b", "rockchip,rk3588";
-
- aliases {
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
- mmc2 = &sdio;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- analog-sound {
- compatible = "audio-graph-card";
- label = "rk3588-es8316";
-
- widgets = "Microphone", "Mic Jack",
- "Headphone", "Headphones";
-
- routing = "MIC2", "Mic Jack",
- "Headphones", "HPOL",
- "Headphones", "HPOR";
-
- dais = <&i2s0_8ch_p0>;
- hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&hp_detect>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_rgb_b>;
-
- led_rgb_b {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- fan: pwm-fan {
- compatible = "pwm-fan";
- cooling-levels = <0 95 145 195 255>;
- fan-supply = <&vcc5v0_sys>;
- pwms = <&pwm1 0 50000 0>;
- #cooling-cells = <2>;
- };
-
- vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_0_vcc3v3_en>;
- regulator-name = "vcc3v3_pcie2x1l0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <50000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie2x1l2";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <5000>;
- vin-supply = <&vcc_3v3_s3>;
- };
-
- vcc3v3_pcie30: vcc3v3-pcie30-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie3_vcc3v3_en>;
- regulator-name = "vcc3v3_pcie30";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <5000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&combphy1_ps {
- status = "okay";
-};
-
-&combphy2_psu {
- status = "okay";
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_b3 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
- status = "okay";
-
- vdd_cpu_big0_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big0_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big1_s0: regulator@43 {
- compatible = "rockchip,rk8603", "rockchip,rk8602";
- reg = <0x43>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big1_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c6 {
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
- wakeup-source;
- };
-};
-
-&i2c7 {
- status = "okay";
-
- es8316: audio-codec@11 {
- compatible = "everest,es8316";
- reg = <0x11>;
- clocks = <&cru I2S0_8CH_MCLKOUT>;
- clock-names = "mclk";
- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
- #sound-dai-cells = <0>;
-
- port {
- es8316_p0_0: endpoint {
- remote-endpoint = <&i2s0_8ch_p0_0>;
- };
- };
- };
-};
-
-&i2s0_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_lrck
- &i2s0_mclk
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdo0>;
- status = "okay";
-
- i2s0_8ch_p0: port {
- i2s0_8ch_p0_0: endpoint {
- dai-format = "i2s";
- mclk-fs = <256>;
- remote-endpoint = <&es8316_p0_0>;
- };
- };
-};
-
-&pcie2x1l0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_0_rst>;
- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
- status = "okay";
-};
-
-&pcie2x1l2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_2_rst>;
- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
- status = "okay";
-};
-
-&pcie30phy {
- status = "okay";
-};
-
-&pcie3x4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie3_rst>;
- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie30>;
- status = "okay";
-};
-
-&pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- leds {
- led_rgb_b: led-rgb-b {
- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sound {
- hp_detect: hp-detect {
- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie2 {
- pcie2_0_rst: pcie2-0-rst {
- rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie2_2_rst: pcie2-2-rst {
- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie3 {
- pcie3_rst: pcie3-rst {
- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pcie3_vcc3v3_en: pcie3-vcc3v3-en {
- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&avcc_1v8_s0>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
-};
-
-&sdmmc {
- max-frequency = <200000000>;
- no-sdio;
- no-mmc;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
-&sdio {
- max-frequency = <200000000>;
- no-sd;
- no-mmc;
- non-removable;
- bus-width = <4>;
- cap-sdio-irq;
- disable-wp;
- keep-power-in-suspend;
- wakeup-source;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_pcie2x1l0>;
- vqmmc-supply = <&vcc_1v8_s3>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdiom0_pins>;
- status = "okay";
-};
-
-&uart6 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>;
- status = "okay";
-};
-
-&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- num-cs = <1>;
-
- pmic@0 {
- compatible = "rockchip,rk806";
- spi-max-frequency = <1000000>;
- reg = <0x0>;
-
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-
- system-power-controller;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl1";
- function = "pin_fun0";
- };
-
- rk806_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- regulators {
- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_gpu_s0";
- regulator-enable-ramp-delay = <400>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_lit_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: dcdc-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_log_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_vdenc_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: dcdc-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_ddr_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- vdd2_ddr_s3: dcdc-reg6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vdd2_ddr_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_2v0_pldo_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vcc_3v3_s3: dcdc-reg8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_3v3_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vddq_ddr_s0: dcdc-reg9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vddq_ddr_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s3: dcdc-reg10 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_s0: pldo-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "avcc_1v8_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: pldo-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avdd_1v2_s0: pldo-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-name = "avdd_1v2_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: pldo-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd_s0: pldo-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vccio_sd_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: pldo-reg6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "pldo6_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: nldo-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_ddr_pll_s0: nldo-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_ddr_pll_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- avdd_0v75_s0: nldo-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "avdd_0v75_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: nldo-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_0v85_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v75_s0: nldo-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy2_host {
- /* connected to USB hub, which is powered by vcc5v0_sys */
- phy-supply = <&vcc5v0_sys>;
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usb_host2_xhci {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * This device tree covers the common case where the RK1 is used as a
- * "compute node" system, where the carrier board is functioning more like a
- * generic backplane (with no non-autoenumerable peripherals of its own) than
- * like a device that the SoM is meant to enable.
- *
- * Copyright (c) 2023 Sam Edwards <CFSworks@gmail.com>
- */
-
-/dts-v1/;
-#include "rk3588-turing-rk1.dtsi"
-
-/ {
- model = "Turing Machines RK1";
- compatible = "turing,rk1", "rockchip,rk3588";
-
- chosen {
- stdout-path = "serial9:115200n8";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device tree definitions for the Turing RK1 SoM.
- *
- * Copyright (c) 2023 Sam Edwards <CFSworks@gmail.com>
- *
- * Based on RK3588-EVB1 devicetree
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3588.dtsi"
-
-/ {
- compatible = "turing,rk1", "rockchip,rk3588";
-
- aliases {
- ethernet0 = &gmac1;
- mmc0 = &sdhci;
- };
-
- fan: pwm-fan {
- compatible = "pwm-fan";
- cooling-levels = <0 25 95 145 195 255>;
- fan-supply = <&vcc5v0_sys>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0m2_pins &fan_int>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
- pwms = <&pwm0 0 50000 0>;
- #cooling-cells = <2>;
- };
-
- vcc3v3_pcie30: vcc3v3-pcie30-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie30";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc3v3_pcie30_en>;
- startup-delay-us = <5000>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&combphy2_psu {
- status = "okay";
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_b3 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&gmac1 {
- clock_in_out = "output";
- phy-handle = <&rgmii_phy>;
- phy-mode = "rgmii-rxid";
- pinctrl-0 = <&gmac1_miim
- &gmac1_tx_bus2
- &gmac1_rx_bus2
- &gmac1_rgmii_clk
- &gmac1_rgmii_bus>;
- pinctrl-names = "default";
- rx_delay = <0x00>;
- tx_delay = <0x43>;
- status = "okay";
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
- status = "okay";
-
- vdd_cpu_big0_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big0_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big1_s0: regulator@43 {
- compatible = "rockchip,rk8603", "rockchip,rk8602";
- reg = <0x43>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big1_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1m2_xfer>;
- status = "okay";
-
- vdd_npu_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_npu_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c6 {
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
- wakeup-source;
- };
-};
-
-&mdio1 {
- rgmii_phy: ethernet-phy@1 {
- /* RTL8211F */
- compatible = "ethernet-phy-id001c.c916",
- "ethernet-phy-ieee802.3-c22";
- reg = <0x1>;
- pinctrl-names = "default";
- pinctrl-0 = <&rtl8211f_rst>;
- reset-assert-us = <15000>;
- reset-deassert-us = <50000>;
- reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- };
-};
-
-&pcie2x1l1 {
- linux,pci-domain = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_reset>;
- reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&pcie30phy {
- status = "okay";
-};
-
-&pcie3x4 {
- linux,pci-domain = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie3_reset>;
- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie30>;
- status = "okay";
-};
-
-&pinctrl {
- fan {
- fan_int: fan-int {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- pcie2 {
- pcie2_reset: pcie2-reset {
- rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pcie3 {
- pcie3_reset: pcie3-reset {
- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc3v3_pcie30_en: pcie3-reg {
- rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- rtl8211f {
- rtl8211f_rst: rtl8211f-rst {
- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
-};
-
-&spi2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- num-cs = <1>;
-
- pmic@0 {
- compatible = "rockchip,rk806";
- spi-max-frequency = <1000000>;
- reg = <0x0>;
-
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- regulators {
- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_gpu_s0";
- regulator-enable-ramp-delay = <400>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_lit_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: dcdc-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_log_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_vdenc_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: dcdc-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_ddr_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- vdd2_ddr_s3: dcdc-reg6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vdd2_ddr_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_2v0_pldo_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vcc_3v3_s3: dcdc-reg8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_3v3_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vddq_ddr_s0: dcdc-reg9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vddq_ddr_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s3: dcdc-reg10 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_s0: pldo-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "avcc_1v8_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: pldo-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avdd_1v2_s0: pldo-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-name = "avdd_1v2_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: pldo-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd_s0: pldo-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vccio_sd_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: pldo-reg6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "pldo6_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: nldo-reg1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_s3";
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_ddr_pll_s0: nldo-reg2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_ddr_pll_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- avdd_0v75_s0: nldo-reg3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "avdd_0v75_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: nldo-reg4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-name = "vdd_0v85_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v75_s0: nldo-reg5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_s0";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
-&uart9 {
- pinctrl-0 = <&uart9m0_xfer>;
- status = "okay";
-};
clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
<&cru ACLK_USB3OTG1>;
clock-names = "ref_clk", "suspend_clk", "bus_clk";
- dr_mode = "host";
- phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
+ dr_mode = "otg";
+ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
power-domains = <&power RK3588_PD_USB>;
};
usb2phy1_grf: syscon@fd5d4000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
- "simple-mfd";
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5d4000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
- u2phy1: usb2-phy@4000 {
+ u2phy1: usb2phy@4000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x4000 0x10>;
- interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy1";
- #clock-cells = <0>;
+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy1_otg: otg-port {
usbdp_phy1: phy@fed90000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed90000 0x0 0x10000>;
- rockchip,u2phy-grf = <&usb2phy1_grf>;
- rockchip,usb-grf = <&usb_grf>;
- rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
- rockchip,vo-grf = <&vo0_grf>;
+ #phy-cells = <1>;
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
<&cru CLK_USBDP_PHY1_IMMORTAL>,
<&cru PCLK_USBDPPHY1>,
<&cru SRST_USBDP_COMBO_PHY1_PCS>,
<&cru SRST_P_USBDPPHY1>;
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy1_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
status = "disabled";
-
- usbdp_phy1_dp: dp-port {
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usbdp_phy1_u3: usb3-port {
- #phy-cells = <0>;
- status = "disabled";
- };
};
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include "rk3588s.dtsi"
-#include "rk3588-pinctrl.dtsi"
-
-/ {
- pcie30_phy_grf: syscon@fd5b8000 {
- compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
- reg = <0x0 0xfd5b8000 0x0 0x10000>;
- };
-
- pipe_phy1_grf: syscon@fd5c0000 {
- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
- reg = <0x0 0xfd5c0000 0x0 0x100>;
- };
-
- i2s8_8ch: i2s@fddc8000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddc8000 0x0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 22>;
- dma-names = "tx";
- power-domains = <&power RK3588_PD_VO0>;
- resets = <&cru SRST_M_I2S8_8CH_TX>;
- reset-names = "tx-m";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s6_8ch: i2s@fddf4000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddf4000 0x0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 4>;
- dma-names = "tx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_I2S6_8CH_TX>;
- reset-names = "tx-m";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s7_8ch: i2s@fddf8000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddf8000 0x0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 21>;
- dma-names = "rx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_I2S7_8CH_RX>;
- reset-names = "rx-m";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s10_8ch: i2s@fde00000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfde00000 0x0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 24>;
- dma-names = "rx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_I2S10_8CH_RX>;
- reset-names = "rx-m";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- pcie3x4: pcie@fe150000 {
- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0x0f>;
- clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
- <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
- <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux", "pipe";
- device_type = "pci";
- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
- <0 0 0 2 &pcie3x4_intc 1>,
- <0 0 0 3 &pcie3x4_intc 2>,
- <0 0 0 4 &pcie3x4_intc 3>;
- linux,pci-domain = <0>;
- max-link-speed = <3>;
- msi-map = <0x0000 &its1 0x0000 0x1000>;
- num-lanes = <4>;
- phys = <&pcie30phy>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3588_PD_PCIE>;
- ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
- <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
- reg = <0xa 0x40000000 0x0 0x00400000>,
- <0x0 0xfe150000 0x0 0x00010000>,
- <0x0 0xf0000000 0x0 0x00100000>;
- reg-names = "dbi", "apb", "config";
- resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
- reset-names = "pwr", "pipe";
- status = "disabled";
-
- pcie3x4_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
- };
- };
-
- pcie3x2: pcie@fe160000 {
- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x10 0x1f>;
- clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
- <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
- <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux", "pipe";
- device_type = "pci";
- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
- <0 0 0 2 &pcie3x2_intc 1>,
- <0 0 0 3 &pcie3x2_intc 2>,
- <0 0 0 4 &pcie3x2_intc 3>;
- linux,pci-domain = <1>;
- max-link-speed = <3>;
- msi-map = <0x1000 &its1 0x1000 0x1000>;
- num-lanes = <2>;
- phys = <&pcie30phy>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3588_PD_PCIE>;
- ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
- <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
- reg = <0xa 0x40400000 0x0 0x00400000>,
- <0x0 0xfe160000 0x0 0x00010000>,
- <0x0 0xf1000000 0x0 0x00100000>;
- reg-names = "dbi", "apb", "config";
- resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
- reset-names = "pwr", "pipe";
- status = "disabled";
-
- pcie3x2_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
- };
- };
-
- pcie2x1l0: pcie@fe170000 {
- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
- bus-range = <0x20 0x2f>;
- clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
- <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
- <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux", "pipe";
- device_type = "pci";
- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
- <0 0 0 2 &pcie2x1l0_intc 1>,
- <0 0 0 3 &pcie2x1l0_intc 2>,
- <0 0 0 4 &pcie2x1l0_intc 3>;
- linux,pci-domain = <2>;
- max-link-speed = <2>;
- msi-map = <0x2000 &its0 0x2000 0x1000>;
- num-lanes = <1>;
- phys = <&combphy1_ps PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3588_PD_PCIE>;
- ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
- <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
- reg = <0xa 0x40800000 0x0 0x00400000>,
- <0x0 0xfe170000 0x0 0x00010000>,
- <0x0 0xf2000000 0x0 0x00100000>;
- reg-names = "dbi", "apb", "config";
- resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
- reset-names = "pwr", "pipe";
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie2x1l0_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
- };
- };
-
- gmac0: ethernet@fe1b0000 {
- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
- reg = <0x0 0xfe1b0000 0x0 0x10000>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "macirq", "eth_wake_irq";
- clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
- <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
- <&cru CLK_GMAC0_PTP_REF>;
- clock-names = "stmmaceth", "clk_mac_ref",
- "pclk_mac", "aclk_mac",
- "ptp_ref";
- power-domains = <&power RK3588_PD_GMAC>;
- resets = <&cru SRST_A_GMAC0>;
- reset-names = "stmmaceth";
- rockchip,grf = <&sys_grf>;
- rockchip,php-grf = <&php_grf>;
- snps,axi-config = <&gmac0_stmmac_axi_setup>;
- snps,mixed-burst;
- snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
- snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
- snps,tso;
- status = "disabled";
-
- mdio0: mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- };
-
- gmac0_stmmac_axi_setup: stmmac-axi-config {
- snps,blen = <0 0 0 0 16 8 4>;
- snps,wr_osr_lmt = <4>;
- snps,rd_osr_lmt = <8>;
- };
-
- gmac0_mtl_rx_setup: rx-queues-config {
- snps,rx-queues-to-use = <2>;
- queue0 {};
- queue1 {};
- };
-
- gmac0_mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <2>;
- queue0 {};
- queue1 {};
- };
- };
-
- sata1: sata@fe220000 {
- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
- reg = <0 0xfe220000 0 0x1000>;
- interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
- <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
- <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
- clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
- ports-implemented = <0x1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- sata-port@0 {
- reg = <0>;
- hba-port-cap = <HBA_PORT_FBSCP>;
- phys = <&combphy1_ps PHY_TYPE_SATA>;
- phy-names = "sata-phy";
- snps,rx-ts-max = <32>;
- snps,tx-ts-max = <32>;
- };
- };
-
- combphy1_ps: phy@fee10000 {
- compatible = "rockchip,rk3588-naneng-combphy";
- reg = <0x0 0xfee10000 0x0 0x100>;
- clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
- <&cru PCLK_PHP_ROOT>;
- clock-names = "ref", "apb", "pipe";
- assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
- assigned-clock-rates = <100000000>;
- #phy-cells = <1>;
- resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
- reset-names = "phy", "apb";
- rockchip,pipe-grf = <&php_grf>;
- rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
- status = "disabled";
- };
-
- pcie30phy: phy@fee80000 {
- compatible = "rockchip,rk3588-pcie3-phy";
- reg = <0x0 0xfee80000 0x0 0x20000>;
- #phy-cells = <0>;
- clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
- clock-names = "pclk";
- resets = <&cru SRST_PCIE30_PHY>;
- reset-names = "phy";
- rockchip,pipe-grf = <&php_grf>;
- rockchip,phy-grf = <&pcie30_phy_grf>;
- status = "disabled";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
- *
- */
-
-#include "rk3588.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
- *
- * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
- *
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3588s.dtsi"
-
-/ {
- model = "RK3588S CoolPi 4 Model B";
- compatible = "coolpi,pi-4b", "rockchip,rk3588s";
-
- aliases {
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
- mmc2 = &sdio;
- };
-
- analog-sound {
- compatible = "audio-graph-card";
- dais = <&i2s0_8ch_p0>;
- label = "rk3588-es8316";
- routing = "MIC2", "Mic Jack",
- "Headphones", "HPOL",
- "Headphones", "HPOR";
- widgets = "Microphone", "Mic Jack",
- "Headphone", "Headphones";
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- leds: leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_leds>;
-
- led0: led-green {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
-
- led1: led-red {
- color = <LED_COLOR_ID_RED>;
- default-state = "off";
- function = LED_FUNCTION_WLAN;
- gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tx";
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&hym8563>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- /*
- * On the module itself this is one of these (depending
- * on the actual card populated):
- * - SDIO_RESET_L_WL_REG_ON
- * - PDN (power down when low)
- */
- post-power-on-delay-ms = <200>;
- reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usbdcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc5v0_usb: vcc5v0-usb-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usbdcin>;
- };
-
- avdd0v85_pcie20: avdd0v85-pcie20-regulator {
- compatible = "regulator-fixed";
- regulator-name = "avdd0v85_pcie20";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- vin-supply = <&vdd_0v85_s0>;
- };
-
- avdd1v8_pcie20: avdd1v8-pcie20-regulator {
- compatible = "regulator-fixed";
- regulator-name = "avdd1v8_pcie20";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&avcc_1v8_s0>;
- };
-
- vcc3v3_mipi: vcc3v3-mipi-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc3v3_mipi";
- regulator-boot-on;
- regulator-always-on;
- vin-supply = <&vcc_3v3_s3>;
- };
-
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- regulator-name = "vcc5v0_host";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_otg: vcc5v0-otg-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_u3host_en>;
- regulator-name = "vcc5v0_otg";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&combphy2_psu {
- status = "okay";
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0m2_xfer>;
- status = "okay";
-
- vdd_cpu_big0_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big0_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big1_s0: regulator@43 {
- compatible = "rockchip,rk8603", "rockchip,rk8602";
- reg = <0x43>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big1_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c2 {
- status = "okay";
-
- vdd_npu_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_npu_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c6 {
- pinctrl-0 = <&i2c6m3_xfer>;
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <0>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- };
-};
-
-&i2c7 {
- pinctrl-0 = <&i2c7m0_xfer>;
- status = "okay";
-
- es8316: audio-codec@11 {
- compatible = "everest,es8316";
- reg = <0x11>;
- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
- clocks = <&cru I2S0_8CH_MCLKOUT>;
- clock-names = "mclk";
- #sound-dai-cells = <0>;
-
- port {
- es8316_p0_0: endpoint {
- remote-endpoint = <&i2s0_8ch_p0_0>;
- };
- };
- };
-};
-
-&i2s0_8ch {
- pinctrl-0 = <&i2s0_lrck
- &i2s0_mclk
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdo0>;
- status = "okay";
-
- i2s0_8ch_p0: port {
- i2s0_8ch_p0_0: endpoint {
- dai-format = "i2s";
- mclk-fs = <256>;
- remote-endpoint = <&es8316_p0_0>;
- };
- };
-};
-
-&pcie2x1l2 {
- pinctrl-names = "default";
- pinctrl-0 = <&rtl8111_isolate>;
- reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- led {
- gpio_leds: gpio-leds {
- rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>,
- <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- rtl8111 {
- rtl8111_isolate: rtl8111-isolate {
- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>,
- <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- vcc5v0_u3host_en: vcc5v0-u3host-en {
- rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- wireless-bluetooth {
- bt_reset_gpio: bt-reset-pin {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_gpio: bt-wake-pin {
- rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_host_irq: bt-wake-host-irq {
- rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- wireless-wlan {
- wifi_host_wake_irq: wifi-host-wake-irq {
- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
- };
-
- wifi_poweren_pin: wifi-poweren-pin {
- rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pwm2 {
- pinctrl-0 = <&pwm2m1_pins>;
- status = "okay";
-};
-
-&pwm13 {
- pinctrl-names = "active";
- pinctrl-0 = <&pwm13m2_pins>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8_s0>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- no-sdio;
- no-sd;
- non-removable;
- status = "okay";
-};
-
-&sdio {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- disable-wp;
- keep-power-in-suspend;
- max-frequency = <150000000>;
- mmc-pwrseq = <&sdio_pwrseq>;
- no-sd;
- no-mmc;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdiom1_pins>,<&wifi_poweren_pin>;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- max-frequency = <150000000>;
- no-sdio;
- no-mmc;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
-&spi2 {
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- status = "okay";
-
- pmic@0 {
- compatible = "rockchip,rk806";
- reg = <0x0>;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- gpio-controller;
- #gpio-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
- spi-max-frequency = <1000000>;
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- regulators {
- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
- regulator-name = "vdd_gpu_s0";
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-enable-ramp-delay = <400>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
- regulator-name = "vdd_cpu_lit_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: dcdc-reg3 {
- regulator-name = "vdd_log_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
- regulator-name = "vdd_vdenc_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: dcdc-reg5 {
- regulator-name = "vdd_ddr_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- vdd2_ddr_s3: dcdc-reg6 {
- regulator-name = "vdd2_ddr_s3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-name = "vdd_2v0_pldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vcc_3v3_s3: dcdc-reg8 {
- regulator-name = "vcc_3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vddq_ddr_s0: dcdc-reg9 {
- regulator-name = "vddq_ddr_s0";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s3: dcdc-reg10 {
- regulator-name = "vcc_1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_s0: pldo-reg1 {
- regulator-name = "avcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: pldo-reg2 {
- regulator-name = "vcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avdd_1v2_s0: pldo-reg3 {
- regulator-name = "avdd_1v2_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: pldo-reg4 {
- regulator-name = "vcc_3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd_s0: pldo-reg5 {
- regulator-name = "vccio_sd_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: pldo-reg6 {
- regulator-name = "pldo6_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: nldo-reg1 {
- regulator-name = "vdd_0v75_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_ddr_pll_s0: nldo-reg2 {
- regulator-name = "vdd_ddr_pll_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- avdd_0v75_s0: nldo-reg3 {
- regulator-name = "avdd_0v75_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: nldo-reg4 {
- regulator-name = "vdd_0v85_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v75_s0: nldo-reg5 {
- regulator-name = "vdd_0v75_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-&u2phy2_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&u2phy3_host {
- status = "okay";
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
-/* bt */
-&uart9 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>;
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3588s.dtsi"
-
-/ {
- model = "Xunlong Orange Pi 5";
- compatible = "xunlong,orangepi-5", "rockchip,rk3588s";
-
- aliases {
- ethernet0 = &gmac1;
- mmc0 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 1>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- button-recovery {
- label = "Recovery";
- linux,code = <KEY_VENDOR>;
- press-threshold-microvolt = <1800>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&leds_gpio>;
-
- led-1 {
- gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
- label = "status_led";
- linux,default-trigger = "heartbeat";
- };
- };
-
- vbus_typec: vbus-typec-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&typec5v_pwren>;
- regulator-name = "vbus_typec";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
- compatible = "regulator-fixed";
- enable-active-low;
- gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
- regulator-name = "vcc_3v3_sd_s0";
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_3v3_s3>;
- };
-
- vcc3v3_pcie20: vcc3v3-pcie20-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc3v3_pcie20";
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- startup-delay-us = <50000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&combphy2_psu {
- status = "okay";
-};
-
-&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b1 {
- cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_b3 {
- cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&gmac1 {
- clock_in_out = "output";
- phy-handle = <&rgmii_phy1>;
- phy-mode = "rgmii-rxid";
- pinctrl-0 = <&gmac1_miim
- &gmac1_tx_bus2
- &gmac1_rx_bus2
- &gmac1_rgmii_clk
- &gmac1_rgmii_bus>;
- pinctrl-names = "default";
- tx_delay = <0x42>;
- status = "okay";
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
- status = "okay";
-
- vdd_cpu_big0_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big0_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_big1_s0: regulator@43 {
- compatible = "rockchip,rk8603", "rockchip,rk8602";
- reg = <0x43>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big1_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c2 {
- status = "okay";
-
- vdd_npu_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_npu_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c6 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6m3_xfer>;
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
- wakeup-source;
- };
-};
-
-&mdio1 {
- rgmii_phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x1>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-};
-
-&pcie2x1l2 {
- reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie20>;
- status = "okay";
-};
-
-&pinctrl {
- gpio-func {
- leds_gpio: leds-gpio {
- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb-typec {
- usbc0_int: usbc0-int {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- typec5v_pwren: typec5v-pwren {
- rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&saradc {
- vref-supply = <&avcc_1v8_s0>;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- disable-wp;
- max-frequency = <150000000>;
- no-mmc;
- no-sdio;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_sd_s0>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
-&sfc {
- pinctrl-names = "default";
- pinctrl-0 = <&fspim0_pins>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-max-frequency = <100000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <1>;
- };
-};
-
-&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
-
- pmic@0 {
- compatible = "rockchip,rk806";
- reg = <0x0>;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
- spi-max-frequency = <1000000>;
- system-power-controller;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- regulators {
- vdd_gpu_s0: dcdc-reg1 {
- regulator-name = "vdd_gpu_s0";
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-enable-ramp-delay = <400>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: dcdc-reg2 {
- regulator-name = "vdd_cpu_lit_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: dcdc-reg3 {
- regulator-name = "vdd_log_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: dcdc-reg4 {
- regulator-name = "vdd_vdenc_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: dcdc-reg5 {
- regulator-name = "vdd_ddr_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 {
- regulator-name = "vdd2_ddr_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1100000>;
- regulator-min-microvolt = <1100000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-name = "vdd_2v0_pldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vcc_3v3_s3: dcdc-reg8 {
- regulator-name = "vcc_3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vddq_ddr_s0: dcdc-reg9 {
- regulator-name = "vddq_ddr_s0";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s3: dcdc-reg10 {
- regulator-name = "vcc_1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_s0: pldo-reg1 {
- regulator-name = "avcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: pldo-reg2 {
- regulator-name = "vcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avdd_1v2_s0: pldo-reg3 {
- regulator-name = "avdd_1v2_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: pldo-reg4 {
- regulator-name = "vcc_3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd_s0: pldo-reg5 {
- regulator-name = "vccio_sd_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: pldo-reg6 {
- regulator-name = "pldo6_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: nldo-reg1 {
- regulator-name = "vdd_0v75_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_ddr_pll_s0: nldo-reg2 {
- regulator-name = "vdd_ddr_pll_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- avdd_0v75_s0: nldo-reg3 {
- regulator-name = "avdd_0v75_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: nldo-reg4 {
- regulator-name = "vdd_0v85_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v75_s0: nldo-reg5 {
- regulator-name = "vdd_0v75_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy2_host {
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-&u2phy3_host {
- status = "okay";
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usb_host2_xhci {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rockchip-pinconf.dtsi"
-
-/*
- * This file is auto generated by pin2dts tool, please keep these code
- * by adding changes at end of this file.
- */
-&pinctrl {
- auddsm {
- /omit-if-no-ref/
- auddsm_pins: auddsm-pins {
- rockchip,pins =
- /* auddsm_ln */
- <3 RK_PA1 4 &pcfg_pull_none>,
- /* auddsm_lp */
- <3 RK_PA2 4 &pcfg_pull_none>,
- /* auddsm_rn */
- <3 RK_PA3 4 &pcfg_pull_none>,
- /* auddsm_rp */
- <3 RK_PA4 4 &pcfg_pull_none>;
- };
- };
-
- bt1120 {
- /omit-if-no-ref/
- bt1120_pins: bt1120-pins {
- rockchip,pins =
- /* bt1120_clkout */
- <4 RK_PB0 2 &pcfg_pull_none>,
- /* bt1120_d0 */
- <4 RK_PA0 2 &pcfg_pull_none>,
- /* bt1120_d1 */
- <4 RK_PA1 2 &pcfg_pull_none>,
- /* bt1120_d2 */
- <4 RK_PA2 2 &pcfg_pull_none>,
- /* bt1120_d3 */
- <4 RK_PA3 2 &pcfg_pull_none>,
- /* bt1120_d4 */
- <4 RK_PA4 2 &pcfg_pull_none>,
- /* bt1120_d5 */
- <4 RK_PA5 2 &pcfg_pull_none>,
- /* bt1120_d6 */
- <4 RK_PA6 2 &pcfg_pull_none>,
- /* bt1120_d7 */
- <4 RK_PA7 2 &pcfg_pull_none>,
- /* bt1120_d8 */
- <4 RK_PB2 2 &pcfg_pull_none>,
- /* bt1120_d9 */
- <4 RK_PB3 2 &pcfg_pull_none>,
- /* bt1120_d10 */
- <4 RK_PB4 2 &pcfg_pull_none>,
- /* bt1120_d11 */
- <4 RK_PB5 2 &pcfg_pull_none>,
- /* bt1120_d12 */
- <4 RK_PB6 2 &pcfg_pull_none>,
- /* bt1120_d13 */
- <4 RK_PB7 2 &pcfg_pull_none>,
- /* bt1120_d14 */
- <4 RK_PC0 2 &pcfg_pull_none>,
- /* bt1120_d15 */
- <4 RK_PC1 2 &pcfg_pull_none>;
- };
- };
-
- can0 {
- /omit-if-no-ref/
- can0m0_pins: can0m0-pins {
- rockchip,pins =
- /* can0_rx_m0 */
- <0 RK_PC0 11 &pcfg_pull_none>,
- /* can0_tx_m0 */
- <0 RK_PB7 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- can0m1_pins: can0m1-pins {
- rockchip,pins =
- /* can0_rx_m1 */
- <4 RK_PD5 9 &pcfg_pull_none>,
- /* can0_tx_m1 */
- <4 RK_PD4 9 &pcfg_pull_none>;
- };
- };
-
- can1 {
- /omit-if-no-ref/
- can1m0_pins: can1m0-pins {
- rockchip,pins =
- /* can1_rx_m0 */
- <3 RK_PB5 9 &pcfg_pull_none>,
- /* can1_tx_m0 */
- <3 RK_PB6 9 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- can1m1_pins: can1m1-pins {
- rockchip,pins =
- /* can1_rx_m1 */
- <4 RK_PB2 12 &pcfg_pull_none>,
- /* can1_tx_m1 */
- <4 RK_PB3 12 &pcfg_pull_none>;
- };
- };
-
- can2 {
- /omit-if-no-ref/
- can2m0_pins: can2m0-pins {
- rockchip,pins =
- /* can2_rx_m0 */
- <3 RK_PC4 9 &pcfg_pull_none>,
- /* can2_tx_m0 */
- <3 RK_PC5 9 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- can2m1_pins: can2m1-pins {
- rockchip,pins =
- /* can2_rx_m1 */
- <0 RK_PD4 10 &pcfg_pull_none>,
- /* can2_tx_m1 */
- <0 RK_PD5 10 &pcfg_pull_none>;
- };
- };
-
- cif {
- /omit-if-no-ref/
- cif_clk: cif-clk {
- rockchip,pins =
- /* cif_clkout */
- <4 RK_PB4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- cif_dvp_clk: cif-dvp-clk {
- rockchip,pins =
- /* cif_clkin */
- <4 RK_PB0 1 &pcfg_pull_none>,
- /* cif_href */
- <4 RK_PB2 1 &pcfg_pull_none>,
- /* cif_vsync */
- <4 RK_PB3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- cif_dvp_bus16: cif-dvp-bus16 {
- rockchip,pins =
- /* cif_d8 */
- <3 RK_PC4 1 &pcfg_pull_none>,
- /* cif_d9 */
- <3 RK_PC5 1 &pcfg_pull_none>,
- /* cif_d10 */
- <3 RK_PC6 1 &pcfg_pull_none>,
- /* cif_d11 */
- <3 RK_PC7 1 &pcfg_pull_none>,
- /* cif_d12 */
- <3 RK_PD0 1 &pcfg_pull_none>,
- /* cif_d13 */
- <3 RK_PD1 1 &pcfg_pull_none>,
- /* cif_d14 */
- <3 RK_PD2 1 &pcfg_pull_none>,
- /* cif_d15 */
- <3 RK_PD3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- cif_dvp_bus8: cif-dvp-bus8 {
- rockchip,pins =
- /* cif_d0 */
- <4 RK_PA0 1 &pcfg_pull_none>,
- /* cif_d1 */
- <4 RK_PA1 1 &pcfg_pull_none>,
- /* cif_d2 */
- <4 RK_PA2 1 &pcfg_pull_none>,
- /* cif_d3 */
- <4 RK_PA3 1 &pcfg_pull_none>,
- /* cif_d4 */
- <4 RK_PA4 1 &pcfg_pull_none>,
- /* cif_d5 */
- <4 RK_PA5 1 &pcfg_pull_none>,
- /* cif_d6 */
- <4 RK_PA6 1 &pcfg_pull_none>,
- /* cif_d7 */
- <4 RK_PA7 1 &pcfg_pull_none>;
- };
- };
-
- clk32k {
- /omit-if-no-ref/
- clk32k_in: clk32k-in {
- rockchip,pins =
- /* clk32k_in */
- <0 RK_PB2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- clk32k_out0: clk32k-out0 {
- rockchip,pins =
- /* clk32k_out0 */
- <0 RK_PB2 2 &pcfg_pull_none>;
- };
- };
-
- cpu {
- /omit-if-no-ref/
- cpu_pins: cpu-pins {
- rockchip,pins =
- /* cpu_big0_avs */
- <0 RK_PD1 2 &pcfg_pull_none>,
- /* cpu_big1_avs */
- <0 RK_PD5 2 &pcfg_pull_none>;
- };
- };
-
- ddrphych0 {
- /omit-if-no-ref/
- ddrphych0_pins: ddrphych0-pins {
- rockchip,pins =
- /* ddrphych0_dtb0 */
- <4 RK_PA0 7 &pcfg_pull_none>,
- /* ddrphych0_dtb1 */
- <4 RK_PA1 7 &pcfg_pull_none>,
- /* ddrphych0_dtb2 */
- <4 RK_PA2 7 &pcfg_pull_none>,
- /* ddrphych0_dtb3 */
- <4 RK_PA3 7 &pcfg_pull_none>;
- };
- };
-
- ddrphych1 {
- /omit-if-no-ref/
- ddrphych1_pins: ddrphych1-pins {
- rockchip,pins =
- /* ddrphych1_dtb0 */
- <4 RK_PA4 7 &pcfg_pull_none>,
- /* ddrphych1_dtb1 */
- <4 RK_PA5 7 &pcfg_pull_none>,
- /* ddrphych1_dtb2 */
- <4 RK_PA6 7 &pcfg_pull_none>,
- /* ddrphych1_dtb3 */
- <4 RK_PA7 7 &pcfg_pull_none>;
- };
- };
-
- ddrphych2 {
- /omit-if-no-ref/
- ddrphych2_pins: ddrphych2-pins {
- rockchip,pins =
- /* ddrphych2_dtb0 */
- <4 RK_PB0 7 &pcfg_pull_none>,
- /* ddrphych2_dtb1 */
- <4 RK_PB1 7 &pcfg_pull_none>,
- /* ddrphych2_dtb2 */
- <4 RK_PB2 7 &pcfg_pull_none>,
- /* ddrphych2_dtb3 */
- <4 RK_PB3 7 &pcfg_pull_none>;
- };
- };
-
- ddrphych3 {
- /omit-if-no-ref/
- ddrphych3_pins: ddrphych3-pins {
- rockchip,pins =
- /* ddrphych3_dtb0 */
- <4 RK_PB4 7 &pcfg_pull_none>,
- /* ddrphych3_dtb1 */
- <4 RK_PB5 7 &pcfg_pull_none>,
- /* ddrphych3_dtb2 */
- <4 RK_PB6 7 &pcfg_pull_none>,
- /* ddrphych3_dtb3 */
- <4 RK_PB7 7 &pcfg_pull_none>;
- };
- };
-
- dp0 {
- /omit-if-no-ref/
- dp0m0_pins: dp0m0-pins {
- rockchip,pins =
- /* dp0_hpdin_m0 */
- <4 RK_PB4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- dp0m1_pins: dp0m1-pins {
- rockchip,pins =
- /* dp0_hpdin_m1 */
- <0 RK_PC4 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- dp0m2_pins: dp0m2-pins {
- rockchip,pins =
- /* dp0_hpdin_m2 */
- <1 RK_PA0 5 &pcfg_pull_none>;
- };
- };
-
- dp1 {
- /omit-if-no-ref/
- dp1m0_pins: dp1m0-pins {
- rockchip,pins =
- /* dp1_hpdin_m0 */
- <3 RK_PD5 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- dp1m1_pins: dp1m1-pins {
- rockchip,pins =
- /* dp1_hpdin_m1 */
- <0 RK_PC5 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- dp1m2_pins: dp1m2-pins {
- rockchip,pins =
- /* dp1_hpdin_m2 */
- <1 RK_PA1 5 &pcfg_pull_none>;
- };
- };
-
- emmc {
- /omit-if-no-ref/
- emmc_rstnout: emmc-rstnout {
- rockchip,pins =
- /* emmc_rstn */
- <2 RK_PA3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- emmc_bus8: emmc-bus8 {
- rockchip,pins =
- /* emmc_d0 */
- <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d1 */
- <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d2 */
- <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d3 */
- <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d4 */
- <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d5 */
- <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d6 */
- <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
- /* emmc_d7 */
- <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- emmc_clk: emmc-clk {
- rockchip,pins =
- /* emmc_clkout */
- <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- emmc_cmd: emmc-cmd {
- rockchip,pins =
- /* emmc_cmd */
- <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- emmc_data_strobe: emmc-data-strobe {
- rockchip,pins =
- /* emmc_data_strobe */
- <2 RK_PA2 1 &pcfg_pull_down>;
- };
- };
-
- eth1 {
- /omit-if-no-ref/
- eth1_pins: eth1-pins {
- rockchip,pins =
- /* eth1_refclko_25m */
- <3 RK_PA6 1 &pcfg_pull_none>;
- };
- };
-
- fspi {
- /omit-if-no-ref/
- fspim0_pins: fspim0-pins {
- rockchip,pins =
- /* fspi_clk_m0 */
- <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
- /* fspi_cs0n_m0 */
- <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>,
- /* fspi_d0_m0 */
- <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
- /* fspi_d1_m0 */
- <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
- /* fspi_d2_m0 */
- <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
- /* fspi_d3_m0 */
- <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- fspim0_cs1: fspim0-cs1 {
- rockchip,pins =
- /* fspi_cs1n_m0 */
- <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- fspim2_pins: fspim2-pins {
- rockchip,pins =
- /* fspi_clk_m2 */
- <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>,
- /* fspi_cs0n_m2 */
- <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
- /* fspi_d0_m2 */
- <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>,
- /* fspi_d1_m2 */
- <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
- /* fspi_d2_m2 */
- <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
- /* fspi_d3_m2 */
- <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- fspim2_cs1: fspim2-cs1 {
- rockchip,pins =
- /* fspi_cs1n_m2 */
- <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>;
- };
- };
-
- gmac1 {
- /omit-if-no-ref/
- gmac1_miim: gmac1-miim {
- rockchip,pins =
- /* gmac1_mdc */
- <3 RK_PC2 1 &pcfg_pull_none>,
- /* gmac1_mdio */
- <3 RK_PC3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_clkinout: gmac1-clkinout {
- rockchip,pins =
- /* gmac1_mclkinout */
- <3 RK_PB6 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_rx_bus2: gmac1-rx-bus2 {
- rockchip,pins =
- /* gmac1_rxd0 */
- <3 RK_PA7 1 &pcfg_pull_none>,
- /* gmac1_rxd1 */
- <3 RK_PB0 1 &pcfg_pull_none>,
- /* gmac1_rxdv_crs */
- <3 RK_PB1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_tx_bus2: gmac1-tx-bus2 {
- rockchip,pins =
- /* gmac1_txd0 */
- <3 RK_PB3 1 &pcfg_pull_none>,
- /* gmac1_txd1 */
- <3 RK_PB4 1 &pcfg_pull_none>,
- /* gmac1_txen */
- <3 RK_PB5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_rgmii_clk: gmac1-rgmii-clk {
- rockchip,pins =
- /* gmac1_rxclk */
- <3 RK_PA5 1 &pcfg_pull_none>,
- /* gmac1_txclk */
- <3 RK_PA4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_rgmii_bus: gmac1-rgmii-bus {
- rockchip,pins =
- /* gmac1_rxd2 */
- <3 RK_PA2 1 &pcfg_pull_none>,
- /* gmac1_rxd3 */
- <3 RK_PA3 1 &pcfg_pull_none>,
- /* gmac1_txd2 */
- <3 RK_PA0 1 &pcfg_pull_none>,
- /* gmac1_txd3 */
- <3 RK_PA1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_ppsclk: gmac1-ppsclk {
- rockchip,pins =
- /* gmac1_ppsclk */
- <3 RK_PC1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_ppstrig: gmac1-ppstrig {
- rockchip,pins =
- /* gmac1_ppstrig */
- <3 RK_PC0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
- rockchip,pins =
- /* gmac1_ptp_ref_clk */
- <3 RK_PB7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- gmac1_txer: gmac1-txer {
- rockchip,pins =
- /* gmac1_txer */
- <3 RK_PB2 1 &pcfg_pull_none>;
- };
- };
-
- gpu {
- /omit-if-no-ref/
- gpu_pins: gpu-pins {
- rockchip,pins =
- /* gpu_avs */
- <0 RK_PC5 2 &pcfg_pull_none>;
- };
- };
-
- hdmi {
- /omit-if-no-ref/
- hdmim0_rx_cec: hdmim0-rx-cec {
- rockchip,pins =
- /* hdmim0_rx_cec */
- <4 RK_PB5 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_rx_hpdin: hdmim0-rx-hpdin {
- rockchip,pins =
- /* hdmim0_rx_hpdin */
- <4 RK_PB6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_rx_scl: hdmim0-rx-scl {
- rockchip,pins =
- /* hdmim0_rx_scl */
- <0 RK_PD2 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_rx_sda: hdmim0-rx-sda {
- rockchip,pins =
- /* hdmim0_rx_sda */
- <0 RK_PD1 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx0_cec: hdmim0-tx0-cec {
- rockchip,pins =
- /* hdmim0_tx0_cec */
- <4 RK_PC1 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx0_hpd: hdmim0-tx0-hpd {
- rockchip,pins =
- /* hdmim0_tx0_hpd */
- <1 RK_PA5 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx0_scl: hdmim0-tx0-scl {
- rockchip,pins =
- /* hdmim0_tx0_scl */
- <4 RK_PB7 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx0_sda: hdmim0-tx0-sda {
- rockchip,pins =
- /* hdmim0_tx0_sda */
- <4 RK_PC0 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim0_tx1_hpd: hdmim0-tx1-hpd {
- rockchip,pins =
- /* hdmim0_tx1_hpd */
- <1 RK_PA6 5 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- hdmim1_rx_cec: hdmim1-rx-cec {
- rockchip,pins =
- /* hdmim1_rx_cec */
- <3 RK_PD1 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_rx_hpdin: hdmim1-rx-hpdin {
- rockchip,pins =
- /* hdmim1_rx_hpdin */
- <3 RK_PD4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_rx_scl: hdmim1-rx-scl {
- rockchip,pins =
- /* hdmim1_rx_scl */
- <3 RK_PD2 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_rx_sda: hdmim1-rx-sda {
- rockchip,pins =
- /* hdmim1_rx_sda */
- <3 RK_PD3 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx0_cec: hdmim1-tx0-cec {
- rockchip,pins =
- /* hdmim1_tx0_cec */
- <0 RK_PD1 13 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx0_hpd: hdmim1-tx0-hpd {
- rockchip,pins =
- /* hdmim1_tx0_hpd */
- <3 RK_PD4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx0_scl: hdmim1-tx0-scl {
- rockchip,pins =
- /* hdmim1_tx0_scl */
- <0 RK_PD5 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx0_sda: hdmim1-tx0-sda {
- rockchip,pins =
- /* hdmim1_tx0_sda */
- <0 RK_PD4 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx1_cec: hdmim1-tx1-cec {
- rockchip,pins =
- /* hdmim1_tx1_cec */
- <0 RK_PD2 13 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx1_hpd: hdmim1-tx1-hpd {
- rockchip,pins =
- /* hdmim1_tx1_hpd */
- <3 RK_PB7 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx1_scl: hdmim1-tx1-scl {
- rockchip,pins =
- /* hdmim1_tx1_scl */
- <3 RK_PC6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim1_tx1_sda: hdmim1-tx1-sda {
- rockchip,pins =
- /* hdmim1_tx1_sda */
- <3 RK_PC5 5 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- hdmim2_rx_cec: hdmim2-rx-cec {
- rockchip,pins =
- /* hdmim2_rx_cec */
- <1 RK_PB7 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_rx_hpdin: hdmim2-rx-hpdin {
- rockchip,pins =
- /* hdmim2_rx_hpdin */
- <1 RK_PB6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_rx_scl: hdmim2-rx-scl {
- rockchip,pins =
- /* hdmim2_rx_scl */
- <1 RK_PD6 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_rx_sda: hdmim2-rx-sda {
- rockchip,pins =
- /* hdmim2_rx_sda */
- <1 RK_PD7 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_tx0_scl: hdmim2-tx0-scl {
- rockchip,pins =
- /* hdmim2_tx0_scl */
- <3 RK_PC7 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_tx0_sda: hdmim2-tx0-sda {
- rockchip,pins =
- /* hdmim2_tx0_sda */
- <3 RK_PD0 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_tx1_cec: hdmim2-tx1-cec {
- rockchip,pins =
- /* hdmim2_tx1_cec */
- <3 RK_PC4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_tx1_scl: hdmim2-tx1-scl {
- rockchip,pins =
- /* hdmim2_tx1_scl */
- <1 RK_PA4 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmim2_tx1_sda: hdmim2-tx1-sda {
- rockchip,pins =
- /* hdmim2_tx1_sda */
- <1 RK_PA3 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug0: hdmi-debug0 {
- rockchip,pins =
- /* hdmi_debug0 */
- <1 RK_PA7 7 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug1: hdmi-debug1 {
- rockchip,pins =
- /* hdmi_debug1 */
- <1 RK_PB0 7 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug2: hdmi-debug2 {
- rockchip,pins =
- /* hdmi_debug2 */
- <1 RK_PB1 7 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug3: hdmi-debug3 {
- rockchip,pins =
- /* hdmi_debug3 */
- <1 RK_PB2 7 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug4: hdmi-debug4 {
- rockchip,pins =
- /* hdmi_debug4 */
- <1 RK_PB3 7 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug5: hdmi-debug5 {
- rockchip,pins =
- /* hdmi_debug5 */
- <1 RK_PB4 7 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- hdmi_debug6: hdmi-debug6 {
- rockchip,pins =
- /* hdmi_debug6 */
- <1 RK_PA0 7 &pcfg_pull_none>;
- };
- };
-
- i2c0 {
- /omit-if-no-ref/
- i2c0m0_xfer: i2c0m0-xfer {
- rockchip,pins =
- /* i2c0_scl_m0 */
- <0 RK_PB3 2 &pcfg_pull_none_smt>,
- /* i2c0_sda_m0 */
- <0 RK_PA6 2 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c0m2_xfer: i2c0m2-xfer {
- rockchip,pins =
- /* i2c0_scl_m2 */
- <0 RK_PD1 3 &pcfg_pull_none_smt>,
- /* i2c0_sda_m2 */
- <0 RK_PD2 3 &pcfg_pull_none_smt>;
- };
- };
-
- i2c1 {
- /omit-if-no-ref/
- i2c1m0_xfer: i2c1m0-xfer {
- rockchip,pins =
- /* i2c1_scl_m0 */
- <0 RK_PB5 9 &pcfg_pull_none_smt>,
- /* i2c1_sda_m0 */
- <0 RK_PB6 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c1m1_xfer: i2c1m1-xfer {
- rockchip,pins =
- /* i2c1_scl_m1 */
- <0 RK_PB0 2 &pcfg_pull_none_smt>,
- /* i2c1_sda_m1 */
- <0 RK_PB1 2 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c1m2_xfer: i2c1m2-xfer {
- rockchip,pins =
- /* i2c1_scl_m2 */
- <0 RK_PD4 9 &pcfg_pull_none_smt>,
- /* i2c1_sda_m2 */
- <0 RK_PD5 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c1m3_xfer: i2c1m3-xfer {
- rockchip,pins =
- /* i2c1_scl_m3 */
- <2 RK_PD4 9 &pcfg_pull_none_smt>,
- /* i2c1_sda_m3 */
- <2 RK_PD5 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c1m4_xfer: i2c1m4-xfer {
- rockchip,pins =
- /* i2c1_scl_m4 */
- <1 RK_PD2 9 &pcfg_pull_none_smt>,
- /* i2c1_sda_m4 */
- <1 RK_PD3 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c2 {
- /omit-if-no-ref/
- i2c2m0_xfer: i2c2m0-xfer {
- rockchip,pins =
- /* i2c2_scl_m0 */
- <0 RK_PB7 9 &pcfg_pull_none_smt>,
- /* i2c2_sda_m0 */
- <0 RK_PC0 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c2m2_xfer: i2c2m2-xfer {
- rockchip,pins =
- /* i2c2_scl_m2 */
- <2 RK_PA3 9 &pcfg_pull_none_smt>,
- /* i2c2_sda_m2 */
- <2 RK_PA2 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c2m3_xfer: i2c2m3-xfer {
- rockchip,pins =
- /* i2c2_scl_m3 */
- <1 RK_PC5 9 &pcfg_pull_none_smt>,
- /* i2c2_sda_m3 */
- <1 RK_PC4 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c2m4_xfer: i2c2m4-xfer {
- rockchip,pins =
- /* i2c2_scl_m4 */
- <1 RK_PA1 9 &pcfg_pull_none_smt>,
- /* i2c2_sda_m4 */
- <1 RK_PA0 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c3 {
- /omit-if-no-ref/
- i2c3m0_xfer: i2c3m0-xfer {
- rockchip,pins =
- /* i2c3_scl_m0 */
- <1 RK_PC1 9 &pcfg_pull_none_smt>,
- /* i2c3_sda_m0 */
- <1 RK_PC0 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c3m1_xfer: i2c3m1-xfer {
- rockchip,pins =
- /* i2c3_scl_m1 */
- <3 RK_PB7 9 &pcfg_pull_none_smt>,
- /* i2c3_sda_m1 */
- <3 RK_PC0 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c3m2_xfer: i2c3m2-xfer {
- rockchip,pins =
- /* i2c3_scl_m2 */
- <4 RK_PA4 9 &pcfg_pull_none_smt>,
- /* i2c3_sda_m2 */
- <4 RK_PA5 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c3m4_xfer: i2c3m4-xfer {
- rockchip,pins =
- /* i2c3_scl_m4 */
- <4 RK_PD0 9 &pcfg_pull_none_smt>,
- /* i2c3_sda_m4 */
- <4 RK_PD1 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c4 {
- /omit-if-no-ref/
- i2c4m0_xfer: i2c4m0-xfer {
- rockchip,pins =
- /* i2c4_scl_m0 */
- <3 RK_PA6 9 &pcfg_pull_none_smt>,
- /* i2c4_sda_m0 */
- <3 RK_PA5 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c4m2_xfer: i2c4m2-xfer {
- rockchip,pins =
- /* i2c4_scl_m2 */
- <0 RK_PC5 9 &pcfg_pull_none_smt>,
- /* i2c4_sda_m2 */
- <0 RK_PC4 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c4m3_xfer: i2c4m3-xfer {
- rockchip,pins =
- /* i2c4_scl_m3 */
- <1 RK_PA3 9 &pcfg_pull_none_smt>,
- /* i2c4_sda_m3 */
- <1 RK_PA2 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c4m4_xfer: i2c4m4-xfer {
- rockchip,pins =
- /* i2c4_scl_m4 */
- <1 RK_PC7 9 &pcfg_pull_none_smt>,
- /* i2c4_sda_m4 */
- <1 RK_PC6 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c5 {
- /omit-if-no-ref/
- i2c5m0_xfer: i2c5m0-xfer {
- rockchip,pins =
- /* i2c5_scl_m0 */
- <3 RK_PC7 9 &pcfg_pull_none_smt>,
- /* i2c5_sda_m0 */
- <3 RK_PD0 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c5m1_xfer: i2c5m1-xfer {
- rockchip,pins =
- /* i2c5_scl_m1 */
- <4 RK_PB6 9 &pcfg_pull_none_smt>,
- /* i2c5_sda_m1 */
- <4 RK_PB7 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c5m2_xfer: i2c5m2-xfer {
- rockchip,pins =
- /* i2c5_scl_m2 */
- <4 RK_PA6 9 &pcfg_pull_none_smt>,
- /* i2c5_sda_m2 */
- <4 RK_PA7 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c5m3_xfer: i2c5m3-xfer {
- rockchip,pins =
- /* i2c5_scl_m3 */
- <1 RK_PB6 9 &pcfg_pull_none_smt>,
- /* i2c5_sda_m3 */
- <1 RK_PB7 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c6 {
- /omit-if-no-ref/
- i2c6m0_xfer: i2c6m0-xfer {
- rockchip,pins =
- /* i2c6_scl_m0 */
- <0 RK_PD0 9 &pcfg_pull_none_smt>,
- /* i2c6_sda_m0 */
- <0 RK_PC7 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c6m1_xfer: i2c6m1-xfer {
- rockchip,pins =
- /* i2c6_scl_m1 */
- <1 RK_PC3 9 &pcfg_pull_none_smt>,
- /* i2c6_sda_m1 */
- <1 RK_PC2 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c6m3_xfer: i2c6m3-xfer {
- rockchip,pins =
- /* i2c6_scl_m3 */
- <4 RK_PB1 9 &pcfg_pull_none_smt>,
- /* i2c6_sda_m3 */
- <4 RK_PB0 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c6m4_xfer: i2c6m4-xfer {
- rockchip,pins =
- /* i2c6_scl_m4 */
- <3 RK_PA1 9 &pcfg_pull_none_smt>,
- /* i2c6_sda_m4 */
- <3 RK_PA0 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c7 {
- /omit-if-no-ref/
- i2c7m0_xfer: i2c7m0-xfer {
- rockchip,pins =
- /* i2c7_scl_m0 */
- <1 RK_PD0 9 &pcfg_pull_none_smt>,
- /* i2c7_sda_m0 */
- <1 RK_PD1 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c7m2_xfer: i2c7m2-xfer {
- rockchip,pins =
- /* i2c7_scl_m2 */
- <3 RK_PD2 9 &pcfg_pull_none_smt>,
- /* i2c7_sda_m2 */
- <3 RK_PD3 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c7m3_xfer: i2c7m3-xfer {
- rockchip,pins =
- /* i2c7_scl_m3 */
- <4 RK_PB2 9 &pcfg_pull_none_smt>,
- /* i2c7_sda_m3 */
- <4 RK_PB3 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2c8 {
- /omit-if-no-ref/
- i2c8m0_xfer: i2c8m0-xfer {
- rockchip,pins =
- /* i2c8_scl_m0 */
- <4 RK_PD2 9 &pcfg_pull_none_smt>,
- /* i2c8_sda_m0 */
- <4 RK_PD3 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c8m2_xfer: i2c8m2-xfer {
- rockchip,pins =
- /* i2c8_scl_m2 */
- <1 RK_PD6 9 &pcfg_pull_none_smt>,
- /* i2c8_sda_m2 */
- <1 RK_PD7 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c8m3_xfer: i2c8m3-xfer {
- rockchip,pins =
- /* i2c8_scl_m3 */
- <4 RK_PC0 9 &pcfg_pull_none_smt>,
- /* i2c8_sda_m3 */
- <4 RK_PC1 9 &pcfg_pull_none_smt>;
- };
-
- /omit-if-no-ref/
- i2c8m4_xfer: i2c8m4-xfer {
- rockchip,pins =
- /* i2c8_scl_m4 */
- <3 RK_PC2 9 &pcfg_pull_none_smt>,
- /* i2c8_sda_m4 */
- <3 RK_PC3 9 &pcfg_pull_none_smt>;
- };
- };
-
- i2s0 {
- /omit-if-no-ref/
- i2s0_lrck: i2s0-lrck {
- rockchip,pins =
- /* i2s0_lrck */
- <1 RK_PC5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_mclk: i2s0-mclk {
- rockchip,pins =
- /* i2s0_mclk */
- <1 RK_PC2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sclk: i2s0-sclk {
- rockchip,pins =
- /* i2s0_sclk */
- <1 RK_PC3 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdi0: i2s0-sdi0 {
- rockchip,pins =
- /* i2s0_sdi0 */
- <1 RK_PD4 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdi1: i2s0-sdi1 {
- rockchip,pins =
- /* i2s0_sdi1 */
- <1 RK_PD3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdi2: i2s0-sdi2 {
- rockchip,pins =
- /* i2s0_sdi2 */
- <1 RK_PD2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdi3: i2s0-sdi3 {
- rockchip,pins =
- /* i2s0_sdi3 */
- <1 RK_PD1 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdo0: i2s0-sdo0 {
- rockchip,pins =
- /* i2s0_sdo0 */
- <1 RK_PC7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdo1: i2s0-sdo1 {
- rockchip,pins =
- /* i2s0_sdo1 */
- <1 RK_PD0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdo2: i2s0-sdo2 {
- rockchip,pins =
- /* i2s0_sdo2 */
- <1 RK_PD1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s0_sdo3: i2s0-sdo3 {
- rockchip,pins =
- /* i2s0_sdo3 */
- <1 RK_PD2 1 &pcfg_pull_none>;
- };
- };
-
- i2s1 {
- /omit-if-no-ref/
- i2s1m0_lrck: i2s1m0-lrck {
- rockchip,pins =
- /* i2s1m0_lrck */
- <4 RK_PA2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_mclk: i2s1m0-mclk {
- rockchip,pins =
- /* i2s1m0_mclk */
- <4 RK_PA0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sclk: i2s1m0-sclk {
- rockchip,pins =
- /* i2s1m0_sclk */
- <4 RK_PA1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdi0: i2s1m0-sdi0 {
- rockchip,pins =
- /* i2s1m0_sdi0 */
- <4 RK_PA5 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdi1: i2s1m0-sdi1 {
- rockchip,pins =
- /* i2s1m0_sdi1 */
- <4 RK_PA6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdi2: i2s1m0-sdi2 {
- rockchip,pins =
- /* i2s1m0_sdi2 */
- <4 RK_PA7 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdi3: i2s1m0-sdi3 {
- rockchip,pins =
- /* i2s1m0_sdi3 */
- <4 RK_PB0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdo0: i2s1m0-sdo0 {
- rockchip,pins =
- /* i2s1m0_sdo0 */
- <4 RK_PB1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdo1: i2s1m0-sdo1 {
- rockchip,pins =
- /* i2s1m0_sdo1 */
- <4 RK_PB2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdo2: i2s1m0-sdo2 {
- rockchip,pins =
- /* i2s1m0_sdo2 */
- <4 RK_PB3 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m0_sdo3: i2s1m0-sdo3 {
- rockchip,pins =
- /* i2s1m0_sdo3 */
- <4 RK_PB4 3 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- i2s1m1_lrck: i2s1m1-lrck {
- rockchip,pins =
- /* i2s1m1_lrck */
- <0 RK_PB7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_mclk: i2s1m1-mclk {
- rockchip,pins =
- /* i2s1m1_mclk */
- <0 RK_PB5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sclk: i2s1m1-sclk {
- rockchip,pins =
- /* i2s1m1_sclk */
- <0 RK_PB6 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdi0: i2s1m1-sdi0 {
- rockchip,pins =
- /* i2s1m1_sdi0 */
- <0 RK_PC5 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdi1: i2s1m1-sdi1 {
- rockchip,pins =
- /* i2s1m1_sdi1 */
- <0 RK_PC6 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdi2: i2s1m1-sdi2 {
- rockchip,pins =
- /* i2s1m1_sdi2 */
- <0 RK_PC7 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdi3: i2s1m1-sdi3 {
- rockchip,pins =
- /* i2s1m1_sdi3 */
- <0 RK_PD0 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdo0: i2s1m1-sdo0 {
- rockchip,pins =
- /* i2s1m1_sdo0 */
- <0 RK_PD1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdo1: i2s1m1-sdo1 {
- rockchip,pins =
- /* i2s1m1_sdo1 */
- <0 RK_PD2 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdo2: i2s1m1-sdo2 {
- rockchip,pins =
- /* i2s1m1_sdo2 */
- <0 RK_PD4 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s1m1_sdo3: i2s1m1-sdo3 {
- rockchip,pins =
- /* i2s1m1_sdo3 */
- <0 RK_PD5 1 &pcfg_pull_none>;
- };
- };
-
- i2s2 {
- /omit-if-no-ref/
- i2s2m0_lrck: i2s2m0-lrck {
- rockchip,pins =
- /* i2s2m0_lrck */
- <2 RK_PC0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_mclk: i2s2m0-mclk {
- rockchip,pins =
- /* i2s2m0_mclk */
- <2 RK_PB6 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sclk: i2s2m0-sclk {
- rockchip,pins =
- /* i2s2m0_sclk */
- <2 RK_PB7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sdi: i2s2m0-sdi {
- rockchip,pins =
- /* i2s2m0_sdi */
- <2 RK_PC3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m0_sdo: i2s2m0-sdo {
- rockchip,pins =
- /* i2s2m0_sdo */
- <4 RK_PC3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_lrck: i2s2m1-lrck {
- rockchip,pins =
- /* i2s2m1_lrck */
- <3 RK_PB6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_mclk: i2s2m1-mclk {
- rockchip,pins =
- /* i2s2m1_mclk */
- <3 RK_PB4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_sclk: i2s2m1-sclk {
- rockchip,pins =
- /* i2s2m1_sclk */
- <3 RK_PB5 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_sdi: i2s2m1-sdi {
- rockchip,pins =
- /* i2s2m1_sdi */
- <3 RK_PB2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s2m1_sdo: i2s2m1-sdo {
- rockchip,pins =
- /* i2s2m1_sdo */
- <3 RK_PB3 3 &pcfg_pull_none>;
- };
- };
-
- i2s3 {
- /omit-if-no-ref/
- i2s3_lrck: i2s3-lrck {
- rockchip,pins =
- /* i2s3_lrck */
- <3 RK_PA2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3_mclk: i2s3-mclk {
- rockchip,pins =
- /* i2s3_mclk */
- <3 RK_PA0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3_sclk: i2s3-sclk {
- rockchip,pins =
- /* i2s3_sclk */
- <3 RK_PA1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3_sdi: i2s3-sdi {
- rockchip,pins =
- /* i2s3_sdi */
- <3 RK_PA4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- i2s3_sdo: i2s3-sdo {
- rockchip,pins =
- /* i2s3_sdo */
- <3 RK_PA3 3 &pcfg_pull_none>;
- };
- };
-
- jtag {
- /omit-if-no-ref/
- jtagm0_pins: jtagm0-pins {
- rockchip,pins =
- /* jtag_tck_m0 */
- <4 RK_PD2 5 &pcfg_pull_none>,
- /* jtag_tms_m0 */
- <4 RK_PD3 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- jtagm1_pins: jtagm1-pins {
- rockchip,pins =
- /* jtag_tck_m1 */
- <4 RK_PD0 5 &pcfg_pull_none>,
- /* jtag_tms_m1 */
- <4 RK_PD1 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- jtagm2_pins: jtagm2-pins {
- rockchip,pins =
- /* jtag_tck_m2 */
- <0 RK_PB5 2 &pcfg_pull_none>,
- /* jtag_tms_m2 */
- <0 RK_PB6 2 &pcfg_pull_none>;
- };
- };
-
- litcpu {
- /omit-if-no-ref/
- litcpu_pins: litcpu-pins {
- rockchip,pins =
- /* litcpu_avs */
- <0 RK_PD3 1 &pcfg_pull_none>;
- };
- };
-
- mcu {
- /omit-if-no-ref/
- mcum0_pins: mcum0-pins {
- rockchip,pins =
- /* mcu_jtag_tck_m0 */
- <4 RK_PD4 5 &pcfg_pull_none>,
- /* mcu_jtag_tms_m0 */
- <4 RK_PD5 5 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mcum1_pins: mcum1-pins {
- rockchip,pins =
- /* mcu_jtag_tck_m1 */
- <3 RK_PD4 6 &pcfg_pull_none>,
- /* mcu_jtag_tms_m1 */
- <3 RK_PD5 6 &pcfg_pull_none>;
- };
- };
-
- mipi {
- /omit-if-no-ref/
- mipim0_camera0_clk: mipim0-camera0-clk {
- rockchip,pins =
- /* mipim0_camera0_clk */
- <4 RK_PB1 1 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim0_camera1_clk: mipim0-camera1-clk {
- rockchip,pins =
- /* mipim0_camera1_clk */
- <1 RK_PB6 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim0_camera2_clk: mipim0-camera2-clk {
- rockchip,pins =
- /* mipim0_camera2_clk */
- <1 RK_PB7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim0_camera3_clk: mipim0-camera3-clk {
- rockchip,pins =
- /* mipim0_camera3_clk */
- <1 RK_PD6 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim0_camera4_clk: mipim0-camera4-clk {
- rockchip,pins =
- /* mipim0_camera4_clk */
- <1 RK_PD7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim1_camera0_clk: mipim1-camera0-clk {
- rockchip,pins =
- /* mipim1_camera0_clk */
- <3 RK_PA5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim1_camera1_clk: mipim1-camera1-clk {
- rockchip,pins =
- /* mipim1_camera1_clk */
- <3 RK_PA6 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim1_camera2_clk: mipim1-camera2-clk {
- rockchip,pins =
- /* mipim1_camera2_clk */
- <3 RK_PA7 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim1_camera3_clk: mipim1-camera3-clk {
- rockchip,pins =
- /* mipim1_camera3_clk */
- <3 RK_PB0 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipim1_camera4_clk: mipim1-camera4-clk {
- rockchip,pins =
- /* mipim1_camera4_clk */
- <3 RK_PB1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipi_te0: mipi-te0 {
- rockchip,pins =
- /* mipi_te0 */
- <3 RK_PC2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- mipi_te1: mipi-te1 {
- rockchip,pins =
- /* mipi_te1 */
- <3 RK_PC3 2 &pcfg_pull_none>;
- };
- };
-
- npu {
- /omit-if-no-ref/
- npu_pins: npu-pins {
- rockchip,pins =
- /* npu_avs */
- <0 RK_PC6 2 &pcfg_pull_none>;
- };
- };
-
- pcie20x1 {
- /omit-if-no-ref/
- pcie20x1m0_pins: pcie20x1m0-pins {
- rockchip,pins =
- /* pcie20x1_2_clkreqn_m0 */
- <3 RK_PC7 4 &pcfg_pull_none>,
- /* pcie20x1_2_perstn_m0 */
- <3 RK_PD1 4 &pcfg_pull_none>,
- /* pcie20x1_2_waken_m0 */
- <3 RK_PD0 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie20x1m1_pins: pcie20x1m1-pins {
- rockchip,pins =
- /* pcie20x1_2_clkreqn_m1 */
- <4 RK_PB7 4 &pcfg_pull_none>,
- /* pcie20x1_2_perstn_m1 */
- <4 RK_PC1 4 &pcfg_pull_none>,
- /* pcie20x1_2_waken_m1 */
- <4 RK_PC0 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
- rockchip,pins =
- /* pcie20x1_2_button_rstn */
- <4 RK_PB3 4 &pcfg_pull_none>;
- };
- };
-
- pcie30phy {
- /omit-if-no-ref/
- pcie30phy_pins: pcie30phy-pins {
- rockchip,pins =
- /* pcie30phy_dtb0 */
- <1 RK_PC4 4 &pcfg_pull_none>,
- /* pcie30phy_dtb1 */
- <1 RK_PD1 4 &pcfg_pull_none>;
- };
- };
-
- pcie30x1 {
- /omit-if-no-ref/
- pcie30x1m0_pins: pcie30x1m0-pins {
- rockchip,pins =
- /* pcie30x1_0_clkreqn_m0 */
- <0 RK_PC0 12 &pcfg_pull_none>,
- /* pcie30x1_0_perstn_m0 */
- <0 RK_PC5 12 &pcfg_pull_none>,
- /* pcie30x1_0_waken_m0 */
- <0 RK_PC4 12 &pcfg_pull_none>,
- /* pcie30x1_1_clkreqn_m0 */
- <0 RK_PB5 12 &pcfg_pull_none>,
- /* pcie30x1_1_perstn_m0 */
- <0 RK_PB7 12 &pcfg_pull_none>,
- /* pcie30x1_1_waken_m0 */
- <0 RK_PB6 12 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x1m1_pins: pcie30x1m1-pins {
- rockchip,pins =
- /* pcie30x1_0_clkreqn_m1 */
- <4 RK_PA3 4 &pcfg_pull_none>,
- /* pcie30x1_0_perstn_m1 */
- <4 RK_PA5 4 &pcfg_pull_none>,
- /* pcie30x1_0_waken_m1 */
- <4 RK_PA4 4 &pcfg_pull_none>,
- /* pcie30x1_1_clkreqn_m1 */
- <4 RK_PA0 4 &pcfg_pull_none>,
- /* pcie30x1_1_perstn_m1 */
- <4 RK_PA2 4 &pcfg_pull_none>,
- /* pcie30x1_1_waken_m1 */
- <4 RK_PA1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x1m2_pins: pcie30x1m2-pins {
- rockchip,pins =
- /* pcie30x1_0_clkreqn_m2 */
- <1 RK_PB5 4 &pcfg_pull_none>,
- /* pcie30x1_0_perstn_m2 */
- <1 RK_PB4 4 &pcfg_pull_none>,
- /* pcie30x1_0_waken_m2 */
- <1 RK_PB3 4 &pcfg_pull_none>,
- /* pcie30x1_1_clkreqn_m2 */
- <1 RK_PA0 4 &pcfg_pull_none>,
- /* pcie30x1_1_perstn_m2 */
- <1 RK_PA7 4 &pcfg_pull_none>,
- /* pcie30x1_1_waken_m2 */
- <1 RK_PA1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
- rockchip,pins =
- /* pcie30x1_0_button_rstn */
- <4 RK_PB1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
- rockchip,pins =
- /* pcie30x1_1_button_rstn */
- <4 RK_PB2 4 &pcfg_pull_none>;
- };
- };
-
- pcie30x2 {
- /omit-if-no-ref/
- pcie30x2m0_pins: pcie30x2m0-pins {
- rockchip,pins =
- /* pcie30x2_clkreqn_m0 */
- <0 RK_PD1 12 &pcfg_pull_none>,
- /* pcie30x2_perstn_m0 */
- <0 RK_PD4 12 &pcfg_pull_none>,
- /* pcie30x2_waken_m0 */
- <0 RK_PD2 12 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x2m1_pins: pcie30x2m1-pins {
- rockchip,pins =
- /* pcie30x2_clkreqn_m1 */
- <4 RK_PA6 4 &pcfg_pull_none>,
- /* pcie30x2_perstn_m1 */
- <4 RK_PB0 4 &pcfg_pull_none>,
- /* pcie30x2_waken_m1 */
- <4 RK_PA7 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x2m2_pins: pcie30x2m2-pins {
- rockchip,pins =
- /* pcie30x2_clkreqn_m2 */
- <3 RK_PD2 4 &pcfg_pull_none>,
- /* pcie30x2_perstn_m2 */
- <3 RK_PD4 4 &pcfg_pull_none>,
- /* pcie30x2_waken_m2 */
- <3 RK_PD3 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x2m3_pins: pcie30x2m3-pins {
- rockchip,pins =
- /* pcie30x2_clkreqn_m3 */
- <1 RK_PD7 4 &pcfg_pull_none>,
- /* pcie30x2_perstn_m3 */
- <1 RK_PB7 4 &pcfg_pull_none>,
- /* pcie30x2_waken_m3 */
- <1 RK_PB6 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x2_button_rstn: pcie30x2-button-rstn {
- rockchip,pins =
- /* pcie30x2_button_rstn */
- <3 RK_PC1 4 &pcfg_pull_none>;
- };
- };
-
- pcie30x4 {
- /omit-if-no-ref/
- pcie30x4m0_pins: pcie30x4m0-pins {
- rockchip,pins =
- /* pcie30x4_clkreqn_m0 */
- <0 RK_PC6 12 &pcfg_pull_none>,
- /* pcie30x4_perstn_m0 */
- <0 RK_PD0 12 &pcfg_pull_none>,
- /* pcie30x4_waken_m0 */
- <0 RK_PC7 12 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x4m1_pins: pcie30x4m1-pins {
- rockchip,pins =
- /* pcie30x4_clkreqn_m1 */
- <4 RK_PB4 4 &pcfg_pull_none>,
- /* pcie30x4_perstn_m1 */
- <4 RK_PB6 4 &pcfg_pull_none>,
- /* pcie30x4_waken_m1 */
- <4 RK_PB5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x4m2_pins: pcie30x4m2-pins {
- rockchip,pins =
- /* pcie30x4_clkreqn_m2 */
- <3 RK_PC4 4 &pcfg_pull_none>,
- /* pcie30x4_perstn_m2 */
- <3 RK_PC6 4 &pcfg_pull_none>,
- /* pcie30x4_waken_m2 */
- <3 RK_PC5 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x4m3_pins: pcie30x4m3-pins {
- rockchip,pins =
- /* pcie30x4_clkreqn_m3 */
- <1 RK_PB0 4 &pcfg_pull_none>,
- /* pcie30x4_perstn_m3 */
- <1 RK_PB2 4 &pcfg_pull_none>,
- /* pcie30x4_waken_m3 */
- <1 RK_PB1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pcie30x4_button_rstn: pcie30x4-button-rstn {
- rockchip,pins =
- /* pcie30x4_button_rstn */
- <3 RK_PD5 4 &pcfg_pull_none>;
- };
- };
-
- pdm0 {
- /omit-if-no-ref/
- pdm0m0_clk: pdm0m0-clk {
- rockchip,pins =
- /* pdm0_clk0_m0 */
- <1 RK_PC6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m0_clk1: pdm0m0-clk1 {
- rockchip,pins =
- /* pdm0m0_clk1 */
- <1 RK_PC4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m0_sdi0: pdm0m0-sdi0 {
- rockchip,pins =
- /* pdm0m0_sdi0 */
- <1 RK_PD5 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m0_sdi1: pdm0m0-sdi1 {
- rockchip,pins =
- /* pdm0m0_sdi1 */
- <1 RK_PD1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m0_sdi2: pdm0m0-sdi2 {
- rockchip,pins =
- /* pdm0m0_sdi2 */
- <1 RK_PD2 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m0_sdi3: pdm0m0-sdi3 {
- rockchip,pins =
- /* pdm0m0_sdi3 */
- <1 RK_PD3 3 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- pdm0m1_clk: pdm0m1-clk {
- rockchip,pins =
- /* pdm0_clk0_m1 */
- <0 RK_PC0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m1_clk1: pdm0m1-clk1 {
- rockchip,pins =
- /* pdm0m1_clk1 */
- <0 RK_PC4 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m1_sdi0: pdm0m1-sdi0 {
- rockchip,pins =
- /* pdm0m1_sdi0 */
- <0 RK_PC7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m1_sdi1: pdm0m1-sdi1 {
- rockchip,pins =
- /* pdm0m1_sdi1 */
- <0 RK_PD0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m1_sdi2: pdm0m1-sdi2 {
- rockchip,pins =
- /* pdm0m1_sdi2 */
- <0 RK_PD4 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm0m1_sdi3: pdm0m1-sdi3 {
- rockchip,pins =
- /* pdm0m1_sdi3 */
- <0 RK_PD6 2 &pcfg_pull_none>;
- };
- };
-
- pdm1 {
- /omit-if-no-ref/
- pdm1m0_clk: pdm1m0-clk {
- rockchip,pins =
- /* pdm1_clk0_m0 */
- <4 RK_PD5 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m0_clk1: pdm1m0-clk1 {
- rockchip,pins =
- /* pdm1m0_clk1 */
- <4 RK_PD4 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m0_sdi0: pdm1m0-sdi0 {
- rockchip,pins =
- /* pdm1m0_sdi0 */
- <4 RK_PD3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m0_sdi1: pdm1m0-sdi1 {
- rockchip,pins =
- /* pdm1m0_sdi1 */
- <4 RK_PD2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m0_sdi2: pdm1m0-sdi2 {
- rockchip,pins =
- /* pdm1m0_sdi2 */
- <4 RK_PD1 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m0_sdi3: pdm1m0-sdi3 {
- rockchip,pins =
- /* pdm1m0_sdi3 */
- <4 RK_PD0 2 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- pdm1m1_clk: pdm1m1-clk {
- rockchip,pins =
- /* pdm1_clk0_m1 */
- <1 RK_PB4 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m1_clk1: pdm1m1-clk1 {
- rockchip,pins =
- /* pdm1m1_clk1 */
- <1 RK_PB3 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m1_sdi0: pdm1m1-sdi0 {
- rockchip,pins =
- /* pdm1m1_sdi0 */
- <1 RK_PA7 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m1_sdi1: pdm1m1-sdi1 {
- rockchip,pins =
- /* pdm1m1_sdi1 */
- <1 RK_PB0 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m1_sdi2: pdm1m1-sdi2 {
- rockchip,pins =
- /* pdm1m1_sdi2 */
- <1 RK_PB1 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pdm1m1_sdi3: pdm1m1-sdi3 {
- rockchip,pins =
- /* pdm1m1_sdi3 */
- <1 RK_PB2 2 &pcfg_pull_none>;
- };
- };
-
- pmic {
- /omit-if-no-ref/
- pmic_pins: pmic-pins {
- rockchip,pins =
- /* pmic_int_l */
- <0 RK_PA7 0 &pcfg_pull_up>,
- /* pmic_sleep1 */
- <0 RK_PA2 1 &pcfg_pull_none>,
- /* pmic_sleep2 */
- <0 RK_PA3 1 &pcfg_pull_none>,
- /* pmic_sleep3 */
- <0 RK_PC1 1 &pcfg_pull_none>,
- /* pmic_sleep4 */
- <0 RK_PC2 1 &pcfg_pull_none>,
- /* pmic_sleep5 */
- <0 RK_PC3 1 &pcfg_pull_none>,
- /* pmic_sleep6 */
- <0 RK_PD6 1 &pcfg_pull_none>;
- };
- };
-
- pmu {
- /omit-if-no-ref/
- pmu_pins: pmu-pins {
- rockchip,pins =
- /* pmu_debug */
- <0 RK_PA5 3 &pcfg_pull_none>;
- };
- };
-
- pwm0 {
- /omit-if-no-ref/
- pwm0m0_pins: pwm0m0-pins {
- rockchip,pins =
- /* pwm0_m0 */
- <0 RK_PB7 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm0m1_pins: pwm0m1-pins {
- rockchip,pins =
- /* pwm0_m1 */
- <1 RK_PD2 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm0m2_pins: pwm0m2-pins {
- rockchip,pins =
- /* pwm0_m2 */
- <1 RK_PA2 11 &pcfg_pull_none>;
- };
- };
-
- pwm1 {
- /omit-if-no-ref/
- pwm1m0_pins: pwm1m0-pins {
- rockchip,pins =
- /* pwm1_m0 */
- <0 RK_PC0 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm1m1_pins: pwm1m1-pins {
- rockchip,pins =
- /* pwm1_m1 */
- <1 RK_PD3 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm1m2_pins: pwm1m2-pins {
- rockchip,pins =
- /* pwm1_m2 */
- <1 RK_PA3 11 &pcfg_pull_none>;
- };
- };
-
- pwm2 {
- /omit-if-no-ref/
- pwm2m0_pins: pwm2m0-pins {
- rockchip,pins =
- /* pwm2_m0 */
- <0 RK_PC4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm2m1_pins: pwm2m1-pins {
- rockchip,pins =
- /* pwm2_m1 */
- <3 RK_PB1 11 &pcfg_pull_none>;
- };
- };
-
- pwm3 {
- /omit-if-no-ref/
- pwm3m0_pins: pwm3m0-pins {
- rockchip,pins =
- /* pwm3_ir_m0 */
- <0 RK_PD4 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm3m1_pins: pwm3m1-pins {
- rockchip,pins =
- /* pwm3_ir_m1 */
- <3 RK_PB2 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm3m2_pins: pwm3m2-pins {
- rockchip,pins =
- /* pwm3_ir_m2 */
- <1 RK_PC2 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm3m3_pins: pwm3m3-pins {
- rockchip,pins =
- /* pwm3_ir_m3 */
- <1 RK_PA7 11 &pcfg_pull_none>;
- };
- };
-
- pwm4 {
- /omit-if-no-ref/
- pwm4m0_pins: pwm4m0-pins {
- rockchip,pins =
- /* pwm4_m0 */
- <0 RK_PC5 11 &pcfg_pull_none>;
- };
- };
-
- pwm5 {
- /omit-if-no-ref/
- pwm5m0_pins: pwm5m0-pins {
- rockchip,pins =
- /* pwm5_m0 */
- <0 RK_PB1 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm5m1_pins: pwm5m1-pins {
- rockchip,pins =
- /* pwm5_m1 */
- <0 RK_PC6 11 &pcfg_pull_none>;
- };
- };
-
- pwm6 {
- /omit-if-no-ref/
- pwm6m0_pins: pwm6m0-pins {
- rockchip,pins =
- /* pwm6_m0 */
- <0 RK_PC7 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm6m1_pins: pwm6m1-pins {
- rockchip,pins =
- /* pwm6_m1 */
- <4 RK_PC1 11 &pcfg_pull_none>;
- };
- };
-
- pwm7 {
- /omit-if-no-ref/
- pwm7m0_pins: pwm7m0-pins {
- rockchip,pins =
- /* pwm7_ir_m0 */
- <0 RK_PD0 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm7m1_pins: pwm7m1-pins {
- rockchip,pins =
- /* pwm7_ir_m1 */
- <4 RK_PD4 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm7m2_pins: pwm7m2-pins {
- rockchip,pins =
- /* pwm7_ir_m2 */
- <1 RK_PC3 11 &pcfg_pull_none>;
- };
- };
-
- pwm8 {
- /omit-if-no-ref/
- pwm8m0_pins: pwm8m0-pins {
- rockchip,pins =
- /* pwm8_m0 */
- <3 RK_PA7 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm8m1_pins: pwm8m1-pins {
- rockchip,pins =
- /* pwm8_m1 */
- <4 RK_PD0 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm8m2_pins: pwm8m2-pins {
- rockchip,pins =
- /* pwm8_m2 */
- <3 RK_PD0 11 &pcfg_pull_none>;
- };
- };
-
- pwm9 {
- /omit-if-no-ref/
- pwm9m0_pins: pwm9m0-pins {
- rockchip,pins =
- /* pwm9_m0 */
- <3 RK_PB0 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm9m1_pins: pwm9m1-pins {
- rockchip,pins =
- /* pwm9_m1 */
- <4 RK_PD1 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm9m2_pins: pwm9m2-pins {
- rockchip,pins =
- /* pwm9_m2 */
- <3 RK_PD1 11 &pcfg_pull_none>;
- };
- };
-
- pwm10 {
- /omit-if-no-ref/
- pwm10m0_pins: pwm10m0-pins {
- rockchip,pins =
- /* pwm10_m0 */
- <3 RK_PA0 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm10m1_pins: pwm10m1-pins {
- rockchip,pins =
- /* pwm10_m1 */
- <4 RK_PD3 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm10m2_pins: pwm10m2-pins {
- rockchip,pins =
- /* pwm10_m2 */
- <3 RK_PD3 11 &pcfg_pull_none>;
- };
- };
-
- pwm11 {
- /omit-if-no-ref/
- pwm11m0_pins: pwm11m0-pins {
- rockchip,pins =
- /* pwm11_ir_m0 */
- <3 RK_PA1 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm11m1_pins: pwm11m1-pins {
- rockchip,pins =
- /* pwm11_ir_m1 */
- <4 RK_PB4 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm11m2_pins: pwm11m2-pins {
- rockchip,pins =
- /* pwm11_ir_m2 */
- <1 RK_PC4 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm11m3_pins: pwm11m3-pins {
- rockchip,pins =
- /* pwm11_ir_m3 */
- <3 RK_PD5 11 &pcfg_pull_none>;
- };
- };
-
- pwm12 {
- /omit-if-no-ref/
- pwm12m0_pins: pwm12m0-pins {
- rockchip,pins =
- /* pwm12_m0 */
- <3 RK_PB5 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm12m1_pins: pwm12m1-pins {
- rockchip,pins =
- /* pwm12_m1 */
- <4 RK_PB5 11 &pcfg_pull_none>;
- };
- };
-
- pwm13 {
- /omit-if-no-ref/
- pwm13m0_pins: pwm13m0-pins {
- rockchip,pins =
- /* pwm13_m0 */
- <3 RK_PB6 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm13m1_pins: pwm13m1-pins {
- rockchip,pins =
- /* pwm13_m1 */
- <4 RK_PB6 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm13m2_pins: pwm13m2-pins {
- rockchip,pins =
- /* pwm13_m2 */
- <1 RK_PB7 11 &pcfg_pull_none>;
- };
- };
-
- pwm14 {
- /omit-if-no-ref/
- pwm14m0_pins: pwm14m0-pins {
- rockchip,pins =
- /* pwm14_m0 */
- <3 RK_PC2 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm14m1_pins: pwm14m1-pins {
- rockchip,pins =
- /* pwm14_m1 */
- <4 RK_PB2 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm14m2_pins: pwm14m2-pins {
- rockchip,pins =
- /* pwm14_m2 */
- <1 RK_PD6 11 &pcfg_pull_none>;
- };
- };
-
- pwm15 {
- /omit-if-no-ref/
- pwm15m0_pins: pwm15m0-pins {
- rockchip,pins =
- /* pwm15_ir_m0 */
- <3 RK_PC3 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm15m1_pins: pwm15m1-pins {
- rockchip,pins =
- /* pwm15_ir_m1 */
- <4 RK_PB3 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm15m2_pins: pwm15m2-pins {
- rockchip,pins =
- /* pwm15_ir_m2 */
- <1 RK_PC6 11 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- pwm15m3_pins: pwm15m3-pins {
- rockchip,pins =
- /* pwm15_ir_m3 */
- <1 RK_PD7 11 &pcfg_pull_none>;
- };
- };
-
- refclk {
- /omit-if-no-ref/
- refclk_pins: refclk-pins {
- rockchip,pins =
- /* refclk_out */
- <0 RK_PA0 1 &pcfg_pull_none>;
- };
- };
-
- sata {
- /omit-if-no-ref/
- sata_pins: sata-pins {
- rockchip,pins =
- /* sata_cp_pod */
- <0 RK_PC6 13 &pcfg_pull_none>,
- /* sata_cpdet */
- <0 RK_PD4 13 &pcfg_pull_none>,
- /* sata_mp_switch */
- <0 RK_PD5 13 &pcfg_pull_none>;
- };
- };
-
- sata0 {
- /omit-if-no-ref/
- sata0m0_pins: sata0m0-pins {
- rockchip,pins =
- /* sata0_act_led_m0 */
- <4 RK_PB6 6 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- sata0m1_pins: sata0m1-pins {
- rockchip,pins =
- /* sata0_act_led_m1 */
- <1 RK_PB3 6 &pcfg_pull_none>;
- };
- };
-
- sata1 {
- /omit-if-no-ref/
- sata1m0_pins: sata1m0-pins {
- rockchip,pins =
- /* sata1_act_led_m0 */
- <4 RK_PB5 6 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- sata1m1_pins: sata1m1-pins {
- rockchip,pins =
- /* sata1_act_led_m1 */
- <1 RK_PA1 6 &pcfg_pull_none>;
- };
- };
-
- sata2 {
- /omit-if-no-ref/
- sata2m0_pins: sata2m0-pins {
- rockchip,pins =
- /* sata2_act_led_m0 */
- <4 RK_PB1 6 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- sata2m1_pins: sata2m1-pins {
- rockchip,pins =
- /* sata2_act_led_m1 */
- <1 RK_PB7 6 &pcfg_pull_none>;
- };
- };
-
- sdio {
- /omit-if-no-ref/
- sdiom1_pins: sdiom1-pins {
- rockchip,pins =
- /* sdio_clk_m1 */
- <3 RK_PA5 2 &pcfg_pull_none>,
- /* sdio_cmd_m1 */
- <3 RK_PA4 2 &pcfg_pull_none>,
- /* sdio_d0_m1 */
- <3 RK_PA0 2 &pcfg_pull_none>,
- /* sdio_d1_m1 */
- <3 RK_PA1 2 &pcfg_pull_none>,
- /* sdio_d2_m1 */
- <3 RK_PA2 2 &pcfg_pull_none>,
- /* sdio_d3_m1 */
- <3 RK_PA3 2 &pcfg_pull_none>;
- };
- };
-
- sdmmc {
- /omit-if-no-ref/
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins =
- /* sdmmc_d0 */
- <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc_d1 */
- <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc_d2 */
- <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc_d3 */
- <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc_clk: sdmmc-clk {
- rockchip,pins =
- /* sdmmc_clk */
- <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins =
- /* sdmmc_cmd */
- <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
- };
-
- /omit-if-no-ref/
- sdmmc_det: sdmmc-det {
- rockchip,pins =
- /* sdmmc_det */
- <0 RK_PA4 1 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- sdmmc_pwren: sdmmc-pwren {
- rockchip,pins =
- /* sdmmc_pwren */
- <0 RK_PA5 2 &pcfg_pull_none>;
- };
- };
-
- spdif0 {
- /omit-if-no-ref/
- spdif0m0_tx: spdif0m0-tx {
- rockchip,pins =
- /* spdif0m0_tx */
- <1 RK_PB6 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spdif0m1_tx: spdif0m1-tx {
- rockchip,pins =
- /* spdif0m1_tx */
- <4 RK_PB4 6 &pcfg_pull_none>;
- };
- };
-
- spdif1 {
- /omit-if-no-ref/
- spdif1m0_tx: spdif1m0-tx {
- rockchip,pins =
- /* spdif1m0_tx */
- <1 RK_PB7 3 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spdif1m1_tx: spdif1m1-tx {
- rockchip,pins =
- /* spdif1m1_tx */
- <4 RK_PB1 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- spdif1m2_tx: spdif1m2-tx {
- rockchip,pins =
- /* spdif1m2_tx */
- <4 RK_PC1 3 &pcfg_pull_none>;
- };
- };
-
- spi0 {
- /omit-if-no-ref/
- spi0m0_pins: spi0m0-pins {
- rockchip,pins =
- /* spi0_clk_m0 */
- <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
- /* spi0_miso_m0 */
- <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>,
- /* spi0_mosi_m0 */
- <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi0m0_cs0: spi0m0-cs0 {
- rockchip,pins =
- /* spi0_cs0_m0 */
- <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi0m0_cs1: spi0m0-cs1 {
- rockchip,pins =
- /* spi0_cs1_m0 */
- <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
- };
- /omit-if-no-ref/
- spi0m1_pins: spi0m1-pins {
- rockchip,pins =
- /* spi0_clk_m1 */
- <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
- /* spi0_miso_m1 */
- <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
- /* spi0_mosi_m1 */
- <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi0m1_cs0: spi0m1-cs0 {
- rockchip,pins =
- /* spi0_cs0_m1 */
- <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi0m1_cs1: spi0m1-cs1 {
- rockchip,pins =
- /* spi0_cs1_m1 */
- <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>;
- };
- /omit-if-no-ref/
- spi0m2_pins: spi0m2-pins {
- rockchip,pins =
- /* spi0_clk_m2 */
- <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>,
- /* spi0_miso_m2 */
- <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>,
- /* spi0_mosi_m2 */
- <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi0m2_cs0: spi0m2-cs0 {
- rockchip,pins =
- /* spi0_cs0_m2 */
- <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi0m2_cs1: spi0m2-cs1 {
- rockchip,pins =
- /* spi0_cs1_m2 */
- <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>;
- };
- /omit-if-no-ref/
- spi0m3_pins: spi0m3-pins {
- rockchip,pins =
- /* spi0_clk_m3 */
- <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
- /* spi0_miso_m3 */
- <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>,
- /* spi0_mosi_m3 */
- <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi0m3_cs0: spi0m3-cs0 {
- rockchip,pins =
- /* spi0_cs0_m3 */
- <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi0m3_cs1: spi0m3-cs1 {
- rockchip,pins =
- /* spi0_cs1_m3 */
- <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- spi1 {
- /omit-if-no-ref/
- spi1m1_pins: spi1m1-pins {
- rockchip,pins =
- /* spi1_clk_m1 */
- <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
- /* spi1_miso_m1 */
- <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
- /* spi1_mosi_m1 */
- <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m1_cs0: spi1m1-cs0 {
- rockchip,pins =
- /* spi1_cs0_m1 */
- <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m1_cs1: spi1m1-cs1 {
- rockchip,pins =
- /* spi1_cs1_m1 */
- <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m2_pins: spi1m2-pins {
- rockchip,pins =
- /* spi1_clk_m2 */
- <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>,
- /* spi1_miso_m2 */
- <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
- /* spi1_mosi_m2 */
- <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m2_cs0: spi1m2-cs0 {
- rockchip,pins =
- /* spi1_cs0_m2 */
- <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi1m2_cs1: spi1m2-cs1 {
- rockchip,pins =
- /* spi1_cs1_m2 */
- <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- spi2 {
- /omit-if-no-ref/
- spi2m0_pins: spi2m0-pins {
- rockchip,pins =
- /* spi2_clk_m0 */
- <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
- /* spi2_miso_m0 */
- <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
- /* spi2_mosi_m0 */
- <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m0_cs0: spi2m0-cs0 {
- rockchip,pins =
- /* spi2_cs0_m0 */
- <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m0_cs1: spi2m0-cs1 {
- rockchip,pins =
- /* spi2_cs1_m0 */
- <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m1_pins: spi2m1-pins {
- rockchip,pins =
- /* spi2_clk_m1 */
- <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
- /* spi2_miso_m1 */
- <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
- /* spi2_mosi_m1 */
- <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m1_cs0: spi2m1-cs0 {
- rockchip,pins =
- /* spi2_cs0_m1 */
- <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m1_cs1: spi2m1-cs1 {
- rockchip,pins =
- /* spi2_cs1_m1 */
- <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m2_pins: spi2m2-pins {
- rockchip,pins =
- /* spi2_clk_m2 */
- <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
- /* spi2_miso_m2 */
- <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
- /* spi2_mosi_m2 */
- <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m2_cs0: spi2m2-cs0 {
- rockchip,pins =
- /* spi2_cs0_m2 */
- <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi2m2_cs1: spi2m2-cs1 {
- rockchip,pins =
- /* spi2_cs1_m2 */
- <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- spi3 {
- /omit-if-no-ref/
- spi3m1_pins: spi3m1-pins {
- rockchip,pins =
- /* spi3_clk_m1 */
- <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>,
- /* spi3_miso_m1 */
- <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>,
- /* spi3_mosi_m1 */
- <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m1_cs0: spi3m1-cs0 {
- rockchip,pins =
- /* spi3_cs0_m1 */
- <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m1_cs1: spi3m1-cs1 {
- rockchip,pins =
- /* spi3_cs1_m1 */
- <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m2_pins: spi3m2-pins {
- rockchip,pins =
- /* spi3_clk_m2 */
- <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
- /* spi3_miso_m2 */
- <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
- /* spi3_mosi_m2 */
- <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m2_cs0: spi3m2-cs0 {
- rockchip,pins =
- /* spi3_cs0_m2 */
- <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m2_cs1: spi3m2-cs1 {
- rockchip,pins =
- /* spi3_cs1_m2 */
- <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m3_pins: spi3m3-pins {
- rockchip,pins =
- /* spi3_clk_m3 */
- <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
- /* spi3_miso_m3 */
- <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
- /* spi3_mosi_m3 */
- <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m3_cs0: spi3m3-cs0 {
- rockchip,pins =
- /* spi3_cs0_m3 */
- <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi3m3_cs1: spi3m3-cs1 {
- rockchip,pins =
- /* spi3_cs1_m3 */
- <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- spi4 {
- /omit-if-no-ref/
- spi4m0_pins: spi4m0-pins {
- rockchip,pins =
- /* spi4_clk_m0 */
- <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>,
- /* spi4_miso_m0 */
- <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
- /* spi4_mosi_m0 */
- <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi4m0_cs0: spi4m0-cs0 {
- rockchip,pins =
- /* spi4_cs0_m0 */
- <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi4m0_cs1: spi4m0-cs1 {
- rockchip,pins =
- /* spi4_cs1_m0 */
- <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi4m1_pins: spi4m1-pins {
- rockchip,pins =
- /* spi4_clk_m1 */
- <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
- /* spi4_miso_m1 */
- <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
- /* spi4_mosi_m1 */
- <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi4m1_cs0: spi4m1-cs0 {
- rockchip,pins =
- /* spi4_cs0_m1 */
- <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi4m1_cs1: spi4m1-cs1 {
- rockchip,pins =
- /* spi4_cs1_m1 */
- <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi4m2_pins: spi4m2-pins {
- rockchip,pins =
- /* spi4_clk_m2 */
- <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
- /* spi4_miso_m2 */
- <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
- /* spi4_mosi_m2 */
- <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
- };
-
- /omit-if-no-ref/
- spi4m2_cs0: spi4m2-cs0 {
- rockchip,pins =
- /* spi4_cs0_m2 */
- <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
- };
- };
-
- tsadc {
- /omit-if-no-ref/
- tsadcm1_shut: tsadcm1-shut {
- rockchip,pins =
- /* tsadcm1_shut */
- <0 RK_PA2 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- tsadc_shut: tsadc-shut {
- rockchip,pins =
- /* tsadc_shut */
- <0 RK_PA1 2 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- tsadc_shut_org: tsadc-shut-org {
- rockchip,pins =
- /* tsadc_shut_org */
- <0 RK_PA1 1 &pcfg_pull_none>;
- };
- };
-
- uart0 {
- /omit-if-no-ref/
- uart0m0_xfer: uart0m0-xfer {
- rockchip,pins =
- /* uart0_rx_m0 */
- <0 RK_PC4 4 &pcfg_pull_up>,
- /* uart0_tx_m0 */
- <0 RK_PC5 4 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart0m1_xfer: uart0m1-xfer {
- rockchip,pins =
- /* uart0_rx_m1 */
- <0 RK_PB0 4 &pcfg_pull_up>,
- /* uart0_tx_m1 */
- <0 RK_PB1 4 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart0m2_xfer: uart0m2-xfer {
- rockchip,pins =
- /* uart0_rx_m2 */
- <4 RK_PA4 10 &pcfg_pull_up>,
- /* uart0_tx_m2 */
- <4 RK_PA3 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart0_ctsn: uart0-ctsn {
- rockchip,pins =
- /* uart0_ctsn */
- <0 RK_PD1 4 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart0_rtsn: uart0-rtsn {
- rockchip,pins =
- /* uart0_rtsn */
- <0 RK_PC6 4 &pcfg_pull_none>;
- };
- };
-
- uart1 {
- /omit-if-no-ref/
- uart1m1_xfer: uart1m1-xfer {
- rockchip,pins =
- /* uart1_rx_m1 */
- <1 RK_PB7 10 &pcfg_pull_up>,
- /* uart1_tx_m1 */
- <1 RK_PB6 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart1m1_ctsn: uart1m1-ctsn {
- rockchip,pins =
- /* uart1m1_ctsn */
- <1 RK_PD7 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart1m1_rtsn: uart1m1-rtsn {
- rockchip,pins =
- /* uart1m1_rtsn */
- <1 RK_PD6 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart1m2_xfer: uart1m2-xfer {
- rockchip,pins =
- /* uart1_rx_m2 */
- <0 RK_PD2 10 &pcfg_pull_up>,
- /* uart1_tx_m2 */
- <0 RK_PD1 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart1m2_ctsn: uart1m2-ctsn {
- rockchip,pins =
- /* uart1m2_ctsn */
- <0 RK_PD0 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart1m2_rtsn: uart1m2-rtsn {
- rockchip,pins =
- /* uart1m2_rtsn */
- <0 RK_PC7 10 &pcfg_pull_none>;
- };
- };
-
- uart2 {
- /omit-if-no-ref/
- uart2m0_xfer: uart2m0-xfer {
- rockchip,pins =
- /* uart2_rx_m0 */
- <0 RK_PB6 10 &pcfg_pull_up>,
- /* uart2_tx_m0 */
- <0 RK_PB5 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart2m1_xfer: uart2m1-xfer {
- rockchip,pins =
- /* uart2_rx_m1 */
- <4 RK_PD1 10 &pcfg_pull_up>,
- /* uart2_tx_m1 */
- <4 RK_PD0 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart2m2_xfer: uart2m2-xfer {
- rockchip,pins =
- /* uart2_rx_m2 */
- <3 RK_PB2 10 &pcfg_pull_up>,
- /* uart2_tx_m2 */
- <3 RK_PB1 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart2_ctsn: uart2-ctsn {
- rockchip,pins =
- /* uart2_ctsn */
- <3 RK_PB4 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart2_rtsn: uart2-rtsn {
- rockchip,pins =
- /* uart2_rtsn */
- <3 RK_PB3 10 &pcfg_pull_none>;
- };
- };
-
- uart3 {
- /omit-if-no-ref/
- uart3m0_xfer: uart3m0-xfer {
- rockchip,pins =
- /* uart3_rx_m0 */
- <1 RK_PC0 10 &pcfg_pull_up>,
- /* uart3_tx_m0 */
- <1 RK_PC1 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart3m1_xfer: uart3m1-xfer {
- rockchip,pins =
- /* uart3_rx_m1 */
- <3 RK_PB6 10 &pcfg_pull_up>,
- /* uart3_tx_m1 */
- <3 RK_PB5 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart3m2_xfer: uart3m2-xfer {
- rockchip,pins =
- /* uart3_rx_m2 */
- <4 RK_PA6 10 &pcfg_pull_up>,
- /* uart3_tx_m2 */
- <4 RK_PA5 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart3_ctsn: uart3-ctsn {
- rockchip,pins =
- /* uart3_ctsn */
- <1 RK_PC3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart3_rtsn: uart3-rtsn {
- rockchip,pins =
- /* uart3_rtsn */
- <1 RK_PC2 10 &pcfg_pull_none>;
- };
- };
-
- uart4 {
- /omit-if-no-ref/
- uart4m0_xfer: uart4m0-xfer {
- rockchip,pins =
- /* uart4_rx_m0 */
- <1 RK_PD3 10 &pcfg_pull_up>,
- /* uart4_tx_m0 */
- <1 RK_PD2 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart4m1_xfer: uart4m1-xfer {
- rockchip,pins =
- /* uart4_rx_m1 */
- <3 RK_PD0 10 &pcfg_pull_up>,
- /* uart4_tx_m1 */
- <3 RK_PD1 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart4m2_xfer: uart4m2-xfer {
- rockchip,pins =
- /* uart4_rx_m2 */
- <1 RK_PB2 10 &pcfg_pull_up>,
- /* uart4_tx_m2 */
- <1 RK_PB3 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart4_ctsn: uart4-ctsn {
- rockchip,pins =
- /* uart4_ctsn */
- <1 RK_PC7 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart4_rtsn: uart4-rtsn {
- rockchip,pins =
- /* uart4_rtsn */
- <1 RK_PC5 10 &pcfg_pull_none>;
- };
- };
-
- uart5 {
- /omit-if-no-ref/
- uart5m0_xfer: uart5m0-xfer {
- rockchip,pins =
- /* uart5_rx_m0 */
- <4 RK_PD4 10 &pcfg_pull_up>,
- /* uart5_tx_m0 */
- <4 RK_PD5 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart5m0_ctsn: uart5m0-ctsn {
- rockchip,pins =
- /* uart5m0_ctsn */
- <4 RK_PD2 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart5m0_rtsn: uart5m0-rtsn {
- rockchip,pins =
- /* uart5m0_rtsn */
- <4 RK_PD3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart5m1_xfer: uart5m1-xfer {
- rockchip,pins =
- /* uart5_rx_m1 */
- <3 RK_PC5 10 &pcfg_pull_up>,
- /* uart5_tx_m1 */
- <3 RK_PC4 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart5m1_ctsn: uart5m1-ctsn {
- rockchip,pins =
- /* uart5m1_ctsn */
- <2 RK_PA2 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart5m1_rtsn: uart5m1-rtsn {
- rockchip,pins =
- /* uart5m1_rtsn */
- <2 RK_PA3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart5m2_xfer: uart5m2-xfer {
- rockchip,pins =
- /* uart5_rx_m2 */
- <2 RK_PD4 10 &pcfg_pull_up>,
- /* uart5_tx_m2 */
- <2 RK_PD5 10 &pcfg_pull_up>;
- };
- };
-
- uart6 {
- /omit-if-no-ref/
- uart6m1_xfer: uart6m1-xfer {
- rockchip,pins =
- /* uart6_rx_m1 */
- <1 RK_PA0 10 &pcfg_pull_up>,
- /* uart6_tx_m1 */
- <1 RK_PA1 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart6m1_ctsn: uart6m1-ctsn {
- rockchip,pins =
- /* uart6m1_ctsn */
- <1 RK_PA3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart6m1_rtsn: uart6m1-rtsn {
- rockchip,pins =
- /* uart6m1_rtsn */
- <1 RK_PA2 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart6m2_xfer: uart6m2-xfer {
- rockchip,pins =
- /* uart6_rx_m2 */
- <1 RK_PD1 10 &pcfg_pull_up>,
- /* uart6_tx_m2 */
- <1 RK_PD0 10 &pcfg_pull_up>;
- };
- };
-
- uart7 {
- /omit-if-no-ref/
- uart7m1_xfer: uart7m1-xfer {
- rockchip,pins =
- /* uart7_rx_m1 */
- <3 RK_PC1 10 &pcfg_pull_up>,
- /* uart7_tx_m1 */
- <3 RK_PC0 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart7m1_ctsn: uart7m1-ctsn {
- rockchip,pins =
- /* uart7m1_ctsn */
- <3 RK_PC3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart7m1_rtsn: uart7m1-rtsn {
- rockchip,pins =
- /* uart7m1_rtsn */
- <3 RK_PC2 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart7m2_xfer: uart7m2-xfer {
- rockchip,pins =
- /* uart7_rx_m2 */
- <1 RK_PB4 10 &pcfg_pull_up>,
- /* uart7_tx_m2 */
- <1 RK_PB5 10 &pcfg_pull_up>;
- };
- };
-
- uart8 {
- /omit-if-no-ref/
- uart8m0_xfer: uart8m0-xfer {
- rockchip,pins =
- /* uart8_rx_m0 */
- <4 RK_PB1 10 &pcfg_pull_up>,
- /* uart8_tx_m0 */
- <4 RK_PB0 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart8m0_ctsn: uart8m0-ctsn {
- rockchip,pins =
- /* uart8m0_ctsn */
- <4 RK_PB3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart8m0_rtsn: uart8m0-rtsn {
- rockchip,pins =
- /* uart8m0_rtsn */
- <4 RK_PB2 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart8m1_xfer: uart8m1-xfer {
- rockchip,pins =
- /* uart8_rx_m1 */
- <3 RK_PA3 10 &pcfg_pull_up>,
- /* uart8_tx_m1 */
- <3 RK_PA2 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart8m1_ctsn: uart8m1-ctsn {
- rockchip,pins =
- /* uart8m1_ctsn */
- <3 RK_PA5 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart8m1_rtsn: uart8m1-rtsn {
- rockchip,pins =
- /* uart8m1_rtsn */
- <3 RK_PA4 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart8_xfer: uart8-xfer {
- rockchip,pins =
- /* uart8_rx_ */
- <4 RK_PB1 10 &pcfg_pull_up>;
- };
- };
-
- uart9 {
- /omit-if-no-ref/
- uart9m0_xfer: uart9m0-xfer {
- rockchip,pins =
- /* uart9_rx_m0 */
- <2 RK_PC4 10 &pcfg_pull_up>,
- /* uart9_tx_m0 */
- <2 RK_PC2 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart9m1_xfer: uart9m1-xfer {
- rockchip,pins =
- /* uart9_rx_m1 */
- <4 RK_PB5 10 &pcfg_pull_up>,
- /* uart9_tx_m1 */
- <4 RK_PB4 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart9m1_ctsn: uart9m1-ctsn {
- rockchip,pins =
- /* uart9m1_ctsn */
- <4 RK_PA1 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart9m1_rtsn: uart9m1-rtsn {
- rockchip,pins =
- /* uart9m1_rtsn */
- <4 RK_PA0 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart9m2_xfer: uart9m2-xfer {
- rockchip,pins =
- /* uart9_rx_m2 */
- <3 RK_PD4 10 &pcfg_pull_up>,
- /* uart9_tx_m2 */
- <3 RK_PD5 10 &pcfg_pull_up>;
- };
-
- /omit-if-no-ref/
- uart9m2_ctsn: uart9m2-ctsn {
- rockchip,pins =
- /* uart9m2_ctsn */
- <3 RK_PD3 10 &pcfg_pull_none>;
- };
-
- /omit-if-no-ref/
- uart9m2_rtsn: uart9m2-rtsn {
- rockchip,pins =
- /* uart9m2_rtsn */
- <3 RK_PD2 10 &pcfg_pull_none>;
- };
- };
-
- vop {
- /omit-if-no-ref/
- vop_pins: vop-pins {
- rockchip,pins =
- /* vop_post_empty */
- <1 RK_PA2 1 &pcfg_pull_none>;
- };
- };
-};
-
-/*
- * This part is edited handly.
- */
-&pinctrl {
- bt656 {
- /omit-if-no-ref/
- bt656_pins: bt656-pins {
- rockchip,pins =
- /* bt1120_clkout */
- <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d0 */
- <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d1 */
- <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d2 */
- <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d3 */
- <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d4 */
- <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d5 */
- <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d6 */
- <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
- /* bt1120_d7 */
- <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
- };
- };
-
- gpio-func {
- /omit-if-no-ref/
- tsadc_gpio_func: tsadc-gpio-func {
- rockchip,pins =
- <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
<&cru ACLK_USB3OTG0>;
clock-names = "ref_clk", "suspend_clk", "bus_clk";
dr_mode = "otg";
- phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
+ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
power-domains = <&power RK3588_PD_USB>;
};
usb2phy0_grf: syscon@fd5d0000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
- "simple-mfd";
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5d0000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
- u2phy0: usb2-phy@0 {
+ u2phy0: usb2phy@0 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x0 0x10>;
- interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy0";
- #clock-cells = <0>;
+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy0_otg: otg-port {
usbdp_phy0: phy@fed80000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed80000 0x0 0x10000>;
- rockchip,u2phy-grf = <&usb2phy0_grf>;
- rockchip,usb-grf = <&usb_grf>;
- rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
- rockchip,vo-grf = <&vo0_grf>;
+ #phy-cells = <1>;
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
<&cru CLK_USBDP_PHY0_IMMORTAL>,
<&cru PCLK_USBDPPHY0>,
<&cru SRST_USBDP_COMBO_PHY0_PCS>,
<&cru SRST_P_USBDPPHY0>;
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy0_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
status = "disabled";
-
- usbdp_phy0_dp: dp-port {
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usbdp_phy0_u3: usb3-port {
- #phy-cells = <0>;
- status = "disabled";
- };
};
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/clock/rockchip,rk3588-cru.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/power/rk3588-power.h>
-#include <dt-bindings/reset/rockchip,rk3588-cru.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/ata/ahci.h>
-
-/ {
- compatible = "rockchip,rk3588";
-
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
- gpio3 = &gpio3;
- gpio4 = &gpio4;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &i2c7;
- i2c8 = &i2c8;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- serial4 = &uart4;
- serial5 = &uart5;
- serial6 = &uart6;
- serial7 = &uart7;
- serial8 = &uart8;
- serial9 = &uart9;
- spi0 = &spi0;
- spi1 = &spi1;
- spi2 = &spi2;
- spi3 = &spi3;
- spi4 = &spi4;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu_l0>;
- };
- core1 {
- cpu = <&cpu_l1>;
- };
- core2 {
- cpu = <&cpu_l2>;
- };
- core3 {
- cpu = <&cpu_l3>;
- };
- };
- cluster1 {
- core0 {
- cpu = <&cpu_b0>;
- };
- core1 {
- cpu = <&cpu_b1>;
- };
- };
- cluster2 {
- core0 {
- cpu = <&cpu_b2>;
- };
- core1 {
- cpu = <&cpu_b3>;
- };
- };
- };
-
- cpu_l0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0>;
- enable-method = "psci";
- capacity-dmips-mhz = <530>;
- clocks = <&scmi_clk SCMI_CLK_CPUL>;
- assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
- assigned-clock-rates = <816000000>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <32768>;
- i-cache-line-size = <64>;
- i-cache-sets = <128>;
- d-cache-size = <32768>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&l2_cache_l0>;
- dynamic-power-coefficient = <228>;
- #cooling-cells = <2>;
- };
-
- cpu_l1: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x100>;
- enable-method = "psci";
- capacity-dmips-mhz = <530>;
- clocks = <&scmi_clk SCMI_CLK_CPUL>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <32768>;
- i-cache-line-size = <64>;
- i-cache-sets = <128>;
- d-cache-size = <32768>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&l2_cache_l1>;
- dynamic-power-coefficient = <228>;
- #cooling-cells = <2>;
- };
-
- cpu_l2: cpu@200 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x200>;
- enable-method = "psci";
- capacity-dmips-mhz = <530>;
- clocks = <&scmi_clk SCMI_CLK_CPUL>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <32768>;
- i-cache-line-size = <64>;
- i-cache-sets = <128>;
- d-cache-size = <32768>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&l2_cache_l2>;
- dynamic-power-coefficient = <228>;
- #cooling-cells = <2>;
- };
-
- cpu_l3: cpu@300 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x300>;
- enable-method = "psci";
- capacity-dmips-mhz = <530>;
- clocks = <&scmi_clk SCMI_CLK_CPUL>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <32768>;
- i-cache-line-size = <64>;
- i-cache-sets = <128>;
- d-cache-size = <32768>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&l2_cache_l3>;
- dynamic-power-coefficient = <228>;
- #cooling-cells = <2>;
- };
-
- cpu_b0: cpu@400 {
- device_type = "cpu";
- compatible = "arm,cortex-a76";
- reg = <0x400>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- clocks = <&scmi_clk SCMI_CLK_CPUB01>;
- assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
- assigned-clock-rates = <816000000>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <65536>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <65536>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&l2_cache_b0>;
- dynamic-power-coefficient = <416>;
- #cooling-cells = <2>;
- };
-
- cpu_b1: cpu@500 {
- device_type = "cpu";
- compatible = "arm,cortex-a76";
- reg = <0x500>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- clocks = <&scmi_clk SCMI_CLK_CPUB01>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <65536>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <65536>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&l2_cache_b1>;
- dynamic-power-coefficient = <416>;
- #cooling-cells = <2>;
- };
-
- cpu_b2: cpu@600 {
- device_type = "cpu";
- compatible = "arm,cortex-a76";
- reg = <0x600>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- clocks = <&scmi_clk SCMI_CLK_CPUB23>;
- assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
- assigned-clock-rates = <816000000>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <65536>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <65536>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&l2_cache_b2>;
- dynamic-power-coefficient = <416>;
- #cooling-cells = <2>;
- };
-
- cpu_b3: cpu@700 {
- device_type = "cpu";
- compatible = "arm,cortex-a76";
- reg = <0x700>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- clocks = <&scmi_clk SCMI_CLK_CPUB23>;
- cpu-idle-states = <&CPU_SLEEP>;
- i-cache-size = <65536>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <65536>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&l2_cache_b3>;
- dynamic-power-coefficient = <416>;
- #cooling-cells = <2>;
- };
-
- idle-states {
- entry-method = "psci";
- CPU_SLEEP: cpu-sleep {
- compatible = "arm,idle-state";
- local-timer-stop;
- arm,psci-suspend-param = <0x0010000>;
- entry-latency-us = <100>;
- exit-latency-us = <120>;
- min-residency-us = <1000>;
- };
- };
-
- l2_cache_l0: l2-cache-l0 {
- compatible = "cache";
- cache-size = <131072>;
- cache-line-size = <64>;
- cache-sets = <512>;
- cache-level = <2>;
- cache-unified;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_l1: l2-cache-l1 {
- compatible = "cache";
- cache-size = <131072>;
- cache-line-size = <64>;
- cache-sets = <512>;
- cache-level = <2>;
- cache-unified;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_l2: l2-cache-l2 {
- compatible = "cache";
- cache-size = <131072>;
- cache-line-size = <64>;
- cache-sets = <512>;
- cache-level = <2>;
- cache-unified;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_l3: l2-cache-l3 {
- compatible = "cache";
- cache-size = <131072>;
- cache-line-size = <64>;
- cache-sets = <512>;
- cache-level = <2>;
- cache-unified;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_b0: l2-cache-b0 {
- compatible = "cache";
- cache-size = <524288>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- cache-level = <2>;
- cache-unified;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_b1: l2-cache-b1 {
- compatible = "cache";
- cache-size = <524288>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- cache-level = <2>;
- cache-unified;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_b2: l2-cache-b2 {
- compatible = "cache";
- cache-size = <524288>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- cache-level = <2>;
- cache-unified;
- next-level-cache = <&l3_cache>;
- };
-
- l2_cache_b3: l2-cache-b3 {
- compatible = "cache";
- cache-size = <524288>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- cache-level = <2>;
- cache-unified;
- next-level-cache = <&l3_cache>;
- };
-
- l3_cache: l3-cache {
- compatible = "cache";
- cache-size = <3145728>;
- cache-line-size = <64>;
- cache-sets = <4096>;
- cache-level = <3>;
- cache-unified;
- };
- };
-
- firmware {
- optee: optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- scmi: scmi {
- compatible = "arm,scmi-smc";
- arm,smc-id = <0x82000010>;
- shmem = <&scmi_shmem>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
- };
-
- scmi_reset: protocol@16 {
- reg = <0x16>;
- #reset-cells = <1>;
- };
- };
- };
-
- pmu-a55 {
- compatible = "arm,cortex-a55-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
- };
-
- pmu-a76 {
- compatible = "arm,cortex-a76-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- spll: clock-0 {
- compatible = "fixed-clock";
- clock-frequency = <702000000>;
- clock-output-names = "spll";
- #clock-cells = <0>;
- };
-
- display_subsystem: display-subsystem {
- compatible = "rockchip,display-subsystem";
- ports = <&vop_out>;
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
- };
-
- xin24m: clock-1 {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- #clock-cells = <0>;
- };
-
- xin32k: clock-2 {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- #clock-cells = <0>;
- };
-
- pmu_sram: sram@10f000 {
- compatible = "mmio-sram";
- reg = <0x0 0x0010f000 0x0 0x100>;
- ranges = <0 0x0 0x0010f000 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- scmi_shmem: sram@0 {
- compatible = "arm,scmi-shmem";
- reg = <0x0 0x100>;
- };
- };
-
- usb_host0_ehci: usb@fc800000 {
- compatible = "rockchip,rk3588-ehci", "generic-ehci";
- reg = <0x0 0xfc800000 0x0 0x40000>;
- interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
- phys = <&u2phy2_host>;
- phy-names = "usb";
- power-domains = <&power RK3588_PD_USB>;
- status = "disabled";
- };
-
- usb_host0_ohci: usb@fc840000 {
- compatible = "rockchip,rk3588-ohci", "generic-ohci";
- reg = <0x0 0xfc840000 0x0 0x40000>;
- interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
- phys = <&u2phy2_host>;
- phy-names = "usb";
- power-domains = <&power RK3588_PD_USB>;
- status = "disabled";
- };
-
- usb_host1_ehci: usb@fc880000 {
- compatible = "rockchip,rk3588-ehci", "generic-ehci";
- reg = <0x0 0xfc880000 0x0 0x40000>;
- interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
- phys = <&u2phy3_host>;
- phy-names = "usb";
- power-domains = <&power RK3588_PD_USB>;
- status = "disabled";
- };
-
- usb_host1_ohci: usb@fc8c0000 {
- compatible = "rockchip,rk3588-ohci", "generic-ohci";
- reg = <0x0 0xfc8c0000 0x0 0x40000>;
- interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
- phys = <&u2phy3_host>;
- phy-names = "usb";
- power-domains = <&power RK3588_PD_USB>;
- status = "disabled";
- };
-
- usb_host2_xhci: usb@fcd00000 {
- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
- reg = <0x0 0xfcd00000 0x0 0x400000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
- <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
- <&cru CLK_PIPEPHY2_PIPE_U3_G>;
- clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
- dr_mode = "host";
- phys = <&combphy2_psu PHY_TYPE_USB3>;
- phy-names = "usb3-phy";
- phy_type = "utmi_wide";
- resets = <&cru SRST_A_USB3OTG2>;
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,dis_rxdet_inp3_quirk;
- status = "disabled";
- };
-
- pmu1grf: syscon@fd58a000 {
- compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
- reg = <0x0 0xfd58a000 0x0 0x10000>;
- };
-
- sys_grf: syscon@fd58c000 {
- compatible = "rockchip,rk3588-sys-grf", "syscon";
- reg = <0x0 0xfd58c000 0x0 0x1000>;
- };
-
- vop_grf: syscon@fd5a4000 {
- compatible = "rockchip,rk3588-vop-grf", "syscon";
- reg = <0x0 0xfd5a4000 0x0 0x2000>;
- };
-
- vo1_grf: syscon@fd5a8000 {
- compatible = "rockchip,rk3588-vo-grf", "syscon";
- reg = <0x0 0xfd5a8000 0x0 0x100>;
- };
-
- php_grf: syscon@fd5b0000 {
- compatible = "rockchip,rk3588-php-grf", "syscon";
- reg = <0x0 0xfd5b0000 0x0 0x1000>;
- };
-
- pipe_phy0_grf: syscon@fd5bc000 {
- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
- reg = <0x0 0xfd5bc000 0x0 0x100>;
- };
-
- pipe_phy2_grf: syscon@fd5c4000 {
- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
- reg = <0x0 0xfd5c4000 0x0 0x100>;
- };
-
- usb2phy2_grf: syscon@fd5d8000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
- reg = <0x0 0xfd5d8000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy2: usb2-phy@8000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0x8000 0x10>;
- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
- reset-names = "phy", "apb";
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy2";
- #clock-cells = <0>;
- status = "disabled";
-
- u2phy2_host: host-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
- usb2phy3_grf: syscon@fd5dc000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
- reg = <0x0 0xfd5dc000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy3: usb2-phy@c000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0xc000 0x10>;
- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
- reset-names = "phy", "apb";
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy3";
- #clock-cells = <0>;
- status = "disabled";
-
- u2phy3_host: host-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
- ioc: syscon@fd5f0000 {
- compatible = "rockchip,rk3588-ioc", "syscon";
- reg = <0x0 0xfd5f0000 0x0 0x10000>;
- };
-
- system_sram1: sram@fd600000 {
- compatible = "mmio-sram";
- reg = <0x0 0xfd600000 0x0 0x100000>;
- ranges = <0x0 0x0 0xfd600000 0x100000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- cru: clock-controller@fd7c0000 {
- compatible = "rockchip,rk3588-cru";
- reg = <0x0 0xfd7c0000 0x0 0x5c000>;
- assigned-clocks =
- <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
- <&cru PLL_NPLL>, <&cru PLL_GPLL>,
- <&cru ACLK_CENTER_ROOT>,
- <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
- <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
- <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
- <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
- <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
- <&cru CLK_GPU>;
- assigned-clock-rates =
- <1100000000>, <786432000>,
- <850000000>, <1188000000>,
- <702000000>,
- <400000000>, <500000000>,
- <800000000>, <100000000>,
- <400000000>, <100000000>,
- <200000000>, <500000000>,
- <375000000>, <150000000>,
- <200000000>;
- rockchip,grf = <&php_grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- i2c0: i2c@fd880000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfd880000 0x0 0x1000>;
- interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
- clock-names = "i2c", "pclk";
- pinctrl-0 = <&i2c0m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- vop: vop@fdd90000 {
- compatible = "rockchip,rk3588-vop";
- reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
- reg-names = "vop", "gamma-lut";
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_VOP>,
- <&cru HCLK_VOP>,
- <&cru DCLK_VOP0>,
- <&cru DCLK_VOP1>,
- <&cru DCLK_VOP2>,
- <&cru DCLK_VOP3>,
- <&cru PCLK_VOP_ROOT>;
- clock-names = "aclk",
- "hclk",
- "dclk_vp0",
- "dclk_vp1",
- "dclk_vp2",
- "dclk_vp3",
- "pclk_vop";
- iommus = <&vop_mmu>;
- power-domains = <&power RK3588_PD_VOP>;
- rockchip,grf = <&sys_grf>;
- rockchip,vop-grf = <&vop_grf>;
- rockchip,vo1-grf = <&vo1_grf>;
- rockchip,pmu = <&pmu>;
- status = "disabled";
-
- vop_out: ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- vp0: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- vp1: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
-
- vp2: port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- vp3: port@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
- };
- };
-
- vop_mmu: iommu@fdd97e00 {
- compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
- reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- power-domains = <&power RK3588_PD_VOP>;
- status = "disabled";
- };
-
- uart0: serial@fd890000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfd890000 0x0 0x100>;
- interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 6>, <&dmac0 7>;
- dma-names = "tx", "rx";
- pinctrl-0 = <&uart0m1_xfer>;
- pinctrl-names = "default";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- pwm0: pwm@fd8b0000 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfd8b0000 0x0 0x10>;
- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm0m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm1: pwm@fd8b0010 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfd8b0010 0x0 0x10>;
- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm1m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm2: pwm@fd8b0020 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfd8b0020 0x0 0x10>;
- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm2m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm3: pwm@fd8b0030 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfd8b0030 0x0 0x10>;
- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm3m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pmu: power-management@fd8d8000 {
- compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
- reg = <0x0 0xfd8d8000 0x0 0x400>;
-
- power: power-controller {
- compatible = "rockchip,rk3588-power-controller";
- #address-cells = <1>;
- #power-domain-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- /* These power domains are grouped by VD_NPU */
- power-domain@RK3588_PD_NPU {
- reg = <RK3588_PD_NPU>;
- #power-domain-cells = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- power-domain@RK3588_PD_NPUTOP {
- reg = <RK3588_PD_NPUTOP>;
- clocks = <&cru HCLK_NPU_ROOT>,
- <&cru PCLK_NPU_ROOT>,
- <&cru CLK_NPU_DSU0>,
- <&cru HCLK_NPU_CM0_ROOT>;
- pm_qos = <&qos_npu0_mwr>,
- <&qos_npu0_mro>,
- <&qos_mcu_npu>;
- #power-domain-cells = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- power-domain@RK3588_PD_NPU1 {
- reg = <RK3588_PD_NPU1>;
- clocks = <&cru HCLK_NPU_ROOT>,
- <&cru PCLK_NPU_ROOT>,
- <&cru CLK_NPU_DSU0>;
- pm_qos = <&qos_npu1>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_NPU2 {
- reg = <RK3588_PD_NPU2>;
- clocks = <&cru HCLK_NPU_ROOT>,
- <&cru PCLK_NPU_ROOT>,
- <&cru CLK_NPU_DSU0>;
- pm_qos = <&qos_npu2>;
- #power-domain-cells = <0>;
- };
- };
- };
- /* These power domains are grouped by VD_GPU */
- power-domain@RK3588_PD_GPU {
- reg = <RK3588_PD_GPU>;
- clocks = <&cru CLK_GPU>,
- <&cru CLK_GPU_COREGROUP>,
- <&cru CLK_GPU_STACKS>;
- pm_qos = <&qos_gpu_m0>,
- <&qos_gpu_m1>,
- <&qos_gpu_m2>,
- <&qos_gpu_m3>;
- #power-domain-cells = <0>;
- };
- /* These power domains are grouped by VD_VCODEC */
- power-domain@RK3588_PD_VCODEC {
- reg = <RK3588_PD_VCODEC>;
- #address-cells = <1>;
- #size-cells = <0>;
- #power-domain-cells = <0>;
-
- power-domain@RK3588_PD_RKVDEC0 {
- reg = <RK3588_PD_RKVDEC0>;
- clocks = <&cru HCLK_RKVDEC0>,
- <&cru HCLK_VDPU_ROOT>,
- <&cru ACLK_VDPU_ROOT>,
- <&cru ACLK_RKVDEC0>,
- <&cru ACLK_RKVDEC_CCU>;
- pm_qos = <&qos_rkvdec0>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_RKVDEC1 {
- reg = <RK3588_PD_RKVDEC1>;
- clocks = <&cru HCLK_RKVDEC1>,
- <&cru HCLK_VDPU_ROOT>,
- <&cru ACLK_VDPU_ROOT>,
- <&cru ACLK_RKVDEC1>;
- pm_qos = <&qos_rkvdec1>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_VENC0 {
- reg = <RK3588_PD_VENC0>;
- clocks = <&cru HCLK_RKVENC0>,
- <&cru ACLK_RKVENC0>;
- pm_qos = <&qos_rkvenc0_m0ro>,
- <&qos_rkvenc0_m1ro>,
- <&qos_rkvenc0_m2wo>;
- #address-cells = <1>;
- #size-cells = <0>;
- #power-domain-cells = <0>;
-
- power-domain@RK3588_PD_VENC1 {
- reg = <RK3588_PD_VENC1>;
- clocks = <&cru HCLK_RKVENC1>,
- <&cru HCLK_RKVENC0>,
- <&cru ACLK_RKVENC0>,
- <&cru ACLK_RKVENC1>;
- pm_qos = <&qos_rkvenc1_m0ro>,
- <&qos_rkvenc1_m1ro>,
- <&qos_rkvenc1_m2wo>;
- #power-domain-cells = <0>;
- };
- };
- };
- /* These power domains are grouped by VD_LOGIC */
- power-domain@RK3588_PD_VDPU {
- reg = <RK3588_PD_VDPU>;
- clocks = <&cru HCLK_VDPU_ROOT>,
- <&cru ACLK_VDPU_LOW_ROOT>,
- <&cru ACLK_VDPU_ROOT>,
- <&cru ACLK_JPEG_DECODER_ROOT>,
- <&cru ACLK_IEP2P0>,
- <&cru HCLK_IEP2P0>,
- <&cru ACLK_JPEG_ENCODER0>,
- <&cru HCLK_JPEG_ENCODER0>,
- <&cru ACLK_JPEG_ENCODER1>,
- <&cru HCLK_JPEG_ENCODER1>,
- <&cru ACLK_JPEG_ENCODER2>,
- <&cru HCLK_JPEG_ENCODER2>,
- <&cru ACLK_JPEG_ENCODER3>,
- <&cru HCLK_JPEG_ENCODER3>,
- <&cru ACLK_JPEG_DECODER>,
- <&cru HCLK_JPEG_DECODER>,
- <&cru ACLK_RGA2>,
- <&cru HCLK_RGA2>;
- pm_qos = <&qos_iep>,
- <&qos_jpeg_dec>,
- <&qos_jpeg_enc0>,
- <&qos_jpeg_enc1>,
- <&qos_jpeg_enc2>,
- <&qos_jpeg_enc3>,
- <&qos_rga2_mro>,
- <&qos_rga2_mwo>;
- #address-cells = <1>;
- #size-cells = <0>;
- #power-domain-cells = <0>;
-
-
- power-domain@RK3588_PD_AV1 {
- reg = <RK3588_PD_AV1>;
- clocks = <&cru PCLK_AV1>,
- <&cru ACLK_AV1>,
- <&cru HCLK_VDPU_ROOT>;
- pm_qos = <&qos_av1>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_RKVDEC0 {
- reg = <RK3588_PD_RKVDEC0>;
- clocks = <&cru HCLK_RKVDEC0>,
- <&cru HCLK_VDPU_ROOT>,
- <&cru ACLK_VDPU_ROOT>,
- <&cru ACLK_RKVDEC0>;
- pm_qos = <&qos_rkvdec0>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_RKVDEC1 {
- reg = <RK3588_PD_RKVDEC1>;
- clocks = <&cru HCLK_RKVDEC1>,
- <&cru HCLK_VDPU_ROOT>,
- <&cru ACLK_VDPU_ROOT>;
- pm_qos = <&qos_rkvdec1>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_RGA30 {
- reg = <RK3588_PD_RGA30>;
- clocks = <&cru ACLK_RGA3_0>,
- <&cru HCLK_RGA3_0>;
- pm_qos = <&qos_rga3_0>;
- #power-domain-cells = <0>;
- };
- };
- power-domain@RK3588_PD_VOP {
- reg = <RK3588_PD_VOP>;
- clocks = <&cru PCLK_VOP_ROOT>,
- <&cru HCLK_VOP_ROOT>,
- <&cru ACLK_VOP>;
- pm_qos = <&qos_vop_m0>,
- <&qos_vop_m1>;
- #address-cells = <1>;
- #size-cells = <0>;
- #power-domain-cells = <0>;
-
- power-domain@RK3588_PD_VO0 {
- reg = <RK3588_PD_VO0>;
- clocks = <&cru PCLK_VO0_ROOT>,
- <&cru PCLK_VO0_S_ROOT>,
- <&cru HCLK_VO0_S_ROOT>,
- <&cru ACLK_VO0_ROOT>,
- <&cru HCLK_HDCP0>,
- <&cru ACLK_HDCP0>,
- <&cru HCLK_VOP_ROOT>;
- pm_qos = <&qos_hdcp0>;
- #power-domain-cells = <0>;
- };
- };
- power-domain@RK3588_PD_VO1 {
- reg = <RK3588_PD_VO1>;
- clocks = <&cru PCLK_VO1_ROOT>,
- <&cru PCLK_VO1_S_ROOT>,
- <&cru HCLK_VO1_S_ROOT>,
- <&cru HCLK_HDCP1>,
- <&cru ACLK_HDCP1>,
- <&cru ACLK_HDMIRX_ROOT>,
- <&cru HCLK_VO1USB_TOP_ROOT>;
- pm_qos = <&qos_hdcp1>,
- <&qos_hdmirx>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_VI {
- reg = <RK3588_PD_VI>;
- clocks = <&cru HCLK_VI_ROOT>,
- <&cru PCLK_VI_ROOT>,
- <&cru HCLK_ISP0>,
- <&cru ACLK_ISP0>,
- <&cru HCLK_VICAP>,
- <&cru ACLK_VICAP>;
- pm_qos = <&qos_isp0_mro>,
- <&qos_isp0_mwo>,
- <&qos_vicap_m0>,
- <&qos_vicap_m1>;
- #address-cells = <1>;
- #size-cells = <0>;
- #power-domain-cells = <0>;
-
- power-domain@RK3588_PD_ISP1 {
- reg = <RK3588_PD_ISP1>;
- clocks = <&cru HCLK_ISP1>,
- <&cru ACLK_ISP1>,
- <&cru HCLK_VI_ROOT>,
- <&cru PCLK_VI_ROOT>;
- pm_qos = <&qos_isp1_mwo>,
- <&qos_isp1_mro>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_FEC {
- reg = <RK3588_PD_FEC>;
- clocks = <&cru HCLK_FISHEYE0>,
- <&cru ACLK_FISHEYE0>,
- <&cru HCLK_FISHEYE1>,
- <&cru ACLK_FISHEYE1>,
- <&cru PCLK_VI_ROOT>;
- pm_qos = <&qos_fisheye0>,
- <&qos_fisheye1>;
- #power-domain-cells = <0>;
- };
- };
- power-domain@RK3588_PD_RGA31 {
- reg = <RK3588_PD_RGA31>;
- clocks = <&cru HCLK_RGA3_1>,
- <&cru ACLK_RGA3_1>;
- pm_qos = <&qos_rga3_1>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_USB {
- reg = <RK3588_PD_USB>;
- clocks = <&cru PCLK_PHP_ROOT>,
- <&cru ACLK_USB_ROOT>,
- <&cru ACLK_USB>,
- <&cru HCLK_USB_ROOT>,
- <&cru HCLK_HOST0>,
- <&cru HCLK_HOST_ARB0>,
- <&cru HCLK_HOST1>,
- <&cru HCLK_HOST_ARB1>;
- pm_qos = <&qos_usb3_0>,
- <&qos_usb3_1>,
- <&qos_usb2host_0>,
- <&qos_usb2host_1>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_GMAC {
- reg = <RK3588_PD_GMAC>;
- clocks = <&cru PCLK_PHP_ROOT>,
- <&cru ACLK_PCIE_ROOT>,
- <&cru ACLK_PHP_ROOT>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_PCIE {
- reg = <RK3588_PD_PCIE>;
- clocks = <&cru PCLK_PHP_ROOT>,
- <&cru ACLK_PCIE_ROOT>,
- <&cru ACLK_PHP_ROOT>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_SDIO {
- reg = <RK3588_PD_SDIO>;
- clocks = <&cru HCLK_SDIO>,
- <&cru HCLK_NVM_ROOT>;
- pm_qos = <&qos_sdio>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_AUDIO {
- reg = <RK3588_PD_AUDIO>;
- clocks = <&cru HCLK_AUDIO_ROOT>,
- <&cru PCLK_AUDIO_ROOT>;
- #power-domain-cells = <0>;
- };
- power-domain@RK3588_PD_SDMMC {
- reg = <RK3588_PD_SDMMC>;
- pm_qos = <&qos_sdmmc>;
- #power-domain-cells = <0>;
- };
- };
- };
-
- i2s4_8ch: i2s@fddc0000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddc0000 0x0 0x1000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 0>;
- dma-names = "tx";
- power-domains = <&power RK3588_PD_VO0>;
- resets = <&cru SRST_M_I2S4_8CH_TX>;
- reset-names = "tx-m";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s5_8ch: i2s@fddf0000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddf0000 0x0 0x1000>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 2>;
- dma-names = "tx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_I2S5_8CH_TX>;
- reset-names = "tx-m";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s9_8ch: i2s@fddfc000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddfc000 0x0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac2 23>;
- dma-names = "rx";
- power-domains = <&power RK3588_PD_VO1>;
- resets = <&cru SRST_M_I2S9_8CH_RX>;
- reset-names = "rx-m";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- qos_gpu_m0: qos@fdf35000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf35000 0x0 0x20>;
- };
-
- qos_gpu_m1: qos@fdf35200 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf35200 0x0 0x20>;
- };
-
- qos_gpu_m2: qos@fdf35400 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf35400 0x0 0x20>;
- };
-
- qos_gpu_m3: qos@fdf35600 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf35600 0x0 0x20>;
- };
-
- qos_rga3_1: qos@fdf36000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf36000 0x0 0x20>;
- };
-
- qos_sdio: qos@fdf39000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf39000 0x0 0x20>;
- };
-
- qos_sdmmc: qos@fdf3d800 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf3d800 0x0 0x20>;
- };
-
- qos_usb3_1: qos@fdf3e000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf3e000 0x0 0x20>;
- };
-
- qos_usb3_0: qos@fdf3e200 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf3e200 0x0 0x20>;
- };
-
- qos_usb2host_0: qos@fdf3e400 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf3e400 0x0 0x20>;
- };
-
- qos_usb2host_1: qos@fdf3e600 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf3e600 0x0 0x20>;
- };
-
- qos_fisheye0: qos@fdf40000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf40000 0x0 0x20>;
- };
-
- qos_fisheye1: qos@fdf40200 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf40200 0x0 0x20>;
- };
-
- qos_isp0_mro: qos@fdf40400 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf40400 0x0 0x20>;
- };
-
- qos_isp0_mwo: qos@fdf40500 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf40500 0x0 0x20>;
- };
-
- qos_vicap_m0: qos@fdf40600 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf40600 0x0 0x20>;
- };
-
- qos_vicap_m1: qos@fdf40800 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf40800 0x0 0x20>;
- };
-
- qos_isp1_mwo: qos@fdf41000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf41000 0x0 0x20>;
- };
-
- qos_isp1_mro: qos@fdf41100 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf41100 0x0 0x20>;
- };
-
- qos_rkvenc0_m0ro: qos@fdf60000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf60000 0x0 0x20>;
- };
-
- qos_rkvenc0_m1ro: qos@fdf60200 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf60200 0x0 0x20>;
- };
-
- qos_rkvenc0_m2wo: qos@fdf60400 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf60400 0x0 0x20>;
- };
-
- qos_rkvenc1_m0ro: qos@fdf61000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf61000 0x0 0x20>;
- };
-
- qos_rkvenc1_m1ro: qos@fdf61200 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf61200 0x0 0x20>;
- };
-
- qos_rkvenc1_m2wo: qos@fdf61400 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf61400 0x0 0x20>;
- };
-
- qos_rkvdec0: qos@fdf62000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf62000 0x0 0x20>;
- };
-
- qos_rkvdec1: qos@fdf63000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf63000 0x0 0x20>;
- };
-
- qos_av1: qos@fdf64000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf64000 0x0 0x20>;
- };
-
- qos_iep: qos@fdf66000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf66000 0x0 0x20>;
- };
-
- qos_jpeg_dec: qos@fdf66200 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf66200 0x0 0x20>;
- };
-
- qos_jpeg_enc0: qos@fdf66400 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf66400 0x0 0x20>;
- };
-
- qos_jpeg_enc1: qos@fdf66600 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf66600 0x0 0x20>;
- };
-
- qos_jpeg_enc2: qos@fdf66800 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf66800 0x0 0x20>;
- };
-
- qos_jpeg_enc3: qos@fdf66a00 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf66a00 0x0 0x20>;
- };
-
- qos_rga2_mro: qos@fdf66c00 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf66c00 0x0 0x20>;
- };
-
- qos_rga2_mwo: qos@fdf66e00 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf66e00 0x0 0x20>;
- };
-
- qos_rga3_0: qos@fdf67000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf67000 0x0 0x20>;
- };
-
- qos_vdpu: qos@fdf67200 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf67200 0x0 0x20>;
- };
-
- qos_npu1: qos@fdf70000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf70000 0x0 0x20>;
- };
-
- qos_npu2: qos@fdf71000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf71000 0x0 0x20>;
- };
-
- qos_npu0_mwr: qos@fdf72000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf72000 0x0 0x20>;
- };
-
- qos_npu0_mro: qos@fdf72200 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf72200 0x0 0x20>;
- };
-
- qos_mcu_npu: qos@fdf72400 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf72400 0x0 0x20>;
- };
-
- qos_hdcp0: qos@fdf80000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf80000 0x0 0x20>;
- };
-
- qos_hdcp1: qos@fdf81000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf81000 0x0 0x20>;
- };
-
- qos_hdmirx: qos@fdf81200 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf81200 0x0 0x20>;
- };
-
- qos_vop_m0: qos@fdf82000 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf82000 0x0 0x20>;
- };
-
- qos_vop_m1: qos@fdf82200 {
- compatible = "rockchip,rk3588-qos", "syscon";
- reg = <0x0 0xfdf82200 0x0 0x20>;
- };
-
- pcie2x1l1: pcie@fe180000 {
- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
- bus-range = <0x30 0x3f>;
- clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
- <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
- <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux", "pipe";
- device_type = "pci";
- interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
- <0 0 0 2 &pcie2x1l1_intc 1>,
- <0 0 0 3 &pcie2x1l1_intc 2>,
- <0 0 0 4 &pcie2x1l1_intc 3>;
- linux,pci-domain = <3>;
- max-link-speed = <2>;
- msi-map = <0x3000 &its0 0x3000 0x1000>;
- num-lanes = <1>;
- phys = <&combphy2_psu PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3588_PD_PCIE>;
- ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
- <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
- reg = <0xa 0x40c00000 0x0 0x00400000>,
- <0x0 0xfe180000 0x0 0x00010000>,
- <0x0 0xf3000000 0x0 0x00100000>;
- reg-names = "dbi", "apb", "config";
- resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
- reset-names = "pwr", "pipe";
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie2x1l1_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
- };
- };
-
- pcie2x1l2: pcie@fe190000 {
- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
- bus-range = <0x40 0x4f>;
- clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
- <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
- <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux", "pipe";
- device_type = "pci";
- interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
- <0 0 0 2 &pcie2x1l2_intc 1>,
- <0 0 0 3 &pcie2x1l2_intc 2>,
- <0 0 0 4 &pcie2x1l2_intc 3>;
- linux,pci-domain = <4>;
- max-link-speed = <2>;
- msi-map = <0x4000 &its0 0x4000 0x1000>;
- num-lanes = <1>;
- phys = <&combphy0_ps PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3588_PD_PCIE>;
- ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
- <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
- reg = <0xa 0x41000000 0x0 0x00400000>,
- <0x0 0xfe190000 0x0 0x00010000>,
- <0x0 0xf4000000 0x0 0x00100000>;
- reg-names = "dbi", "apb", "config";
- resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
- reset-names = "pwr", "pipe";
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie2x1l2_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
- };
- };
-
- dfi: dfi@fe060000 {
- reg = <0x00 0xfe060000 0x00 0x10000>;
- compatible = "rockchip,rk3588-dfi";
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
- rockchip,pmu = <&pmu1grf>;
- };
-
- gmac1: ethernet@fe1c0000 {
- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
- reg = <0x0 0xfe1c0000 0x0 0x10000>;
- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "macirq", "eth_wake_irq";
- clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
- <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
- <&cru CLK_GMAC1_PTP_REF>;
- clock-names = "stmmaceth", "clk_mac_ref",
- "pclk_mac", "aclk_mac",
- "ptp_ref";
- power-domains = <&power RK3588_PD_GMAC>;
- resets = <&cru SRST_A_GMAC1>;
- reset-names = "stmmaceth";
- rockchip,grf = <&sys_grf>;
- rockchip,php-grf = <&php_grf>;
- snps,axi-config = <&gmac1_stmmac_axi_setup>;
- snps,mixed-burst;
- snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
- snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
- snps,tso;
- status = "disabled";
-
- mdio1: mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- };
-
- gmac1_stmmac_axi_setup: stmmac-axi-config {
- snps,blen = <0 0 0 0 16 8 4>;
- snps,wr_osr_lmt = <4>;
- snps,rd_osr_lmt = <8>;
- };
-
- gmac1_mtl_rx_setup: rx-queues-config {
- snps,rx-queues-to-use = <2>;
- queue0 {};
- queue1 {};
- };
-
- gmac1_mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <2>;
- queue0 {};
- queue1 {};
- };
- };
-
- sata0: sata@fe210000 {
- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
- reg = <0 0xfe210000 0 0x1000>;
- interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
- <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
- <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
- clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
- ports-implemented = <0x1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- sata-port@0 {
- reg = <0>;
- hba-port-cap = <HBA_PORT_FBSCP>;
- phys = <&combphy0_ps PHY_TYPE_SATA>;
- phy-names = "sata-phy";
- snps,rx-ts-max = <32>;
- snps,tx-ts-max = <32>;
- };
- };
-
- sata2: sata@fe230000 {
- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
- reg = <0 0xfe230000 0 0x1000>;
- interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
- <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
- <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
- clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
- ports-implemented = <0x1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- sata-port@0 {
- reg = <0>;
- hba-port-cap = <HBA_PORT_FBSCP>;
- phys = <&combphy2_psu PHY_TYPE_SATA>;
- phy-names = "sata-phy";
- snps,rx-ts-max = <32>;
- snps,tx-ts-max = <32>;
- };
- };
-
- sfc: spi@fe2b0000 {
- compatible = "rockchip,sfc";
- reg = <0x0 0xfe2b0000 0x0 0x4000>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
- clock-names = "clk_sfc", "hclk_sfc";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sdmmc: mmc@fe2c0000 {
- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xfe2c0000 0x0 0x4000>;
- interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <200000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
- power-domains = <&power RK3588_PD_SDMMC>;
- status = "disabled";
- };
-
- sdio: mmc@fe2d0000 {
- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x00 0xfe2d0000 0x00 0x4000>;
- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <200000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdiom1_pins>;
- power-domains = <&power RK3588_PD_SDIO>;
- status = "disabled";
- };
-
- sdhci: mmc@fe2e0000 {
- compatible = "rockchip,rk3588-dwcmshc";
- reg = <0x0 0xfe2e0000 0x0 0x10000>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
- assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
- assigned-clock-rates = <200000000>, <24000000>, <200000000>;
- clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
- <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
- <&cru TMCLK_EMMC>;
- clock-names = "core", "bus", "axi", "block", "timer";
- max-frequency = <200000000>;
- pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
- <&emmc_cmd>, <&emmc_data_strobe>;
- pinctrl-names = "default";
- resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
- <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
- <&cru SRST_T_EMMC>;
- reset-names = "core", "bus", "axi", "block", "timer";
- status = "disabled";
- };
-
- i2s0_8ch: i2s@fe470000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfe470000 0x0 0x1000>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
- dmas = <&dmac0 0>, <&dmac0 1>;
- dma-names = "tx", "rx";
- power-domains = <&power RK3588_PD_AUDIO>;
- resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
- reset-names = "tx-m", "rx-m";
- rockchip,trcm-sync-tx-only;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_lrck
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdi1
- &i2s0_sdi2
- &i2s0_sdi3
- &i2s0_sdo0
- &i2s0_sdo1
- &i2s0_sdo2
- &i2s0_sdo3>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s1_8ch: i2s@fe480000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfe480000 0x0 0x1000>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
- clock-names = "mclk_tx", "mclk_rx", "hclk";
- dmas = <&dmac0 2>, <&dmac0 3>;
- dma-names = "tx", "rx";
- resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
- reset-names = "tx-m", "rx-m";
- rockchip,trcm-sync-tx-only;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_lrck
- &i2s1m0_sclk
- &i2s1m0_sdi0
- &i2s1m0_sdi1
- &i2s1m0_sdi2
- &i2s1m0_sdi3
- &i2s1m0_sdo0
- &i2s1m0_sdo1
- &i2s1m0_sdo2
- &i2s1m0_sdo3>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s2_2ch: i2s@fe490000 {
- compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xfe490000 0x0 0x1000>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
- clock-names = "i2s_clk", "i2s_hclk";
- assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac1 0>, <&dmac1 1>;
- dma-names = "tx", "rx";
- power-domains = <&power RK3588_PD_AUDIO>;
- rockchip,trcm-sync-tx-only;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s2m1_lrck
- &i2s2m1_sclk
- &i2s2m1_sdi
- &i2s2m1_sdo>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- i2s3_2ch: i2s@fe4a0000 {
- compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xfe4a0000 0x0 0x1000>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
- clock-names = "i2s_clk", "i2s_hclk";
- assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
- assigned-clock-parents = <&cru PLL_AUPLL>;
- dmas = <&dmac1 2>, <&dmac1 3>;
- dma-names = "tx", "rx";
- power-domains = <&power RK3588_PD_AUDIO>;
- rockchip,trcm-sync-tx-only;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s3_lrck
- &i2s3_sclk
- &i2s3_sdi
- &i2s3_sdo>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- gic: interrupt-controller@fe600000 {
- compatible = "arm,gic-v3";
- reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
- <0x0 0xfe680000 0 0x100000>; /* GICR */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-controller;
- mbi-alias = <0x0 0xfe610000>;
- mbi-ranges = <424 56>;
- msi-controller;
- ranges;
- #address-cells = <2>;
- #interrupt-cells = <4>;
- #size-cells = <2>;
-
- its0: msi-controller@fe640000 {
- compatible = "arm,gic-v3-its";
- reg = <0x0 0xfe640000 0x0 0x20000>;
- msi-controller;
- #msi-cells = <1>;
- };
-
- its1: msi-controller@fe660000 {
- compatible = "arm,gic-v3-its";
- reg = <0x0 0xfe660000 0x0 0x20000>;
- msi-controller;
- #msi-cells = <1>;
- };
-
- ppi-partitions {
- ppi_partition0: interrupt-partition-0 {
- affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
- };
-
- ppi_partition1: interrupt-partition-1 {
- affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
- };
- };
- };
-
- dmac0: dma-controller@fea10000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xfea10000 0x0 0x4000>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_DMAC0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
-
- dmac1: dma-controller@fea30000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xfea30000 0x0 0x4000>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_DMAC1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
-
- i2c1: i2c@fea90000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfea90000 0x0 0x1000>;
- clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-0 = <&i2c1m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@feaa0000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfeaa0000 0x0 0x1000>;
- clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-0 = <&i2c2m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@feab0000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfeab0000 0x0 0x1000>;
- clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-0 = <&i2c3m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@feac0000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfeac0000 0x0 0x1000>;
- clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-0 = <&i2c4m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c5: i2c@fead0000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfead0000 0x0 0x1000>;
- clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-0 = <&i2c5m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- timer0: timer@feae0000 {
- compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
- reg = <0x0 0xfeae0000 0x0 0x20>;
- interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
- clock-names = "pclk", "timer";
- };
-
- wdt: watchdog@feaf0000 {
- compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
- reg = <0x0 0xfeaf0000 0x0 0x100>;
- clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
- clock-names = "tclk", "pclk";
- interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
- };
-
- spi0: spi@feb00000 {
- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xfeb00000 0x0 0x1000>;
- interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac0 14>, <&dmac0 15>;
- dma-names = "tx", "rx";
- num-cs = <2>;
- pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@feb10000 {
- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xfeb10000 0x0 0x1000>;
- interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac0 16>, <&dmac0 17>;
- dma-names = "tx", "rx";
- num-cs = <2>;
- pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi2: spi@feb20000 {
- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xfeb20000 0x0 0x1000>;
- interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac1 15>, <&dmac1 16>;
- dma-names = "tx", "rx";
- num-cs = <2>;
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi3: spi@feb30000 {
- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xfeb30000 0x0 0x1000>;
- interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac1 17>, <&dmac1 18>;
- dma-names = "tx", "rx";
- num-cs = <2>;
- pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart1: serial@feb40000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeb40000 0x0 0x100>;
- interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 8>, <&dmac0 9>;
- dma-names = "tx", "rx";
- pinctrl-0 = <&uart1m1_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart2: serial@feb50000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeb50000 0x0 0x100>;
- interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 10>, <&dmac0 11>;
- dma-names = "tx", "rx";
- pinctrl-0 = <&uart2m1_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart3: serial@feb60000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeb60000 0x0 0x100>;
- interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac0 12>, <&dmac0 13>;
- dma-names = "tx", "rx";
- pinctrl-0 = <&uart3m1_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart4: serial@feb70000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeb70000 0x0 0x100>;
- interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac1 9>, <&dmac1 10>;
- dma-names = "tx", "rx";
- pinctrl-0 = <&uart4m1_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart5: serial@feb80000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeb80000 0x0 0x100>;
- interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac1 11>, <&dmac1 12>;
- dma-names = "tx", "rx";
- pinctrl-0 = <&uart5m1_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart6: serial@feb90000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeb90000 0x0 0x100>;
- interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac1 13>, <&dmac1 14>;
- dma-names = "tx", "rx";
- pinctrl-0 = <&uart6m1_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart7: serial@feba0000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfeba0000 0x0 0x100>;
- interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac2 7>, <&dmac2 8>;
- dma-names = "tx", "rx";
- pinctrl-0 = <&uart7m1_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart8: serial@febb0000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfebb0000 0x0 0x100>;
- interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac2 9>, <&dmac2 10>;
- dma-names = "tx", "rx";
- pinctrl-0 = <&uart8m1_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart9: serial@febc0000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfebc0000 0x0 0x100>;
- interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac2 11>, <&dmac2 12>;
- dma-names = "tx", "rx";
- pinctrl-0 = <&uart9m1_xfer>;
- pinctrl-names = "default";
- reg-io-width = <4>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- pwm4: pwm@febd0000 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebd0000 0x0 0x10>;
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm4m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm5: pwm@febd0010 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebd0010 0x0 0x10>;
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm5m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm6: pwm@febd0020 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebd0020 0x0 0x10>;
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm6m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm7: pwm@febd0030 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebd0030 0x0 0x10>;
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm7m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm8: pwm@febe0000 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebe0000 0x0 0x10>;
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm8m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm9: pwm@febe0010 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebe0010 0x0 0x10>;
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm9m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm10: pwm@febe0020 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebe0020 0x0 0x10>;
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm10m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm11: pwm@febe0030 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebe0030 0x0 0x10>;
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm11m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm12: pwm@febf0000 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebf0000 0x0 0x10>;
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm12m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm13: pwm@febf0010 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebf0010 0x0 0x10>;
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm13m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm14: pwm@febf0020 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebf0020 0x0 0x10>;
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm14m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm15: pwm@febf0030 {
- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
- reg = <0x0 0xfebf0030 0x0 0x10>;
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
- clock-names = "pwm", "pclk";
- pinctrl-0 = <&pwm15m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- tsadc: tsadc@fec00000 {
- compatible = "rockchip,rk3588-tsadc";
- reg = <0x0 0xfec00000 0x0 0x400>;
- interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
- clock-names = "tsadc", "apb_pclk";
- assigned-clocks = <&cru CLK_TSADC>;
- assigned-clock-rates = <2000000>;
- resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
- reset-names = "tsadc-apb", "tsadc";
- rockchip,hw-tshut-temp = <120000>;
- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
- pinctrl-0 = <&tsadc_gpio_func>;
- pinctrl-1 = <&tsadc_shut>;
- pinctrl-names = "gpio", "otpout";
- #thermal-sensor-cells = <1>;
- status = "disabled";
- };
-
- saradc: adc@fec10000 {
- compatible = "rockchip,rk3588-saradc";
- reg = <0x0 0xfec10000 0x0 0x10000>;
- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
- #io-channel-cells = <1>;
- clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
- clock-names = "saradc", "apb_pclk";
- resets = <&cru SRST_P_SARADC>;
- reset-names = "saradc-apb";
- status = "disabled";
- };
-
- i2c6: i2c@fec80000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfec80000 0x0 0x1000>;
- clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-0 = <&i2c6m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c7: i2c@fec90000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfec90000 0x0 0x1000>;
- clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-0 = <&i2c7m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c8: i2c@feca0000 {
- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
- reg = <0x0 0xfeca0000 0x0 0x1000>;
- clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
- clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-0 = <&i2c8m0_xfer>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi4: spi@fecb0000 {
- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xfecb0000 0x0 0x1000>;
- interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
- clock-names = "spiclk", "apb_pclk";
- dmas = <&dmac2 13>, <&dmac2 14>;
- dma-names = "tx", "rx";
- num-cs = <2>;
- pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- otp: efuse@fecc0000 {
- compatible = "rockchip,rk3588-otp";
- reg = <0x0 0xfecc0000 0x0 0x400>;
- clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
- <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
- clock-names = "otp", "apb_pclk", "phy", "arb";
- resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
- <&cru SRST_OTPC_ARB>;
- reset-names = "otp", "apb", "arb";
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpu_code: cpu-code@2 {
- reg = <0x02 0x2>;
- };
-
- otp_id: id@7 {
- reg = <0x07 0x10>;
- };
-
- cpub0_leakage: cpu-leakage@17 {
- reg = <0x17 0x1>;
- };
-
- cpub1_leakage: cpu-leakage@18 {
- reg = <0x18 0x1>;
- };
-
- cpul_leakage: cpu-leakage@19 {
- reg = <0x19 0x1>;
- };
-
- log_leakage: log-leakage@1a {
- reg = <0x1a 0x1>;
- };
-
- gpu_leakage: gpu-leakage@1b {
- reg = <0x1b 0x1>;
- };
-
- otp_cpu_version: cpu-version@1c {
- reg = <0x1c 0x1>;
- bits = <3 3>;
- };
-
- npu_leakage: npu-leakage@28 {
- reg = <0x28 0x1>;
- };
-
- codec_leakage: codec-leakage@29 {
- reg = <0x29 0x1>;
- };
- };
-
- dmac2: dma-controller@fed10000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xfed10000 0x0 0x4000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_DMAC2>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
-
- combphy0_ps: phy@fee00000 {
- compatible = "rockchip,rk3588-naneng-combphy";
- reg = <0x0 0xfee00000 0x0 0x100>;
- clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
- <&cru PCLK_PHP_ROOT>;
- clock-names = "ref", "apb", "pipe";
- assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
- assigned-clock-rates = <100000000>;
- #phy-cells = <1>;
- resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
- reset-names = "phy", "apb";
- rockchip,pipe-grf = <&php_grf>;
- rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
- status = "disabled";
- };
-
- combphy2_psu: phy@fee20000 {
- compatible = "rockchip,rk3588-naneng-combphy";
- reg = <0x0 0xfee20000 0x0 0x100>;
- clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
- <&cru PCLK_PHP_ROOT>;
- clock-names = "ref", "apb", "pipe";
- assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
- assigned-clock-rates = <100000000>;
- #phy-cells = <1>;
- resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
- reset-names = "phy", "apb";
- rockchip,pipe-grf = <&php_grf>;
- rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
- status = "disabled";
- };
-
- system_sram2: sram@ff001000 {
- compatible = "mmio-sram";
- reg = <0x0 0xff001000 0x0 0xef000>;
- ranges = <0x0 0x0 0xff001000 0xef000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3588-pinctrl";
- ranges;
- rockchip,grf = <&ioc>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- gpio0: gpio@fd8a0000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfd8a0000 0x0 0x100>;
- interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 32>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@fec20000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfec20000 0x0 0x100>;
- interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 32 32>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@fec30000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfec30000 0x0 0x100>;
- interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 64 32>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@fec40000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfec40000 0x0 0x100>;
- interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 96 32>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@fec50000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xfec50000 0x0 0x100>;
- interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 128 32>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
- };
-
- av1d: video-codec@fdc70000 {
- compatible = "rockchip,rk3588-av1-vpu";
- reg = <0x0 0xfdc70000 0x0 0x800>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vdpu";
- assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
- assigned-clock-rates = <400000000>, <400000000>;
- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
- clock-names = "aclk", "hclk";
- power-domains = <&power RK3588_PD_AV1>;
- resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
- };
-};
-
-#include "rk3588s-pinctrl.dtsi"
#clock-cells = <0>;
};
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&hym8563>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ };
+
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
status = "okay";
};
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-
-#include "rv1108.dtsi"
-
-/ {
- model = "Elgin RV1108 R1 board";
- compatible = "elgin,rv1108-elgin", "rockchip,rv1108";
-
- memory@60000000 {
- device_type = "memory";
- reg = <0x60000000 0x08000000>;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-};
-
-&emmc {
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
- bus-width = <8>;
- cap-mmc-highspeed;
- disable-wp;
- non-removable;
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-
- u2phy_otg: otg-port {
- status = "okay";
- };
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2m0_xfer_pullup>;
- status = "okay";
-};
-
-&usb20_otg {
- status = "okay";
-};
-
-&pinctrl {
- uart2m0 {
- uart2m0_xfer_pullup: uart2m0-xfer-pullup {
- rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
- <2 RK_PD1 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-
-#include "rv1108.dtsi"
-
-/ {
- model = "Rockchip RV1108 Evaluation board";
- compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
-
- memory@60000000 {
- device_type = "memory";
- reg = <0x60000000 0x08000000>;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- vcc5v0_otg: vcc5v0-otg-drv {
- compatible = "regulator-fixed";
- enable-active-high;
- regulator-name = "vcc5v0_otg";
- gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-};
-
-&gmac {
- status = "okay";
- clock_in_out = <0>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>;
-};
-
-&saradc {
- status = "okay";
-};
-
-&sfc {
- status = "okay";
- flash@0 {
- compatible = "gd25q256","jedec,spi-nor";
- reg = <0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- spi-max-frequency = <96000000>;
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usb20_otg {
- vbus-supply = <&vcc5v0_otg>;
- status = "okay";
-};
-
-&usb_host_ehci {
- status = "okay";
-};
-
-&usb_host_ohci {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/rv1108-cru.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- compatible = "rockchip,rv1108";
-
- interrupt-parent = <&gic>;
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- spi0 = &sfc;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@f00 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf00>;
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
- clock-frequency = <24000000>;
- };
-
- xin24m: oscillator {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- #clock-cells = <0>;
- };
-
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pdma: pdma@102a0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x102a0000 0x4000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- arm,pl330-broken-no-flushp;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
- };
- };
-
- bus_intmem@10080000 {
- compatible = "mmio-sram";
- reg = <0x10080000 0x2000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x10080000 0x2000>;
- };
-
- uart2: serial@10210000 {
- compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
- reg = <0x10210000 0x100>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2m0_xfer>;
- status = "disabled";
- };
-
- uart1: serial@10220000 {
- compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
- reg = <0x10220000 0x100>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer>;
- status = "disabled";
- };
-
- uart0: serial@10230000 {
- compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
- reg = <0x10230000 0x100>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- status = "disabled";
- };
-
- grf: syscon@10300000 {
- compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
- reg = <0x10300000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy: usb2-phy@100 {
- compatible = "rockchip,rv1108-usb2phy";
- reg = <0x100 0x0c>;
- clocks = <&cru SCLK_USBPHY>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "usbphy";
- rockchip,usbgrf = <&usbgrf>;
- status = "disabled";
-
- u2phy_otg: otg-port {
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "otg-mux";
- #phy-cells = <0>;
- status = "disabled";
- };
-
- u2phy_host: host-port {
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "linestate";
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
- saradc: saradc@1038c000 {
- compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
- reg = <0x1038c000 0x100>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- #io-channel-cells = <1>;
- clock-frequency = <1000000>;
- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
- clock-names = "saradc", "apb_pclk";
- status = "disabled";
- };
-
- pmugrf: syscon@20060000 {
- compatible = "rockchip,rv1108-pmugrf", "syscon";
- reg = <0x20060000 0x1000>;
- };
-
- usbgrf: syscon@202a0000 {
- compatible = "rockchip,rv1108-usbgrf", "syscon";
- reg = <0x202a0000 0x1000>;
- };
-
- cru: clock-controller@20200000 {
- compatible = "rockchip,rv1108-cru";
- reg = <0x20200000 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- emmc: dwmmc@30110000 {
- compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
- clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x30110000 0x4000>;
- status = "disabled";
- };
-
- sdio: dwmmc@30120000 {
- compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
- clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x30120000 0x4000>;
- status = "disabled";
- };
-
- sdmmc: dwmmc@30130000 {
- compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
- clock-freq-min-max = <400000 100000000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x30130000 0x4000>;
- status = "disabled";
- };
-
- usb_host_ehci: usb@30140000 {
- compatible = "generic-ehci";
- reg = <0x30140000 0x20000>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- usb_host_ohci: usb@30160000 {
- compatible = "generic-ohci";
- reg = <0x30160000 0x20000>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- usb20_otg: usb@30180000 {
- compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
- "snps,dwc2";
- reg = <0x30180000 0x40000>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_OTG>;
- clock-names = "otg";
- dr_mode = "otg";
- g-np-tx-fifo-size = <16>;
- g-rx-fifo-size = <280>;
- g-tx-fifo-size = <256 128 128 64 32 16>;
- g-use-dma;
- phys = <&u2phy_otg>;
- phy-names = "usb2-phy";
- status = "disabled";
- };
-
- sfc: sfc@301c0000 {
- compatible = "rockchip,sfc";
- reg = <0x301c0000 0x200>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
- clock-names = "clk_sfc", "hclk_sfc";
- pinctrl-0 = <&sfc_pins>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- gmac: ethernet@30200000 {
- compatible = "rockchip,rv1108-gmac";
- reg = <0x30200000 0x10000>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- rockchip,grf = <&grf>;
- clocks = <&cru SCLK_MAC>,
- <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
- <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
- <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
- clock-names = "stmmaceth",
- "mac_clk_rx", "mac_clk_tx",
- "clk_mac_ref", "clk_mac_refout",
- "aclk_mac", "pclk_mac";
- pinctrl-names = "default";
- pinctrl-0 = <&rmii_pins>;
- phy-mode = "rmii";
- max-speed = <100>;
- status = "disabled";
- };
-
- gic: interrupt-controller@32010000 {
- compatible = "arm,gic-400";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <0>;
-
- reg = <0x32011000 0x1000>,
- <0x32012000 0x1000>,
- <0x32014000 0x2000>,
- <0x32016000 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- pinctrl: pinctrl {
- compatible = "rockchip,rv1108-pinctrl";
- rockchip,grf = <&grf>;
- rockchip,pmu = <&pmugrf>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- gpio0: gpio0@20030000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x20030000 0x100>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio1@10310000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x10310000 0x100>;
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio2@10320000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x10320000 0x100>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio3@10330000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x10330000 0x100>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- pcfg_pull_up: pcfg-pull-up {
- bias-pull-up;
- };
-
- pcfg_pull_down: pcfg-pull-down {
- bias-pull-down;
- };
-
- pcfg_pull_none: pcfg-pull-none {
- bias-disable;
- };
-
- pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
- drive-strength = <8>;
- };
-
- pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
- drive-strength = <12>;
- };
-
- pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
- bias-pull-up;
- drive-strength = <8>;
- };
-
- pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
- drive-strength = <4>;
- };
-
- pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
- bias-pull-up;
- drive-strength = <4>;
- };
-
- pcfg_output_high: pcfg-output-high {
- output-high;
- };
-
- pcfg_output_low: pcfg-output-low {
- output-low;
- };
-
- pcfg_input_high: pcfg-input-high {
- bias-pull-up;
- input-enable;
- };
-
- gmac {
- rmii_pins: rmii-pins {
- rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
- <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
- <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
- <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
- <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
- <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
- <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
- <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
- <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
- <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
- };
- };
-
- i2c1 {
- i2c1_xfer: i2c1-xfer {
- rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
- <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
- };
- };
-
- i2c2m1 {
- i2c2m1_xfer: i2c2m1-xfer {
- rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
- <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
- };
-
- i2c2m1_gpio: i2c2m1-gpio {
- rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
- <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- i2c2m05v {
- i2c2m05v_xfer: i2c2m05v-xfer {
- rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
- <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
- };
-
- i2c2m05v_gpio: i2c2m05v-gpio {
- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
- <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- i2c3 {
- i2c3_xfer: i2c3-xfer {
- rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
- <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
- };
- };
-
- sfc {
- sfc_pins: sfc-pins {
- rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>,
- <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>,
- <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,
- <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>,
- <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
- <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>;
- };
- };
-
- emmc {
- emmc_clk: emmc-clk {
- rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
- };
-
- emmc_cmd: emmc-cmd {
- rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
- };
-
- emmc_pwren: emmc-pwren {
- rockchip,pins = <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
- };
-
- emmc_bus1: emmc-bus1 {
- rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
- };
-
- emmc_bus8: emmc-bus8 {
- rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
- <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
- <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
- <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
- <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
- <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
- <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
- <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
- };
- };
-
- sdmmc {
- sdmmc_clk: sdmmc-clk {
- rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
- };
-
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
- };
-
- sdmmc_cd: sdmmc-cd {
- rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
- };
-
- sdmmc_bus1: sdmmc-bus1 {
- rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
- };
-
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
- <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
- <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
- <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
- };
- };
-
- uart0 {
- uart0_xfer: uart0-xfer {
- rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
- <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
- };
-
- uart0_cts: uart0-cts {
- rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
- };
-
- uart0_rts: uart0-rts {
- rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
- };
-
- uart0_rts_gpio: uart0-rts-gpio {
- rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- uart1 {
- uart1_xfer: uart1-xfer {
- rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
- <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
- };
-
- uart1_cts: uart1-cts {
- rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
- };
-
- uart01rts: uart1-rts {
- rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
-
- uart2m0 {
- uart2m0_xfer: uart2m0-xfer {
- rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
- <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
-
- uart2m1 {
- uart2m1_xfer: uart2m1-xfer {
- rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
- <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
- };
- };
-
- uart2_5v {
- uart2_5v_cts: uart2_5v-cts {
- rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
- };
-
- uart2_5v_rts: uart2_5v-rts {
- rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-edgeble-neu2.dtsi"
-
-/ {
- model = "Edgeble Neu2 IO Board";
- compatible = "edgeble,neural-compute-module-2-io",
- "edgeble,neural-compute-module-2", "rockchip,rv1126";
-
- aliases {
- serial2 = &uart2;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- v3v3_sys: v3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "v3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&gmac {
- assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
- <&cru CLK_GMAC_ETHERNET_OUT>;
- assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
- assigned-clock-rates = <125000000>, <0>, <25000000>;
- clock_in_out = "input";
- phy-handle = <&phy>;
- phy-mode = "rgmii";
- phy-supply = <&vcc_3v3>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>;
- tx_delay = <0x2a>;
- rx_delay = <0x1a>;
- status = "okay";
-};
-
-&mdio {
- phy: ethernet-phy@0 {
- compatible = "ethernet-phy-id001c.c916",
- "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- pinctrl-names = "default";
- pinctrl-0 = <ð_phy_rst>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
- };
-};
-
-&pinctrl {
- ethernet {
- eth_phy_rst: eth-phy-rst {
- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-};
-
-&pwm11 {
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
- rockchip,default-sample-phase = <90>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr104;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/ {
- compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
-
- aliases {
- mmc0 = &emmc;
- };
-
- vccio_flash: vccio-flash-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&flash_vol_sel>;
- regulator-name = "vccio_flash";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- };
-
- sdio_pwrseq: pwrseq-sdio {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk809 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
- bus-width = <8>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>;
- rockchip,default-sample-phase = <90>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vccio_flash>;
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc_buck5>;
- vcc6-supply = <&vcc_buck5>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
-
- regulators {
- vdd_npu_vepu: DCDC_REG1 {
- regulator-name = "vdd_npu_vepu";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <650000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc3v3_sys: DCDC_REG4 {
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_buck5: DCDC_REG5 {
- regulator-name = "vcc_buck5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2200000>;
- regulator-max-microvolt = <2200000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2200000>;
- };
- };
-
- vcc_0v8: LDO_REG1 {
- regulator-name = "vcc_0v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_pmu: LDO_REG2 {
- regulator-name = "vcc1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd0v8_pmu: LDO_REG3 {
- regulator-name = "vcc0v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <800000>;
- };
- };
-
- vcc_1v8: LDO_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_dovdd: LDO_REG5 {
- regulator-name = "vcc_dovdd";
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_dvdd: LDO_REG6 {
- regulator-name = "vcc_dvdd";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_avdd: LDO_REG7 {
- regulator-name = "vcc_avdd";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG8 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: LDO_REG9 {
- regulator-name = "vcc3v3_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_5v0: SWITCH_REG1 {
- regulator-name = "vcc_5v0";
- };
-
- vcc_3v3: SWITCH_REG2 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-};
-
-&pinctrl {
- bt {
- bt_enable: bt-enable {
- rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- flash {
- flash_vol_sel: flash-vol-sel {
- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- wifi {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio0-supply = <&vcc1v8_pmu>;
- pmuio1-supply = <&vcc3v3_sys>;
- vccio1-supply = <&vccio_flash>;
- vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_1v8>;
- vccio4-supply = <&vcc_dovdd>;
- vccio5-supply = <&vcc_1v8>;
- vccio6-supply = <&vcc_1v8>;
- vccio7-supply = <&vcc_dovdd>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sfc {
- pinctrl-names = "default";
- pinctrl-0 = <&fspi_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <1>;
- };
-};
-
-&sdio {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- max-frequency = <100000000>;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
- rockchip,default-sample-phase = <90>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sys>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
- status = "okay";
-
- bluetooth {
- compatible = "qcom,qca9377-bt";
- clocks = <&rk809 1>;
- enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */
- max-speed = <2000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_enable>;
- vddxo-supply = <&vcc3v3_sys>;
- vddio-supply = <&vcc_1v8>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rockchip-pinconf.dtsi"
-
-/*
- * This file is auto generated by pin2dts tool, please keep these code
- * by adding changes at end of this file.
- */
-&pinctrl {
- clk_out_ethernet {
- /omit-if-no-ref/
- clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
- rockchip,pins =
- /* clk_out_ethernet_m1 */
- <2 RK_PC5 2 &pcfg_pull_none>;
- };
- };
- emmc {
- /omit-if-no-ref/
- emmc_rstnout: emmc-rstnout {
- rockchip,pins =
- /* emmc_rstn */
- <1 RK_PA3 2 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- emmc_bus8: emmc-bus8 {
- rockchip,pins =
- /* emmc_d0 */
- <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d1 */
- <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d2 */
- <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d3 */
- <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d4 */
- <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d5 */
- <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d6 */
- <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
- /* emmc_d7 */
- <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- emmc_clk: emmc-clk {
- rockchip,pins =
- /* emmc_clko */
- <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- emmc_cmd: emmc-cmd {
- rockchip,pins =
- /* emmc_cmd */
- <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
- };
- };
- fspi {
- /omit-if-no-ref/
- fspi_pins: fspi-pins {
- rockchip,pins =
- /* fspi_clk */
- <1 RK_PA3 3 &pcfg_pull_down>,
- /* fspi_cs0n */
- <0 RK_PD4 3 &pcfg_pull_up>,
- /* fspi_d0 */
- <1 RK_PA0 3 &pcfg_pull_up>,
- /* fspi_d1 */
- <1 RK_PA1 3 &pcfg_pull_up>,
- /* fspi_d2 */
- <0 RK_PD6 3 &pcfg_pull_up>,
- /* fspi_d3 */
- <1 RK_PA2 3 &pcfg_pull_up>;
- };
- };
- i2c0 {
- /omit-if-no-ref/
- i2c0_xfer: i2c0-xfer {
- rockchip,pins =
- /* i2c0_scl */
- <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
- /* i2c0_sda */
- <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
- };
- };
- i2c2 {
- /omit-if-no-ref/
- i2c2_xfer: i2c2-xfer {
- rockchip,pins =
- /* i2c2_scl */
- <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
- /* i2c2_sda */
- <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
- };
- };
- pwm2 {
- /omit-if-no-ref/
- pwm2m0_pins: pwm2m0-pins {
- rockchip,pins =
- /* pwm2_pin_m0 */
- <0 RK_PC0 3 &pcfg_pull_none>;
- };
- };
- pwm11 {
- /omit-if-no-ref/
- pwm11m0_pins: pwm11m0-pins {
- rockchip,pins =
- /* pwm11_pin_m0 */
- <3 RK_PA7 6 &pcfg_pull_none>;
- };
- };
- rgmii {
- /omit-if-no-ref/
- rgmiim1_miim: rgmiim1-miim {
- rockchip,pins =
- /* rgmii_mdc_m1 */
- <2 RK_PC2 2 &pcfg_pull_none>,
- /* rgmii_mdio_m1 */
- <2 RK_PC1 2 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- rgmiim1_rxer: rgmiim1-rxer {
- rockchip,pins =
- /* rgmii_rxer_m1 */
- <2 RK_PC0 2 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- rgmiim1_bus2: rgmiim1-bus2 {
- rockchip,pins =
- /* rgmii_rxd0_m1 */
- <2 RK_PB5 2 &pcfg_pull_none>,
- /* rgmii_rxd1_m1 */
- <2 RK_PB6 2 &pcfg_pull_none>,
- /* rgmii_rxdv_m1 */
- <2 RK_PB4 2 &pcfg_pull_none>,
- /* rgmii_txd0_m1 */
- <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
- /* rgmii_txd1_m1 */
- <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
- /* rgmii_txen_m1 */
- <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
- };
- /omit-if-no-ref/
- rgmiim1_bus4: rgmiim1-bus4 {
- rockchip,pins =
- /* rgmii_rxclk_m1 */
- <2 RK_PD3 2 &pcfg_pull_none>,
- /* rgmii_rxd2_m1 */
- <2 RK_PC7 2 &pcfg_pull_none>,
- /* rgmii_rxd3_m1 */
- <2 RK_PD0 2 &pcfg_pull_none>,
- /* rgmii_txclk_m1 */
- <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
- /* rgmii_txd2_m1 */
- <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
- /* rgmii_txd3_m1 */
- <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>;
- };
- /omit-if-no-ref/
- rgmiim1_mclkinout: rgmiim1-mclkinout {
- rockchip,pins =
- /* rgmii_clk_m1 */
- <2 RK_PB7 2 &pcfg_pull_none>;
- };
- };
- sdmmc0 {
- /omit-if-no-ref/
- sdmmc0_bus4: sdmmc0-bus4 {
- rockchip,pins =
- /* sdmmc0_d0 */
- <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc0_d1 */
- <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc0_d2 */
- <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc0_d3 */
- <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- sdmmc0_clk: sdmmc0-clk {
- rockchip,pins =
- /* sdmmc0_clk */
- <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- sdmmc0_cmd: sdmmc0-cmd {
- rockchip,pins =
- /* sdmmc0_cmd */
- <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- sdmmc0_det: sdmmc0-det {
- rockchip,pins =
- <0 RK_PA3 1 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- sdmmc0_pwr: sdmmc0-pwr {
- rockchip,pins =
- <0 RK_PC0 1 &pcfg_pull_none>;
- };
- };
- sdmmc1 {
- /omit-if-no-ref/
- sdmmc1_bus4: sdmmc1-bus4 {
- rockchip,pins =
- /* sdmmc1_d0 */
- <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc1_d1 */
- <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc1_d2 */
- <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
- /* sdmmc1_d3 */
- <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- sdmmc1_clk: sdmmc1-clk {
- rockchip,pins =
- /* sdmmc1_clk */
- <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- sdmmc1_cmd: sdmmc1-cmd {
- rockchip,pins =
- /* sdmmc1_cmd */
- <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
- };
- /omit-if-no-ref/
- sdmmc1_det: sdmmc1-det {
- rockchip,pins =
- <1 RK_PD0 2 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- sdmmc1_pwr: sdmmc1-pwr {
- rockchip,pins =
- <1 RK_PD1 2 &pcfg_pull_none>;
- };
- };
- uart0 {
- /omit-if-no-ref/
- uart0_xfer: uart0-xfer {
- rockchip,pins =
- /* uart0_rx */
- <1 RK_PC2 1 &pcfg_pull_up>,
- /* uart0_tx */
- <1 RK_PC3 1 &pcfg_pull_up>;
- };
- /omit-if-no-ref/
- uart0_ctsn: uart0-ctsn {
- rockchip,pins =
- <1 RK_PC1 1 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- uart0_rtsn: uart0-rtsn {
- rockchip,pins =
- <1 RK_PC0 1 &pcfg_pull_none>;
- };
- /omit-if-no-ref/
- uart0_rtsn_gpio: uart0-rts-pin {
- rockchip,pins =
- <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
- uart1 {
- /omit-if-no-ref/
- uart1m0_xfer: uart1m0-xfer {
- rockchip,pins =
- /* uart1_rx_m0 */
- <0 RK_PB7 2 &pcfg_pull_up>,
- /* uart1_tx_m0 */
- <0 RK_PB6 2 &pcfg_pull_up>;
- };
- };
- uart2 {
- /omit-if-no-ref/
- uart2m1_xfer: uart2m1-xfer {
- rockchip,pins =
- /* uart2_rx_m1 */
- <3 RK_PA3 1 &pcfg_pull_up>,
- /* uart2_tx_m1 */
- <3 RK_PA2 1 &pcfg_pull_up>;
- };
- };
- uart3 {
- /omit-if-no-ref/
- uart3m0_xfer: uart3m0-xfer {
- rockchip,pins =
- /* uart3_rx_m0 */
- <3 RK_PC7 4 &pcfg_pull_up>,
- /* uart3_tx_m0 */
- <3 RK_PC6 4 &pcfg_pull_up>;
- };
- /omit-if-no-ref/
- uart3m2_xfer: uart3m2-xfer {
- rockchip,pins =
- /* uart3_rx_m2 */
- <3 RK_PA1 4 &pcfg_pull_up>,
- /* uart3_tx_m2 */
- <3 RK_PA0 4 &pcfg_pull_up>;
- };
- };
- uart4 {
- /omit-if-no-ref/
- uart4m0_xfer: uart4m0-xfer {
- rockchip,pins =
- /* uart4_rx_m0 */
- <3 RK_PA5 4 &pcfg_pull_up>,
- /* uart4_tx_m0 */
- <3 RK_PA4 4 &pcfg_pull_up>;
- };
- /omit-if-no-ref/
- uart4m2_xfer: uart4m2-xfer {
- rockchip,pins =
- /* uart4_rx_m2 */
- <1 RK_PD4 3 &pcfg_pull_up>,
- /* uart4_tx_m2 */
- <1 RK_PD5 3 &pcfg_pull_up>;
- };
- };
- uart5 {
- /omit-if-no-ref/
- uart5m0_xfer: uart5m0-xfer {
- rockchip,pins =
- /* uart5_rx_m0 */
- <3 RK_PA7 4 &pcfg_pull_up>,
- /* uart5_tx_m0 */
- <3 RK_PA6 4 &pcfg_pull_up>;
- };
- /omit-if-no-ref/
- uart5m2_xfer: uart5m2-xfer {
- rockchip,pins =
- /* uart5_rx_m2 */
- <2 RK_PA1 3 &pcfg_pull_up>,
- /* uart5_tx_m2 */
- <2 RK_PA0 3 &pcfg_pull_up>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-sonoff-ihost.dtsi"
-
-/ {
- model = "Sonoff iHost 4G";
- compatible = "itead,sonoff-ihost", "rockchip,rv1126";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/ {
- aliases {
- ethernet0 = &gmac;
- mmc0 = &emmc;
- };
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- vcc5v0_sys: regulator-vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- sdio_pwrseq: pwrseq-sdio {
- compatible = "mmc-pwrseq-simple";
- clocks = <&rk809 1>;
- clock-names = "ext_clock";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
- };
-};
-
-&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
- rockchip,default-sample-phase = <90>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc_buck5>;
- vcc6-supply = <&vcc_buck5>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
-
- regulators {
- vdd_npu_vepu: DCDC_REG1 {
- regulator-name = "vdd_npu_vepu";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <650000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc3v3_sys: DCDC_REG4 {
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_buck5: DCDC_REG5 {
- regulator-name = "vcc_buck5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2200000>;
- regulator-max-microvolt = <2200000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2200000>;
- };
- };
-
- vcc_0v8: LDO_REG1 {
- regulator-name = "vcc_0v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc1v8_pmu: LDO_REG2 {
- regulator-name = "vcc1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd0v8_pmu: LDO_REG3 {
- regulator-name = "vcc0v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <800000>;
- };
- };
-
- vcc_1v8: LDO_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_dovdd: LDO_REG5 {
- regulator-name = "vcc_dovdd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_dvdd: LDO_REG6 {
- regulator-name = "vcc_dvdd";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_avdd: LDO_REG7 {
- regulator-name = "vcc_avdd";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG8 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: LDO_REG9 {
- regulator-name = "vcc3v3_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_5v0: SWITCH_REG1 {
- regulator-name = "vcc_5v0";
- };
-
- vcc_3v3: SWITCH_REG2 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-};
-
-&i2c2 {
- status = "okay";
- clock-frequency = <400000>;
-
- pcf8563: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- #clock-cells = <0>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
- clock-output-names = "xin32k";
- };
-};
-
-&gmac {
- assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>,
- <&cru CLK_GMAC_TX_RX>;
- assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>,
- <&cru RMII_MODE_CLK>;
- assigned-clock-rates = <0>, <50000000>;
- clock_in_out = "output";
- phy-handle = <&phy>;
- phy-mode = "rmii";
- phy-supply = <&vcc_3v3>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_miim &rgmiim1_rxer &rgmiim1_bus2 &rgmiim1_mclkinout>;
- status = "okay";
-};
-
-&mdio {
- phy: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- pinctrl-names = "default";
- pinctrl-0 = <ð_phy_rst>;
- reset-active-low;
- reset-assert-us = <50000>;
- reset-deassert-us = <10000>;
- reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
- };
-};
-
-&pinctrl {
- ethernet {
- eth_phy_rst: eth-phy-rst {
- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
- bt {
- bt_enable: bt-enable {
- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_dev: bt-wake-dev {
- rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- bt_wake_host: bt-wake-host {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- wifi {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio0-supply = <&vcc1v8_pmu>;
- pmuio1-supply = <&vcc3v3_sys>;
- vccio1-supply = <&vcc_1v8>;
- vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_1v8>;
- vccio4-supply = <&vcc_dovdd>;
- vccio5-supply = <&vcc_1v8>;
- vccio6-supply = <&vcc_1v8>;
- vccio7-supply = <&vcc_dovdd>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdio {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- max-frequency = <100000000>;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
- rockchip,default-sample-phase = <90>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sys>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
- rockchip,default-sample-phase = <90>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr104;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "realtek,rtl8723ds-bt";
- device-wake-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; /* BT_WAKE */
- enable-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; /* BT_RST */
- host-wake-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; /* BT_WAKE_HOST */
- max-speed = <2000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>;
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart3m2_xfer>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart4m2_xfer>;
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/clock/rockchip,rv1126-cru.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/power/rockchip,rv1126-power.h>
-#include <dt-bindings/soc/rockchip,boot-mode.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- compatible = "rockchip,rv1126";
-
- interrupt-parent = <&gic>;
-
- aliases {
- i2c0 = &i2c0;
- i2c2 = &i2c2;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- serial4 = &uart4;
- serial5 = &uart5;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@f00 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf00>;
- enable-method = "psci";
- clocks = <&cru ARMCLK>;
- };
-
- cpu1: cpu@f01 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf01>;
- enable-method = "psci";
- clocks = <&cru ARMCLK>;
- };
-
- cpu2: cpu@f02 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf02>;
- enable-method = "psci";
- clocks = <&cru ARMCLK>;
- };
-
- cpu3: cpu@f03 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf03>;
- enable-method = "psci";
- clocks = <&cru ARMCLK>;
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- clock-frequency = <24000000>;
- };
-
- display_subsystem {
- compatible = "rockchip,display-subsystem";
- ports = <&vop_out>;
- };
-
- xin24m: oscillator {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- #clock-cells = <0>;
- };
-
- grf: syscon@fe000000 {
- compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
- reg = <0xfe000000 0x20000>;
- };
-
- pmugrf: syscon@fe020000 {
- compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
- reg = <0xfe020000 0x1000>;
-
- pmu_io_domains: io-domains {
- compatible = "rockchip,rv1126-pmu-io-voltage-domain";
- status = "disabled";
- };
- };
-
- qos_emmc: qos@fe860000 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe860000 0x20>;
- };
-
- qos_nandc: qos@fe860080 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe860080 0x20>;
- };
-
- qos_sfc: qos@fe860200 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe860200 0x20>;
- };
-
- qos_sdio: qos@fe86c000 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe86c000 0x20>;
- };
-
- qos_iep: qos@fe8a0000 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe8a0000 0x20>;
- };
-
- qos_rga_rd: qos@fe8a0080 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe8a0080 0x20>;
- };
-
- qos_rga_wr: qos@fe8a0100 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe8a0100 0x20>;
- };
-
- qos_vop: qos@fe8a0180 {
- compatible = "rockchip,rv1126-qos", "syscon";
- reg = <0xfe8a0180 0x20>;
- };
-
- gic: interrupt-controller@feff0000 {
- compatible = "arm,gic-400";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <0>;
-
- reg = <0xfeff1000 0x1000>,
- <0xfeff2000 0x2000>,
- <0xfeff4000 0x2000>,
- <0xfeff6000 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- pmu: power-management@ff3e0000 {
- compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
- reg = <0xff3e0000 0x1000>;
-
- power: power-controller {
- compatible = "rockchip,rv1126-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- power-domain@RV1126_PD_NVM {
- reg = <RV1126_PD_NVM>;
- clocks = <&cru HCLK_EMMC>,
- <&cru CLK_EMMC>,
- <&cru HCLK_NANDC>,
- <&cru CLK_NANDC>,
- <&cru HCLK_SFC>,
- <&cru HCLK_SFCXIP>,
- <&cru SCLK_SFC>;
- pm_qos = <&qos_emmc>,
- <&qos_nandc>,
- <&qos_sfc>;
- #power-domain-cells = <0>;
- };
-
- power-domain@RV1126_PD_SDIO {
- reg = <RV1126_PD_SDIO>;
- clocks = <&cru HCLK_SDIO>,
- <&cru CLK_SDIO>;
- pm_qos = <&qos_sdio>;
- #power-domain-cells = <0>;
- };
-
- power-domain@RV1126_PD_VO {
- reg = <RV1126_PD_VO>;
- clocks = <&cru ACLK_RGA>,
- <&cru HCLK_RGA>,
- <&cru CLK_RGA_CORE>,
- <&cru ACLK_VOP>,
- <&cru HCLK_VOP>,
- <&cru DCLK_VOP>,
- <&cru PCLK_DSIHOST>,
- <&cru ACLK_IEP>,
- <&cru HCLK_IEP>,
- <&cru CLK_IEP_CORE>;
- pm_qos = <&qos_rga_rd>,
- <&qos_rga_wr>,
- <&qos_vop>,
- <&qos_iep>;
- #power-domain-cells = <0>;
- };
- };
- };
-
- i2c0: i2c@ff3f0000 {
- compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
- reg = <0xff3f0000 0x1000>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,grf = <&pmugrf>;
- clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
- clock-names = "i2c", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@ff400000 {
- compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
- reg = <0xff400000 0x1000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,grf = <&pmugrf>;
- clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
- clock-names = "i2c", "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart1: serial@ff410000 {
- compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
- reg = <0xff410000 0x100>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 7>, <&dmac 6>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m0_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- pwm2: pwm@ff430020 {
- compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
- reg = <0xff430020 0x10>;
- clock-names = "pwm", "pclk";
- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm2m0_pins>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pmucru: clock-controller@ff480000 {
- compatible = "rockchip,rv1126-pmucru";
- reg = <0xff480000 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- cru: clock-controller@ff490000 {
- compatible = "rockchip,rv1126-cru";
- reg = <0xff490000 0x1000>;
- clocks = <&xin24m>;
- clock-names = "xin24m";
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- dmac: dma-controller@ff4e0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0xff4e0000 0x4000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
- };
-
- pwm11: pwm@ff550030 {
- compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
- reg = <0xff550030 0x10>;
- clock-names = "pwm", "pclk";
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
- pinctrl-0 = <&pwm11m0_pins>;
- pinctrl-names = "default";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- uart0: serial@ff560000 {
- compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
- reg = <0xff560000 0x100>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 5>, <&dmac 4>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart2: serial@ff570000 {
- compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
- reg = <0xff570000 0x100>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 9>, <&dmac 8>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2m1_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart3: serial@ff580000 {
- compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
- reg = <0xff580000 0x100>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 11>, <&dmac 10>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3m0_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart4: serial@ff590000 {
- compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
- reg = <0xff590000 0x100>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 13>, <&dmac 12>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart4m0_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart5: serial@ff5a0000 {
- compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
- reg = <0xff5a0000 0x100>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
- clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac 15>, <&dmac 14>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&uart5m0_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- saradc: adc@ff5e0000 {
- compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
- reg = <0xff5e0000 0x100>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- #io-channel-cells = <1>;
- clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
- clock-names = "saradc", "apb_pclk";
- resets = <&cru SRST_SARADC_P>;
- reset-names = "saradc-apb";
- status = "disabled";
- };
-
- timer0: timer@ff660000 {
- compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
- reg = <0xff660000 0x20>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
- clock-names = "pclk", "timer";
- };
-
- vop: vop@ffb00000 {
- compatible = "rockchip,rv1126-vop";
- reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
- clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
- reset-names = "axi", "ahb", "dclk";
- resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
- iommus = <&vop_mmu>;
- power-domains = <&power RV1126_PD_VO>;
- status = "disabled";
-
- vop_out: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- vop_out_rgb: endpoint@0 {
- reg = <0>;
- };
-
- vop_out_dsi: endpoint@1 {
- reg = <1>;
- };
- };
- };
-
- vop_mmu: iommu@ffb00f00 {
- compatible = "rockchip,iommu";
- reg = <0xffb00f00 0x100>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "aclk", "iface";
- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
- #iommu-cells = <0>;
- power-domains = <&power RV1126_PD_VO>;
- status = "disabled";
- };
-
- gmac: ethernet@ffc40000 {
- compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
- reg = <0xffc40000 0x4000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq", "eth_wake_irq";
- rockchip,grf = <&grf>;
- clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
- <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
- <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
- <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
- clock-names = "stmmaceth", "mac_clk_rx",
- "mac_clk_tx", "clk_mac_ref",
- "aclk_mac", "pclk_mac",
- "clk_mac_speed", "ptp_ref";
- resets = <&cru SRST_GMAC_A>;
- reset-names = "stmmaceth";
-
- snps,mixed-burst;
- snps,tso;
-
- snps,axi-config = <&stmmac_axi_setup>;
- snps,mtl-rx-config = <&mtl_rx_setup>;
- snps,mtl-tx-config = <&mtl_tx_setup>;
- status = "disabled";
-
- mdio: mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- };
-
- stmmac_axi_setup: stmmac-axi-config {
- snps,wr_osr_lmt = <4>;
- snps,rd_osr_lmt = <8>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
-
- mtl_rx_setup: rx-queues-config {
- snps,rx-queues-to-use = <1>;
- queue0 {};
- };
-
- mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <1>;
- queue0 {};
- };
- };
-
- emmc: mmc@ffc50000 {
- compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0xffc50000 0x4000>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <200000000>;
- power-domains = <&power RV1126_PD_NVM>;
- status = "disabled";
- };
-
- sdmmc: mmc@ffc60000 {
- compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0xffc60000 0x4000>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <200000000>;
- status = "disabled";
- };
-
- sdio: mmc@ffc70000 {
- compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0xffc70000 0x4000>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- fifo-depth = <0x100>;
- max-frequency = <200000000>;
- power-domains = <&power RV1126_PD_SDIO>;
- status = "disabled";
- };
-
- sfc: spi@ffc90000 {
- compatible = "rockchip,sfc";
- reg = <0xffc90000 0x4000>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- assigned-clocks = <&cru SCLK_SFC>;
- assigned-clock-rates = <80000000>;
- clock-names = "clk_sfc", "hclk_sfc";
- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
- power-domains = <&power RV1126_PD_NVM>;
- status = "disabled";
- };
-
- pinctrl: pinctrl {
- compatible = "rockchip,rv1126-pinctrl";
- rockchip,grf = <&grf>;
- rockchip,pmu = <&pmugrf>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- gpio0: gpio@ff460000 {
- compatible = "rockchip,gpio-bank";
- reg = <0xff460000 0x100>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@ff620000 {
- compatible = "rockchip,gpio-bank";
- reg = <0xff620000 0x100>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@ff630000 {
- compatible = "rockchip,gpio-bank";
- reg = <0xff630000 0x100>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@ff640000 {
- compatible = "rockchip,gpio-bank";
- reg = <0xff640000 0x100>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@ff650000 {
- compatible = "rockchip,gpio-bank";
- reg = <0xff650000 0x100>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-};
-
-#include "rv1126-pinctrl.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for common parts of Salvator-X board variants
- *
- * Copyright (C) 2015-2016 Renesas Electronics Corp.
- */
-
-/*
- * SSI-AK4613
- *
- * This command is required when Playback/Capture
- *
- * amixer set "DVC Out" 100%
- * amixer set "DVC In" 100%
- *
- * You can use Mute
- *
- * amixer set "DVC Out Mute" on
- * amixer set "DVC In Mute" on
- *
- * You can use Volume Ramp
- *
- * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
- * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
- * amixer set "DVC Out Ramp" on
- * aplay xxx.wav &
- * amixer set "DVC Out" 80% // Volume Down
- * amixer set "DVC Out" 100% // Volume Up
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &i2c_dvfs;
- serial0 = &scif2;
- serial1 = &hscif1;
- ethernet0 = &avb;
- mmc0 = &sdhi2;
- mmc1 = &sdhi0;
- mmc2 = &sdhi3;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- audio_clkout: audio-clkout {
- /*
- * This is same as <&rcar_sound 0>
- * but needed to avoid cs2000/rcar_sound probe dead-lock
- */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12288000>;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm1 0 50000>;
-
- brightness-levels = <256 128 64 16 8 4 0>;
- default-brightness-level = <6>;
-
- power-supply = <®_12v>;
- enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
- };
-
- cvbs-in {
- compatible = "composite-video-connector";
- label = "CVBS IN";
-
- port {
- cvbs_con: endpoint {
- remote-endpoint = <&adv7482_ain7>;
- };
- };
- };
-
- hdmi-in {
- compatible = "hdmi-connector";
- label = "HDMI IN";
- type = "a";
-
- port {
- hdmi_in_con: endpoint {
- remote-endpoint = <&adv7482_hdmi>;
- };
- };
- };
-
- hdmi0-out {
- compatible = "hdmi-connector";
- label = "HDMI0 OUT";
- type = "a";
-
- port {
- hdmi0_con: endpoint {
- remote-endpoint = <&rcar_dw_hdmi0_out>;
- };
- };
- };
-
- hdmi1-out {
- compatible = "hdmi-connector";
- label = "HDMI1 OUT";
- type = "a";
-
- port {
- hdmi1_con: endpoint {
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&keys_pins>;
- pinctrl-names = "default";
-
- key-1 {
- gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_1>;
- label = "SW4-1";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-2 {
- gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_2>;
- label = "SW4-2";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-3 {
- gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_3>;
- label = "SW4-3";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-4 {
- gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_4>;
- label = "SW4-4";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-a {
- gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_A>;
- label = "TSW0";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-b {
- gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_B>;
- label = "TSW1";
- wakeup-source;
- debounce-interval = <20>;
- };
- key-c {
- gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_C>;
- label = "TSW2";
- wakeup-source;
- debounce-interval = <20>;
- };
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_12v: regulator-12v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-12V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sound_card: sound {
- compatible = "audio-graph-card";
-
- label = "rcar-sound";
-
- dais = <&rsnd_port0 /* ak4613 */
- &rsnd_port1 /* HDMI0 */
-#ifdef SOC_HAS_HDMI1
- &rsnd_port2 /* HDMI1 */
-#endif
- >;
- };
-
- vbus0_usb2: regulator-vbus0-usb2 {
- compatible = "regulator-fixed";
-
- regulator-name = "USB20_VBUS0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vcc_sdhi3: regulator-vcc-sdhi3 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI3 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi3: regulator-vccq-sdhi3 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI3 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- vga {
- compatible = "vga-connector";
-
- port {
- vga_in: endpoint {
- remote-endpoint = <&adv7123_out>;
- };
- };
- };
-
- vga-encoder {
- compatible = "adi,adv7123";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7123_in: endpoint {
- remote-endpoint = <&du_out_rgb>;
- };
- };
- port@1 {
- reg = <1>;
- adv7123_out: endpoint {
- remote-endpoint = <&vga_in>;
- };
- };
- };
- };
-
- x12_clk: x12 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- /* External DU dot clocks */
- x21_clk: x21-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <33000000>;
- };
-
- x22_clk: x22-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <33000000>;
- };
-
- x23_clk: x23-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-};
-
-&a57_0 {
- cpu-supply = <&dvfs>;
-};
-
-&audio_clk_a {
- clock-frequency = <22579200>;
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
- phy-handle = <&phy0>;
- tx-internal-delay-ps = <2000>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0022.1622",
- "ethernet-phy-ieee802.3-c22";
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio2>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
- };
-};
-
-&csi20 {
- status = "okay";
-
- ports {
- port@0 {
- csi20_in: endpoint {
- clock-lanes = <0>;
- data-lanes = <1>;
- remote-endpoint = <&adv7482_txb>;
- };
- };
- };
-};
-
-&csi40 {
- status = "okay";
-
- ports {
- port@0 {
- csi40_in: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&adv7482_txa>;
- };
- };
- };
-};
-
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- ports {
- port@0 {
- du_out_rgb: endpoint {
- remote-endpoint = <&adv7123_in>;
- };
- };
- };
-};
-
-&ehci0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&hdmi0 {
- status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
- rcar_dw_hdmi0_out: endpoint {
- remote-endpoint = <&hdmi0_con>;
- };
- };
- port@2 {
- reg = <2>;
- dw_hdmi0_snd_in: endpoint {
- remote-endpoint = <&rsnd_endpoint1>;
- };
- };
- };
-};
-
-#ifdef SOC_HAS_HDMI1
-&hdmi1 {
- status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
- rcar_dw_hdmi1_out: endpoint {
- remote-endpoint = <&hdmi1_con>;
- };
- };
- port@2 {
- reg = <2>;
- dw_hdmi1_snd_in: endpoint {
- remote-endpoint = <&rsnd_endpoint2>;
- };
- };
- };
-};
-
-&hdmi1_con {
- remote-endpoint = <&rcar_dw_hdmi1_out>;
-};
-#endif /* SOC_HAS_HDMI1 */
-
-&hscif1 {
- pinctrl-0 = <&hscif1_pins>;
- pinctrl-names = "default";
-
- uart-has-rtscts;
- /* Please only enable hscif1 or scif1 */
- status = "okay";
-};
-
-&hsusb {
- dr_mode = "otg";
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- clock-frequency = <100000>;
-
- ak4613: codec@10 {
- compatible = "asahi-kasei,ak4613";
- #sound-dai-cells = <0>;
- reg = <0x10>;
- clocks = <&rcar_sound 3>;
-
- asahi-kasei,in1-single-end;
- asahi-kasei,in2-single-end;
- asahi-kasei,out1-single-end;
- asahi-kasei,out2-single-end;
- asahi-kasei,out3-single-end;
- asahi-kasei,out4-single-end;
- asahi-kasei,out5-single-end;
- asahi-kasei,out6-single-end;
-
- port {
- ak4613_endpoint: endpoint {
- remote-endpoint = <&rsnd_endpoint0>;
- };
- };
- };
-
- cs2000: clk_multiplier@4f {
- #clock-cells = <0>;
- compatible = "cirrus,cs2000-cp";
- reg = <0x4f>;
- clocks = <&audio_clkout>, <&x12_clk>;
- clock-names = "clk_in", "ref_clk";
-
- assigned-clocks = <&cs2000>;
- assigned-clock-rates = <24576000>; /* 1/1 divide */
- };
-};
-
-&i2c4 {
- status = "okay";
-
- pca9654: gpio@20 {
- compatible = "onnn,pca9654";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- video-receiver@70 {
- compatible = "adi,adv7482";
- reg = <0x70 0x71 0x72 0x73 0x74 0x75
- 0x60 0x61 0x62 0x63 0x64 0x65>;
- reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
- "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
-
- interrupt-parent = <&gpio6>;
- interrupt-names = "intrq1", "intrq2";
- interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
- <31 IRQ_TYPE_LEVEL_LOW>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@7 {
- reg = <7>;
-
- adv7482_ain7: endpoint {
- remote-endpoint = <&cvbs_con>;
- };
- };
-
- port@8 {
- reg = <8>;
-
- adv7482_hdmi: endpoint {
- remote-endpoint = <&hdmi_in_con>;
- };
- };
-
- port@a {
- reg = <10>;
-
- adv7482_txa: endpoint {
- clock-lanes = <0>;
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&csi40_in>;
- };
- };
-
- port@b {
- reg = <11>;
-
- adv7482_txb: endpoint {
- clock-lanes = <0>;
- data-lanes = <1>;
- remote-endpoint = <&csi20_in>;
- };
- };
- };
- };
-
- csa_vdd: adc@7c {
- compatible = "maxim,max9611";
- reg = <0x7c>;
-
- shunt-resistor-micro-ohms = <5000>;
- };
-
- csa_dvfs: adc@7f {
- compatible = "maxim,max9611";
- reg = <0x7f>;
-
- shunt-resistor-micro-ohms = <5000>;
- };
-};
-
-&i2c_dvfs {
- status = "okay";
-
- clock-frequency = <400000>;
-
- pmic: pmic@30 {
- pinctrl-0 = <&irq0_pins>;
- pinctrl-names = "default";
-
- compatible = "rohm,bd9571mwv";
- reg = <0x30>;
- interrupt-parent = <&intc_ex>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- rohm,ddr-backup-power = <0xf>;
- rohm,rstbmode-level;
-
- regulators {
- dvfs: dvfs {
- regulator-name = "dvfs";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1030000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-
- eeprom@50 {
- compatible = "rohm,br24t01", "atmel,24c01";
- reg = <0x50>;
- pagesize = <8>;
- };
-};
-
-&ohci0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&pcie_bus_clk {
- clock-frequency = <100000000>;
-};
-
-&pciec0 {
- status = "okay";
-};
-
-&pciec1 {
- status = "okay";
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- avb_pins: avb {
- mux {
- groups = "avb_link", "avb_mdio", "avb_mii";
- function = "avb";
- };
-
- pins_mdio {
- groups = "avb_mdio";
- drive-strength = <24>;
- };
-
- pins_mii_tx {
- pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
- "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
- drive-strength = <12>;
- };
- };
-
- du_pins: du {
- groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
- function = "du";
- };
-
- hscif1_pins: hscif1 {
- groups = "hscif1_data_a", "hscif1_ctrl_a";
- function = "hscif1";
- };
-
- i2c2_pins: i2c2 {
- groups = "i2c2_a";
- function = "i2c2";
- };
-
- irq0_pins: irq0 {
- groups = "intc_ex_irq0";
- function = "intc_ex";
- };
-
- keys_pins: keys {
- pins = "GP_5_17", "GP_5_20", "GP_5_22";
- bias-pull-up;
- };
-
- pwm1_pins: pwm1 {
- groups = "pwm1_a";
- function = "pwm1";
- };
-
- scif1_pins: scif1 {
- groups = "scif1_data_a", "scif1_ctrl";
- function = "scif1";
- };
-
- scif2_pins: scif2 {
- groups = "scif2_data_a";
- function = "scif2";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk_a";
- function = "scif_clk";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi2_pins: sd2 {
- groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
- function = "sdhi2";
- power-source = <1800>;
- };
-
- sdhi3_pins: sd3 {
- groups = "sdhi3_data4", "sdhi3_ctrl";
- function = "sdhi3";
- power-source = <3300>;
- };
-
- sdhi3_pins_uhs: sd3_uhs {
- groups = "sdhi3_data4", "sdhi3_ctrl";
- function = "sdhi3";
- power-source = <1800>;
- };
-
- sound_pins: sound {
- groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
- function = "ssi";
- };
-
- sound_clk_pins: sound_clk {
- groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
- "audio_clkout_a", "audio_clkout3_a";
- function = "audio_clk";
- };
-
- usb0_pins: usb0 {
- groups = "usb0";
- function = "usb0";
- };
-
- usb1_pins: usb1 {
- mux {
- groups = "usb1";
- function = "usb1";
- };
-
- ovc {
- pins = "GP_6_27";
- bias-pull-up;
- };
-
- pwen {
- pins = "GP_6_26";
- bias-pull-down;
- };
- };
-
- usb30_pins: usb30 {
- groups = "usb30";
- function = "usb30";
- };
-};
-
-&pwm1 {
- pinctrl-0 = <&pwm1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
- pinctrl-names = "default";
-
- /* audio_clkout0/1/2/3 */
- #clock-cells = <1>;
- clock-frequency = <12288000 11289600>;
-
- status = "okay";
-
- /* update <audio_clk_b> to <cs2000> */
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&cs2000>,
- <&audio_clk_c>,
- <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- rsnd_port0: port@0 {
- reg = <0>;
- rsnd_endpoint0: endpoint {
- remote-endpoint = <&ak4613_endpoint>;
-
- dai-format = "left_j";
- bitclock-master = <&rsnd_endpoint0>;
- frame-master = <&rsnd_endpoint0>;
-
- playback = <&ssi0>, <&src0>, <&dvc0>;
- capture = <&ssi1>, <&src1>, <&dvc1>;
- };
- };
-
- rsnd_port1: port@1 {
- reg = <1>;
- rsnd_endpoint1: endpoint {
- remote-endpoint = <&dw_hdmi0_snd_in>;
-
- dai-format = "i2s";
- bitclock-master = <&rsnd_endpoint1>;
- frame-master = <&rsnd_endpoint1>;
-
- playback = <&ssi2>;
- };
- };
-
-#ifdef SOC_HAS_HDMI1
- rsnd_port2: port@2 {
- reg = <2>;
- rsnd_endpoint2: endpoint {
- remote-endpoint = <&dw_hdmi1_snd_in>;
-
- dai-format = "i2s";
- bitclock-master = <&rsnd_endpoint2>;
- frame-master = <&rsnd_endpoint2>;
-
- playback = <&ssi3>;
- };
- };
-#endif /* SOC_HAS_HDMI1 */
- };
-};
-
-&rpc {
- /* Left disabled. To be enabled by firmware when unlocked. */
-
- flash@0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootparam@0 {
- reg = <0x00000000 0x040000>;
- read-only;
- };
- bl2@40000 {
- reg = <0x00040000 0x140000>;
- read-only;
- };
- cert_header_sa6@180000 {
- reg = <0x00180000 0x040000>;
- read-only;
- };
- bl31@1c0000 {
- reg = <0x001c0000 0x040000>;
- read-only;
- };
- tee@200000 {
- reg = <0x00200000 0x440000>;
- read-only;
- };
- uboot@640000 {
- reg = <0x00640000 0x100000>;
- read-only;
- };
- dtb@740000 {
- reg = <0x00740000 0x080000>;
- };
- kernel@7c0000 {
- reg = <0x007c0000 0x1400000>;
- };
- user@1bc0000 {
- reg = <0x01bc0000 0x2440000>;
- };
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-#ifdef SOC_HAS_SATA
-&sata {
- status = "okay";
-};
-#endif /* SOC_HAS_SATA */
-
-&scif1 {
- pinctrl-0 = <&scif1_pins>;
- pinctrl-names = "default";
-
- uart-has-rtscts;
- /* Please only enable hscif1 or scif1 */
- /* status = "okay"; */
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
- bus-width = <4>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdhi2 {
- /* used for on-board 8bit eMMC */
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-1 = <&sdhi2_pins>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- bus-width = <8>;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- no-sd;
- no-sdio;
- non-removable;
- fixed-emmc-driver-type = <1>;
- full-pwr-cycle-in-suspend;
- status = "okay";
-};
-
-&sdhi3 {
- pinctrl-0 = <&sdhi3_pins>;
- pinctrl-1 = <&sdhi3_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi3>;
- vqmmc-supply = <&vccq_sdhi3>;
- cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
- bus-width = <4>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&ssi1 {
- shared-pin;
-};
-
-&usb_extal_clk {
- clock-frequency = <50000000>;
-};
-
-&usb2_phy0 {
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-
- vbus-supply = <&vbus0_usb2>;
- status = "okay";
-};
-
-&usb2_phy1 {
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&usb3_peri0 {
- phys = <&usb3_phy0>;
- phy-names = "usb";
-
- companion = <&xhci0>;
-
- status = "okay";
-};
-
-&usb3_phy0 {
- status = "okay";
-};
-
-&usb3s0_clk {
- clock-frequency = <100000000>;
-};
-
-&vin0 {
- status = "okay";
-};
-
-&vin1 {
- status = "okay";
-};
-
-&vin2 {
- status = "okay";
-};
-
-&vin3 {
- status = "okay";
-};
-
-&vin4 {
- status = "okay";
-};
-
-&vin5 {
- status = "okay";
-};
-
-&vin6 {
- status = "okay";
-};
-
-&vin7 {
- status = "okay";
-};
-
-&xhci0 {
- pinctrl-0 = <&usb30_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-#ifdef SOC_HAS_USB2_CH2
-&ehci2 {
- status = "okay";
-};
-
-&ohci2 {
- status = "okay";
-};
-
-&pfc {
- usb2_pins: usb2 {
- groups = "usb2";
- function = "usb2";
- };
-};
-
-&usb2_phy2 {
- pinctrl-0 = <&usb2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-#endif /* SOC_HAS_USB2_CH2 */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Salvator-X board
- *
- * Copyright (C) 2015-2016 Renesas Electronics Corp.
- */
-
-#include "salvator-common.dtsi"
-
-/ {
- model = "Renesas Salvator-X board";
- compatible = "renesas,salvator-x";
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&i2c4 {
- clock-frequency = <400000>;
-
- versaclock5: clock-generator@6a {
- compatible = "idt,5p49v5923";
- reg = <0x6a>;
- #clock-cells = <1>;
- clocks = <&x23_clk>;
- clock-names = "xin";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Salvator-X 2nd version board
- *
- * Copyright (C) 2015-2017 Renesas Electronics Corp.
- */
-
-#include "salvator-common.dtsi"
-
-/ {
- model = "Renesas Salvator-X 2nd version board";
- compatible = "renesas,salvator-xs";
-};
-
-&extal_clk {
- clock-frequency = <16640000>;
-};
-
-&i2c4 {
- clock-frequency = <400000>;
-
- versaclock6: clock-generator@6a {
- compatible = "idt,5p49v6901";
- reg = <0x6a>;
- #clock-cells = <1>;
- clocks = <&x23_clk>;
- clock-names = "xin";
- };
-};
-
-#ifdef SOC_HAS_SATA
-&pca9654 {
- pcie-sata-switch-hog {
- gpio-hog;
- gpios = <7 GPIO_ACTIVE_HIGH>;
- output-low; /* enable SATA by default */
- line-name = "PCIE/SATA switch";
- };
-};
-
-/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
-#endif /* SOC_HAS_SATA */
-
-#ifdef SOC_HAS_USB2_CH3
-&ehci3 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&hsusb3 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&ohci3 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&pfc {
- /*
- * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
- * (when SW31 is the default setting on Salvator-XS).
- * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
- * r8a77951 with Salvator-XS.
- * Hence the SW31 setting must be changed like 2) below.
- * 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
- * - Connect GP6_3[01] to ADV7842.
- * 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
- * - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
- * - Connect GP6_{04,21} to ADV7842.
- */
- usb2_ch3_pins: usb2_ch3 {
- groups = "usb2_ch3";
- function = "usb2_ch3";
- };
-};
-
-&usb2_phy3 {
- pinctrl-0 = <&usb2_ch3_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-#endif /* SOC_HAS_USB2_CH3 */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree for ULCB + Audio Graph Card
- *
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-
-/*
- * (A) CPU0 <-----> ak4613
- * (B) CPU1 -----> HDMI
- *
- * (A) aplay -D plughw:0,0 xxx.wav
- * (B) aplay -D plughw:0,1 xxx.wav
- *
- * (A) arecord -D plughw:0,0 xxx.wav
- */
-
-/ {
- sound_card: sound {
- compatible = "audio-graph-card";
- label = "rcar-sound";
-
- dais = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */
- &rsnd_port1 /* (B) CPU1 -> HDMI */
- >;
- };
-};
-
-&ak4613 {
- #sound-dai-cells = <0>;
-
- port {
- /*
- * (A) CPU0 <-> ak4613
- */
- ak4613_endpoint: endpoint {
- remote-endpoint = <&rsnd_for_ak4613>;
- };
- };
-};
-
-&hdmi0 {
- ports {
- port@2 {
- /*
- * (B) CPU1 -> HDMI
- */
- dw_hdmi0_snd_in: endpoint {
- remote-endpoint = <&rsnd_for_hdmi>;
- };
- };
- };
-};
-
-&rcar_sound {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- rsnd_port0: port@0 {
- /*
- * (A) CPU0 <-> ak4613
- */
- reg = <0>;
- rsnd_for_ak4613: endpoint {
- remote-endpoint = <&ak4613_endpoint>;
- bitclock-master;
- frame-master;
- playback = <&ssi0>, <&src0>, <&dvc0>;
- capture = <&ssi1>, <&src1>, <&dvc1>;
- };
- };
- rsnd_port1: port@1 {
- /*
- * (B) CPU1 -> HDMI
- */
- reg = <1>;
- rsnd_for_hdmi: endpoint {
- remote-endpoint = <&dw_hdmi0_snd_in>;
- bitclock-master;
- frame-master;
- playback = <&ssi2>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree for ULCB + Audio Graph Card2
- *
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-
-/*
- * (A) CPU0 <----> ak4613
- * (B) CPU1 ----> HDMI
- *
- * (A) aplay -D plughw:0,0 xxx.wav
- * (B) aplay -D plughw:0,1 xxx.wav
- *
- * (A) arecord -D plughw:0,0 xxx.wav
- */
-#include "ulcb-audio-graph-card.dtsi"
-
-&sound_card {
- compatible = "audio-graph-card2";
-
- /delete-property/ dais;
- links = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */
- &rsnd_port1 /* (B) CPU1 -> HDMI */
- >;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car Gen3 ULCB board
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- * Copyright (C) 2016 Cogent Embedded, Inc.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Renesas R-Car Gen3 ULCB board";
-
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- i2c6 = &i2c6;
- i2c7 = &i2c_dvfs;
- serial0 = &scif2;
- ethernet0 = &avb;
- mmc0 = &sdhi2;
- mmc1 = &sdhi0;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
- };
-
- audio_clkout: audio-clkout {
- /*
- * This is same as <&rcar_sound 0>
- * but needed to avoid cs2000/rcar_sound probe dead-lock
- */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12288000>;
- };
-
- hdmi0-out {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi0_con: endpoint {
- remote-endpoint = <&rcar_dw_hdmi0_out>;
- };
- };
- };
-
- keyboard {
- compatible = "gpio-keys";
-
- key-1 {
- linux,code = <KEY_1>;
- label = "SW3";
- wakeup-source;
- debounce-interval = <20>;
- gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led5 {
- gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
- };
- led6 {
- gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
- };
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vcc_sdhi0: regulator-vcc-sdhi0 {
- compatible = "regulator-fixed";
-
- regulator-name = "SDHI0 Vcc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- x12_clk: x12 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- x23_clk: x23-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-};
-
-&a57_0 {
- cpu-supply = <&dvfs>;
-};
-
-&audio_clk_a {
- clock-frequency = <22579200>;
-};
-
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
- phy-handle = <&phy0>;
- tx-internal-delay-ps = <2000>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0022.1622",
- "ethernet-phy-ieee802.3-c22";
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio2>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
- };
-};
-
-&du {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&hdmi0 {
- status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
- rcar_dw_hdmi0_out: endpoint {
- remote-endpoint = <&hdmi0_con>;
- };
- };
- port@2 {
- reg = <2>;
- };
- };
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- clock-frequency = <100000>;
-
- ak4613: codec@10 {
- compatible = "asahi-kasei,ak4613";
- reg = <0x10>;
- clocks = <&rcar_sound 3>;
-
- asahi-kasei,in1-single-end;
- asahi-kasei,in2-single-end;
- asahi-kasei,out1-single-end;
- asahi-kasei,out2-single-end;
- asahi-kasei,out3-single-end;
- asahi-kasei,out4-single-end;
- asahi-kasei,out5-single-end;
- asahi-kasei,out6-single-end;
- };
-
- cs2000: clk-multiplier@4f {
- #clock-cells = <0>;
- compatible = "cirrus,cs2000-cp";
- reg = <0x4f>;
- clocks = <&audio_clkout>, <&x12_clk>;
- clock-names = "clk_in", "ref_clk";
-
- assigned-clocks = <&cs2000>;
- assigned-clock-rates = <24576000>; /* 1/1 divide */
- };
-};
-
-&i2c4 {
- status = "okay";
-
- clock-frequency = <400000>;
-
- versaclock5: clock-generator@6a {
- compatible = "idt,5p49v5925";
- reg = <0x6a>;
- #clock-cells = <1>;
- clocks = <&x23_clk>;
- clock-names = "xin";
- };
-};
-
-&i2c_dvfs {
- status = "okay";
-
- clock-frequency = <400000>;
-
- pmic: pmic@30 {
- pinctrl-0 = <&irq0_pins>;
- pinctrl-names = "default";
-
- compatible = "rohm,bd9571mwv";
- reg = <0x30>;
- interrupt-parent = <&intc_ex>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- rohm,ddr-backup-power = <0xf>;
- rohm,rstbmode-pulse;
-
- regulators {
- dvfs: dvfs {
- regulator-name = "dvfs";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1030000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-
- eeprom@50 {
- compatible = "rohm,br24t01", "atmel,24c01";
- reg = <0x50>;
- pagesize = <8>;
- };
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- avb_pins: avb {
- mux {
- groups = "avb_link", "avb_mdio", "avb_mii";
- function = "avb";
- };
-
- pins_mdio {
- groups = "avb_mdio";
- drive-strength = <24>;
- };
-
- pins_mii_tx {
- pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
- "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
- drive-strength = <12>;
- };
- };
-
- i2c2_pins: i2c2 {
- groups = "i2c2_a";
- function = "i2c2";
- };
-
- irq0_pins: irq0 {
- groups = "intc_ex_irq0";
- function = "intc_ex";
- };
-
- scif2_pins: scif2 {
- groups = "scif2_data_a";
- function = "scif2";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk_a";
- function = "scif_clk";
- };
-
- sdhi0_pins: sd0 {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <3300>;
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- groups = "sdhi0_data4", "sdhi0_ctrl";
- function = "sdhi0";
- power-source = <1800>;
- };
-
- sdhi2_pins: sd2 {
- groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
- function = "sdhi2";
- power-source = <1800>;
- };
-
- sound_pins: sound {
- groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
- function = "ssi";
- };
-
- sound_clk_pins: sound-clk {
- groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
- "audio_clkout_a", "audio_clkout3_a";
- function = "audio_clk";
- };
-
- usb1_pins: usb1 {
- groups = "usb1";
- function = "usb1";
- };
-};
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
- pinctrl-names = "default";
-
- /* audio_clkout0/1/2/3 */
- #clock-cells = <1>;
- clock-frequency = <12288000 11289600>;
-
- status = "okay";
-
- /* update <audio_clk_b> to <cs2000> */
- clocks = <&cpg CPG_MOD 1005>,
- <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
- <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
- <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
- <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
- <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
- <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
- <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
- <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
- <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
- <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
- <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
- <&audio_clk_a>, <&cs2000>,
- <&audio_clk_c>,
- <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
-};
-
-&rpc {
- /* Left disabled. To be enabled by firmware when unlocked. */
-
- flash@0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootparam@0 {
- reg = <0x00000000 0x040000>;
- read-only;
- };
- bl2@40000 {
- reg = <0x00040000 0x140000>;
- read-only;
- };
- cert_header_sa6@180000 {
- reg = <0x00180000 0x040000>;
- read-only;
- };
- bl31@1c0000 {
- reg = <0x001c0000 0x040000>;
- read-only;
- };
- tee@200000 {
- reg = <0x00200000 0x440000>;
- read-only;
- };
- uboot@640000 {
- reg = <0x00640000 0x100000>;
- read-only;
- };
- dtb@740000 {
- reg = <0x00740000 0x080000>;
- };
- kernel@7c0000 {
- reg = <0x007c0000 0x1400000>;
- };
- user@1bc0000 {
- reg = <0x01bc0000 0x2440000>;
- };
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <14745600>;
-};
-
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&vcc_sdhi0>;
- vqmmc-supply = <&vccq_sdhi0>;
- cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&sdhi2 {
- /* used for on-board 8bit eMMC */
- pinctrl-0 = <&sdhi2_pins>;
- pinctrl-1 = <&sdhi2_pins>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- bus-width = <8>;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- no-sd;
- no-sdio;
- non-removable;
- full-pwr-cycle-in-suspend;
- status = "okay";
-};
-
-&ssi1 {
- shared-pin;
-};
-
-&usb2_phy1 {
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-
-/*
- * For sound-test.
- *
- * We can switch Audio Card for testing
- *
- * #include "ulcb-simple-audio-card.dtsi"
- * #include "ulcb-simple-audio-card-mix+split.dtsi"
- * #include "ulcb-audio-graph-card.dtsi"
- * #include "ulcb-audio-graph-card-mix+split.dtsi"
- * #include "ulcb-audio-graph-card2-mix+split.dtsi"
- */
-#include "ulcb-audio-graph-card2.dtsi"
V0PLL,
AUPLL,
PPLL,
+ SPLL,
PLL_COUNT,
};
#define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
#define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
+#define RK3588_SBUSCRU_SPLL_CON(x) ((x) * 0x4 + 0x220)
+#define RK3588_SBUSCRU_MODE_CON0 0x280
+
enum {
/* CRU_CLK_SEL8_CON */
ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT = 14,
This option creates a build targeting the ARMv7/AArch32 ISA.
select BCM2711_32B
- imply OF_HAS_PRIOR_STAGE
config TARGET_RPI_4
bool "Raspberry Pi 4 64-bit build"
This option creates a build targeting the ARMv8/AArch64 ISA.
select BCM2711_64B
- imply OF_HAS_PRIOR_STAGE
config TARGET_RPI_ARM64
bool "Raspberry Pi one binary 64-bit build"
Support for all armv8 based Raspberry Pi variants, such as
the RPi 4 model B, in AArch64 (64-bit) mode.
select ARM64
- imply OF_HAS_PRIOR_STAGE
endchoice
select MACH_DAVINCI_DA850_EVM
select SOC_DA850
select SUPPORT_SPL
+ imply OF_UPSTREAM
config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
select OF_CONTROL
select PINCTRL
select PINCTRL_EXYNOS850
+ imply OF_UPSTREAM
endchoice
endif
static struct mm_region exynos850_mem_map[] = {
{
+ /* iRAM */
+ .virt = 0x02000000UL,
+ .phys = 0x02000000UL,
+ .size = SZ_2M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
/* Peripheral block */
.virt = 0x10000000UL,
.phys = 0x10000000UL,
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+ imply OF_UPSTREAM
config TARGET_PHYCORE_IMX8MP
bool "PHYTEC PHYCORE i.MX8MP"
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
+ imply OF_UPSTREAM
config TARGET_IMX8MM_CL_IOT_GATE
bool "CompuLab iot-gate-imx8"
bool "TI K3 based AM62P5 EVM running on A53"
select ARM64
select BINMAN
+ select OF_SYSTEM_SETUP
config TARGET_AM62P5_R5_EVM
bool "TI K3 based AM62P5 EVM running on R5"
# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
# Andrew Davis <afd@ti.com>
+obj-$(CONFIG_OF_SYSTEM_SETUP) += am62p5_fdt.o
obj-$(CONFIG_SPL_BUILD) += am62p5_init.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/hardware.h>
+#include "../common_fdt.h"
+#include <fdt_support.h>
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+ fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000);
+ fdt_fixup_reserved(blob, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000);
+
+ return 0;
+}
imply LEGACY_IMAGE_FORMAT
imply MISC
imply MISC_INIT_R
+ imply OF_UPSTREAM
imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_OTP
imply MISC
imply MISC_INIT_R
imply OF_LIVE
+ imply OF_UPSTREAM
imply PRE_CONSOLE_BUFFER
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_EFUSE
select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_SEPARATE_BSS
select SPL_SERIAL
- select SPL_DRIVERS_MISC
select CLK
select FIT
select PINCTRL
select DM_PMIC
select DM_REGULATOR_FIXED
select BOARD_LATE_INIT
+ imply ARMV8_CRYPTO
+ imply ARMV8_SET_SMPEN
+ imply BOOTSTD_FULL
+ imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
+ imply DM_RNG
+ imply LEGACY_IMAGE_FORMAT
+ imply MISC
+ imply MISC_INIT_R
+ imply OF_LIBFDT_OVERLAY
+ imply OF_LIVE
+ imply OF_UPSTREAM
imply PARTITION_TYPE_GUID
+ imply PHY_GIGE if GMAC_ROCKCHIP
imply PRE_CONSOLE_BUFFER
+ imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_EFUSE
imply ROCKCHIP_SDRAM_COMMON
+ imply SPL_DM_SEQ_ALIAS
+ imply SPL_FIT_SIGNATURE
imply SPL_ROCKCHIP_COMMON_BOARD
- imply TPL_SERIAL
+ imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
+ imply TPL_CLK
+ imply TPL_DM
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
- imply TPL_SYS_MALLOC_SIMPLE
- imply TPL_DRIVERS_MISC
imply TPL_OF_CONTROL
- imply TPL_DM
+ imply TPL_RAM
imply TPL_REGMAP
+ imply TPL_ROCKCHIP_COMMON_BOARD
+ imply TPL_SERIAL
+ imply TPL_SYS_MALLOC_SIMPLE
imply TPL_SYSCON
- imply TPL_RAM
- imply TPL_CLK
imply TPL_TINY_MEMSET
- imply TPL_ROCKCHIP_COMMON_BOARD
- imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
- imply BOOTSTD_FULL
- imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
- imply MISC
- imply ROCKCHIP_EFUSE
- imply MISC_INIT_R
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
and quad-core Cortex-A53.
imply MISC_INIT_R
imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
imply OF_LIBFDT_OVERLAY
+ imply OF_UPSTREAM
imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
imply MISC_INIT_R
imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
imply OF_LIBFDT_OVERLAY
+ imply OF_UPSTREAM
imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
bool "Support Rockchip RV1108"
select CPU_V7A
imply ROCKCHIP_COMMON_BOARD
+ imply OF_UPSTREAM
help
The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
and a DSP.
imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_SERIAL
imply SPL_SYSCON
+ imply OF_UPSTREAM
config ROCKCHIP_USB_UART
bool "Route uart output to usb pins"
config SYS_SOC
default "px30"
+config ROCKCHIP_COMMON_STACK_ADDR
+ default y
+
config SYS_MALLOC_F_LEN
- default 0x400
+ default 0x400 if !SPL_SHARES_INIT_SP_ADDR
config SPL_SERIAL
default y
config TPL_STACK
default 0xff0e4fff
+config TPL_SYS_MALLOC_F_LEN
+ default 0x600
+
config DEBUG_UART_CHANNEL
int "Mux channel to use for debug UART2/UART3"
depends on DEBUG_UART_BOARD_INIT
help
Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC.
+config TARGET_POWKIDDY_X55_RK3566
+ bool "Powkiddy X55"
+ help
+ Powkiddy X55 handheld gaming console with an RK3566 SoC.
+
config TARGET_QUARTZ64_RK3566
bool "Pine64 Quartz64"
help
source "board/anbernic/rgxx3_rk3566/Kconfig"
source "board/hardkernel/odroid_m1/Kconfig"
source "board/pine64/quartz64_rk3566/Kconfig"
+source "board/powkiddy/x55/Kconfig"
endif
Power: 5.5*2.1mm DC Jack, 12VDC input
Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)
+config TARGET_NOVA_RK3588
+ bool "Indiedroid Nova RK3588"
+ select BOARD_LATE_INIT
+ help
+ Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid.
+ It comes in configurations from 4GB of RAM to 16GB of RAM,
+ includes socket for eMMC storage, an SDMMC slot, and a 40-pin
+ GPIO header for expansion.
+
config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
source "board/edgeble/neural-compute-module-6/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
+source "board/indiedroid/nova/Kconfig"
source "board/pine64/quartzpro64-rk3588/Kconfig"
source "board/turing/turing-rk1-rk3588/Kconfig"
source "board/radxa/rock5a-rk3588s/Kconfig"
gd->arch.tlb_addr = tlb_addr;
gd->arch.tlb_size = tlb_size;
- carveout_start = get_timer(0);
- /* Takes ~20-50ms on SDM845 */
- carve_out_reserved_memory();
- debug("carveout time: %lums\n", get_timer(carveout_start));
-
+ /* We do the carveouts only for QCS404, for now. */
+ if (fdt_node_check_compatible(gd->fdt_blob, 0, "qcom,qcs404") == 0) {
+ carveout_start = get_timer(0);
+ /* Takes ~20-50ms on SDM845 */
+ carve_out_reserved_memory();
+ debug("carveout time: %lums\n", get_timer(carveout_start));
+ }
dcache_enable();
}
Sifive core devices that uses L2 cache to store SPL.
# board-specific options below
-source "board/AndesTech/ae350/Kconfig"
+source "board/andestech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/openpiton/riscv64/Kconfig"
source "board/xilinx/mbv/Kconfig"
# platform-specific options below
-source "arch/riscv/cpu/andesv5/Kconfig"
+source "arch/riscv/cpu/andes/Kconfig"
source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
-config RISCV_NDS
+config RISCV_ANDES
bool
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
imply ANDES_PLMT_TIMER
imply SPL_ANDES_PLMT_TIMER
imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
- imply V5L2_CACHE
+ imply ANDES_L2_CACHE
imply SPL_CPU
imply SPL_OPENSBI
imply SPL_LOAD_FIT
#include <dm/uclass-internal.h>
#include <asm/arch-andes/csr.h>
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
void enable_caches(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_CACHE,
- DM_DRIVER_GET(v5l2_cache),
+ DM_DRIVER_GET(andes_l2_cache),
&dev);
if (ret) {
- log_debug("Cannot enable v5l2 cache\n");
+ log_debug("Cannot enable Andes L2 cache\n");
} else {
ret = cache_enable(dev);
if (ret)
- log_debug("v5l2 cache enable failed\n");
+ log_debug("Failed to enable Andes L2 cache\n");
}
}
void flush_dcache_all(void)
{
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
- csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
-#endif
+ csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
}
void flush_dcache_range(unsigned long start, unsigned long end)
asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL));
#endif
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
cache_ops(cache_enable);
#endif
}
asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL));
#endif
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
cache_ops(cache_disable);
#endif
}
bnez s2, secondary_hart_loop
#endif
- /* Enable cache */
- jal icache_enable
- jal dcache_enable
-
#ifdef CONFIG_DEBUG_UART
jal debug_uart_init
#endif
#define CSR_MCACHE_CTL 0x7ca
#define CSR_MMISC_CTL 0x7d0
-#define CSR_MCCTLCOMMAND 0x7cc
+#define CSR_UCCTLCOMMAND 0x80c
/* mcache_ctl register */
u8 get_pcb_revision_from_eeprom(void);
u32 get_ddr_size_from_eeprom(void);
+/**
+ * get_mmc_size_from_eeprom() - read eMMC size from EEPROM
+ *
+ * @return: size in GiB or 0 on error.
+ */
+u32 get_mmc_size_from_eeprom(void);
+
/**
* get_product_id_from_eeprom - get product ID string
*
#endif
}
-#if defined(CONFIG_FRAMEPOINTER) || defined(CONFIG_SPL_FRAMEPOINTER)
-static void show_backtrace(struct pt_regs *regs)
+static void __maybe_unused show_backtrace(struct pt_regs *regs)
{
uintptr_t *fp = (uintptr_t *)regs->s0;
unsigned count = 0;
ulong ra;
- printf("backtrace:\n");
+ printf("\nbacktrace:\n");
/* there are a few entry points where the s0 register is
* set to gd, so to avoid changing those, just abort if
* the value is the same */
while (fp != NULL && fp != (uintptr_t *)gd) {
ra = fp[-1];
- printf("backtrace %2d: FP: " REG_FMT " RA: " REG_FMT,
+ printf("%3d: FP: " REG_FMT " RA: " REG_FMT,
count, (ulong)fp, ra);
if (gd && gd->flags & GD_FLG_RELOC)
count++;
}
}
-#else
-static void show_backtrace(struct pt_regs *regs)
-{
- printf("No backtrace support enabled\n");
-}
-#endif
/**
* instr_len() - get instruction length
epc - gd->reloc_off, regs->ra - gd->reloc_off);
show_regs(regs);
- show_backtrace(regs);
+ if (CONFIG_IS_ENABLED(FRAMEPOINTER))
+ show_backtrace(regs);
show_code(epc);
show_efi_loaded_images(epc);
panic("\n");
*/
#include <config.h>
+#include <stdio.h>
#include <vsprintf.h>
#include <env.h>
#include <net.h>
if TARGET_ANDES_AE350
config SYS_CPU
- default "andesv5"
+ default "andes"
config SYS_BOARD
default "ae350"
config SYS_VENDOR
- default "AndesTech"
+ default "andestech"
config SYS_SOC
default "ae350"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select RISCV_NDS
+ select RISCV_ANDES
select SUPPORT_SPL
select BINMAN if SPL
imply SMP
AE350 BOARD
M: Rick Chen <rick@andestech.com>
S: Maintained
-F: board/AndesTech/ae350/
+F: board/andestech/ae350/
F: include/configs/ae350.h
F: configs/ae350_rv32_defconfig
F: configs/ae350_rv32_falcon_defconfig
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init()
{
- /* enable v5l2 cache */
+ /* enable andes-l2 cache */
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
enable_caches();
}
VERSATILE EXPRESS BOARDS
-M: Kristian Amlie <kristian.amlie@northern.tech>
+M: Josef Holzmayr <josef.holzmayr@northern.tech>
S: Maintained
F: board/armltd/vexpress/
F: include/configs/vexpress_ca9x4.h
BEACON_RZG2M BOARD
M: Adam Ford <aford173@gmail.com>
+M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
F: board/beacon/beacon-rzg2m/
F: include/configs/beacon-rzg2m.h
static const struct lpddr4_desc lpddr4_array[] = {
{ .name = "Nanya", .id = 0x05000010, .subind = 0xff,
.size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
- { .name = "Samsung", .id = 0x01061010, .subind = 0xff,
+ { .name = "Samsung", .id = 0x01061010, .subind = 0x04,
+ .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
+ { .name = "Samsung", .id = 0x01061010, .subind = 0x02,
.size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
{ .name = "Kingston", .id = 0xff000010, .subind = 0x04,
.size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
#include <efi_loader.h>
#include <env.h>
#include <extension_board.h>
+#include <fdt_support.h>
#include <hang.h>
#include <i2c.h>
#include <init.h>
DECLARE_GLOBAL_DATA_PTR;
+static int fec_phyaddr = -1;
+
#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
struct efi_fw_image fw_images[] = {
#if defined(CONFIG_TARGET_IMX8MM_CL_IOT_GATE)
return 0;
}
+#define FDT_PHYADDR "/soc@0/bus@30800000/ethernet@30be0000/mdio/ethernet-phy@0"
+#define FLIP_32B(val) (((val >> 24) & 0xff) | ((val << 8) & 0xff0000) | ((val >> 8) & 0xff00) | ((val << 24) & 0xff000000))
+static int fdt_set_fec_phy_addr(void *blob)
+{
+ u32 val;
+
+ if (fec_phyaddr < 0)
+ return -EINVAL;
+
+ val = FLIP_32B(fec_phyaddr);
+ return fdt_find_and_setprop(blob, FDT_PHYADDR, "reg", (const void *)&val,
+ sizeof(val), 0);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ fdt_set_fec_phy_addr(blob);
+ return 0;
+}
+
+/*
+ * These are specific ID, purposed to distiguish between PHY vendors.
+ * These values are not equal to real vendors' OUI (half of MAC address)
+ */
+#define OUI_PHY_ATHEROS 0x1374
+#define OUI_PHY_REALTEK 0x0732
+
int board_phy_config(struct phy_device *phydev)
{
- if (IS_ENABLED(CONFIG_FEC_MXC)) {
+ unsigned int model, rev, oui;
+ int phyid1, phyid2;
+ unsigned int reg;
+
+ if (!IS_ENABLED(CONFIG_FEC_MXC))
+ return 0;
+
+ phyid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1);
+ if (phyid1 < 0) {
+ printf("%s: PHYID1 registry read fail %i\n", __func__, phyid1);
+ return phyid1;
+ }
+
+ phyid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2);
+ if (phyid2 < 0) {
+ printf("%s: PHYID2 registry read fail %i\n", __func__, phyid2);
+ return phyid2;
+ }
+
+ reg = phyid2 | phyid1 << 16;
+ if (reg == 0xffff) {
+ printf("%s: There is no device @%i\n", __func__, phydev->addr);
+ return -ENODEV;
+ }
+
+ rev = reg & 0xf;
+ reg >>= 4;
+ model = reg & 0x3f;
+ reg >>= 6;
+ oui = reg;
+ debug("%s: PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
+ __func__, phydev->addr, oui, model, rev);
+
+ switch (oui) {
+ case OUI_PHY_ATHEROS:
/* enable rgmii rxc skew and phy mode select to RGMII copper */
+ printf("phy: AR803x@%x\t", phydev->addr);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+ break;
+ case OUI_PHY_REALTEK:
+ printf("phy: RTL8211E@%x\t", phydev->addr);
+ /* RTL8211E-VB-CG - add TX and RX delay */
+ unsigned short val;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x07);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0xa4);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1c);
+ val |= (0x1 << 13) | (0x1 << 12) | (0x1 << 11);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, val);
+ /* LEDs: set to extension page */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0007);
+ /* extension Page44 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x002c);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, 0x0430);//LCR
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1a, 0x0010);//LACR
+ /*
+ * To disable EEE LED mode (blinking .4s/2s)
+ * Extension Page5
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x05, 0x8b82);//magic const
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x06, 0x052b);//magic const
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x00);// Back to Page0
- if (phydev->drv->config)
- phydev->drv->config(phydev);
+ break;
+ default:
+ printf("%s: ERROR: unknown PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
+ __func__, phydev->addr, oui, model, rev);
+ return -ENOSYS;
}
+
+ fec_phyaddr = phydev->addr;
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
return 0;
}
GO2
-M: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
+M: Heiko Stuebner <heiko.stuebner@cherry.de>
S: Maintained
F: board/hardkernel/odroid_go2/
F: include/configs/odroid_go2.h
--- /dev/null
+if TARGET_NOVA_RK3588
+
+config SYS_BOARD
+ default "nova-rk3588s"
+
+config SYS_VENDOR
+ default "indiedroid"
+
+config SYS_CONFIG_NAME
+ default "nova-rk3588s"
+
+endif
--- /dev/null
+INDIEDROID-NOVA-RK3588
+M: Chris Morgan <macromorgan@hotmail.com>
+S: Maintained
+F: board/indiedroid/nova
+F: configs/nova-rk3588s_defconfig
+F: include/configs/nova-rk3588s.h
#include <fdt_support.h>
#include "igep00x0.h"
-static const struct ns16550_plat igep_serial = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DRVINFO(igep_uart) = {
- "ns16550_serial",
- &igep_serial
-};
-
/*
* Routine: get_board_revision
* Description: GPIO_28 and GPIO_129 are used to read board and revision from
int board_late_init(void)
{
u32 ret;
- u32 node;
+ int node;
u8 idx;
u8 device_serial_number[16] = { 0 };
unsigned char mac_addr[6];
char icicle_mac_addr[20];
void *blob = (void *)gd->fdt_blob;
- node = fdt_path_offset(blob, "/soc/ethernet@20112000");
- if (node < 0) {
- printf("No ethernet0 path offset\n");
- return -ENODEV;
- }
-
- ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr, 6);
- if (ret) {
- printf("No local-mac-address property for ethernet@20112000\n");
- return -EINVAL;
- }
-
read_device_serial_number(device_serial_number, 16);
/* Update MAC address with device serial number */
mac_addr[4] = device_serial_number[1];
mac_addr[5] = device_serial_number[0];
- ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
- if (ret) {
- printf("Error setting local-mac-address property for ethernet@20112000\n");
- return -ENODEV;
+ node = fdt_path_offset(blob, "/soc/ethernet@20112000");
+ if (node >= 0) {
+ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+ if (ret) {
+ printf("Error setting local-mac-address property for ethernet@20112000\n");
+ return -ENODEV;
+ }
}
icicle_mac_addr[0] = '[';
M: Teresa Remmet <t.remmet@phytec.de>
W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/
S: Maintained
-F: arch/arm/dts/imx8mm-phyboard-polis-rdk.dts
-F: arch/arm/dts/imx8mm-phycore-som.dtsi
F: arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
-F: arch/arm/dts/imx8mm-phygate-tauri-l.dts
F: arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi
F: board/phytec/phycore_imx8mm/
F: configs/imx8mm-phygate-tauri-l_defconfig
config IMX_CONFIG
default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg"
+config PHYCORE_IMX8MP_RAM_SIZE_FIX
+ bool "Set phyCORE-i.MX8MP RAM size fix instead of detecting"
+ default false
+ help
+ RAM size is automatic being detected with the help of
+ the EEPROM introspection data. Set RAM size to a fix value
+ instead.
+
+choice
+ prompt "phyCORE-i.MX8MP RAM size"
+ depends on PHYCORE_IMX8MP_RAM_SIZE_FIX
+ default PHYCORE_IMX8MP_RAM_SIZE_2GB
+
+config PHYCORE_IMX8MP_RAM_SIZE_1GB
+ bool "1GB RAM"
+ help
+ Set RAM size fix to 1GB for phyCORE-i.MX8MP.
+ RAM frequency is configured independent.
+
+config PHYCORE_IMX8MP_RAM_SIZE_2GB
+ bool "2GB RAM"
+ help
+ Set RAM size fix to 2GB for phyCORE-i.MX8MP.
+ RAM frequency is configured independent.
+
+config PHYCORE_IMX8MP_RAM_SIZE_4GB
+ bool "4GB RAM"
+ help
+ Set RAM size fix to 4GB for phyCORE-i.MX8MP.
+ RAM frequency is configured independent.
+
+config PHYCORE_IMX8MP_RAM_SIZE_8GB
+ bool "8GB RAM"
+ select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
+ help
+ Set RAM size fix to 8GB for phyCORE-i.MX8MP.
+ Only 2GHz RAMs are supported.
+
+endchoice
+
+config PHYCORE_IMX8MP_RAM_FREQ_FIX
+ bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting"
+ default false
+ help
+ RAM frequency is automatic being detected with the help of
+ the EEPROM introspection data. Set RAM frequency to a fix value
+ instead.
+
+choice
+ prompt "phyCORE-i.MX8MP RAM frequency"
+ depends on PHYCORE_IMX8MP_RAM_FREQ_FIX
+ default PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS
+
+config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
+ bool "Use 2GHz RAM timings"
+ help
+ Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of
+ 1.5GHz timings.
+
+config PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS
+ depends on !PHYCORE_IMX8MP_RAM_SIZE_8GB
+ bool "Use 1.5GHz RAM timings"
+ help
+ Use fix 1.5GHz RAM timings for phyCORE-i.MX8MP instead of
+ 2GHz timings.
+endchoice
+
source "board/phytec/common/Kconfig"
endif
M: Teresa Remmet <t.remmet@phytec.de>
W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-plus/
S: Maintained
-F: arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
F: arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
F: board/phytec/phycore_imx8mp/
F: configs/phycore-imx8mp_defconfig
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3000, 400, 100, },
};
+
+void set_dram_timings_2ghz_2gb(void)
+{
+ dram_timing.ddrc_cfg[3].val = 0x1323;
+ dram_timing.ddrc_cfg[4].val = 0x1e84800;
+ dram_timing.ddrc_cfg[5].val = 0x7a0118;
+ dram_timing.ddrc_cfg[8].val = 0xc00307a3;
+ dram_timing.ddrc_cfg[9].val = 0xc50000;
+ dram_timing.ddrc_cfg[10].val = 0xf4003f;
+ dram_timing.ddrc_cfg[11].val = 0xf30000;
+ dram_timing.ddrc_cfg[14].val = 0x2028222a;
+ dram_timing.ddrc_cfg[15].val = 0x8083f;
+ dram_timing.ddrc_cfg[16].val = 0xe0e000;
+ dram_timing.ddrc_cfg[17].val = 0x12040a12;
+ dram_timing.ddrc_cfg[18].val = 0x2050f0f;
+ dram_timing.ddrc_cfg[19].val = 0x1010009;
+ dram_timing.ddrc_cfg[20].val = 0x502;
+ dram_timing.ddrc_cfg[21].val = 0x20800;
+ dram_timing.ddrc_cfg[22].val = 0xe100002;
+ dram_timing.ddrc_cfg[23].val = 0x120;
+ dram_timing.ddrc_cfg[24].val = 0xc80064;
+ dram_timing.ddrc_cfg[25].val = 0x3e8001e;
+ dram_timing.ddrc_cfg[26].val = 0x3207a12;
+ dram_timing.ddrc_cfg[28].val = 0x4a3820e;
+ dram_timing.ddrc_cfg[30].val = 0x230e;
+ dram_timing.ddrc_cfg[37].val = 0x799;
+ dram_timing.ddrc_cfg[38].val = 0x9141d1c;
+ dram_timing.ddrc_cfg[74].val = 0x302;
+ dram_timing.ddrc_cfg[83].val = 0x599;
+ dram_timing.ddrc_cfg[99].val = 0x302;
+ dram_timing.ddrc_cfg[108].val = 0x599;
+ dram_timing.ddrphy_cfg[66].val = 0x18;
+ dram_timing.ddrphy_cfg[75].val = 0x1e3;
+ dram_timing.ddrphy_cfg[77].val = 0x1e3;
+ dram_timing.ddrphy_cfg[79].val = 0x1e3;
+ dram_timing.ddrphy_cfg[145].val = 0x3e8;
+ dram_timing.fsp_msg[0].drate = 4000;
+ dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
+ dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
+ dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
+ dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
+ dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
+ dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
+ dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
+ dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
+ dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
+ dram_timing.fsp_msg[3].drate = 4000;
+ dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
+ dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
+ dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
+ dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
+ dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
+ dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
+ dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
+ dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
+ dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
+ dram_timing.ddrphy_pie[480].val = 0x465;
+ dram_timing.ddrphy_pie[481].val = 0xfa;
+ dram_timing.ddrphy_pie[482].val = 0x9c4;
+ dram_timing.fsp_table[0] = 4000;
+}
+
+void set_dram_timings_1_5ghz_1gb(void)
+{
+ dram_timing.ddrc_cfg[3].val = 0x1233;
+ dram_timing.ddrc_cfg[5].val = 0x5b0087;
+ dram_timing.ddrc_cfg[6].val = 0x61027f10;
+ dram_timing.ddrc_cfg[7].val = 0x7b0;
+ dram_timing.ddrc_cfg[11].val = 0xf30000;
+ dram_timing.ddrc_cfg[23].val = 0x8d;
+ dram_timing.ddrc_cfg[45].val = 0xf070707;
+ dram_timing.ddrc_cfg[59].val = 0x1031;
+ dram_timing.ddrc_cfg[62].val = 0xc0012;
+ dram_timing.ddrc_cfg[77].val = 0x13;
+ dram_timing.ddrc_cfg[84].val = 0x1031;
+ dram_timing.ddrc_cfg[87].val = 0x30005;
+ dram_timing.ddrc_cfg[102].val = 0x5;
+ dram_timing.ddrphy_cfg[75].val = 0x1e3;
+ dram_timing.ddrphy_cfg[77].val = 0x1e3;
+ dram_timing.ddrphy_cfg[79].val = 0x1e3;
+ dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
+ dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
+ dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf32d;
+ dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf32d;
+ dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
+ dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
+ dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf32d;
+ dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf32d;
+}
+
+void set_dram_timings_2ghz_1gb(void)
+{
+ set_dram_timings_2ghz_2gb();
+ dram_timing.ddrc_cfg[5].val = 0x7a00b4;
+ dram_timing.ddrc_cfg[23].val = 0xbc;
+ dram_timing.ddrc_cfg[45].val = 0xf070707;
+ dram_timing.ddrc_cfg[62].val = 0xc0012;
+ dram_timing.ddrc_cfg[77].val = 0x13;
+ dram_timing.ddrc_cfg[87].val = 0x30005;
+ dram_timing.ddrc_cfg[102].val = 0x5;
+}
+
+void set_dram_timings_1_5ghz_4gb(void)
+{
+ dram_timing.ddrc_cfg[2].val = 0xa3080020;
+ dram_timing.ddrc_cfg[39].val = 0x17;
+ dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
+ dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
+ dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
+ dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
+ dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+}
+
+void set_dram_timings_2ghz_4gb(void)
+{
+ set_dram_timings_2ghz_2gb();
+ dram_timing.ddrc_cfg[2].val = 0xa3080020;
+ dram_timing.ddrc_cfg[39].val = 0x17;
+ dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
+ dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
+ dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
+ dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
+ dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+}
+
+void set_dram_timings_2ghz_8gb(void)
+{
+ set_dram_timings_2ghz_2gb();
+ dram_timing.ddrc_cfg[2].val = 0xa3080020;
+ dram_timing.ddrc_cfg[5].val = 0x7a017c;
+ dram_timing.ddrc_cfg[23].val = 0x184;
+ dram_timing.ddrc_cfg[39].val = 0x18;
+ dram_timing.ddrc_cfg[46].val = 0xf07;
+ dram_timing.ddrc_cfg[62].val = 0xc0026;
+ dram_timing.ddrc_cfg[77].val = 0x27;
+ dram_timing.ddrc_cfg[87].val = 0x3000a;
+ dram_timing.ddrc_cfg[102].val = 0xa;
+
+ dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
+ dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
+ dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
+ dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
+ dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+ dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+void set_dram_timings_2ghz_2gb(void);
+void set_dram_timings_2ghz_1gb(void);
+void set_dram_timings_2ghz_4gb(void);
+void set_dram_timings_1_5ghz_1gb(void);
+void set_dram_timings_1_5ghz_4gb(void);
+void set_dram_timings_2ghz_8gb(void);
+
+#endif /* __LPDDR4_TIMING_H__ */
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
+#include <init.h>
#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ if (!size)
+ return -EINVAL;
+
+ *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
+
+ return 0;
+}
#include <power/pca9450.h>
#include <spl.h>
+#include "lpddr4_timing.h"
#include "../common/imx8m_som_detection.h"
DECLARE_GLOBAL_DATA_PTR;
-#define EEPROM_ADDR 0x51
-#define EEPROM_ADDR_FALLBACK 0x59
+#define EEPROM_ADDR 0x51
+#define EEPROM_ADDR_FALLBACK 0x59
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
+enum phytec_imx8mp_ddr_eeprom_code {
+ PHYTEC_IMX8MP_DDR_1GB = 2,
+ PHYTEC_IMX8MP_DDR_2GB = 3,
+ PHYTEC_IMX8MP_DDR_4GB = 5,
+ PHYTEC_IMX8MP_DDR_8GB = 7,
+ PHYTEC_IMX8MP_DDR_4GB_2GHZ = 8,
+};
+
void spl_dram_init(void)
{
int ret;
+ bool use_2ghz_timings = false;
+ enum phytec_imx8mp_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL;
ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
EEPROM_ADDR_FALLBACK);
- if (ret)
+ if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX))
goto out;
ret = phytec_imx8m_detect(NULL);
if (!ret)
phytec_print_som_info(NULL);
- u8 rev = phytec_get_rev(NULL);
- u8 somtype = phytec_get_som_type(NULL);
-
- if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) {
- dram_timing.ddrc_cfg[3].val = 0x1323;
- dram_timing.ddrc_cfg[4].val = 0x1e84800;
- dram_timing.ddrc_cfg[5].val = 0x7a0118;
- dram_timing.ddrc_cfg[8].val = 0xc00307a3;
- dram_timing.ddrc_cfg[9].val = 0xc50000;
- dram_timing.ddrc_cfg[10].val = 0xf4003f;
- dram_timing.ddrc_cfg[11].val = 0xf30000;
- dram_timing.ddrc_cfg[14].val = 0x2028222a;
- dram_timing.ddrc_cfg[15].val = 0x8083f;
- dram_timing.ddrc_cfg[16].val = 0xe0e000;
- dram_timing.ddrc_cfg[17].val = 0x12040a12;
- dram_timing.ddrc_cfg[18].val = 0x2050f0f;
- dram_timing.ddrc_cfg[19].val = 0x1010009;
- dram_timing.ddrc_cfg[20].val = 0x502;
- dram_timing.ddrc_cfg[21].val = 0x20800;
- dram_timing.ddrc_cfg[22].val = 0xe100002;
- dram_timing.ddrc_cfg[23].val = 0x120;
- dram_timing.ddrc_cfg[24].val = 0xc80064;
- dram_timing.ddrc_cfg[25].val = 0x3e8001e;
- dram_timing.ddrc_cfg[26].val = 0x3207a12;
- dram_timing.ddrc_cfg[28].val = 0x4a3820e;
- dram_timing.ddrc_cfg[30].val = 0x230e;
- dram_timing.ddrc_cfg[37].val = 0x799;
- dram_timing.ddrc_cfg[38].val = 0x9141d1c;
- dram_timing.ddrc_cfg[74].val = 0x302;
- dram_timing.ddrc_cfg[83].val = 0x599;
- dram_timing.ddrc_cfg[99].val = 0x302;
- dram_timing.ddrc_cfg[108].val = 0x599;
- dram_timing.ddrphy_cfg[66].val = 0x18;
- dram_timing.ddrphy_cfg[75].val = 0x1e3;
- dram_timing.ddrphy_cfg[77].val = 0x1e3;
- dram_timing.ddrphy_cfg[79].val = 0x1e3;
- dram_timing.ddrphy_cfg[145].val = 0x3e8;
- dram_timing.fsp_msg[0].drate = 4000;
- dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
- dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
- dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
- dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
- dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
- dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
- dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
- dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
- dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
- dram_timing.fsp_msg[3].drate = 4000;
- dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
- dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
- dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
- dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
- dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
- dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
- dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
- dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
- dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
- dram_timing.ddrphy_pie[480].val = 0x465;
- dram_timing.ddrphy_pie[481].val = 0xfa;
- dram_timing.ddrphy_pie[482].val = 0x9c4;
- dram_timing.fsp_table[0] = 4000;
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) {
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_1GB))
+ size = PHYTEC_IMX8MP_DDR_1GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_2GB))
+ size = PHYTEC_IMX8MP_DDR_2GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_4GB))
+ size = PHYTEC_IMX8MP_DDR_4GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB))
+ size = PHYTEC_IMX8MP_DDR_8GB;
+ } else {
+ size = phytec_get_imx8m_ddr_size(NULL);
+ }
+
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_FREQ_FIX)) {
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) {
+ if (size == PHYTEC_IMX8MP_DDR_4GB)
+ size = PHYTEC_IMX8MP_DDR_4GB_2GHZ;
+ else
+ use_2ghz_timings = true;
+ } else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS)) {
+ if (size == PHYTEC_IMX8MP_DDR_4GB_2GHZ)
+ size = PHYTEC_IMX8MP_DDR_4GB;
+ else
+ use_2ghz_timings = false;
+ }
+ } else {
+ u8 rev = phytec_get_rev(NULL);
+ u8 somtype = phytec_get_som_type(NULL);
+
+ if (rev != PHYTEC_EEPROM_INVAL &&
+ (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1)))
+ use_2ghz_timings = true;
}
+ switch (size) {
+ case PHYTEC_IMX8MP_DDR_1GB:
+ if (use_2ghz_timings)
+ set_dram_timings_2ghz_1gb();
+ else
+ set_dram_timings_1_5ghz_1gb();
+ break;
+ case PHYTEC_IMX8MP_DDR_2GB:
+ if (use_2ghz_timings)
+ set_dram_timings_2ghz_2gb();
+ break;
+ case PHYTEC_IMX8MP_DDR_4GB:
+ set_dram_timings_1_5ghz_4gb();
+ break;
+ case PHYTEC_IMX8MP_DDR_4GB_2GHZ:
+ set_dram_timings_2ghz_4gb();
+ break;
+ case PHYTEC_IMX8MP_DDR_8GB:
+ set_dram_timings_2ghz_8gb();
+ break;
+ default:
+ goto out;
+ }
+ ddr_init(&dram_timing);
+ return;
out:
+ printf("Could not detect correct RAM size. Fallback to default.\n");
ddr_init(&dram_timing);
}
--- /dev/null
+if TARGET_POWKIDDY_X55_RK3566
+
+config SYS_BOARD
+ default "x55"
+
+config SYS_VENDOR
+ default "powkiddy"
+
+config SYS_CONFIG_NAME
+ default "powkiddy-x55-rk3566"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+
+endif
--- /dev/null
+X55
+M: Chris Morgan <macromorgan@hotmail.com>
+S: Maintained
+F: board/powkiddy/x55
+F: include/configs/powkiddy-x55-rk3566.h
+F: configs/powkiddy-x55-rk3566_defconfig
+F: arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2023 Chris Morgan <macromorgan@hotmail.com>
+#
+
+obj-y += x55.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Chris Morgan <macromorgan@hotmail.com>
+ */
+
+#include <asm/io.h>
+
+#define GPIO4_BASE 0xfe770000
+#define GPIO_SWPORT_DR_L 0x0000
+#define GPIO_SWPORT_DDR_L 0x0008
+#define GPIO_B4 BIT(12)
+#define GPIO_B5 BIT(13)
+#define GPIO_B6 BIT(14)
+
+#define GPIO_WRITEMASK(bits) ((bits) << 16)
+
+/*
+ * Start LED very early so user knows device is on. Set color
+ * to red.
+ */
+void spl_board_init(void)
+{
+ /* Set GPIO4_B4, GPIO4_B5, and GPIO4_B6 to output. */
+ writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | \
+ (GPIO_B6 | GPIO_B5 | GPIO_B4),
+ (GPIO4_BASE + GPIO_SWPORT_DDR_L));
+ /* Set GPIO4_B5 and GPIO4_B6 to 0 and GPIO4_B4 to 1. */
+ writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | GPIO_B4,
+ (GPIO4_BASE + GPIO_SWPORT_DR_L));
+}
+
+int rk_board_late_init(void)
+{
+ /* Turn off red LED and turn on orange LED. */
+ writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | GPIO_B6,
+ (GPIO4_BASE + GPIO_SWPORT_DR_L));
+
+ return 0;
+}
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: arch/arm/dts/exynos850-e850-96-u-boot.dtsi
-F: arch/arm/dts/exynos850-e850-96.dts
F: board/samsung/e850-96/
F: configs/e850-96_defconfig
F: doc/board/samsung/e850-96.rst
imply PHY_LIB
imply PHY_MSCC
+config STARFIVE_NO_EMMC
+ bool "Report eMMC size as zero"
+ help
+ The serial number string in the EEPROM is meant to report the
+ size of onboard eMMC. Unfortunately some Milk-V Mars CM Lite
+ modules without eMMC show a non-zero size here.
+
+ Set to 'Y' if you have a Mars CM Lite module.
+
endif
"tx-internal-delay-ps", "0"},
};
+static const struct starfive_vf2_pro star64_pine64[] = {
+ {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
+ {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
+
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-10-inverted", NULL},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-1000-inverted", NULL},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,rx-clk-drv-microamp", "2910"},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,rx-data-drv-microamp", "2910"},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "rx-internal-delay-ps", "1900"},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "tx-internal-delay-ps", "1500"},
+
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-10-inverted", NULL},
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "motorcomm,rx-clk-drv-microamp", "2910"},
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "motorcomm,rx-data-drv-microamp", "2910"},
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "rx-internal-delay-ps", "0"},
+ {"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+ "tx-internal-delay-ps", "300"},
+};
+
void spl_fdt_fixup_mars(void *fdt)
{
static const char compat[] = "milkv,mars\0starfive,jh7110";
}
}
+void spl_fdt_fixup_mars_cm(void *fdt)
+{
+ const char *compat;
+ const char *model;
+
+ spl_fdt_fixup_mars(fdt);
+
+ if (!get_mmc_size_from_eeprom()) {
+ int offset;
+
+ model = "Milk-V Mars CM Lite";
+ compat = "milkv,mars-cm-lite\0starfive,jh7110";
+
+ offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest");
+ /* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */
+ fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016);
+ } else {
+ model = "Milk-V Mars CM";
+ compat = "milkv,mars-cm\0starfive,jh7110";
+ }
+ fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model);
+}
+
void spl_fdt_fixup_version_a(void *fdt)
{
static const char compat[] = "starfive,visionfive-2-v1.2a\0starfive,jh7110";
}
}
+void spl_fdt_fixup_star64(void *fdt)
+{
+ static const char compat[] = "pine64,star64\0starfive,jh7110";
+ u32 phandle;
+ u8 i;
+ int offset;
+ int ret;
+
+ fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+ "Pine64 Star64");
+
+ /* gmac0 */
+ offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
+ phandle = fdt_get_phandle(fdt, offset);
+ offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
+
+ fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
+ fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_AONCLK_GMAC0_RMII_RTX);
+
+ /* gmac1 */
+ offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
+ phandle = fdt_get_phandle(fdt, offset);
+ offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
+
+ fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
+ fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_SYSCLK_GMAC1_RMII_RTX);
+
+ for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) {
+ offset = fdt_path_offset(fdt, star64_pine64[i].path);
+
+ if (star64_pine64[i].value)
+ ret = fdt_setprop_u32(fdt, offset, star64_pine64[i].name,
+ dectoul(star64_pine64[i].value, NULL));
+ else
+ ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name);
+
+ if (ret) {
+ pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name);
+ break;
+ }
+ }
+}
+
void spl_perform_fixups(struct spl_image_info *spl_image)
{
u8 version;
pr_err("Can't read EEPROM\n");
return;
}
- if (!strncmp(product_id, "MARS", 4)) {
+ if (!strncmp(product_id, "MARC", 4)) {
+ spl_fdt_fixup_mars_cm(spl_image->fdt_addr);
+ } else if (!strncmp(product_id, "MARS", 4)) {
spl_fdt_fixup_mars(spl_image->fdt_addr);
} else if (!strncmp(product_id, "VF7110", 6)) {
version = get_pcb_revision_from_eeprom();
spl_fdt_fixup_version_b(spl_image->fdt_addr);
break;
};
+ } else if (!strncmp(product_id, "STAR64", 6)) {
+ spl_fdt_fixup_star64(spl_image->fdt_addr);
} else {
pr_err("Unknown product %s\n", product_id);
};
#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
#define FDTFILE_MILK_V_MARS \
"starfive/jh7110-milkv-mars.dtb"
+#define FDTFILE_MILK_V_MARS_CM \
+ "starfive/jh7110-milkv-mars-cm.dtb"
+#define FDTFILE_MILK_V_MARS_CM_LITE \
+ "starfive/jh7110-milkv-mars-cm-lite.dtb"
#define FDTFILE_VISIONFIVE2_1_2A \
"starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
#define FDTFILE_VISIONFIVE2_1_3B \
"starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+#define FDTFILE_PINE64_STAR64 \
+ "starfive/jh7110-pine64-star64.dtb"
/* enable U74-mc hart1~hart4 prefetcher */
static void enable_prefetcher(void)
log_err("Can't read EEPROM\n");
return;
}
- if (!strncmp(product_id, "MARS", 4)) {
+ if (!strncmp(product_id, "MARC", 4)) {
+ if (get_mmc_size_from_eeprom())
+ fdtfile = FDTFILE_MILK_V_MARS_CM;
+ else
+ fdtfile = FDTFILE_MILK_V_MARS_CM_LITE;
+ } else if (!strncmp(product_id, "MARS", 4)) {
fdtfile = FDTFILE_MILK_V_MARS;
} else if (!strncmp(product_id, "VF7110", 6)) {
version = get_pcb_revision_from_eeprom();
fdtfile = FDTFILE_VISIONFIVE2_1_3B;
break;
}
+ } else if (!strncmp(product_id, "STAR64", 6)) {
+ fdtfile = FDTFILE_PINE64_STAR64;
} else {
log_err("Unknown product\n");
return;
update_crc();
}
+/**
+ * set_vendor() - set vendor name
+ *
+ * Takes a pointer to a string representing the vendor name, e.g.
+ * "StarFive Technology Co., Ltd.", stores it in the vendor field
+ * of the EEPROM local copy, and updates the CRC of the local copy.
+ */
+static void set_vendor(char *string)
+{
+ memset(pbuf.eeprom.atom1.data.vstr, 0,
+ sizeof(pbuf.eeprom.atom1.data.vstr));
+
+ strncpy(pbuf.eeprom.atom1.data.vstr,
+ string, sizeof(pbuf.eeprom.atom1.data.vstr) - 1);
+
+ update_crc();
+}
+
const char *get_product_id_from_eeprom(void)
{
if (read_eeprom())
} else if (!strcmp(cmd, "product_id")) {
set_product_id(argv[2]);
return 0;
+ } else if (!strcmp(cmd, "vendor")) {
+ set_vendor(argv[2]);
+ return 0;
}
return CMD_RET_USAGE;
return hextoul(&pbuf.eeprom.atom1.data.pstr[14], NULL);
}
+u32 get_mmc_size_from_eeprom(void)
+{
+ u32 size;
+
+ if (IS_ENABLED(CONFIG_STARFIVE_NO_EMMC))
+ return 0;
+
+ if (read_eeprom())
+ return 0;
+
+ size = dectoul(&pbuf.eeprom.atom1.data.pstr[19], NULL);
+
+ if (pbuf.eeprom.atom1.data.pstr[21] == 'T')
+ size <<= 10;
+
+ return size;
+}
+
U_BOOT_LONGHELP(mac,
"\n"
" - display EEPROM content\n"
"mac bom_revision <A>\n"
" - stores a StarFive BOM revision into the local EEPROM copy\n"
"mac product_id <VF7110A1-2228-D008E000-xxxxxxxx>\n"
- " - stores a StarFive product ID into the local EEPROM copy\n");
+ " - stores a StarFive product ID into the local EEPROM copy\n"
+ "mac vendor <Vendor Name>\n"
+ " - set vendor string\n");
U_BOOT_CMD(
mac, 3, 1, do_mac,
JAGUAR-RK3588 (SBC-RK3588-AMR Single Board Computer)
-M: Klaus Goger <klaus.goger@theobroma-systems.com>
-M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
+M: Klaus Goger <klaus.goger@cherry.de>
+M: Quentin Schulz <quentin.schulz@cherry.de>
M: Heiko Stuebner <heiko.stuebner@cherry.de>
S: Maintained
F: board/theobroma-systems/jaguar_rk3588
F: include/configs/jaguar_rk3588.h
F: arch/arm/dts/rk3588-jaguar*
F: configs/jaguar-rk3588_defconfig
-W: https://theobroma-systems.com/product/jaguar-sbc-rk3588/
-T: git git://git.theobroma-systems.com/jaguar-u-boot.git
+W: https://embedded.cherry.de/product/jaguar-sbc-rk3588/
+T: git git://git.embedded.cherry.de/jaguar-u-boot.git
LION-RK3368 (RK3368-uQ7 system-on-module)
-M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
-M: Klaus Goger <klaus.goger@theobroma-systems.com>
+M: Quentin Schulz <quentin.schulz@cherry.de>
+M: Klaus Goger <klaus.goger@cherry.de>
S: Maintained
F: board/theobroma-systems/lion_rk3368
F: include/configs/lion_rk3368.h
PUMA-RK3399
-M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
-M: Klaus Goger <klaus.goger@theobroma-systems.com>
+M: Quentin Schulz <quentin.schulz@cherry.de>
+M: Klaus Goger <klaus.goger@cherry.de>
S: Maintained
F: board/theobroma-systems/puma_rk3399
F: board/theobroma-systems/common
F: include/configs/puma_rk3399.h
F: arch/arm/dts/rk3399-puma*
F: configs/puma-rk3399_defconfig
-W: https://www.theobroma-systems.com/rk3399-q7/tech-specs
-T: git git://git.theobroma-systems.com/puma-u-boot.git
+W: https://embedded.cherry.de/product/puma-som-rk3399-q7/
+T: git git://git.embedded.cherry.de/puma-u-boot.git
RINGNECK-PX30
-M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
-M: Klaus Goger <klaus.goger@theobroma-systems.com>
+M: Quentin Schulz <quentin.schulz@cherry.de>
+M: Klaus Goger <klaus.goger@cherry.de>
S: Maintained
F: board/theobroma-systems/ringneck_px30
F: board/theobroma-systems/common
F: include/configs/ringneck_px30.h
F: arch/arm/dts/px30-ringneck*
F: configs/ringneck-px30_defconfig
-W: https://theobroma-systems.com/product/ringneck-som-px30-uq7/
+W: https://embedded.cherry.de/product/ringneck-som-px30-uq7/
+T: git git://git.embedded.cherry.de/ringneck-u-boot.git
*/
#include <env.h>
-#include <vsprintf.h>
+#include <stdio.h>
#include "fdt_ops.h"
void ti_set_fdt_env(const char *board_name, struct ti_fdt_map *fdt_map)
F: include/configs/j721s2_evm.h
F: configs/j721s2_evm_r5_defconfig
F: configs/j721s2_evm_a72_defconfig
-F: arch/arm/dts/k3-j721s2.dtsi
-F: arch/arm/dts/k3-j721s2-main.dtsi
-F: arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
-F: arch/arm/dts/k3-j721s2-thermal.dtsi
-F: arch/arm/dts/k3-j721s2-som-p0.dtsi
-F: arch/arm/dts/k3-j721s2-common-proc-board.dts
+F: configs/am68_sk_r5_defconfig
+F: configs/am68_sk_a72_defconfig
F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+F: arch/arm/dts/k3-j721s2-r5.dtsi
F: arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
F: arch/arm/dts/k3-j721s2-ddr.dtsi
F: arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
-F: arch/arm/dts/k3-am68-sk-som.dtsi
-F: arch/arm/dts/k3-am68-sk-base-board.dts
F: arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
F: arch/arm/dts/k3-am68-sk-r5-base-board.dts
${mtdparts}
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+boot_targets=mmc1 mmc0 usb pxe dhcp
boot=mmc
mmcdev=1
bootpart=1:2
Apalis iMX8
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
S: Maintained
F: arch/arm/dts/fsl-imx8qm-apalis.dts
Apalis TK1
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
F: board/toradex/apalis-tk1/
F: board/toradex/common/
Apalis iMX6
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
Apalis T30
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
F: board/toradex/apalis_t30/
F: board/toradex/common/
Colibri iMX6ULL
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
Colibri iMX8X
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
S: Maintained
F: arch/arm/dts/fsl-imx8x-colibri.dts
Colibri iMX6
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
Colibri iMX7
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
COLIBRI_T20
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
F: board/toradex/colibri_t20/
F: board/toradex/common/
Colibri T30
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
F: board/toradex/colibri_t30/
F: board/toradex/common/
Colibri VFxx
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
[85] = { "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) },
[86] = { "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
[87] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
+ [88] = { "Aquila AM69 Octa 32GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) },
+ [89] = { "Verdin iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) },
+ [90] = { "Verdin iMX8M Mini Quad 4GB WB ET", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
};
struct pid4list {
APALIS_IMX6Q_IT_NOWINCE, /* 85 */
VERDIN_IMX8MMDL_2G_IT,
VERDIN_IMX8MMQ_2G_IT_NO_CAN,
+ AQUILA_AM69O_32G_WIFI_BT_IT,
+ VERDIN_IMX95H_16G_WIFI_BT_IT,
+ VERDIN_IMX8MMQ_4G_WIFI_BT_ET, /* 90 */
};
enum {
F: configs/verdin-am62_r5_defconfig
F: doc/board/toradex/verdin-am62.rst
F: include/configs/verdin-am62.h
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am-62
Verdin iMX8M Mini
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini
S: Maintained
F: arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
{0x3d400000, 0xa1080020},
{0x3d400020, 0x202},
{0x3d400024, 0x3a980},
- {0x3d400064, 0x2d00d2},
+ {0x3d400064, 0x2d011d},
{0x3d4000d0, 0xc00305ba},
{0x3d4000d4, 0x940000},
{0x3d4000dc, 0xd4002d},
{0x3d40011c, 0x402},
{0x3d400130, 0x20600},
{0x3d400134, 0xc100002},
- {0x3d400138, 0xd8},
+ {0x3d400138, 0x123},
{0x3d400144, 0x96004b},
{0x3d400180, 0x2ee0017},
{0x3d400184, 0x2605b8e},
{0x3d400204, 0x80808},
{0x3d400214, 0x7070707},
{0x3d400218, 0x7070707},
- {0x3d40021c, 0xf0f},
+ {0x3d40021c, 0xf07},
{0x3d400250, 0x29001701},
{0x3d400254, 0x2c},
{0x3d40025c, 0x4000030},
{0x3d402020, 0x0},
{0x3d402024, 0x7d00},
{0x3d402050, 0x20d040},
- {0x3d402064, 0x6001c},
+ {0x3d402064, 0x60026},
{0x3d4020dc, 0x840000},
{0x3d4020e0, 0x310000},
{0x3d4020e8, 0x66004d},
{0x3d40211c, 0x302},
{0x3d402130, 0x20300},
{0x3d402134, 0xa100002},
- {0x3d402138, 0x1d},
+ {0x3d402138, 0x27},
{0x3d402144, 0x14000a},
{0x3d402180, 0x640004},
{0x3d402190, 0x3818200},
{0x3d403020, 0x0},
{0x3d403024, 0x1f40},
{0x3d403050, 0x20d040},
- {0x3d403064, 0x30007},
+ {0x3d403064, 0x3000A},
{0x3d4030dc, 0x840000},
{0x3d4030e0, 0x310000},
{0x3d4030e8, 0x66004d},
{0x3d40311c, 0x302},
{0x3d403130, 0x20300},
{0x3d403134, 0xa100002},
- {0x3d403138, 0x8},
+ {0x3d403138, 0xA},
{0x3d403144, 0x50003},
{0x3d403180, 0x190004},
{0x3d403190, 0x3818200},
*/
is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) ||
(tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT) ||
- (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN);
+ (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN) ||
+ (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET);
}
switch (get_pcb_revision()) {
if (!size)
return -EINVAL;
- *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
return 0;
}
F: configs/verdin-imx8mp_defconfig
F: doc/board/toradex/verdin-imx8mp.rst
F: include/configs/verdin-imx8mp.h
-M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus
#include <image.h>
#include <bootstage.h>
#include <u-boot/crc.h>
-#include <u-boot/md5.h>
-#include <u-boot/sha1.h>
-#include <u-boot/sha256.h>
-#include <u-boot/sha512.h>
/*****************************************************************************/
/* New uImage format routines */
#endif
#include <asm/global_data.h>
-#include <u-boot/md5.h>
-#include <u-boot/sha1.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <linux/types.h>
-static void print_mdata(struct fwu_mdata *mdata)
+static void print_mdata(struct fwu_data *data)
{
int i, j;
struct fwu_image_entry *img_entry;
struct fwu_image_bank_info *img_info;
printf("\tFWU Metadata\n");
- printf("crc32: %#x\n", mdata->crc32);
- printf("version: %#x\n", mdata->version);
- printf("active_index: %#x\n", mdata->active_index);
- printf("previous_active_index: %#x\n", mdata->previous_active_index);
+ printf("crc32: %#x\n", data->crc32);
+ printf("version: %#x\n", data->version);
+ printf("active_index: %#x\n", data->active_index);
+ printf("previous_active_index: %#x\n", data->previous_active_index);
+
+ if (data->version == 2) {
+ for (i = 0; i < 4; i++)
+ printf("bank_state[%d]: %#x\n",
+ i, data->bank_state[i]);
+ }
printf("\tImage Info\n");
for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
- img_entry = &mdata->img_entry[i];
+ img_entry = &data->fwu_images[i];
printf("\nImage Type Guid: %pUL\n",
- &img_entry->image_type_uuid);
- printf("Location Guid: %pUL\n", &img_entry->location_uuid);
+ &img_entry->image_type_guid);
+ printf("Location Guid: %pUL\n", &img_entry->location_guid);
for (j = 0; j < CONFIG_FWU_NUM_BANKS; j++) {
img_info = &img_entry->img_bank_info[j];
- printf("Image Guid: %pUL\n", &img_info->image_uuid);
+ printf("Image Guid: %pUL\n", &img_info->image_guid);
printf("Image Acceptance: %s\n",
img_info->accepted == 0x1 ? "yes" : "no");
}
int do_fwu_mdata_read(struct cmd_tbl *cmdtp, int flag,
int argc, char * const argv[])
{
- int ret = CMD_RET_SUCCESS, res;
- struct fwu_mdata mdata;
-
- res = fwu_get_mdata(&mdata);
- if (res < 0) {
- log_err("Unable to get valid FWU metadata\n");
- ret = CMD_RET_FAILURE;
- goto out;
- }
+ struct fwu_data *data = fwu_get_data();
- print_mdata(&mdata);
+ print_mdata(data);
-out:
- return ret;
+ return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
#include <command.h>
#include <env.h>
#include <part.h>
+#include <stdio.h>
#include <vsprintf.h>
enum cmd_part_info {
struct tpm_chip_priv *priv;
u32 index = simple_strtoul(argv[1], NULL, 0);
void *digest = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
+ int algo = TPM2_ALG_SHA256;
+ int algo_len;
int ret;
u32 rc;
- if (argc != 3)
+ if (argc < 3 || argc > 4)
return CMD_RET_USAGE;
+ if (argc == 4) {
+ algo = tpm2_name_to_algorithm(argv[3]);
+ if (algo < 0)
+ return CMD_RET_FAILURE;
+ }
+ algo_len = tpm2_algorithm_to_len(algo);
ret = get_tpm(&dev);
if (ret)
if (index >= priv->pcr_count)
return -EINVAL;
- rc = tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, digest,
- TPM2_DIGEST_LEN);
+ rc = tpm2_pcr_extend(dev, index, algo, digest, algo_len);
+ if (!rc) {
+ printf("PCR #%u extended with %d byte %s digest\n", index,
+ algo_len, tpm2_algorithm_name(algo));
+ print_byte_string(digest, algo_len);
+ }
unmap_sysmem(digest);
static int do_tpm_pcr_read(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
+ enum tpm2_algorithms algo = TPM2_ALG_SHA256;
struct udevice *dev;
struct tpm_chip_priv *priv;
u32 index, rc;
+ int algo_len;
unsigned int updates;
void *data;
int ret;
- if (argc != 3)
+ if (argc < 3 || argc > 4)
return CMD_RET_USAGE;
+ if (argc == 4) {
+ algo = tpm2_name_to_algorithm(argv[3]);
+ if (algo < 0)
+ return CMD_RET_FAILURE;
+ }
+ algo_len = tpm2_algorithm_to_len(algo);
ret = get_tpm(&dev);
if (ret)
data = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
- rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, TPM2_ALG_SHA256,
- data, TPM2_DIGEST_LEN, &updates);
+ rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, algo,
+ data, algo_len, &updates);
if (!rc) {
- printf("PCR #%u content (%u known updates):\n", index, updates);
- print_byte_string(data, TPM2_DIGEST_LEN);
+ printf("PCR #%u %s %d byte content (%u known updates):\n", index,
+ tpm2_algorithm_name(algo), algo_len, updates);
+ print_byte_string(data, algo_len);
}
unmap_sysmem(data);
" <hierarchy> is one of:\n"
" * TPM2_RH_LOCKOUT\n"
" * TPM2_RH_PLATFORM\n"
-"pcr_extend <pcr> <digest_addr>\n"
-" Extend PCR #<pcr> with digest at <digest_addr>.\n"
+"pcr_extend <pcr> <digest_addr> [<digest_algo>]\n"
+" Extend PCR #<pcr> with digest at <digest_addr> with digest_algo.\n"
" <pcr>: index of the PCR\n"
-" <digest_addr>: address of a 32-byte SHA256 digest\n"
-"pcr_read <pcr> <digest_addr>\n"
-" Read PCR #<pcr> to memory address <digest_addr>.\n"
+" <digest_addr>: address of digest of digest_algo type (defaults to SHA256)\n"
+"pcr_read <pcr> <digest_addr> [<digest_algo>]\n"
+" Read PCR #<pcr> to memory address <digest_addr> with <digest_algo>.\n"
" <pcr>: index of the PCR\n"
-" <digest_addr>: address to store the a 32-byte SHA256 digest\n"
+" <digest_addr>: address of digest of digest_algo type (defaults to SHA256)\n"
"get_capability <capability> <property> <addr> <count>\n"
" Read and display <count> entries indexed by <capability>/<property>.\n"
" Values are 4 bytes long and are written at <addr>.\n"
#include <command.h>
#include <env.h>
#include <log.h>
-#include <vsprintf.h>
+#include <stdio.h>
/* Some sane limit "just in case" */
#define MAX_BTN_CMDS 32
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
-CONFIG_DEFAULT_DEVICE_TREE="am3517-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/omap/am3517-evm"
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_AM3517_EVM=y
CONFIG_EMIF4=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
--- /dev/null
+#include <configs/j721s2_evm_a72_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J721S2=y
+CONFIG_TARGET_J721S2_A72_EVM=y
+
+CONFIG_SPL_OF_LIST="ti/k3-am68-sk-base-board"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am68-sk-base-board"
+CONFIG_OF_LIST="ti/k3-am68-sk-base-board"
--- /dev/null
+#include <configs/j721s2_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J721S2=y
+CONFIG_TARGET_J721S2_R5_EVM=y
+
+CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-r5-base-board"
+CONFIG_SPL_OF_LIST="k3-am68-sk-r5-base-board"
+CONFIG_OF_LIST="k3-am68-sk-r5-base-board"
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
# CONFIG_NET is not set
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-bpi-r2-pro"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-bob"
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
+# CONFIG_SPL_FIT_SIGNATURE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_ADDR=0x100000
CONFIG_BLOBLIST_SIZE=0x1000
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x1e000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_HANDOFF=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_CROS_EC=y
CONFIG_PWM_ROCKCHIP=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-kevin"
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
+# CONFIG_SPL_FIT_SIGNATURE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_ADDR=0x100000
CONFIG_BLOBLIST_SIZE=0x1000
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x1e000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_HANDOFF=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_CROS_EC=y
CONFIG_PWM_ROCKCHIP=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-coolpi-4b"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-coolpi-cm5-evb"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_FWU_MULTI_BANK_UPDATE=y
+CONFIG_FWU_MDATA_V1=y
CONFIG_ENV_OFFSET=0x80000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm"
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0x8001ff00
CONFIG_ENV_SIZE=0x2800
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm"
CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_ENV_ADDR=0x60100000
CONFIG_LTO=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x0
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm"
CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0x8001ff00
CONFIG_ARCH_EXYNOS9=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000
-CONFIG_DEFAULT_DEVICE_TREE="exynos850-e850-96"
+CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos850-e850-96"
CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_AUTOBOOT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-eaidk-610"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-eaidk-610"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-eaidk-610.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rv1108-elgin-r1"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1108-elgin-r1"
CONFIG_ROCKCHIP_RV1108=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
CONFIG_TARGET_ELGIN_RV1108=y
CONFIG_TARGET_EVB_PX30=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-evb"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-evb"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-evb"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
CONFIG_DISPLAY_ROCKCHIP_MIPI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-evb1-v10"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb1-v10.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-evb1-v10"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_EVB_RK3588=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
-CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1108-evb"
CONFIG_ROCKCHIP_RV1108=y
CONFIG_DEBUG_UART_BASE=0x10210000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus"
-CONFIG_SPL_TEXT_BASE=0xff8c2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-ficus"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
CONFIG_TARGET_ROCK960_RK3399=y
-CONFIG_SPL_STACK=0xff8effff
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0xff8e0000
-CONFIG_SPL_BSS_MAX_SIZE=0x10000
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_RGMII=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_ERRNO_STR=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-firefly"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_ENV_SIZE=0x8000
-CONFIG_DEFAULT_DEVICE_TREE="omap3-igep0020"
+CONFIG_DEFAULT_DEVICE_TREE="ti/omap/omap3-igep0020"
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SYS_MONITOR_LEN=262144
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_UBI_INFO_ADDR=0x88080000
CONFIG_SPL_UBI_VOL_IDS=8
CONFIG_SPL_UBI_LOAD_MONITOR_ID=0
-CONFIG_SPL_UBI_LOAD_KERNEL_ID=3
-CONFIG_SPL_UBI_LOAD_ARGS_ID=4
CONFIG_SPL_ONENAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x84000000
-CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x280000
-CONFIG_SPL_FALCON_BOOT_MMCSD=y
-CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
-CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
-CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
CONFIG_CMD_SPL=y
CONFIG_CMD_NAND=y
CONFIG_CMD_ONENAND=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_UBI=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_NET is not set
+CONFIG_SPL_DM=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=3
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_OMAP3_SPI=y
CONFIG_BCH=y
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0xFFFFDE00
+CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=1
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="mmc partconf 0 distro_bootpart && load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
+CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-mx8menlo.dtb"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2081
# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_CRC32 is not set
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FEC"
+CONFIG_ETHPRIME="eth0"
CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_SPL_DM=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
CONFIG_GPIO_HOG=y
+CONFIG_SPL_GPIO_HOG=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_MDIO=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_SPL_PHY=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y
+CONFIG_HEXDUMP=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phygate-tauri-l"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phygate-tauri-l"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PHYCORE_IMX8MM=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721s2-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="k3-j721s2-common-proc-board k3-am68-sk-base-board"
+CONFIG_OF_LIST="ti/k3-j721s2-common-proc-board"
CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_OF_UPSTREAM=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_OF_LIST="k3-j721s2-r5-common-proc-board k3-am68-sk-r5-base-board"
+CONFIG_SPL_OF_LIST="k3-j721s2-r5-common-proc-board"
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_ENV_SIZE=0x1f000
-CONFIG_DEFAULT_DEVICE_TREE="rk3588-jaguar"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-jaguar"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
CONFIG_SPL_SERIAL=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-captain"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-khadas-edge-captain"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb"
CONFIG_SYS_PBSIZE=1048
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="kedge# "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-khadas-edge"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
CONFIG_SYS_PBSIZE=1048
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="kedge# "
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_PHY_REALTEK=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-v"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-khadas-edge-v"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb"
CONFIG_SYS_PBSIZE=1048
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="kedge# "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-leez-p710"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-leez-p710"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-lubancat-2"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0x180000
CONFIG_SYS_LOAD_ADDR=0x70800000
+CONFIG_CMD_BMODE=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="boot/fitImage"
+CONFIG_BOOTFILE="fitImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FEC0"
CONFIG_USE_HOSTNAME=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopc-t4"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopc-t4"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-nanopc-t6"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-m4"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4b"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-m4b"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-neo4"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-nanopi-r2c-plus"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-nanopi-r2c"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-nanopi-r2s"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-r4s"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-nanopi-r5c"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-nanopi-r5s"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="rv1126-edgeble-neu2-io"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1126-edgeble-neu2-io"
CONFIG_SYS_MONITOR_LEN=614400
CONFIG_ROCKCHIP_RV1126=y
CONFIG_TARGET_RV1126_NEU2=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-edgeble-neu6a-io"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_RK3588_NEU6=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-edgeble-neu6b-io"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_RK3588_NEU6=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-indiedroid-nova"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_NOVA_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-indiedroid-nova.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x1000
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-odroid-m1"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
-CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-35xx-devkit"
+CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-torpedo-35xx-devkit"
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
-CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-35xx-devkit"
+CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-som-lv-35xx-devkit"
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
-CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
+CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-torpedo-37xx-devkit"
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
-CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit"
+CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-som-lv-37xx-devkit"
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="rk3588-orangepi-5-plus"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-orangepi-5-plus"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="rk3588s-orangepi-5"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-orangepi-5"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-orangepi-r1-plus-lts"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-orangepi-r1-plus"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-orangepi"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phyboard-polis-rdk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PHYCORE_IMX8MM=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_PHYCORE_IMX8MP=y
CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_IMX_WATCHDOG=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Phytec"
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
CONFIG_CI_UDC=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Phytec"
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
CONFIG_CI_UDC=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-pinebook-pro"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_EDP=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-pinephone-pro"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_EDP=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_LIST="rk3566-pinetab2-v0.1 rk3566-pinetab2-v2.0"
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-powkiddy-x55"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-powkiddy-x55.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-puma-haikou"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_PUMA_RK3399=y
-CONFIG_SPL_STACK=0xff8effff
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0xff8e0000
-CONFIG_SPL_BSS_MAX_SIZE=0x10000
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_DEBUG_UART_BASE=0xFF180000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x38000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_GPIO_HOG=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_GPIO=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-quartz64-a"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-b"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-quartz64-b"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-quartzpro64"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_QUARTZPRO64_RK3588=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="r8a779h0-gray-hawk"
+CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779h0-gray-hawk-single"
CONFIG_RCAR_GEN4=y
CONFIG_TARGET_GRAYHAWK=y
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-# CONFIG_OF_UPSTREAM is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-radxa-cm3-io"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-radxa-e25"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou"
-CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_RINGNECK_PX30=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-roc-cc"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-roc-cc"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-roc-pc-mezzanine"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-roc-pc"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
-CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_RAM_ROCKCHIP_LPDDR4=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-rock-3a"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus"
-CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rock-4c-plus"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_ROCKPI4_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
-CONFIG_PCI=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se"
-CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rock-4se"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_ROCKPI4_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
-CONFIG_SPL_FIT_SIGNATURE=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a"
-CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rock-pi-4a"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
-CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c"
-CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rock-pi-4c"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_ROCKPI4_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
+CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-rock-pi-e"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399pro-rock-pi-n10"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399pro-rock-pi-n10"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb"
# CONFIG_CONSOLE_MUX is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-rock-pi-s"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-rock-5a"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_ROCK5A_RK3588=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-rock-5b"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-rock64"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rock960"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROCK960_RK3399=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
-CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
CONFIG_SYS_PBSIZE=1052
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SF is not set
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rockpro64"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
-CONFIG_SPL_FIT_SIGNATURE=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_EMBED=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_EMBED=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_EMBED=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_EMBED=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_EMBED=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_EMBED=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ENV_OFFSET=0x0
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFE000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-beacon-rzg2m-kit"
CONFIG_RCAR_GEN3=y
CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rv1126-sonoff-ihost"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1126-sonoff-ihost"
CONFIG_SYS_MONITOR_LEN=614400
CONFIG_ROCKCHIP_RV1126=y
CONFIG_TARGET_RV1126_SONOFF_IHOST=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-soquartz-blade"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_QUARTZ64_RK3566=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-cm4"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-soquartz-cm4"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_QUARTZ64_RK3566=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-model-a"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-soquartz-model-a"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_QUARTZ64_RK3566=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="StarFive # "
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_SIZE=512
CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox"
CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_TARGET_DEVELOPERBOX=y
-CONFIG_FWU_NUM_IMAGES_PER_BANK=1
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_FWU_MULTI_BANK_UPDATE=y
+CONFIG_FWU_MDATA_V2=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=24000000
-CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-turing-rk1"
CONFIG_ROCKCHIP_RK3588=y
-CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_TURINGRK1_RK3588=y
CONFIG_DEBUG_UART_BASE=0xFEBC0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_SF_DEFAULT_BUS=5
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_XMC=y
-CONFIG_SPI_FLASH_XTX=y
+# CONFIG_SPI_FLASH is not set
CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_SCSI=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
-CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
actions/index
advantech/index
- AndesTech/index
+ andestech/index
allwinner/index
amlogic/index
anbernic/index
- Pine64 SOQuartz on Blade (soquartz-blade-rk3566)
- Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566)
- Pine64 SOQuartz on Model A (soquartz-model-a-rk3566)
+ - Powkiddy X55 (powkiddy-x55-rk3566)
- Radxa CM3 IO Board (radxa-cm3-io-rk3566)
* rk3568
- Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
- FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
- Generic RK3588S/RK3588 (generic-rk3588)
+ - Indiedroid Nova (nova-rk3588s)
- Pine64 QuartzPro64 (quartzpro64-rk3588)
- Radxa ROCK 5A (rock5a-rk3588s)
- Radxa ROCK 5B (rock5b-rk3588)
CONFIG_FWU_NUM_BANKS=2
CONFIG_FWU_NUM_IMAGES_PER_BANK=1
CONFIG_CMD_FWU_METADATA=y
+ CONFIG_FWU_MDATA_V2=y
And build it::
By default, the CONFIG_FWU_NUM_BANKS and CONFIG_FWU_NUM_IMAGES_PER_BANKS are
set to 2 and 1 respectively. This uses FIP (Firmware Image Package) type image
which contains TF-A, U-Boot and OP-TEE (the OP-TEE is optional).
-You can use fiptool to compose the FIP image from those firmware images.
+You can use fiptool to compose the FIP image from those firmware
+images. There are two versions of the FWU metadata, of which the
+platform enables version 2 by default.
Rebuild SCP firmware
--------------------
These UUIDs are used for making a FWU metadata image.
-u-boot$ ./tools/mkfwumdata -i 1 -b 2 \
+u-boot$ ./tools/mkfwumdata -v 2 -i 1 -b 2 \
17e86d77-41f9-4fd7-87ec-a55df9842de5,10c36d7d-ca52-b843-b7b9-f9d6c501d108,5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0 \
../devbox-fwu-mdata.img
.. toctree::
:maxdepth: 1
- milk-v_mars.rst
+ milk-v_mars
+ milk-v_mars_cm
+ pine64_star64
visionfive2
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Milk-V Mars CM
+==============
+
+U-Boot for the Milk-V Mars CM uses the same U-Boot binaries as the VisionFive 2
+board. In U-Boot SPL the actual board is detected and the device-tree patched
+accordingly.
+
+The Milk-V Mars CM Lite comes without eMMC and needs a different pin muxing
+than the Milk-V Mars CM. The availability and size of the eMMC shows up in the
+serial number displayed by the *mac* command, e.g.
+MARC-V10-2340-D002E016-00000304. The number after the E is the MMC size. U-Boot
+takes a value of E000 as an indicator for the Lite version. Unfortunately the
+vendor has not set this value correctly on some Lite boards.
+
+Please, use CONFIG_STARFIVE_NO_EMMC=y if EEPROM data indicates eMMC is present
+on the Milk-V Mars CM Lite. Otherwise you will not be able to read from the
+SD-card.
+
+The serial number can be corrected using the *mac* command:
+
+.. code-block::
+
+ mac read_eeprom
+ mac product_id MARC-V10-2340-D002E000-00000304
+ mac write_eeprom
+
+.. note::
+
+ The *mac initialize* command overwrites the vendor string and the MAC
+ addresses. This is why it is avoided here.
+
+By default the EEPROM is write protected. The write protection may be overcome
+by connecting the "GND" and "EN" test pads on top of the module.
+
+Building
+~~~~~~~~
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+The M-mode software OpenSBI provides the supervisor binary interface (SBI) and
+is responsible for the switch to S-Mode. It is a prerequisite to build U-Boot.
+Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended to use
+a current release.
+
+.. code-block:: console
+
+ git clone https://github.com/riscv/opensbi.git
+ cd opensbi
+ make PLATFORM=generic FW_TEXT_START=0x40000000
+
+(*FW_TEXT_START* is not needed anymore after OpenSBI patch d4d2582eef7a
+"firmware: remove FW_TEXT_START" which should appear in OpenSBI 1.5.)
+
+Now build the U-Boot SPL and U-Boot proper.
+
+.. code-block:: console
+
+ cd <U-Boot-dir>
+ make starfive_visionfive2_defconfig
+ make OPENSBI=$(opensbi_dir)/build/platform/generic/firmware/fw_dynamic.bin
+
+This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well
+as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
+
+Device-tree selection
+~~~~~~~~~~~~~~~~~~~~~
+
+Depending on the board version U-Boot sets variable $fdtfile to either
+starfive/jh7110-milkv-mars-cm.dtb (with eMMC storage) or
+starfive/jh7110-milkv-mars-cm-lite.dtb (without eMMC storage).
+
+To overrule this selection the variable can be set manually and saved in the
+environment
+
+::
+
+ env set fdtfile my_device-tree.dtb
+ env save
+
+or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to
+provide a default value.
+
+The variable *$fdtfile* is used in the boot process to automatically load
+a device-tree provided by the operating system. For details of the boot
+process refer to the :doc:`U-Boot Standard Boot <../../../develop/bootstd>`
+description.
+
+Boot source selection
+~~~~~~~~~~~~~~~~~~~~~
+
+The low speed connector nRPIBOOT line is used to switch the boot source.
+
+* If nRPIBOOT is connected to ground, the board boots from UART.
+* If nRPIBOOT is not connected, the board boots from SPI flash.
+
+Compute module boards typically have a switch or jumper for this line.
+
+Flashing a new U-Boot version
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+U-Boot SPL is provided as file spl/u-boot-spl.bin.normal.out. Main U-Boot is
+in file u-boot.itb.
+
+Assuming your new U-Boot version is on partition 1 of an SD-card you could
+install it to the SPI flash with:
+
+::
+
+ sf probe
+ load mmc 0:1 $kernel_addr_r u-boot-spl.bin.normal.out
+ sf update $kernel_addr_r 0 $filesize
+ load mmc 0:1 $kernel_addr_r u-boot.itb
+ sf update $kernel_addr_r 0x100000 $filesize
+
+For loading the files from a TFTP server refer to the dhcp and tftpboot
+commands.
+
+After updating U-Boot you may want to reboot and reset the environment to the
+default.
+
+::
+
+ env default -f -a
+ env save
+
+Booting from UART
+~~~~~~~~~~~~~~~~~
+
+For booting via UART U-Boot must be built with CONFIG_SPL_YMODEM_SUPPORT=y.
+
+With nRPIBOOT connected to ground for UART boot, power the board and upload
+u-boot-spl.bin.normal.out via XMODEM. Then upload u-boot.itb via YMODEM.
+
+The XMODEM implementation in the boot ROM is not fully specification compliant.
+It sends too many NAKs in a row. Tio is a terminal emulation that tolerates
+these faults.
+
+::
+
+ $ tio -b 115200 --databits 8 --flow none --stopbits 1 /dev/ttyUSB0
+ [08:14:54.700] tio v2.7
+ [08:14:54.700] Press ctrl-t q to quit
+ [08:14:54.701] Connected
+
+ (C)StarFive
+ CCC
+ (C)StarFive
+ CCCCCCCC
+
+Press *ctrl-t x* to initiate XMODEM-1K transfer.
+
+::
+
+ [08:15:14.778] Send file with XMODEM
+ [08:15:22.459] Sending file 'u-boot-spl.bin.normal.out'
+ [08:15:22.459] Press any key to abort transfer
+ ........................................................................
+ .......................................................................|
+ [08:15:22.459] Done
+
+ U-Boot SPL 2024.07-rc1-00075-gd6a4ab20097 (Apr 25 2024 - 16:32:10 +0200)
+ DDR version: dc2e84f0.
+ Trying to boot from UART
+ CC
+
+Press *ctrl-t y* to initiate YMODEM transfer.
+
+::
+
+ [08:15:50.331] Send file with YMODEM
+ [08:15:53.540] Sending file 'u-boot.itb'
+ [08:15:53.540] Press any key to abort transfer
+ ........................................................................
+ …
+ ...............|
+ [08:15:53.540] Done
+ Loaded 1040599 bytes
+
+
+ U-Boot 2024.07-rc1-00075-gd6a4ab20097 (Apr 25 2024 - 16:32:10 +0200)
+
+Booting from SPI flash
+~~~~~~~~~~~~~~~~~~~~~~
+
+With nRPIBOOT disconnected from ground for SPI boot, power up the board. You
+should see the U-Boot prompt on the serial console.
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Pine64 Star64
+=============
+
+U-Boot for the Star64 uses the same U-Boot binaries as the VisionFive 2 board.
+In U-Boot SPL the actual board is detected and the device-tree patched
+accordingly.
+
+Building
+~~~~~~~~
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+The M-mode software OpenSBI provides the supervisor binary interface (SBI) and
+is responsible for the switch to S-Mode. It is a prerequisite to build U-Boot.
+Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended to use
+a current release.
+
+.. code-block:: console
+
+ git clone https://github.com/riscv/opensbi.git
+ cd opensbi
+ make PLATFORM=generic FW_TEXT_START=0x40000000
+
+Now build the U-Boot SPL and U-Boot proper.
+
+.. code-block:: console
+
+ cd <U-Boot-dir>
+ make starfive_visionfive2_defconfig
+ make OPENSBI=$(opensbi_dir)/build/platform/generic/firmware/fw_dynamic.bin
+
+This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well
+as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
+
+Device-tree selection
+~~~~~~~~~~~~~~~~~~~~~
+
+U-Boot will set variable $fdtfile to starfive/jh7110-pine64-star64.dtb.
+
+To overrule this selection the variable can be set manually and saved in the
+environment
+
+::
+
+ env set fdtfile my_device-tree.dtb
+ env save
+
+or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to
+provide a default value.
+
+Boot source selection
+~~~~~~~~~~~~~~~~~~~~~
+
+Boot mode is selected by an MSEL-DIP marked S1804 and GPIO_0 position adjacent
+to the 40pin GPIO header. ON/ONKE and number markings of the MSEL-DIP are
+misleading; Instead refer to the ``L`` (0) and ``H`` (1) silkscreen for
+accurate selection.
+
++ (QSPI) Flash: 00
++ SD: 01
++ EMMC: 10
++ UART: 11
+
+Preparing the SD-Card
+~~~~~~~~~~~~~~~~~~~~~
+
+The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
+partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
+to choose any partition number.
+
+With the default configuration U-Boot SPL loads the U-Boot FIT image
+(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2).
+When formatting it is recommended to use GUID
+BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition.
+
+The FIT image (u-boot.itb) is a combination of OpenSBI's fw_dynamic.bin,
+u-boot-nodtb.bin and the device tree blob.
+
+Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
+
+.. code-block:: bash
+
+ sudo sgdisk --clear \
+ --set-alignment=2 \
+ --new=1:4096:8191 --change-name=1:spl --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985\
+ --new=2:8192:16383 --change-name=2:uboot --typecode=2:BC13C2FF-59E6-4262-A352-B275FD6F7172 \
+ --new=3:16384:1654784 --change-name=3:system --typecode=3:EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 \
+ /dev/sdb
+
+Copy U-Boot to the SD card
+
+.. code-block:: bash
+
+ sudo dd if=u-boot-spl.bin.normal.out of=/dev/sdb1
+ sudo dd if=u-boot.itb of=/dev/sdb2
+
+ sudo mount /dev/sdb3 /mnt/
+ sudo cp u-boot-spl.bin.normal.out /mnt/
+ sudo cp u-boot.itb /mnt/
+ sudo cp Image.gz /mnt/
+ sudo cp initramfs.cpio.gz /mnt/
+ sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
+ sudo umount /mnt
+
+Booting
+~~~~~~~
+
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Serial Number and MAC address issues
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+U-Boot requires valid EEPROM data to determine which board-specific fix-up to
+apply at runtime. This affects the size of memory initialized, network mac
+address numbering, and tuning of the network PHYs.
+
+The Star64 does not currently ship with unique serial numbers per-device.
+Devices follow a pattern where the last mac address bytes are a sum of 0x7558
+and the serial number (lower port mac0), or a sum of 0x7559 and the serial
+number (upper port mac1).
+
+As tested there are several 4gb model units where the serial number and network
+mac addresses collide with other devices (serial
+``STAR64V1-2310-D004E000-00000005``, MACs ``6c:cf:39:00:75:61``,
+``6c:cf:39:00:75:62``)
+
+Some early Star64 boards shipped with an uninitialized EEPROM and no write
+protect pull-up resistor in place. Later units of all 4gb and 8gb models
+sharing the same serial number in EEPROM data will have this problem that the
+network mac addresses are alike between different models and this may be
+corrected by defeating the write protect resistor to write new values. As an
+alternative to this, it may be worked around by overriding the mac addresses
+via U-Boot environment variables.
+
+It is required for any unit having uninitialized EEPROM and recommended for
+all later Star64 4gb model units (not properly serialized) to have decided on a
+new 6-byte serial number. This serial number should be high enough to
+avoid collision with other JH7110 boards and low enough not to overflow i.e.
+between ``cafe00`` and ``f00d00``.
+
+Update EEPROM values
+^^^^^^^^^^^^^^^^^^^^
+
+1. Prepare EEPROM data in memory
+
+::
+
+ ## When there is no error to load existing data:
+ mac read_eeprom
+
+ ## When there is an error to load non-existing data:
+ # "DRAM: Not a StarFive EEPROM data format - magic error"
+ mac initialize
+
+2. Set Star64 values
+
+::
+
+ ## Common values
+ mac vendor PINE64
+ mac pcb_revision c1
+ mac bom_revision A
+
+ ## Device-specific values
+ # Year 2023 week 10 production date, 8GB DRAM, optional eMMC, serial cdef01
+ mac product_id STAR64V1-2310-D008E000-00cdef01
+
+ # Last three bytes mac0: 0x7558 + serial number 0xcdef01
+ mac mac0_address 6c:cf:39:ce:64:59
+
+ # Last three bytes mac1: 0x7559 + serial number 0xcdef01
+ mac mac1_address 6c:cf:39:ce:64:5a
+
+3. Defeat write-protect pull-up resistor (if installed) and write to EEPROM
+
+::
+
+ mac write_eeprom
+
+Set Variables in U-Boot
+^^^^^^^^^^^^^^^^^^^^^^^
+
+.. note:: Changing just the serial number will not alter your MAC address
+
+The MAC addresses may be "set" as follows by writing as a custom config to SPI
+(Change the last 3 bytes of MAC addreses as appropriate):
+
+::
+
+ env set serial# STAR64V1-2310-D008E000-00cdef01
+ env set ethaddr 6c:cf:39:ce:64:59
+ env set eth1addr 6c:cf:39:ce:64:5a
+ env save
+ reset
* U-Boot v2024.07-rc2 was released on Mon 06 May 2024.
-.. * U-Boot v2024.07-rc3 was released on Mon 20 May 2024.
+* U-Boot v2024.07-rc3 was released on Mon 20 May 2024.
-.. * U-Boot v2024.07-rc4 was released on Mon 03 June 2024.
+* U-Boot v2024.07-rc4 was released on Mon 03 June 2024.
.. * U-Boot v2024.07-rc5 was released on Mon 17 June 2024.
CONFIG_FWU_NUM_BANKS=<val>
CONFIG_FWU_NUM_IMAGES_PER_BANK=<val>
+ CONFIG_FWU_MDATA_V1=y or CONFIG_FWU_MDATA_V2=y
+
in the .config file
By enabling the CONFIG_CMD_FWU_METADATA config option, the
section :ref:`uefi_capsule_update_ref` for more details on generation
of the UEFI capsule.
+FWU Metadata
+------------
+
+U-Boot supports both versions(1 and 2) of the FWU metadata defined in
+the two revisions of the specification. Support can be enabled for
+either of the two versions through a config flag. The mkfwumdata tool
+can generate metadata for both the supported versions.
+
Setting up the device for GPT partitioned storage
-------------------------------------------------
* UniquePartitionGUID
The PartitionTypeGUID value should correspond to the
-``image_type_uuid`` field of the FWU metadata. This field is used to
+``image_type_guid`` field of the FWU metadata. This field is used to
identify a given type of updatable firmware image, e.g. U-Boot,
OP-TEE, FIP etc. This GUID should also be used for specifying the
`--guid` parameter when generating the capsule.
-The UniquePartitionGUID value should correspond to the ``image_uuid``
+The UniquePartitionGUID value should correspond to the ``image_guid``
field in the FWU metadata. This GUID is used to identify images of a
given image type in different banks.
metadata partitions. Similarly, the UEFI specification defines the ESP
GUID to be be used.
-When generating the metadata, the ``image_type_uuid`` and the
-``image_uuid`` values should match the *PartitionTypeGUID* and the
+When generating the metadata, the ``image_type_guid`` and the
+``image_guid`` values should match the *PartitionTypeGUID* and the
*UniquePartitionGUID* values respectively.
Performing the Update
Links
-----
-* [1] https://developer.arm.com/documentation/den0118/a/ - FWU Specification
+* [1] https://developer.arm.com/documentation/den0118/ - FWU Specification
* [2] https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24e18d4319e108a758d02e/mbfw.pdf - Dependable Boot Specification
+++ /dev/null
-Rockchip Dynamic Memory Controller Driver
-Required properties:
-- compatible: "rockchip,rk3399-dmc", "syscon"
-- rockchip,cru: this driver should access cru regs, so need get cru here
-- rockchip,pmucru: this driver should access pmucru regs, so need get pmucru here
-- rockchip,pmugrf: this driver should access pmugrf regs, so need get pmugrf here
-- rockchip,pmusgrf: this driver should access pmusgrf regs, so need get pmusgrf here
-- rockchip,cic: this driver should access cic regs, so need get cic here
-- reg: dynamic ram protocol controller(PCTL) address, PHY Independent(PI) address, phy controller(PHYCTL) address and memory schedule(MSCH) address
-- clock: must include clock specifiers corresponding to entries in the clock-names property.
- Must contain
- dmc_clk: for ddr working frequency
-- rockchip,sdram-params: SDRAM parameters, including all the information by ddr driver:
- Must contain
- Genarate by vendor tool and adjust for U-Boot dtsi.
-
-Example:
- dmc: dmc {
- bootph-all;
- compatible = "rockchip,rk3399-dmc";
- devfreq-events = <&dfi>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_DDRCLK>;
- clock-names = "dmc_clk";
- reg = <0x0 0xffa80000 0x0 0x0800
- 0x0 0xffa80800 0x0 0x1800
- 0x0 0xffa82000 0x0 0x2000
- 0x0 0xffa84000 0x0 0x1000
- 0x0 0xffa88000 0x0 0x0800
- 0x0 0xffa88800 0x0 0x1800
- 0x0 0xffa8a000 0x0 0x2000
- 0x0 0xffa8c000 0x0 0x1000>;
- };
-
- &dmc {
- rockchip,sdram-params = <
- 0x2
- 0xa
- 0x3
- ...
- >;
- };
+++ /dev/null
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Samsung Exynos850 SoC clock controller
-
-maintainers:
- - Sam Protsenko <semen.protsenko@linaro.org>
-
-description: |
- Exynos850 clock controller is comprised of several CMU units, generating
- clocks for different domains. Those CMU units are modeled as separate device
- tree nodes, and might depend on each other. Root clocks in that clock tree are
- two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
- clocks must be defined as fixed-rate clocks in dts.
-
- CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
- dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
-
- Each clock is assigned an identifier and client nodes can use this identifier
- to specify the clock which they consume. All clocks available for usage
- in clock consumer nodes are defined as preprocessor macros in
- 'dt-bindings/clock/exynos850.h' header.
-
-properties:
- compatible:
- enum:
- - samsung,exynos850-cmu-top
- - samsung,exynos850-cmu-apm
- - samsung,exynos850-cmu-aud
- - samsung,exynos850-cmu-cmgp
- - samsung,exynos850-cmu-core
- - samsung,exynos850-cmu-dpu
- - samsung,exynos850-cmu-g3d
- - samsung,exynos850-cmu-hsi
- - samsung,exynos850-cmu-is
- - samsung,exynos850-cmu-mfcmscl
- - samsung,exynos850-cmu-peri
-
- clocks:
- minItems: 1
- maxItems: 5
-
- clock-names:
- minItems: 1
- maxItems: 5
-
- "#clock-cells":
- const: 1
-
- reg:
- maxItems: 1
-
-allOf:
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-top
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
-
- clock-names:
- items:
- - const: oscclk
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-apm
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: CMU_APM bus clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_clkcmu_apm_bus
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-aud
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: AUD clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_aud
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-cmgp
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: CMU_CMGP bus clock (from CMU_APM)
-
- clock-names:
- items:
- - const: oscclk
- - const: gout_clkcmu_cmgp_bus
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-core
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: CMU_CORE bus clock (from CMU_TOP)
- - description: CCI clock (from CMU_TOP)
- - description: eMMC clock (from CMU_TOP)
- - description: SSS clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_core_bus
- - const: dout_core_cci
- - const: dout_core_mmc_embd
- - const: dout_core_sss
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-dpu
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: DPU clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_dpu
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-g3d
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: G3D clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_g3d_switch
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-hsi
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: External RTC clock (32768 Hz)
- - description: CMU_HSI bus clock (from CMU_TOP)
- - description: SD card clock (from CMU_TOP)
- - description: USB 2.0 DRD clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: rtcclk
- - const: dout_hsi_bus
- - const: dout_hsi_mmc_card
- - const: dout_hsi_usb20drd
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-is
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: CMU_IS bus clock (from CMU_TOP)
- - description: Image Texture Processing core clock (from CMU_TOP)
- - description: Visual Recognition Accelerator clock (from CMU_TOP)
- - description: Geometric Distortion Correction clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_is_bus
- - const: dout_is_itp
- - const: dout_is_vra
- - const: dout_is_gdc
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-mfcmscl
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: Multi-Format Codec clock (from CMU_TOP)
- - description: Memory to Memory Scaler clock (from CMU_TOP)
- - description: Multi-Channel Scaler clock (from CMU_TOP)
- - description: JPEG codec clock (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_mfcmscl_mfc
- - const: dout_mfcmscl_m2m
- - const: dout_mfcmscl_mcsc
- - const: dout_mfcmscl_jpeg
-
- - if:
- properties:
- compatible:
- contains:
- const: samsung,exynos850-cmu-peri
-
- then:
- properties:
- clocks:
- items:
- - description: External reference clock (26 MHz)
- - description: CMU_PERI bus clock (from CMU_TOP)
- - description: UART clock (from CMU_TOP)
- - description: Parent clock for HSI2C and SPI (from CMU_TOP)
-
- clock-names:
- items:
- - const: oscclk
- - const: dout_peri_bus
- - const: dout_peri_uart
- - const: dout_peri_ip
-
-required:
- - compatible
- - "#clock-cells"
- - clocks
- - clock-names
- - reg
-
-additionalProperties: false
-
-examples:
- # Clock controller node for CMU_PERI
- - |
- #include <dt-bindings/clock/exynos850.h>
-
- cmu_peri: clock-controller@10030000 {
- compatible = "samsung,exynos850-cmu-peri";
- reg = <0x10030000 0x8000>;
- #clock-cells = <1>;
-
- clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
- <&cmu_top CLK_DOUT_PERI_UART>,
- <&cmu_top CLK_DOUT_PERI_IP>;
- clock-names = "oscclk", "dout_peri_bus",
- "dout_peri_uart", "dout_peri_ip";
- };
-
-...
+++ /dev/null
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Samsung's Exynos USI (Universal Serial Interface)
-
-maintainers:
- - Sam Protsenko <semen.protsenko@linaro.org>
-
-description: |
- USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
- USI shares almost all internal circuits within each protocol, so only one
- protocol can be chosen at a time. USI is modeled as a node with zero or more
- child nodes, each representing a serial sub-node device. The mode setting
- selects which particular function will be used.
-
-properties:
- $nodename:
- pattern: "^usi@[0-9a-f]+$"
-
- compatible:
- enum:
- - samsung,exynos850-usi
-
- reg: true
-
- clocks: true
-
- clock-names: true
-
- ranges: true
-
- "#address-cells":
- const: 1
-
- "#size-cells":
- const: 1
-
- samsung,sysreg:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- items:
- - items:
- - description: phandle to System Register syscon node
- - description: offset of SW_CONF register for this USI controller
- description:
- Should be phandle/offset pair. The phandle to System Register syscon node
- (for the same domain where this USI controller resides) and the offset
- of SW_CONF register for this USI controller.
-
- samsung,mode:
- $ref: /schemas/types.yaml#/definitions/uint32
- description:
- Selects USI function (which serial protocol to use). Refer to
- <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
-
- samsung,clkreq-on:
- type: boolean
- description:
- Enable this property if underlying protocol requires the clock to be
- continuously provided without automatic gating. As suggested by SoC
- manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
- multi-master mode. Usually this property is needed if USI mode is set
- to "UART".
-
- This property is optional.
-
-patternProperties:
- "^i2c@[0-9a-f]+$":
- $ref: /schemas/i2c/i2c-exynos5.yaml
- description: Child node describing underlying I2C
-
- "^serial@[0-9a-f]+$":
- $ref: /schemas/serial/samsung_uart.yaml
- description: Child node describing underlying UART/serial
-
- "^spi@[0-9a-f]+$":
- $ref: /schemas/spi/samsung,spi.yaml
- description: Child node describing underlying SPI
-
-required:
- - compatible
- - ranges
- - "#address-cells"
- - "#size-cells"
- - samsung,sysreg
- - samsung,mode
-
-if:
- properties:
- compatible:
- contains:
- enum:
- - samsung,exynos850-usi
-
-then:
- properties:
- reg:
- maxItems: 1
-
- clocks:
- items:
- - description: Bus (APB) clock
- - description: Operating clock for UART/SPI/I2C protocol
-
- clock-names:
- items:
- - const: pclk
- - const: ipclk
-
- required:
- - reg
- - clocks
- - clock-names
-
-else:
- properties:
- reg: false
- clocks: false
- clock-names: false
- samsung,clkreq-on: false
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/soc/samsung,exynos-usi.h>
-
- usi0: usi@138200c0 {
- compatible = "samsung,exynos850-usi";
- reg = <0x138200c0 0x20>;
- samsung,sysreg = <&sysreg_peri 0x1010>;
- samsung,mode = <USI_V2_UART>;
- samsung,clkreq-on; /* needed for UART mode */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clocks = <&cmu_peri 32>, <&cmu_peri 31>;
- clock-names = "pclk", "ipclk";
-
- serial_0: serial@13820000 {
- compatible = "samsung,exynos850-uart";
- reg = <0x13820000 0xc0>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu_peri 32>, <&cmu_peri 31>;
- clock-names = "uart", "clk_uart_baud0";
- status = "disabled";
- };
-
- hsi2c_0: i2c@13820000 {
- compatible = "samsung,exynosautov9-hsi2c";
- reg = <0x13820000 0xc0>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cmu_peri 31>, <&cmu_peri 32>;
- clock-names = "hsi2c", "hsi2c_pclk";
- status = "disabled";
- };
- };
+++ /dev/null
-#!/bin/sh
-
-# 0) Generate keys
-#
-# WARNING: ECDSA keys are only supported by HAB 4.5 and newer (i.e. i.MX8M Plus)
-#
-# cd /path/to/cst-3.3.1/keys/
-# ./hab4_pki_tree.sh -existing-ca n -use-ecc n -kl 4096 -duration 10 -num-srk 4 -srk-ca y
-# cd /path/to/cst-3.3.1/crts/
-# ../linux64/bin/srktool -h 4 -t SRK_1_2_3_4_table.bin -e SRK_1_2_3_4_fuse.bin -d sha256 -c ./SRK1_sha256_4096_65537_v3_ca_crt.pem,./SRK2_sha256_4096_65537_v3_ca_crt.pem,./SRK3_sha256_4096_65537_v3_ca_crt.pem,./SRK4_sha256_4096_65537_v3_ca_crt.pem -f 1
-
-# 1) Build U-Boot (e.g. for i.MX8MM)
-#
-# cp -Lv /path/to/arm-trusted-firmware/build/imx8mm/release/bl31.bin .
-# cp -Lv /path/to/firmware-imx-8.14/firmware/ddr/synopsys/ddr3* .
-# make -j imx8mm_board_defconfig
-# make -j`nproc` flash.bin
-
-# 2) Sign SPL and DRAM blobs
-
-cp doc/imx/habv4/csf_examples/mx8m/csf_spl.txt csf_spl.tmp
-cp doc/imx/habv4/csf_examples/mx8m/csf_fit.txt csf_fit.tmp
-
-# update File Paths from env vars
-if ! [ -r $CSF_KEY ]; then
- echo "Error: \$CSF_KEY not found"
- exit 1
-fi
-if ! [ -r $IMG_KEY ]; then
- echo "Error: \$IMG_KEY not found"
- exit 1
-fi
-if ! [ -r $SRK_TABLE ]; then
- echo "Error: \$SRK_TABLE not found"
- exit 1
-fi
-sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_spl.tmp
-sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_spl.tmp
-sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_spl.tmp
-sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_fit.tmp
-sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_fit.tmp
-sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_fit.tmp
-
-# update SPL Blocks
-spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p" .config) - 0x40)) )
-spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin))
-sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size \"flash.bin\"@" csf_spl.tmp
-
-# Generate CSF blob
-cst -i csf_spl.tmp -o csf_spl.bin
-
-# Patch CSF blob into flash.bin
-spl_csf_offset=$(xxd -s 24 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@")
-spl_bin_offset=$(xxd -s 4 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@")
-spl_dd_offset=$((${spl_csf_offset} - ${spl_bin_offset} + 0x40))
-dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc
-
-# 3) Sign u-boot.itb
-
-# fitImage
-fit_block_base=$(printf "0x%x" $(sed -n "/CONFIG_SPL_LOAD_FIT_ADDRESS=/ s@.*=@@p" .config) )
-fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset))
-fit_block_size=$(printf "0x%x" $(( ( ( $(stat -tc %s u-boot.itb) + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) )
-sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\"@" csf_fit.tmp
-
-# IVT
-ivt_ptr_base=$(printf "%08x" ${fit_block_base} | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-ivt_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} - 0x20 )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-csf_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-ivt_block_offset=$((${fit_block_offset} + ${fit_block_size} - 0x20))
-csf_block_offset=$((${ivt_block_offset} + 0x20))
-
-echo "0xd1002041 ${ivt_block_base} 0x00000000 0x00000000 0x00000000 ${ivt_block_base} ${csf_block_base} 0x00000000" | xxd -r -p > ivt.bin
-dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc
-
-# Generate CSF blob
-cst -i csf_fit.tmp -o csf_fit.bin
-
-# When loading flash.bin via USB, we must ensure that the file being
-# served is as large as the target expects (see
-# board_spl_fit_size_align()), otherwise the target will hang in
-# rom_api_download_image() waiting for the remaining bytes.
-#
-# Note that in order for dd to actually extend the file, one must not
-# pass conv=notrunc here. With a non-zero seek= argument, dd is
-# documented to preserve the contents of the file seeked past; in
-# particular, dd does not open the file with O_TRUNC.
-CSF_SIZE=$(sed -n "/CONFIG_CSF_SIZE=/ s@.*=@@p" .config)
-dd if=/dev/null of=csf_fit.bin bs=1 seek=$((CSF_SIZE - 0x20)) count=0
-
-# Patch CSF blob into flash.bin
-dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc
+++ /dev/null
-[Header]
- Version = 4.3
- Hash Algorithm = sha256
- Engine = CAAM
- Engine Configuration = 0
- Certificate Format = X509
- Signature Format = CMS
-
-[Install SRK]
- # SRK_TABLE is full path to SRK_1_2_3_4_table.bin
- File = "$SRK_TABLE"
- Source index = 0
-
-[Install CSFK]
- # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem
- File = "$CSF_KEY"
-
-[Authenticate CSF]
-
-[Install Key]
- Verification index = 0
- Target Index = 2
- # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem
- File = "$IMG_KEY"
-
-[Authenticate Data]
- Verification index = 2
- # FIXME:
- # Line 1 -- fitImage
- Blocks = CONFIG_SPL_LOAD_FIT_ADDRESS 0x57c00 0xffff "flash.bin"
+++ /dev/null
-[Header]
- Version = 4.3
- Hash Algorithm = sha256
- Engine = CAAM
- Engine Configuration = 0
- Certificate Format = X509
- Signature Format = CMS
-
-[Install SRK]
- # SRK_TABLE is full path to SRK_1_2_3_4_table.bin
- File = "$SRK_TABLE"
- Source index = 0
-
-[Install CSFK]
- # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem
- File = "$CSF_KEY"
-
-[Authenticate CSF]
-
-[Unlock]
- Engine = CAAM
- Features = MID
-
-[Install Key]
- Verification index = 0
- Target Index = 2
- # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem
- File = "$IMG_KEY"
-
-[Authenticate Data]
- Verification index = 2
- # FIXME: Adjust start (first column) and size (third column) here
- Blocks = 0x7e0fc0 0x0 0x306f0 "flash.bin"
- Defconfig:
CONFIG_IMX_HAB=y
+ CONFIG_FSL_CAAM=y
+ CONFIG_ARCH_MISC_INIT=y
+ CONFIG_SPL_CRYPTO=y
- Kconfig:
The CSF contains all the commands that the HAB executes during the secure
boot. These commands instruct the HAB code on which memory areas of the image
-to authenticate, which keys to install, use and etc.
-
-CSF examples are available under doc/imx/habv4/csf_examples/ directory.
-
-CSF "Blocks" line for csf_spl.txt can be generated as follows:
-
-```
-spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p" .config) - 0x40)) )
-spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin))
-sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size \"flash.bin\"@" csf_spl.txt
-```
-
-The resulting line looks as follows:
-```
- Blocks = 0x7e0fc0 0x0 0x306f0 "flash.bin"
-```
-
-The columns mean:
- - CONFIG_SPL_TEXT_BASE - 0x40 -- Start address of signed data, in DRAM
- - 0x0 -- Start address of signed data, in "flash.bin"
- - 0x306f0 -- Length of signed data, in "flash.bin"
- - Filename -- "flash.bin"
-
-To generate signature for the SPL part of flash.bin container, use CST:
-```
-cst -i csf_spl.tmp -o csf_spl.bin
-```
-
-The newly generated CST blob has to be patched into existing flash.bin
-container. Conveniently, flash.bin IVT contains physical address of the
-CSF blob. Remember, the SPL part of flash.bin container is loaded by the
-BootROM at CONFIG_SPL_TEXT_BASE - 0x40 , so the offset of CSF blob in
-the fitImage can be calculated and inserted into the flash.bin in the
-correct location as follows:
-```
-# offset = IVT_HEADER[6 = CSF address] - CONFIG_SPL_TEXT_BASE - 0x40
-spl_csf_offset=$(xxd -s 24 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@")
-spl_bin_offset=$(xxd -s 4 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@")
-spl_dd_offset=$((${spl_csf_offset} - ${spl_bin_offset} + 0x40))
-dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc
-```
-
-CSF "Blocks" line for csf_fit.txt can be generated as follows:
-```
-# fitImage
-fit_block_base=$(printf "0x%x" $(sed -n "/CONFIG_SPL_LOAD_FIT_ADDRESS=/ s@.*=@@p" .config) )
-fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset))
-fit_block_size=$(printf "0x%x" $(( ( ( $(stat -tc %s u-boot.itb) + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) )
-sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\"@" csf_fit.tmp
-```
-
-The fitImage part of flash.bin requires separate IVT. Generate the IVT and
-patch it into the correct aligned location of flash.bin as follows:
-```
-# IVT
-ivt_ptr_base=$(printf "%08x" ${fit_block_base} | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-ivt_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} - 0x20 )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-csf_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-ivt_block_offset=$((${fit_block_offset} + ${fit_block_size} - 0x20))
-csf_block_offset=$((${ivt_block_offset} + 0x20))
-
-echo "0xd1002041 ${ivt_block_base} 0x00000000 0x00000000 0x00000000 ${ivt_block_base} ${csf_block_base} 0x00000000" | xxd -r -p > ivt.bin
-dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc
-```
-
-To generate CSF signature for the fitImage part of flash.bin container, use CST:
-```
-cst -i csf_fit.tmp -o csf_fit.bin
-```
-
-Finally, patch the CSF signature into the fitImage right past the IVT:
-```
-dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc
-```
-
-The entire script is available in doc/imx/habv4/csf_examples/mx8m/csf.sh
-and can be used as follows to modify flash.bin to be signed
-(adjust paths as needed):
+to authenticate, which keys to install, use and etc. The CSF is generated
+using the CST Code Signing Tool based on input configuration file. This tool
+input configuration file is generated using binman, and the tool is invoked
+from binman as well.
+
+The SPL and fitImage sections of the generated image are signed separately.
+The signing is activated by wrapping SPL and fitImage sections into nxp-imx8mcst
+etype, which is done automatically in arch/arm/dts/imx8m{m,n,p,q}-u-boot.dtsi
+in case CONFIG_IMX_HAB Kconfig symbol is enabled.
+
+Per default the HAB keys and certificates need to be located in the build
+directory, this means creating a symbolic link or copying the following files
+from the HAB keys directory flat (e.g. removing the `keys` and `cert`
+subdirectory) into the u-boot build directory for the CST Code Signing Tool to
+locate them:
+
+- `crts/SRK_1_2_3_4_table.bin`
+- `crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem`
+- `keys/CSF1_1_sha256_4096_65537_v3_usr_key.pem`
+- `crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem`
+- `keys/IMG1_1_sha256_4096_65537_v3_usr_key.pem`
+- `keys/key_pass.txt`
+
+The paths to the SRK table and the certificates can be modified via changes to
+the nxp_imx8mcst device tree node(s), however the other files are required by
+the CST tools as well, and will be searched for in relation to them.
+
+Build of flash.bin target then produces a signed flash.bin automatically.
+
+The nxp-imx8mcst etype is configurable using either DT properties or environment
+variables. The following DT properties and environment variables are supported.
+Note that environment variables override DT properties.
+
++--------------------+-----------+------------------------------------------------------------------+
+| DT property | Variable | Description |
++====================+===========+==================================================================+
+| nxp,loader-address | | SPL base address |
++--------------------+-----------+------------------------------------------------------------------+
+| nxp,srk-table | SRK_TABLE | full path to SRK_1_2_3_4_table.bin |
++--------------------+-----------+------------------------------------------------------------------+
+| nxp,csf-crt | CSF_KEY | full path to the CSF Key CSF1_1_sha256_4096_65537_v3_usr_crt.pem |
++--------------------+-----------+------------------------------------------------------------------+
+| nxp,img-crt | IMG_KEY | full path to the IMG Key IMG1_1_sha256_4096_65537_v3_usr_crt.pem |
++--------------------+-----------+------------------------------------------------------------------+
+
+Environment variables can be set as follows to point the build process
+to external key material:
```
export CST_DIR=/usr/src/cst-3.3.1/
export CSF_KEY=$CST_DIR/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem
export IMG_KEY=$CST_DIR/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem
export SRK_TABLE=$CST_DIR/crts/SRK_1_2_3_4_table.bin
-export PATH=$CST_DIR/linux64/bin:$PATH
-/bin/sh doc/imx/habv4/csf_examples/mx8m/csf.sh
+make flash.bin
```
1.4 Closing the device
.
.SH SYNOPSIS
.SY mkfwumdata
+.OP \-v version
.OP \-a activeidx
.OP \-p previousidx
.OP \-g
+.OP \-V vendor-file
.BI \-i\~ imagecount
.BI \-b\~ bankcount
.I UUIDs
Print usage information and exit.
.
.TP
+.B \-v
+Set
+.IR version
+as the metadata version to generate. Valid values 1 or 2.
+.
+.TP
.B \-a
Set
.IR activeidx
as GUIDs before use.
.
.TP
+.B \-V
+Pass
+.IR vendor-file
+for appending vendor data to the metadata. Supported only with version 2.
+.
+.TP
.B \-i
Specify there are
.IR imagecount
.EX
.in +4
$ \c
-.B mkfwumdata \-a 0 \-p 1 \-b 2 \-i 1 \\\\\&
+.B mkfwumdata \-v 2 \-a 0 \-p 1 \-b 2 \-i 1 \\\\\&
.in +6
.B 17e86d77-41f9-4fd7-87ec-a55df9842de5,\\\\\&
.B 10c36d7d-ca52-b843-b7b9-f9d6c501d108,\\\\\&
docutils==0.20.1
idna==3.7
imagesize==1.4.1
-Jinja2==3.1.3
+Jinja2==3.1.4
MarkupSafe==2.1.3
packaging==23.2
Pygments==2.17.2
ARMv7(32-bit) devices. The driver configures the cache settings
found in the device tree.
-config V5L2_CACHE
- bool "Andes V5L2 cache driver"
+config ANDES_L2_CACHE
+ bool "Andes L2 cache driver"
select CACHE
help
- Support Andes V5L2 cache controller in AE350 platform.
+ Support Andes L2 cache controller in AE350 platform.
It will configure tag and data ram timing control from the
device tree and enable L2 cache.
obj-$(CONFIG_SANDBOX) += sandbox_cache.o
obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
-obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
+obj-$(CONFIG_ANDES_L2_CACHE) += cache-andes-l2.o
obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o
volatile u64 cctl_command2;
volatile u64 cctl_access_line2;
volatile u64 cctl_command3;
- volatile u64 cctl_access_line4;
+ volatile u64 cctl_access_line3;
volatile u64 cctl_status;
};
DECLARE_GLOBAL_DATA_PTR;
-struct v5l2_plat {
+struct andes_l2_plat {
struct l2cache *regs;
u32 iprefetch;
u32 dprefetch;
u32 dram_ctl[2];
};
-static int v5l2_enable(struct udevice *dev)
+static int andes_l2_enable(struct udevice *dev)
{
- struct v5l2_plat *plat = dev_get_plat(dev);
+ struct andes_l2_plat *plat = dev_get_plat(dev);
volatile struct l2cache *regs = plat->regs;
if (regs)
return 0;
}
-static int v5l2_disable(struct udevice *dev)
+static int andes_l2_disable(struct udevice *dev)
{
- struct v5l2_plat *plat = dev_get_plat(dev);
+ struct andes_l2_plat *plat = dev_get_plat(dev);
volatile struct l2cache *regs = plat->regs;
u8 hart = gd->arch.boot_hart;
+
void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+ void __iomem *cctlstatus = (void __iomem *)CCTL_STATUS_REG(regs, hart);
if ((regs) && (readl(®s->control) & L2_ENABLE)) {
writel(L2_WBINVAL_ALL, cctlcmd);
- while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) {
- if ((readl(®s->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
+ while ((readl(cctlstatus) & CCTL_STATUS_MSK(hart))) {
+ if ((readl(cctlstatus) & CCTL_STATUS_ILLEGAL(hart))) {
printf("L2 flush illegal! hanging...");
hang();
}
return 0;
}
-static int v5l2_of_to_plat(struct udevice *dev)
+static int andes_l2_of_to_plat(struct udevice *dev)
{
- struct v5l2_plat *plat = dev_get_plat(dev);
+ struct andes_l2_plat *plat = dev_get_plat(dev);
struct l2cache *regs;
regs = dev_read_addr_ptr(dev);
return 0;
}
-static int v5l2_probe(struct udevice *dev)
+static int andes_l2_probe(struct udevice *dev)
{
- struct v5l2_plat *plat = dev_get_plat(dev);
+ struct andes_l2_plat *plat = dev_get_plat(dev);
struct l2cache *regs = plat->regs;
u32 cfg_val, ctl_val;
return 0;
}
-static const struct udevice_id v5l2_cache_ids[] = {
+static const struct udevice_id andes_l2_cache_ids[] = {
{ .compatible = "cache" },
{}
};
-static const struct cache_ops v5l2_cache_ops = {
- .enable = v5l2_enable,
- .disable = v5l2_disable,
+static const struct cache_ops andes_l2_cache_ops = {
+ .enable = andes_l2_enable,
+ .disable = andes_l2_disable,
};
-U_BOOT_DRIVER(v5l2_cache) = {
- .name = "v5l2_cache",
+U_BOOT_DRIVER(andes_l2_cache) = {
+ .name = "andes_l2_cache",
.id = UCLASS_CACHE,
- .of_match = v5l2_cache_ids,
- .of_to_plat = v5l2_of_to_plat,
- .probe = v5l2_probe,
- .plat_auto = sizeof(struct v5l2_plat),
- .ops = &v5l2_cache_ops,
+ .of_match = andes_l2_cache_ids,
+ .of_to_plat = andes_l2_of_to_plat,
+ .probe = andes_l2_probe,
+ .plat_auto = sizeof(struct andes_l2_plat),
+ .ops = &andes_l2_cache_ops,
.flags = DM_FLAG_PRE_RELOC,
};
case PCLK_HDMIPHY:
rate = rk3328_hdmiphy_get_clk(priv->cru);
break;
+ case SCLK_USB3OTG_REF:
+ rate = OSC_HZ;
+ break;
default:
return -ENOENT;
}
case PCLK_DDR:
case ACLK_GMAC:
case PCLK_GMAC:
+ case SCLK_USB3OTG_REF:
case SCLK_USB3OTG_SUSPEND:
case USB480M:
return 0;
return rk3399_saradc_get_clk(cru);
}
+static ulong rk3399_pciephy_get_clk(struct rockchip_cru *cru)
+{
+ if (readl(&cru->clksel_con[18]) & BIT(10))
+ return 100 * MHz;
+ else
+ return OSC_HZ;
+}
+
+static ulong rk3399_pciephy_set_clk(struct rockchip_cru *cru, uint hz)
+{
+ if (hz == 100 * MHz)
+ rk_setreg(&cru->clksel_con[18], BIT(10));
+ else if (hz == OSC_HZ)
+ rk_clrreg(&cru->clksel_con[18], BIT(10));
+ else
+ return -EINVAL;
+
+ return rk3399_pciephy_get_clk(cru);
+}
+
static ulong rk3399_clk_get_rate(struct clk *clk)
{
struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
case SCLK_UART1:
case SCLK_UART2:
case SCLK_UART3:
- return 24000000;
+ case SCLK_USB3OTG0_REF:
+ case SCLK_USB3OTG1_REF:
+ return OSC_HZ;
case PCLK_HDMI_CTRL:
break;
case DCLK_VOP0:
case SCLK_SARADC:
rate = rk3399_saradc_get_clk(priv->cru);
break;
+ case SCLK_PCIEPHY_REF:
+ rate = rk3399_pciephy_get_clk(priv->cru);
+ break;
case ACLK_VIO:
case ACLK_HDCP:
case ACLK_GIC_PRE:
case PCLK_DDR:
+ case ACLK_VDU:
break;
case PCLK_ALIVE:
case PCLK_WDT:
* return 0 to satisfy clk_set_defaults during device probe.
*/
return 0;
- case SCLK_DDRCLK:
+ case SCLK_DDRC:
ret = rk3399_ddr_set_clk(priv->cru, rate);
break;
case PCLK_EFUSE1024NS:
case SCLK_SARADC:
ret = rk3399_saradc_set_clk(priv->cru, rate);
break;
+ case SCLK_PCIEPHY_REF:
+ ret = rk3399_pciephy_set_clk(priv->cru, rate);
+ break;
case ACLK_VIO:
case ACLK_HDCP:
case ACLK_GIC_PRE:
case PCLK_DDR:
+ case ACLK_VDU:
return 0;
default:
log_debug("Unknown clock %lu\n", clk->id);
return -EINVAL;
}
+static int __maybe_unused rk3399_pciephy_set_parent(struct clk *clk,
+ struct clk *parent)
+{
+ struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
+ const char *clock_output_name;
+ int ret;
+
+ if (parent->dev == clk->dev && parent->id == SCLK_PCIEPHY_REF100M) {
+ rk_setreg(&priv->cru->clksel_con[18], BIT(10));
+ return 0;
+ }
+
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ if (!strcmp(clock_output_name, "xin24m")) {
+ rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
struct clk *parent)
{
switch (clk->id) {
case SCLK_RMII_SRC:
return rk3399_gmac_set_parent(clk, parent);
+ case SCLK_PCIEPHY_REF:
+ return rk3399_pciephy_set_parent(clk, parent);
}
debug("%s: unsupported clk %ld\n", __func__, clk->id);
rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
break;
case SCLK_PCIEPHY_REF:
- rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ if (readl(&priv->cru->clksel_con[18]) & BIT(10))
+ rk_clrreg(&priv->cru->clkgate_con[12], BIT(6));
break;
default:
debug("%s: unsupported clk %ld\n", __func__, clk->id);
rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
break;
case SCLK_PCIEPHY_REF:
- rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ if (readl(&priv->cru->clksel_con[18]) & BIT(10))
+ rk_setreg(&priv->cru->clkgate_con[12], BIT(6));
break;
default:
debug("%s: unsupported clk %ld\n", __func__, clk->id);
RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
RK3588_PLL_RATE(742500000, 4, 495, 2, 0),
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
+ RK3588_PLL_RATE(702000000, 3, 351, 2, 0),
RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
RK3588_PLL_RATE(200000000, 3, 400, 4, 0),
RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
[PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
+#ifdef CONFIG_SPL_BUILD
+ /*
+ * The SPLL is part of the SBUSCRU, not the main CRU and as
+ * such only directly accessible during the SPL stage.
+ */
+ [SPLL] = PLL(pll_rk3588, 0, RK3588_SBUSCRU_SPLL_CON(0),
+ RK3588_SBUSCRU_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
+#endif
+
};
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_SPL_BUILD
#define SCRU_BASE 0xfd7d0000
+#define SBUSCRU_BASE 0xfd7d8000
static ulong rk3588_scru_clk_get_rate(struct clk *clk)
{
return rk3588_scru_clk_get_rate(clk);
}
+static int rk3588_scru_clk_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[SPLL],
+ (void *)SBUSCRU_BASE, SPLL, SPLL_HZ);
+ if (ret)
+ debug("%s setting spll rate failed %d\n", __func__, ret);
+
+ return 0;
+}
+
static const struct clk_ops rk3588_scru_clk_ops = {
.get_rate = rk3588_scru_clk_get_rate,
.set_rate = rk3588_scru_clk_set_rate,
};
U_BOOT_DRIVER(rockchip_rk3588_scru) = {
- .name = "rockchip_rk3588_scru",
- .id = UCLASS_CLK,
- .ops = &rk3588_scru_clk_ops,
+ .name = "rockchip_rk3588_scru",
+ .id = UCLASS_CLK,
+ .ops = &rk3588_scru_clk_ops,
+ .probe = rk3588_scru_clk_probe,
};
static int rk3588_scmi_spl_glue_bind(struct udevice *dev)
#include <cpu.h>
#include <dm.h>
#include <log.h>
-#include <vsprintf.h>
+#include <stdio.h>
#include <linux/bitops.h>
#include "mpc83xx_cpu.h"
const char *cpu;
cpu = dev_read_string(dev, "compatible");
- if (size < (strlen(cpu) + 1))
+ if (!cpu || size < (strlen(cpu) + 1))
return -ENOSPC;
strcpy(buf, cpu);
/* MD5 */
static void hash_init_md5(void *ctx)
{
- MD5Init((struct MD5Context *)ctx);
+ MD5Init((MD5Context *)ctx);
}
static void hash_update_md5(void *ctx, const void *ibuf, uint32_t ilen)
{
- MD5Update((struct MD5Context *)ctx, ibuf, ilen);
+ MD5Update((MD5Context *)ctx, ibuf, ilen);
}
static void hash_finish_md5(void *ctx, void *obuf)
{
- MD5Final(obuf, (struct MD5Context *)ctx);
+ MD5Final(obuf, (MD5Context *)ctx);
}
/* SHA1 */
.init = hash_init_md5,
.update = hash_update_md5,
.finish = hash_finish_md5,
- .ctx_alloc_sz = sizeof(struct MD5Context),
+ .ctx_alloc_sz = sizeof(MD5Context),
},
[HASH_ALGO_SHA1] = {
cppi5_hdesc_set_pktlen(desc_rx, size);
cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size);
+ invalidate_dcache_range((unsigned long)dma_dst,
+ (unsigned long)(dma_dst + size));
+
flush_dcache_range((unsigned long)desc_rx,
ALIGN((unsigned long)desc_rx + uc->config.hdesc_size,
ARCH_DMA_MINALIGN));
*
* Return: 0 if OK, -ve on error
*/
-int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
+int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary,
+ uint32_t size)
{
const struct fwu_mdata_ops *ops = device_get_ops(dev);
return -ENOSYS;
}
- return ops->read_mdata(dev, mdata, primary);
+ return ops->read_mdata(dev, mdata, primary, size);
}
/**
*
* Return: 0 if OK, -ve on error
*/
-int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
+int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary,
+ uint32_t size)
{
const struct fwu_mdata_ops *ops = device_get_ops(dev);
return -ENOSYS;
}
- return ops->write_mdata(dev, mdata, primary);
+ return ops->write_mdata(dev, mdata, primary, size);
}
UCLASS_DRIVER(fwu_mdata) = {
return -ENOENT;
}
-static int gpt_read_write_mdata(struct blk_desc *desc,
- struct fwu_mdata *mdata,
- u8 access, u32 part_num)
+static int gpt_read_write_mdata(struct blk_desc *desc, struct fwu_mdata *mdata,
+ u8 access, u32 part_num, u32 size)
{
int ret;
u32 len, blk_start, blkcnt;
struct disk_partition info;
- ALLOC_CACHE_ALIGN_BUFFER_PAD(struct fwu_mdata, mdata_aligned, 1,
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(u8, mdata_aligned, size,
desc->blksz);
if (!mdata)
return -ENOENT;
}
- len = sizeof(*mdata);
+ len = size;
blkcnt = BLOCK_CNT(len, desc);
if (blkcnt > info.size) {
log_debug("Block count exceeds FWU metadata partition size\n");
log_debug("Error reading FWU metadata from the device\n");
return -EIO;
}
- memcpy(mdata, mdata_aligned, sizeof(struct fwu_mdata));
+ memcpy(mdata, mdata_aligned, size);
} else {
if (blk_dwrite(desc, blk_start, blkcnt, mdata) != blkcnt) {
log_debug("Error writing FWU metadata to the device\n");
}
static int fwu_gpt_read_mdata(struct udevice *dev, struct fwu_mdata *mdata,
- bool primary)
+ bool primary, u32 size)
{
struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
struct blk_desc *desc = dev_get_uclass_plat(priv->blk_dev);
}
return gpt_read_write_mdata(desc, mdata, MDATA_READ,
- primary ? g_mdata_part[0] : g_mdata_part[1]);
+ primary ?
+ g_mdata_part[0] : g_mdata_part[1],
+ size);
}
static int fwu_gpt_write_mdata(struct udevice *dev, struct fwu_mdata *mdata,
- bool primary)
+ bool primary, u32 size)
{
struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev);
struct blk_desc *desc = dev_get_uclass_plat(priv->blk_dev);
}
return gpt_read_write_mdata(desc, mdata, MDATA_WRITE,
- primary ? g_mdata_part[0] : g_mdata_part[1]);
+ primary ?
+ g_mdata_part[0] : g_mdata_part[1],
+ size);
}
static const struct fwu_mdata_ops fwu_gpt_blk_ops = {
#include <linux/errno.h>
#include <linux/types.h>
-/* Internal helper structure to move data around */
-struct fwu_mdata_mtd_priv {
- struct mtd_info *mtd;
- char pri_label[50];
- char sec_label[50];
- u32 pri_offset;
- u32 sec_offset;
-};
-
enum fwu_mtd_op {
FWU_MTD_READ,
FWU_MTD_WRITE,
};
-extern struct fwu_mtd_image_info fwu_mtd_images[];
-
static bool mtd_is_aligned_with_block_size(struct mtd_info *mtd, u64 size)
{
return !do_div(size, mtd->erasesize);
return ret;
}
-static int fwu_mtd_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
+static int fwu_mtd_read_mdata(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary, u32 size)
{
struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
struct mtd_info *mtd = mtd_priv->mtd;
u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset;
- return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_READ);
+ return mtd_io_data(mtd, offs, size, mdata, FWU_MTD_READ);
}
-static int fwu_mtd_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary)
+static int fwu_mtd_write_mdata(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary, u32 size)
{
struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
struct mtd_info *mtd = mtd_priv->mtd;
u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset;
- return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_WRITE);
+ return mtd_io_data(mtd, offs, size, mdata, FWU_MTD_WRITE);
}
static int flash_partition_offset(struct udevice *dev, const char *part_name, fdt_addr_t *offset)
return (int)size;
}
-static int fwu_mdata_mtd_of_to_plat(struct udevice *dev)
+static int get_fwu_mdata_dev(struct udevice *dev)
{
struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
const fdt32_t *phandle_p = NULL;
fdt_addr_t offset;
int ret, size;
u32 phandle;
- ofnode bank;
- int off_img;
/* Find the FWU mdata storage device */
phandle_p = ofnode_get_property(dev_ofnode(dev),
return ret;
mtd_priv->sec_offset = offset;
- off_img = 0;
+ return 0;
+}
+
+static int fwu_mtd_image_info_populate(struct udevice *dev, u8 nbanks,
+ u16 nimages)
+{
+ struct fwu_mtd_image_info *mtd_images;
+ struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev);
+ struct udevice *mtd_dev = mtd_priv->mtd->dev;
+ fdt_addr_t offset;
+ ofnode bank;
+ int off_img;
+ u32 total_images;
+ total_images = nbanks * nimages;
+ mtd_priv->fwu_mtd_images = malloc(sizeof(struct fwu_mtd_image_info) *
+ total_images);
+ if (!mtd_priv->fwu_mtd_images)
+ return -ENOMEM;
+
+ off_img = 0;
+ mtd_images = mtd_priv->fwu_mtd_images;
ofnode_for_each_subnode(bank, dev_ofnode(dev)) {
int bank_num, bank_offset, bank_size;
const char *bank_name;
int image_num, image_offset, image_size;
const char *uuid;
- if (off_img == CONFIG_FWU_NUM_BANKS *
- CONFIG_FWU_NUM_IMAGES_PER_BANK) {
+ if (off_img == total_images) {
log_err("DT provides more images than configured!\n");
break;
}
ofnode_read_u32(image, "offset", &image_offset);
ofnode_read_u32(image, "size", &image_size);
- fwu_mtd_images[off_img].start = bank_offset + image_offset;
- fwu_mtd_images[off_img].size = image_size;
- fwu_mtd_images[off_img].bank_num = bank_num;
- fwu_mtd_images[off_img].image_num = image_num;
- strcpy(fwu_mtd_images[off_img].uuidbuf, uuid);
+ mtd_images[off_img].start = bank_offset + image_offset;
+ mtd_images[off_img].size = image_size;
+ mtd_images[off_img].bank_num = bank_num;
+ mtd_images[off_img].image_num = image_num;
+ strcpy(mtd_images[off_img].uuidbuf, uuid);
log_debug("\tImage%d: %s @0x%x\n\n",
image_num, uuid, bank_offset + image_offset);
off_img++;
static int fwu_mdata_mtd_probe(struct udevice *dev)
{
- /* Ensure the metadata can be read. */
- return fwu_get_mdata(NULL);
+ u8 nbanks;
+ u16 nimages;
+ int ret;
+
+ ret = get_fwu_mdata_dev(dev);
+ if (ret)
+ return ret;
+
+ nbanks = CONFIG_FWU_NUM_BANKS;
+ nimages = CONFIG_FWU_NUM_IMAGES_PER_BANK;
+ ret = fwu_mtd_image_info_populate(dev, nbanks, nimages);
+ if (ret)
+ return ret;
+
+ return 0;
}
static struct fwu_mdata_ops fwu_mtd_ops = {
.of_match = fwu_mdata_ids,
.ops = &fwu_mtd_ops,
.probe = fwu_mdata_mtd_probe,
- .of_to_plat = fwu_mdata_mtd_of_to_plat,
.priv_auto = sizeof(struct fwu_mdata_mtd_priv),
};
#include <dm/device_compat.h>
#include <linux/bitfield.h>
#include <linux/delay.h>
+#include <dt-bindings/phy/nuvoton,npcm-usbphy.h>
/* GCR Register Offsets */
#define GCR_INTCR3 0x9C
#define USBPHY3SW_HOST2 FIELD_PREP(USBPHY3SW, 1)
#define USBPHY3SW_DEV8_PHY3 FIELD_PREP(USBPHY3SW, 3)
-enum controller_id {
- UDC0_7,
- UDC8,
- UDC9,
- USBH1,
- USBH2,
-};
-
enum phy_id {
PHY1 = 1,
PHY2,
};
/* Phy Switch Settings */
-#define USBDPHY1 ((PHY1 << 8) | UDC0_7) /* Connect UDC0~7 to PHY1 */
-#define USBD8PHY1 ((PHY1 << 8) | UDC8) /* Connect UDC8 to PHY1 */
-#define USBD9PHY1 ((PHY1 << 8) | UDC9) /* Connect UDC9 to PHY1 */
-#define USBD9PHY2 ((PHY2 << 8) | UDC9) /* Connect UDC9 to PHY2 */
-#define USBH1PHY2 ((PHY2 << 8) | USBH1) /* Connect USBH1 to PHY2 */
-#define USBD8PHY3 ((PHY3 << 8) | UDC8) /* Connect UDC8 to PHY3 */
-#define USBH2PHY3 ((PHY3 << 8) | USBH2) /* Connect USBH2 to PHY3 */
+#define USBDPHY1 ((PHY1 << 8) | NPCM_UDC0_7) /* Connect UDC0~7 to PHY1 */
+#define USBD8PHY1 ((PHY1 << 8) | NPCM_UDC8) /* Connect UDC8 to PHY1 */
+#define USBD9PHY1 ((PHY1 << 8) | NPCM_UDC9) /* Connect UDC9 to PHY1 */
+#define USBD9PHY2 ((PHY2 << 8) | NPCM_UDC9) /* Connect UDC9 to PHY2 */
+#define USBH1PHY2 ((PHY2 << 8) | NPCM_USBH1) /* Connect USBH1 to PHY2 */
+#define USBD8PHY3 ((PHY3 << 8) | NPCM_UDC8) /* Connect UDC8 to PHY3 */
+#define USBH2PHY3 ((PHY3 << 8) | NPCM_USBH2) /* Connect USBH2 to PHY3 */
struct npcm_usbphy {
struct regmap *syscon;
return 0;
}
-static int npcm_usb_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args)
+static int npcm_usb_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args)
{
struct npcm_usbphy *priv = dev_get_priv(phy->dev);
u16 phy_switch;
- if (args->args_count < 1 || args->args[0] > USBH2)
+ if (args->args_count < 1 || args->args[0] > NPCM_MAX_USB_CTRL_ID)
return -EINVAL;
phy_switch = (priv->id << 8) | args->args[0];
#include <reset.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
-
+#include <dt-bindings/phy/phy.h>
#include <linux/usb/phy-rockchip-usbdp.h>
#define BIT_WRITEABLE_SHIFT 16
struct rockchip_udphy;
struct rockchip_udphy_cfg {
+ unsigned int num_phys;
+ unsigned int phy_ids[2];
/* resets to be requested */
const char * const *rst_list;
int num_rsts;
return 0;
}
+static int rockchip_u3phy_of_xlate(struct phy *phy,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count == 0)
+ return -EINVAL;
+
+ if (args->args[0] != PHY_TYPE_USB3)
+ return -EINVAL;
+
+ return 0;
+}
+
static int rockchip_u3phy_init(struct phy *phy)
{
- struct udevice *parent = phy->dev->parent;
- struct rockchip_udphy *udphy = dev_get_priv(parent);
+ struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
/* DP only or high-speed, disable U3 port */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
static int rockchip_u3phy_exit(struct phy *phy)
{
- struct udevice *parent = phy->dev->parent;
- struct rockchip_udphy *udphy = dev_get_priv(parent);
+ struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
/* DP only or high-speed */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
}
static const struct phy_ops rockchip_u3phy_ops = {
+ .of_xlate = rockchip_u3phy_of_xlate,
.init = rockchip_u3phy_init,
.exit = rockchip_u3phy_exit,
};
-int rockchip_u3phy_uboot_init(void)
-{
- struct udevice *udev;
- struct rockchip_udphy *udphy;
- int ret;
-
- ret = uclass_get_device_by_driver(UCLASS_PHY,
- DM_DRIVER_GET(rockchip_udphy_u3_port),
- &udev);
- if (ret) {
- pr_err("%s: get u3-port failed: %d\n", __func__, ret);
- return ret;
- }
-
- /* DP only or high-speed, disable U3 port */
- udphy = dev_get_priv(udev->parent);
- if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
- udphy_u3_port_disable(udphy, true);
- return 0;
- }
-
- return udphy_power_on(udphy, UDPHY_MODE_USB);
-}
-
static int rockchip_udphy_probe(struct udevice *dev)
{
- const struct device_node *np = ofnode_to_np(dev_ofnode(dev));
struct rockchip_udphy *udphy = dev_get_priv(dev);
const struct rockchip_udphy_cfg *phy_cfgs;
+ unsigned int reg;
int id, ret;
udphy->dev = dev;
- id = of_alias_get_id(np, "usbdp");
- if (id < 0)
- id = 0;
- udphy->id = id;
+ ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, ®);
+ if (ret) {
+ dev_err(dev, "failed to read reg[0] property\n");
+ return ret;
+ }
+ if (reg == 0 && dev_read_addr_cells(dev) == 2) {
+ ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, ®);
+ if (ret) {
+ dev_err(dev, "failed to read reg[1] property\n");
+ return ret;
+ }
+ }
phy_cfgs = (const struct rockchip_udphy_cfg *)dev_get_driver_data(dev);
if (!phy_cfgs) {
}
udphy->cfgs = phy_cfgs;
+ /* find the phy-id from the io address */
+ udphy->id = -ENODEV;
+ for (id = 0; id < udphy->cfgs->num_phys; id++) {
+ if (reg == udphy->cfgs->phy_ids[id]) {
+ udphy->id = id;
+ break;
+ }
+ }
+
+ if (udphy->id < 0) {
+ dev_err(dev, "no matching device found\n");
+ return -ENODEV;
+ }
+
ret = regmap_init_mem(dev_ofnode(dev), &udphy->pma_regmap);
if (ret)
return ret;
return 0;
}
-static int rockchip_udphy_bind(struct udevice *parent)
-{
- struct udevice *child;
- ofnode subnode;
- const char *node_name;
- int ret;
-
- dev_for_each_subnode(subnode, parent) {
- if (!ofnode_valid(subnode)) {
- printf("%s: no subnode for %s", __func__, parent->name);
- return -ENXIO;
- }
-
- node_name = ofnode_get_name(subnode);
- debug("%s: subnode %s\n", __func__, node_name);
-
- /* if there is no match, continue */
- if (strcasecmp(node_name, "usb3-port"))
- continue;
-
- /* node name is usb3-port */
- ret = device_bind_driver_to_node(parent,
- "rockchip_udphy_u3_port",
- node_name, subnode, &child);
- if (ret) {
- printf("%s: '%s' cannot bind its driver\n",
- __func__, node_name);
- return ret;
- }
- }
-
- return 0;
-}
-
static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
{
/* configure phy reference clock */
};
static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
+ .num_phys = 2,
+ .phy_ids = {
+ 0xfed80000,
+ 0xfed90000,
+ },
.num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
.rst_list = rk3588_udphy_rst_l,
.grfcfg = {
{ /* sentinel */ }
};
-U_BOOT_DRIVER(rockchip_udphy_u3_port) = {
- .name = "rockchip_udphy_u3_port",
- .id = UCLASS_PHY,
- .ops = &rockchip_u3phy_ops,
-};
-
U_BOOT_DRIVER(rockchip_udphy) = {
.name = "rockchip_udphy",
.id = UCLASS_PHY,
.of_match = rockchip_udphy_dt_match,
.probe = rockchip_udphy_probe,
- .bind = rockchip_udphy_bind,
+ .ops = &rockchip_u3phy_ops,
.priv_auto = sizeof(struct rockchip_udphy),
};
pfc_base = args.args[1];
pfc_pins = args.args[2];
- if (offset >= gpio_offset && offset <= gpio_offset + pfc_pins)
+ if (offset >= gpio_offset && offset < gpio_offset + pfc_pins)
break;
}
/* legacy reset */
ret = gpio_request_by_name(dev, "gpio-reset", 0,
&reset_gpio, GPIOD_IS_OUT);
- if (ret) {
+ if (!ret) {
log(LOGC_NONE, LOGL_NOTICE,
- "%s: missing reset GPIO\n", __func__);
- goto init;
+ "%s: gpio-reset is deprecated\n", __func__);
}
- log(LOGC_NONE, LOGL_NOTICE,
- "%s: gpio-reset is deprecated\n", __func__);
}
- dm_gpio_set_value(&reset_gpio, 1);
- mdelay(1);
- dm_gpio_set_value(&reset_gpio, 0);
+
+ if (!ret) {
+ log(LOGC_NONE, LOGL_WARNING,
+ "%s: TPM gpio reset should not be used on secure production devices\n",
+ dev->name);
+ dm_gpio_set_value(&reset_gpio, 1);
+ mdelay(1);
+ dm_gpio_set_value(&reset_gpio, 0);
+ }
}
-init:
+
/* Ensure a minimum amount of time elapsed since reset of the TPM */
mdelay(drv_data->time_before_first_cmd_ms);
writel(USB_IEN_INIT, ®s->usb_ien);
writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, ®s->usb_conf);
+ /* Set the Fast access bit */
+ writel(PUSB_PWR_FST_REG_ACCESS, &priv_dev->regs->usb_pwr);
+
cdns3_configure_dmult(priv_dev, NULL);
cdns3_gadget_pullup(&priv_dev->gadget, 1);
/* disable interrupt for device */
writel(0, &priv_dev->regs->usb_ien);
+ writel(0, &priv_dev->regs->usb_pwr);
writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
return ret;
#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
+#define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
+
/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
#define DWC3_DALEPENA_EP(n) (1 << n)
unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
{
u32 timeout = 500;
+ u32 saved_config = 0;
u32 reg;
+ int ret = -EINVAL;
+
+ /*
+ * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
+ * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
+ * endpoint command.
+ *
+ * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
+ * settings. Restore them after the command is completed.
+ *
+ * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
+ */
+ if (dwc->gadget.speed <= USB_SPEED_HIGH ||
+ DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+ if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
+ saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
+ reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
+ }
+
+ if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
+ saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
+ reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
+ }
+
+ if (saved_config)
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ }
+
dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
if (!(reg & DWC3_DEPCMD_CMDACT)) {
dev_vdbg(dwc->dev, "Command Complete --> %d\n",
DWC3_DEPCMD_STATUS(reg));
- return 0;
+ ret = 0;
+ break;
}
/*
* interrupt context.
*/
timeout--;
- if (!timeout)
- return -ETIMEDOUT;
+ if (!timeout) {
+ ret = -ETIMEDOUT;
+ break;
+ }
udelay(1);
} while (1);
+
+ if (saved_config) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+ reg |= saved_config;
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ }
+
+ return ret;
}
static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
-Wno-unique_unit_address \
-Wunique_unit_address_if_enabled
-# Disable undocumented compatible checks until warning free
-override DT_CHECKER_FLAGS ?=
-
$(obj)/processed-schema.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
$(call if_changed_rule,chkdt)
title: Amlogic SoC based Platforms
maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ - Jerome Brunet <jbrunet@baylibre.com>
- Kevin Hilman <khilman@baylibre.com>
-description: |+
- Work in progress statement:
-
- Device tree files and bindings applying to Amlogic SoCs and boards are
- considered "unstable". Any Amlogic device tree binding may change at
- any time. Be sure to use a device tree binary and a kernel image
- generated from the same source tree.
-
- Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
- stable binding/ABI.
-
properties:
$nodename:
const: '/'
- enum:
- amediatech,x96-max
- amlogic,u200
+ - freebox,fbx8am
- radxa,zero
- seirobotics,sei510
- const: amlogic,g12a
- Linus Walleij <linus.walleij@linaro.org>
description: |+
- The ARM RealView series of reference designs were built to explore the ARM
- 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
- the earlier CPUs such as TrustZone and multicore (MPCore).
+ The ARM RealView series of reference designs were built to explore the Arm11,
+ Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the
+ earlier CPUs such as TrustZone and multicore (MPCore).
properties:
$nodename:
- const: microchip,sama7g5
- const: microchip,sama7
+ - description: Microchip SAMA7G54 Curiosity Board
+ items:
+ - const: microchip,sama7g54-curiosity
+ - const: microchip,sama7g5
+ - const: microchip,sama7
+
- description: Microchip LAN9662 Evaluation Boards.
items:
- enum:
- toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board
- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board
- toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board
- - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board
+ - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board v1.0/v1.1
+ - toradex,apalis_imx6q-eval-v1.2 # Apalis iMX6Q/D Module on Apalis Evaluation Board v1.2
- const: toradex,apalis_imx6q
- const: fsl,imx6q
- prt,prtvt7 # Protonic VT7 board
- rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board
- riot,imx6s-riotboard # RIoTboard i.MX6S
+ - sielaff,imx6dl-board # Sielaff i.MX6 Solo Board
- skov,imx6dl-skov-revc-lt2 # SKOV IMX6 CPU SoloCore lt2
- skov,imx6dl-skov-revc-lt6 # SKOV IMX6 CPU SoloCore lt6
- solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite
- toradex,colibri-imx6ull # Colibri iMX6ULL Modules
- toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
- toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules
+ - uni-t,uti260b # UNI-T UTi260B Thermal Camera
- const: fsl,imx6ull
- description: i.MX6ULL Armadeus Systems OPOS6ULDev Board
items:
- enum:
- dimonoff,gateway-evk # i.MX8MN Dimonoff Gateway EVK Board
- - rve,rve-gateway # i.MX8MN RVE Gateway Board
+ - rve,gateway # i.MX8MN RVE Gateway Board
- variscite,var-som-mx8mn-symphony
- const: variscite,var-som-mx8mn
- const: fsl,imx8mn
- description: i.MX8QM Boards with Toradex Apalis iMX8 Modules
items:
- enum:
- - toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation Board
+ - toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation V1.0/V1.1 Board
+ - toradex,apalis-imx8-eval-v1.2 # Apalis iMX8 Module on Apalis Evaluation V1.2 Board
- toradex,apalis-imx8-ixora-v1.1 # Apalis iMX8 Module on Ixora V1.1 Carrier Board
- const: toradex,apalis-imx8
- const: fsl,imx8qm
- description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules
items:
- enum:
- - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. Board
+ - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. V1.0/V1.1 Board
+ - toradex,apalis-imx8-v1.1-eval-v1.2 # Apalis iMX8 V1.1 Module on Apalis Eval. V1.2 Board
- toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board
- toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board
- const: toradex,apalis-imx8-v1.1
- const: toradex,colibri-imx8x
- const: fsl,imx8qxp
+ - description:
+ TQMa8Xx is a series of SOM featuring NXP i.MX8X system-on-chip
+ variants. It is designed to be clicked on different carrier boards
+ MBa8Xx is the starterkit
+ oneOf:
+ - items:
+ - enum:
+ - tq,imx8dxp-tqma8xdp-mba8xx # TQ-Systems GmbH TQMa8XDP SOM on MBa8Xx
+ - const: tq,imx8dxp-tqma8xdp # TQ-Systems GmbH TQMa8XDP SOM (with i.MX8DXP)
+ - const: fsl,imx8dxp
+ - items:
+ - enum:
+ - tq,imx8qxp-tqma8xqp-mba8xx # TQ-Systems GmbH TQMa8XQP SOM on MBa8Xx
+ - const: tq,imx8qxp-tqma8xqp # TQ-Systems GmbH TQMa8XQP SOM (with i.MX8QXP)
+ - const: fsl,imx8qxp
+
- description: i.MX8ULP based Boards
items:
- enum:
- const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM
- const: fsl,imx93
+ - description: PHYTEC phyCORE-i.MX93 SoM based boards
+ items:
+ - const: phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93
+ - const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM
+ - const: fsl,imx93
+
+ - description: Variscite VAR-SOM-MX93 based boards
+ items:
+ - const: variscite,var-som-mx93-symphony
+ - const: variscite,var-som-mx93
+ - const: fsl,imx93
+
- description:
Freescale Vybrid Platform Device Tree Bindings
+++ /dev/null
-Marvell Armada 38x Platforms Device Tree Bindings
--------------------------------------------------
-
-Boards with a SoC of the Marvell Armada 38x family shall have the
-following property:
-
-Required root node property:
-
- - compatible: must contain "marvell,armada380"
-
-In addition, boards using the Marvell Armada 385 SoC shall have the
-following property before the previous one:
-
-Required root node property:
-
-compatible: must contain "marvell,armada385"
-
-In addition, boards using the Marvell Armada 388 SoC shall have the
-following property before the previous one:
-
-Required root node property:
-
-compatible: must contain "marvell,armada388"
-
-Example:
-
-compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/marvell/armada-38x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Armada 38x Platforms
+
+maintainers:
+ - Gregory CLEMENT <gregory.clement@bootlin.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description:
+ Netgear Armada 380 GS110EM Managed Switch.
+ items:
+ - const: netgear,gs110emx
+ - const: marvell,armada380
+
+ - description:
+ Marvell Armada 385 Development Boards.
+ items:
+ - enum:
+ - marvell,a385-db-amc
+ - marvell,a385-db-ap
+ - const: marvell,armada385
+ - const: marvell,armada380
+
+ - description:
+ SolidRun Armada 385 based single-board computers.
+ items:
+ - enum:
+ - solidrun,clearfog-gtr-l8
+ - solidrun,clearfog-gtr-s4
+ - const: marvell,armada385
+ - const: marvell,armada380
+
+ - description:
+ Kobol Armada 388 based Helios-4 NAS.
+ items:
+ - const: kobol,helios4
+ - const: marvell,armada388
+ - const: marvell,armada385
+ - const: marvell,armada380
+
+ - description:
+ Marvell Armada 388 Development Boards.
+ items:
+ - enum:
+ - marvell,a388-gp
+ - const: marvell,armada388
+ - const: marvell,armada385
+ - const: marvell,armada380
+
+ - description:
+ SolidRun Armada 388 clearfog family single-board computers.
+ items:
+ - enum:
+ - solidrun,clearfog-base-a1
+ - solidrun,clearfog-pro-a1
+ - const: solidrun,clearfog-a1
+ - const: marvell,armada388
+ - const: marvell,armada385
+ - const: marvell,armada380
+
+additionalProperties: true
const: '/'
compatible:
oneOf:
+ # Sort by SoC (last) compatible, then board compatible
- items:
- enum:
- mediatek,mt2701-evb
- const: mediatek,mt7629
- items:
- enum:
+ - xiaomi,ax3000t
+ - const: mediatek,mt7981b
+ - items:
+ - enum:
+ - acelink,ew-7886cax
- bananapi,bpi-r3
- mediatek,mt7986a-rfb
- const: mediatek,mt7986a
- enum:
- mediatek,mt7986b-rfb
- const: mediatek,mt7986b
+ - items:
+ - enum:
+ - bananapi,bpi-r4
+ - const: mediatek,mt7988a
- items:
- enum:
- mediatek,mt8127-moose
- enum:
- mediatek,mt8173-evb
- const: mediatek,mt8173
- - items:
- - enum:
- - mediatek,mt8183-evb
- - const: mediatek,mt8183
- - description: Google Hayato rev5
- items:
- - const: google,hayato-rev5-sku2
- - const: google,hayato-sku2
- - const: google,hayato
- - const: mediatek,mt8192
- - description: Google Hayato
- items:
- - const: google,hayato-rev1
- - const: google,hayato
- - const: mediatek,mt8192
- - description: Google Spherion rev4 (Acer Chromebook 514)
- items:
- - const: google,spherion-rev4
- - const: google,spherion
- - const: mediatek,mt8192
- - description: Google Spherion (Acer Chromebook 514)
- items:
- - const: google,spherion-rev3
- - const: google,spherion-rev2
- - const: google,spherion-rev1
- - const: google,spherion-rev0
- - const: google,spherion
- - const: mediatek,mt8192
- - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)
- items:
- - enum:
- - google,tomato-rev2
- - google,tomato-rev1
- - const: google,tomato
- - const: mediatek,mt8195
- - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)
- items:
- - const: google,tomato-rev4
- - const: google,tomato-rev3
- - const: google,tomato
- - const: mediatek,mt8195
- - items:
- - enum:
- - mediatek,mt8186-evb
- - const: mediatek,mt8186
- - items:
- - enum:
- - mediatek,mt8188-evb
- - const: mediatek,mt8188
- - items:
- - enum:
- - mediatek,mt8192-evb
- - const: mediatek,mt8192
- - items:
- - enum:
- - mediatek,mt8195-demo
- - mediatek,mt8195-evb
- - const: mediatek,mt8195
- description: Google Burnet (HP Chromebook x360 11MK G3 EE)
items:
- const: google,burnet
- const: mediatek,mt8183
- - description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
- items:
- - enum:
- - google,krane-sku0
- - google,krane-sku176
- - const: google,krane
- - const: mediatek,mt8183
- description: Google Cozmo (Acer Chromebook 314)
items:
- const: google,cozmo
- google,kodama-sku32
- const: google,kodama
- const: mediatek,mt8183
+ - description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
+ items:
+ - enum:
+ - google,krane-sku0
+ - google,krane-sku176
+ - const: google,krane
+ - const: mediatek,mt8183
- description: Google Makomo (Lenovo 100e Chromebook 2nd Gen MTK 2)
items:
- enum:
- google,willow-sku1
- const: google,willow
- const: mediatek,mt8183
+ - items:
+ - enum:
+ - mediatek,mt8183-evb
+ - const: mediatek,mt8183
- items:
- enum:
- mediatek,mt8183-pumpkin
- const: mediatek,mt8183
+ - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
+ items:
+ - const: google,steelix-sku393219
+ - const: google,steelix-sku393216
+ - const: google,steelix
+ - const: mediatek,mt8186
+ - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
+ items:
+ - const: google,steelix-sku393220
+ - const: google,steelix-sku393217
+ - const: google,steelix
+ - const: mediatek,mt8186
+ - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
+ items:
+ - const: google,steelix-sku393221
+ - const: google,steelix-sku393218
+ - const: google,steelix
+ - const: mediatek,mt8186
+ - description: Google Rusty (Lenovo 100e Chromebook Gen 4)
+ items:
+ - const: google,steelix-sku196609
+ - const: google,steelix-sku196608
+ - const: google,steelix
+ - const: mediatek,mt8186
+ - description: Google Steelix (Lenovo 300e Yoga Chromebook Gen 4)
+ items:
+ - enum:
+ - google,steelix-sku131072
+ - google,steelix-sku131073
+ - const: google,steelix
+ - const: mediatek,mt8186
+ - description: Google Tentacruel (ASUS Chromebook CM14 Flip CM1402F)
+ items:
+ - const: google,tentacruel-sku262147
+ - const: google,tentacruel-sku262146
+ - const: google,tentacruel-sku262145
+ - const: google,tentacruel-sku262144
+ - const: google,tentacruel
+ - const: mediatek,mt8186
+ - description: Google Tentacruel (ASUS Chromebook CM14 Flip CM1402F)
+ items:
+ - const: google,tentacruel-sku262151
+ - const: google,tentacruel-sku262150
+ - const: google,tentacruel-sku262149
+ - const: google,tentacruel-sku262148
+ - const: google,tentacruel
+ - const: mediatek,mt8186
+ - description: Google Tentacool (ASUS Chromebook CM14 CM1402C)
+ items:
+ - const: google,tentacruel-sku327681
+ - const: google,tentacruel
+ - const: mediatek,mt8186
+ - description: Google Tentacool (ASUS Chromebook CM14 CM1402C)
+ items:
+ - const: google,tentacruel-sku327683
+ - const: google,tentacruel
+ - const: mediatek,mt8186
+ - items:
+ - enum:
+ - mediatek,mt8186-evb
+ - const: mediatek,mt8186
+ - items:
+ - enum:
+ - mediatek,mt8188-evb
+ - const: mediatek,mt8188
+ - description: Google Hayato
+ items:
+ - const: google,hayato-rev1
+ - const: google,hayato
+ - const: mediatek,mt8192
+ - description: Google Hayato rev5
+ items:
+ - const: google,hayato-rev5-sku2
+ - const: google,hayato-sku2
+ - const: google,hayato
+ - const: mediatek,mt8192
+ - description: Google Spherion (Acer Chromebook 514)
+ items:
+ - const: google,spherion-rev3
+ - const: google,spherion-rev2
+ - const: google,spherion-rev1
+ - const: google,spherion-rev0
+ - const: google,spherion
+ - const: mediatek,mt8192
+ - description: Google Spherion rev4 (Acer Chromebook 514)
+ items:
+ - const: google,spherion-rev4
+ - const: google,spherion
+ - const: mediatek,mt8192
+ - items:
+ - enum:
+ - mediatek,mt8192-evb
+ - const: mediatek,mt8192
+ - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)
+ items:
+ - enum:
+ - google,tomato-rev2
+ - google,tomato-rev1
+ - const: google,tomato
+ - const: mediatek,mt8195
+ - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)
+ items:
+ - const: google,tomato-rev4
+ - const: google,tomato-rev3
+ - const: google,tomato
+ - const: mediatek,mt8195
+ - items:
+ - enum:
+ - mediatek,mt8195-demo
+ - mediatek,mt8195-evb
+ - const: mediatek,mt8195
- items:
- enum:
- mediatek,mt8365-evk
- items:
- enum:
- mediatek,mt8395-evk
+ - radxa,nio-12l
- const: mediatek,mt8395
- const: mediatek,mt8195
- items:
+++ /dev/null
-Mediatek hifsys controller
-============================
-
-The Mediatek hifsys controller provides various clocks and reset
-outputs to the system.
-
-Required Properties:
-
-- compatible: Should be:
- - "mediatek,mt2701-hifsys", "syscon"
- - "mediatek,mt7622-hifsys", "syscon"
- - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon"
-- #clock-cells: Must be 1
-
-The hifsys controller uses the common clk binding from
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-
-Example:
-
-hifsys: clock-controller@1a000000 {
- compatible = "mediatek,mt2701-hifsys", "syscon";
- reg = <0 0x1a000000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-};
+++ /dev/null
-MediaTek PCIESYS controller
-============================
-
-The MediaTek PCIESYS controller provides various clocks to the system.
-
-Required Properties:
-
-- compatible: Should be:
- - "mediatek,mt7622-pciesys", "syscon"
- - "mediatek,mt7629-pciesys", "syscon"
-- #clock-cells: Must be 1
-- #reset-cells: Must be 1
-
-The PCIESYS controller uses the common clk binding from
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-
-Example:
-
-pciesys: pciesys@1a100800 {
- compatible = "mediatek,mt7622-pciesys", "syscon";
- reg = <0 0x1a100800 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-};
+++ /dev/null
-MediaTek SSUSBSYS controller
-============================
-
-The MediaTek SSUSBSYS controller provides various clocks to the system.
-
-Required Properties:
-
-- compatible: Should be:
- - "mediatek,mt7622-ssusbsys", "syscon"
- - "mediatek,mt7629-ssusbsys", "syscon"
-- #clock-cells: Must be 1
-- #reset-cells: Must be 1
-
-The SSUSBSYS controller uses the common clk binding from
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-
-Example:
-
-ssusbsys: ssusbsys@1a000000 {
- compatible = "mediatek,mt7622-ssusbsys", "syscon";
- reg = <0 0x1a000000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-};
+++ /dev/null
-SPM AVS Wrapper 2 (SAW2)
-
-The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
-Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
-power-controller that transitions a piece of hardware (like a processor or
-subsystem) into and out of low power modes via a direct connection to
-the PMIC. It can also be wired up to interact with other processors in the
-system, notifying them when a low power state is entered or exited.
-
-Multiple revisions of the SAW hardware are supported using these Device Nodes.
-SAW2 revisions differ in the register offset and configuration data. Also, the
-same revision of the SAW in different SoCs may have different configuration
-data due the differences in hardware capabilities. Hence the SoC name, the
-version of the SAW hardware in that SoC and the distinction between cpu (big
-or Little) or cache, may be needed to uniquely identify the SAW register
-configuration and initialization data. The compatible string is used to
-indicate this parameter.
-
-PROPERTIES
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: Must have
- "qcom,saw2"
- A more specific value could be one of:
- "qcom,apq8064-saw2-v1.1-cpu"
- "qcom,msm8226-saw2-v2.1-cpu"
- "qcom,msm8974-saw2-v2.1-cpu"
- "qcom,apq8084-saw2-v2.1-cpu"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: the first element specifies the base address and size of
- the register region. An optional second element specifies
- the base address and size of the alias register region.
-
-- regulator:
- Usage: optional
- Value type: boolean
- Definition: Indicates that this SPM device acts as a regulator device
- device for the core (CPU or Cache) the SPM is attached
- to.
-
-Example 1:
-
- power-controller@2099000 {
- compatible = "qcom,saw2";
- reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
- };
-
-Example 2:
- saw0: power-controller@f9089000 {
- compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
- reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
- };
minItems: 1
maxItems: 2
- qcom,dsb-element-size:
+ qcom,dsb-element-bits:
description:
Specifies the DSB(Discrete Single Bit) element size supported by
the monitor. The associated aggregator will read this size before it
is enabled. DSB element size currently only supports 32-bit and 64-bit.
- $ref: /schemas/types.yaml#/definitions/uint8
enum: [32, 64]
+ qcom,cmb-element-bits:
+ description:
+ Specifies the CMB(Continuous Multi-Bit) element size supported by
+ the monitor. The associated aggregator will read this size before it
+ is enabled. CMB element size currently only supports 8-bit, 32-bit
+ and 64-bit.
+ enum: [8, 32, 64]
+
qcom,dsb-msrs-num:
description:
Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)
minimum: 0
maximum: 32
+ qcom,cmb-msrs-num:
+ description:
+ Specifies the number of CMB MSR(mux select register) registers supported
+ by the monitor. If this property is not configured or set to 0, it means
+ this TPDM doesn't support CMB MSR.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 32
+
clocks:
maxItems: 1
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0684c000 0x1000>;
- qcom,dsb-element-size = /bits/ 8 <32>;
+ qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <16>;
clocks = <&aoss_qmp>;
};
};
+ tpdm@6c29000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x06c29000 0x1000>;
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_ipcc_out_funnel_center: endpoint {
+ remote-endpoint = <&funnel_center_in_tpdm_ipcc>;
+ };
+ };
+ };
+ };
...
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
- Some qcom based bootloaders identify the dtb blob based on a set of
- device properties like SoC and platform and revisions of those components.
- To support this scheme, we encode this information into the board compatible
- string.
-
- Each board must specify a top-level board compatible string with the following
- format:
-
- compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
-
- The 'SoC' and 'board' elements are required. All other elements are optional.
+ For devices using the Qualcomm SoC the "compatible" properties consists of
+ one or several "manufacturer,model" strings, describing the device itself,
+ followed by one or several "qcom,<SoC>" strings, describing the SoC used in
+ the device.
The 'SoC' element must be one of the following strings:
sm8650
x1e80100
- The 'board' element must be one of the following strings:
-
- adp
- cdp
- dragonboard
- idp
- liquid
- mtp
- qcp
- qrd
- rb2
- ride
- sbc
- x100
-
- The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
- where the minor number may be omitted when it's zero, i.e. v1.0 is the same
- as v1. If all versions of the 'board_version' elements match, then a
- wildcard '*' should be used, e.g. 'v*'.
-
- The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9.
-
- Examples:
-
- "qcom,msm8916-v1-cdp-pm8916-v2.1"
-
- A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version
- 2.1.
-
- "qcom,apq8074-v2.0-2-dragonboard/1-v0.1"
-
- A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
- foundry 2.
-
There are many devices in the list below that run the standard ChromeOS
bootloader setup and use the open source depthcharge bootloader to boot the
- OS. These devices do not use the scheme described above. For details, see:
+ OS. These devices use the bootflow explained at
https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html
properties:
- microsoft,superman-lte
- microsoft,tesla
- motorola,peregrine
+ - samsung,matisselte
- const: qcom,msm8926
- const: qcom,msm8226
- samsung,a5u-eur
- samsung,e5
- samsung,e7
+ - samsung,fortuna3g
+ - samsung,gprimeltecan
- samsung,grandmax
+ - samsung,grandprimelte
- samsung,gt510
- samsung,gt58
- samsung,j5
- samsung,j5x
+ - samsung,rossa
- samsung,serranove
- thwc,uf896
- thwc,ufi001c
- items:
- enum:
+ - xiaomi,curtana
- xiaomi,joyeuse
- const: qcom,sm7125
- items:
- enum:
+ - qcom,sm8550-hdk
- qcom,sm8550-mtp
- qcom,sm8550-qrd
- const: qcom,sm8550
- anbernic,rg351v
- const: rockchip,rk3326
- - description: Anbernic RG353P
+ - description: Anbernic RK3566 Handheld Gaming Console
items:
- - const: anbernic,rg353p
- - const: rockchip,rk3566
-
- - description: Anbernic RG353PS
- items:
- - const: anbernic,rg353ps
- - const: rockchip,rk3566
-
- - description: Anbernic RG353V
- items:
- - const: anbernic,rg353v
- - const: rockchip,rk3566
-
- - description: Anbernic RG353VS
- items:
- - const: anbernic,rg353vs
- - const: rockchip,rk3566
-
- - description: Anbernic RG503
- items:
- - const: anbernic,rg503
+ - enum:
+ - anbernic,rg353p
+ - anbernic,rg353ps
+ - anbernic,rg353v
+ - anbernic,rg353vs
+ - anbernic,rg503
+ - anbernic,rg-arc-d
+ - anbernic,rg-arc-s
- const: rockchip,rk3566
- description: Asus Tinker board
- friendlyarm,nanopi-r5s
- const: rockchip,rk3568
+ - description: FriendlyElec NanoPi R6 series boards
+ items:
+ - enum:
+ - friendlyarm,nanopi-r6c
+ - friendlyarm,nanopi-r6s
+ - const: rockchip,rk3588s
+
- description: FriendlyElec NanoPC T6
items:
- const: friendlyarm,nanopc-t6
- const: openailab,eaidk-610
- const: rockchip,rk3399
- - description: Orange Pi RK3399 board
+ - description: Xunlong Orange Pi RK3399 board
items:
- - const: rockchip,rk3399-orangepi
+ - const: xunlong,rk3399-orangepi
- const: rockchip,rk3399
- description: Phytec phyCORE-RK3288 Rapid Development Kit
- const: pine64,pinephone-pro
- const: rockchip,rk3399
+ - description: Pine64 PineTab2
+ items:
+ - enum:
+ - pine64,pinetab2-v0.1
+ - pine64,pinetab2-v2.0
+ - const: pine64,pinetab2
+ - const: rockchip,rk3566
+
- description: Pine64 Rock64
items:
- const: pine64,rock64
- description: Powkiddy RK3566 Handheld Gaming Console
items:
- enum:
+ - powkiddy,rgb10max3
- powkiddy,rgb30
- powkiddy,rk2023
- powkiddy,x55
- const: rockchip,rk3566
+ - description: QNAP TS-433-4G 4-Bay NAS
+ items:
+ - const: qnap,ts433
+ - const: rockchip,rk3568
+
- description: Radxa Compute Module 3(CM3)
items:
- enum:
- const: rockchip,rv1108-evb
- const: rockchip,rv1108
+ - description: Rockchip Toybrick TB-RK3588X board
+ items:
+ - const: rockchip,rk3588-toybrick-x0
+ - const: rockchip,rk3588
+
- description: Theobroma Systems PX30-uQ7 with Haikou baseboard
items:
- const: tsd,px30-ringneck-haikou
- const: tsd,rk3588-jaguar
- const: rockchip,rk3588
+ - description: Theobroma Systems RK3588-Q7 with Haikou baseboard
+ items:
+ - const: tsd,rk3588-tiger-haikou
+ - const: tsd,rk3588-tiger
+ - const: rockchip,rk3588
+
- description: Tronsmart Orion R68 Meta
items:
- const: tronsmart,orion-r68-meta
- const: rockchip,rk3568-evb1-v10
- const: rockchip,rk3568
- - description: Rockchip RK3568 Banana Pi R2 Pro
+ - description: Sinovoip RK3568 Banana Pi R2 Pro
items:
- - const: rockchip,rk3568-bpi-r2pro
+ - const: sinovoip,rk3568-bpi-r2pro
- const: rockchip,rk3568
- description: Sonoff iHost Smart Home Hub
- const: allwinner,r7-tv-dongle
- const: allwinner,sun5i-a10s
+ - description: Remix Mini PC
+ items:
+ - const: jide,remix-mini-pc
+ - const: allwinner,sun50i-h64
+ - const: allwinner,sun50i-a64
+
- description: RerVision H3-DVK
items:
- const: rervision,h3-dvk
- const: sinlinx,sina33
- const: allwinner,sun8i-a33
+ - description: Sipeed Longan Pi 3H board for the Sipeed Longan Module 3H
+ items:
+ - const: sipeed,longan-pi-3h
+ - const: sipeed,longan-module-3h
+ - const: allwinner,sun50i-h618
+
- description: SourceParts PopStick v1.1
items:
- const: sourceparts,popstick-v1.1
---------------------------------------------------------------
-Work in progress statement:
-
-Device tree files and bindings applying to Marvell Berlin SoCs and boards are
-considered "unstable". Any Marvell Berlin device tree binding may change at any
-time. Be sure to use a device tree binary and a kernel image generated from the
-same source tree.
-
-Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
-stable binding/ABI.
-
----------------------------------------------------------------
-
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:
- items:
- const: asus,tf700t
- const: nvidia,tegra30
+ - description: LG Optimus 4X P880
+ items:
+ - const: lg,p880
+ - const: nvidia,tegra30
+ - description: LG Optimus Vu P895
+ items:
+ - const: lg,p895
+ - const: nvidia,tegra30
- items:
- const: toradex,apalis_t30-eval
- const: toradex,apalis_t30
- const: pmc
- const: wake
- const: aotag
- - const: scratch
+ - enum: [ scratch, misc ]
- const: misc
interrupt-controller: true
description: If present, inverts the PMU interrupt signal.
$ref: /schemas/types.yaml#/definitions/flag
-if:
- properties:
- compatible:
- contains:
- const: nvidia,tegra186-pmc
-then:
- properties:
- reg:
- maxItems: 4
-
- reg-names:
- maxItems: 4
-else:
- properties:
- reg:
- minItems: 5
-
- reg-names:
- minItems: 5
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra186-pmc
+ then:
+ properties:
+ reg:
+ maxItems: 4
+ reg-names:
+ maxItems: 4
+ contains:
+ const: scratch
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra194-pmc
+ then:
+ properties:
+ reg:
+ minItems: 5
+ reg-names:
+ minItems: 5
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra234-pmc
+ then:
+ properties:
+ reg-names:
+ contains:
+ const: misc
patternProperties:
"^[a-z0-9]+-[a-z0-9]+$":
- const: tq,am642-tqma6442l
- const: ti,am642
+ - description: K3 AM642 SoC SolidRun SoM based boards
+ items:
+ - enum:
+ - solidrun,am642-hummingboard-t
+ - const: solidrun,am642-sr-som
+ - const: ti,am642
+
- description: K3 AM654 SoC
items:
- enum:
- siemens,iot2050-advanced
- siemens,iot2050-advanced-m2
- siemens,iot2050-advanced-pg2
+ - siemens,iot2050-advanced-sm
- siemens,iot2050-basic
- siemens,iot2050-basic-pg2
- ti,am654-evm
- ti,j721s2-evm
- const: ti,j721s2
+ - description: K3 J722S SoC and Boards
+ items:
+ - enum:
+ - ti,j722s-evm
+ - const: ti,j722s
+
- description: K3 J784s4 SoC
items:
- enum:
+++ /dev/null
-MediaTek Serial ATA controller
-
-Required properties:
- - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
- When using "mediatek,mtk-ahci" compatible strings, you
- need SoC specific ones in addition, one of:
- - "mediatek,mt7622-ahci"
- - reg : Physical base addresses and length of register sets.
- - interrupts : Interrupt associated with the SATA device.
- - interrupt-names : Associated name must be: "hostc".
- - clocks : A list of phandle and clock specifier pairs, one for each
- entry in clock-names.
- - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
- - phys : A phandle and PHY specifier pair for the PHY port.
- - phy-names : Associated name must be: "sata-phy".
- - ports-implemented : See ./ahci-platform.txt for details.
-
-Optional properties:
- - power-domains : A phandle and power domain specifier pair to the power
- domain which is responsible for collapsing and restoring
- power to the peripheral.
- - resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names : Associated names must be: "axi", "sw", "reg".
- - mediatek,phy-mode : A phandle to the system controller, used to enable
- SATA function.
-
-Example:
-
- sata: sata@1a200000 {
- compatible = "mediatek,mt7622-ahci",
- "mediatek,mtk-ahci";
- reg = <0 0x1a200000 0 0x1100>;
- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hostc";
- clocks = <&pciesys CLK_SATA_AHB_EN>,
- <&pciesys CLK_SATA_AXI_EN>,
- <&pciesys CLK_SATA_ASIC_EN>,
- <&pciesys CLK_SATA_RBC_EN>,
- <&pciesys CLK_SATA_PM_EN>;
- clock-names = "ahb", "axi", "asic", "rbc", "pm";
- phys = <&u3port1 PHY_TYPE_SATA>;
- phy-names = "sata-phy";
- ports-implemented = <0x1>;
- power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
- resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
- <&pciesys MT7622_SATA_PHY_SW_RST>,
- <&pciesys MT7622_SATA_PHY_REG_RST>;
- reset-names = "axi", "sw", "reg";
- mediatek,phy-mode = <&pciesys>;
- };
+++ /dev/null
-Atmel AT91RM9200 CompactFlash
-
-Required properties:
-- compatible : "atmel,at91rm9200-cf".
-- reg : should specify localbus address and size used.
-- gpios : specifies the gpio pins to control the CF device. Detect
- and reset gpio's are mandatory while irq and vcc gpio's are
- optional and may be set to 0 if not present.
-
-Example:
-compact-flash@50000000 {
- compatible = "atmel,at91rm9200-cf";
- reg = <0x50000000 0x30000000>;
- gpios = <&pioC 13 0 /* irq */
- &pioC 15 0 /* detect */
- 0 /* vcc */
- &pioC 5 0 /* reset */
- >;
-};
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/mediatek,mtk-ahci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Serial ATA controller
+
+maintainers:
+ - Ryder Lee <ryder.lee@mediatek.com>
+
+allOf:
+ - $ref: ahci-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt7622-ahci
+ - const: mediatek,mtk-ahci
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: hostc
+
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: axi
+ - const: asic
+ - const: rbc
+ - const: pm
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 3
+
+ reset-names:
+ items:
+ - const: axi
+ - const: sw
+ - const: reg
+
+ mediatek,phy-mode:
+ description: System controller phandle, used to enable SATA function
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+ - ports-implemented
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt7622-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/power/mt7622-power.h>
+ #include <dt-bindings/reset/mt7622-reset.h>
+
+ sata@1a200000 {
+ compatible = "mediatek,mt7622-ahci", "mediatek,mtk-ahci";
+ reg = <0x1a200000 0x1100>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ clocks = <&pciesys CLK_SATA_AHB_EN>,
+ <&pciesys CLK_SATA_AXI_EN>,
+ <&pciesys CLK_SATA_ASIC_EN>,
+ <&pciesys CLK_SATA_RBC_EN>,
+ <&pciesys CLK_SATA_PM_EN>;
+ clock-names = "ahb", "axi", "asic", "rbc", "pm";
+ phys = <&u3port1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi", "sw", "reg";
+ mediatek,phy-mode = <&pciesys>;
+ };
examples:
- |
lcd@10008000 {
- compatible = "arm,versatile-lcd";
- reg = <0x10008000 0x1000>;
+ compatible = "arm,versatile-lcd";
+ reg = <0x10008000 0x1000>;
};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/auxdisplay/gpio-7-segment.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GPIO based LED segment display
+
+maintainers:
+ - Chris Packham <chris.packham@alliedtelesis.co.nz>
+
+properties:
+ compatible:
+ const: gpio-7-segment
+
+ segment-gpios:
+ description: |
+ An array of GPIOs one per segment. The first GPIO corresponds to the A
+ segment, the seventh GPIO corresponds to the G segment. Some LED blocks
+ also have a decimal point which can be specified as an optional eighth
+ segment.
+
+ -a-
+ | |
+ f b
+ | |
+ -g-
+ | |
+ e c
+ | |
+ -d- dp
+
+ minItems: 7
+ maxItems: 8
+
+required:
+ - segment-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #include <dt-bindings/gpio/gpio.h>
+
+ led-7seg {
+ compatible = "gpio-7-segment";
+ segment-gpios = <&gpio 0 GPIO_ACTIVE_LOW>,
+ <&gpio 1 GPIO_ACTIVE_LOW>,
+ <&gpio 2 GPIO_ACTIVE_LOW>,
+ <&gpio 3 GPIO_ACTIVE_LOW>,
+ <&gpio 4 GPIO_ACTIVE_LOW>,
+ <&gpio 5 GPIO_ACTIVE_LOW>,
+ <&gpio 6 GPIO_ACTIVE_LOW>;
+ };
examples:
- |
#include <dt-bindings/gpio/gpio.h>
- auxdisplay {
- compatible = "hit,hd44780";
-
- data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>,
- <&hc595 1 GPIO_ACTIVE_HIGH>,
- <&hc595 2 GPIO_ACTIVE_HIGH>,
- <&hc595 3 GPIO_ACTIVE_HIGH>;
- enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
- rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
-
- display-height-chars = <2>;
- display-width-chars = <16>;
+ display-controller {
+ compatible = "hit,hd44780";
+
+ data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>,
+ <&hc595 1 GPIO_ACTIVE_HIGH>,
+ <&hc595 2 GPIO_ACTIVE_HIGH>,
+ <&hc595 3 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
+ rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
+
+ display-height-chars = <2>;
+ display-width-chars = <16>;
};
+
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
- #address-cells = <1>;
- #size-cells = <0>;
-
- pcf8574: pcf8574@27 {
- compatible = "nxp,pcf8574";
- reg = <0x27>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcf8574: gpio-expander@27 {
+ compatible = "nxp,pcf8574";
+ reg = <0x27>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
- hd44780 {
- compatible = "hit,hd44780";
- display-height-chars = <2>;
- display-width-chars = <16>;
- data-gpios = <&pcf8574 4 0>,
- <&pcf8574 5 0>,
- <&pcf8574 6 0>,
- <&pcf8574 7 0>;
- enable-gpios = <&pcf8574 2 0>;
- rs-gpios = <&pcf8574 0 0>;
- rw-gpios = <&pcf8574 1 0>;
- backlight-gpios = <&pcf8574 3 0>;
+
+ display-controller {
+ compatible = "hit,hd44780";
+ display-height-chars = <2>;
+ display-width-chars = <16>;
+ data-gpios = <&pcf8574 4 GPIO_ACTIVE_HIGH>,
+ <&pcf8574 5 GPIO_ACTIVE_HIGH>,
+ <&pcf8574 6 GPIO_ACTIVE_HIGH>,
+ <&pcf8574 7 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&pcf8574 2 GPIO_ACTIVE_HIGH>;
+ rs-gpios = <&pcf8574 0 GPIO_ACTIVE_HIGH>;
+ rw-gpios = <&pcf8574 1 GPIO_ACTIVE_HIGH>;
+ backlight-gpios = <&pcf8574 3 GPIO_ACTIVE_HIGH>;
};
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
i2c {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ht16k33: ht16k33@70 {
- compatible = "holtek,ht16k33";
- reg = <0x70>;
- refresh-rate-hz = <20>;
- interrupt-parent = <&gpio4>;
- interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
- debounce-delay-ms = <50>;
- linux,keymap = <MATRIX_KEY(2, 0, KEY_F6)>,
- <MATRIX_KEY(3, 0, KEY_F8)>,
- <MATRIX_KEY(4, 0, KEY_F10)>,
- <MATRIX_KEY(5, 0, KEY_F4)>,
- <MATRIX_KEY(6, 0, KEY_F2)>,
- <MATRIX_KEY(2, 1, KEY_F5)>,
- <MATRIX_KEY(3, 1, KEY_F7)>,
- <MATRIX_KEY(4, 1, KEY_F9)>,
- <MATRIX_KEY(5, 1, KEY_F3)>,
- <MATRIX_KEY(6, 1, KEY_F1)>;
-
- led {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_BACKLIGHT;
- linux,default-trigger = "backlight";
- };
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display-controller@70 {
+ compatible = "holtek,ht16k33";
+ reg = <0x70>;
+ refresh-rate-hz = <20>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
+ debounce-delay-ms = <50>;
+ linux,keymap = <MATRIX_KEY(2, 0, KEY_F6)>,
+ <MATRIX_KEY(3, 0, KEY_F8)>,
+ <MATRIX_KEY(4, 0, KEY_F10)>,
+ <MATRIX_KEY(5, 0, KEY_F4)>,
+ <MATRIX_KEY(6, 0, KEY_F2)>,
+ <MATRIX_KEY(2, 1, KEY_F5)>,
+ <MATRIX_KEY(3, 1, KEY_F7)>,
+ <MATRIX_KEY(4, 1, KEY_F9)>,
+ <MATRIX_KEY(5, 1, KEY_F3)>,
+ <MATRIX_KEY(6, 1, KEY_F1)>;
+
+ led {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_BACKLIGHT;
+ linux,default-trigger = "backlight";
};
- };
+ };
+ };
examples:
- |
lcd: lcd@17fff000 {
- compatible = "img,boston-lcd";
- reg = <0x17fff000 0x8>;
+ compatible = "img,boston-lcd";
+ reg = <0x17fff000 0x8>;
};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/auxdisplay/maxim,max6959.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MAX6958/6959 7-segment LED display controller
+
+maintainers:
+ - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+
+description:
+ The Maxim MAX6958/6959 7-segment LED display controller provides
+ an I2C interface to up to four 7-segment LED digits. The MAX6959,
+ in comparison to MAX6958, adds input support. Type of the chip can
+ be autodetected via specific register read, and hence the features
+ may be enabled in the driver at run-time, in case they are requested
+ via Device Tree. A given hardware is simple and does not provide
+ any additional pins, such as reset or power enable.
+
+properties:
+ compatible:
+ const: maxim,max6959
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display-controller@38 {
+ compatible = "maxim,max6959";
+ reg = <0x38>;
+ };
+ };
- const: brcm,gisb-arb
- items:
- enum:
+ - brcm,bcm74165-gisb-arb # for V7 new style 16nm chips
- brcm,bcm7278-gisb-arb # for V7 28nm chips
- brcm,bcm7435-gisb-arb # for newer 40nm chips
- brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips
+++ /dev/null
-Device tree bindings for i.MX Wireless External Interface Module (WEIM)
-
-The term "wireless" does not imply that the WEIM is literally an interface
-without wires. It simply means that this module was originally designed for
-wireless and mobile applications that use low-power technology.
-
-The actual devices are instantiated from the child nodes of a WEIM node.
-
-Required properties:
-
- - compatible: Should contain one of the following:
- "fsl,imx1-weim"
- "fsl,imx27-weim"
- "fsl,imx51-weim"
- "fsl,imx50-weim"
- "fsl,imx6q-weim"
- - reg: A resource specifier for the register space
- (see the example below)
- - clocks: the clock, see the example below.
- - #address-cells: Must be set to 2 to allow memory address translation
- - #size-cells: Must be set to 1 to allow CS address passing
- - ranges: Must be set up to reflect the memory layout with four
- integer values for each chip-select line in use:
-
- <cs-number> 0 <physical address of mapping> <size>
-
-Optional properties:
-
- - fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
- devices, it should be the phandle to the system General
- Purpose Register controller that contains WEIM CS GPR
- register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
- should be set up as one of the following 4 possible
- values depending on the CS space configuration.
-
- IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
- ---------------------------------------------
- 05 128M 0M 0M 0M
- 033 64M 64M 0M 0M
- 0113 64M 32M 32M 0M
- 01111 32M 32M 32M 32M
-
- In case that the property is absent, the reset value or
- what bootloader sets up in IOMUXC_GPR1[11:0] will be
- used.
-
- - fsl,burst-clk-enable For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
- devices, the presence of this property indicates that
- the weim bus should operate in Burst Clock Mode.
-
- - fsl,continuous-burst-clk Make Burst Clock to output continuous clock.
- Without this option Burst Clock will output clock
- only when necessary. This takes effect only if
- "fsl,burst-clk-enable" is set.
-
-Timing property for child nodes. It is mandatory, not optional.
-
- - fsl,weim-cs-timing: The timing array, contains timing values for the
- child node. We get the CS indexes from the address
- ranges in the child node's "reg" property.
- The number of registers depends on the selected chip:
- For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
- registers: CSxU, CSxL.
- For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
- there are three registers: CSCRxU, CSCRxL, CSCRxA.
- For i.MX50, i.MX53 ("fsl,imx50-weim"),
- i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim")
- there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,
- CSxRCR2, CSxWCR1, CSxWCR2.
-
-Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
-
- weim: weim@21b8000 {
- compatible = "fsl,imx6q-weim";
- reg = <0x021b8000 0x4000>;
- clocks = <&clks 196>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0x08000000 0x08000000>;
- fsl,weim-cs-gpr = <&gpr>;
-
- nor@0,0 {
- compatible = "cfi-flash";
- reg = <0 0 0x02000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- bank-width = <2>;
- fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
- 0x0000c000 0x1404a38e 0x00000000>;
- };
- };
-
-Example for an imx6q-based board, a multi-chipselect device connected to WEIM:
-
-In this case, both chip select 0 and 1 will be configured with the same timing
-array values.
-
- weim: weim@21b8000 {
- compatible = "fsl,imx6q-weim";
- reg = <0x021b8000 0x4000>;
- clocks = <&clks 196>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0x08000000 0x02000000
- 1 0 0x0a000000 0x02000000
- 2 0 0x0c000000 0x02000000
- 3 0 0x0e000000 0x02000000>;
- fsl,weim-cs-gpr = <&gpr>;
-
- acme@0 {
- compatible = "acme,whatever";
- reg = <0 0 0x100>, <0 0x400000 0x800>,
- <1 0x400000 0x800>;
- fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
- 0x00000000 0xa0000240 0x00000000>;
- };
- };
- google,gs101-cmu-top
- google,gs101-cmu-apm
- google,gs101-cmu-misc
+ - google,gs101-cmu-peric0
+ - google,gs101-cmu-peric1
clocks:
minItems: 1
- maxItems: 2
+ maxItems: 3
clock-names:
minItems: 1
- maxItems: 2
+ maxItems: 3
"#clock-cells":
const: 1
- const: bus
- const: sss
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - google,gs101-cmu-peric0
+ - google,gs101-cmu-peric1
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24.576 MHz)
+ - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
+ - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: bus
+ - const: ip
+
additionalProperties: false
examples:
-Status: Unstable - ABI compatibility may be broken in the future
-
Binding for Keystone gate control driver which uses PSC controller IP.
This binding uses the common clock binding[1].
-Status: Unstable - ABI compatibility may be broken in the future
-
Binding for keystone PLLs. The main PLL IP typically has a multiplier,
a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
and PAPLL are controlled by the memory mapped register where as the Main
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt2701-hifsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek HIFSYS clock and reset controller
+
+description:
+ The MediaTek HIFSYS controller provides various clocks and reset outputs to
+ the system.
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt2701-hifsys
+ - mediatek,mt7622-hifsys
+ - items:
+ - enum:
+ - mediatek,mt7623-hifsys
+ - const: mediatek,mt2701-hifsys
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+ description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - reg
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@1a000000 {
+ compatible = "mediatek,mt2701-hifsys";
+ reg = <0x1a000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek PCIESYS clock and reset controller
+
+description:
+ The MediaTek PCIESYS controller provides various clocks to the system.
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt7622-pciesys
+ - mediatek,mt7629-pciesys
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+ description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@1a100800 {
+ compatible = "mediatek,mt7622-pciesys";
+ reg = <0x1a100800 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7622-ssusbsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek SSUSBSYS clock and reset controller
+
+description:
+ The MediaTek SSUSBSYS controller provides various clocks to the system.
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt7622-ssusbsys
+ - mediatek,mt7629-ssusbsys
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+ description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@1a000000 {
+ compatible = "mediatek,mt7622-ssusbsys";
+ reg = <0x1a000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobileye EyeQ5 clock controller
+
+description:
+ The EyeQ5 clock controller handles 10 read-only PLLs derived from the main
+ crystal clock. It also exposes one divider clock, a child of one of the PLLs.
+ Its registers live in a shared region called OLB.
+
+maintainers:
+ - Grégory Clement <gregory.clement@bootlin.com>
+ - Théo Lebrun <theo.lebrun@bootlin.com>
+ - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
+
+properties:
+ compatible:
+ const: mobileye,eyeq5-clk
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: plls
+ - const: ospi
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+ description:
+ Input parent clock to all PLLs. Expected to be the main crystal.
+
+ clock-names:
+ items:
+ - const: ref
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#clock-cells"
+ - clocks
+ - clock-names
+
+additionalProperties: false
- const: bi_tcxo_ao
- const: sleep_clk
+ power-domains:
+ items:
+ - description: CX domain
+
required:
- compatible
- clocks
- clock-names
+ - power-domains
allOf:
- $ref: qcom,gcc.yaml#
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sc8180x";
reg = <0x00100000 0x1f0000>;
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+ power-domains = <&rpmhpd SC8180X_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains:
maxItems: 1
+ vdd-gfx-supply:
+ description: Regulator supply for the VDD_GFX pads
+
'#clock-cells':
const: 1
- '#reset-cells'
- '#power-domain-cells'
+# Require that power-domains and vdd-gfx-supply are not both present
+not:
+ required:
+ - power-domains
+ - vdd-gfx-supply
+
additionalProperties: false
examples:
title: Q6SSTOP clock Controller
maintainers:
- - Govind Singh <govinds@codeaurora.org>
+ - Bjorn Andersson <andersson@kernel.org>
properties:
compatible:
+++ /dev/null
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Modem Clock Controller on SC7180
-
-maintainers:
- - Taniya Das <quic_tdas@quicinc.com>
-
-description: |
- Qualcomm modem clock control module provides the clocks on SC7180.
-
- See also:: include/dt-bindings/clock/qcom,mss-sc7180.h
-
-properties:
- compatible:
- const: qcom,sc7180-mss
-
- clocks:
- items:
- - description: gcc_mss_mfab_axi clock from GCC
- - description: gcc_mss_nav_axi clock from GCC
- - description: gcc_mss_cfg_ahb clock from GCC
-
- clock-names:
- items:
- - const: gcc_mss_mfab_axis
- - const: gcc_mss_nav_axi
- - const: cfg_ahb
-
- '#clock-cells':
- const: 1
-
- reg:
- maxItems: 1
-
-required:
- - compatible
- - reg
- - clocks
- - '#clock-cells'
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,gcc-sc7180.h>
- clock-controller@41a8000 {
- compatible = "qcom,sc7180-mss";
- reg = <0x041a8000 0x8000>;
- clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>,
- <&gcc GCC_MSS_NAV_AXI_CLK>,
- <&gcc GCC_MSS_CFG_AHB_CLK>;
- clock-names = "gcc_mss_mfab_axis",
- "gcc_mss_nav_axi",
- "cfg_ahb";
- #clock-cells = <1>;
- };
-...
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
+ include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
- $ref: qcom,gcc.yaml#
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
+ - qcom,x1e80100-camcc
clocks:
items:
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
include/dt-bindings/reset/qcom,sm8650-gpucc.h
+ include/dt-bindings/reset/qcom,x1e80100-gpucc.h
properties:
compatible:
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc
+ - qcom,x1e80100-gpucc
clocks:
items:
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8550.
- See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
+ See also:
+ - include/dt-bindings/clock/qcom,sm8550-dispcc.h
+ - include/dt-bindings/clock/qcom,sm8650-dispcc.h
+ - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
properties:
compatible:
enum:
- qcom,sm8550-dispcc
+ - qcom,sm8650-dispcc
+ - qcom,x1e80100-dispcc
clocks:
items:
- enum:
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
+ - qcom,x1e80100-tcsr
- const: syscon
clocks:
+++ /dev/null
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display Clock & Reset Controller for SM8650
-
-maintainers:
- - Bjorn Andersson <andersson@kernel.org>
- - Neil Armstrong <neil.armstrong@linaro.org>
-
-description: |
- Qualcomm display clock control module provides the clocks, resets and power
- domains on SM8650.
-
- See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
-
-properties:
- compatible:
- enum:
- - qcom,sm8650-dispcc
-
- clocks:
- items:
- - description: Board XO source
- - description: Board Always On XO source
- - description: Display's AHB clock
- - description: sleep clock
- - description: Byte clock from DSI PHY0
- - description: Pixel clock from DSI PHY0
- - description: Byte clock from DSI PHY1
- - description: Pixel clock from DSI PHY1
- - description: Link clock from DP PHY0
- - description: VCO DIV clock from DP PHY0
- - description: Link clock from DP PHY1
- - description: VCO DIV clock from DP PHY1
- - description: Link clock from DP PHY2
- - description: VCO DIV clock from DP PHY2
- - description: Link clock from DP PHY3
- - description: VCO DIV clock from DP PHY3
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- power-domains:
- description:
- A phandle and PM domain specifier for the MMCX power domain.
- maxItems: 1
-
- required-opps:
- description:
- A phandle to an OPP node describing required MMCX performance point.
- maxItems: 1
-
-required:
- - compatible
- - reg
- - clocks
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,sm8650-gcc.h>
- #include <dt-bindings/clock/qcom,rpmh.h>
- #include <dt-bindings/power/qcom-rpmpd.h>
- #include <dt-bindings/power/qcom,rpmhpd.h>
- clock-controller@af00000 {
- compatible = "qcom,sm8650-dispcc";
- reg = <0x0af00000 0x10000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&rpmhcc RPMH_CXO_CLK_A>,
- <&gcc GCC_DISP_AHB_CLK>,
- <&sleep_clk>,
- <&dsi0_phy 0>,
- <&dsi0_phy 1>,
- <&dsi1_phy 0>,
- <&dsi1_phy 1>,
- <&dp0_phy 0>,
- <&dp0_phy 1>,
- <&dp1_phy 0>,
- <&dp1_phy 1>,
- <&dp2_phy 0>,
- <&dp2_phy 1>,
- <&dp3_phy 0>,
- <&dp3_phy 1>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- power-domains = <&rpmhpd RPMHPD_MMCX>;
- required-opps = <&rpmhpd_opp_low_svs>;
- };
-...
- renesas,r8a779a0-cpg-mssr # R-Car V3U
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
- renesas,r8a779g0-cpg-mssr # R-Car V4H
+ - renesas,r8a779h0-cpg-mssr # R-Car V4M
reg:
maxItems: 1
- samsung,exynos850-cmu-aud
- samsung,exynos850-cmu-cmgp
- samsung,exynos850-cmu-core
+ - samsung,exynos850-cmu-cpucl0
+ - samsung,exynos850-cmu-cpucl1
- samsung,exynos850-cmu-dpu
- samsung,exynos850-cmu-g3d
- samsung,exynos850-cmu-hsi
- const: dout_core_mmc_embd
- const: dout_core_sss
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-cpucl0
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CPUCL0 switch clock (from CMU_TOP)
+ - description: CPUCL0 debug clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cpucl0_switch
+ - const: dout_cpucl0_dbg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-cpucl1
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CPUCL1 switch clock (from CMU_TOP)
+ - description: CPUCL1 debug clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cpucl1_switch
+ - const: dout_cpucl1_dbg
+
- if:
properties:
compatible:
description: |
FSD clock controller consist of several clock management unit
- (CMU), which generates clocks for various inteernal SoC blocks.
+ (CMU), which generates clocks for various internal SoC blocks.
The root clock comes from external OSC clock (24 MHz).
All available clocks are defined as preprocessor macros in
Binding for Texas Instruments ADPLL clock.
-Binding status: Unstable - ABI compatibility may be broken in the future
-
This binding uses the common clock binding[1]. It assumes a
register-mapped ADPLL with two to three selectable input clocks
and three to four children.
Binding for Texas Instruments APLL clock.
-Binding status: Unstable - ABI compatibility may be broken in the future
-
This binding uses the common clock binding[1]. It assumes a
register-mapped APLL with usually two selectable input clocks
(reference clock and bypass clock), with analog phase locked
Binding for Texas Instruments autoidle clock.
-Binding status: Unstable - ABI compatibility may be broken in the future
-
This binding uses the common clock binding[1]. It assumes a register mapped
clock which can be put to idle automatically by hardware based on the usage
and a configuration bit setting. Autoidle clock is never an individual
Binding for Texas Instruments clockdomain.
-Binding status: Unstable - ABI compatibility may be broken in the future
-
This binding uses the common clock binding[1] in consumer role.
Every clock on TI SoC belongs to one clockdomain, but software
only needs this information for specific clocks which require
Binding for TI composite clock.
-Binding status: Unstable - ABI compatibility may be broken in the future
-
This binding uses the common clock binding[1]. It assumes a
register-mapped composite clock with multiple different sub-types;
Binding for TI divider clock
-Binding status: Unstable - ABI compatibility may be broken in the future
-
This binding uses the common clock binding[1]. It assumes a
register-mapped adjustable clock rate divider that does not gate and has
only one input clock or parent. By default the value programmed into
Binding for Texas Instruments DPLL clock.
-Binding status: Unstable - ABI compatibility may be broken in the future
-
This binding uses the common clock binding[1]. It assumes a
register-mapped DPLL with usually two selectable input clocks
(reference clock and bypass clock), with digital phase locked
Binding for Texas Instruments FAPLL clock.
-Binding status: Unstable - ABI compatibility may be broken in the future
-
This binding uses the common clock binding[1]. It assumes a
register-mapped FAPLL with usually two selectable input clocks
(reference clock and bypass clock), and one or more child
Binding for TI fixed factor rate clock sources.
-Binding status: Unstable - ABI compatibility may be broken in the future
-
This binding uses the common clock binding[1], and also uses the autoidle
support from TI autoidle clock [2].
Binding for Texas Instruments gate clock.
-Binding status: Unstable - ABI compatibility may be broken in the future
-
This binding uses the common clock binding[1]. This clock is
quite much similar to the basic gate-clock [2], however,
it supports a number of additional features. If no register
Binding for Texas Instruments interface clock.
-Binding status: Unstable - ABI compatibility may be broken in the future
-
This binding uses the common clock binding[1]. This clock is
quite much similar to the basic gate-clock [2], however,
it supports a number of additional features, including
Binding for TI mux clock.
-Binding status: Unstable - ABI compatibility may be broken in the future
-
This binding uses the common clock binding[1]. It assumes a
register-mapped multiplexer with multiple input clock signals or
parents, one of which can be selected as output. This clock does not
properties:
compatible:
- const: atmel,at91sam9g46-aes
+ oneOf:
+ - const: atmel,at91sam9g46-aes
+ - items:
+ - const: microchip,sam9x7-aes
+ - const: atmel,at91sam9g46-aes
reg:
maxItems: 1
properties:
compatible:
- const: atmel,at91sam9g46-sha
+ oneOf:
+ - const: atmel,at91sam9g46-sha
+ - items:
+ - const: microchip,sam9x7-sha
+ - const: atmel,at91sam9g46-sha
reg:
maxItems: 1
properties:
compatible:
- const: atmel,at91sam9g46-tdes
+ oneOf:
+ - const: atmel,at91sam9g46-tdes
+ - items:
+ - const: microchip,sam9x7-tdes
+ - const: atmel,at91sam9g46-tdes
reg:
maxItems: 1
items:
- enum:
- qcom,sa8775p-inline-crypto-engine
+ - qcom,sc7180-inline-crypto-engine
- qcom,sm8450-inline-crypto-engine
- qcom,sm8550-inline-crypto-engine
- qcom,sm8650-inline-crypto-engine
- items:
- enum:
- qcom,sc7280-qce
+ - qcom,sm6350-qce
- qcom,sm8250-qce
- qcom,sm8350-qce
- qcom,sm8450-qce
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/atmel/atmel,hlcdc-display-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel's High LCD Controller (HLCDC)
+
+maintainers:
+ - Nicolas Ferre <nicolas.ferre@microchip.com>
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+ - Claudiu Beznea <claudiu.beznea@tuxon.dev>
+
+description:
+ The LCD Controller (LCDC) consists of logic for transferring LCD image
+ data from an external display buffer to a TFT LCD panel. The LCDC has one
+ display input buffer per layer that fetches pixels through the single bus
+ host interface and a look-up table to allow palletized display
+ configurations.
+
+properties:
+ compatible:
+ const: atmel,hlcdc-display-controller
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Output endpoint of the controller, connecting the LCD panel signals.
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ reg:
+ maxItems: 1
+
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+ description:
+ Endpoint connecting the LCD panel signals.
+
+ properties:
+ bus-width:
+ enum: [ 12, 16, 18, 24 ]
+
+required:
+ - '#address-cells'
+ - '#size-cells'
+ - compatible
+ - port@0
+
+additionalProperties: false
+++ /dev/null
-Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver
-
-The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device.
-See ../../mfd/atmel-hlcdc.txt for more details.
-
-Required properties:
- - compatible: value should be "atmel,hlcdc-display-controller"
- - pinctrl-names: the pin control state names. Should contain "default".
- - pinctrl-0: should contain the default pinctrl states.
- - #address-cells: should be set to 1.
- - #size-cells: should be set to 0.
-
-Required children nodes:
- Children nodes are encoding available output ports and their connections
- to external devices using the OF graph representation (see ../graph.txt).
- At least one port node is required.
-
-Optional properties in grandchild nodes:
- Any endpoint grandchild node may specify a desired video interface
- according to ../../media/video-interfaces.txt, specifically
- - bus-width: recognized values are <12>, <16>, <18> and <24>, and
- override any output mode selection heuristic, forcing "rgb444",
- "rgb565", "rgb666" and "rgb888" respectively.
-
-Example:
-
- hlcdc: hlcdc@f0030000 {
- compatible = "atmel,sama5d3-hlcdc";
- reg = <0xf0030000 0x2000>;
- interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
- clock-names = "periph_clk","sys_clk", "slow_clk";
-
- hlcdc-display-controller {
- compatible = "atmel,hlcdc-display-controller";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- hlcdc_panel_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&panel_input>;
- };
- };
- };
-
- hlcdc_pwm: hlcdc-pwm {
- compatible = "atmel,hlcdc-pwm";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcd_pwm>;
- #pwm-cells = <3>;
- };
- };
-
-Example 2: With a video interface override to force rgb565; as above
-but with these changes/additions:
-
- &hlcdc {
- hlcdc-display-controller {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>;
-
- port@0 {
- hlcdc_panel_output: endpoint@0 {
- bus-width = <16>;
- };
- };
- };
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8MP DWC HDMI TX Encoder
+
+maintainers:
+ - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+ The i.MX8MP HDMI transmitter is a Synopsys DesignWare
+ HDMI 2.0a TX controller IP.
+
+allOf:
+ - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml#
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8mp-hdmi-tx
+
+ reg-io-width:
+ const: 1
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: iahb
+ - const: isfr
+ - const: cec
+ - const: pix
+
+ power-domains:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Parallel RGB input port
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: HDMI output port
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - power-domains
+ - ports
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mp-clock.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/imx8mp-power.h>
+
+ hdmi@32fd8000 {
+ compatible = "fsl,imx8mp-hdmi-tx";
+ reg = <0x32fd8000 0x7eff>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+ <&clk IMX8MP_CLK_HDMI_REF_266M>,
+ <&clk IMX8MP_CLK_32K>,
+ <&hdmi_tx_phy>;
+ clock-names = "iahb", "isfr", "cec", "pix";
+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
+ reg-io-width = <1>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+
+ hdmi_tx_from_pvi: endpoint {
+ remote-endpoint = <&pvi_to_hdmi_tx>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ };
+ };
title: SN65DSI86 DSI to eDP bridge chip
maintainers:
- - Sandeep Panda <spanda@codeaurora.org>
+ - Douglas Anderson <dianders@chromium.org>
description: |
The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
maxItems: 1
clock-names:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ const: fsl,imx6sx-lcdif
+ then:
+ required:
+ - power-domains
- if:
properties:
compatible:
contains:
enum:
- fsl,imx6sl-lcdif
- - fsl,imx6sx-lcdif
- fsl,imx8mm-lcdif
- fsl,imx8mn-lcdif
- fsl,imx8mp-lcdif
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8MP HDMI Parallel Video Interface
+
+maintainers:
+ - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+ The HDMI parallel video interface is a timing and sync generator block in the
+ i.MX8MP SoC, that sits between the video source and the HDMI TX controller.
+
+properties:
+ compatible:
+ const: fsl,imx8mp-hdmi-pvi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Input from the LCDIF controller.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output to the HDMI TX controller.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/imx8mp-power.h>
+
+ display-bridge@32fc4000 {
+ compatible = "fsl,imx8mp-hdmi-pvi";
+ reg = <0x32fc4000 0x44>;
+ interrupt-parent = <&irqsteer_hdmi>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ pvi_from_lcdif3: endpoint {
+ remote-endpoint = <&lcdif3_to_pvi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ pvi_to_hdmi_tx: endpoint {
+ remote-endpoint = <&hdmi_tx_from_pvi>;
+ };
+ };
+ };
+ };
- qcom,msm8916-dsi-ctrl
- qcom,msm8953-dsi-ctrl
- qcom,msm8974-dsi-ctrl
+ - qcom,msm8976-dsi-ctrl
- qcom,msm8996-dsi-ctrl
- qcom,msm8998-dsi-ctrl
- qcom,qcm2290-dsi-ctrl
contains:
enum:
- qcom,msm8953-dsi-ctrl
+ - qcom,msm8976-dsi-ctrl
then:
properties:
clocks:
enum:
- qcom,adreno-gmu-730.1
- qcom,adreno-gmu-740.1
+ - qcom,adreno-gmu-750.1
then:
properties:
reg:
The driver is parsing the compat string for Adreno to
figure out the gpu-id and patch level.
items:
- - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$'
+ - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$'
- const: qcom,adreno
- description: |
The driver is parsing the compat string for Imageon to
properties:
compatible:
contains:
- pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
+ pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$'
then:
properties:
properties:
compatible:
contains:
- pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$'
+ pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$'
then: # Starting with A6xx, the clocks are usually defined in the GMU node
properties:
- qcom,dsi-phy-20nm
- qcom,dsi-phy-28nm-8226
- qcom,dsi-phy-28nm-hpm
+ - qcom,dsi-phy-28nm-hpm-fam-b
- qcom,dsi-phy-28nm-lp
- qcom,hdmi-phy-8084
- qcom,hdmi-phy-8660
compatible:
const: qcom,sm8150-dpu
+ "^displayport-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ contains:
+ const: qcom,sm8150-dp
+
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
- const: qcom,sm8650-dpu
+ enum:
+ - qcom,sm8650-dpu
+ - qcom,x1e80100-dpu
reg:
items:
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
+ additionalProperties: true
properties:
compatible:
const: qcom,sm8650-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
+ additionalProperties: true
properties:
compatible:
const: qcom,sm8650-dp
"^dsi@[0-9a-f]+$":
type: object
+ additionalProperties: true
properties:
compatible:
items:
"^phy@[0-9a-f]+$":
type: object
+ additionalProperties: true
properties:
compatible:
const: qcom,sm8650-dsi-phy-4nm
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm X1E80100 Display MDSS
+
+maintainers:
+ - Abel Vesa <abel.vesa@linaro.org>
+
+description:
+ X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
+ DPU display controller, DP interfaces, etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,x1e80100-mdss
+
+ clocks:
+ items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 3
+
+ interconnect-names:
+ maxItems: 3
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,x1e80100-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,x1e80100-dp
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,x1e80100-dp-phy
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
+ #include <dt-bindings/phy/phy-qcom-qmp.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,x1e80100-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
+ <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg";
+
+ resets = <&dispcc_core_bcr>;
+
+ power-domains = <&dispcc_gdsc>;
+
+ clocks = <&dispcc_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>,
+ <&dispcc_mdp_clk>;
+ clock-names = "bus", "nrt_bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1c00 0x2>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,x1e80100-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc_axi_clk>,
+ <&dispcc_ahb_clk>,
+ <&dispcc_mdp_lut_clk>,
+ <&dispcc_mdp_clk>,
+ <&dispcc_mdp_vsync_clk>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc_mdp_vsync_clk>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-514000000 {
+ opp-hz = /bits/ 64 <514000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ displayport-controller@ae90000 {
+ compatible = "qcom,x1e80100-dp";
+ reg = <0 0xae90000 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0x600>,
+ <0 0xae91000 0 0x400>,
+ <0 0xae91400 0 0x400>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+
+ clocks = <&dispcc_mdss_ahb_clk>,
+ <&dispcc_dptx0_aux_clk>,
+ <&dispcc_dptx0_link_clk>,
+ <&dispcc_dptx0_link_intf_clk>,
+ <&dispcc_dptx0_pixel0_clk>;
+ clock-names = "core_iface", "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
+ <&dispcc_mdss_dptx0_pixel0_clk_src>;
+ assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ operating-points-v2 = <&mdss_dp0_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp0_in: endpoint {
+ remote-endpoint = <&mdss_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp0_out: endpoint {
+ };
+ };
+ };
+
+ mdss_dp0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/boe,th101mb31ig002-28a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: BOE TH101MB31IG002-28A WXGA DSI Display Panel
+
+maintainers:
+ - Manuel Traut <manut@mecka.net>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ # BOE TH101MB31IG002-28A 10.1" WXGA TFT LCD panel
+ - boe,th101mb31ig002-28a
+
+ reg: true
+ backlight: true
+ enable-gpios: true
+ power-supply: true
+ port: true
+ rotation: true
+
+required:
+ - compatible
+ - reg
+ - enable-gpios
+ - power-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "boe,th101mb31ig002-28a";
+ reg = <0>;
+ backlight = <&backlight_lcd0>;
+ enable-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
+ rotation = <90>;
+ power-supply = <&vcc_3v3>;
+ port {
+ panel_in_dsi: endpoint {
+ remote-endpoint = <&dsi_out_con>;
+ };
+ };
+ };
+ };
+
+...
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/himax,hx83112a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Himax HX83112A-based DSI display panels
+
+maintainers:
+ - Luca Weiss <luca.weiss@fairphone.com>
+
+description:
+ The Himax HX83112A is a generic DSI Panel IC used to control
+ LCD panels.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ contains:
+ const: djn,9a-3r063-1102b
+
+ vdd1-supply:
+ description: Digital voltage rail
+
+ vsn-supply:
+ description: Positive source voltage rail
+
+ vsp-supply:
+ description: Negative source voltage rail
+
+ reg: true
+ port: true
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - vdd1-supply
+ - vsn-supply
+ - vsp-supply
+ - port
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "djn,9a-3r063-1102b";
+ reg = <0>;
+
+ backlight = <&pm6150l_wled>;
+ reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>;
+
+ vdd1-supply = <&vreg_l1e>;
+ vsn-supply = <&pm6150l_lcdb_ncp>;
+ vsp-supply = <&pm6150l_lcdb_ldo>;
+
+ port {
+ panel_in_0: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ };
+
+...
properties:
compatible:
- const: leadtek,ltk500hd1829
+ enum:
+ - leadtek,ltk101b4029w
+ - leadtek,ltk500hd1829
reg: true
backlight: true
reset-gpios: true
properties:
compatible:
items:
- - const: hydis,hva40wv1
+ - enum:
+ - frida,frd400b25025
+ - hydis,hva40wv1
- const: novatek,nt35510
description: This indicates the panel manufacturer of the panel
that is in turn using the NT35510 panel driver. The compatible
vddi-supply:
description: regulator that supplies the vddi voltage
backlight: true
+ port: true
required:
- compatible
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/novatek,nt36672e.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Novatek NT36672E LCD DSI Panel
+
+maintainers:
+ - Ritesh Kumar <quic_riteshk@quicinc.com>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ const: novatek,nt36672e
+
+ reg:
+ maxItems: 1
+ description: DSI virtual channel
+
+ vddi-supply: true
+ avdd-supply: true
+ avee-supply: true
+ port: true
+ reset-gpios: true
+ backlight: true
+
+required:
+ - compatible
+ - reg
+ - vddi-supply
+ - avdd-supply
+ - avee-supply
+ - reset-gpios
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "novatek,nt36672e";
+ reg = <0>;
+
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
+
+ vddi-supply = <&vreg_l8c_1p8>;
+ avdd-supply = <&disp_avdd>;
+ avee-supply = <&disp_avee>;
+
+ backlight = <&pwm_backlight>;
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ };
+...
compatible:
items:
- enum:
+ # Admatec 9904379 10.1" 1024x600 LVDS panel
+ - admatec,9904379
- auo,b101ew05
# Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel
- chunghwa,claa070wp03xg
+ # EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel
+ - edt,etml0700z9ndha
# HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel
- hannstar,hsd101pww2
# Hydis Technologies 7" WXGA (800x1280) TFT LCD LVDS panel
- auo,t215hvn01
# Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel
- avic,tm070ddh03
+ # BOE BP082WX1-100 8.2" WXGA (1280x800) LVDS panel
+ - boe,bp082wx1-100
# BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel
- boe,bp101wx1-100
# BOE EV121WXM-N10-1850 12.1" WXGA (1280x800) TFT LCD panel
- edt,etm0700g0edh6
# Emerging Display Technology Corp. LVDS WSVGA TFT Display with capacitive touch
- edt,etml0700y5dha
+ # Emerging Display Technology Corp. 10.1" LVDS WXGA TFT Display with capacitive touch
+ - edt,etml1010g3dra
# Emerging Display Technology Corp. 5.7" VGA TFT LCD panel with
# capacitive touch
- edt,etmv570g2dhu
enum:
# Anberic RG353V-V2 5.0" 640x480 TFT LCD panel
- anbernic,rg353v-panel-v2
+ # Powkiddy RGB10MAX3 5.0" 720x1280 TFT LCD panel
+ - powkiddy,rgb10max3-panel
# Powkiddy RGB30 3.0" 720x720 TFT LCD panel
- powkiddy,rgb30-panel
# Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel
reset-gpios: true
backlight: true
+ rotation: true
required:
- compatible
-# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/visionox,r66451.yaml#
title: Visionox model RM69299 Panels
maintainers:
- - Harigovindan P <harigovi@codeaurora.org>
+ - Abhinav Kumar <quic_abhinavk@quicinc.com>
+ - Jessica Zhang <quic_jesszhan@quicinc.com>
description: |
This binding is for display panels using a Visionox RM692999 panel.
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L Display Unit (DU)
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description: |
+ These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
+ and RZ/V2L SoCs.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - renesas,r9a07g044-du # RZ/G2{L,LC}
+ - items:
+ - enum:
+ - renesas,r9a07g054-du # RZ/V2L
+ - const: renesas,r9a07g044-du # RZ/G2L fallback
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main clock
+ - description: Register access clock
+ - description: Video clock
+
+ clock-names:
+ items:
+ - const: aclk
+ - const: pclk
+ - const: vclk
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: |
+ The connections to the DU output video ports are modeled using the OF
+ graph bindings. The number of ports and their assignment are
+ model-dependent. Each port shall have a single endpoint.
+
+ patternProperties:
+ "^port@[0-1]$":
+ $ref: /schemas/graph.yaml#/properties/port
+ unevaluatedProperties: false
+
+ required:
+ - port@0
+
+ unevaluatedProperties: false
+
+ renesas,vsps:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle to VSP instance that serves the DU channel
+ - description: Channel index identifying the LIF instance in that VSP
+ description:
+ A list of phandle and channel index tuples to the VSPs that handle the
+ memory interfaces for the DU channels.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - power-domains
+ - ports
+ - renesas,vsps
+
+additionalProperties: false
+
+examples:
+ # RZ/G2L DU
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ display@10890000 {
+ compatible = "renesas,r9a07g044-du";
+ reg = <0x10890000 0x10000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+ clock-names = "aclk", "pclk", "vclk";
+ resets = <&cpg R9A07G044_LCDC_RESET_N>;
+ power-domains = <&cpg>;
+
+ renesas,vsps = <&vspd0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+...
- const: default
- const: unwedge
+ power-domains:
+ maxItems: 1
+
ports:
$ref: /schemas/graph.yaml#/properties/ports
- patternProperties:
- "^port(@0)?$":
+ properties:
+ port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input of the DWC HDMI TX
properties:
description: Connection to the VOPB
endpoint@1:
description: Connection to the VOPL
- properties:
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output of the DWC HDMI TX
+ required:
+ - port@0
+ - port@1
+
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
#include <dt-bindings/clock/rk3288-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/rk3288-power.h>
hdmi: hdmi@ff980000 {
compatible = "rockchip,rk3288-dw-hdmi";
reg = <0xff980000 0x20000>;
reg-io-width = <4>;
- ddc-i2c-bus = <&i2c5>;
- rockchip,grf = <&grf>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
clock-names = "iahb", "isfr";
+ ddc-i2c-bus = <&i2c5>;
+ power-domains = <&power RK3288_PD_VIO>;
+ rockchip,grf = <&grf>;
ports {
- port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
remote-endpoint = <&vopb_out_hdmi>;
};
+
hdmi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_hdmi>;
};
};
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
};
};
const: sinowealth,sh1106
then:
properties:
- width:
+ solomon,width:
default: 132
- height:
+ solomon,height:
default: 64
solomon,dclk-div:
default: 1
- solomon,ssd1305
then:
properties:
- width:
+ solomon,width:
default: 132
- height:
+ solomon,height:
default: 64
solomon,dclk-div:
default: 1
- solomon,ssd1306
then:
properties:
- width:
+ solomon,width:
default: 128
- height:
+ solomon,height:
default: 64
solomon,dclk-div:
default: 1
- solomon,ssd1307
then:
properties:
- width:
+ solomon,width:
default: 128
- height:
+ solomon,height:
default: 39
solomon,dclk-div:
default: 2
- solomon,ssd1309
then:
properties:
- width:
+ solomon,width:
default: 128
- height:
+ solomon,height:
default: 64
solomon,dclk-div:
default: 1
const: solomon,ssd1322
then:
properties:
- width:
+ solomon,width:
default: 480
- height:
+ solomon,height:
default: 128
- if:
const: solomon,ssd1325
then:
properties:
- width:
+ solomon,width:
default: 128
- height:
+ solomon,height:
default: 80
- if:
const: solomon,ssd1327
then:
properties:
- width:
+ solomon,width:
default: 128
- height:
+ solomon,height:
default: 128
unevaluatedProperties: false
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/solomon,ssd133x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Solomon SSD133x OLED Display Controllers
+
+maintainers:
+ - Javier Martinez Canillas <javierm@redhat.com>
+
+allOf:
+ - $ref: solomon,ssd-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - solomon,ssd1331
+
+ solomon,width:
+ default: 96
+
+ solomon,height:
+ default: 64
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ oled@0 {
+ compatible = "solomon,ssd1331";
+ reg = <0x0>;
+ reset-gpios = <&gpio2 7>;
+ dc-gpios = <&gpio2 8>;
+ spi-max-frequency = <10000000>;
+ };
+ };
- description: OVR2 overlay manager for vp2
- description: VP1 video port 1
- description: VP2 video port 2
+ - description: common1 DSS register area
reg-names:
items:
- const: ovr2
- const: vp1
- const: vp2
+ - const: common1
clocks:
items:
<0x04a07000 0x1000>, /* ovr1 */
<0x04a08000 0x1000>, /* ovr2 */
<0x04a0a000 0x1000>, /* vp1 */
- <0x04a0b000 0x1000>; /* vp2 */
+ <0x04a0b000 0x1000>, /* vp2 */
+ <0x04a01000 0x1000>; /* common1 */
reg-names = "common", "vidl1", "vid",
- "ovr1", "ovr2", "vp1", "vp2";
+ "ovr1", "ovr2", "vp1", "vp2", "common1";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 67 1>,
- items:
- const: allwinner,sun8i-r40-dma
- const: allwinner,sun50i-a64-dma
+ - items:
+ - const: allwinner,sun50i-h616-dma
+ - const: allwinner,sun50i-a100-dma
reg:
maxItems: 1
if:
properties:
compatible:
- enum:
- - allwinner,sun20i-d1-dma
- - allwinner,sun50i-a100-dma
- - allwinner,sun50i-h6-dma
+ contains:
+ enum:
+ - allwinner,sun20i-d1-dma
+ - allwinner,sun50i-a100-dma
+ - allwinner,sun50i-h6-dma
then:
properties:
- fsl,imx8qm-edma
- fsl,imx93-edma3
- fsl,imx93-edma4
+ - fsl,imx95-edma5
- items:
- const: fsl,ls1028a-edma
- const: fsl,vf610-edma
- fsl,imx8qm-edma
- fsl,imx93-edma3
- fsl,imx93-edma4
+ - fsl,imx95-edma5
then:
properties:
"#dma-cells":
description: needs firmware more than ver 2
- Shared ASRC: 23
- SAI: 24
- - HDMI Audio: 25
+ - Multi SAI: 25
+ - HDMI Audio: 26
The third cell: transfer priority ID
enum:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/marvell,mmp-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MMP DMA controller
+
+maintainers:
+ - Duje Mihanović <duje.mihanovic@skole.hr>
+
+description:
+ Marvell MMP SoCs may have two types of DMA controllers, peripheral and audio.
+
+properties:
+ compatible:
+ enum:
+ - marvell,pdma-1.0
+ - marvell,adma-1.0
+ - marvell,pxa910-squ
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Interrupt lines for the controller, may be shared or one per DMA channel
+ minItems: 1
+
+ asram:
+ description:
+ A phandle to the SRAM pool
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ '#dma-channels':
+ deprecated: true
+
+ '#dma-requests':
+ deprecated: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - '#dma-cells'
+
+allOf:
+ - $ref: dma-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - marvell,pdma-1.0
+ then:
+ properties:
+ asram: false
+ else:
+ required:
+ - asram
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ dma-controller@d4000000 {
+ compatible = "marvell,pdma-1.0";
+ reg = <0xd4000000 0x10000>;
+ interrupts = <47>;
+ #dma-cells = <2>;
+ dma-channels = <16>;
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/mediatek,mt7622-hsdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek High-Speed DMA Controller
+
+maintainers:
+ - Sean Wang <sean.wang@mediatek.com>
+
+allOf:
+ - $ref: dma-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt7622-hsdma
+ - mediatek,mt7623-hsdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: hsdma
+
+ power-domains:
+ maxItems: 1
+
+ "#dma-cells":
+ description: Channel number
+ const: 1
+
+required:
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt2701-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/mt2701-power.h>
+
+ dma-controller@1b007000 {
+ compatible = "mediatek,mt7623-hsdma";
+ reg = <0x1b007000 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <ðsys CLK_ETHSYS_HSDMA>;
+ clock-names = "hsdma";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+ #dma-cells = <1>;
+ };
+++ /dev/null
-* MARVELL MMP DMA controller
-
-Marvell Peripheral DMA Controller
-Used platforms: pxa688, pxa910, pxa3xx, etc
-
-Required properties:
-- compatible: Should be "marvell,pdma-1.0"
-- reg: Should contain DMA registers location and length.
-- interrupts: Either contain all of the per-channel DMA interrupts
- or one irq for pdma device
-
-Optional properties:
-- dma-channels: Number of DMA channels supported by the controller (defaults
- to 32 when not specified)
-- #dma-channels: deprecated
-- dma-requests: Number of DMA requestor lines supported by the controller
- (defaults to 32 when not specified)
-- #dma-requests: deprecated
-
-"marvell,pdma-1.0"
-Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
-
-Examples:
-
-/*
- * Each channel has specific irq
- * ICU parse out irq channel from ICU register,
- * while DMA controller may not able to distinguish the irq channel
- * Using this method, interrupt-parent is required as demuxer
- * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
- * 18~21 is ADMA irq
- */
-pdma: dma-controller@d4000000 {
- compatible = "marvell,pdma-1.0";
- reg = <0xd4000000 0x10000>;
- interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
- interrupt-parent = <&intcmux32>;
- dma-channels = <16>;
- };
-
-/*
- * One irq for all channels
- * Dmaengine driver (DMA controller) distinguish irq channel via
- * parsing internal register
- */
-pdma: dma-controller@d4000000 {
- compatible = "marvell,pdma-1.0";
- reg = <0xd4000000 0x10000>;
- interrupts = <47>;
- dma-channels = <16>;
- };
-
-
-Marvell Two Channel DMA Controller used specifically for audio
-Used platforms: pxa688, pxa910
-
-Required properties:
-- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
-- reg: Should contain DMA registers location and length.
-- interrupts: Either contain all of the per-channel DMA interrupts
- or one irq for dma device
-
-"marvell,adma-1.0" used on pxa688
-"marvell,pxa910-squ" used on pxa910
-
-Examples:
-
-/* each channel has specific irq */
-adma0: dma-controller@d42a0800 {
- compatible = "marvell,adma-1.0";
- reg = <0xd42a0800 0x100>;
- interrupts = <18 19>;
- interrupt-parent = <&intcmux32>;
- };
-
-/* One irq for all channels */
-squ: dma-controller@d42a0800 {
- compatible = "marvell,pxa910-squ";
- reg = <0xd42a0800 0x100>;
- interrupts = <46>;
- };
+++ /dev/null
-MediaTek High-Speed DMA Controller
-==================================
-
-This device follows the generic DMA bindings defined in dma/dma.txt.
-
-Required properties:
-
-- compatible: Must be one of
- "mediatek,mt7622-hsdma": for MT7622 SoC
- "mediatek,mt7623-hsdma": for MT7623 SoC
-- reg: Should contain the register's base address and length.
-- interrupts: Should contain a reference to the interrupt used by this
- device.
-- clocks: Should be the clock specifiers corresponding to the entry in
- clock-names property.
-- clock-names: Should contain "hsdma" entries.
-- power-domains: Phandle to the power domain that the device is part of
-- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
- in dmas property of a client device represents the channel
- number.
-Example:
-
- hsdma: dma-controller@1b007000 {
- compatible = "mediatek,mt7623-hsdma";
- reg = <0 0x1b007000 0 0x1000>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
- clocks = <ðsys CLK_ETHSYS_HSDMA>;
- clock-names = "hsdma";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
- #dma-cells = <1>;
- };
-
-DMA clients must use the format described in dma/dma.txt file.
- renesas,dmac-r8a779a0 # R-Car V3U
- renesas,dmac-r8a779f0 # R-Car S4-8
- renesas,dmac-r8a779g0 # R-Car V4H
+ - renesas,dmac-r8a779h0 # R-Car V4M
- const: renesas,rcar-gen4-dmac # R-Car Gen4
reg: true
#dma-cells = <1>;
clocks = <&clock_controller 0>, <&clock_controller 1>;
clock-names = "bus", "host";
+ #address-cells = <1>;
+ #size-cells = <1>;
vendor,custom-property = <2>;
status = "disabled";
pattern: cs16$
- items:
pattern: c32$
- - items:
- pattern: c32d-wl$
- items:
pattern: cs32$
- items:
pattern: c64$
- - items:
- pattern: c64d-wl$
- items:
pattern: cs64$
- items:
- renesas,r1ex24128
- samsung,s524ad0xd1
- const: atmel,24c128
+ - pattern: '^atmel,24c(32|64)d-wl$' # Actual vendor is st
label:
description: Descriptive name of the EEPROM.
- description: For implementations complying for Versal.
const: xlnx,versal-firmware
+ - description: For implementations complying for Versal NET.
+ items:
+ - enum:
+ - xlnx,versal-net-firmware
+ - const: xlnx,versal-firmware
+
method:
description: |
The method of calling the PM-API firmware layer.
"#power-domain-cells":
const: 1
- versal_fpga:
+ clock-controller:
+ $ref: /schemas/clock/xlnx,versal-clk.yaml#
+ description: The clock controller is a hardware block of Xilinx versal
+ clock tree. It reads required input clock frequencies from the devicetree
+ and acts as clock provider for all clock consumers of PS clocks.list of
+ clock specifiers which are external input clocks to the given clock
+ controller.
+ type: object
+
+ gpio:
+ $ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
+ description: The gpio node describes connect to PS_MODE pins via firmware
+ interface.
+ type: object
+
+ soc-nvmem:
+ $ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
+ description: The ZynqMP MPSoC provides access to the hardware related data
+ like SOC revision, IDCODE and specific purpose efuses.
+ type: object
+
+ pcap:
+ $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml
+ description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
+ configure the Programmable Logic (PL). The configuration uses the
+ firmware interface.
+ type: object
+
+ pinctrl:
+ $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
+ description: The pinctrl node provides access to pinconfig and pincontrol
+ functionality available in firmware.
+ type: object
+
+ power-management:
+ $ref: /schemas/power/reset/xlnx,zynqmp-power.yaml#
+ description: The zynqmp-power node describes the power management
+ configurations. It will control remote suspend/shutdown interfaces.
+ type: object
+
+ reset-controller:
+ $ref: /schemas/reset/xlnx,zynqmp-reset.yaml#
+ description: The reset-controller node describes connection to the reset
+ functionality via firmware interface.
+ type: object
+
+ versal-fpga:
$ref: /schemas/fpga/xlnx,versal-fpga.yaml#
description: Compatible of the FPGA device.
type: object
vector.
type: object
- clock-controller:
- $ref: /schemas/clock/xlnx,versal-clk.yaml#
- description: The clock controller is a hardware block of Xilinx versal
- clock tree. It reads required input clock frequencies from the devicetree
- and acts as clock provider for all clock consumers of PS clocks.list of
- clock specifiers which are external input clocks to the given clock
- controller.
- type: object
-
required:
- compatible
firmware {
zynqmp_firmware: zynqmp-firmware {
#power-domain-cells = <1>;
+ soc-nvmem {
+ compatible = "xlnx,zynqmp-nvmem-fw";
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc_revision: soc-revision@0 {
+ reg = <0x0 0x4>;
+ };
+ };
+ };
+ gpio {
+ compatible = "xlnx,zynqmp-gpio-modepin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ pcap {
+ compatible = "xlnx,zynqmp-pcap-fpga";
};
+ pinctrl {
+ compatible = "xlnx,zynqmp-pinctrl";
+ };
+ power-management {
+ compatible = "xlnx,zynqmp-power";
+ interrupts = <0 35 4>;
+ };
+ reset-controller {
+ compatible = "xlnx,zynqmp-reset";
+ #reset-cells = <1>;
+ };
+ };
};
sata {
compatible = "xlnx,versal-firmware";
method = "smc";
- versal_fpga: versal_fpga {
+ versal_fpga: versal-fpga {
compatible = "xlnx,versal-fpga";
};
+++ /dev/null
-FPGA Region Device Tree Binding
-
-Alan Tull 2016
-
- CONTENTS
- - Introduction
- - Terminology
- - Sequence
- - FPGA Region
- - Supported Use Models
- - Device Tree Examples
- - Constraints
-
-
-Introduction
-============
-
-FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
-the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
-control.
-
-This device tree binding document hits some of the high points of FPGA usage and
-attempts to include terminology used by both major FPGA manufacturers. This
-document isn't a replacement for any manufacturers specifications for FPGA
-usage.
-
-
-Terminology
-===========
-
-Full Reconfiguration
- * The entire FPGA is programmed.
-
-Partial Reconfiguration (PR)
- * A section of an FPGA is reprogrammed while the rest of the FPGA is not
- affected.
- * Not all FPGA's support PR.
-
-Partial Reconfiguration Region (PRR)
- * Also called a "reconfigurable partition"
- * A PRR is a specific section of an FPGA reserved for reconfiguration.
- * A base (or static) FPGA image may create a set of PRR's that later may
- be independently reprogrammed many times.
- * The size and specific location of each PRR is fixed.
- * The connections at the edge of each PRR are fixed. The image that is loaded
- into a PRR must fit and must use a subset of the region's connections.
- * The busses within the FPGA are split such that each region gets its own
- branch that may be gated independently.
-
-Persona
- * Also called a "partial bit stream"
- * An FPGA image that is designed to be loaded into a PRR. There may be
- any number of personas designed to fit into a PRR, but only one at at time
- may be loaded.
- * A persona may create more regions.
-
-FPGA Bridge
- * FPGA Bridges gate bus signals between a host and FPGA.
- * FPGA Bridges should be disabled while the FPGA is being programmed to
- prevent spurious signals on the cpu bus and to the soft logic.
- * FPGA bridges may be actual hardware or soft logic on an FPGA.
- * During Full Reconfiguration, hardware bridges between the host and FPGA
- will be disabled.
- * During Partial Reconfiguration of a specific region, that region's bridge
- will be used to gate the busses. Traffic to other regions is not affected.
- * In some implementations, the FPGA Manager transparently handles gating the
- buses, eliminating the need to show the hardware FPGA bridges in the
- device tree.
- * An FPGA image may create a set of reprogrammable regions, each having its
- own bridge and its own split of the busses in the FPGA.
-
-FPGA Manager
- * An FPGA Manager is a hardware block that programs an FPGA under the control
- of a host processor.
-
-Base Image
- * Also called the "static image"
- * An FPGA image that is designed to do full reconfiguration of the FPGA.
- * A base image may set up a set of partial reconfiguration regions that may
- later be reprogrammed.
-
- ---------------- ----------------------------------
- | Host CPU | | FPGA |
- | | | |
- | ----| | ----------- -------- |
- | | H | | |==>| Bridge0 |<==>| PRR0 | |
- | | W | | | ----------- -------- |
- | | | | | |
- | | B |<=====>|<==| ----------- -------- |
- | | R | | |==>| Bridge1 |<==>| PRR1 | |
- | | I | | | ----------- -------- |
- | | D | | | |
- | | G | | | ----------- -------- |
- | | E | | |==>| Bridge2 |<==>| PRR2 | |
- | ----| | ----------- -------- |
- | | | |
- ---------------- ----------------------------------
-
-Figure 1: An FPGA set up with a base image that created three regions. Each
-region (PRR0-2) gets its own split of the busses that is independently gated by
-a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
-reprogrammed independently while the rest of the system continues to function.
-
-
-Sequence
-========
-
-When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
-do the following:
-
- 1. Disable appropriate FPGA bridges.
- 2. Program the FPGA using the FPGA manager.
- 3. Enable the FPGA bridges.
- 4. The Device Tree overlay is accepted into the live tree.
- 5. Child devices are populated.
-
-When the overlay is removed, the child nodes will be removed and the FPGA Region
-will disable the bridges.
-
-
-FPGA Region
-===========
-
-FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA
-Region brings together the elements needed to program on a running system and
-add the child devices:
-
- * FPGA Manager
- * FPGA Bridges
- * image-specific information needed to to the programming.
- * child nodes
-
-The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
-FPGA while an operating system is running.
-
-An FPGA Region that exists in the live Device Tree reflects the current state.
-If the live tree shows a "firmware-name" property or child nodes under an FPGA
-Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
-and adds the "firmware-name" property is taken as a request to reprogram the
-FPGA. After reprogramming is successful, the overlay is accepted into the live
-tree.
-
-The base FPGA Region in the device tree represents the FPGA and supports full
-reconfiguration. It must include a phandle to an FPGA Manager. The base
-FPGA region will be the child of one of the hardware bridges (the bridge that
-allows register access) between the cpu and the FPGA. If there are more than
-one bridge to control during FPGA programming, the region will also contain a
-list of phandles to the additional hardware FPGA Bridges.
-
-For partial reconfiguration (PR), each PR region will have an FPGA Region.
-These FPGA regions are children of FPGA bridges which are then children of the
-base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
-this.
-
-If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
-Manager specified by its ancestor FPGA Region. This supports both the case
-where the same FPGA Manager is used for all of an FPGA as well the case where
-a different FPGA Manager is used for each region.
-
-FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents
-shutting down bridges that are upstream from the other active regions while one
-region is getting reconfigured (see Figure 1 above). During PR, the FPGA's
-hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges
-within the static image of the FPGA.
-
-Required properties:
-- compatible : should contain "fpga-region"
-- fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions
- inherit this property from their ancestor regions. An fpga-mgr property
- in a region will override any inherited FPGA manager.
-- #address-cells, #size-cells, ranges : must be present to handle address space
- mapping for child nodes.
-
-Optional properties:
-- firmware-name : should contain the name of an FPGA image file located on the
- firmware search path. If this property shows up in a live device tree
- it indicates that the FPGA has already been programmed with this image.
- If this property is in an overlay targeting an FPGA region, it is a
- request to program the FPGA with that image.
-- fpga-bridges : should contain a list of phandles to FPGA Bridges that must be
- controlled during FPGA programming along with the parent FPGA bridge.
- This property is optional if the FPGA Manager handles the bridges.
- If the fpga-region is the child of an fpga-bridge, the list should not
- contain the parent bridge.
-- partial-fpga-config : boolean, set if partial reconfiguration is to be done,
- otherwise full reconfiguration is done.
-- external-fpga-config : boolean, set if the FPGA has already been configured
- prior to OS boot up.
-- encrypted-fpga-config : boolean, set if the bitstream is encrypted
-- region-unfreeze-timeout-us : The maximum time in microseconds to wait for
- bridges to successfully become enabled after the region has been
- programmed.
-- region-freeze-timeout-us : The maximum time in microseconds to wait for
- bridges to successfully become disabled before the region has been
- programmed.
-- config-complete-timeout-us : The maximum time in microseconds time for the
- FPGA to go to operating mode after the region has been programmed.
-- child nodes : devices in the FPGA after programming.
-
-In the example below, when an overlay is applied targeting fpga-region0,
-fpga_mgr is used to program the FPGA. Two bridges are controlled during
-programming: the parent fpga_bridge0 and fpga_bridge1. Because the region is
-the child of fpga_bridge0, only fpga_bridge1 needs to be specified in the
-fpga-bridges property. During programming, these bridges are disabled, the
-firmware specified in the overlay is loaded to the FPGA using the FPGA manager
-specified in the region. If FPGA programming succeeds, the bridges are
-reenabled and the overlay makes it into the live device tree. The child devices
-are then populated. If FPGA programming fails, the bridges are left disabled
-and the overlay is rejected. The overlay's ranges property maps the lwhps
-bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by
-the two child devices.
-
-Example:
-Base tree contains:
-
- fpga_mgr: fpga-mgr@ff706000 {
- compatible = "altr,socfpga-fpga-mgr";
- reg = <0xff706000 0x1000
- 0xffb90000 0x20>;
- interrupts = <0 175 4>;
- };
-
- fpga_bridge0: fpga-bridge@ff400000 {
- compatible = "altr,socfpga-lwhps2fpga-bridge";
- reg = <0xff400000 0x100000>;
- resets = <&rst LWHPS2FPGA_RESET>;
- clocks = <&l4_main_clk>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- fpga_region0: fpga-region0 {
- compatible = "fpga-region";
- fpga-mgr = <&fpga_mgr>;
- };
- };
-
- fpga_bridge1: fpga-bridge@ff500000 {
- compatible = "altr,socfpga-hps2fpga-bridge";
- reg = <0xff500000 0x10000>;
- resets = <&rst HPS2FPGA_RESET>;
- clocks = <&l4_main_clk>;
- };
-
-Overlay contains:
-
-/dts-v1/;
-/plugin/;
-
-&fpga_region0 {
- #address-cells = <1>;
- #size-cells = <1>;
-
- firmware-name = "soc_system.rbf";
- fpga-bridges = <&fpga_bridge1>;
- ranges = <0x20000 0xff200000 0x100000>,
- <0x0 0xc0000000 0x20000000>;
-
- gpio@10040 {
- compatible = "altr,pio-1.0";
- reg = <0x10040 0x20>;
- altr,ngpio = <4>;
- #gpio-cells = <2>;
- clocks = <2>;
- gpio-controller;
- };
-
- onchip-memory {
- device_type = "memory";
- compatible = "altr,onchipmem-15.1";
- reg = <0x0 0x10000>;
- };
-};
-
-
-Supported Use Models
-====================
-
-In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
-a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some
-uses are specific to an FPGA device.
-
- * No FPGA Bridges
- In this case, the FPGA Manager which programs the FPGA also handles the
- bridges behind the scenes. No FPGA Bridge devices are needed for full
- reconfiguration.
-
- * Full reconfiguration with hardware bridges
- In this case, there are hardware bridges between the processor and FPGA that
- need to be controlled during full reconfiguration. Before the overlay is
- applied, the live DT must include the FPGA Manager, FPGA Bridges, and a
- FPGA Region. The FPGA Region is the child of the bridge that allows
- register access to the FPGA. Additional bridges may be listed in a
- fpga-bridges property in the FPGA region or in the device tree overlay.
-
- * Partial reconfiguration with bridges in the FPGA
- In this case, the FPGA will have one or more PRR's that may be programmed
- separately while the rest of the FPGA can remain active. To manage this,
- bridges need to exist in the FPGA that can gate the buses going to each FPGA
- region while the buses are enabled for other sections. Before any partial
- reconfiguration can be done, a base FPGA image must be loaded which includes
- PRR's with FPGA bridges. The device tree should have an FPGA region for each
- PRR.
-
-Device Tree Examples
-====================
-
-The intention of this section is to give some simple examples, focusing on
-the placement of the elements detailed above, especially:
- * FPGA Manager
- * FPGA Bridges
- * FPGA Region
- * ranges
- * target-path or target
-
-For the purposes of this section, I'm dividing the Device Tree into two parts,
-each with its own requirements. The two parts are:
- * The live DT prior to the overlay being added
- * The DT overlay
-
-The live Device Tree must contain an FPGA Region, an FPGA Manager, and any FPGA
-Bridges. The FPGA Region's "fpga-mgr" property specifies the manager by phandle
-to handle programming the FPGA. If the FPGA Region is the child of another FPGA
-Region, the parent's FPGA Manager is used. If FPGA Bridges need to be involved,
-they are specified in the FPGA Region by the "fpga-bridges" property. During
-FPGA programming, the FPGA Region will disable the bridges that are in its
-"fpga-bridges" list and will re-enable them after FPGA programming has
-succeeded.
-
-The Device Tree Overlay will contain:
- * "target-path" or "target"
- The insertion point where the contents of the overlay will go into the
- live tree. target-path is a full path, while target is a phandle.
- * "ranges"
- The address space mapping from processor to FPGA bus(ses).
- * "firmware-name"
- Specifies the name of the FPGA image file on the firmware search
- path. The search path is described in the firmware class documentation.
- * "partial-fpga-config"
- This binding is a boolean and should be present if partial reconfiguration
- is to be done.
- * child nodes corresponding to hardware that will be loaded in this region of
- the FPGA.
-
-Device Tree Example: Full Reconfiguration without Bridges
-=========================================================
-
-Live Device Tree contains:
- fpga_mgr0: fpga-mgr@f8007000 {
- compatible = "xlnx,zynq-devcfg-1.0";
- reg = <0xf8007000 0x100>;
- interrupt-parent = <&intc>;
- interrupts = <0 8 4>;
- clocks = <&clkc 12>;
- clock-names = "ref_clk";
- syscon = <&slcr>;
- };
-
- fpga_region0: fpga-region0 {
- compatible = "fpga-region";
- fpga-mgr = <&fpga_mgr0>;
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- ranges;
- };
-
-DT Overlay contains:
-
-/dts-v1/;
-/plugin/;
-
-&fpga_region0 {
- #address-cells = <1>;
- #size-cells = <1>;
-
- firmware-name = "zynq-gpio.bin";
-
- gpio1: gpio@40000000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = <0x40000000 0x10000>;
- gpio-controller;
- #gpio-cells = <0x2>;
- xlnx,gpio-width= <0x6>;
- };
-};
-
-Device Tree Example: Full Reconfiguration to add PRR's
-======================================================
-
-The base FPGA Region is specified similar to the first example above.
-
-This example programs the FPGA to have two regions that can later be partially
-configured. Each region has its own bridge in the FPGA fabric.
-
-DT Overlay contains:
-
-/dts-v1/;
-/plugin/;
-
-&fpga_region0 {
- #address-cells = <1>;
- #size-cells = <1>;
-
- firmware-name = "base.rbf";
-
- fpga-bridge@4400 {
- compatible = "altr,freeze-bridge-controller";
- reg = <0x4400 0x10>;
-
- fpga_region1: fpga-region1 {
- compatible = "fpga-region";
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- ranges;
- };
- };
-
- fpga-bridge@4420 {
- compatible = "altr,freeze-bridge-controller";
- reg = <0x4420 0x10>;
-
- fpga_region2: fpga-region2 {
- compatible = "fpga-region";
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- ranges;
- };
- };
-};
-
-Device Tree Example: Partial Reconfiguration
-============================================
-
-This example reprograms one of the PRR's set up in the previous example.
-
-The sequence that occurs when this overlay is similar to the above, the only
-differences are that the FPGA is partially reconfigured due to the
-"partial-fpga-config" boolean and the only bridge that is controlled during
-programming is the FPGA based bridge of fpga_region1.
-
-/dts-v1/;
-/plugin/;
-
-&fpga_region1 {
- #address-cells = <1>;
- #size-cells = <1>;
-
- firmware-name = "soc_image2.rbf";
- partial-fpga-config;
-
- gpio@10040 {
- compatible = "altr,pio-1.0";
- reg = <0x10040 0x20>;
- clocks = <0x2>;
- altr,ngpio = <0x4>;
- #gpio-cells = <0x2>;
- gpio-controller;
- };
-};
-
-Constraints
-===========
-
-It is beyond the scope of this document to fully describe all the FPGA design
-constraints required to make partial reconfiguration work[1] [2] [3], but a few
-deserve quick mention.
-
-A persona must have boundary connections that line up with those of the partition
-or region it is designed to go into.
-
-During programming, transactions through those connections must be stopped and
-the connections must be held at a fixed logic level. This can be achieved by
-FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
-
---
-[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
-[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
-[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FPGA Region
+
+maintainers:
+ - Michal Simek <michal.simek@amd.com>
+
+description: |
+ CONTENTS
+ - Introduction
+ - Terminology
+ - Sequence
+ - FPGA Region
+ - Supported Use Models
+ - Constraints
+
+
+ Introduction
+ ============
+
+ FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
+ the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
+ control.
+
+ The documentation hits some of the high points of FPGA usage and
+ attempts to include terminology used by both major FPGA manufacturers. This
+ document isn't a replacement for any manufacturers specifications for FPGA
+ usage.
+
+
+ Terminology
+ ===========
+
+ Full Reconfiguration
+ * The entire FPGA is programmed.
+
+ Partial Reconfiguration (PR)
+ * A section of an FPGA is reprogrammed while the rest of the FPGA is not
+ affected.
+ * Not all FPGA's support PR.
+
+ Partial Reconfiguration Region (PRR)
+ * Also called a "reconfigurable partition"
+ * A PRR is a specific section of an FPGA reserved for reconfiguration.
+ * A base (or static) FPGA image may create a set of PRR's that later may
+ be independently reprogrammed many times.
+ * The size and specific location of each PRR is fixed.
+ * The connections at the edge of each PRR are fixed. The image that is loaded
+ into a PRR must fit and must use a subset of the region's connections.
+ * The busses within the FPGA are split such that each region gets its own
+ branch that may be gated independently.
+
+ Persona
+ * Also called a "partial bit stream"
+ * An FPGA image that is designed to be loaded into a PRR. There may be
+ any number of personas designed to fit into a PRR, but only one at a time
+ may be loaded.
+ * A persona may create more regions.
+
+ FPGA Bridge
+ * FPGA Bridges gate bus signals between a host and FPGA.
+ * FPGA Bridges should be disabled while the FPGA is being programmed to
+ prevent spurious signals on the cpu bus and to the soft logic.
+ * FPGA bridges may be actual hardware or soft logic on an FPGA.
+ * During Full Reconfiguration, hardware bridges between the host and FPGA
+ will be disabled.
+ * During Partial Reconfiguration of a specific region, that region's bridge
+ will be used to gate the busses. Traffic to other regions is not affected.
+ * In some implementations, the FPGA Manager transparently handles gating the
+ buses, eliminating the need to show the hardware FPGA bridges in the
+ device tree.
+ * An FPGA image may create a set of reprogrammable regions, each having its
+ own bridge and its own split of the busses in the FPGA.
+
+ FPGA Manager
+ * An FPGA Manager is a hardware block that programs an FPGA under the control
+ of a host processor.
+
+ Base Image
+ * Also called the "static image"
+ * An FPGA image that is designed to do full reconfiguration of the FPGA.
+ * A base image may set up a set of partial reconfiguration regions that may
+ later be reprogrammed.
+
+ ---------------- ----------------------------------
+ | Host CPU | | FPGA |
+ | | | |
+ | ----| | ----------- -------- |
+ | | H | | |==>| Bridge0 |<==>| PRR0 | |
+ | | W | | | ----------- -------- |
+ | | | | | |
+ | | B |<=====>|<==| ----------- -------- |
+ | | R | | |==>| Bridge1 |<==>| PRR1 | |
+ | | I | | | ----------- -------- |
+ | | D | | | |
+ | | G | | | ----------- -------- |
+ | | E | | |==>| Bridge2 |<==>| PRR2 | |
+ | ----| | ----------- -------- |
+ | | | |
+ ---------------- ----------------------------------
+
+ Figure 1: An FPGA set up with a base image that created three regions. Each
+ region (PRR0-2) gets its own split of the busses that is independently gated by
+ a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
+ reprogrammed independently while the rest of the system continues to function.
+
+
+ Sequence
+ ========
+
+ When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
+ do the following:
+
+ 1. Disable appropriate FPGA bridges.
+ 2. Program the FPGA using the FPGA manager.
+ 3. Enable the FPGA bridges.
+ 4. The Device Tree overlay is accepted into the live tree.
+ 5. Child devices are populated.
+
+ When the overlay is removed, the child nodes will be removed and the FPGA Region
+ will disable the bridges.
+
+
+ FPGA Region
+ ===========
+
+ FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA
+ Region brings together the elements needed to program on a running system and
+ add the child devices:
+
+ * FPGA Manager
+ * FPGA Bridges
+ * image-specific information needed to the programming.
+ * child nodes
+
+ The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
+ FPGA while an operating system is running.
+
+ An FPGA Region that exists in the live Device Tree reflects the current state.
+ If the live tree shows a "firmware-name" property or child nodes under an FPGA
+ Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
+ and adds the "firmware-name" property is taken as a request to reprogram the
+ FPGA. After reprogramming is successful, the overlay is accepted into the live
+ tree.
+
+ The base FPGA Region in the device tree represents the FPGA and supports full
+ reconfiguration. It must include a phandle to an FPGA Manager. The base
+ FPGA region will be the child of one of the hardware bridges (the bridge that
+ allows register access) between the cpu and the FPGA. If there are more than
+ one bridge to control during FPGA programming, the region will also contain a
+ list of phandles to the additional hardware FPGA Bridges.
+
+ For partial reconfiguration (PR), each PR region will have an FPGA Region.
+ These FPGA regions are children of FPGA bridges which are then children of the
+ base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
+ this.
+
+ If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
+ Manager specified by its ancestor FPGA Region. This supports both the case
+ where the same FPGA Manager is used for all of an FPGA as well the case where
+ a different FPGA Manager is used for each region.
+
+ FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents
+ shutting down bridges that are upstream from the other active regions while one
+ region is getting reconfigured (see Figure 1 above). During PR, the FPGA's
+ hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges
+ within the static image of the FPGA.
+
+
+ Supported Use Models
+ ====================
+
+ In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
+ a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some
+ uses are specific to an FPGA device.
+
+ * No FPGA Bridges
+ In this case, the FPGA Manager which programs the FPGA also handles the
+ bridges behind the scenes. No FPGA Bridge devices are needed for full
+ reconfiguration.
+
+ * Full reconfiguration with hardware bridges
+ In this case, there are hardware bridges between the processor and FPGA that
+ need to be controlled during full reconfiguration. Before the overlay is
+ applied, the live DT must include the FPGA Manager, FPGA Bridges, and a
+ FPGA Region. The FPGA Region is the child of the bridge that allows
+ register access to the FPGA. Additional bridges may be listed in a
+ fpga-bridges property in the FPGA region or in the device tree overlay.
+
+ * Partial reconfiguration with bridges in the FPGA
+ In this case, the FPGA will have one or more PRR's that may be programmed
+ separately while the rest of the FPGA can remain active. To manage this,
+ bridges need to exist in the FPGA that can gate the buses going to each FPGA
+ region while the buses are enabled for other sections. Before any partial
+ reconfiguration can be done, a base FPGA image must be loaded which includes
+ PRR's with FPGA bridges. The device tree should have an FPGA region for each
+ PRR.
+
+ Constraints
+ ===========
+
+ It is beyond the scope of this document to fully describe all the FPGA design
+ constraints required to make partial reconfiguration work[1] [2] [3], but a few
+ deserve quick mention.
+
+ A persona must have boundary connections that line up with those of the partition
+ or region it is designed to go into.
+
+ During programming, transactions through those connections must be stopped and
+ the connections must be held at a fixed logic level. This can be achieved by
+ FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
+
+ --
+ [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
+ [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
+ [3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
+
+properties:
+ $nodename:
+ pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$"
+
+ compatible:
+ const: fpga-region
+
+ reg:
+ maxItems: 1
+
+ ranges: true
+ "#address-cells": true
+ "#size-cells": true
+
+ config-complete-timeout-us:
+ description:
+ The maximum time in microseconds time for the FPGA to go to operating
+ mode after the region has been programmed.
+
+ encrypted-fpga-config:
+ type: boolean
+ description:
+ Set if the bitstream is encrypted.
+
+ external-fpga-config:
+ type: boolean
+ description:
+ Set if the FPGA has already been configured prior to OS boot up.
+
+ firmware-name:
+ maxItems: 1
+ description:
+ Should contain the name of an FPGA image file located on the firmware
+ search path. If this property shows up in a live device tree it indicates
+ that the FPGA has already been programmed with this image.
+ If this property is in an overlay targeting an FPGA region, it is
+ a request to program the FPGA with that image.
+
+ fpga-bridges:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Should contain a list of phandles to FPGA Bridges that must be
+ controlled during FPGA programming along with the parent FPGA bridge.
+ This property is optional if the FPGA Manager handles the bridges.
+ If the fpga-region is the child of an fpga-bridge, the list should not
+ contain the parent bridge.
+
+ fpga-mgr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Should contain a phandle to an FPGA Manager. Child FPGA Regions
+ inherit this property from their ancestor regions. An fpga-mgr property
+ in a region will override any inherited FPGA manager.
+
+ partial-fpga-config:
+ type: boolean
+ description:
+ Set if partial reconfiguration is to be done, otherwise full
+ reconfiguration is done.
+
+ region-freeze-timeout-us:
+ description:
+ The maximum time in microseconds to wait for bridges to successfully
+ become disabled before the region has been programmed.
+
+ region-unfreeze-timeout-us:
+ description:
+ The maximum time in microseconds to wait for bridges to successfully
+ become enabled after the region has been programmed.
+
+required:
+ - compatible
+ - fpga-mgr
+
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ /*
+ * Full Reconfiguration without Bridges with DT overlay
+ */
+ fpga_region0: fpga-region@0 {
+ compatible = "fpga-region";
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ fpga-mgr = <&fpga_mgr0>;
+ ranges = <0x10000000 0x20000000 0x10000000>;
+
+ /* DT Overlay contains: &fpga_region0 */
+ firmware-name = "zynq-gpio.bin";
+ gpio@40000000 {
+ compatible = "xlnx,xps-gpio-1.00.a";
+ reg = <0x40000000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ - |
+ /*
+ * Partial reconfiguration with bridge
+ */
+ fpga_region1: fpga-region@0 {
+ compatible = "fpga-region";
+ reg = <0 0>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ fpga-mgr = <&fpga_mgr1>;
+ fpga-bridges = <&fpga_bridge1>;
+ partial-fpga-config;
+
+ /* DT Overlay contains: &fpga_region1 */
+ firmware-name = "zynq-gpio-partial.bin";
+ clk: clock {
+ compatible = "fixed-factor-clock";
+ clocks = <&parentclk>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+ axi {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ gpio@40000000 {
+ compatible = "xlnx,xps-gpio-1.00.a";
+ reg = <0x40000000 0x10000>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ clocks = <&clk>;
+ };
+ };
+ };
examples:
- |
- versal_fpga: versal_fpga {
+ versal_fpga: versal-fpga {
compatible = "xlnx,versal-fpga";
};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/aspeed,ast2400-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed GPIO controller
+
+maintainers:
+ - Andrew Jeffery <andrew@codeconstruct.com.au>
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2400-gpio
+ - aspeed,ast2500-gpio
+ - aspeed,ast2600-gpio
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: The clock to use for debounce timings
+
+ gpio-controller: true
+ gpio-line-names:
+ minItems: 36
+ maxItems: 232
+
+ gpio-ranges: true
+
+ "#gpio-cells":
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ ngpios:
+ minimum: 36
+ maximum: 232
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+ - gpio-controller
+ - "#gpio-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: aspeed,ast2400-gpio
+ then:
+ properties:
+ gpio-line-names:
+ minItems: 220
+ maxItems: 220
+ ngpios:
+ const: 220
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: aspeed,ast2500-gpio
+ then:
+ properties:
+ gpio-line-names:
+ minItems: 232
+ maxItems: 232
+ ngpios:
+ const: 232
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: aspeed,ast2600-gpio
+ then:
+ properties:
+ gpio-line-names:
+ minItems: 36
+ maxItems: 208
+ ngpios:
+ enum: [ 36, 208 ]
+ required:
+ - ngpios
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio@1e780000 {
+ compatible = "aspeed,ast2400-gpio";
+ reg = <0x1e780000 0x1000>;
+ interrupts = <20>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ - |
+ gpio: gpio@1e780000 {
+ compatible = "aspeed,ast2500-gpio";
+ reg = <0x1e780000 0x200>;
+ interrupts = <20>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 232>;
+ };
+ - |
+ #include <dt-bindings/clock/ast2600-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ gpio0: gpio@1e780000 {
+ compatible = "aspeed,ast2600-gpio";
+ reg = <0x1e780000 0x400>;
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 208>;
+ ngpios = <208>;
+ };
+ gpio1: gpio@1e780800 {
+ compatible = "aspeed,ast2600-gpio";
+ reg = <0x1e780800 0x800>;
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 208 36>;
+ ngpios = <36>;
+ };
Gateworks PLD GPIO controller bindings
-The GPIO controller should be a child node on an I2C bus,
-see: i2c/i2c.txt for details.
+The GPIO controller should be a child node on an I2C bus.
Required properties:
- compatible: Should be "gateworks,pld-gpio"
+++ /dev/null
-Aspeed GPIO controller Device Tree Bindings
--------------------------------------------
-
-Required properties:
-- compatible : Either "aspeed,ast2400-gpio", "aspeed,ast2500-gpio",
- or "aspeed,ast2600-gpio".
-
-- #gpio-cells : Should be two
- - First cell is the GPIO line number
- - Second cell is used to specify optional
- parameters (unused)
-
-- reg : Address and length of the register set for the device
-- gpio-controller : Marks the device node as a GPIO controller.
-- interrupts : Interrupt specifier (see interrupt bindings for
- details)
-- interrupt-controller : Mark the GPIO controller as an interrupt-controller
-
-Optional properties:
-
-- clocks : A phandle to the clock to use for debounce timings
-- ngpios : Number of GPIOs controlled by this controller. Should be set
- when there are multiple GPIO controllers on a SoC (ast2600).
-
-The gpio and interrupt properties are further described in their respective
-bindings documentation:
-
-- Documentation/devicetree/bindings/gpio/gpio.txt
-- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
- Example:
- gpio@1e780000 {
- #gpio-cells = <2>;
- compatible = "aspeed,ast2400-gpio";
- gpio-controller;
- interrupts = <20>;
- reg = <0x1e780000 0x1000>;
- interrupt-controller;
- };
required:
- reg
-unevaluatedProperties: true
+unevaluatedProperties: false
examples:
- |
+++ /dev/null
-Nomadik GPIO controller
-
-Required properties:
-- compatible : Should be "st,nomadik-gpio".
-- reg : Physical base address and length of the controller's registers.
-- interrupts : The interrupt outputs from the controller.
-- #gpio-cells : Should be two:
- The first cell is the pin number.
- The second cell is used to specify optional parameters:
- - bits[3:0] trigger type and level flags:
- 1 = low-to-high edge triggered.
- 2 = high-to-low edge triggered.
- 4 = active high level-sensitive.
- 8 = active low level-sensitive.
-- gpio-controller : Marks the device node as a GPIO controller.
-- interrupt-controller : Marks the device node as an interrupt controller.
-- gpio-bank : Specifies which bank a controller owns.
-- st,supports-sleepmode : Specifies whether controller can sleep or not
-
-Example:
-
- gpio1: gpio@8012e080 {
- compatible = "st,nomadik-gpio";
- reg = <0x8012e080 0x80>;
- interrupts = <0 120 0x4>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- st,supports-sleepmode;
- gpio-bank = <1>;
- };
minItems: 4
maxItems: 8
+ label:
+ description: A descriptive name for this device.
+
required:
- compatible
- reg
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
- - Rob Herring <robh+dt@kernel.org>
+ - Rob Herring <robh@kernel.org>
allOf:
- if:
- renesas,gpio-r8a779a0 # R-Car V3U
- renesas,gpio-r8a779f0 # R-Car S4-8
- renesas,gpio-r8a779g0 # R-Car V4H
+ - renesas,gpio-r8a779h0 # R-Car V4M
- const: renesas,rcar-gen4-gpio # R-Car Gen4
reg:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/st,nomadik-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nomadik GPIO controller
+
+description:
+ The Nomadik GPIO driver handles Nomadik SoC GPIO blocks. This block has also
+ been called ST STA2X11. On the Nomadik platform, this driver is intertwined
+ with pinctrl-nomadik.
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+properties:
+ $nodename:
+ pattern: "^gpio@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - st,nomadik-gpio
+ - mobileye,eyeq5-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ gpio-bank:
+ description: System-wide GPIO bank index.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ st,supports-sleepmode:
+ description: Whether the controller can sleep or not.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ clocks:
+ maxItems: 1
+
+ gpio-ranges:
+ maxItems: 1
+
+ ngpios:
+ minimum: 0
+ maximum: 32
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#gpio-cells"
+ - gpio-controller
+ - interrupt-controller
+ - gpio-bank
+
+unevaluatedProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mobileye,eyeq5-gpio
+ then:
+ properties:
+ st,supports-sleepmode: false
+
+examples:
+ - |
+ gpio@8012e080 {
+ compatible = "st,nomadik-gpio";
+ reg = <0x8012e080 0x80>;
+ interrupts = <0 120 0x4>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ st,supports-sleepmode;
+ gpio-bank = <1>;
+ };
# Copyright (c) 2023 Imagination Technologies Ltd.
%YAML 1.2
---
-$id: http://devicetree.org/schemas/gpu/img,powervr.yaml#
+$id: http://devicetree.org/schemas/gpu/img,powervr-rogue.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Imagination Technologies PowerVR and IMG GPU
+title: Imagination Technologies PowerVR and IMG Rogue GPUs
maintainers:
- Frank Binns <frank.binns@imgtec.com>
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2023 Imagination Technologies Ltd.
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination Technologies PowerVR SGX GPUs
+
+maintainers:
+ - Frank Binns <frank.binns@imgtec.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - ti,omap3430-gpu # Rev 121
+ - ti,omap3630-gpu # Rev 125
+ - const: img,powervr-sgx530
+ - items:
+ - enum:
+ - ingenic,jz4780-gpu # Rev 130
+ - ti,omap4430-gpu # Rev 120
+ - const: img,powervr-sgx540
+ - items:
+ - enum:
+ - allwinner,sun6i-a31-gpu # MP2 Rev 115
+ - ti,omap4470-gpu # MP1 Rev 112
+ - ti,omap5432-gpu # MP2 Rev 105
+ - ti,am5728-gpu # MP2 Rev 116
+ - ti,am6548-gpu # MP1 Rev 117
+ - const: img,powervr-sgx544
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: core
+ - const: mem
+ - const: sys
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,am6548-gpu
+ then:
+ required:
+ - power-domains
+ else:
+ properties:
+ power-domains: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - allwinner,sun6i-a31-gpu
+ - ingenic,jz4780-gpu
+ then:
+ required:
+ - clocks
+ - clock-names
+ else:
+ properties:
+ clocks: false
+ clock-names: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun6i-a31-gpu
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ minItems: 2
+ maxItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ingenic,jz4780-gpu
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+ gpu@7000000 {
+ compatible = "ti,am6548-gpu", "img,powervr-sgx544";
+ reg = <0x7000000 0x10000>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ gpu: gpu@1c40000 {
+ compatible = "allwinner,sun6i-a31-gpu", "img,powervr-sgx544";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu 1>, <&ccu 2>;
+ clock-names = "core", "mem";
+ };
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: hwmon-common.yaml#
+
+unevaluatedProperties: false
examples:
- |
reg:
maxItems: 1
- shunt-resistor-micro-ohms:
- description:
- Shunt resistor value in micro-Ohm.
-
adi,volt-curr-sample-average:
description: |
Number of samples to be used to report voltage and current values.
enum: [1, 2, 4, 8, 16, 32, 64, 128]
allOf:
+ - $ref: hwmon-common.yaml#
- if:
properties:
compatible:
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: hwmon-common.yaml#
+
+unevaluatedProperties: false
examples:
- |
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/adi,ltc4282.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices LTC4282 I2C High Current Hot Swap Controller over I2C
+
+maintainers:
+ - Nuno Sa <nuno.sa@analog.com>
+
+description: |
+ Analog Devices LTC4282 I2C High Current Hot Swap Controller over I2C.
+
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4282.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ltc4282
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+ adi,rsense-nano-ohms:
+ description: Value of the sense resistor.
+
+ adi,vin-mode-microvolt:
+ description:
+ Selects operating range for the Undervoltage, Overvoltage and Foldback
+ pins. Also for the ADC. Should be set to the nominal input voltage.
+ enum: [3300000, 5000000, 12000000, 24000000]
+ default: 12000000
+
+ adi,fet-bad-timeout-ms:
+ description:
+ From the moment a FET bad conditions is present, this property selects the
+ wait time/timeout for a FET-bad fault to be signaled. Setting this to 0,
+ disables FET bad faults to be reported.
+ default: 255
+ maximum: 255
+
+ adi,overvoltage-dividers:
+ description: |
+ Select which dividers to use for VDD Overvoltage detection. Note that
+ when the internal dividers are used the threshold is referenced to VDD.
+ The percentages in the datasheet are misleading since the actual values
+ to look for are in the "Absolute Maximum Ratings" table in the
+ "Comparator Inputs" section. In there there's a line for each of the 5%,
+ 10% and 15% settings with the actual min, typical and max tolerances.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [external, vdd_5_percent, vdd_10_percent, vdd_15_percent]
+ default: external
+
+ adi,undervoltage-dividers:
+ description: |
+ Select which dividers to use for VDD Overvoltage detection. Note that
+ when the internal dividers are used the threshold is referenced to VDD.
+ The percentages in the datasheet are misleading since the actual values
+ to look for are in the "Absolute Maximum Ratings" table in the
+ "Comparator Inputs" section. In there there's a line for each of the 5%,
+ 10% and 15% settings with the actual min, typical and max tolerances.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [external, vdd_5_percent, vdd_10_percent, vdd_15_percent]
+ default: external
+
+ adi,current-limit-sense-microvolt:
+ description:
+ The current limit sense voltage of the chip is adjustable between
+ 12.5mV and 34.4mV in 3.1mV steps. This effectively limits the current
+ on the load.
+ enum: [12500, 15625, 18750, 21875, 25000, 28125, 31250, 34375]
+ default: 25000
+
+ adi,overcurrent-retry:
+ description:
+ If set, enables the chip to auto-retry 256 timer cycles after an
+ Overcurrent fault.
+ type: boolean
+
+ adi,overvoltage-retry-disable:
+ description:
+ If set, disables the chip to auto-retry 50ms after an Overvoltage fault.
+ It's enabled by default.
+ type: boolean
+
+ adi,undervoltage-retry-disable:
+ description:
+ If set, disables the chip to auto-retry 50ms after an Undervoltage fault.
+ It's enabled by default.
+ type: boolean
+
+ adi,fault-log-enable:
+ description:
+ If set, enables the FAULT_LOG and ADC_ALERT_LOG registers to be written
+ to the EEPROM when a fault bit transitions high and hence, will be
+ available after a power cycle (the chip loads the contents of
+ the EE_FAULT_LOG register - the one in EEPROM - into FAULT_LOG at boot).
+ type: boolean
+
+ adi,gpio1-mode:
+ description: Defines the function of the Pin. It can indicate that power is
+ good (PULL the pin low when power is not good) or that power is bad (Go
+ into high-z when power is not good).
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [power_bad, power_good]
+ default: power_good
+
+ adi,gpio2-mode:
+ description: Defines the function of the Pin. It can be set as the input for
+ the ADC or indicating that the MOSFET is in stress (dissipating power).
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [adc_input, stress_fet]
+ default: adc_input
+
+ adi,gpio3-monitor-enable:
+ description: If set, gpio3 is set as input for the ADC instead of gpio2.
+ type: boolean
+
+allOf:
+ - if:
+ required:
+ - adi,gpio3-monitor-enable
+ then:
+ properties:
+ adi,gpio2-mode:
+ const: stress_fet
+
+required:
+ - compatible
+ - reg
+ - adi,rsense-nano-ohms
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hwmon@50 {
+ compatible = "adi,ltc4282";
+ reg = <0x50>;
+ adi,rsense-nano-ohms = <500>;
+
+ adi,gpio1-mode = "power_good";
+ adi,gpio2-mode = "adc_input";
+ };
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/amphenol,chipcap2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ChipCap 2 humidity and temperature iio sensor
+
+maintainers:
+ - Javier Carrasco <javier.carrasco.cruz@gmail.com>
+
+description: |
+ Relative humidity and temperature sensor on I2C bus.
+
+ Datasheets:
+ https://www.amphenol-sensors.com/en/telaire/humidity/527-humidity-sensors/3095-chipcap-2
+
+properties:
+ compatible:
+ oneOf:
+ - const: amphenol,cc2d23
+ - items:
+ - enum:
+ - amphenol,cc2d23s
+ - amphenol,cc2d25
+ - amphenol,cc2d25s
+ - amphenol,cc2d33
+ - amphenol,cc2d33s
+ - amphenol,cc2d35
+ - amphenol,cc2d35s
+ - const: amphenol,cc2d23
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: measurement ready indicator
+ - description: low humidity alarm
+ - description: high humidity alarm
+
+ interrupt-names:
+ items:
+ - const: ready
+ - const: low
+ - const: high
+
+ vdd-supply:
+ description:
+ Dedicated, controllable supply-regulator to reset the device and
+ enter in command mode.
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ humidity@28 {
+ compatible = "amphenol,cc2d23s", "amphenol,cc2d23";
+ reg = <0x28>;
+ interrupt-parent = <&gpio>;
+ interrupts = <4 IRQ_TYPE_EDGE_RISING>,
+ <5 IRQ_TYPE_EDGE_RISING>,
+ <6 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ready", "low", "high";
+ vdd-supply = <®_vdd>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2023 Aspeed, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/aspeed,g6-pwm-tach.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED G6 PWM and Fan Tach controller
+
+maintainers:
+ - Billy Tsai <billy_tsai@aspeedtech.com>
+
+description: |
+ The ASPEED PWM controller can support up to 16 PWM outputs.
+ The ASPEED Fan Tacho controller can support up to 16 fan tach input.
+ They are independent hardware blocks, which are different from the
+ previous version of the ASPEED chip.
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2600-pwm-tach
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+
+patternProperties:
+ "^fan-[0-9]+$":
+ $ref: fan-common.yaml#
+ unevaluatedProperties: false
+ required:
+ - tach-ch
+
+required:
+ - reg
+ - clocks
+ - resets
+ - "#pwm-cells"
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/aspeed-clock.h>
+ pwm_tach: pwm-tach-controller@1e610000 {
+ compatible = "aspeed,ast2600-pwm-tach";
+ reg = <0x1e610000 0x100>;
+ clocks = <&syscon ASPEED_CLK_AHB>;
+ resets = <&syscon ASPEED_RESET_PWM>;
+ #pwm-cells = <3>;
+
+ fan-0 {
+ tach-ch = /bits/ 8 <0x0>;
+ pwms = <&pwm_tach 0 40000 0>;
+ };
+
+ fan-1 {
+ tach-ch = /bits/ 8 <0x1 0x2>;
+ pwms = <&pwm_tach 1 40000 0>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/fan-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common Fan Properties
+
+maintainers:
+ - Naresh Solanki <naresh.solanki@9elements.com>
+ - Billy Tsai <billy_tsai@aspeedtech.com>
+
+properties:
+ max-rpm:
+ description:
+ Max RPM supported by fan.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 100000
+
+ min-rpm:
+ description:
+ Min RPM supported by fan.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 1000
+
+ pulses-per-revolution:
+ description:
+ The number of pulse from fan sensor per revolution.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 4
+
+ tach-div:
+ description:
+ Divisor for the tach sampling clock, which determines the sensitivity of the tach pin.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ target-rpm:
+ description:
+ The default desired fan speed in RPM.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ fan-driving-mode:
+ description:
+ Select the driving mode of the fan.(DC, PWM and so on)
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [ dc, pwm ]
+
+ pwms:
+ description:
+ PWM provider.
+ maxItems: 1
+
+ "#cooling-cells":
+ const: 2
+
+ cooling-levels:
+ description:
+ The control value which correspond to thermal cooling states.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ tach-ch:
+ description:
+ The tach channel used for the fan.
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+
+ label:
+ description:
+ Optional fan label
+
+ fan-supply:
+ description:
+ Power supply for fan.
+
+ reg:
+ maxItems: 1
+
+additionalProperties: true
+
+...
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/hwmon-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hardware Monitoring Devices Common Properties
+
+maintainers:
+ - Guenter Roeck <linux@roeck-us.net>
+
+properties:
+ label:
+ description: A descriptive name for this device.
+
+ shunt-resistor-micro-ohms:
+ description: The value of current sense resistor.
+
+additionalProperties: true
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: hwmon-common.yaml#
+
+unevaluatedProperties: false
examples:
- |
The default is 102.4 volts.
type: boolean
- shunt-resistor-micro-ohms:
- description:
- Resistor value micro-ohms.
-
required:
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: hwmon-common.yaml#
+
+unevaluatedProperties: false
examples:
- |
- reg
allOf:
+ - $ref: hwmon-common.yaml#
- if:
not:
properties:
properties:
interrupts: false
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- nuvoton,nct6796
- nuvoton,nct6797
- nuvoton,nct6798
+ - nuvoton,nct6799
reg:
maxItems: 1
unconnected(has internal pull-down).
type: boolean
+ interrupts:
+ maxItems: 1
+
+ regulators:
+ type: object
+ description:
+ list of regulators provided by this controller.
+
+ properties:
+ vout:
+ $ref: /schemas/regulator/regulator.yaml#
+ type: object
+
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
required:
- compatible
- reg
examples:
- |
+ #include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
tda38640@40 {
compatible = "infineon,tda38640";
reg = <0x40>;
+
+ interrupt-parent = <&smb_pex_cpu0_event>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ pvnn_main_cpu0: vout {
+ regulator-name = "pvnn_main_cpu0";
+ regulator-enable-ramp-delay = <200>;
+ };
+ };
};
};
Shunt (sense) resistor value in micro-Ohms
default: 1000
+ regulators:
+ type: object
+
+ properties:
+ vout:
+ $ref: /schemas/regulator/regulator.yaml#
+ type: object
+
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
required:
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: /schemas/hwmon/hwmon-common.yaml#
+
+unevaluatedProperties: false
examples:
- |
- ti,ina231
- ti,ina237
- ti,ina238
+ - ti,ina260
reg:
maxItems: 1
+ "#io-channel-cells":
+ const: 1
+
shunt-resistor:
description:
Shunt resistor value in micro-Ohm.
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: hwmon-common.yaml#
+
+unevaluatedProperties: false
examples:
- |
power-sensor@44 {
compatible = "ti,ina220";
reg = <0x44>;
+ #io-channel-cells = <1>;
+ label = "vdd_3v0";
shunt-resistor = <1000>;
vs-supply = <&vdd_3v0>;
};
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: hwmon-common.yaml#
+
+unevaluatedProperties: false
examples:
- |
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: hwmon-common.yaml#
+
+unevaluatedProperties: false
examples:
- |
- atmel,sama5d2-i2c
- microchip,sam9x60-i2c
- items:
- - const: microchip,sama7g5-i2c
+ - enum:
+ - microchip,sama7g5-i2c
+ - microchip,sam9x7-i2c
- const: microchip,sam9x60-i2c
reg:
+-------------------------------+
allOf:
- - $ref: i2c-mux.yaml
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
i2c-parent:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description:
List of phandles of I2C masters available for selection. The first one
will be used as default.
- const: samsung,exynos7-hsi2c
- items:
- enum:
+ - google,gs101-hsi2c
- samsung,exynos850-hsi2c
- const: samsung,exynosautov9-hsi2c
- const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420
- fsl,imx8qm-lpi2c
- fsl,imx8ulp-lpi2c
- fsl,imx93-lpi2c
+ - fsl,imx95-lpi2c
- const: fsl,imx7ulp-lpi2c
reg:
interrupts = <43 2>;
interrupt-parent = <&mpic>;
clock-frequency = <400000>;
- i2c-scl-clk-low-timeout-us = <10000>;
+ i2c-transfer-timeout-us = <10000>;
};
...
description: A voltage regulator supplying power to the chip. On PCA9846
the regulator supplies power to VDD2 (core logic) and optionally to VDD1.
+ maxim,isolate-stuck-channel:
+ type: boolean
+ description: Allows to use non faulty channels while a stuck channel is
+ isolated from the upstream bus. If not set all channels are isolated from
+ the upstream bus until the fault is cleared.
+
+ maxim,send-flush-out-sequence:
+ type: boolean
+ description: Send a flush-out sequence to stuck auxiliary buses
+ automatically after a stuck channel is being detected.
+
+ maxim,preconnection-wiggle-test-enable:
+ type: boolean
+ description: Send a STOP condition to the auxiliary buses when the switch
+ register activates a channel to detect a stuck high fault. On fault the
+ channel is isolated from the upstream bus.
+
required:
- compatible
- reg
"#interrupt-cells": false
interrupt-controller: false
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - maxim,max7357
+ then:
+ properties:
+ maxim,isolate-stuck-channel: false
+ maxim,send-flush-out-sequence: false
+ maxim,preconnection-wiggle-test-enable: false
+
unevaluatedProperties: false
examples:
title: Marvell MMP I2C controller
maintainers:
- - Rob Herring <robh+dt@kernel.org>
+ - Rob Herring <robh@kernel.org>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
+++ /dev/null
-Generic device tree bindings for I2C busses
-===========================================
-
-This document describes generic bindings which can be used to describe I2C
-busses and their child devices in a device tree.
-
-Required properties (per bus)
------------------------------
-
-- #address-cells - should be <1>. Read more about addresses below.
-- #size-cells - should be <0>.
-- compatible - name of I2C bus controller
-
-For other required properties e.g. to describe register sets,
-clocks, etc. check the binding documentation of the specific driver.
-
-The cells properties above define that an address of children of an I2C bus
-are described by a single value.
-
-Optional properties (per bus)
------------------------------
-
-These properties may not be supported by all drivers. However, if a driver
-wants to support one of the below features, it should adapt these bindings.
-
-- clock-frequency
- frequency of bus clock in Hz.
-
-- i2c-bus
- For I2C adapters that have child nodes that are a mixture of both I2C
- devices and non-I2C devices, the 'i2c-bus' subnode can be used for
- populating I2C devices. If the 'i2c-bus' subnode is present, only
- subnodes of this will be considered as I2C slaves. The properties,
- '#address-cells' and '#size-cells' must be defined under this subnode
- if present.
-
-- i2c-scl-falling-time-ns
- Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C
- specification.
-
-- i2c-scl-internal-delay-ns
- Number of nanoseconds the IP core additionally needs to setup SCL.
-
-- i2c-scl-rising-time-ns
- Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C
- specification.
-
-- i2c-sda-falling-time-ns
- Number of nanoseconds the SDA signal takes to fall; t(f) in the I2C
- specification.
-
-- i2c-analog-filter
- Enable analog filter for i2c lines.
-
-- i2c-digital-filter
- Enable digital filter for i2c lines.
-
-- i2c-digital-filter-width-ns
- Width of spikes which can be filtered by digital filter
- (i2c-digital-filter). This width is specified in nanoseconds.
-
-- i2c-analog-filter-cutoff-frequency
- Frequency that the analog filter (i2c-analog-filter) uses to distinguish
- which signal to filter. Signal with higher frequency than specified will
- be filtered out. Only lower frequency will pass (this is applicable to
- a low-pass analog filter). Typical value should be above the normal
- i2c bus clock frequency (clock-frequency).
- Specified in Hz.
-
-- multi-master
- states that there is another master active on this bus. The OS can use
- this information to adapt power management to keep the arbitration awake
- all the time, for example. Can not be combined with 'single-master'.
-
-- pinctrl
- add extra pinctrl to configure SCL/SDA pins to GPIO function for bus
- recovery, call it "gpio" or "recovery" (deprecated) state
-
-- scl-gpios
- specify the gpio related to SCL pin. Used for GPIO bus recovery.
-
-- sda-gpios
- specify the gpio related to SDA pin. Optional for GPIO bus recovery.
-
-- single-master
- states that there is no other master active on this bus. The OS can use
- this information to detect a stalled bus more reliably, for example.
- Can not be combined with 'multi-master'.
-
-- smbus
- states that additional SMBus restrictions and features apply to this bus.
- An example of feature is SMBusHostNotify. Examples of restrictions are
- more reserved addresses and timeout definitions.
-
-- smbus-alert
- states that the optional SMBus-Alert feature apply to this bus.
-
-- mctp-controller
- indicates that the system is accessible via this bus as an endpoint for
- MCTP over I2C transport.
-
-Required properties (per child device)
---------------------------------------
-
-- compatible
- name of I2C slave device
-
-- reg
- One or many I2C slave addresses. These are usually a 7 bit addresses.
- However, flags can be attached to an address. I2C_TEN_BIT_ADDRESS is
- used to mark a 10 bit address. It is needed to avoid the ambiguity
- between e.g. a 7 bit address of 0x50 and a 10 bit address of 0x050
- which, in theory, can be on the same bus.
- Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we
- listen to be devices ourselves.
-
-Optional properties (per child device)
---------------------------------------
-
-These properties may not be supported by all drivers. However, if a driver
-wants to support one of the below features, it should adapt these bindings.
-
-- host-notify
- device uses SMBus host notify protocol instead of interrupt line.
-
-- interrupts
- interrupts used by the device.
-
-- interrupt-names
- "irq", "wakeup" and "smbus_alert" names are recognized by I2C core,
- other names are left to individual drivers.
-
-- reg-names
- Names of map programmable addresses.
- It can contain any map needing another address than default one.
-
-- wakeup-source
- device can be used as a wakeup source.
-
-Binding may contain optional "interrupts" property, describing interrupts
-used by the device. I2C core will assign "irq" interrupt (or the very first
-interrupt if not using interrupt names) as primary interrupt for the slave.
-
-Alternatively, devices supporting SMBus Host Notify, and connected to
-adapters that support this feature, may use "host-notify" property. I2C
-core will create a virtual interrupt for Host Notify and assign it as
-primary interrupt for the slave.
-
-Also, if device is marked as a wakeup source, I2C core will set up "wakeup"
-interrupt for the device. If "wakeup" interrupt name is not present in the
-binding, then primary interrupt will be used as wakeup interrupt.
See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
binding.
- This node represents an I2C controller. See ../i2c/i2c.txt for details
- of the core I2C binding.
+ This node represents an I2C controller.
properties:
compatible:
port {
ov7251_ep: endpoint {
- data-lanes = <0 1>;
+ data-lanes = <0>;
link-frequencies = /bits/ 64 <240000000 319200000>;
remote-endpoint = <&csiphy3_ep>;
};
- renesas,i2c-r8a779a0 # R-Car V3U
- renesas,i2c-r8a779f0 # R-Car S4-8
- renesas,i2c-r8a779g0 # R-Car V4H
+ - renesas,i2c-r8a779h0 # R-Car V4M
- const: renesas,rcar-gen4-i2c # R-Car Gen4
reg:
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
-allOf:
- - $ref: /schemas/i2c/i2c-controller.yaml#
-
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
contains:
enum:
- st,nomadik-i2c
+ - mobileye,eyeq5-i2c
required:
- compatible
properties:
compatible:
oneOf:
- # The variant found in STn8815
- items:
- const: st,nomadik-i2c
- const: arm,primecell
- # The variant found in DB8500
- items:
- const: stericsson,db8500-i2c
- const: st,nomadik-i2c
- const: arm,primecell
+ - items:
+ - const: mobileye,eyeq5-i2c
+ - const: arm,primecell
reg:
maxItems: 1
- items:
- const: mclk
- const: apb_pclk
- # Clock name in DB8500
+ # Clock name in DB8500 or EyeQ5
- items:
- const: i2cclk
- const: apb_pclk
minimum: 1
maximum: 400000
+ mobileye,olb:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: Phandle to OLB system controller node.
+ - description: Platform-wide controller ID (integer starting from zero).
+ description:
+ The phandle pointing to OLB system controller node, with the I2C
+ controller index.
+
required:
- compatible
- reg
unevaluatedProperties: false
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mobileye,eyeq5-i2c
+ then:
+ required:
+ - mobileye,olb
+ else:
+ properties:
+ mobileye,olb: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
clocks = <&i2c0clk>, <&pclki2c0>;
clock-names = "mclk", "apb_pclk";
};
+ - |
+ #include <dt-bindings/interrupt-controller/mips-gic.h>
+ i2c@300000 {
+ compatible = "mobileye,eyeq5-i2c", "arm,primecell";
+ reg = <0x300000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&i2c_ser_clk>, <&i2c_clk>;
+ clock-names = "i2cclk", "apb_pclk";
+ mobileye,olb = <&olb 0>;
+ };
...
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
- i3c-master@2000 {
+ i3c@2000 {
compatible = "aspeed,ast2600-i3c";
reg = <0x2000 0x1000>;
#address-cells = <3>;
examples:
- |
- i3c-master@d040000 {
+ i3c@d040000 {
compatible = "cdns,i3c-master";
clocks = <&coreclock>, <&i3csysclock>;
clock-names = "pclk", "sysclk";
properties:
$nodename:
- pattern: "^i3c-master@[0-9a-f]+$"
+ pattern: "^i3c@[0-9a-f]+$"
"#address-cells":
const: 3
description: |
I2C child, should be named: <device-type>@<i2c-address>
- All properties described in Documentation/devicetree/bindings/i2c/i2c.txt
+ All properties described in dtschema schemas/i2c/i2c-controller.yaml
are valid here, except the reg property whose content is changed.
properties:
examples:
- |
- i3c-master@d040000 {
+ i3c@d040000 {
compatible = "cdns,i3c-master";
clocks = <&coreclock>, <&i3csysclock>;
clock-names = "pclk", "sysclk";
examples:
- |
- i3c-master@a0000000 {
+ i3c@a0000000 {
compatible = "mipi-i3c-hci";
reg = <0xa0000000 0x2000>;
interrupts = <89>;
examples:
- |
- i3c-master@a0000000 {
+ i3c@a0000000 {
compatible = "silvaco,i3c-master-v1";
clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>;
clock-names = "pclk", "fast_clk", "slow_clk";
examples:
- |
- i3c-master@2000 {
+ i3c@2000 {
compatible = "snps,dw-i3c-master-1.00a";
#address-cells = <3>;
#size-cells = <0>;
maxItems: 1
label:
- $ref: /schemas/types.yaml#/definitions/string
description: Unique name to identify which channel this is.
bipolar:
Pin that controls the powerdown mode of the device.
maxItems: 1
+ io-backends:
+ maxItems: 1
+
reset-gpios:
description:
Reset pin for the device.
reg = <0>;
clocks = <&adc_clk>;
clock-names = "adc-clk";
+ io-backends = <&iio_backend>;
};
};
...
$ref: /schemas/types.yaml#/definitions/phandle
description:
A reference to a the actual ADC to which this FPGA ADC interfaces to.
+ deprecated: true
+
+ '#io-backend-cells':
+ const: 0
required:
- compatible
- dmas
- reg
- - adi,adc-dev
additionalProperties: false
reg = <0x44a00000 0x10000>;
dmas = <&rx_dma 0>;
dma-names = "rx";
-
- adi,adc-dev = <&spi_adc>;
+ #io-backend-cells = <0>;
};
...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/microchip,pac1934.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PAC1934 Power Monitors with Accumulator
+
+maintainers:
+ - Marius Cristea <marius.cristea@microchip.com>
+
+description: |
+ This device is part of the Microchip family of Power Monitors with
+ Accumulator.
+ The datasheet for PAC1931, PAC1932, PAC1933 and PAC1934 can be found here:
+ https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/PAC1931-Family-Data-Sheet-DS20005850E.pdf
+
+properties:
+ compatible:
+ enum:
+ - microchip,pac1931
+ - microchip,pac1932
+ - microchip,pac1933
+ - microchip,pac1934
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ interrupts:
+ maxItems: 1
+
+ slow-io-gpios:
+ description:
+ A GPIO used to trigger a change is sampling rate (lowering the chip power
+ consumption). If configured in SLOW mode, if this pin is forced high,
+ sampling rate is forced to eight samples/second. When it is forced low,
+ the sampling rate is 1024 samples/second unless a different sample rate
+ has been programmed.
+
+patternProperties:
+ "^channel@[1-4]+$":
+ type: object
+ $ref: adc.yaml
+ description:
+ Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ items:
+ minimum: 1
+ maximum: 4
+
+ shunt-resistor-micro-ohms:
+ description:
+ Value in micro Ohms of the shunt resistor connected between
+ the SENSE+ and SENSE- inputs, across which the current is measured.
+ Value is needed to compute the scaling of the measured current.
+
+ required:
+ - reg
+ - shunt-resistor-micro-ohms
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-monitor@10 {
+ compatible = "microchip,pac1934";
+ reg = <0x10>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@1 {
+ reg = <0x1>;
+ shunt-resistor-micro-ohms = <24900000>;
+ label = "CPU";
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ shunt-resistor-micro-ohms = <49900000>;
+ label = "GPU";
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ shunt-resistor-micro-ohms = <75000000>;
+ label = "MEM";
+ bipolar;
+ };
+
+ channel@4 {
+ reg = <0x4>;
+ shunt-resistor-micro-ohms = <100000000>;
+ label = "NET";
+ bipolar;
+ };
+ };
+ };
+
+...
- description: normal conversion, include EOC (End of Conversion),
ECH (End of Chain), JEOC (End of Injected Conversion) and
JECH (End of injected Chain).
- - description: Self-testing Interrupts.
clocks:
maxItems: 1
reg = <0x44530000 0x10000>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_ADC1_GATE>;
clock-names = "ipg";
vref-supply = <®_vref_1v8>;
in the PMIC-specific files in include/dt-bindings/iio/.
label:
- $ref: /schemas/types.yaml#/definitions/string
description: |
ADC input of the platform as seen in the schematics.
For thermistor inputs connected to generic AMUX or GPIO inputs
properties:
compatible:
- const: richtek,rtq6056
+ oneOf:
+ - enum:
+ - richtek,rtq6056
+ - richtek,rtq6059
+ - items:
+ - enum:
+ - richtek,rtq6053
+ - const: richtek,rtq6056
reg:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads1298.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments' ads1298 medical ADC chips
+
+description: |
+ Datasheet at: https://www.ti.com/product/ADS1298
+ Bindings for this chip aren't complete.
+
+maintainers:
+ - Mike Looijmans <mike.looijmans@topic.nl>
+
+properties:
+ compatible:
+ enum:
+ - ti,ads1298
+
+ reg:
+ maxItems: 1
+
+ spi-cpha: true
+
+ reset-gpios:
+ maxItems: 1
+
+ avdd-supply:
+ description:
+ Analog power supply, voltage between AVDD and AVSS. When providing a
+ symmetric +/- 2.5V, the regulator should report 5V.
+
+ vref-supply:
+ description:
+ Optional reference voltage. If omitted, internal reference is used,
+ which is 2.4V when analog supply is below 4.4V, 4V otherwise.
+
+ clocks:
+ description: Optional 2.048 MHz external source clock on CLK pin
+ maxItems: 1
+
+ interrupts:
+ description: Interrupt on DRDY pin, triggers on falling edge
+ maxItems: 1
+
+ label: true
+
+required:
+ - compatible
+ - reg
+ - avdd-supply
+ - interrupts
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@1 {
+ reg = <1>;
+ compatible = "ti,ads1298";
+ label = "ads1298-1-ecg";
+ avdd-supply = <®_iso_5v_a>;
+ clocks = <&clk_ads1298>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <78 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <20000000>;
+ spi-cpha;
+ };
+ };
+...
description: |
Channel node of a voltage io-channel.
+ '#io-channel-cells':
+ description:
+ In addition to consuming the measurement services of a voltage
+ output channel, the voltage divider can act as a provider of
+ measurement services to other devices. This is particularly
+ useful in scenarios wherein an ADC has an analog frontend,
+ such as a voltage divider, and then consuming its raw value
+ isn't interesting. In this case, the voltage before the divider
+ is desired.
+ const: 1
+
output-ohms:
description:
Resistance Rout over which the output voltage is measured. See full-ohms.
HMC540S 1 dB LSB Silicon MMIC 4-Bit Digital Positive Control Attenuator, 0.1 - 8 GHz
https://www.analog.com/media/en/technical-documentation/data-sheets/hmc540s.pdf
+ LTC6373 is a 3-Bit precision instrumentation amplifier with fully differential outputs
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ltc6373.pdf
properties:
compatible:
- adi,adrf5740
- adi,hmc425a
- adi,hmc540s
+ - adi,ltc6373
vcc-supply: true
ctrl-gpios:
description:
- Must contain an array of 6 GPIO specifiers, referring to the GPIO pins
- connected to the control pins V1-V6.
- minItems: 6
+ Must contain an array of GPIO specifiers, referring to the GPIO pins
+ connected to the control pins.
+ ADRF5740 - 4 GPIO connected to D2-D5
+ HMC540S - 4 GPIO connected to V1-V4
+ HMC425A - 6 GPIO connected to V1-V6
+ LTC6373 - 3 GPIO connected to A0-A2
+ minItems: 1
maxItems: 6
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: adi,hmc425a
+ then:
+ properties:
+ ctrl-gpios:
+ minItems: 6
+ maxItems: 6
+ - if:
+ properties:
+ compatible:
+ contains:
+ anyOf:
+ - const: adi,adrf5740
+ - const: adi,hmc540s
+ then:
+ properties:
+ ctrl-gpios:
+ minItems: 4
+ maxItems: 4
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: adi,ltc6373
+ then:
+ properties:
+ ctrl-gpios:
+ minItems: 3
+ maxItems: 3
+
required:
- compatible
- ctrl-gpios
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2024 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/frequency/adi,admfm2000.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADMFM2000 Dual Microwave Down Converter
+
+maintainers:
+ - Kim Seer Paller <kimseer.paller@analog.com>
+
+description:
+ Dual microwave down converter module with input RF and LO frequency ranges
+ from 0.5 to 32 GHz and an output IF frequency range from 0.1 to 8 GHz.
+ It consists of a LNA, mixer, IF filter, DSA, and IF amplifier for each down
+ conversion path.
+
+properties:
+ compatible:
+ enum:
+ - adi,admfm2000
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ "^channel@[0-1]$":
+ type: object
+ description: Represents a channel of the device.
+
+ additionalProperties: false
+
+ properties:
+ reg:
+ description:
+ The channel number.
+ minimum: 0
+ maximum: 1
+
+ adi,mixer-mode:
+ description:
+ Enable mixer mode for the channel. It downconverts RF between 5 GHz
+ and 32 GHz to IF between 0.5 GHz and 8 GHz. If not present, the channel
+ is in direct IF mode which bypasses the mixer and downconverts RF
+ between 2 GHz and 8 GHz to IF between 0.5 GHz and 8 GHz.
+ type: boolean
+
+ switch-gpios:
+ description: |
+ GPIOs to select the RF path for the channel. The same state of CTRL-A
+ and CTRL-B GPIOs is not permitted.
+ CTRL-A CTRL-B CH1 Status CH2 Status
+ 1 0 Direct IF mode Mixer mode
+ 0 1 Mixer mode Direct IF mode
+
+ items:
+ - description: CTRL-A GPIO
+ - description: CTRL-B GPIO
+
+ attenuation-gpios:
+ description: |
+ Choice of attenuation:
+ DSA-V4 DSA-V3 DSA-V2 DSA-V1 DSA-V0
+ 1 1 1 1 1 0 dB
+ 1 1 1 1 0 -1 dB
+ 1 1 1 0 1 -2 dB
+ 1 1 0 1 1 -4 dB
+ 1 0 1 1 1 -8 dB
+ 0 1 1 1 1 -16 dB
+ 0 0 0 0 0 -31 dB
+
+ items:
+ - description: DSA-V0 GPIO
+ - description: DSA-V1 GPIO
+ - description: DSA-V2 GPIO
+ - description: DSA-V3 GPIO
+ - description: DSA-V4 GPIO
+
+ required:
+ - reg
+ - switch-gpios
+ - attenuation-gpios
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ converter {
+ compatible = "adi,admfm2000";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ switch-gpios = <&gpio 1 GPIO_ACTIVE_LOW>,
+ <&gpio 2 GPIO_ACTIVE_HIGH>;
+
+ attenuation-gpios = <&gpio 17 GPIO_ACTIVE_LOW>,
+ <&gpio 22 GPIO_ACTIVE_LOW>,
+ <&gpio 23 GPIO_ACTIVE_LOW>,
+ <&gpio 24 GPIO_ACTIVE_LOW>,
+ <&gpio 25 GPIO_ACTIVE_LOW>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ adi,mixer-mode;
+ switch-gpios = <&gpio 3 GPIO_ACTIVE_LOW>,
+ <&gpio 4 GPIO_ACTIVE_HIGH>;
+
+ attenuation-gpios = <&gpio 0 GPIO_ACTIVE_LOW>,
+ <&gpio 5 GPIO_ACTIVE_LOW>,
+ <&gpio 6 GPIO_ACTIVE_LOW>,
+ <&gpio 16 GPIO_ACTIVE_LOW>,
+ <&gpio 26 GPIO_ACTIVE_LOW>;
+ };
+ };
+...
vdd-supply: true
vddio-supply: true
+ spi-max-frequency:
+ maximum: 10000000
+
interrupts:
minItems: 1
maxItems: 2
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
examples:
- |
properties:
compatible:
contains:
- const: maxim,max30100
+ const: maxim,max30102
then:
properties:
maxim,green-led-current-microamp: false
reg:
maxItems: 1
+ interrupts:
+ maxItems: 1
+
required:
- compatible
- reg
examples:
- |
+ #include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,hdc3021", "ti,hdc3020";
reg = <0x47>;
vdd-supply = <&vcc_3v3>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <23 IRQ_TYPE_EDGE_RISING>;
};
};
- st,lsm6dsv
- st,lsm6dso16is
- items:
- - const: st,asm330lhhx
+ - enum:
+ - st,asm330lhhx
+ - st,asm330lhhxg1
- const: st,lsm6dsr
- items:
- const: st,lsm6dstx
$id: http://devicetree.org/schemas/iio/light/ams,as73211.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: AMS AS73211 JENCOLOR(R) Digital XYZ Sensor
+title: AMS AS73211 JENCOLOR(R) Digital XYZ Sensor and AMS AS7331 UV Sensor
maintainers:
- Christian Eggers <ceggers@arri.de>
description: |
- XYZ True Color Sensor with I2C Interface
+ AMS AS73211 XYZ True Color Sensor with I2C Interface
https://ams.com/documents/20143/36005/AS73211_DS000556_3-01.pdf/a65474c0-b302-c2fd-e30a-c98df87616df
+ AMS AS7331 UVA, UVB and UVC Sensor with I2C Interface
+ https://ams.com/documents/20143/9106314/AS7331_DS001047_4-00.pdf
properties:
compatible:
enum:
- ams,as73211
+ - ams,as7331
reg:
description:
required:
- compatible
- reg
+ - vdd-supply
additionalProperties: false
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/magnetometer/voltafield,af8133j.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Voltafield AF8133J magnetometer sensor
+
+maintainers:
+ - Ondřej Jirman <megi@xff.cz>
+
+properties:
+ compatible:
+ const: voltafield,af8133j
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ description:
+ A signal for active low reset input of the sensor. (optional; if not
+ used, software reset over I2C will be used instead)
+
+ avdd-supply:
+ description:
+ A regulator that provides AVDD power (Working power, usually 3.3V) to
+ the sensor.
+
+ dvdd-supply:
+ description:
+ A regulator that provides DVDD power (Digital IO power, 1.8V - AVDD)
+ to the sensor.
+
+ mount-matrix:
+ description: An optional 3x3 mounting rotation matrix.
+
+required:
+ - compatible
+ - reg
+ - avdd-supply
+ - dvdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ magnetometer@1c {
+ compatible = "voltafield,af8133j";
+ reg = <0x1c>;
+ avdd-supply = <®_dldo1>;
+ dvdd-supply = <®_dldo1>;
+ reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>;
+ };
+ };
- honeywell,transfer-function
- honeywell,pressure-triplet
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml
+
additionalProperties: false
dependentSchemas:
maintainers:
- Andreas Klinger <ak@it-klinger.de>
+ - Petre Rodan <petre.rodan@subdimension.ro>
description: |
Honeywell pressure sensor of model mprls0025pa.
- This sensor has an I2C and SPI interface. Only the I2C interface is
- implemented.
+ This sensor has an I2C and SPI interface.
There are many models with different pressure ranges available. The vendor
calls them "mpr series". All of them have the identical programming model and
differ in the pressure range, unit and transfer function.
- To support different models one need to specify the pressure range as well as
- the transfer function. Pressure range needs to be converted from its unit to
- pascal.
+ To support different models one need to specify its pressure triplet as well
+ as the transfer function.
+
+ For custom silicon chips not covered by the Honeywell MPR series datasheet,
+ the pressure values can be specified manually via honeywell,pmin-pascal and
+ honeywell,pmax-pascal.
+ The minimal range value stands for the minimum pressure and the maximum value
+ also for the maximum pressure with linear relation inside the range.
The transfer function defines the ranges of numerical values delivered by the
- sensor. The minimal range value stands for the minimum pressure and the
- maximum value also for the maximum pressure with linear relation inside the
- range.
+ sensor.
Specifications about the devices can be found at:
https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/
maxItems: 1
interrupts:
+ description:
+ Optional interrupt for indicating End-of-conversion.
+ If not present, the driver loops for a while until the received status
+ byte indicates correct measurement.
maxItems: 1
reset-gpios:
If not present the device is not reset during the probe.
maxItems: 1
- honeywell,pmin-pascal:
- description:
- Minimum pressure value the sensor can measure in pascal.
-
- honeywell,pmax-pascal:
- description:
- Maximum pressure value the sensor can measure in pascal.
-
honeywell,transfer-function:
description: |
Transfer function which defines the range of valid values delivered by the
1 - A, 10% to 90% of 2^24 (1677722 .. 15099494)
2 - B, 2.5% to 22.5% of 2^24 (419430 .. 3774874)
3 - C, 20% to 80% of 2^24 (3355443 .. 13421773)
+ enum: [1, 2, 3]
$ref: /schemas/types.yaml#/definitions/uint32
+ honeywell,pressure-triplet:
+ description: |
+ Case-sensitive five character string that defines pressure range, unit
+ and type as part of the device nomenclature. In the unlikely case of a
+ custom chip, unset and provide pmin-pascal and pmax-pascal instead.
+ enum: [0001BA, 01.6BA, 02.5BA, 0060MG, 0100MG, 0160MG, 0250MG, 0400MG,
+ 0600MG, 0001BG, 01.6BG, 02.5BG, 0100KA, 0160KA, 0250KA, 0006KG,
+ 0010KG, 0016KG, 0025KG, 0040KG, 0060KG, 0100KG, 0160KG, 0250KG,
+ 0015PA, 0025PA, 0030PA, 0001PG, 0005PG, 0015PG, 0030PG, 0300YG]
+ $ref: /schemas/types.yaml#/definitions/string
+
+ honeywell,pmin-pascal:
+ description:
+ Minimum pressure value the sensor can measure in pascal.
+
+ honeywell,pmax-pascal:
+ description:
+ Maximum pressure value the sensor can measure in pascal.
+
+ spi-max-frequency:
+ maximum: 800000
+
vdd-supply:
description: provide VDD power to the sensor.
required:
- compatible
- reg
- - honeywell,pmin-pascal
- - honeywell,pmax-pascal
- honeywell,transfer-function
- vdd-supply
+oneOf:
+ - required:
+ - honeywell,pressure-triplet
+ - required:
+ - honeywell,pmin-pascal
+ - honeywell,pmax-pascal
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml
+ - if:
+ required:
+ - honeywell,pressure-triplet
+ then:
+ properties:
+ honeywell,pmin-pascal: false
+ honeywell,pmax-pascal: false
+
additionalProperties: false
examples:
reg = <0x18>;
reset-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio3>;
- interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
- honeywell,pmin-pascal = <0>;
- honeywell,pmax-pascal = <172369>;
+ interrupts = <21 IRQ_TYPE_EDGE_RISING>;
+
+ honeywell,pressure-triplet = "0025PA";
+ honeywell,transfer-function = <1>;
+ vdd-supply = <&vcc_3v3>;
+ };
+ };
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pressure@0 {
+ compatible = "honeywell,mprls0025pa";
+ reg = <0>;
+ spi-max-frequency = <800000>;
+ reset-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <30 IRQ_TYPE_EDGE_RISING>;
+
+ honeywell,pressure-triplet = "0015PA";
honeywell,transfer-function = <1>;
vdd-supply = <&vcc_3v3>;
};
};
+...
reg:
maxItems: 1
+ vcc-supply:
+ description: provide VCC power to the sensor.
+
+ label:
+ description: Unique name to identify which device this is.
+
required:
- compatible
- reg
+ - vcc-supply
additionalProperties: false
tmp117@48 {
compatible = "ti,tmp117";
reg = <0x48>;
+ vcc-supply = <&pmic_reg_3v3>;
};
};
$ref: input.yaml#
properties:
label:
- $ref: /schemas/types.yaml#/definitions/string
description: Descriptive name of the key
linux,code: true
+++ /dev/null
-Device tree bindings for Atmel capacitive touch device, typically
-an Atmel touch sensor connected to AtmegaXX MCU running firmware
-based on Qtouch library.
-
-The node for this device must be a child of a I2C controller node, as the
-device communicates via I2C.
-
-Required properties:
-
- compatible: Must be "atmel,captouch".
- reg: The I2C slave address of the device.
- interrupts: Property describing the interrupt line the device
- is connected to. The device only has one interrupt
- source.
- linux,keycodes: Specifies an array of numeric keycode values to
- be used for reporting button presses. The array can
- contain up to 8 entries.
-
-Optional properties:
-
- autorepeat: Enables the Linux input system's autorepeat
- feature on the input device.
-
-Example:
-
- atmel-captouch@51 {
- compatible = "atmel,captouch";
- reg = <0x51>;
- interrupt-parent = <&tlmm>;
- interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
- linux,keycodes = <BTN_0>, <BTN_1>,
- <BTN_2>, <BTN_3>,
- <BTN_4>, <BTN_5>,
- <BTN_6>, <BTN_7>;
- autorepeat;
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/atmel,captouch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel capacitive touch device
+
+maintainers:
+ - Dharma balasubiramani <dharma.b@microchip.com>
+
+description:
+ Atmel capacitive touch device, typically an Atmel touch sensor connected to
+ AtmegaXX MCU running firmware based on Qtouch library.
+
+allOf:
+ - $ref: input.yaml#
+
+properties:
+ compatible:
+ const: atmel,captouch
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ linux,keycodes:
+ minItems: 1
+ maxItems: 8
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - linux,keycodes
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/input/linux-event-codes.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ touch@51 {
+ compatible = "atmel,captouch";
+ reg = <0x51>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
+ linux,keycodes = <BTN_0>, <BTN_1>,
+ <BTN_2>, <BTN_3>,
+ <BTN_4>, <BTN_5>,
+ <BTN_6>, <BTN_7>;
+ autorepeat;
+ };
+ };
+++ /dev/null
-* Dialog DA9061/62/63 OnKey Module
-
-This module is part of the DA9061/DA9062/DA9063. For more details about entire
-DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt
-For DA9063 see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml
-
-This module provides the KEY_POWER event.
-
-Required properties:
-
-- compatible: should be one of the following valid compatible string lines:
- "dlg,da9061-onkey", "dlg,da9062-onkey"
- "dlg,da9062-onkey"
- "dlg,da9063-onkey"
-
-Optional properties:
-
-- dlg,disable-key-power : Disable power-down using a long key-press. If this
- entry exists the OnKey driver will remove support for the KEY_POWER key
- press when triggered using a long press of the OnKey.
-
-Example: DA9063
-
- pmic0: da9063@58 {
- onkey {
- compatible = "dlg,da9063-onkey";
- dlg,disable-key-power;
- };
- };
-
-Example: DA9062
-
- pmic0: da9062@58 {
- onkey {
- compatible = "dlg,da9062-onkey";
- dlg,disable-key-power;
- };
- };
-
-Example: DA9061 using a fall-back compatible for the DA9062 onkey driver
-
- pmic0: da9061@58 {
- onkey {
- compatible = "dlg,da9061-onkey", "dlg,da9062-onkey";
- dlg,disable-key-power;
- };
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/dlg,da9062-onkey.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Dialog DA9061/62/63 OnKey Module
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ This module is part of the DA9061/DA9062/DA9063. For more details about entire
+ DA906{1,2,3} chips see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml
+
+ This module provides the KEY_POWER event.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - dlg,da9062-onkey
+ - dlg,da9063-onkey
+ - items:
+ - const: dlg,da9061-onkey
+ - const: dlg,da9062-onkey
+
+ dlg,disable-key-power:
+ type: boolean
+ description:
+ Disable power-down using a long key-press. If this entry exists
+ the OnKey driver will remove support for the KEY_POWER key press
+ when triggered using a long press of the OnKey.
+
+required:
+ - compatible
+
+additionalProperties: false
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/samsung,s3c6410-keypad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series Keypad Controller
+
+description:
+ Samsung SoC Keypad controller is used to interface a SoC with a matrix-type
+ keypad device. The keypad controller supports multiple row and column lines.
+ A key can be placed at each intersection of a unique row and a unique column.
+ The keypad controller can sense a key-press and key-release and report the
+ event using a interrupt to the cpu.
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - samsung,s3c6410-keypad
+ - samsung,s5pv210-keypad
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: keypad
+
+ interrupts:
+ maxItems: 1
+
+ wakeup-source: true
+
+ linux,input-no-autorepeat:
+ type: boolean
+ description:
+ Do no enable autorepeat feature.
+
+ linux,input-wakeup:
+ type: boolean
+ deprecated: true
+
+ samsung,keypad-num-columns:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of column lines connected to the keypad controller.
+
+ samsung,keypad-num-rows:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of row lines connected to the keypad controller.
+
+patternProperties:
+ '^key-[0-9a-z]+$':
+ type: object
+ $ref: input.yaml#
+ additionalProperties: false
+ description:
+ Each key connected to the keypad controller is represented as a child
+ node to the keypad controller device node.
+
+ properties:
+ keypad,column:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The column number to which the key is connected.
+
+ keypad,row:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The row number to which the key is connected.
+
+ linux,code: true
+
+ required:
+ - keypad,column
+ - keypad,row
+ - linux,code
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - samsung,keypad-num-columns
+ - samsung,keypad-num-rows
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos4.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ keypad@100a0000 {
+ compatible = "samsung,s5pv210-keypad";
+ reg = <0x100a0000 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_KEYIF>;
+ clock-names = "keypad";
+
+ samsung,keypad-num-rows = <2>;
+ samsung,keypad-num-columns = <8>;
+ linux,input-no-autorepeat;
+ wakeup-source;
+
+ key-1 {
+ keypad,row = <0>;
+ keypad,column = <3>;
+ linux,code = <2>;
+ };
+
+ key-2 {
+ keypad,row = <0>;
+ keypad,column = <4>;
+ linux,code = <3>;
+ };
+ };
+++ /dev/null
-* Samsung's Keypad Controller device tree bindings
-
-Samsung's Keypad controller is used to interface a SoC with a matrix-type
-keypad device. The keypad controller supports multiple row and column lines.
-A key can be placed at each intersection of a unique row and a unique column.
-The keypad controller can sense a key-press and key-release and report the
-event using a interrupt to the cpu.
-
-Required SoC Specific Properties:
-- compatible: should be one of the following
- - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad
- controller.
- - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad
- controller.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- interrupts: The interrupt number to the cpu.
-
-Required Board Specific Properties:
-- samsung,keypad-num-rows: Number of row lines connected to the keypad
- controller.
-
-- samsung,keypad-num-columns: Number of column lines connected to the
- keypad controller.
-
-- Keys represented as child nodes: Each key connected to the keypad
- controller is represented as a child node to the keypad controller
- device node and should include the following properties.
- - keypad,row: the row number to which the key is connected.
- - keypad,column: the column number to which the key is connected.
- - linux,code: the key-code to be reported when the key is pressed
- and released.
-
-- pinctrl-0: Should specify pin control groups used for this controller.
-- pinctrl-names: Should contain only one value - "default".
-
-Optional Properties:
-- wakeup-source: use any event on keypad as wakeup event.
- (Legacy property supported: "linux,input-wakeup")
-
-Optional Properties specific to linux:
-- linux,keypad-no-autorepeat: do no enable autorepeat feature.
-
-
-Example:
- keypad@100a0000 {
- compatible = "samsung,s5pv210-keypad";
- reg = <0x100A0000 0x100>;
- interrupts = <173>;
- samsung,keypad-num-rows = <2>;
- samsung,keypad-num-columns = <8>;
- linux,input-no-autorepeat;
- wakeup-source;
-
- pinctrl-names = "default";
- pinctrl-0 = <&keypad_rows &keypad_columns>;
-
- key_1 {
- keypad,row = <0>;
- keypad,column = <3>;
- linux,code = <2>;
- };
-
- key_2 {
- keypad,row = <0>;
- keypad,column = <4>;
- linux,code = <3>;
- };
-
- key_3 {
- keypad,row = <0>;
- keypad,column = <5>;
- linux,code = <4>;
- };
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/fsl,imx6ul-tsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6UL Touch Controller
+
+maintainers:
+ - Haibo Chen <haibo.chen@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+
+properties:
+ compatible:
+ const: fsl,imx6ul-tsc
+
+ reg:
+ items:
+ - description: touch controller address
+ - description: ADC2 address
+
+ interrupts:
+ items:
+ - description: touch controller address
+ - description: ADC2 address
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: tsc
+ - const: adc
+
+ xnur-gpios:
+ maxItems: 1
+ description:
+ The X- gpio this controller connect to. This xnur-gpio returns to
+ low once the finger leave the touch screen (The last touch event
+ the touch controller capture).
+
+ measure-delay-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The value of measure delay time. Before X-axis or Y-axis measurement,
+ the screen need some time before even potential distribution ready.
+ default: 0xffff
+ minimum: 0
+ maximum: 0xffffff
+
+ pre-charge-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The touch screen need some time to precharge.
+ default: 0xfff
+ minimum: 0
+ maximum: 0xffffffff
+
+ touchscreen-average-samples:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Number of data samples which are averaged for each read.
+ enum: [ 1, 4, 8, 16, 32 ]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - xnur-gpios
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/imx6ul-clock.h>
+ #include <dt-bindings/gpio/gpio.h>
+ touchscreen@2040000 {
+ compatible = "fsl,imx6ul-tsc";
+ reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_IPG>,
+ <&clks IMX6UL_CLK_ADC2>;
+ clock-names = "tsc", "adc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc>;
+ xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ measure-delay-time = <0xfff>;
+ pre-charge-time = <0xffff>;
+ touchscreen-average-samples = <32>;
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/goodix,gt9916.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Goodix Berlin series touchscreen controller
+
+description: The Goodix Berlin series of touchscreen controllers
+ be connected to either I2C or SPI buses.
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+allOf:
+ - $ref: touchscreen.yaml#
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ enum:
+ - goodix,gt9916
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ avdd-supply:
+ description: Analog power supply regulator on AVDD pin
+
+ vddio-supply:
+ description: power supply regulator on VDDIO pin
+
+ spi-max-frequency: true
+ touchscreen-inverted-x: true
+ touchscreen-inverted-y: true
+ touchscreen-size-x: true
+ touchscreen-size-y: true
+ touchscreen-swapped-x-y: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - avdd-supply
+ - touchscreen-size-x
+ - touchscreen-size-y
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ touchscreen@5d {
+ compatible = "goodix,gt9916";
+ reg = <0x5d>;
+ interrupt-parent = <&gpio>;
+ interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ avdd-supply = <&ts_avdd>;
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <768>;
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <1>;
+ cs-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
+ touchscreen@0 {
+ compatible = "goodix,gt9916";
+ reg = <0>;
+ interrupt-parent = <&gpio>;
+ interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ avdd-supply = <&ts_avdd>;
+ spi-max-frequency = <1000000>;
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <768>;
+ };
+ };
+
+...
maxItems: 1
irq-gpios:
- description: GPIO pin used for IRQ. The driver uses the interrupt gpio pin
- as output to reset the device.
+ description: GPIO pin used for IRQ input. Additionally, this line is
+ sampled by the device on reset deassertion to select the I2C client
+ address, thus it can be driven by the host during the reset sequence.
maxItems: 1
reset-gpios:
maintainers:
- Markuss Broks <markuss.broks@gmail.com>
-allOf:
- - $ref: touchscreen.yaml#
-
properties:
$nodename:
pattern: "^touchscreen@[0-9a-f]+$"
compatible:
enum:
+ - imagis,ist3032c
+ - imagis,ist3038b
- imagis,ist3038c
reg:
vddio-supply:
description: Power supply regulator for the I2C bus
+ linux,keycodes:
+ description: Keycodes for the touch keys
+ maxItems: 5
+
touchscreen-size-x: true
touchscreen-size-y: true
touchscreen-fuzz-x: true
additionalProperties: false
+allOf:
+ - $ref: touchscreen.yaml#
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: imagis,ist3032c
+ then:
+ properties:
+ linux,keycodes: false
+
required:
- compatible
- reg
+++ /dev/null
-* Freescale i.MX6UL Touch Controller
-
-Required properties:
-- compatible: must be "fsl,imx6ul-tsc".
-- reg: this touch controller address and the ADC2 address.
-- interrupts: the interrupt of this touch controller and ADC2.
-- clocks: the root clock of touch controller and ADC2.
-- clock-names; must be "tsc" and "adc".
-- xnur-gpio: the X- gpio this controller connect to.
- This xnur-gpio returns to low once the finger leave the touch screen (The
- last touch event the touch controller capture).
-
-Optional properties:
-- measure-delay-time: the value of measure delay time.
- Before X-axis or Y-axis measurement, the screen need some time before
- even potential distribution ready.
- This value depends on the touch screen.
-- pre-charge-time: the touch screen need some time to precharge.
- This value depends on the touch screen.
-- touchscreen-average-samples: Number of data samples which are averaged for
- each read. Valid values are 1, 4, 8, 16 and 32.
-
-Example:
- tsc: tsc@2040000 {
- compatible = "fsl,imx6ul-tsc";
- reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_IPG>,
- <&clks IMX6UL_CLK_ADC2>;
- clock-names = "tsc", "adc";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tsc>;
- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
- measure-delay-time = <0xfff>;
- pre-charge-time = <0xffff>;
- touchscreen-average-samples = <32>;
- };
pattern: "^touchscreen(@.*)?$"
compatible:
- items:
+ oneOf:
- enum:
- melfas,mms114
- melfas,mms134s
- melfas,mms136
- melfas,mms152
- melfas,mms345l
+ - items:
+ - enum:
+ - melfas,mms252
+ - const: melfas,mms114
reg:
description: I2C address
maxItems: 1
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description: >
File basename for board specific firmware
compatible:
enum:
+ - qcom,msm8909-bimc
+ - qcom,msm8909-pcnoc
+ - qcom,msm8909-snoc
- qcom,msm8916-bimc
- qcom,msm8916-pcnoc
- qcom,msm8916-snoc
maintainers:
- Georgi Djakov <georgi.djakov@linaro.org>
- - Odelu Kukatla <okukatla@codeaurora.org>
+ - Odelu Kukatla <quic_okukatla@quicinc.com>
description: |
RPMh interconnect providers support system bandwidth requirements through
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,sm7150-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect on SM7150
+
+maintainers:
+ - Danila Tikhonov <danila@jiaxyga.com>
+
+description: |
+ RPMh interconnect providers support system bandwidth requirements through
+ RPMh hardware accelerators known as Bus Clock Manager (BCM).
+
+ See also:: include/dt-bindings/interconnect/qcom,sm7150-rpmh.h
+
+allOf:
+ - $ref: qcom,rpmh-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm7150-aggre1-noc
+ - qcom,sm7150-aggre2-noc
+ - qcom,sm7150-compute-noc
+ - qcom,sm7150-config-noc
+ - qcom,sm7150-dc-noc
+ - qcom,sm7150-gem-noc
+ - qcom,sm7150-mc-virt
+ - qcom,sm7150-mmss-noc
+ - qcom,sm7150-system-noc
+
+ reg:
+ maxItems: 1
+
+# Child node's properties
+patternProperties:
+ '^interconnect-[0-9]+$':
+ type: object
+ description:
+ The interconnect providers do not have a separate QoS register space,
+ but share parent's space.
+
+ allOf:
+ - $ref: qcom,rpmh-common.yaml#
+
+ properties:
+ compatible:
+ enum:
+ - qcom,sm7150-camnoc-virt
+
+ required:
+ - compatible
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mc_virt: interconnect@1380000 {
+ compatible = "qcom,sm7150-mc-virt";
+ reg = <0x01380000 0x40000>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1620000 {
+ compatible = "qcom,sm7150-system-noc";
+ reg = <0x01620000 0x40000>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ camnoc_virt: interconnect-0 {
+ compatible = "qcom,sm7150-camnoc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+ };
- amlogic,meson-a1-gpio-intc
- amlogic,meson-s4-gpio-intc
- amlogic,c3-gpio-intc
+ - amlogic,t7-gpio-intc
- const: amlogic,meson-gpio-intc
reg:
+++ /dev/null
-* Advanced Interrupt Controller (AIC)
-
-Required properties:
-- compatible: Should be:
- - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
- "sama5d3" or "sama5d4"
- - "microchip,<chip>-aic" where <chip> can be "sam9x60"
-
-- interrupt-controller: Identifies the node as an interrupt controller.
-- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
- The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
- The second cell is used to specify flags:
- bits[3:0] trigger type and level flags:
- 1 = low-to-high edge triggered.
- 2 = high-to-low edge triggered.
- 4 = active high level-sensitive.
- 8 = active low level-sensitive.
- Valid combinations are 1, 2, 3, 4, 8.
- Default flag for internal sources should be set to 4 (active high).
- The third cell is used to specify the irq priority from 0 (lowest) to 7
- (highest).
-- reg: Should contain AIC registers location and length
-- atmel,external-irqs: u32 array of external irqs.
-
-Examples:
- /*
- * AIC
- */
- aic: interrupt-controller@fffff000 {
- compatible = "atmel,at91rm9200-aic";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = <0xfffff000 0x200>;
- };
-
- /*
- * An interrupt generating device that is wired to an AIC.
- */
- dma: dma-controller@ffffec00 {
- compatible = "atmel,at91sam9g45-dma";
- reg = <0xffffec00 0x200>;
- interrupts = <21 4 5>;
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Advanced Interrupt Controller (AIC)
+
+maintainers:
+ - Nicolas Ferre <nicolas.ferre@microchip.com>
+ - Dharma balasubiramani <dharma.b@microchip.com>
+
+description:
+ The Advanced Interrupt Controller (AIC) is an 8-level priority, individually
+ maskable, vectored interrupt controller providing handling of up to one
+ hundred and twenty-eight interrupt sources.
+
+properties:
+ compatible:
+ enum:
+ - atmel,at91rm9200-aic
+ - atmel,sama5d2-aic
+ - atmel,sama5d3-aic
+ - atmel,sama5d4-aic
+ - microchip,sam9x60-aic
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 3
+ description: |
+ The 1st cell is the IRQ number (Peripheral IDentifier on datasheet).
+ The 2nd cell specifies flags:
+ bits[3:0] trigger type and level flags:
+ 1 = low-to-high edge triggered.
+ 2 = high-to-low edge triggered.
+ 4 = active high level-sensitive.
+ 8 = active low level-sensitive.
+ Valid combinations: 1, 2, 3, 4, 8.
+ Default for internal sources: 4 (active high).
+ The 3rd cell specifies irq priority from 0 (lowest) to 7 (highest).
+
+ interrupts:
+ maxItems: 1
+
+ atmel,external-irqs:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: u32 array of external irqs.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: atmel,at91rm9200-aic
+ then:
+ properties:
+ atmel,external-irqs:
+ minItems: 1
+ maxItems: 7
+ else:
+ properties:
+ atmel,external-irqs:
+ minItems: 1
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - "#interrupt-cells"
+ - atmel,external-irqs
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ interrupt-controller@fffff000 {
+ compatible = "atmel,at91rm9200-aic";
+ reg = <0xfffff000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ atmel,external-irqs = <31>;
+ };
+...
clock-names:
const: ipg
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mt6577-sysirq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek sysirq
+
+description:
+ MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
+ interrupt.
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: mediatek,mt6577-sysirq
+ - items:
+ - enum:
+ - mediatek,mt2701-sysirq
+ - mediatek,mt2712-sysirq
+ - mediatek,mt6580-sysirq
+ - mediatek,mt6582-sysirq
+ - mediatek,mt6589-sysirq
+ - mediatek,mt6592-sysirq
+ - mediatek,mt6755-sysirq
+ - mediatek,mt6765-sysirq
+ - mediatek,mt6779-sysirq
+ - mediatek,mt6795-sysirq
+ - mediatek,mt6797-sysirq
+ - mediatek,mt7622-sysirq
+ - mediatek,mt7623-sysirq
+ - mediatek,mt7629-sysirq
+ - mediatek,mt8127-sysirq
+ - mediatek,mt8135-sysirq
+ - mediatek,mt8173-sysirq
+ - mediatek,mt8183-sysirq
+ - mediatek,mt8365-sysirq
+ - mediatek,mt8516-sysirq
+ - const: mediatek,mt6577-sysirq
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ $ref: "arm,gic.yaml#/properties/#interrupt-cells"
+
+required:
+ - reg
+ - interrupt-controller
+ - "#interrupt-cells"
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt6797-sysirq
+ then:
+ properties:
+ reg:
+ minItems: 2
+ else:
+ properties:
+ reg:
+ maxItems: 1
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ interrupt-controller@10200620 {
+ compatible = "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq";
+ reg = <0x10220620 0x20>,
+ <0x10220690 0x10>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+++ /dev/null
-MediaTek sysirq
-
-MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
-interrupt.
-
-Required properties:
-- compatible: should be
- "mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
- "mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183
- "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
- "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
- "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
- "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
- "mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623
- "mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
- "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
- "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
- "mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq": for MT6779
- "mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765
- "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
- "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
- "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
- "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
- "mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
- "mediatek,mt6577-sysirq": for MT6577
- "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
- "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
- "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
-- reg: Physical base address of the intpol registers and length of memory
- mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others
- need 1.
-
-Example:
- sysirq: intpol-controller@10200620 {
- compatible = "mediatek,mt6797-sysirq",
- "mediatek,mt6577-sysirq";
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- reg = <0 0x10220620 0 0x20>,
- <0 0x10220690 0 0x10>;
- };
maxItems: 1
interrupts:
- minItems: 41
+ minItems: 45
items:
- description: NMI interrupt
- description: IRQ0 interrupt
- description: GPIO interrupt, TINT30
- description: GPIO interrupt, TINT31
- description: Bus error interrupt
+ - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt
+ - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt
+ - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt
+ - description: ECCRAM1 1bit error interrupt
+ - description: ECCRAM1 2bit error interrupt
+ - description: ECCRAM1 error overflow interrupt
interrupt-names:
- minItems: 41
+ minItems: 45
items:
- const: nmi
- const: irq0
- const: tint30
- const: tint31
- const: bus-err
+ - const: ec7tie1-0
+ - const: ec7tie2-0
+ - const: ec7tiovf-0
+ - const: ec7tie1-1
+ - const: ec7tie2-1
+ - const: ec7tiovf-1
clocks:
maxItems: 2
- interrupt-controller
- reg
- interrupts
+ - interrupt-names
- clocks
- clock-names
- power-domains
compatible:
contains:
enum:
- - renesas,r9a07g043u-irqc
- renesas,r9a08g045-irqc
then:
properties:
interrupts:
- minItems: 42
+ maxItems: 45
interrupt-names:
- minItems: 42
- required:
- - interrupt-names
+ maxItems: 45
+ else:
+ properties:
+ interrupts:
+ minItems: 48
+ interrupt-names:
+ minItems: 48
unevaluatedProperties: false
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "nmi",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
- "tint28", "tint29", "tint30", "tint31";
+ "tint28", "tint29", "tint30", "tint31",
+ "bus-err", "ec7tie1-0", "ec7tie2-0",
+ "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
+ "ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
clock-names = "clk", "pclk";
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive External Interrupt Controller
+
+description:
+ StarFive SoC JH8100 contain a external interrupt controller. It can be used
+ to handle high-level input interrupt signals. It also send the output
+ interrupt signal to RISC-V PLIC.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh8100-intc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: APB clock for the interrupt controller
+ maxItems: 1
+
+ resets:
+ description: APB reset for the interrupt controller
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller@12260000 {
+ compatible = "starfive,jh8100-intc";
+ reg = <0x12260000 0x10000>;
+ clocks = <&syscrg_ne 76>;
+ resets = <&syscrg_ne 13>;
+ interrupts = <45>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
- description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
items:
- enum:
+ - qcom,qcm2290-smmu-500
- qcom,sa8775p-smmu-500
- qcom,sc7280-smmu-500
- qcom,sc8280xp-smmu-500
- qcom,sm8350-smmu-500
- qcom,sm8450-smmu-500
- qcom,sm8550-smmu-500
+ - qcom,sm8650-smmu-500
- const: qcom,adreno-smmu
- const: qcom,smmu-500
- const: arm,mmu-500
compatible:
items:
- enum:
+ - qcom,qcm2290-smmu-500
- qcom,sm6115-smmu-500
- qcom,sm6125-smmu-500
- const: qcom,adreno-smmu
- if:
properties:
compatible:
- const: qcom,sm8450-smmu-500
+ items:
+ - const: qcom,sm8450-smmu-500
+ - const: qcom,adreno-smmu
+ - const: qcom,smmu-500
+ - const: arm,mmu-500
+
then:
properties:
clock-names:
- if:
properties:
compatible:
- const: qcom,sm8550-smmu-500
+ items:
+ - enum:
+ - qcom,sm8550-smmu-500
+ - qcom,sm8650-smmu-500
+ - const: qcom,adreno-smmu
+ - const: qcom,smmu-500
+ - const: arm,mmu-500
then:
properties:
clock-names:
- cavium,smmu-v2
- marvell,ap806-smmu-500
- nvidia,smmu-500
- - qcom,qcm2290-smmu-500
- qcom,qdu1000-smmu-500
- qcom,sc7180-smmu-500
- qcom,sc8180x-smmu-500
- qcom,sdx65-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm6375-smmu-500
- - qcom,sm8650-smmu-500
- qcom,x1e80100-smmu-500
then:
properties:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/backlight/kinetic,ktd2801.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kinetic Technologies KTD2801 one-wire backlight
+
+maintainers:
+ - Duje Mihanović <duje.mihanovic@skole.hr>
+
+description: |
+ The Kinetic Technologies KTD2801 is a LED backlight driver controlled
+ by a single GPIO line. The driver can be controlled with a PWM signal
+ or by pulsing the GPIO line to set the backlight level. This is called
+ "ExpressWire".
+
+allOf:
+ - $ref: common.yaml#
+
+properties:
+ compatible:
+ const: kinetic,ktd2801
+
+ ctrl-gpios:
+ maxItems: 1
+
+ default-brightness: true
+ max-brightness: true
+
+required:
+ - compatible
+ - ctrl-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ backlight {
+ compatible = "kinetic,ktd2801";
+ ctrl-gpios = <&gpio 97 GPIO_ACTIVE_HIGH>;
+ max-brightness = <210>;
+ default-brightness = <100>;
+ };
title: Qualcomm Technologies, Inc. WLED driver
maintainers:
- - Bjorn Andersson <bjorn.andersson@linaro.org>
- - Kiran Gunda <kgunda@codeaurora.org>
+ - Bjorn Andersson <andersson@kernel.org>
+ - Kiran Gunda <quic_kgunda@quicinc.com>
description: |
WLED (White Light Emitting Diode) driver is used for controlling display
#trigger-source-cells property in the source node.
$ref: /schemas/types.yaml#/definitions/phandle-array
+ active-low:
+ type: boolean
+ description:
+ Makes LED active low. To turn the LED ON, line needs to be
+ set to low voltage instead of high.
+
+ inactive-high-impedance:
+ type: boolean
+ description:
+ Set LED to high-impedance mode to turn the LED OFF. LED might also
+ describe this mode as tristate.
+
# Required properties for flash LED child nodes:
flash-max-microamp:
description:
maxItems: 1
description: LED pin number
- active-low:
- type: boolean
- description: Makes LED active low
-
required:
- reg
- maximum: 23
description: LED pin number (only LEDs 0 to 23 are valid).
- active-low:
- type: boolean
- description: Makes LED active low.
-
brcm,hardware-controlled:
type: boolean
description: Makes this LED hardware controlled.
LED sub-node optional properties:
- label : see Documentation/devicetree/bindings/leds/common.txt
- - active-low : Boolean, makes LED active low.
- Default : false
- default-state : see
Documentation/devicetree/bindings/leds/common.txt
- linux,default-trigger : see
pwm-names: true
- active-low:
- description: For PWMs where the LED is wired to supply rather than ground.
- type: boolean
+ active-low: true
color: true
Maximum brightness possible for the LED
$ref: /schemas/types.yaml#/definitions/uint32
- active-low:
- description:
- For PWMs where the LED is wired to supply rather than ground.
- type: boolean
-
required:
- pwms
- max-brightness
description: >
The Qualcomm Light Pulse Generator consists of three different hardware blocks;
- a ramp generator with lookup table, the light pulse generator and a three
+ a ramp generator with lookup table (LUT), the light pulse generator and a three
channel current sink. These blocks are found in a wide range of Qualcomm PMICs.
properties:
- description: dtest line to attach
- description: flags for the attachment
+ nvmem:
+ description: >
+ This property is required for PMICs that supports PPG, which is when a
+ PMIC stores LPG per-channel data and pattern LUT in SDAM modules instead
+ of in a LUT peripheral. For PMICs, such as PM8350C, per-channel data
+ and pattern LUT is separated into 2 SDAM modules. In that case, phandles
+ to both SDAM modules need to be specified.
+ minItems: 1
+ maxItems: 2
+
+ nvmem-names:
+ minItems: 1
+ items:
+ - const: lpg_chan_sdam
+ - const: lut_sdam
+
+ qcom,pbs:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: >
+ Phandle of the Qualcomm Programmable Boot Sequencer node (PBS).
+ PBS node is used to trigger LPG pattern sequences for PMICs that support
+ single SDAM PPG.
+
multi-led:
type: object
$ref: leds-class-multicolor.yaml#
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pm660l-lpg
+ - qcom,pm8150b-lpg
+ - qcom,pm8150l-lpg
+ - qcom,pm8916-pwm
+ - qcom,pm8941-lpg
+ - qcom,pm8994-lpg
+ - qcom,pmc8180c-lpg
+ - qcom,pmi8994-lpg
+ - qcom,pmi8998-lpg
+ - qcom,pmk8550-pwm
+ then:
+ properties:
+ nvmem: false
+ nvmem-names: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,pmi632-lpg
+ then:
+ properties:
+ nvmem:
+ maxItems: 1
+ nvmem-names:
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pm8350c-pwm
+ then:
+ properties:
+ nvmem:
+ minItems: 2
+ nvmem-names:
+ minItems: 2
+
examples:
- |
#include <dt-bindings/leds/common.h>
compatible = "qcom,pm8916-pwm";
#pwm-cells = <2>;
};
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ led-controller {
+ compatible = "qcom,pmi632-lpg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pwm-cells = <2>;
+ nvmem-names = "lpg_chan_sdam";
+ nvmem = <&pmi632_sdam_7>;
+ qcom,pbs = <&pmi632_pbs_client3>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ label = "red";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "green";
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ label = "blue";
+ };
+ };
+
...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/onnn,ncp5623.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ON Semiconductor NCP5623 multi-LED Driver
+
+maintainers:
+ - Abdel Alkuor <alkuor@gmail.com>
+
+description:
+ NCP5623 Triple Output I2C Controlled LED Driver.
+ https://www.onsemi.com/pdf/datasheet/ncp5623-d.pdf
+
+properties:
+ compatible:
+ enum:
+ - onnn,ncp5623
+
+ reg:
+ const: 0x38
+
+ multi-led:
+ type: object
+ $ref: leds-class-multicolor.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^led@[0-2]$":
+ type: object
+ $ref: common.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 2
+
+ required:
+ - reg
+ - color
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+
+required:
+ - compatible
+ - reg
+ - multi-led
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led-controller@38 {
+ compatible = "onnn,ncp5623";
+ reg = <0x38>;
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+ };
+ };
- const: fsl,imx8ulp-mu
- const: fsl,imx8-mu-scu
- const: fsl,imx8-mu-seco
- - const: fsl,imx93-mu-s4
- const: fsl,imx8ulp-mu-s4
+ - const: fsl,imx93-mu-s4
+ - const: fsl,imx95-mu
+ - const: fsl,imx95-mu-ele
+ - const: fsl,imx95-mu-v2x
- items:
- const: fsl,imx93-mu
- const: fsl,imx8ulp-mu
power-domains:
maxItems: 1
+ ranges: true
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+patternProperties:
+ "^sram@[a-f0-9]+":
+ $ref: /schemas/sram/sram.yaml#
+ unevaluatedProperties: false
+
required:
- compatible
- reg
required:
- interrupt-names
+ - if:
+ not:
+ properties:
+ compatible:
+ const: fsl,imx95-mu
+ then:
+ patternProperties:
+ "^sram@[a-f0-9]+": false
+
additionalProperties: false
examples:
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mailbox@445b0000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x445b0000 0x10000>;
+ ranges;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #mbox-cells = <2>;
+
+ sram@445b1000 {
+ compatible = "mmio-sram";
+ reg = <0x445b1000 0x400>;
+ ranges = <0x0 0x445b1000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ scmi-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
+
+ scmi-sram-section@80 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x80 0x80>;
+ };
+ };
+ };
properties:
port@0:
- $ref: /schemas/graph.yaml#/$defs/port-base
+ $ref: /schemas/graph.yaml#/properties/port
description: Analog input port
properties:
properties:
compatible:
- enum:
- - mediatek,mt8173-vcodec-enc-vp8
- - mediatek,mt8173-vcodec-enc
- - mediatek,mt8183-vcodec-enc
- - mediatek,mt8188-vcodec-enc
- - mediatek,mt8192-vcodec-enc
- - mediatek,mt8195-vcodec-enc
-
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt8173-vcodec-enc-vp8
+ - mediatek,mt8173-vcodec-enc
+ - mediatek,mt8183-vcodec-enc
+ - mediatek,mt8188-vcodec-enc
+ - mediatek,mt8192-vcodec-enc
+ - mediatek,mt8195-vcodec-enc
+ - items:
+ - const: mediatek,mt8186-vcodec-enc
+ - const: mediatek,mt8183-vcodec-enc
reg:
maxItems: 1
properties:
compatible:
enum:
- - mediatek,mt8173-vcodec-enc
- - mediatek,mt8188-vcodec-enc
- - mediatek,mt8192-vcodec-enc
- - mediatek,mt8195-vcodec-enc
+ - mediatek,mt8173-vcodec-enc-vp8
then:
properties:
maxItems: 1
clock-names:
items:
- - const: venc_sel
- else: # for vp8 hw encoder
+ - const: venc_lt_sel
+ else:
properties:
clock:
items:
maxItems: 1
clock-names:
items:
- - const: venc_lt_sel
+ - const: venc_sel
additionalProperties: false
maxItems: 1
iommus:
- maxItems: 2
+ minItems: 2
+ maxItems: 4
description: |
Points to the respective IOMMU block with master port as argument, see
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
properties:
compatible:
enum:
+ - fsl,imx8mp-isp
- rockchip,px30-cif-isp
- rockchip,rk3399-cif-isp
minItems: 3
items:
# isp0 and isp1
- - description: ISP clock
- - description: ISP AXI clock
- - description: ISP AHB clock
+ - description: ISP clock (for imx8mp, clk)
+ - description: ISP AXI clock (for imx8mp, m_hclk)
+ - description: ISP AHB clock (for imx8mp, hclk)
# only for isp1
- description: ISP Pixel clock
# only for isp1
- const: pclk
+ fsl,blk-ctrl:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+ description:
+ A phandle to the media block control for the ISP, followed by a cell
+ containing the index of the gasket.
+
iommus:
maxItems: 1
- interrupts
- clocks
- clock-names
- - iommus
- - phys
- - phy-names
- power-domains
- ports
required:
- interrupt-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mp-isp
+ then:
+ properties:
+ iommus: false
+ phys: false
+ phy-names: false
+ required:
+ - fsl,blk-ctrl
+ else:
+ properties:
+ fsl,blk-ctrl: false
+ required:
+ - iommus
+ - phys
+ - phy-names
+
additionalProperties: false
examples:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/st,stm32mp25-video-codec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32MP25 VDEC video decoder & VENC video encoder
+
+maintainers:
+ - Hugues Fruchet <hugues.fruchet@foss.st.com>
+
+description:
+ The STMicroelectronics STM32MP25 SOCs embeds a VDEC video hardware
+ decoder peripheral based on Verisilicon VC8000NanoD IP (former Hantro G1)
+ and a VENC video hardware encoder peripheral based on Verisilicon
+ VC8000NanoE IP (former Hantro H1).
+
+properties:
+ compatible:
+ enum:
+ - st,stm32mp25-vdec
+ - st,stm32mp25-venc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ video-codec@580d0000 {
+ compatible = "st,stm32mp25-vdec";
+ reg = <0x580d0000 0x3c8>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ck_icn_p_vdec>;
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX WEIM Bus Peripheral Nodes
+
+maintainers:
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+
+description:
+ This binding is meant for the child nodes of the WEIM node. The node
+ represents any device connected to the WEIM bus. It may be a Flash chip,
+ RAM chip or Ethernet controller, etc. These properties are meant for
+ configuring the WEIM settings/timings and will accompany the bindings
+ supported by the respective device.
+
+properties:
+ reg: true
+
+ fsl,weim-cs-timing:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ Timing values for the child node.
+ minItems: 2
+ maxItems: 6
+
+# the WEIM child will have its own native properties
+additionalProperties: true
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX Wireless External Interface Module (WEIM)
+
+maintainers:
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+
+description:
+ The term "wireless" does not imply that the WEIM is literally an interface
+ without wires. It simply means that this module was originally designed for
+ wireless and mobile applications that use low-power technology. The actual
+ devices are instantiated from the child nodes of a WEIM node.
+
+properties:
+ $nodename:
+ pattern: "^memory-controller@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - enum:
+ - fsl,imx1-weim
+ - fsl,imx27-weim
+ - fsl,imx50-weim
+ - fsl,imx51-weim
+ - fsl,imx6q-weim
+ - items:
+ - enum:
+ - fsl,imx31-weim
+ - fsl,imx35-weim
+ - const: fsl,imx27-weim
+ - items:
+ - enum:
+ - fsl,imx6sx-weim
+ - fsl,imx6ul-weim
+ - const: fsl,imx6q-weim
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ ranges: true
+
+ fsl,weim-cs-gpr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ Phandle to the system General Purpose Register controller that contains
+ WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
+ should be set up as one of the following 4 possible values depending on
+ the CS space configuration.
+
+ IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
+ ---------------------------------------------
+ 05 128M 0M 0M 0M
+ 033 64M 64M 0M 0M
+ 0113 64M 32M 32M 0M
+ 01111 32M 32M 32M 32M
+
+ In case that the property is absent, the reset value or what bootloader
+ sets up in IOMUXC_GPR1[11:0] will be used.
+
+ fsl,burst-clk-enable:
+ type: boolean
+ description:
+ The presence of this property indicates that the weim bus should operate
+ in Burst Clock Mode.
+
+ fsl,continuous-burst-clk:
+ type: boolean
+ description:
+ Make Burst Clock to output continuous clock. Without this option Burst
+ Clock will output clock only when necessary.
+
+patternProperties:
+ "^.*@[0-7],[0-9a-f]+$":
+ type: object
+ description: Devices attached to chip selects are represented as subnodes.
+ $ref: fsl,imx-weim-peripherals.yaml
+ additionalProperties: true
+ required:
+ - fsl,weim-cs-timing
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ enum:
+ - fsl,imx50-weim
+ - fsl,imx6q-weim
+ then:
+ properties:
+ fsl,weim-cs-gpr: false
+ fsl,burst-clk-enable: false
+ - if:
+ not:
+ required:
+ - fsl,burst-clk-enable
+ then:
+ properties:
+ fsl,continuous-burst-clk: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx1-weim
+ then:
+ patternProperties:
+ "^.*@[0-7],[0-9a-f]+$":
+ properties:
+ fsl,weim-cs-timing:
+ items:
+ items:
+ - description: CSxU
+ - description: CSxL
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx27-weim
+ - fsl,imx31-weim
+ - fsl,imx35-weim
+ then:
+ patternProperties:
+ "^.*@[0-7],[0-9a-f]+$":
+ properties:
+ fsl,weim-cs-timing:
+ items:
+ items:
+ - description: CSCRxU
+ - description: CSCRxL
+ - description: CSCRxA
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx50-weim
+ - fsl,imx51-weim
+ - fsl,imx6q-weim
+ - fsl,imx6sx-weim
+ - fsl,imx6ul-weim
+ then:
+ patternProperties:
+ "^.*@[0-7],[0-9a-f]+$":
+ properties:
+ fsl,weim-cs-timing:
+ items:
+ items:
+ - description: CSxGCR1
+ - description: CSxGCR2
+ - description: CSxRCR1
+ - description: CSxRCR2
+ - description: CSxWCR1
+ - description: CSxWCR2
+
+additionalProperties: false
+
+examples:
+ - |
+ memory-controller@21b8000 {
+ compatible = "fsl,imx6q-weim";
+ reg = <0x021b8000 0x4000>;
+ clocks = <&clks 196>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x08000000 0x08000000>;
+ fsl,weim-cs-gpr = <&gpr>;
+
+ flash@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x02000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+ 0x0000c000 0x1404a38e 0x00000000>;
+ };
+ };
- $ref: ingenic,nemc-peripherals.yaml#
- $ref: intel,ixp4xx-expansion-peripheral-props.yaml#
- $ref: ti,gpmc-child.yaml#
+ - $ref: fsl/fsl,imx-weim-peripherals.yaml
additionalProperties: true
"^emc-table@[0-9]+$":
$ref: "#/$defs/emc-table"
- "^emc-tables@[a-z0-9-]+$":
+ "^emc-tables@[a-f0-9-]+$":
type: object
properties:
reg:
- items:
- enum:
- renesas,r8a779g0-rpc-if # R-Car V4H
+ - renesas,r8a779h0-rpc-if # R-Car V4M
- const: renesas,rcar-gen4-rpc-if # a generic R-Car gen4 device
- items:
properties:
compatible:
- const: st,stm32mp1-fmc2-ebi
+ enum:
+ - st,stm32mp1-fmc2-ebi
+ - st,stm32mp25-fmc2-ebi
reg:
maxItems: 1
resets:
maxItems: 1
+ power-domains:
+ maxItems: 1
+
"#address-cells":
const: 2
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/atmel,hlcdc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel's HLCD Controller
+
+maintainers:
+ - Nicolas Ferre <nicolas.ferre@microchip.com>
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+ - Claudiu Beznea <claudiu.beznea@tuxon.dev>
+
+description:
+ The Atmel HLCDC (HLCD Controller) IP available on Atmel SoCs exposes two
+ subdevices, a PWM chip and a Display Controller.
+
+properties:
+ compatible:
+ enum:
+ - atmel,at91sam9n12-hlcdc
+ - atmel,at91sam9x5-hlcdc
+ - atmel,sama5d2-hlcdc
+ - atmel,sama5d3-hlcdc
+ - atmel,sama5d4-hlcdc
+ - microchip,sam9x60-hlcdc
+ - microchip,sam9x75-xlcdc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 3
+
+ clock-names:
+ items:
+ - const: periph_clk
+ - const: sys_clk
+ - const: slow_clk
+ - const: lvds_pll_clk
+ minItems: 3
+
+ display-controller:
+ $ref: /schemas/display/atmel/atmel,hlcdc-display-controller.yaml
+
+ pwm:
+ $ref: /schemas/pwm/atmel,hlcdc-pwm.yaml
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/at91.h>
+ #include <dt-bindings/dma/at91.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ lcd_controller: lcd-controller@f0030000 {
+ compatible = "atmel,sama5d3-hlcdc";
+ reg = <0xf0030000 0x2000>;
+ clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+ clock-names = "periph_clk", "sys_clk", "slow_clk";
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ display-controller {
+ compatible = "atmel,hlcdc-display-controller";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ hlcdc_panel_output: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+
+ pwm {
+ compatible = "atmel,hlcdc-pwm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_pwm>;
+ #pwm-cells = <3>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/atmel,sama5d2-flexcom.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Flexcom (Flexible Serial Communication Unit)
+
+maintainers:
+ - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
+
+description:
+ The Microchip Flexcom is just a wrapper which embeds a SPI controller,
+ an I2C controller and an USART. Only one function can be used at a
+ time and is chosen at boot time according to the device tree.
+
+properties:
+ compatible:
+ oneOf:
+ - const: atmel,sama5d2-flexcom
+ - items:
+ - const: microchip,sam9x7-flexcom
+ - const: atmel,sama5d2-flexcom
+ - items:
+ - const: microchip,sama7g5-flexcom
+ - const: atmel,sama5d2-flexcom
+
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges:
+ description:
+ One range for the full I/O register region. (including USART,
+ TWI and SPI registers).
+ items:
+ maxItems: 3
+
+ atmel,flexcom-mode:
+ description: |
+ Specifies the flexcom mode as follows:
+ 1: USART
+ 2: SPI
+ 3: I2C.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 3]
+
+patternProperties:
+ "^serial@[0-9a-f]+$":
+ type: object
+ description:
+ Child node describing USART. See atmel-usart.txt for details
+ of USART bindings.
+
+ "^spi@[0-9a-f]+$":
+ type: object
+ description:
+ Child node describing SPI. See ../spi/spi_atmel.txt for details
+ of SPI bindings.
+
+ "^i2c@[0-9a-f]+$":
+ $ref: /schemas/i2c/atmel,at91sam-i2c.yaml
+ description:
+ Child node describing I2C.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - atmel,flexcom-mode
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ flx0: flexcom@f8034000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8034000 0x200>;
+ clocks = <&flx0_clk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8034000 0x800>;
+ atmel,flexcom-mode = <2>;
+ };
+...
+++ /dev/null
-* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit)
-
-The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C
-controller and an USART. Only one function can be used at a time and is chosen
-at boot time according to the device tree.
-
-Required properties:
-- compatible: Should be "atmel,sama5d2-flexcom"
- or "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"
-- reg: Should be the offset/length value for Flexcom dedicated
- I/O registers (without USART, TWI or SPI registers).
-- clocks: Should be the Flexcom peripheral clock from PMC.
-- #address-cells: Should be <1>
-- #size-cells: Should be <1>
-- ranges: Should be one range for the full I/O register region
- (including USART, TWI and SPI registers).
-- atmel,flexcom-mode: Should be one of the following values:
- - <1> for USART
- - <2> for SPI
- - <3> for I2C
-
-Required child:
-A single available child device of type matching the "atmel,flexcom-mode"
-property.
-
-The phandle provided by the clocks property of the child is the same as one for
-the Flexcom parent.
-
-For other properties, please refer to the documentations of the respective
-device:
-- ../serial/atmel-usart.txt
-- ../spi/spi_atmel.txt
-- ../i2c/i2c-at91.txt
-
-Example:
-
-flexcom@f8034000 {
- compatible = "atmel,sama5d2-flexcom";
- reg = <0xf8034000 0x200>;
- clocks = <&flx0_clk>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xf8034000 0x800>;
- atmel,flexcom-mode = <2>;
-
- spi@400 {
- compatible = "atmel,at91rm9200-spi";
- reg = <0x400 0x200>;
- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flx0_default>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&flx0_clk>;
- clock-names = "spi_clk";
- atmel,fifo-size = <32>;
-
- flash@0 {
- compatible = "atmel,at25f512b";
- reg = <0>;
- spi-max-frequency = <20000000>;
- };
- };
-};
+++ /dev/null
-Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver
-
-Required properties:
- - compatible: value should be one of the following:
- "atmel,at91sam9n12-hlcdc"
- "atmel,at91sam9x5-hlcdc"
- "atmel,sama5d2-hlcdc"
- "atmel,sama5d3-hlcdc"
- "atmel,sama5d4-hlcdc"
- "microchip,sam9x60-hlcdc"
- "microchip,sam9x75-xlcdc"
- - reg: base address and size of the HLCDC device registers.
- - clock-names: the name of the 3 clocks requested by the HLCDC device.
- Should contain "periph_clk", "sys_clk" and "slow_clk".
- - clocks: should contain the 3 clocks requested by the HLCDC device.
- - interrupts: should contain the description of the HLCDC interrupt line
-
-The HLCDC IP exposes two subdevices:
- - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt
- - a Display Controller: see ../display/atmel/hlcdc-dc.txt
-
-Example:
-
- hlcdc: hlcdc@f0030000 {
- compatible = "atmel,sama5d3-hlcdc";
- reg = <0xf0030000 0x2000>;
- clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
- clock-names = "periph_clk","sys_clk", "slow_clk";
- interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
-
- hlcdc-display-controller {
- compatible = "atmel,hlcdc-display-controller";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- hlcdc_panel_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&panel_input>;
- };
- };
- };
-
- hlcdc_pwm: hlcdc-pwm {
- compatible = "atmel,hlcdc-pwm";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcd_pwm>;
- #pwm-cells = <3>;
- };
- };
+++ /dev/null
-* Dialog DA9062 Power Management Integrated Circuit (PMIC)
-
-Product information for the DA9062 and DA9061 devices can be found here:
-- https://www.dialog-semiconductor.com/products/da9062
-- https://www.dialog-semiconductor.com/products/da9061
-
-The DA9062 PMIC consists of:
-
-Device Supply Names Description
------- ------------ -----------
-da9062-regulator : : LDOs & BUCKs
-da9062-rtc : : Real-Time Clock
-da9062-onkey : : On Key
-da9062-watchdog : : Watchdog Timer
-da9062-thermal : : Thermal
-da9062-gpio : : GPIOs
-
-The DA9061 PMIC consists of:
-
-Device Supply Names Description
------- ------------ -----------
-da9062-regulator : : LDOs & BUCKs
-da9062-onkey : : On Key
-da9062-watchdog : : Watchdog Timer
-da9062-thermal : : Thermal
-
-======
-
-Required properties:
-
-- compatible : Should be
- "dlg,da9062" for DA9062
- "dlg,da9061" for DA9061
-- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be
- modified to match the chip's OTP settings).
-
-Optional properties:
-
-- gpio-controller : Marks the device as a gpio controller.
-- #gpio-cells : Should be two. The first cell is the pin number and the
- second cell is used to specify the gpio polarity.
-
-See Documentation/devicetree/bindings/gpio/gpio.txt for further information on
-GPIO bindings.
-
-- interrupts : IRQ line information.
-- interrupt-controller
-
-See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
-further information on IRQ bindings.
-
-Sub-nodes:
-
-- regulators : This node defines the settings for the LDOs and BUCKs.
- The DA9062 regulators are bound using their names listed below:
-
- buck1 : BUCK_1
- buck2 : BUCK_2
- buck3 : BUCK_3
- buck4 : BUCK_4
- ldo1 : LDO_1
- ldo2 : LDO_2
- ldo3 : LDO_3
- ldo4 : LDO_4
-
- The DA9061 regulators are bound using their names listed below:
-
- buck1 : BUCK_1
- buck2 : BUCK_2
- buck3 : BUCK_3
- ldo1 : LDO_1
- ldo2 : LDO_2
- ldo3 : LDO_3
- ldo4 : LDO_4
-
- The component follows the standard regulator framework and the bindings
- details of individual regulator device can be found in:
- Documentation/devicetree/bindings/regulator/regulator.txt
-
- regulator-initial-mode may be specified for buck regulators using mode values
- from include/dt-bindings/regulator/dlg,da9063-regulator.h.
-
-- rtc : This node defines settings required for the Real-Time Clock associated
- with the DA9062. There are currently no entries in this binding, however
- compatible = "dlg,da9062-rtc" should be added if a node is created.
-
-- onkey : See ../input/da9062-onkey.txt
-
-- watchdog: See ../watchdog/da9062-wdt.txt
-
-- thermal : See ../thermal/da9062-thermal.txt
-
-Example:
-
- pmic0: da9062@58 {
- compatible = "dlg,da9062";
- reg = <0x58>;
- interrupt-parent = <&gpio6>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
-
- rtc {
- compatible = "dlg,da9062-rtc";
- };
-
- regulators {
- DA9062_BUCK1: buck1 {
- regulator-name = "BUCK1";
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1570000>;
- regulator-min-microamp = <500000>;
- regulator-max-microamp = <2000000>;
- regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
- regulator-boot-on;
- };
- DA9062_LDO1: ldo1 {
- regulator-name = "LDO_1";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <3600000>;
- regulator-boot-on;
- };
- };
- };
-
$id: http://devicetree.org/schemas/mfd/dlg,da9063.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Dialog DA9063/DA9063L Power Management Integrated Circuit (PMIC)
+title: Dialog DA906{3L,3,2,1} Power Management Integrated Circuit (PMIC)
maintainers:
- Steve Twiss <stwiss.opensource@diasemi.com>
moment where all voltage monitors are disabled. Next, as da9063 only supports
UV *and* OV monitoring, both must be set to the same severity and value
(0: disable, 1: enable).
+ Product information for the DA906{3L,3,2,1} devices can be found here:
+ - https://www.dialog-semiconductor.com/products/da9063l
+ - https://www.dialog-semiconductor.com/products/da9063
+ - https://www.dialog-semiconductor.com/products/da9062
+ - https://www.dialog-semiconductor.com/products/da9061
properties:
compatible:
enum:
+ - dlg,da9061
+ - dlg,da9062
- dlg,da9063
- dlg,da9063l
"#interrupt-cells":
const: 2
- dlg,use-sw-pm:
- type: boolean
- description:
- Disable the watchdog during suspend.
- Only use this option if you can't use the watchdog automatic suspend
- function during a suspend (see register CONTROL_B).
+ gpio-controller: true
- watchdog:
+ "#gpio-cells":
+ const: 2
+
+ gpio:
type: object
- $ref: /schemas/watchdog/watchdog.yaml#
- unevaluatedProperties: false
+ additionalProperties: false
properties:
compatible:
- const: dlg,da9063-watchdog
+ const: dlg,da9062-gpio
+
+ onkey:
+ $ref: /schemas/input/dlg,da9062-onkey.yaml
+
+ regulators:
+ type: object
+ additionalProperties: false
+ patternProperties:
+ "^(ldo([1-9]|1[01])|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged|buck[1-4])$":
+ $ref: /schemas/regulator/regulator.yaml
+ unevaluatedProperties: false
rtc:
type: object
unevaluatedProperties: false
properties:
compatible:
- const: dlg,da9063-rtc
+ enum:
+ - dlg,da9062-rtc
+ - dlg,da9063-rtc
- onkey:
- type: object
- $ref: /schemas/input/input.yaml#
- unevaluatedProperties: false
- properties:
- compatible:
- const: dlg,da9063-onkey
+ thermal:
+ $ref: /schemas/thermal/dlg,da9062-thermal.yaml
- dlg,disable-key-power:
- type: boolean
- description: |
- Disable power-down using a long key-press.
- If this entry does not exist then by default the key-press triggered
- power down is enabled and the OnKey will support both KEY_POWER and
- KEY_SLEEP.
+ watchdog:
+ $ref: /schemas/watchdog/dlg,da9062-watchdog.yaml
- regulators:
+patternProperties:
+ "^(.+-hog(-[0-9]+)?)$":
type: object
- additionalProperties: false
- patternProperties:
- "^(ldo([1-9]|1[01])|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged)$":
- $ref: /schemas/regulator/regulator.yaml
- unevaluatedProperties: false
+
+ required:
+ - gpio-hog
required:
- compatible
- reg
- - interrupts
- - interrupt-controller
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - dlg,da9063
+ - dlg,da9063l
+ then:
+ properties:
+ gpio-controller: false
+ "#gpio-cells": false
+ gpio: false
+ regulators:
+ patternProperties:
+ "^buck[1-4]$": false
+ thermal: false
+ required:
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - dlg,da9062
+ then:
+ properties:
+ regulators:
+ patternProperties:
+ "^(ldo([5-9]|10|11)|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged)$": false
+ required:
+ - gpio
+ - onkey
+ - rtc
+ - thermal
+ - watchdog
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - dlg,da9061
+ then:
+ properties:
+ gpio-controller: false
+ "#gpio-cells": false
+ gpio: false
+ regulators:
+ patternProperties:
+ "^(ldo([5-9]|10|11)|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged|buck4)$": false
+ rtc: false
+ required:
+ - onkey
+ - thermal
+ - watchdog
additionalProperties: false
pmic@58 {
compatible = "dlg,da9063";
reg = <0x58>;
- #interrupt-cells = <2>;
interrupt-parent = <&gpio6>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
+ #interrupt-cells = <2>;
rtc {
compatible = "dlg,da9063-rtc";
};
};
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/regulator/dlg,da9063-regulator.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic@58 {
+ compatible = "dlg,da9062";
+ reg = <0x58>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ sd0-pwr-sel-hog {
+ gpio-hog;
+ gpios = <1 0>;
+ input;
+ line-name = "SD0_PWR_SEL";
+ };
+
+ sd1-pwr-sel-hog {
+ gpio-hog;
+ gpios = <2 0>;
+ input;
+ line-name = "SD1_PWR_SEL";
+ };
+
+ sw-et0-en-hog {
+ gpio-hog;
+ gpios = <3 0>;
+ input;
+ line-name = "SW_ET0_EN#";
+ };
+
+ pmic-good-hog {
+ gpio-hog;
+ gpios = <4 0>;
+ output-high;
+ line-name = "PMIC_PGOOD";
+ };
+
+ gpio {
+ compatible = "dlg,da9062-gpio";
+ };
+
+ onkey {
+ compatible = "dlg,da9062-onkey";
+ };
+
+ regulators {
+ buck1 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1380000>;
+ regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
+ regulator-always-on;
+ };
+ buck2 {
+ regulator-name = "vdd_soc";
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1380000>;
+ regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
+ regulator-always-on;
+ };
+ buck3 {
+ regulator-name = "vdd_ddr3";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
+ regulator-always-on;
+ };
+ buck4 {
+ regulator-name = "vdd_eth";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
+ regulator-always-on;
+ };
+ ldo1 {
+ regulator-name = "vdd_snvs";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+ ldo2 {
+ regulator-name = "vdd_high";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+ ldo3 {
+ regulator-name = "vdd_eth_io";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+ ldo4 {
+ regulator-name = "vdd_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ };
+
+ rtc {
+ compatible = "dlg,da9062-rtc";
+ };
+
+ thermal {
+ compatible = "dlg,da9062-thermal";
+ };
+
+ watchdog {
+ compatible = "dlg,da9062-watchdog";
+ dlg,use-sw-pm;
+ };
+ };
+ };
...
'#size-cells':
const: 0
+ '#gpio-cells':
+ const: 2
+
+ gpio-controller: true
+
typec:
$ref: /schemas/chrome/google,cros-ec-typec.yaml#
interrupts = <99 0>;
interrupt-parent = <&gpio7>;
spi-max-frequency = <5000000>;
+ #gpio-cells = <2>;
+ gpio-controller;
proximity {
compatible = "google,cros-ec-mkbp-proximity";
maxItems: 1
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description:
Specifies the name of the calibration and configuration file selected by
the driver. If this property is omitted, the name is chosen based on the
- enum:
- qcom,msm8976-tcsr
- qcom,msm8998-tcsr
+ - qcom,qcm2290-tcsr
- qcom,qcs404-tcsr
- qcom,sc7180-tcsr
- qcom,sc7280-tcsr
- qcom,sdx55-tcsr
- qcom,sdx65-tcsr
- qcom,sm4450-tcsr
+ - qcom,sm6115-tcsr
- qcom,sm8150-tcsr
- qcom,sm8250-tcsr
- qcom,sm8350-tcsr
- rockchip,rk3588-qos
- rockchip,rv1126-qos
- starfive,jh7100-sysmain
+ - ti,am62-usb-phy-ctrl
- ti,am654-dss-oldi-io-ctrl
+ - ti,am654-serdes-ctrl
+ - ti,j784s4-pcie-ctrl
- const: syscon
interrupt-controller: true
+ system-power-controller: true
+
"#interrupt-cells":
const: 1
- brcm,bmips4380
- brcm,bmips5000
- brcm,bmips5200
- - ingenic,xburst-mxu1.0
+ - img,i6500
- ingenic,xburst-fpu1.0-mxu1.1
- ingenic,xburst-fpu2.0-mxu2.0
+ - ingenic,xburst-mxu1.0
- ingenic,xburst2-fpu2.1-mxu2.1-smt
- loongson,gs264
- mips,m14Kc
- - mips,mips4Kc
- - mips,mips4KEc
- - mips,mips24Kc
+ - mips,mips1004Kc
- mips,mips24KEc
+ - mips,mips24Kc
+ - mips,mips4KEc
+ - mips,mips4Kc
- mips,mips74Kc
- - mips,mips1004Kc
- mti,interaptiv
- - mti,mips24KEc
- mti,mips14KEc
- mti,mips14Kc
+ - mti,mips24KEc
reg:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright 2023 Mobileye Vision Technologies Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/mobileye.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobileye SoC series
+
+maintainers:
+ - Vladimir Kondratiev <vladimir.kondratiev@intel.com>
+ - Gregory CLEMENT <gregory.clement@bootlin.com>
+ - Théo Lebrun <theo.lebrun@bootlin.com>
+
+description:
+ Boards with a Mobileye SoC shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+
+ compatible:
+ oneOf:
+ - description: Boards with Mobileye EyeQ5 SoC
+ items:
+ - enum:
+ - mobileye,eyeq5-epm5
+ - const: mobileye,eyeq5
+
+additionalProperties: true
+
+...
reg:
maxItems: 1
+ dma-coherent: true
+
iommus:
minItems: 1
maxItems: 3
+++ /dev/null
-* Xilinx SDFEC(16nm) IP *
-
-The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
-which provides high-throughput LDPC and Turbo Code implementations.
-The LDPC decode & encode functionality is capable of covering a range of
-customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
-principally covers codes used by LTE. The FEC Engine offers significant
-power and area savings versus implementations done in the FPGA fabric.
-
-
-Required properties:
-- compatible: Must be "xlnx,sd-fec-1.1"
-- clock-names : List of input clock names from the following:
- - "core_clk", Main processing clock for processing core (required)
- - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
- - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
- - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
- - "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional)
- - "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional)
- - "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional)
- - "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional)
-- clocks : Clock phandles (see clock_bindings.txt for details).
-- reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers
- location and length.
-- xlnx,sdfec-code : Should contain "ldpc" or "turbo" to describe the codes
- being used.
-- xlnx,sdfec-din-words : A value 0 indicates that the DIN_WORDS interface is
- driven with a fixed value and is not present on the device, a value of 1
- configures the DIN_WORDS to be block based, while a value of 2 configures the
- DIN_WORDS input to be supplied for each AXI transaction.
-- xlnx,sdfec-din-width : Configures the DIN AXI stream where a value of 1
- configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
- of "4x128b".
-- xlnx,sdfec-dout-words : A value 0 indicates that the DOUT_WORDS interface is
- driven with a fixed value and is not present on the device, a value of 1
- configures the DOUT_WORDS to be block based, while a value of 2 configures the
- DOUT_WORDS input to be supplied for each AXI transaction.
-- xlnx,sdfec-dout-width : Configures the DOUT AXI stream where a value of 1
- configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
- of "4x128b".
-Optional properties:
-- interrupts: should contain SDFEC interrupt number
-
-Example
----------------------------------------
- sd_fec_0: sd-fec@a0040000 {
- compatible = "xlnx,sd-fec-1.1";
- clock-names = "core_clk","s_axi_aclk","s_axis_ctrl_aclk","s_axis_din_aclk","m_axis_status_aclk","m_axis_dout_aclk";
- clocks = <&misc_clk_2>,<&misc_clk_0>,<&misc_clk_1>,<&misc_clk_1>,<&misc_clk_1>, <&misc_clk_1>;
- reg = <0x0 0xa0040000 0x0 0x40000>;
- interrupt-parent = <&axi_intc>;
- interrupts = <1 0>;
- xlnx,sdfec-code = "ldpc";
- xlnx,sdfec-din-words = <0>;
- xlnx,sdfec-din-width = <2>;
- xlnx,sdfec-dout-words = <0>;
- xlnx,sdfec-dout-width = <1>;
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx SDFEC(16nm) IP
+
+maintainers:
+ - Cvetic, Dragan <dragan.cvetic@amd.com>
+ - Erim, Salih <salih.erim@amd.com>
+
+description:
+ The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
+ which provides high-throughput LDPC and Turbo Code implementations.
+ The LDPC decode & encode functionality is capable of covering a range of
+ customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
+ principally covers codes used by LTE. The FEC Engine offers significant
+ power and area savings versus implementations done in the FPGA fabric.
+
+properties:
+ compatible:
+ const: xlnx,sd-fec-1.1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 8
+ additionalItems: true
+ items:
+ - description: Main processing clock for processing core
+ - description: AXI4-Lite memory-mapped slave interface clock
+ - description: Control input AXI4-Stream Slave interface clock
+ - description: DIN AXI4-Stream Slave interface clock
+ - description: Status output AXI4-Stream Master interface clock
+ - description: DOUT AXI4-Stream Master interface clock
+ - description: DIN_WORDS AXI4-Stream Slave interface clock
+ - description: DOUT_WORDS AXI4-Stream Master interface clock
+
+ clock-names:
+ allOf:
+ - minItems: 2
+ maxItems: 8
+ additionalItems: true
+ items:
+ - const: core_clk
+ - const: s_axi_aclk
+ - items:
+ enum:
+ - core_clk
+ - s_axi_aclk
+ - s_axis_ctrl_aclk
+ - s_axis_din_aclk
+ - m_axis_status_aclk
+ - m_axis_dout_aclk
+ - s_axis_din_words_aclk
+ - m_axis_dout_words_aclk
+
+ interrupts:
+ maxItems: 1
+
+ xlnx,sdfec-code:
+ description:
+ The SD-FEC integrated block supports Low Density Parity Check (LDPC)
+ decoding and encoding and Turbo code decoding. The LDPC codes used are
+ highly configurable, and the specific code used can be specified on
+ a codeword-by-codeword basis. The Turbo code decoding is required by LTE
+ standard.
+ $ref: /schemas/types.yaml#/definitions/string
+ items:
+ enum: [ ldpc, turbo ]
+
+ xlnx,sdfec-din-width:
+ description:
+ Configures the DIN AXI stream where a value of 1
+ configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
+ of "4x128b".
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2, 4 ]
+
+ xlnx,sdfec-din-words:
+ description:
+ A value 0 indicates that the DIN_WORDS interface is
+ driven with a fixed value and is not present on the device, a value of 1
+ configures the DIN_WORDS to be block based, while a value of 2 configures the
+ DIN_WORDS input to be supplied for each AXI transaction.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 2 ]
+
+ xlnx,sdfec-dout-width:
+ description:
+ Configures the DOUT AXI stream where a value of 1 configures a width of "1x128b",
+ 2 a width of "2x128b" and 4 configures a width of "4x128b".
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2, 4 ]
+
+ xlnx,sdfec-dout-words:
+ description:
+ A value 0 indicates that the DOUT_WORDS interface is
+ driven with a fixed value and is not present on the device, a value of 1
+ configures the DOUT_WORDS to be block based, while a value of 2 configures the
+ DOUT_WORDS input to be supplied for each AXI transaction.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 2 ]
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - xlnx,sdfec-code
+ - xlnx,sdfec-din-width
+ - xlnx,sdfec-din-words
+ - xlnx,sdfec-dout-width
+ - xlnx,sdfec-dout-words
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ sd-fec@a0040000 {
+ compatible = "xlnx,sd-fec-1.1";
+ reg = <0xa0040000 0x40000>;
+ clocks = <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_1>,
+ <&misc_clk_1>, <&misc_clk_1>;
+ clock-names = "core_clk", "s_axi_aclk", "s_axis_ctrl_aclk",
+ "s_axis_din_aclk", "m_axis_status_aclk",
+ "m_axis_dout_aclk";
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ xlnx,sdfec-code = "ldpc";
+ xlnx,sdfec-din-width = <2>;
+ xlnx,sdfec-din-words = <0>;
+ xlnx,sdfec-dout-width = <1>;
+ xlnx,sdfec-dout-words = <0>;
+ };
+
- enum:
- fsl,imx8mn-usdhc
- fsl,imx8mp-usdhc
- - fsl,imx93-usdhc
- fsl,imx8ulp-usdhc
+ - fsl,imx93-usdhc
+ - fsl,imx95-usdhc
- const: fsl,imx8mm-usdhc
- items:
- enum:
- const: ahb
- const: per
+ iommus:
+ maxItems: 1
+
power-domains:
maxItems: 1
- const: state_100mhz
- const: state_200mhz
- const: sleep
+ - minItems: 2
+ items:
+ - const: default
+ - const: state_100mhz
+ - const: sleep
- minItems: 1
items:
- const: default
reg:
maxItems: 1
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: ipg
+ - const: per
+
interrupts:
maxItems: 1
const: rx-tx
required:
+ - clocks
+ - clock-names
- compatible
- reg
- interrupts
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x10014000 0x1000>;
interrupts = <11>;
+ clocks = <&clks 29>, <&clks 60>;
+ clock-names = "ipg", "per";
dmas = <&dma 7>;
dma-names = "rx-tx";
bus-width = <4>;
+++ /dev/null
-* Hisilicon Hi3798CV200 specific extensions to the Synopsys Designware Mobile
- Storage Host Controller
-
-Read synopsys-dw-mshc.txt for more details
-
-The Synopsys designware mobile storage host controller is used to interface
-a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
-differences between the core Synopsys dw mshc controller properties described
-by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200
-specific extensions to the Synopsys Designware Mobile Storage Host Controller.
-
-Required Properties:
-- compatible: Should contain "hisilicon,hi3798cv200-dw-mshc".
-- clocks: A list of phandle + clock-specifier pairs for the clocks listed
- in clock-names.
-- clock-names: Should contain the following:
- "ciu" - The ciu clock described in synopsys-dw-mshc.txt.
- "biu" - The biu clock described in synopsys-dw-mshc.txt.
- "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
- "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving.
-
-Example:
-
- emmc: mmc@9830000 {
- compatible = "hisilicon,hi3798cv200-dw-mshc";
- reg = <0x9830000 0x10000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&crg HISTB_MMC_CIU_CLK>,
- <&crg HISTB_MMC_BIU_CLK>,
- <&crg HISTB_MMC_SAMPLE_CLK>,
- <&crg HISTB_MMC_DRV_CLK>;
- clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
- fifo-depth = <256>;
- clock-frequency = <200000000>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- non-removable;
- bus-width = <8>;
- };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon HiSTB SoCs specific extensions to the Synopsys DWMMC controller
+
+maintainers:
+ - Yang Xiwen <forbidden405@outlook.com>
+
+properties:
+ compatible:
+ enum:
+ - hisilicon,hi3798cv200-dw-mshc
+ - hisilicon,hi3798mv200-dw-mshc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: bus interface unit clock
+ - description: card interface unit clock
+ - description: card input sample phase clock
+ - description: controller output drive phase clock
+
+ clock-names:
+ items:
+ - const: ciu
+ - const: biu
+ - const: ciu-sample
+ - const: ciu-drive
+
+ hisilicon,sap-dll-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ DWMMC core on Hi3798MV2x SoCs has a delay-locked-loop(DLL) attached to card data input path.
+ It is integrated into CRG core on the SoC and has to be controlled during tuning.
+ items:
+ - description: A phandle pointed to the CRG syscon node
+ - description: Sample DLL register offset in CRG address space
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+allOf:
+ - $ref: synopsys-dw-mshc-common.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: hisilicon,hi3798mv200-dw-mshc
+ then:
+ required:
+ - hisilicon,sap-dll-reg
+ else:
+ properties:
+ hisilicon,sap-dll-reg: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/histb-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mmc@9830000 {
+ compatible = "hisilicon,hi3798cv200-dw-mshc";
+ reg = <0x9830000 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_MMC_CIU_CLK>,
+ <&crg HISTB_MMC_BIU_CLK>,
+ <&crg HISTB_MMC_SAMPLE_CLK>,
+ <&crg HISTB_MMC_DRV_CLK>;
+ clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
+ resets = <&crg 0xa0 4>;
+ reset-names = "reset";
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
+ &emmc_pins_3 &emmc_pins_4>;
+ fifo-depth = <256>;
+ clock-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ bus-width = <8>;
+ };
- renesas,sdhi-r8a779a0 # R-Car V3U
- renesas,sdhi-r8a779f0 # R-Car S4-8
- renesas,sdhi-r8a779g0 # R-Car V4H
+ - renesas,sdhi-r8a779h0 # R-Car V4M
- const: renesas,rcar-gen4-sdhi # R-Car Gen4
reg:
- rockchip,rk3568-dwcmshc
- rockchip,rk3588-dwcmshc
- snps,dwcmshc-sdhci
+ - sophgo,cv1800b-dwcmshc
+ - sophgo,sg2002-dwcmshc
- thead,th1520-dwcmshc
reg:
"atmel,sama5d4-pmecc"
"atmel,sama5d2-pmecc"
"microchip,sam9x60-pmecc"
+ "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"
- reg: should contain 2 register ranges. The first one is pointing to the PMECC
block, and the second one to the PMECC_ERRLOC block.
maintainers:
- Brian Norris <computersforpeace@gmail.com>
- Kamal Dasu <kdasu.kdev@gmail.com>
+ - William Zhang <william.zhang@broadcom.com>
description: |
The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
supports basic PROGRAM and READ functions, among other features.
This controller was originally designed for STB SoCs (BCM7xxx) but is now
- available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
- iProc/Cygnus. Its history includes several similar (but not fully register
- compatible) versions.
+ available on a variety of Broadcom SoCs, including some BCM3xxx, MIPS based
+ Broadband SoC (BCM63xx), ARM based Broadband SoC (BCMBCA) and iProc/Cygnus.
+ Its history includes several similar (but not fully register compatible)
+ versions.
-- Additional SoC-specific NAND controller properties --
- brcm,brcmnand-v7.2
- brcm,brcmnand-v7.3
- const: brcm,brcmnand
- - description: BCM63138 SoC-specific NAND controller
+ - description: BCMBCA SoC-specific NAND controller
items:
- const: brcm,nand-bcm63138
- enum:
earlier versions of this core that include WP
type: boolean
+ brcm,wp-not-connected:
+ description:
+ Use this property when WP pin is not physically wired to the NAND chip.
+ Write protection feature cannot be used. By default, controller assumes
+ the pin is connected and feature is used.
+ $ref: /schemas/types.yaml#/definitions/flag
+
patternProperties:
"^nand@[a-f0-9]$":
type: object
layout.
$ref: /schemas/types.yaml#/definitions/uint32
+ brcm,nand-ecc-use-strap:
+ description:
+ This property requires the host system to get the ECC related
+ settings from the SoC NAND boot strap configuration instead of
+ the generic NAND ECC settings. This is a common hardware design
+ on BCMBCA based boards. This strap ECC option and generic NAND
+ ECC option can not be specified at the same time.
+ $ref: /schemas/types.yaml#/definitions/flag
+
unevaluatedProperties: false
allOf:
- const: iproc-idm
- const: iproc-ext
- if:
+ required:
+ - interrupts
properties:
interrupts:
minItems: 2
required:
- interrupt-names
+ - if:
+ patternProperties:
+ "^nand@[a-f0-9]$":
+ required:
+ - brcm,nand-ecc-use-strap
+ then:
+ patternProperties:
+ "^nand@[a-f0-9]$":
+ properties:
+ nand-ecc-strength: false
+ nand-ecc-step-size: false
+ nand-ecc-maximize: false
+ nand-ecc-algo: false
+ brcm,nand-oob-sector-size: false
+
unevaluatedProperties: false
required:
- reg
- reg-names
- - interrupts
examples:
- |
false.
Nand device bindings may contain additional sub-nodes describing partitions of
-the address space. See partition.txt for more detail. The NAND Flash timing
+the address space. See mtd.yaml for more detail. The NAND Flash timing
values must be programmed in the chip select’s node of AEMIF
memory-controller (see Documentation/devicetree/bindings/memory-controllers/
davinci-aemif.txt).
completing the bindings.
The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
+address space. See mtd.yaml for more detail.
Example:
(R/B# pins not connected).
Each flash chip described may optionally contain additional sub-nodes
-describing partitions of the address space. See partition.txt for more
+describing partitions of the address space. See mtd.yaml for more
detail.
Examples:
read to ensure that the GPIO accesses have completed.
The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
+address space. See mtd.yaml for more detail.
Examples:
description: |
The GPMI nand controller provides an interface to control the NAND
flash chips. The device tree may optionally contain sub-nodes
- describing partitions of the address space. See partition.txt for
+ describing partitions of the address space. See mtd.yaml for
more detail.
properties:
- nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
Flash chip may optionally contain additional sub-nodes describing partitions of
-the address space. See partition.txt for more detail.
+the address space. See mtd.yaml for more detail.
Example:
minItems: 1
maxItems: 2
+ interrupts:
+ maxItems: 1
+
m25p,fast-read:
type: boolean
description:
- Miquel Raynal <miquel.raynal@bootlin.com>
- Richard Weinberger <richard@nod.at>
+select: false
+
properties:
$nodename:
pattern: "^(flash|.*sram|nand)(@.*)?$"
- wp-gpios: GPIO specifier for the write protect pin.
Optional child node of NAND chip nodes:
-Partitions: see partition.txt
+Partitions: see mtd.yaml
Example:
nand-controller@70008000 {
registers in usecs
The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
+address space. See mtd.yaml for more detail.
Example:
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/partitions/linux,ubi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unsorted Block Images
+
+description: |
+ UBI ("Unsorted Block Images") is a volume management system for raw
+ flash devices which manages multiple logical volumes on a single
+ physical flash device and spreads the I/O load (i.e wear-leveling)
+ across the whole flash chip.
+
+maintainers:
+ - Daniel Golle <daniel@makrotopia.org>
+
+allOf:
+ - $ref: partition.yaml#
+
+properties:
+ compatible:
+ const: linux,ubi
+
+ volumes:
+ type: object
+ description: UBI Volumes
+
+ patternProperties:
+ "^ubi-volume-.*$":
+ $ref: /schemas/mtd/partitions/ubi-volume.yaml#
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x0 0x100000>;
+ label = "bootloader";
+ read-only;
+ };
+
+ partition@100000 {
+ reg = <0x100000 0x1ff00000>;
+ label = "ubi";
+ compatible = "linux,ubi";
+
+ volumes {
+ ubi-volume-caldata {
+ volid = <2>;
+ volname = "rf";
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom@0 {
+ reg = <0x0 0x1000>;
+ };
+ };
+ };
+ };
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/partitions/ubi-volume.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UBI volume
+
+description: |
+ This binding describes a single UBI volume. Volumes can be matches either
+ by their ID or their name, or both.
+
+maintainers:
+ - Daniel Golle <daniel@makrotopia.org>
+
+properties:
+ volid:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Match UBI volume ID
+
+ volname:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ Match UBI volume ID
+
+ nvmem-layout:
+ $ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
+ description:
+ This container may reference an NVMEM layout parser.
+
+anyOf:
+ - required:
+ - volid
+
+ - required:
+ - volname
+
+# This is a generic file other binding inherit from and extend
+additionalProperties: true
Each child device node may optionally contain a 'partitions' sub-node,
which further contains sub-nodes describing the flash partition mapping.
-See partition.txt for more detail.
+See mtd.yaml for more detail.
Example:
enum:
- st,stm32mp15-fmc2
- st,stm32mp1-fmc2-nfc
+ - st,stm32mp25-fmc2-nfc
reg:
minItems: 6
- maxItems: 7
+ maxItems: 12
interrupts:
maxItems: 1
- description: Chip select 1 command
- description: Chip select 1 address space
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp25-fmc2-nfc
+ then:
+ properties:
+ reg:
+ items:
+ - description: Chip select 0 data
+ - description: Chip select 0 command
+ - description: Chip select 0 address space
+ - description: Chip select 1 data
+ - description: Chip select 1 command
+ - description: Chip select 1 address space
+ - description: Chip select 2 data
+ - description: Chip select 2 command
+ - description: Chip select 2 address space
+ - description: Chip select 3 data
+ - description: Chip select 3 command
+ - description: Chip select 3 address space
+
required:
- compatible
- reg
properties:
$nodename:
- pattern: '^mux-controller(@.*|-[0-9a-f]+)?$'
+ pattern: '^mux-controller(@.*|-([0-9]|[1-9][0-9]+))?$'
'#mux-control-cells':
enum: [ 0, 1 ]
title: Qualcomm Bluetooth Chips
maintainers:
- - Balakrishna Godavarthi <bgodavar@codeaurora.org>
- - Rocky Liao <rjliao@codeaurora.org>
+ - Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
+ - Rocky Liao <quic_rjliao@quicinc.com>
description:
This binding describes Qualcomm UART-attached bluetooth chips.
local-bd-address: true
+ qcom,local-bd-address-broken:
+ type: boolean
+ description:
+ boot firmware is incorrectly passing the address in big-endian order
required:
- compatible
properties:
compatible:
oneOf:
+ - items:
+ - enum:
+ - brcm,bcm74165b0-asp
+ - const: brcm,asp-v2.2
- items:
- enum:
- brcm,bcm74165-asp
- brcm,genet-mdio-v5
- brcm,asp-v2.0-mdio
- brcm,asp-v2.1-mdio
+ - brcm,asp-v2.2-mdio
- brcm,unimac-mdio
reg:
- fsl,imx6ul-flexcan
- fsl,imx6sx-flexcan
- const: fsl,imx6q-flexcan
+ - items:
+ - const: fsl,imx95-flexcan
+ - const: fsl,imx93-flexcan
- items:
- enum:
- fsl,ls1028ar1-flexcan
maxItems: 1
clocks:
- maxItems: 1
+ items:
+ - description: AHB peripheral clock
+ - description: CAN bus clock
required:
- compatible
can@2010c000 {
compatible = "microchip,mpfs-can";
reg = <0x2010c000 0x1000>;
- clocks = <&clkcfg 17>;
+ clocks = <&clkcfg 17>, <&clkcfg 37>;
interrupt-parent = <&plic>;
interrupts = <56>;
};
available with tcan4552/4553.
- device-wake-gpios: Wake up GPIO to wake up the TCAN device. Not
available with tcan4552/4553.
+ - wakeup-source: Leave the chip running when suspended, and configure
+ the RX interrupt to wake up the device.
Example:
tcan4x5x: tcan4x5x@0 {
device-state-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
device-wake-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ wakeup-source;
};
resets:
maxItems: 1
+ xlnx,has-ecc:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN)
+
required:
- compatible
- reg
interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ xlnx,has-ecc;
};
- |
- cdns,gem # Generic
- cdns,macb # Generic
+ - items:
+ - enum:
+ - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface
+ - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
+
reg:
minItems: 1
items:
+++ /dev/null
-Atheros AR9331 built-in switch
-=============================
-
-It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal
-MDIO bus. All PHYs are built-in as well.
-
-Required properties:
-
- - compatible: should be: "qca,ar9331-switch"
- - reg: Address on the MII bus for the switch.
- - resets : Must contain an entry for each entry in reset-names.
- - reset-names : Must include the following entries: "switch"
- - interrupt-parent: Phandle to the parent interrupt controller
- - interrupts: IRQ line for the switch
- - interrupt-controller: Indicates the switch is itself an interrupt
- controller. This is used for the PHY interrupts.
- - #interrupt-cells: must be 1
- - mdio: Container of PHY and devices on the switches MDIO bus.
-
-See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
-required and optional properties.
-Examples:
-
-eth0: ethernet@19000000 {
- compatible = "qca,ar9330-eth";
- reg = <0x19000000 0x200>;
- interrupts = <4>;
-
- resets = <&rst 9>, <&rst 22>;
- reset-names = "mac", "mdio";
- clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
- clock-names = "eth", "mdio";
-
- phy-mode = "mii";
- phy-handle = <&phy_port4>;
-};
-
-eth1: ethernet@1a000000 {
- compatible = "qca,ar9330-eth";
- reg = <0x1a000000 0x200>;
- interrupts = <5>;
- resets = <&rst 13>, <&rst 23>;
- reset-names = "mac", "mdio";
- clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
- clock-names = "eth", "mdio";
-
- phy-mode = "gmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- switch10: switch@10 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "qca,ar9331-switch";
- reg = <0x10>;
- resets = <&rst 8>;
- reset-names = "switch";
-
- interrupt-parent = <&miscintc>;
- interrupts = <12>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- switch_port0: port@0 {
- reg = <0x0>;
- ethernet = <ð1>;
-
- phy-mode = "gmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- switch_port1: port@1 {
- reg = <0x1>;
- phy-handle = <&phy_port0>;
- phy-mode = "internal";
- };
-
- switch_port2: port@2 {
- reg = <0x2>;
- phy-handle = <&phy_port1>;
- phy-mode = "internal";
- };
-
- switch_port3: port@3 {
- reg = <0x3>;
- phy-handle = <&phy_port2>;
- phy-mode = "internal";
- };
-
- switch_port4: port@4 {
- reg = <0x4>;
- phy-handle = <&phy_port3>;
- phy-mode = "internal";
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&switch10>;
-
- phy_port0: phy@0 {
- reg = <0x0>;
- interrupts = <0>;
- };
-
- phy_port1: phy@1 {
- reg = <0x1>;
- interrupts = <0>;
- };
-
- phy_port2: phy@2 {
- reg = <0x2>;
- interrupts = <0>;
- };
-
- phy_port3: phy@3 {
- reg = <0x3>;
- interrupts = <0>;
- };
-
- phy_port4: phy@4 {
- reg = <0x4>;
- interrupts = <0>;
- };
- };
- };
- };
-};
- microchip,ksz9893
- microchip,ksz9563
- microchip,ksz8563
+ - microchip,ksz8567
reset-gpios:
description:
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/qca,ar9331.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Atheros AR9331 built-in switch
+
+maintainers:
+ - Oleksij Rempel <o.rempel@pengutronix.de>
+
+description:
+ Qualcomm Atheros AR9331 is a switch built-in to Atheros AR9331 WiSoC and
+ addressable over internal MDIO bus. All PHYs are built-in as well.
+
+properties:
+ compatible:
+ const: qca,ar9331-switch
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+
+ mdio:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+ properties:
+ interrupt-parent: true
+
+ patternProperties:
+ '(ethernet-)?phy@[0-4]+$':
+ type: object
+ unevaluatedProperties: false
+
+ properties:
+ reg: true
+ interrupts:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: switch
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - mdio
+ - ports
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: dsa.yaml#/$defs/ethernet-ports
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch10: switch@10 {
+ compatible = "qca,ar9331-switch";
+ reg = <0x10>;
+
+ interrupt-parent = <&miscintc>;
+ interrupts = <12>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ resets = <&rst 8>;
+ reset-names = "switch";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+ ethernet = <ð1>;
+
+ phy-mode = "gmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+ phy-handle = <&phy_port0>;
+ phy-mode = "internal";
+ };
+
+ port@2 {
+ reg = <0x2>;
+ phy-handle = <&phy_port1>;
+ phy-mode = "internal";
+ };
+
+ port@3 {
+ reg = <0x3>;
+ phy-handle = <&phy_port2>;
+ phy-mode = "internal";
+ };
+
+ port@4 {
+ reg = <0x4>;
+ phy-handle = <&phy_port3>;
+ phy-mode = "internal";
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&switch10>;
+
+ phy_port0: ethernet-phy@0 {
+ reg = <0x0>;
+ interrupts = <0>;
+ };
+
+ phy_port1: ethernet-phy@1 {
+ reg = <0x1>;
+ interrupts = <0>;
+ };
+
+ phy_port2: ethernet-phy@2 {
+ reg = <0x2>;
+ interrupts = <0>;
+ };
+
+ phy_port3: ethernet-phy@3 {
+ reg = <0x3>;
+ interrupts = <0>;
+ };
+
+ phy_port4: ethernet-phy@4 {
+ reg = <0x4>;
+ interrupts = <0>;
+ };
+ };
+ };
+ };
description: GPIO to be used to reset the whole device
maxItems: 1
+ resets:
+ maxItems: 1
+
realtek,disable-leds:
type: boolean
description: |
- mdc-gpios
- mdio-gpios
- mdio
- - reset-gpios
required:
- compatible
pattern: "^ethernet(@.*)?$"
label:
- $ref: /schemas/types.yaml#/definitions/string
description: Human readable label on a port of a box.
local-mac-address:
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ethernet PHY Package Common Properties
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description:
+ PHY packages are multi-port Ethernet PHY of the same family
+ and each Ethernet PHY is affected by the global configuration
+ of the PHY package.
+
+ Each reg of the PHYs defined in the PHY package node is
+ absolute and describe the real address of the Ethernet PHY on
+ the MDIO bus.
+
+properties:
+ $nodename:
+ pattern: "^ethernet-phy-package@[a-f0-9]+$"
+
+ reg:
+ minimum: 0
+ maximum: 31
+ description:
+ The base ID number for the PHY package.
+ Commonly the ID of the first PHY in the PHY package.
+
+ Some PHY in the PHY package might be not defined but
+ still occupy ID on the device (just not attached to
+ anything) hence the PHY package reg might correspond
+ to a not attached PHY (offset 0).
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ ^ethernet-phy@[a-f0-9]+$:
+ $ref: ethernet-phy.yaml#
+
+required:
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: true
Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms.
Other delays are invalid.
+ iommus:
+ maxItems: 1
+
required:
- compatible
- reg
minItems: 4
clocks:
- minItems: 34
- maxItems: 34
+ minItems: 24
+ maxItems: 24
clock-names:
items:
- const: ethwarp_wocpu1
- const: ethwarp_wocpu0
- const: esw
- - const: netsys0
- - const: netsys1
- - const: sgmii_tx250m
- - const: sgmii_rx250m
- - const: sgmii2_tx250m
- - const: sgmii2_rx250m
- - const: top_usxgmii0_sel
- - const: top_usxgmii1_sel
- - const: top_sgm0_sel
- - const: top_sgm1_sel
- - const: top_xfi_phy0_xtal_sel
- - const: top_xfi_phy1_xtal_sel
- const: top_eth_gmii_sel
- const: top_eth_refck_50m_sel
- const: top_eth_sys_200m_sel
- const: top_netsys_sync_250m_sel
- const: top_netsys_ppefb_250m_sel
- const: top_netsys_warp_sel
- - const: wocpu1
- - const: wocpu0
- const: xgp1
- const: xgp2
- const: xgp3
- mediatek,sgmiisys:
- minItems: 2
- maxItems: 2
-
patternProperties:
"^mac@[0-1]$":
type: object
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
- i2c {
+ spi {
#address-cells = <1>;
#size-cells = <0>;
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/qca,qca808x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Atheros QCA808X PHY
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description:
+ QCA808X PHYs can have up to 3 LEDs attached.
+ All 3 LEDs are disabled by default.
+ 2 LEDs have dedicated pins with the 3rd LED having the
+ double function of Interrupt LEDs/GPIO or additional LED.
+
+ By default this special PIN is set to LED function.
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ethernet-phy-id004d.d101
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@0 {
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <0>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+ };
+ };
+ };
items:
- description: Combined signal for various interrupt events
- description: The interrupt that occurs when Rx exits the LPI state
+ - description: The interrupt that occurs when HW safety error triggered
interrupt-names:
minItems: 1
items:
- const: macirq
- - const: eth_lpi
+ - enum: [eth_lpi, sfty]
+ - const: sfty
clocks:
maxItems: 4
<&gcc GCC_ETH_PTP_CLK>,
<&gcc GCC_ETH_RGMII_CLK>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq", "eth_lpi";
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi", "sfty";
rx-fifo-depth = <4096>;
tx-fifo-depth = <4096>;
when the AP (not the modem) performs early initialization.
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description:
If present, name (or relative path) of the file within the
firmware search path containing the firmware image used when
items:
- const: gcc_mdio_ahb_clk
+ clock-frequency:
+ description:
+ The MDIO bus clock that must be output by the MDIO bus hardware, if
+ absent, the default hardware values are used.
+
+ MDC rate is feed by an external clock (fixed 100MHz) and is divider
+ internally. The default divider is /256 resulting in the default rate
+ applied of 390KHz.
+
+ To follow 802.3 standard that instruct up to 2.5MHz by default, if
+ this property is not declared and the divider is set to /256, by
+ default 1.5625Mhz is select.
+ enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ]
+ default: 1562500
+
required:
- compatible
- reg
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/qcom,qca807x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCA807x Ethernet PHY
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+ - Robert Marko <robert.marko@sartura.hr>
+
+description: |
+ Qualcomm QCA8072/5 Ethernet PHY is PHY package of 2 or 5
+ IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
+ 1000BASE-T PHY-s.
+
+ They feature 2 SerDes, one for PSGMII or QSGMII connection with
+ MAC, while second one is SGMII for connection to MAC or fiber.
+
+ Both models have a combo port that supports 1000BASE-X and
+ 100BASE-FX fiber.
+
+ Each PHY inside of QCA807x series has 4 digitally controlled
+ output only pins that natively drive LED-s for up to 2 attached
+ LEDs. Some vendor also use these 4 output for GPIO usage without
+ attaching LEDs.
+
+ Note that output pins can be set to drive LEDs OR GPIO, mixed
+ definition are not accepted.
+
+$ref: ethernet-phy-package.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,qca8072-package
+ - qcom,qca8075-package
+
+ qcom,package-mode:
+ description: |
+ PHY package can be configured in 3 mode following this table:
+
+ First Serdes mode Second Serdes mode
+ Option 1 PSGMII for copper Disabled
+ ports 0-4
+ Option 2 PSGMII for copper 1000BASE-X / 100BASE-FX
+ ports 0-4
+ Option 3 QSGMII for copper SGMII for
+ ports 0-3 copper port 4
+
+ PSGMII mode (option 1 or 2) is configured dynamically based on
+ the presence of a connected SFP device.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum:
+ - qsgmii
+ - psgmii
+ default: psgmii
+
+ qcom,tx-drive-strength-milliwatt:
+ description: set the TX Amplifier value in mv.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [140, 160, 180, 200, 220,
+ 240, 260, 280, 300, 320,
+ 400, 500, 600]
+ default: 600
+
+patternProperties:
+ ^ethernet-phy@[a-f0-9]+$:
+ $ref: ethernet-phy.yaml#
+
+ properties:
+ qcom,dac-full-amplitude:
+ description:
+ Set Analog MDI driver amplitude to FULL.
+
+ With this not defined, amplitude is set to DSP.
+ (amplitude is adjusted based on cable length)
+
+ With this enabled and qcom,dac-full-bias-current
+ and qcom,dac-disable-bias-current-tweak disabled,
+ bias current is half.
+ type: boolean
+
+ qcom,dac-full-bias-current:
+ description:
+ Set Analog MDI driver bias current to FULL.
+
+ With this not defined, bias current is set to DSP.
+ (bias current is adjusted based on cable length)
+
+ Actual bias current might be different with
+ qcom,dac-disable-bias-current-tweak disabled.
+ type: boolean
+
+ qcom,dac-disable-bias-current-tweak:
+ description: |
+ Set Analog MDI driver bias current to disable tweak
+ to bias current.
+
+ With this not defined, bias current tweak are enabled
+ by default.
+
+ With this enabled the following tweak are NOT applied:
+ - With both FULL amplitude and FULL bias current: bias current
+ is set to half.
+ - With only DSP amplitude: bias current is set to half and
+ is set to 1/4 with cable < 10m.
+ - With DSP bias current (included both DSP amplitude and
+ DSP bias current): bias current is half the detected current
+ with cable < 10m.
+ type: boolean
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ if:
+ required:
+ - gpio-controller
+ then:
+ properties:
+ leds: false
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy-package@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,qca8075-package";
+ reg = <0>;
+
+ qcom,package-mode = "qsgmii";
+
+ ethernet-phy@0 {
+ reg = <0>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+
+ ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ ethernet-phy@2 {
+ reg = <2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ethernet-phy@3 {
+ reg = <3>;
+ };
+
+ ethernet-phy@4 {
+ reg = <4>;
+ };
+ };
+ };
- enum:
- renesas,etheravb-r8a779a0 # R-Car V3U
- renesas,etheravb-r8a779g0 # R-Car V4H
+ - renesas,etheravb-r8a779h0 # R-Car V4M
- const: renesas,etheravb-rcar-gen4 # R-Car Gen4
- items:
- snps,dwmac-5.20
- snps,dwxgmac
- snps,dwxgmac-2.10
+ - starfive,jh7100-dwmac
- starfive,jh7110-dwmac
reg:
- description: Combined signal for various interrupt events
- description: The interrupt to manage the remote wake-up packet detection
- description: The interrupt that occurs when Rx exits the LPI state
+ - description: The interrupt that occurs when HW safety error triggered
interrupt-names:
minItems: 1
items:
- const: macirq
- - enum: [eth_wake_irq, eth_lpi]
- - const: eth_lpi
+ - enum: [eth_wake_irq, eth_lpi, sfty]
+ - enum: [eth_wake_irq, eth_lpi, sfty]
+ - enum: [eth_wake_irq, eth_lpi, sfty]
clocks:
minItems: 1
- description: AHB reset
reset-names:
- minItems: 1
- items:
- - const: stmmaceth
- - const: ahb
+ oneOf:
+ - items:
+ - enum: [stmmaceth, ahb]
+ - items:
+ - const: stmmaceth
+ - const: ahb
power-domains:
maxItems: 1
compatible:
contains:
enum:
+ - starfive,jh7100-dwmac
- starfive,jh7110-dwmac
required:
- compatible
properties:
compatible:
- items:
- - enum:
- - starfive,jh7110-dwmac
- - const: snps,dwmac-5.20
+ oneOf:
+ - items:
+ - const: starfive,jh7100-dwmac
+ - const: snps,dwmac
+ - items:
+ - const: starfive,jh7110-dwmac
+ - const: snps,dwmac-5.20
reg:
maxItems: 1
- const: tx
- const: gtx
- interrupts:
- minItems: 3
- maxItems: 3
-
- interrupt-names:
- minItems: 3
- maxItems: 3
-
- resets:
- items:
- - description: MAC Reset signal.
- - description: AHB Reset signal.
-
- reset-names:
- items:
- - const: stmmaceth
- - const: ahb
-
starfive,tx-use-rgmii-clk:
description:
Tx clock is provided by external rgmii clock.
allOf:
- $ref: snps,dwmac.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7100-dwmac
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ interrupt-names:
+ minItems: 2
+ maxItems: 2
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: ahb
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-dwmac
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
+ interrupt-names:
+ minItems: 3
+ maxItems: 3
+
+ resets:
+ minItems: 2
+
+ reset-names:
+ minItems: 2
+
unevaluatedProperties: false
examples:
title: TI SoC Ethernet Switch Controller (CPSW)
maintainers:
- - Grygorii Strashko <grygorii.strashko@ti.com>
- - Sekhar Nori <nsekhar@ti.com>
+ - Siddharth Vadapalli <s-vadapalli@ti.com>
+ - Ravi Gunasekaran <r-gunasekaran@ti.com>
+ - Roger Quadros <rogerq@kernel.org>
description:
The 3-port switch gigabit ethernet subsystem provides ethernet packet
for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
to transmit data.
+ ti,cfg-dac-minus-one-bp:
+ description: |
+ DP83826 PHY only.
+ Sets the voltage ratio (with respect to the nominal value)
+ of the logical level -1 for the MLT-3 encoded TX data.
+ enum: [5000, 5625, 6250, 6875, 7500, 8125, 8750, 9375, 10000,
+ 10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000]
+ default: 10000
+
+ ti,cfg-dac-plus-one-bp:
+ description: |
+ DP83826 PHY only.
+ Sets the voltage ratio (with respect to the nominal value)
+ of the logical level +1 for the MLT-3 encoded TX data.
+ enum: [5000, 5625, 6250, 6875, 7500, 8125, 8750, 9375, 10000,
+ 10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000]
+ default: 10000
+
+ ti,rmii-mode:
+ description: |
+ If present, select the RMII operation mode. Two modes are
+ available:
+ - RMII master, where the PHY outputs a 50MHz reference clock which can
+ be connected to the MAC.
+ - RMII slave, where the PHY expects a 50MHz reference clock input
+ shared with the MAC.
+ The RMII operation mode can also be configured by its straps.
+ If the strap pin is not set correctly or not set at all, then this can be
+ used to configure it.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum:
+ - master
+ - slave
+
required:
- reg
title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller)
maintainers:
- - Grygorii Strashko <grygorii.strashko@ti.com>
- - Sekhar Nori <nsekhar@ti.com>
+ - Siddharth Vadapalli <s-vadapalli@ti.com>
+ - Ravi Gunasekaran <r-gunasekaran@ti.com>
+ - Roger Quadros <rogerq@kernel.org>
description:
The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module
maintainers:
- - Grygorii Strashko <grygorii.strashko@ti.com>
- - Sekhar Nori <nsekhar@ti.com>
+ - Siddharth Vadapalli <s-vadapalli@ti.com>
+ - Ravi Gunasekaran <r-gunasekaran@ti.com>
+ - Roger Quadros <rogerq@kernel.org>
description: |+
The TI AM654x/J721E CPTS module is used to facilitate host control of time
Alternatively, it can specify the wireless part of the MT7628/MT7688
or MT7622/MT7986 SoC.
-allOf:
- - $ref: ieee80211.yaml#
-
properties:
compatible:
enum:
MT7986 should contain 3 regions consys, dcm, and sku, in this order.
interrupts:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: major interrupt for rings
+ - description: additional interrupt for ring 19
+ - description: additional interrupt for ring 4
+ - description: additional interrupt for ring 5
power-domains:
maxItems: 1
- compatible
- reg
+allOf:
+ - $ref: ieee80211.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt7981-wmac
+ - mediatek,mt7986-wmac
+ then:
+ properties:
+ interrupts:
+ minItems: 4
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+
unevaluatedProperties: false
examples:
reg = <0x18000000 0x1000000>,
<0x10003000 0x1000>,
<0x11d10000 0x1000>;
- interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen 50>,
<&topckgen 62>;
clock-names = "mcu", "ap2conn";
maintainers:
- Kalle Valo <kvalo@kernel.org>
+ - Jeff Johnson <jjohnson@kernel.org>
description:
Qualcomm Technologies, Inc. IEEE 802.11ac devices.
maintainers:
- Kalle Valo <kvalo@kernel.org>
+ - Jeff Johnson <jjohnson@kernel.org>
description: |
Qualcomm Technologies IEEE 802.11ax PCIe devices
maintainers:
- Kalle Valo <kvalo@kernel.org>
+ - Jeff Johnson <jjohnson@kernel.org>
description: |
These are dt entries for Qualcomm Technologies, Inc. IEEE 802.11ax
allOf:
- if:
+ properties:
+ compatible:
+ contains:
+ const: mac-base
required: [ compatible ]
then:
- if:
- properties:
- compatible:
- contains:
- const: mac-base
- then:
- properties:
- "#nvmem-cell-cells":
- description: The first argument is a MAC address offset.
- const: 1
- required:
- - "#nvmem-cell-cells"
+ properties:
+ "#nvmem-cell-cells":
+ description: The first argument is a MAC address offset.
+ const: 1
+ required:
+ - "#nvmem-cell-cells"
required:
- reg
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/nvmem-provider.yaml#
+$schema: http://devicetree.org/meta-schemas/base.yaml#
+
+title: NVMEM (Non Volatile Memory) Provider
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+select: true
+
+properties:
+ '#nvmem-cell-cells':
+ enum: [0, 1]
+
+additionalProperties: true
+++ /dev/null
---------------------------------------------------------------------------
-= Zynq UltraScale+ MPSoC nvmem firmware driver binding =
---------------------------------------------------------------------------
-The nvmem_firmware node provides access to the hardware related data
-like soc revision, IDCODE... etc, By using the firmware interface.
-
-Required properties:
-- compatible: should be "xlnx,zynqmp-nvmem-fw"
-
-= Data cells =
-Are child nodes of silicon id, bindings of which as described in
-bindings/nvmem/nvmem.txt
-
--------
- Example
--------
-firmware {
- zynqmp_firmware: zynqmp-firmware {
- compatible = "xlnx,zynqmp-firmware";
- method = "smc";
-
- nvmem_firmware {
- compatible = "xlnx,zynqmp-nvmem-fw";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* Data cells */
- soc_revision: soc_revision {
- reg = <0x0 0x4>;
- };
- };
- };
-};
-
-= Data consumers =
-Are device nodes which consume nvmem data cells.
-
-For example:
- pcap {
- ...
-
- nvmem-cells = <&soc_revision>;
- nvmem-cell-names = "soc_revision";
-
- ...
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Zynq UltraScale+ MPSoC Non Volatile Memory interface
+
+description: |
+ The ZynqMP MPSoC provides access to the hardware related data
+ like SOC revision, IDCODE and specific purpose efuses.
+
+maintainers:
+ - Kalyani Akula <kalyani.akula@amd.com>
+ - Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
+
+allOf:
+ - $ref: nvmem.yaml#
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-nvmem-fw
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ nvmem {
+ compatible = "xlnx,zynqmp-nvmem-fw";
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc_revision: soc-revision@0 {
+ reg = <0x0 0x4>;
+ };
+ };
+ };
specific binding.
minItems: 1
maxItems: 32
- items:
- maxItems: 1
opp-microvolt:
description: |
- {}
- const: pcie_phy
- const: pcie_aux
- - if:
- properties:
- compatible:
- not:
- contains:
- enum:
- - fsl,imx6sx-pcie
- - fsl,imx8mq-pcie
- - fsl,imx6sx-pcie-ep
- - fsl,imx8mq-pcie-ep
- then:
- properties:
- clocks:
- maxItems: 3
- clock-names:
- maxItems: 3
- if:
properties:
- fsl,imx6sx-pcie
- fsl,imx6q-pcie
- fsl,imx6qp-pcie
+ - fsl,imx95-pcie
- fsl,imx6sx-pcie-ep
- fsl,imx6q-pcie-ep
- fsl,imx6qp-pcie-ep
- fsl,imx8mm-pcie-ep
- fsl,imx8mq-pcie-ep
- fsl,imx8mp-pcie-ep
-
- reg:
- minItems: 2
-
- reg-names:
- items:
- - const: dbi
- - const: addr_space
+ - fsl,imx95-pcie-ep
clocks:
minItems: 3
allOf:
- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx8mm-pcie-ep
+ - fsl,imx8mq-pcie-ep
+ - fsl,imx8mp-pcie-ep
+ then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+ reg-names:
+ items:
+ - const: dbi
+ - const: addr_space
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx95-pcie-ep
+ then:
+ properties:
+ reg:
+ minItems: 6
+ maxItems: 6
+ reg-names:
+ items:
+ - const: dbi
+ - const: atu
+ - const: dbi2
+ - const: app
+ - const: dma
+ - const: addr_space
+
- if:
properties:
compatible:
enum:
- fsl,imx8mq-pcie-ep
+ - fsl,imx95-pcie-ep
then:
properties:
clocks:
- fsl,imx8mq-pcie
- fsl,imx8mm-pcie
- fsl,imx8mp-pcie
-
- reg:
- items:
- - description: Data Bus Interface (DBI) registers.
- - description: PCIe configuration space region.
-
- reg-names:
- items:
- - const: dbi
- - const: config
+ - fsl,imx95-pcie
clocks:
minItems: 3
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx6q-pcie
+ - fsl,imx6sx-pcie
+ - fsl,imx6qp-pcie
+ - fsl,imx7d-pcie
+ - fsl,imx8mq-pcie
+ - fsl,imx8mm-pcie
+ - fsl,imx8mp-pcie
+ then:
+ properties:
+ reg:
+ maxItems: 2
+ reg-names:
+ items:
+ - const: dbi
+ - const: config
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx95-pcie
+ then:
+ properties:
+ reg:
+ minItems: 4
+ maxItems: 4
+ reg-names:
+ items:
+ - const: dbi
+ - const: config
+ - const: atu
+ - const: app
+
- if:
properties:
compatible:
compatible:
enum:
- fsl,imx8mq-pcie
+ - fsl,imx95-pcie
then:
properties:
clocks:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm PCI Express Root Complex Common Properties
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+properties:
+ reg:
+ minItems: 4
+ maxItems: 6
+
+ reg-names:
+ minItems: 4
+ maxItems: 6
+
+ interrupts:
+ minItems: 1
+ maxItems: 8
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 8
+
+ iommu-map:
+ minItems: 1
+ maxItems: 16
+
+ clocks:
+ minItems: 3
+ maxItems: 13
+
+ clock-names:
+ minItems: 3
+ maxItems: 13
+
+ dma-coherent: true
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: pcie-mem
+ - const: cpu-pcie
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: pciephy
+
+ power-domains:
+ maxItems: 1
+
+ required-opps:
+ maxItems: 1
+
+ resets:
+ minItems: 1
+ maxItems: 12
+
+ reset-names:
+ minItems: 1
+ maxItems: 12
+
+ perst-gpios:
+ description: GPIO controlled connection to PERST# signal
+ maxItems: 1
+
+ wake-gpios:
+ description: GPIO controlled connection to WAKE# signal
+ maxItems: 1
+
+required:
+ - reg
+ - reg-names
+ - interrupt-map-mask
+ - interrupt-map
+ - clocks
+ - clock-names
+
+anyOf:
+ - required:
+ - interrupts
+ - interrupt-names
+ - "#interrupt-cells"
+ - required:
+ - msi-map
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+additionalProperties: true
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SA8775p PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,pcie-sa8775p
+
+ reg:
+ minItems: 6
+ maxItems: 6
+
+ reg-names:
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 5
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+
+ interrupts:
+ minItems: 8
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+required:
+ - interconnects
+ - interconnect-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sa8775p";
+ reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x40000000 0x0 0xf20>,
+ <0x0 0x40000f20 0x0 0xa8>,
+ <0x0 0x40001000 0x0 0x4000>,
+ <0x0 0x40100000 0x0 0x100000>,
+ <0x0 0x01c03000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ dma-coherent;
+
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
+ <0x100 &pcie_smmu 0x0001 0x1>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC7280 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,pcie-sc7280
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 13
+ maxItems: 13
+
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: pipe_mux # PIPE MUX
+ - const: phy_pipe # PIPE output clock
+ - const: ref # REFERENCE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ items:
+ - const: msi
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+ vddpe-3v3-supply:
+ description: PCIe endpoint power supply
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sc7280.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c08000 {
+ compatible = "qcom,pcie-sc7280";
+ reg = <0 0x01c08000 0 0x3000>,
+ <0 0x40000000 0 0xf1d>,
+ <0 0x40000f20 0 0xa8>,
+ <0 0x40001000 0 0x1000>,
+ <0 0x40100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ num-lanes = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
+ <&pcie1_phy>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
+
+ clock-names = "pipe",
+ "pipe_mux",
+ "phy_pipe",
+ "ref",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ddrss_sf_tbu",
+ "aggre0",
+ "aggre1";
+
+ dma-coherent;
+
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+ <0x100 &apps_smmu 0x1c81 0x1>;
+
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_clkreq_n>;
+
+ power-domains = <&gcc GCC_PCIE_1_GDSC>;
+
+ resets = <&gcc GCC_PCIE_1_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ vddpe-3v3-supply = <&pp3300_ssd>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC8180x PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,pcie-sc8180x
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 8
+ maxItems: 8
+
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ref # REFERENCE clock
+ - const: tbu # PCIe TBU clock
+
+ interrupts:
+ minItems: 8
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
+ #include <dt-bindings/interconnect/qcom,sc8180x.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sc8180x";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
+ ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_PCIE_0_CLKREF_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ref",
+ "tbu";
+
+ dma-coherent;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
+ <0x100 &apps_smmu 0x1d81 0x1>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC8280XP PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-sa8540p
+ - qcom,pcie-sc8280xp
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 8
+ maxItems: 9
+
+ clock-names:
+ minItems: 8
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: noc_aggr_4 # NoC aggregate 4 clock
+ - const: noc_aggr_south_sf # NoC aggregate South SF clock
+ - const: cnoc_qx # Configuration NoC QX clock
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+ vddpe-3v3-supply:
+ description: A phandle to the PCIe endpoint power supply
+
+required:
+ - interconnects
+ - interconnect-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sc8280xp
+ then:
+ properties:
+ interrupts:
+ minItems: 4
+ maxItems: 4
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: msi
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sc8280xp.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c20000 {
+ compatible = "qcom,pcie-sc8280xp";
+ reg = <0x0 0x01c20000 0x0 0x3000>,
+ <0x0 0x3c000000 0x0 0xf1d>,
+ <0x0 0x3c000f20 0x0 0xa8>,
+ <0x0 0x3c001000 0x0 0x1000>,
+ <0x0 0x3c100000 0x0 0x100000>,
+ <0x0 0x01c23000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
+ <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <2>;
+ num-lanes = <4>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+ clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
+ <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr_4",
+ "noc_aggr_south_sf";
+
+ dma-coherent;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ phys = <&pcie2a_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie2a_default>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_2A_GDSC>;
+
+ resets = <&gcc GCC_PCIE_2A_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+ vddpe-3v3-supply = <&vreg_nvme>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8150 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,pcie-sm8150
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 8
+ maxItems: 8
+
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ref # REFERENCE clock
+
+ interrupts:
+ minItems: 8
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8150.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sm8150.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sm8150";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ref";
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
+ <0x100 &apps_smmu 0x1d81 0x1>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8250 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,pcie-sm8250
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 8
+ maxItems: 9
+
+ clock-names:
+ # Unfortunately the "optional" ref clock is used in the middle of the list
+ oneOf:
+ - items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ref # REFERENCE clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+
+ interrupts:
+ minItems: 8
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8250.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sm8250.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sm8250";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>,
+ <0 0x01c03000 0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ddrss_sf_tbu";
+
+ dma-coherent;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8350.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,pcie-sm8350
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 8
+ maxItems: 9
+
+ clock-names:
+ minItems: 8
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
+ - const: aggre0 # Aggre NoC PCIe0 AXI clock
+
+ interrupts:
+ minItems: 8
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+oneOf:
+ - properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: msi
+
+ - properties:
+ interrupts:
+ minItems: 8
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8350.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sm8350.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sm8350";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ddrss_sf_tbu",
+ "aggre1",
+ "aggre0";
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8450 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-sm8450-pcie0
+ - qcom,pcie-sm8450-pcie1
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 11
+ maxItems: 12
+
+ clock-names:
+ minItems: 11
+ items:
+ - const: pipe # PIPE clock
+ - const: pipe_mux # PIPE MUX
+ - const: phy_pipe # PIPE output clock
+ - const: ref # REFERENCE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - enum: [aggre0, aggre1] # Aggre NoC PCIe0/1 AXI clock
+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
+
+ interrupts:
+ minItems: 8
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8450.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sm8450.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sm8450-pcie0";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
+ <&pcie0_phy>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
+ clock-names = "pipe",
+ "pipe_mux",
+ "phy_pipe",
+ "ref",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "aggre0",
+ "aggre1";
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ msi-map = <0x0 &gic_its 0x5981 0x1>,
+ <0x100 &gic_its 0x5980 0x1>;
+ msi-map-mask = <0xff00>;
+
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8550 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
+ the Synopsys DesignWare PCIe IP.
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,pcie-sm8550
+ - items:
+ - enum:
+ - qcom,pcie-sm8650
+ - const: qcom,pcie-sm8550
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 7
+ maxItems: 8
+
+ clock-names:
+ minItems: 7
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: noc_aggr # Aggre NoC PCIe AXI clock
+ - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
+
+ interrupts:
+ minItems: 8
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
+ items:
+ - const: pci # PCIe core reset
+ - const: link_down # PCIe link down reset
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm8550-gcc.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sm8550";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr";
+
+ dma-coherent;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
+ <0x100 &apps_smmu 0x1401 0x1>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm X1E80100 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
+ the Synopsys DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,pcie-x1e80100
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 7
+ maxItems: 7
+
+ clock-names:
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: noc_aggr # Aggre NoC PCIe AXI clock
+ - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
+
+ interrupts:
+ minItems: 8
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
+ items:
+ - const: pci # PCIe core reset
+ - const: link_down # PCIe link down reset
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c08000 {
+ compatible = "qcom,pcie-x1e80100";
+ reg = <0 0x01c08000 0 0x3000>,
+ <0 0x7c000000 0 0xf1d>,
+ <0 0x7c000f40 0 0xa8>,
+ <0 0x7c001000 0 0x1000>,
+ <0 0x7c100000 0 0x100000>,
+ <0 0x01c0b000 0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
+ <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
+ <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ dma-coherent;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interconnects = <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_4 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
+ <0x100 &apps_smmu 0x1401 0x1>;
+
+ phys = <&pcie4_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc GCC_PCIE_4_GDSC>;
+
+ resets = <&gcc GCC_PCIE_4_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ };
+ };
- qcom,pcie-ipq8074-gen3
- qcom,pcie-msm8996
- qcom,pcie-qcs404
- - qcom,pcie-sa8540p
- - qcom,pcie-sa8775p
- - qcom,pcie-sc7280
- - qcom,pcie-sc8180x
- - qcom,pcie-sc8280xp
- qcom,pcie-sdm845
- qcom,pcie-sdx55
- - qcom,pcie-sm8150
- - qcom,pcie-sm8250
- - qcom,pcie-sm8350
- - qcom,pcie-sm8450-pcie0
- - qcom,pcie-sm8450-pcie1
- - qcom,pcie-sm8550
- - items:
- - enum:
- - qcom,pcie-sm8650
- - const: qcom,pcie-sm8550
- items:
- const: qcom,pcie-msm8998
- const: qcom,pcie-msm8996
vdda_refclk-supply:
description: A phandle to the core analog power supply for IC which generates reference clock
- vddpe-3v3-supply:
- description: A phandle to the PCIe endpoint power supply
-
phys:
maxItems: 1
description: GPIO controlled connection to PERST# signal
maxItems: 1
+ required-opps:
+ maxItems: 1
+
wake-gpios:
description: GPIO controlled connection to WAKE# signal
maxItems: 1
- "#interrupt-cells"
- required:
- msi-map
- - msi-map-mask
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
compatible:
contains:
enum:
- - qcom,pcie-sa8775p
- - qcom,pcie-sc7280
- - qcom,pcie-sc8180x
- - qcom,pcie-sc8280xp
- qcom,pcie-sdx55
- - qcom,pcie-sm8250
- - qcom,pcie-sm8350
- - qcom,pcie-sm8450-pcie0
- - qcom,pcie-sm8450-pcie1
- - qcom,pcie-sm8550
then:
properties:
reg:
- const: pwr # PWR reset
- const: ahb # AHB reset
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sc7280
- then:
- properties:
- clocks:
- minItems: 13
- maxItems: 13
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: pipe_mux # PIPE MUX
- - const: phy_pipe # PIPE output clock
- - const: ref # REFERENCE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: tbu # PCIe TBU clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
- - const: aggre1 # Aggre NoC PCIe1 AXI clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sc8180x
- then:
- properties:
- clocks:
- minItems: 8
- maxItems: 8
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: ref # REFERENCE clock
- - const: tbu # PCIe TBU clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- if:
properties:
compatible:
items:
- const: pci # PCIe core reset
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sm8150
- then:
- properties:
- clocks:
- minItems: 8
- maxItems: 8
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: tbu # PCIe TBU clock
- - const: ref # REFERENCE clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sm8250
- then:
- oneOf:
- # Unfortunately the "optional" ref clock is used in the middle of the list
- - properties:
- clocks:
- minItems: 9
- maxItems: 9
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: ref # REFERENCE clock
- - const: tbu # PCIe TBU clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - properties:
- clocks:
- minItems: 8
- maxItems: 8
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: tbu # PCIe TBU clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- properties:
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sm8350
- then:
- properties:
- clocks:
- minItems: 8
- maxItems: 9
- clock-names:
- minItems: 8
- items:
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: tbu # PCIe TBU clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - const: aggre1 # Aggre NoC PCIe1 AXI clock
- - const: aggre0 # Aggre NoC PCIe0 AXI clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sm8450-pcie0
- then:
- properties:
- clocks:
- minItems: 12
- maxItems: 12
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: pipe_mux # PIPE MUX
- - const: phy_pipe # PIPE output clock
- - const: ref # REFERENCE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - const: aggre0 # Aggre NoC PCIe0 AXI clock
- - const: aggre1 # Aggre NoC PCIe1 AXI clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sm8450-pcie1
- then:
- properties:
- clocks:
- minItems: 11
- maxItems: 11
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: pipe_mux # PIPE MUX
- - const: phy_pipe # PIPE output clock
- - const: ref # REFERENCE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - const: aggre1 # Aggre NoC PCIe1 AXI clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sm8550
- then:
- properties:
- clocks:
- minItems: 7
- maxItems: 8
- clock-names:
- minItems: 7
- items:
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - const: noc_aggr # Aggre NoC PCIe AXI clock
- - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
- resets:
- minItems: 1
- maxItems: 2
- reset-names:
- minItems: 1
- items:
- - const: pci # PCIe core reset
- - const: link_down # PCIe link down reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sa8540p
- - qcom,pcie-sc8280xp
- then:
- properties:
- clocks:
- minItems: 8
- maxItems: 9
- clock-names:
- minItems: 8
- items:
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - const: noc_aggr_4 # NoC aggregate 4 clock
- - const: noc_aggr_south_sf # NoC aggregate South SF clock
- - const: cnoc_qx # Configuration NoC QX clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- if:
properties:
compatible:
items:
- const: pci # PCIe core reset
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sa8775p
- then:
- properties:
- clocks:
- minItems: 5
- maxItems: 5
- clock-names:
- items:
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sa8540p
- - qcom,pcie-sa8775p
- - qcom,pcie-sc8280xp
- then:
- required:
- - interconnects
- - interconnect-names
-
- if:
not:
properties:
contains:
enum:
- qcom,pcie-msm8996
- - qcom,pcie-sa8775p
- - qcom,pcie-sc7280
- - qcom,pcie-sc8180x
- qcom,pcie-sdm845
- - qcom,pcie-sm8150
- - qcom,pcie-sm8250
- - qcom,pcie-sm8350
- - qcom,pcie-sm8450-pcie0
- - qcom,pcie-sm8450-pcie1
- - qcom,pcie-sm8550
then:
oneOf:
- properties:
- const: msi6
- const: msi7
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sc8280xp
- then:
- properties:
- interrupts:
- minItems: 4
- maxItems: 4
- interrupt-names:
- items:
- - const: msi0
- - const: msi1
- - const: msi2
- - const: msi3
-
- if:
properties:
compatible:
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
- qcom,pcie-qcs404
- - qcom,pcie-sa8540p
then:
properties:
interrupts:
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/arm,coresight-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm Coresight Performance Monitoring Unit Architecture
+
+maintainers:
+ - Robin Murphy <robin.murphy@arm.com>
+
+properties:
+ compatible:
+ const: arm,coresight-pmu
+
+ reg:
+ items:
+ - description: Register page 0
+ - description: Register page 1, if the PMU implements the dual-page extension
+ minItems: 1
+
+ interrupts:
+ items:
+ - description: Overflow interrupt
+
+ cpus:
+ description: If the PMU is associated with a particular CPU or subset of CPUs,
+ array of phandles to the appropriate CPU node(s)
+
+ reg-io-width:
+ description: Granularity at which PMU register accesses are single-copy atomic
+ default: 4
+ enum: [4, 8]
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/starfive,jh8100-starlink-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH8100 StarLink PMU
+
+maintainers:
+ - Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
+
+description:
+ StarFive's JH8100 StarLink PMU integrates one or more CPU cores with a
+ shared L3 memory system. The PMU support overflow interrupt, up to
+ 16 programmable 64bit event counters, and an independent 64bit cycle
+ counter. StarFive's JH8100 StarLink PMU is accessed via MMIO.
+
+properties:
+ compatible:
+ const: starfive,jh8100-starlink-pmu
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pmu@12900000 {
+ compatible = "starfive,jh8100-starlink-pmu";
+ reg = <0x0 0x12900000 0x0 0x10000>;
+ interrupts = <34>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2023 MediaTek, BayLibre
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Sensor Interface MIPI CSI CD-PHY
+
+maintainers:
+ - Julien Stephan <jstephan@baylibre.com>
+ - Andy Hsieh <andy.hsieh@mediatek.com>
+
+description:
+ The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
+ receivers. The number of PHYs depends on the SoC model.
+ Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
+ capable.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8365-csi-rx
+
+ reg:
+ maxItems: 1
+
+ num-lanes:
+ enum: [2, 3, 4]
+
+ '#phy-cells':
+ enum: [0, 1]
+ description: |
+ If the PHY doesn't support mode selection then #phy-cells must be 0 and
+ PHY mode is described using phy-type property.
+ If the PHY supports mode selection, then #phy-cells must be 1 and mode
+ is set in the PHY cells. Supported modes are:
+ - PHY_TYPE_DPHY
+ - PHY_TYPE_CPHY
+ See include/dt-bindings/phy/phy.h for constants.
+
+ phy-type:
+ description:
+ If the PHY doesn't support mode selection then this set the operating mode.
+ See include/dt-bindings/phy/phy.h for constants.
+ const: 10
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - reg
+ - num-lanes
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ csi0_rx: phy@11c10000 {
+ compatible = "mediatek,mt8365-csi-rx";
+ reg = <0 0x11c10000 0 0x2000>;
+ num-lanes = <2>;
+ #phy-cells = <1>;
+ };
+
+ csi1_rx: phy@11c12000 {
+ compatible = "mediatek,mt8365-csi-rx";
+ reg = <0 0x11c12000 0 0x2000>;
+ phy-type = <PHY_TYPE_DPHY>;
+ num-lanes = <2>;
+ #phy-cells = <0>;
+ };
+ };
+...
compatible:
enum:
- cdns,torrent-phy
+ - ti,j7200-serdes-10g
- ti,j721e-serdes-10g
'#address-cells':
minItems: 1
maxItems: 2
description:
- PHY reference clock for 1 item. Must contain an entry in clock-names.
- Optional Parent to enable output reference clock.
+ PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
+ pll1_refclk is optional and used for multi-protocol configurations requiring
+ separate reference clock for each protocol.
+ Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.
+ Optional parent clock (phy_en_refclk) to enable a reference clock output feature
+ on some platforms to output either derived or received reference clock.
clock-names:
minItems: 1
items:
- const: refclk
- - const: phy_en_refclk
+ - enum: [ pll1_refclk, phy_en_refclk ]
reg:
minItems: 1
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-usb3-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QMP PHY controller (USB, MSM8998)
+
+maintainers:
+ - Vinod Koul <vkoul@kernel.org>
+
+description:
+ The QMP PHY controller supports physical layer functionality for USB-C on
+ several Qualcomm chipsets.
+
+properties:
+ compatible:
+ enum:
+ - qcom,msm8998-qmp-usb3-phy
+ - qcom,qcm2290-qmp-usb3-phy
+ - qcom,sdm660-qmp-usb3-phy
+ - qcom,sm6115-qmp-usb3-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ maxItems: 4
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: phy
+ - const: phy_phy
+
+ vdda-phy-supply: true
+
+ vdda-pll-supply: true
+
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ orientation-switch:
+ description:
+ Flag the PHY as possible handler of USB Type-C orientation switching
+ type: boolean
+
+ qcom,tcsr-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to TCSR hardware block
+ - description: offset of the VLS CLAMP register
+ description: Clamp register present in the TCSR
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output endpoint of the PHY
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Incoming endpoint from the USB controller
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+ - "#clock-cells"
+ - clock-output-names
+ - "#phy-cells"
+ - qcom,tcsr-reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-qmp-usb3-phy
+ - qcom,sdm660-qmp-usb3-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 4
+ clock-names:
+ items:
+ - const: aux
+ - const: ref
+ - const: cfg_ahb
+ - const: pipe
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcm2290-qmp-usb3-phy
+ - qcom,sm6115-qmp-usb3-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 4
+ clock-names:
+ items:
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+ - const: pipe
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8998.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ phy@c010000 {
+ compatible = "qcom,msm8998-qmp-usb3-phy";
+ reg = <0x0c010000 0x1000>;
+
+ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_CLKREF_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ vdda-phy-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l2a_1p2>;
+
+ orientation-switch;
+
+ qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ endpoint {
+ remote-endpoint = <&pmic_typec_mux_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ endpoint {
+ remote-endpoint = <&usb_dwc3_ss>;
+ };
+ };
+ };
+ };
- qcom,sm8550-qmp-gen4x2-pcie-phy
- qcom,sm8650-qmp-gen3x2-pcie-phy
- qcom,sm8650-qmp-gen4x2-pcie-phy
+ - qcom,x1e80100-qmp-gen3x2-pcie-phy
+ - qcom,x1e80100-qmp-gen4x2-pcie-phy
reg:
minItems: 1
- qcom,sm8550-qmp-gen4x2-pcie-phy
- qcom,sm8650-qmp-gen3x2-pcie-phy
- qcom,sm8650-qmp-gen4x2-pcie-phy
+ - qcom,x1e80100-qmp-gen3x2-pcie-phy
+ - qcom,x1e80100-qmp-gen4x2-pcie-phy
then:
properties:
clocks:
enum:
- qcom,sm8550-qmp-gen4x2-pcie-phy
- qcom,sm8650-qmp-gen4x2-pcie-phy
+ - qcom,x1e80100-qmp-gen3x2-pcie-phy
+ - qcom,x1e80100-qmp-gen4x2-pcie-phy
then:
properties:
resets:
- qcom,msm8996-qmp-ufs-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,sa8775p-qmp-ufs-phy
+ - qcom,sc7180-qmp-ufs-phy
- qcom,sc7280-qmp-ufs-phy
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8280xp-qmp-ufs-phy
maxItems: 1
clocks:
- minItems: 1
+ minItems: 2
maxItems: 3
clock-names:
- minItems: 1
- items:
- - const: ref
- - const: ref_aux
- - const: qref
+ minItems: 2
+ maxItems: 3
power-domains:
maxItems: 1
compatible:
contains:
enum:
+ - qcom,msm8998-qmp-ufs-phy
- qcom,sa8775p-qmp-ufs-phy
- qcom,sc7280-qmp-ufs-phy
- - qcom,sm8450-qmp-ufs-phy
- then:
- properties:
- clocks:
- minItems: 3
- clock-names:
- minItems: 3
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,msm8998-qmp-ufs-phy
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8280xp-qmp-ufs-phy
- qcom,sdm845-qmp-ufs-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8250-qmp-ufs-phy
- qcom,sm8350-qmp-ufs-phy
+ - qcom,sm8450-qmp-ufs-phy
- qcom,sm8550-qmp-ufs-phy
- qcom,sm8650-qmp-ufs-phy
then:
properties:
clocks:
- maxItems: 2
+ minItems: 3
+ maxItems: 3
clock-names:
- maxItems: 2
+ items:
+ - const: ref
+ - const: ref_aux
+ - const: qref
- if:
properties:
then:
properties:
clocks:
- maxItems: 1
+ minItems: 2
+ maxItems: 2
clock-names:
- maxItems: 1
+ items:
+ - const: ref
+ - const: qref
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sc8280xp-qmp-ufs-phy";
reg = <0x01d87000 0x1000>;
- clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
- clock-names = "ref", "ref_aux";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_REF_CLKREF_CLK>;
+
+ clock-names = "ref", "ref_aux", "qref";
power-domains = <&gcc UFS_PHY_GDSC>;
- qcom,ipq8074-qmp-usb3-phy
- qcom,ipq9574-qmp-usb3-phy
- qcom,msm8996-qmp-usb3-phy
- - qcom,msm8998-qmp-usb3-phy
- - qcom,qcm2290-qmp-usb3-phy
- qcom,sa8775p-qmp-usb3-uni-phy
- qcom,sc8280xp-qmp-usb3-uni-phy
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sdx55-qmp-usb3-uni-phy
- qcom,sdx65-qmp-usb3-uni-phy
- qcom,sdx75-qmp-usb3-uni-phy
- - qcom,sm6115-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-uni-phy
- qcom,sm8350-qmp-usb3-uni-phy
- qcom,ipq8074-qmp-usb3-phy
- qcom,ipq9574-qmp-usb3-phy
- qcom,msm8996-qmp-usb3-phy
- - qcom,msm8998-qmp-usb3-phy
- qcom,sdx55-qmp-usb3-uni-phy
- qcom,sdx65-qmp-usb3-uni-phy
- qcom,sdx75-qmp-usb3-uni-phy
- const: cfg_ahb
- const: pipe
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,qcm2290-qmp-usb3-phy
- - qcom,sm6115-qmp-usb3-phy
- then:
- properties:
- clocks:
- maxItems: 4
- clock-names:
- items:
- - const: cfg_ahb
- - const: ref
- - const: com_aux
- - const: pipe
-
- if:
properties:
compatible:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC HDMI/eDP Transmitter Combo PHY
+
+maintainers:
+ - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3588-hdptx-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Reference clock
+ - description: APB clock
+
+ clock-names:
+ items:
+ - const: ref
+ - const: apb
+
+ "#phy-cells":
+ const: 0
+
+ resets:
+ items:
+ - description: PHY reset line
+ - description: APB reset line
+ - description: INIT reset line
+ - description: CMN reset line
+ - description: LANE reset line
+ - description: ROPLL reset line
+ - description: LCPLL reset line
+
+ reset-names:
+ items:
+ - const: phy
+ - const: apb
+ - const: init
+ - const: cmn
+ - const: lane
+ - const: ropll
+ - const: lcpll
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Some PHY related data is accessed through GRF regs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+ - resets
+ - reset-names
+ - rockchip,grf
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+ #include <dt-bindings/reset/rockchip,rk3588-cru.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ phy@fed60000 {
+ compatible = "rockchip,rk3588-hdptx-phy";
+ reg = <0x0 0xfed60000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
+ clock-names = "ref", "apb";
+ #phy-cells = <0>;
+ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
+ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
+ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
+ <&cru SRST_HDPTX0_LCPLL>;
+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
+ rockchip,grf = <&hdptxphy_grf>;
+ };
+ };
- compatible
patternProperties:
- "^bank@[0-9a-z]+$":
+ "^bank@[0-9a-f]+$":
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio
unevaluatedProperties: false
- compatible
patternProperties:
- "^bank@[0-9a-z]+$":
+ "^bank@[0-9a-f]+$":
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio
unevaluatedProperties: false
- compatible
patternProperties:
- "^bank@[0-9a-z]+$":
+ "^bank@[0-9a-f]+$":
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio
unevaluatedProperties: false
- compatible
patternProperties:
- "^bank@[0-9a-z]+$":
+ "^bank@[0-9a-f]+$":
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio
unevaluatedProperties: false
- compatible
patternProperties:
- "^bank@[0-9a-z]+$":
+ "^bank@[0-9a-f]+$":
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio
unevaluatedProperties: false
Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
+ or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
For each bank the required properties are:
- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or
"microchip,sam9x60-gpio"
+ or "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"
- reg: physical base address and length of the controller's registers
- interrupts: interrupt outputs from the controller
- interrupt-controller: marks the device node as an interrupt controller
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/awinic,aw9523-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Awinic AW9523/AW9523B I2C GPIO Expander
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
+
+description: |
+ The Awinic AW9523/AW9523B I2C GPIO Expander featuring 16 multi-function
+ I/O, 256 steps PWM mode and interrupt support.
+
+properties:
+ compatible:
+ const: awinic,aw9523-pinctrl
+
+ reg:
+ maxItems: 1
+
+ '#gpio-cells':
+ description: |
+ Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-controller: true
+
+ gpio-ranges:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ interrupts:
+ maxItems: 1
+ description: Specifies the INTN pin IRQ.
+
+ '#interrupt-cells':
+ description:
+ Specifies the PIN numbers and Flags, as defined in defined in
+ include/dt-bindings/interrupt-controller/irq.h
+ const: 2
+
+ reset-gpios:
+ maxItems: 1
+
+# PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: /schemas/pinctrl/pincfg-node.yaml
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in
+ this subnode.
+ items:
+ pattern: "^gpio([0-9]|1[0-5])$"
+ minItems: 1
+ maxItems: 16
+
+ function:
+ description:
+ Specify the alternative function to be configured for the
+ specified pins.
+
+ enum: [ gpio, pwm ]
+
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ drive-open-drain: true
+ drive-push-pull: true
+ input-enable: true
+ input-disable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ # Example configuration to drive pins for a keyboard matrix
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ aw9523: gpio-expander@58 {
+ compatible = "awinic,aw9523-pinctrl";
+ reg = <0x58>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <50 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 16>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reset-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+
+ keyboard-matrix-col-pins {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15";
+ function = "gpio";
+ input-disable;
+ output-low;
+ };
+
+ keyboard-matrix-row-pins {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3",
+ "gpio4", "gpio5", "gpio6", "gpio7";
+ function = "gpio";
+ bias-pull-up;
+ drive-open-drain;
+ input-enable;
+ };
+ };
+ };
input-schmitt-disable: true
- input-debounce: true
+ input-debounce:
+ maxItems: 1
output-low: true
maxItems: 1
gpio-reserved-ranges:
- maxItems: 1
+ minItems: 1
+ maxItems: 60
vdd-supply:
description:
bias-disable: true
+ input-enable: true
+
output-high: true
output-low: true
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
vdd-supply = <&p3v3>;
- gpio-reserved-ranges = <5 1>;
+ gpio-reserved-ranges = <1 2>, <6 1>, <10 1>, <15 1>;
+
+ pinctrl-0 = <&U62160_pins>, <&U62160_ipins>;
+ pinctrl-names = "default";
+
+ U62160_pins: cfg-pins {
+ pins = "gp03", "gp16", "gp20", "gp50", "gp51";
+ function = "gpio";
+ input-enable;
+ bias-pull-up;
+ };
+
+ U62160_ipins: icfg-pins {
+ pins = "gp04", "gp17", "gp21", "gp52", "gp53";
+ function = "gpio";
+ input-enable;
+ bias-pull-up;
+ };
};
};
+++ /dev/null
-* Freescale i.MX6 UltraLite IOMUX Controller
-
-Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
-and usage.
-
-Required properties:
-- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
- "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
-- fsl,pins: each entry consists of 6 integers and represents the mux and config
- setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
- input_val> are specified using a PIN_FUNC_ID macro, which can be found in
- imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is
- the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite
- Reference Manual for detailed CONFIG settings.
-
-CONFIG bits definition:
-PAD_CTL_HYS (1 << 16)
-PAD_CTL_PUS_100K_DOWN (0 << 14)
-PAD_CTL_PUS_47K_UP (1 << 14)
-PAD_CTL_PUS_100K_UP (2 << 14)
-PAD_CTL_PUS_22K_UP (3 << 14)
-PAD_CTL_PUE (1 << 13)
-PAD_CTL_PKE (1 << 12)
-PAD_CTL_ODE (1 << 11)
-PAD_CTL_SPEED_LOW (0 << 6)
-PAD_CTL_SPEED_MED (1 << 6)
-PAD_CTL_SPEED_HIGH (3 << 6)
-PAD_CTL_DSE_DISABLE (0 << 3)
-PAD_CTL_DSE_260ohm (1 << 3)
-PAD_CTL_DSE_130ohm (2 << 3)
-PAD_CTL_DSE_87ohm (3 << 3)
-PAD_CTL_DSE_65ohm (4 << 3)
-PAD_CTL_DSE_52ohm (5 << 3)
-PAD_CTL_DSE_43ohm (6 << 3)
-PAD_CTL_DSE_37ohm (7 << 3)
-PAD_CTL_SRE_FAST (1 << 0)
-PAD_CTL_SRE_SLOW (0 << 0)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale IMX6UL IOMUX Controller
+
+maintainers:
+ - Dong Aisheng <aisheng.dong@nxp.com>
+
+description:
+ Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
+ for common binding part and usage.
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx6ul-iomuxc
+ - fsl,imx6ull-iomuxc-snvs
+
+ reg:
+ maxItems: 1
+
+# Client device subnode's properties
+patternProperties:
+ 'grp$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+
+ properties:
+ fsl,pins:
+ description:
+ each entry consists of 6 integers and represents the mux and config
+ setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
+ mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
+ be found in <arch/arm/boot/dts/imx6ul-pinfunc.h>. The last integer
+ CONFIG is the pad setting value like pull-up on this pin. Please
+ refer to i.MX6UL Reference Manual for detailed CONFIG settings.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ items:
+ - description: |
+ "mux_reg" indicates the offset of mux register.
+ - description: |
+ "conf_reg" indicates the offset of pad configuration register.
+ - description: |
+ "input_reg" indicates the offset of select input register.
+ - description: |
+ "mux_val" indicates the mux value to be applied.
+ - description: |
+ "input_val" indicates the select input value to be applied.
+ - description: |
+ "pad_setting" indicates the pad configuration value to be applied:
+ PAD_CTL_HYS (1 << 16)
+ PAD_CTL_PUS_100K_DOWN (0 << 14)
+ PAD_CTL_PUS_47K_UP (1 << 14)
+ PAD_CTL_PUS_100K_UP (2 << 14)
+ PAD_CTL_PUS_22K_UP (3 << 14)
+ PAD_CTL_PUE (1 << 13)
+ PAD_CTL_PKE (1 << 12)
+ PAD_CTL_ODE (1 << 11)
+ PAD_CTL_SPEED_LOW (0 << 6)
+ PAD_CTL_SPEED_MED (1 << 6)
+ PAD_CTL_SPEED_HIGH (3 << 6)
+ PAD_CTL_DSE_DISABLE (0 << 3)
+ PAD_CTL_DSE_260ohm (1 << 3)
+ PAD_CTL_DSE_130ohm (2 << 3)
+ PAD_CTL_DSE_87ohm (3 << 3)
+ PAD_CTL_DSE_65ohm (4 << 3)
+ PAD_CTL_DSE_52ohm (5 << 3)
+ PAD_CTL_DSE_43ohm (6 << 3)
+ PAD_CTL_DSE_37ohm (7 << 3)
+ PAD_CTL_SRE_FAST (1 << 0)
+ PAD_CTL_SRE_SLOW (0 << 0)
+
+ required:
+ - fsl,pins
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ iomuxc: pinctrl@20e0000 {
+ compatible = "fsl,imx6ul-iomuxc";
+ reg = <0x020e0000 0x4000>;
+
+ mux_uart: uartgrp {
+ fsl,pins = <
+ 0x0084 0x0310 0x0000 0 0 0x1b0b1
+ 0x0088 0x0314 0x0624 0 3 0x1b0b1
+ >;
+ };
+ };
+ - |
+ iomuxc_snvs: pinctrl@2290000 {
+ compatible = "fsl,imx6ull-iomuxc-snvs";
+ reg = <0x02290000 0x4000>;
+
+ pinctrl_snvs_usbc_det: snvsusbcdetgrp {
+ fsl,pins = <
+ 0x0010 0x0054 0x0000 0x5 0x0 0x130b0
+ >;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobileye EyeQ5 pin controller
+
+description: >
+ The EyeQ5 pin controller handles the two pin banks of the system. It belongs
+ to a system-controller block called OLB.
+
+ Pin control is about bias (pull-down, pull-up), drive strength and muxing. Pin
+ muxing supports two functions for each pin: first is GPIO, second is
+ pin-dependent.
+
+ Pins and groups are bijective.
+
+maintainers:
+ - Grégory Clement <gregory.clement@bootlin.com>
+ - Théo Lebrun <theo.lebrun@bootlin.com>
+ - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
+
+$ref: pinctrl.yaml#
+
+properties:
+ compatible:
+ enum:
+ - mobileye,eyeq5-pinctrl
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "-pins?$":
+ type: object
+ description: Pin muxing configuration.
+ $ref: pinmux-node.yaml#
+ additionalProperties: false
+ properties:
+ pins: true
+ function:
+ enum: [gpio,
+ # Bank A
+ timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0,
+ spi1, refclk0,
+ # Bank B
+ timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0]
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ drive-strength: true
+ required:
+ - pins
+ - function
+ allOf:
+ - if:
+ properties:
+ function:
+ const: gpio
+ then:
+ properties:
+ pins:
+ items: # PA0 - PA28, PB0 - PB22
+ pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$'
+ - if:
+ properties:
+ function:
+ const: timer0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA0, PA1]
+ - if:
+ properties:
+ function:
+ const: timer1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA2, PA3]
+ - if:
+ properties:
+ function:
+ const: timer2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA4, PA5]
+ - if:
+ properties:
+ function:
+ const: timer5
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA6, PA7, PA8, PA9]
+ - if:
+ properties:
+ function:
+ const: uart0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA10, PA11]
+ - if:
+ properties:
+ function:
+ const: uart1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA12, PA13]
+ - if:
+ properties:
+ function:
+ const: can0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA14, PA15]
+ - if:
+ properties:
+ function:
+ const: can1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA16, PA17]
+ - if:
+ properties:
+ function:
+ const: spi0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA18, PA19, PA20, PA21, PA22]
+ - if:
+ properties:
+ function:
+ const: spi1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA23, PA24, PA25, PA26, PA27]
+ - if:
+ properties:
+ function:
+ const: refclk0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA28]
+ - if:
+ properties:
+ function:
+ const: timer3
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB0, PB1]
+ - if:
+ properties:
+ function:
+ const: timer4
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB2, PB3]
+ - if:
+ properties:
+ function:
+ const: timer6
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB4, PB5, PB6, PB7]
+ - if:
+ properties:
+ function:
+ const: uart2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB8, PB9]
+ - if:
+ properties:
+ function:
+ const: can2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB10, PB11]
+ - if:
+ properties:
+ function:
+ const: spi2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB12, PB13, PB14, PB15, PB16]
+ - if:
+ properties:
+ function:
+ const: spi3
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB17, PB18, PB19, PB20, PB21]
+ - if:
+ properties:
+ function:
+ const: mclk0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB22]
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
description:
Debouncing periods in microseconds, one period per interrupt
bank found in the controller
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 4
description: |
0: Low rate
1: High rate
- $ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
drive-strength:
items:
pattern: "^gpio1?[0-9]{1,2}$"
- input-debounce: true
+ input-debounce:
+ maxItems: 1
additionalProperties: false
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
-$ref: nvidia,tegra234-pinmux-common.yaml
-
properties:
compatible:
const: nvidia,tegra234-pinmux-aon
+ reg:
+ maxItems: 1
+
patternProperties:
"^pinmux(-[a-z0-9-]+)?$":
type: object
# pin groups
additionalProperties:
+ $ref: nvidia,tegra234-pinmux-common.yaml
+
properties:
nvidia,pins:
items:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
-properties:
- reg:
- items:
- - description: pinmux registers
-
-patternProperties:
- "^pinmux(-[a-z0-9-]+)?$":
- type: object
-
- # pin groups
- additionalProperties:
- $ref: nvidia,tegra-pinmux-common.yaml
- # We would typically use unevaluatedProperties here but that has the
- # downside that all the properties in the common bindings become valid
- # for all chip generations. In this case, however, we want the per-SoC
- # bindings to be able to override which of the common properties are
- # allowed, since not all pinmux generations support the same sets of
- # properties. This way, the common bindings define the format of the
- # properties but the per-SoC bindings define which of them apply to a
- # given chip.
- additionalProperties: false
- properties:
- nvidia,function:
- enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2,
- eth1, dp, eth3, i2c4, i2c7, i2c9, eqos, pe2, pe1, pe0, pe3,
- pe4, pe5, pe6, pe7, pe8, pe9, pe10, qspi0, qspi1, qpsi,
- sdmmc1, sce, soc, gpio, hdmi, ufs0, spi3, spi1, uartb, uarte,
- usb, extperiph2, extperiph1, i2c3, vi0, i2c5, uarta, uartd,
- i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc,
- dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4,
- ccla, i2s1, i2s2, i2s3, i2s8, rsvd2, dmic5, dca, displayb,
- displaya, vi1, dcb, dmic1, dmic4, i2s7, dmic2, dspk0, rsvd3,
- tsc_alt, istctrl, vi1_alt, dspk1, igpu ]
+$ref: nvidia,tegra-pinmux-common.yaml
- # out of the common properties, only these are allowed for Tegra234
- nvidia,pins: true
- nvidia,pull: true
- nvidia,tristate: true
- nvidia,schmitt: true
- nvidia,enable-input: true
- nvidia,open-drain: true
- nvidia,lock: true
- nvidia,drive-type: true
- nvidia,io-hv: true
-
- required:
- - nvidia,pins
+properties:
+ nvidia,function:
+ enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2,
+ eth1, dp, eth3, i2c4, i2c7, i2c9, eqos, pe2, pe1, pe0, pe3,
+ pe4, pe5, pe6, pe7, pe8, pe9, pe10, qspi0, qspi1, qpsi,
+ sdmmc1, sce, soc, gpio, hdmi, ufs0, spi3, spi1, uartb, uarte,
+ usb, extperiph2, extperiph1, i2c3, vi0, i2c5, uarta, uartd,
+ i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc,
+ dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4,
+ ccla, i2s1, i2s2, i2s3, i2s8, rsvd2, dmic5, dca, displayb,
+ displaya, vi1, dcb, dmic1, dmic4, i2s7, dmic2, dspk0, rsvd3,
+ tsc_alt, istctrl, vi1_alt, dspk1, igpu ]
+
+ # out of the common properties, only these are allowed for Tegra234
+ nvidia,pins: true
+ nvidia,pull: true
+ nvidia,tristate: true
+ nvidia,schmitt: true
+ nvidia,enable-input: true
+ nvidia,open-drain: true
+ nvidia,lock: true
+ nvidia,drive-type: true
+ nvidia,io-hv: true
required:
- - compatible
- - reg
+ - nvidia,pins
+
+# We would typically use unevaluatedProperties here but that has the
+# downside that all the properties in the common bindings become valid
+# for all chip generations. In this case, however, we want the per-SoC
+# bindings to be able to override which of the common properties are
+# allowed, since not all pinmux generations support the same sets of
+# properties. This way, the common bindings define the format of the
+# properties but the per-SoC bindings define which of them apply to a
+# given chip.
+additionalProperties: false
-additionalProperties: true
...
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
-$ref: nvidia,tegra234-pinmux-common.yaml
-
properties:
compatible:
const: nvidia,tegra234-pinmux
+ reg:
+ maxItems: 1
+
patternProperties:
"^pinmux(-[a-z0-9-]+)?$":
type: object
# pin groups
additionalProperties:
+ $ref: nvidia,tegra234-pinmux-common.yaml
+
properties:
nvidia,pins:
items:
description: disable schmitt-trigger mode
input-debounce:
- $ref: /schemas/types.yaml#/definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32-array
description: Takes the debounce time in usec as argument or 0 to disable
debouncing
properties:
compatible:
- const: qcom,sm4450-pinctrl
+ const: qcom,sm4450-tlmm
reg:
maxItems: 1
- renesas,pfc-r8a779a0 # R-Car V3U
- renesas,pfc-r8a779f0 # R-Car S4-8
- renesas,pfc-r8a779g0 # R-Car V4H
+ - renesas,pfc-r8a779h0 # R-Car V4M
- renesas,pfc-sh73a0 # SH-Mobile AG5
reg:
slew-rate: true
gpio-hog: true
gpios: true
+ input: true
input-enable: true
+ output-enable: true
output-high: true
output-low: true
line-name: true
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml#
+$id: http://devicetree.org/schemas/pinctrl/xlnx,pinctrl-zynq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Pinctrl
properties:
compatible:
- const: xlnx,zynq-pinctrl
+ const: xlnx,pinctrl-zynq
reg:
description: Specifies the base address and size of the SLCR space.
- |
#include <dt-bindings/pinctrl/pinctrl-zynq.h>
pinctrl0: pinctrl@700 {
- compatible = "xlnx,zynq-pinctrl";
+ compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <&slcr>;
- qcom,msm8917-rpmpd
- qcom,msm8939-rpmpd
- qcom,msm8953-rpmpd
+ - qcom,msm8974-rpmpd
+ - qcom,msm8974pro-pma8084-rpmpd
- qcom,msm8976-rpmpd
- qcom,msm8994-rpmpd
- qcom,msm8996-rpmpd
- renesas,r8a779a0-sysc # R-Car V3U
- renesas,r8a779f0-sysc # R-Car S4-8
- renesas,r8a779g0-sysc # R-Car V4H
+ - renesas,r8a779h0-sysc # R-Car V4M
reg:
maxItems: 1
Documentation/devicetree/bindings/mfd/tc3589x.txt
Documentation/devicetree/bindings/input/touchscreen/ads7846.txt
4. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
-5. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt
+5. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung,s3c6410-keypad.yaml
6. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
Examples
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/atmel,hlcdc-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel's HLCDC's PWM controller
+
+maintainers:
+ - Nicolas Ferre <nicolas.ferre@microchip.com>
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+ - Claudiu Beznea <claudiu.beznea@tuxon.dev>
+
+description:
+ The LCDC integrates a Pulse Width Modulation (PWM) Controller. This block
+ generates the LCD contrast control signal (LCD_PWM) that controls the
+ display's contrast by software. LCDC_PWM is an 8-bit PWM signal that can be
+ converted to an analog voltage with a simple passive filter. LCD display
+ panels have different backlight specifications in terms of minimum/maximum
+ values for PWM frequency. If the LCDC PWM frequency range does not match the
+ LCD display panel, it is possible to use the standalone PWM Controller to
+ drive the backlight.
+
+properties:
+ compatible:
+ const: atmel,hlcdc-pwm
+
+ "#pwm-cells":
+ const: 3
+
+required:
+ - compatible
+ - "#pwm-cells"
+
+additionalProperties: false
+++ /dev/null
-Device-Tree bindings for Atmel's HLCDC (High-end LCD Controller) PWM driver
-
-The Atmel HLCDC PWM is subdevice of the HLCDC MFD device.
-See ../mfd/atmel-hlcdc.txt for more details.
-
-Required properties:
- - compatible: value should be one of the following:
- "atmel,hlcdc-pwm"
- - pinctr-names: the pin control state names. Should contain "default".
- - pinctrl-0: should contain the pinctrl states described by pinctrl
- default.
- - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells
- bindings defined in pwm.yaml in this directory.
-
-Example:
-
- hlcdc: hlcdc@f0030000 {
- compatible = "atmel,sama5d3-hlcdc";
- reg = <0xf0030000 0x2000>;
- clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
- clock-names = "periph_clk","sys_clk", "slow_clk";
-
- hlcdc_pwm: hlcdc-pwm {
- compatible = "atmel,hlcdc-pwm";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcd_pwm>;
- #pwm-cells = <3>;
- };
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/marvell,pxa-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell PXA PWM
+
+maintainers:
+ - Duje Mihanović <duje.mihanovic@skole.hr>
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ enum:
+ - marvell,pxa250-pwm
+ - marvell,pxa270-pwm
+ - marvell,pxa168-pwm
+ - marvell,pxa910-pwm
+
+ reg:
+ # Length should be 0x10
+ maxItems: 1
+
+ "#pwm-cells":
+ # Used for specifying the period length in nanoseconds
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - "#pwm-cells"
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/pxa-clock.h>
+
+ pwm0: pwm@40b00000 {
+ compatible = "marvell,pxa250-pwm";
+ reg = <0x40b00000 0x10>;
+ #pwm-cells = <1>;
+ clocks = <&clks CLK_PWM0>;
+ };
- mediatek,mt7629-pwm
- mediatek,mt7981-pwm
- mediatek,mt7986-pwm
+ - mediatek,mt7988-pwm
- mediatek,mt8183-pwm
- mediatek,mt8365-pwm
- mediatek,mt8516-pwm
- const: main
- const: mm
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OpenCores PWM controller
+
+maintainers:
+ - William Qiu <william.qiu@starfivetech.com>
+
+description:
+ The OpenCores PTC ip core contains a PWM controller. When operating in PWM
+ mode, the PTC core generates binary signal with user-programmable low and
+ high periods. All PTC counters and registers are 32-bit.
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - starfive,jh7100-pwm
+ - starfive,jh7110-pwm
+ - starfive,jh8100-pwm
+ - const: opencores,pwm-v1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ pwm@12490000 {
+ compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
+ reg = <0x12490000 0x10000>;
+ clocks = <&clkgen 181>;
+ resets = <&rstgen 109>;
+ #pwm-cells = <3>;
+ };
maintainers:
- Heiner Kallweit <hkallweit1@gmail.com>
-allOf:
- - $ref: pwm.yaml#
-
properties:
compatible:
oneOf:
- amlogic,meson-g12a-ee-pwm
- amlogic,meson-g12a-ao-pwm-ab
- amlogic,meson-g12a-ao-pwm-cd
- - amlogic,meson-s4-pwm
+ deprecated: true
- items:
- const: amlogic,meson-gx-pwm
- const: amlogic,meson-gxbb-pwm
+ deprecated: true
- items:
- const: amlogic,meson-gx-ao-pwm
- const: amlogic,meson-gxbb-ao-pwm
+ deprecated: true
- items:
- const: amlogic,meson8-pwm
- const: amlogic,meson8b-pwm
+ deprecated: true
+ - enum:
+ - amlogic,meson8-pwm-v2
+ - amlogic,meson-s4-pwm
+ - items:
+ - enum:
+ - amlogic,meson8b-pwm-v2
+ - amlogic,meson-gxbb-pwm-v2
+ - amlogic,meson-axg-pwm-v2
+ - amlogic,meson-g12-pwm-v2
+ - const: amlogic,meson8-pwm-v2
reg:
maxItems: 1
clocks:
minItems: 1
- maxItems: 2
+ maxItems: 4
clock-names:
- oneOf:
- - items:
- - enum: [clkin0, clkin1]
- - items:
- - const: clkin0
- - const: clkin1
+ minItems: 1
+ maxItems: 2
"#pwm-cells":
const: 3
- compatible
- reg
+allOf:
+ - $ref: pwm.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,meson8-pwm
+ - amlogic,meson8b-pwm
+ - amlogic,meson-gxbb-pwm
+ - amlogic,meson-gxbb-ao-pwm
+ - amlogic,meson-axg-ee-pwm
+ - amlogic,meson-axg-ao-pwm
+ - amlogic,meson-g12a-ee-pwm
+ - amlogic,meson-g12a-ao-pwm-ab
+ - amlogic,meson-g12a-ao-pwm-cd
+ then:
+ # Obsolete historic bindings tied to the driver implementation
+ # The clocks provided here are meant to be matched with the input
+ # known (hard-coded) in the driver and used to select pwm clock
+ # source. Currently, the linux driver ignores this.
+ # This is kept to maintain ABI backward compatibility.
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ oneOf:
+ - items:
+ - enum: [clkin0, clkin1]
+ - items:
+ - const: clkin0
+ - const: clkin1
+
+ # Newer binding where clock describe the actual clock inputs of the pwm
+ # block. These are necessary but some inputs may be grounded.
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,meson8-pwm-v2
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ items:
+ - description: input clock 0 of the pwm block
+ - description: input clock 1 of the pwm block
+ - description: input clock 2 of the pwm block
+ - description: input clock 3 of the pwm block
+ clock-names: false
+ required:
+ - clocks
+
+ # Newer IP block take a single input per channel, instead of 4 inputs
+ # for both channels
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,meson-s4-pwm
+ then:
+ properties:
+ clocks:
+ items:
+ - description: input clock of PWM channel A
+ - description: input clock of PWM channel B
+ clock-names: false
+ required:
+ - clocks
+
additionalProperties: false
examples:
clock-names = "clkin0", "clkin1";
#pwm-cells = <3>;
};
+ - |
+ pwm@2000 {
+ compatible = "amlogic,meson8-pwm-v2";
+ reg = <0x1000 0x10>;
+ clocks = <&xtal>, <0>, <&fdiv4>, <&fdiv5>;
+ #pwm-cells = <3>;
+ };
+ - |
+ pwm@1000 {
+ compatible = "amlogic,meson-s4-pwm";
+ reg = <0x1000 0x10>;
+ clocks = <&pwm_src_a>, <&pwm_src_b>;
+ #pwm-cells = <3>;
+ };
+++ /dev/null
-Marvell PWM controller
-
-Required properties:
-- compatible: should be one or more of:
- - "marvell,pxa250-pwm"
- - "marvell,pxa270-pwm"
- - "marvell,pxa168-pwm"
- - "marvell,pxa910-pwm"
-- reg: Physical base address and length of the registers used by the PWM channel
- Note that one device instance must be created for each PWM that is used, so the
- length covers only the register window for one PWM output, not that of the
- entire PWM controller. Currently length is 0x10 for all supported devices.
-- #pwm-cells: Should be 1. This cell is used to specify the period in
- nanoseconds.
-
-Example PWM device node:
-
-pwm0: pwm@40b00000 {
- compatible = "marvell,pxa250-pwm";
- reg = <0x40b00000 0x10>;
- #pwm-cells = <1>;
-};
-
-Example PWM client node:
-
-backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm0 5000000>;
- ...
-}
1: HIGH
Default is LOW if nothing else is specified.
$ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
maxItems: 8
items:
enum: [0, 1]
regulator and matching GPIO configurations to achieve them. If there are
no states in the "states" array, use a fixed regulator instead.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
- maxItems: 8
+ minItems: 2
+ maxItems: 256
items:
items:
- description: Voltage in microvolts
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/infineon,ir38060.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Infineon Buck Regulators with PMBUS interfaces
+
+maintainers:
+ - Not Me.
+
+allOf:
+ - $ref: regulator.yaml#
+
+properties:
+ compatible:
+ enum:
+ - infineon,ir38060
+ - infineon,ir38064
+ - infineon,ir38164
+ - infineon,ir38263
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ regulator@34 {
+ compatible = "infineon,ir38060";
+ reg = <0x34>;
+
+ regulator-min-microvolt = <437500>;
+ regulator-max-microvolt = <1387500>;
+ };
+ };
+++ /dev/null
-MCP16502 PMIC
-
-Required properties:
-- compatible: "microchip,mcp16502"
-- reg: I2C slave address
-- lpm-gpios: GPIO for LPM pin. Note that this GPIO *must* remain high during
- suspend-to-ram, keeping the PMIC into HIBERNATE mode; this
- property is optional;
-- regulators: A node that houses a sub-node for each regulator within
- the device. Each sub-node is identified using the node's
- name. The content of each sub-node is defined by the
- standard binding for regulators; see regulator.txt.
-
-Regulators of MCP16502 PMIC:
-1) VDD_IO - Buck (1.2 - 3.7 V)
-2) VDD_DDR - Buck (0.6 - 1.85 V)
-3) VDD_CORE - Buck (0.6 - 1.85 V)
-4) VDD_OTHER - BUCK (0.6 - 1.85 V)
-5) LDO1 - LDO (1.2 - 3.7 V)
-6) LDO2 - LDO (1.2 - 3.7 V)
-
-Regulator modes:
-2 - FPWM: higher precision, higher consumption
-4 - AutoPFM: lower precision, lower consumption
-
-Each regulator is defined using the standard binding for regulators.
-
-Example:
-
-mcp16502@5b {
- compatible = "microchip,mcp16502";
- reg = <0x5b>;
- status = "okay";
- lpm-gpios = <&pioBU 7 GPIO_ACTIVE_HIGH>;
-
- regulators {
- VDD_IO {
- regulator-name = "VDD_IO";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
- regulator-initial-mode = <2>;
- regulator-allowed-modes = <2>, <4>;
- regulator-always-on;
-
- regulator-state-standby {
- regulator-on-in-suspend;
- regulator-mode = <4>;
- };
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-mode = <4>;
- };
- };
-
- VDD_DDR {
- regulator-name = "VDD_DDR";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1850000>;
- regulator-initial-mode = <2>;
- regulator-allowed-modes = <2>, <4>;
- regulator-always-on;
-
- regulator-state-standby {
- regulator-on-in-suspend;
- regulator-mode = <4>;
- };
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-mode = <4>;
- };
- };
-
- VDD_CORE {
- regulator-name = "VDD_CORE";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1850000>;
- regulator-initial-mode = <2>;
- regulator-allowed-modes = <2>, <4>;
- regulator-always-on;
-
- regulator-state-standby {
- regulator-on-in-suspend;
- regulator-mode = <4>;
- };
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-mode = <4>;
- };
- };
-
- VDD_OTHER {
- regulator-name = "VDD_OTHER";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1850000>;
- regulator-initial-mode = <2>;
- regulator-allowed-modes = <2>, <4>;
- regulator-always-on;
-
- regulator-state-standby {
- regulator-on-in-suspend;
- regulator-mode = <4>;
- };
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-mode = <4>;
- };
- };
-
- LDO1 {
- regulator-name = "LDO1";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
- regulator-always-on;
-
- regulator-state-standby {
- regulator-on-in-suspend;
- };
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- LDO2 {
- regulator-name = "LDO2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
- regulator-always-on;
-
- regulator-state-standby {
- regulator-on-in-suspend;
- };
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- };
-};
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/microchip,mcp16502.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MCP16502 - High-Performance PMIC
+
+maintainers:
+ - Andrei Simion <andrei.simion@microchip.com>
+
+description:
+ The MCP16502 is an optimally integrated PMIC compatible
+ with Microchip's eMPUs(Embedded Microprocessor Units),
+ requiring Dynamic Voltage Scaling (DVS) with the use
+ of High-Performance mode (HPM).
+
+properties:
+ compatible:
+ const: microchip,mcp16502
+
+ lpm-gpios:
+ maxItems: 1
+ description: GPIO for LPM pin.
+ Note that this GPIO must remain high during
+ suspend-to-ram, keeping the PMIC into HIBERNATE mode.
+
+ reg:
+ maxItems: 1
+
+ regulators:
+ type: object
+ additionalProperties: false
+ description: List of regulators and its properties.
+
+ patternProperties:
+ "^(VDD_(IO|CORE|DDR|OTHER)|LDO[1-2])$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ regulator-initial-mode:
+ enum: [2, 4]
+ default: 2
+ description: Initial operating mode
+
+ regulator-allowed-modes:
+ items:
+ enum: [2, 4]
+ description: Supported modes
+ 2 - FPWM higher precision, higher consumption
+ 4 - AutoPFM lower precision, lower consumption
+
+required:
+ - compatible
+ - reg
+ - regulators
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic@5b {
+ compatible = "microchip,mcp16502";
+ reg = <0x5b>;
+
+ regulators {
+ VDD_IO {
+ regulator-name = "VDD_IO";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ VDD_DDR {
+ regulator-name = "VDD_DDR";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ VDD_CORE {
+ regulator-name = "VDD_CORE";
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ VDD_OTHER {
+ regulator-name = "VDD_OTHER";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+ };
properties:
compatible:
- enum:
- - qcom,pm8150b-vbus-reg
+ oneOf:
+ - enum:
+ - qcom,pm8150b-vbus-reg
+ - items:
+ - enum:
+ - qcom,pm4125-vbus-reg
+ - qcom,pm6150-vbus-reg
+ - qcom,pmi632-vbus-reg
+ - const: qcom,pm8150b-vbus-reg
reg:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/ti,tps65132.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI TPS65132 Dual Output Power Regulators
+
+maintainers:
+ - devicetree@vger.kernel.org
+
+description: |
+ The TPS65132 is designed to supply positive/negative driven applications.
+
+ Datasheet is available at:
+ https://www.ti.com/lit/gpn/tps65132
+
+properties:
+ compatible:
+ enum:
+ - ti,tps65132
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^out[pn]$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for single regulator.
+
+ properties:
+ enable-gpios:
+ maxItems: 1
+ description:
+ GPIO specifier to enable the GPIO control (on/off) for regulator.
+
+ active-discharge-gpios:
+ maxItems: 1
+ description:
+ GPIO specifier to actively discharge the delay mechanism.
+
+ ti,active-discharge-time-us:
+ description: Regulator active discharge time in microseconds.
+
+ dependencies:
+ active-discharge-gpios: [ 'ti,active-discharge-time-us' ]
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ regulator@3e {
+ compatible = "ti,tps65132";
+ reg = <0x3e>;
+
+ outp {
+ regulator-name = "outp";
+ regulator-boot-on;
+ regulator-always-on;
+ enable-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ outn {
+ regulator-name = "outn";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-active-discharge = <0>;
+ enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ };
+++ /dev/null
-TPS65132 regulators
-
-Required properties:
-- compatible: "ti,tps65132"
-- reg: I2C slave address
-
-Optional Subnode:
-Device supports two regulators OUTP and OUTN. A sub node within the
- device node describe the properties of these regulators. The sub-node
- names must be as follows:
- -For regulator outp, the sub node name should be "outp".
- -For regulator outn, the sub node name should be "outn".
-
--enable-gpios:(active high, output) Regulators are controlled by the input pins.
- If it is connected to GPIO through host system then provide the
- gpio number as per gpio.txt.
--active-discharge-gpios: (active high, output) Some configurations use delay mechanisms
- on the enable pin, to keep the regulator enabled for some time after
- the enable signal goes low. This GPIO is used to actively discharge
- the delay mechanism. Requires specification of ti,active-discharge-time-us
--ti,active-discharge-time-us: how long the active discharge gpio should be
- asserted for during active discharge, in microseconds.
-
-Each regulator is defined using the standard binding for regulators.
-
-Example:
-
- tps65132@3e {
- compatible = "ti,tps65132";
- reg = <0x3e>;
-
- outp {
- regulator-name = "outp";
- regulator-boot-on;
- regulator-always-on;
- enable-gpios = <&gpio 23 0>;
- };
-
- outn {
- regulator-name = "outn";
- regulator-boot-on;
- regulator-always-on;
- regulator-active-discharge = <0>;
- enable-gpios = <&gpio 40 0>;
- };
- };
maxItems: 1
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description:
If present, name (or relative path) of the file within the
firmware search path containing the firmware image used when
maxItems: 1
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description:
If present, name (or relative path) of the file within the
firmware search path containing the firmware image used when
const: qcom,glink-rpm
label:
- $ref: /schemas/types.yaml#/definitions/string
description:
Name of the edge, used for debugging and identification purposes. The
node name will be used if this is not present.
description: Reference to the reserved-memory for the Hexagon core
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description: Firmware name for the Hexagon core
required:
smd-edge: false
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description: Firmware name for the Hexagon core
required:
description: Reference to the reserved-memory for the Hexagon core
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description:
The name of the firmware which should be loaded for this remote
processor.
description: Reference to the reserved-memory for the Hexagon core
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description: Firmware name for the Hexagon core
required:
smd-edge: false
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description: Firmware name for the Hexagon core
required:
smd-edge: false
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description: Firmware name for the Hexagon core
required:
description: Reference to the reserved-memory for the Hexagon core
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description: Firmware name for the Hexagon core
smd-edge: false
smd-edge: false
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description: Firmware name for the Hexagon core
required:
description: Reference to the reserved-memory for the Hexagon core
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description: Firmware name for the Hexagon core
required:
- qcom,sm8550-adsp-pas
- qcom,sm8550-cdsp-pas
- qcom,sm8550-mpss-pas
+ - qcom,sm8650-adsp-pas
+ - qcom,sm8650-cdsp-pas
+ - qcom,sm8650-mpss-pas
+ - qcom,x1e80100-adsp-pas
+ - qcom,x1e80100-cdsp-pas
reg:
maxItems: 1
- description: Memory region for main Firmware authentication
- description: Memory region for Devicetree Firmware authentication
- description: DSM Memory region
+ - description: DSM Memory region 2
+ - description: Memory region for Qlink Logging
required:
- compatible
enum:
- qcom,sm8550-adsp-pas
- qcom,sm8550-cdsp-pas
+ - qcom,sm8650-adsp-pas
+ - qcom,x1e80100-adsp-pas
+ - qcom,x1e80100-cdsp-pas
then:
properties:
interrupts:
maxItems: 5
memory-region:
maxItems: 2
- else:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sm8650-cdsp-pas
+ then:
+ properties:
+ interrupts:
+ maxItems: 5
+ interrupt-names:
+ maxItems: 5
+ memory-region:
+ minItems: 3
+ maxItems: 3
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sm8550-mpss-pas
+ then:
properties:
interrupts:
minItems: 6
minItems: 6
memory-region:
minItems: 3
+ maxItems: 3
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sm8650-mpss-pas
+ then:
+ properties:
+ interrupts:
+ minItems: 6
+ interrupt-names:
+ minItems: 6
+ memory-region:
+ minItems: 5
+ maxItems: 5
- if:
properties:
compatible:
enum:
- qcom,sm8550-adsp-pas
+ - qcom,sm8650-adsp-pas
+ - qcom,x1e80100-adsp-pas
then:
properties:
power-domains:
compatible:
enum:
- qcom,sm8550-mpss-pas
+ - qcom,sm8650-mpss-pas
then:
properties:
power-domains:
compatible:
enum:
- qcom,sm8550-cdsp-pas
+ - qcom,sm8650-cdsp-pas
+ - qcom,x1e80100-cdsp-pas
then:
properties:
power-domains:
- const: stop-ack
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description:
Relative firmware image path for the WCNSS core. Defaults to
"wcnss.mdt".
TI Davinci DSP devices
=======================
-Binding status: Unstable - Subject to changes for DT representation of clocks
- and resets
-
The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
is used to offload some of the processor-intensive tasks or algorithms, for
achieving various system level goals.
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/mobileye,eyeq5-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobileye EyeQ5 reset controller
+
+description:
+ The EyeQ5 reset driver handles three reset domains. Its registers live in a
+ shared region called OLB.
+
+maintainers:
+ - Grégory Clement <gregory.clement@bootlin.com>
+ - Théo Lebrun <theo.lebrun@bootlin.com>
+ - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
+
+properties:
+ compatible:
+ const: mobileye,eyeq5-reset
+
+ reg:
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: d0
+ - const: d1
+ - const: d2
+
+ "#reset-cells":
+ const: 2
+ description:
+ The first cell is the domain (0 to 2 inclusive) and the second one is the
+ reset index inside that domain.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#reset-cells"
+
+additionalProperties: false
- renesas,r8a779a0-rst # R-Car V3U
- renesas,r8a779f0-rst # R-Car S4-8
- renesas,r8a779g0-rst # R-Car V4H
+ - renesas,r8a779h0-rst # R-Car V4M
reg:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 SoC Reset Controller
+
+maintainers:
+ - Chen Wang <unicorn_wang@outlook.com>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ rstgen: reset-controller@c00 {
+ compatible = "sophgo,sg2042-reset";
+ reg = <0xc00 0xc>;
+ #reset-cells = <1>;
+ };
- riscv,sv57
- riscv,none
+ reg:
+ description:
+ The hart ID of this CPU node.
+
riscv,cbom-block-size:
$ref: /schemas/types.yaml#/definitions/uint32
description:
const: 1
compatible:
- const: riscv,cpu-intc
+ oneOf:
+ - items:
+ - const: andestech,cpu-intc
+ - const: riscv,cpu-intc
+ - const: riscv,cpu-intc
interrupt-controller: true
latency, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
+ - const: xandespmu
+ description:
+ The Andes Technology performance monitor extension for counter overflow
+ and privilege mode filtering. For more details, see Counter Related
+ Registers in the AX45MP datasheet.
+ https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+
additionalProperties: true
...
- enum:
- microchip,sama7g5-trng
- const: atmel,at91sam9g45-trng
+ - items:
+ - enum:
+ - microchip,sam9x7-trng
+ - const: microchip,sam9x60-trng
clocks:
maxItems: 1
+++ /dev/null
-Abracon ABX80X I2C ultra low power RTC/Alarm chip
-
-The Abracon ABX80X family consist of the ab0801, ab0803, ab0804, ab0805, ab1801,
-ab1803, ab1804 and ab1805. The ab0805 is the superset of ab080x and the ab1805
-is the superset of ab180x.
-
-Required properties:
-
- - "compatible": should one of:
- "abracon,abx80x"
- "abracon,ab0801"
- "abracon,ab0803"
- "abracon,ab0804"
- "abracon,ab0805"
- "abracon,ab1801"
- "abracon,ab1803"
- "abracon,ab1804"
- "abracon,ab1805"
- "microcrystal,rv1805"
- Using "abracon,abx80x" will enable chip autodetection.
- - "reg": I2C bus address of the device
-
-Optional properties:
-
-The abx804 and abx805 have a trickle charger that is able to charge the
-connected battery or supercap. Both the following properties have to be defined
-and valid to enable charging:
-
- - "abracon,tc-diode": should be "standard" (0.6V) or "schottky" (0.3V)
- - "abracon,tc-resistor": should be <0>, <3>, <6> or <11>. 0 disables the output
- resistor, the other values are in kOhm.
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/abracon,abx80x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Abracon ABX80X I2C ultra low power RTC/Alarm chip
+
+maintainers:
+ - linux-rtc@vger.kernel.org
+
+properties:
+ compatible:
+ description:
+ The wildcard 'abracon,abx80x' may be used to support a mix
+ of different abracon rtc`s. In this case the driver
+ must perform auto-detection from ID register.
+ enum:
+ - abracon,abx80x
+ - abracon,ab0801
+ - abracon,ab0803
+ - abracon,ab0804
+ - abracon,ab0805
+ - abracon,ab1801
+ - abracon,ab1803
+ - abracon,ab1804
+ - abracon,ab1805
+ - microcrystal,rv1805
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ abracon,tc-diode:
+ description:
+ Trickle-charge diode type.
+ Required to enable charging backup battery.
+
+ Supported are 'standard' diodes with a 0.6V drop
+ and 'schottky' diodes with a 0.3V drop.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum:
+ - standard
+ - schottky
+
+ abracon,tc-resistor:
+ description:
+ Trickle-charge resistor value in kOhm.
+ Required to enable charging backup battery.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 3, 6, 11]
+
+dependentRequired:
+ abracon,tc-diode: ["abracon,tc-resistor"]
+ abracon,tc-resistor: ["abracon,tc-diode"]
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: rtc.yaml#
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ enum:
+ - abracon,abx80x
+ - abracon,ab0804
+ - abracon,ab1804
+ - abracon,ab0805
+ - abracon,ab1805
+ then:
+ properties:
+ abracon,tc-diode: false
+ abracon,tc-resistor: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@69 {
+ compatible = "abracon,abx80x";
+ reg = <0x69>;
+ abracon,tc-diode = "schottky";
+ abracon,tc-resistor = <3>;
+ interrupts = <44 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
- items:
- const: atmel,at91sam9260-rtt
- items:
- - const: microchip,sam9x60-rtt
+ - enum:
+ - microchip,sam9x60-rtt
+ - microchip,sam9x7-rtt
- const: atmel,at91sam9260-rtt
- items:
- const: microchip,sama7g5-rtt
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/mediatek,mt2712-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT2712 on-SoC RTC
+
+allOf:
+ - $ref: rtc.yaml#
+
+maintainers:
+ - Ran Bi <ran.bi@mediatek.com>
+
+properties:
+ compatible:
+ const: mediatek,mt2712-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ rtc@10011000 {
+ compatible = "mediatek,mt2712-rtc";
+ reg = <0x10011000 0x1000>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>;
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/mediatek,mt7622-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT7622 on-SoC RTC
+
+allOf:
+ - $ref: rtc.yaml#
+
+maintainers:
+ - Sean Wang <sean.wang@mediatek.com>
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt7622-rtc
+ - const: mediatek,soc-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: rtc
+
+required:
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt7622-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ rtc@10212800 {
+ compatible = "mediatek,mt7622-rtc", "mediatek,soc-rtc";
+ reg = <0x10212800 0x200>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_RTC>;
+ clock-names = "rtc";
+ };
+++ /dev/null
-Device-Tree bindings for MediaTek SoC based RTC
-
-Required properties:
-- compatible : Should be "mediatek,mt2712-rtc" : for MT2712 SoC
-- reg : Specifies base physical address and size of the registers;
-- interrupts : Should contain the interrupt for RTC alarm;
-
-Example:
-
-rtc: rtc@10011000 {
- compatible = "mediatek,mt2712-rtc";
- reg = <0 0x10011000 0 0x1000>;
- interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>;
-};
+++ /dev/null
-Device-Tree bindings for MediaTek SoC based RTC
-
-Required properties:
-- compatible : Should be
- "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC
-- reg : Specifies base physical address and size of the registers;
-- interrupts : Should contain the interrupt for RTC alarm;
-- clocks : Specifies list of clock specifiers, corresponding to
- entries in clock-names property;
-- clock-names : Should contain "rtc" entries
-
-Example:
-
-rtc: rtc@10212800 {
- compatible = "mediatek,mt7622-rtc",
- "mediatek,soc-rtc";
- reg = <0 0x10212800 0 0x200>;
- interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_RTC>;
- clock-names = "rtc";
-};
maintainers:
- Alessandro Zummo <a.zummo@towertech.it>
- Alexandre Belloni <alexandre.belloni@bootlin.com>
- - Rob Herring <robh+dt@kernel.org>
+ - Rob Herring <robh@kernel.org>
properties:
compatible:
properties:
compatible:
- const: xlnx,zynqmp-rtc
+ oneOf:
+ - const: xlnx,zynqmp-rtc
+ - items:
+ - enum:
+ - xlnx,versal-rtc
+ - xlnx,versal-net-rtc
+ - const: xlnx,zynqmp-rtc
reg:
maxItems: 1
default: 0x198233
deprecated: true
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
maintainers:
- - Richard Genoud <richard.genoud@gmail.com>
+ - Richard Genoud <richard.genoud@bootlin.com>
properties:
compatible:
allOf:
- $ref: serial.yaml#
+ - $ref: rs485.yaml#
- if:
properties:
compatible:
- items:
- enum:
- fsl,imx93-lpuart
+ - fsl,imx95-lpuart
- const: fsl,imx8ulp-lpuart
- const: fsl,imx7ulp-lpuart
- items:
- renesas,hscif-r8a779a0 # R-Car V3U
- renesas,hscif-r8a779f0 # R-Car S4-8
- renesas,hscif-r8a779g0 # R-Car V4H
+ - renesas,hscif-r8a779h0 # R-Car V4M
- const: renesas,rcar-gen4-hscif # R-Car Gen4
- const: renesas,hscif # generic HSCIF compatible UART
then:
required:
- samsung,uart-fifosize
+ properties:
+ reg-io-width: false
unevaluatedProperties: false
TX FIFO threshold configuration (in bytes).
patternProperties:
- "^(bluetooth|bluetooth-gnss|gnss|gps|mcu)$":
+ "^(bluetooth|bluetooth-gnss|gnss|gps|mcu|onewire)$":
if:
type: object
then:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/st,asc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STi SoCs Serial Port
+
+maintainers:
+ - Patrice Chotard <patrice.chotard@foss.st.com>
+
+allOf:
+ - $ref: serial.yaml#
+
+properties:
+ compatible:
+ const: st,asc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ st,hw-flow-ctrl:
+ description: When set, enable hardware flow control.
+ type: boolean
+
+ st,force-m1:
+ description: When set, force asc to be in Mode-1. This is recommended for
+ high bit rates above 19.2K.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/stih407-clks.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ serial@9830000 {
+ compatible = "st,asc";
+ reg = <0x9830000 0x2c>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ };
+...
wakeup-source: true
+ power-domains:
+ maxItems: 1
+
rx-threshold:
description:
If value is set to 1, RX FIFO threshold is disabled.
+++ /dev/null
-*st-asc(Serial Port)
-
-Required properties:
-- compatible : Should be "st,asc".
-- reg, reg-names, interrupts, interrupt-names : Standard way to define device
- resources with names. look in
- Documentation/devicetree/bindings/resource-names.txt
-
-Optional properties:
-- st,hw-flow-ctrl bool flag to enable hardware flow control.
-- st,force-m1 bool flat to force asc to be in Mode-1 recommended
- for high bit rates (above 19.2K)
-Example:
-serial@fe440000{
- compatible = "st,asc";
- reg = <0xfe440000 0x2c>;
- interrupts = <0 209 0>;
-};
ranges: true
patternProperties:
- "^clock-controller@[0-9a-z]+$":
+ "^clock-controller@[0-9a-f]+$":
$ref: /schemas/clock/fsl,flexspi-clock.yaml#
required:
ranges: true
patternProperties:
- "^interrupt-controller@[a-z0-9]+$":
+ "^interrupt-controller@[a-f0-9]+$":
$ref: /schemas/interrupt-controller/fsl,ls-extirq.yaml#
required:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx-anatop.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ANATOP register
+
+maintainers:
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,imx6sl-anatop
+ - fsl,imx6sll-anatop
+ - fsl,imx6sx-anatop
+ - fsl,imx6ul-anatop
+ - fsl,imx7d-anatop
+ - const: fsl,imx6q-anatop
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - const: fsl,imx6q-anatop
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Temperature sensor event
+ - description: Brown-out event on either of the support regulators
+ - description: Brown-out event on either the core, gpu or soc regulators
+
+ tempmon:
+ type: object
+ unevaluatedProperties: false
+ $ref: /schemas/thermal/imx-thermal.yaml
+
+patternProperties:
+ "regulator-((1p1)|(2p5)|(3p0)|(vddcore)|(vddpu)|(vddsoc))$":
+ type: object
+ unevaluatedProperties: false
+ $ref: /schemas/regulator/anatop-regulator.yaml
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx6ul-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ anatop: anatop@20c8000 {
+ compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
+ "syscon", "simple-mfd";
+ reg = <0x020c8000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+
+ reg_3p0: regulator-3p0 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd3p0";
+ regulator-min-microvolt = <2625000>;
+ regulator-max-microvolt = <3400000>;
+ anatop-reg-offset = <0x120>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2625000>;
+ anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
+ };
+
+ reg_arm: regulator-vddcore {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "cpu";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <0>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <24>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+
+ reg_soc: regulator-vddsoc {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vddsoc";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <18>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <28>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
+ };
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
+ interrupt-parent = <&gpc>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
compatible:
oneOf:
- items:
- - const: fsl,imx8mq-iomuxc-gpr
+ - enum:
+ - fsl,imx6q-iomuxc-gpr
+ - fsl,imx8mq-iomuxc-gpr
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - enum:
+ - fsl,imx6sl-iomuxc-gpr
+ - fsl,imx6sll-iomuxc-gpr
+ - fsl,imx6ul-iomuxc-gpr
+ - const: fsl,imx6q-iomuxc-gpr
+ - const: syscon
+ - items:
+ - enum:
+ - fsl,imx6sx-iomuxc-gpr
+ - fsl,imx7d-iomuxc-gpr
+ - const: fsl,imx6q-iomuxc-gpr
- const: syscon
- const: simple-mfd
- items:
const: 1
power-domains:
- minItems: 8
- maxItems: 8
+ minItems: 10
+ maxItems: 10
power-domain-names:
items:
- const: trng
- const: hdmi-tx
- const: hdmi-tx-phy
+ - const: hdcp
+ - const: hrv
clocks:
- minItems: 4
- maxItems: 4
+ minItems: 5
+ maxItems: 5
clock-names:
items:
- const: axi
- const: ref_266m
- const: ref_24m
+ - const: fdcc
interconnects:
maxItems: 3
clocks = <&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_ROOT>,
<&clk IMX8MP_CLK_HDMI_REF_266M>,
- <&clk IMX8MP_CLK_HDMI_24M>;
- clock-names = "apb", "axi", "ref_266m", "ref_24m";
+ <&clk IMX8MP_CLK_HDMI_24M>,
+ <&clk IMX8MP_CLK_HDMI_FDCC_TST>;
+ clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc";
power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,
<&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,
- <&pgc_hdmimix>, <&pgc_hdmi_phy>;
+ <&pgc_hdmimix>, <&pgc_hdmi_phy>,
+ <&pgc_hdmimix>, <&pgc_hdmimix>;
power-domain-names = "bus", "irqsteer", "lcdif", "pai", "pvi", "trng",
- "hdmi-tx", "hdmi-tx-phy";
+ "hdmi-tx", "hdmi-tx-phy",
+ "hdcp", "hrv";
#power-domain-cells = <1>;
};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,pbs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Programmable Boot Sequencer
+
+maintainers:
+ - Anjelique Melendez <quic_amelende@quicinc.com>
+
+description: |
+ The Qualcomm Technologies, Inc. Programmable Boot Sequencer (PBS)
+ supports triggering power up and power down sequences for clients
+ upon request.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,pmi632-pbs
+ - const: qcom,pbs
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/spmi/spmi.h>
+
+ pmic@0 {
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pbs@7400 {
+ compatible = "qcom,pmi632-pbs", "qcom,pbs";
+ reg = <0x7400>;
+ };
+ };
oneOf:
- items:
- enum:
+ - qcom,qcm6490-pmic-glink
- qcom,sc8180x-pmic-glink
- qcom,sc8280xp-pmic-glink
- qcom,sm8350-pmic-glink
- items:
- enum:
- qcom,sm8650-pmic-glink
+ - qcom,x1e80100-pmic-glink
- const: qcom,sm8550-pmic-glink
- const: qcom,pmic-glink
enum:
- qcom,sm8450-pmic-glink
- qcom,sm8550-pmic-glink
+ - qcom,x1e80100-pmic-glink
then:
properties:
orientation-gpios: false
description: Phandle to an RPM MSG RAM slice containing the master stats
minItems: 1
maxItems: 5
+ items:
+ maxItems: 1
qcom,master-names:
$ref: /schemas/types.yaml#/definitions/string-array
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml#
+$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Subsystem Power Manager
+title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2)
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
- This binding describes the Qualcomm Subsystem Power Manager, used to control
- the peripheral logic surrounding the application cores in Qualcomm platforms.
+ The Qualcomm Subsystem Power Manager is used to control the peripheral logic
+ surrounding the application cores in Qualcomm platforms.
+
+ The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
+ Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
+ power-controller that transitions a piece of hardware (like a processor or
+ subsystem) into and out of low power modes via a direct connection to
+ the PMIC. It can also be wired up to interact with other processors in the
+ system, notifying them when a low power state is entered or exited.
properties:
compatible:
items:
- enum:
+ - qcom,ipq4019-saw2-cpu
+ - qcom,ipq4019-saw2-l2
+ - qcom,ipq8064-saw2-cpu
- qcom,sdm660-gold-saw2-v4.1-l2
- qcom,sdm660-silver-saw2-v4.1-l2
- qcom,msm8998-gold-saw2-v4.1-l2
- qcom,msm8916-saw2-v3.0-cpu
- qcom,msm8939-saw2-v3.0-cpu
- qcom,msm8226-saw2-v2.1-cpu
+ - qcom,msm8226-saw2-v2.1-l2
+ - qcom,msm8960-saw2-cpu
- qcom,msm8974-saw2-v2.1-cpu
+ - qcom,msm8974-saw2-v2.1-l2
- qcom,msm8976-gold-saw2-v2.3-l2
- qcom,msm8976-silver-saw2-v2.3-l2
- qcom,apq8084-saw2-v2.1-cpu
+ - qcom,apq8084-saw2-v2.1-l2
- qcom,apq8064-saw2-v1.1-cpu
- const: qcom,saw2
reg:
- description: Base address and size of the SPM register region
- maxItems: 1
+ items:
+ - description: Base address and size of the SPM register region
+ - description: Base address and size of the alias register region
+ minItems: 1
+
+ regulator:
+ $ref: /schemas/regulator/regulator.yaml#
+ description: Indicates that this SPM device acts as a regulator device
+ device for the core (CPU or Cache) the SPM is attached to.
required:
- compatible
reg = <0x17912000 0x1000>;
};
+ - |
+ /*
+ * Example 3: SAW2 with the bundled regulator definition.
+ */
+ power-manager@2089000 {
+ compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
+ reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+
+ regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
+ };
...
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/renesas/renesas-soc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SoC compatibles naming convention
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Niklas Söderlund <niklas.soderlund@ragnatech.se>
+
+description: |
+ Guidelines for new compatibles for SoC blocks/components.
+ When adding new compatibles in new bindings, use the format::
+ renesas,SoC-IP
+
+ For example::
+ renesas,r8a77965-csi2
+
+ When adding new compatibles to existing bindings, use the format in the
+ existing binding, even if it contradicts the above.
+
+select:
+ properties:
+ compatible:
+ contains:
+ pattern: "^renesas,.+-.+$"
+ required:
+ - compatible
+
+properties:
+ compatible:
+ minItems: 1
+ maxItems: 4
+ items:
+ anyOf:
+ # Preferred naming style for compatibles of SoC components
+ - pattern: "^renesas,(emev2|r(7s|8a|9a)[a-z0-9]+|rcar|rmobile|rz[a-z0-9]*|sh(7[a-z0-9]+)?|mobile)-[a-z0-9-]+$"
+ - pattern: "^renesas,(condor|falcon|gr-peach|gray-hawk|salvator|sk-rz|smar(c(2)?)?|spider|white-hawk)(.*)?$"
+
+ # Legacy compatibles
+ #
+ # New compatibles are not allowed.
+ - pattern: "^renesas,(can|cpg|dmac|du|(g)?ether(avb)?|gpio|hscif|(r)?i[i2]c|imr|intc|ipmmu|irqc|jpu|mmcif|msiof|mtu2|pci(e)?|pfc|pwm|[rq]spi|rcar_sound|sata|scif[ab]*|sdhi|thermal|tmu|tpu|usb(2|hs)?|vin|xhci)-[a-z0-9-]+$"
+ - pattern: "^renesas,(d|s)?bsc(3)?-(r8a73a4|r8a7740|sh73a0)$"
+ - pattern: "^renesas,em-(gio|sti|uart)$"
+ - pattern: "^renesas,fsi2-(r8a7740|sh73a0)$"
+ - pattern: "^renesas,hspi-r8a777[89]$"
+ - pattern: "^renesas,sysc-(r8a73a4|r8a7740|rmobile|sh73a0)$"
+ - enum:
+ - renesas,imr-lx4
+ - renesas,mtu2-r7s72100
+
+ # None SoC component compatibles
+ #
+ # Compatibles with the Renesas vendor prefix that do not relate to any SoC
+ # component are OK. New compatibles are allowed.
+ - enum:
+ - renesas,smp-sram
+
+ # Do not fail compatibles not matching the select pattern
+ #
+ # Some SoC components in addition to a Renesas compatible list
+ # compatibles not related to Renesas. The select pattern for this
+ # schema hits all compatibles that have at lest one Renesas compatible
+ # and try to validate all values in that compatible array, allow all
+ # that don't match the schema select pattern. For example,
+ #
+ # compatible = "renesas,r9a07g044-mali", "arm,mali-bifrost";
+ - pattern: "^(?!renesas,.+-.+).+$"
+
+additionalProperties: true
- renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000)
- const: renesas,r8a779g0
+ - description: R-Car V4H (R8A779G2)
+ items:
+ - enum:
+ - renesas,white-hawk-single # White Hawk Single board (RTP8A779G2ASKB0F10SA001)
+ - const: renesas,r8a779g2
+ - const: renesas,r8a779g0
+
- items:
- enum:
- renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000)
- const: renesas,white-hawk-cpu
- const: renesas,r8a779g0
+ - description: R-Car V4M (R8A779H0)
+ items:
+ - enum:
+ - renesas,gray-hawk-single # Gray Hawk Single board (RTP8A779H0ASKB0F10S)
+ - const: renesas,r8a779h0
+
- description: R-Car H3e (R8A779M0)
items:
- enum:
- renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
- const: renesas,r9a07g054
- - description: RZ/V2M (R9A09G011)
- items:
- - enum:
- - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
- - const: renesas,r9a09g011
-
- description: RZ/G3S (R9A08G045)
items:
- enum:
- const: renesas,r9a08g045s33 # PCIe support
- const: renesas,r9a08g045
+ - description: RZ/V2M (R9A09G011)
+ items:
+ - enum:
+ - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
+ - const: renesas,r9a09g011
+
additionalProperties: true
...
- rockchip,rk3568-usb2phy-grf
- rockchip,rk3588-bigcore0-grf
- rockchip,rk3588-bigcore1-grf
+ - rockchip,rk3588-hdptxphy-grf
- rockchip,rk3588-ioc
- rockchip,rk3588-php-grf
- rockchip,rk3588-pipe-phy-grf
- rockchip,rk3588-sys-grf
- rockchip,rk3588-pcie3-phy-grf
- rockchip,rk3588-pcie3-pipe-grf
+ - rockchip,rk3588-usb-grf
+ - rockchip,rk3588-usbdpphy-grf
- rockchip,rk3588-vo-grf
- rockchip,rk3588-vop-grf
- rockchip,rv1108-usbgrf
reg:
maxItems: 1
+ clocks:
+ maxItems: 1
+
"#address-cells":
const: 1
unevaluatedProperties: false
pcie-phy:
+ type: object
description:
Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
unevaluatedProperties: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rk3588-vo-grf
+
+ then:
+ required:
+ - clocks
+
+ else:
+ properties:
+ clocks: false
+
+
examples:
- |
#include <dt-bindings/clock/rk3399-cru.h>
compatible:
contains:
enum:
+ - google,gs101-peric0-sysreg
+ - google,gs101-peric1-sysreg
- samsung,exynos850-cmgp-sysreg
- samsung,exynos850-peri-sysreg
- samsung,exynos850-sysreg
- const: xlnx,zynqmp
- description: Xilinx Kria SOMs
+ minItems: 3
items:
- - const: xlnx,zynqmp-sm-k26-rev1
- - const: xlnx,zynqmp-sm-k26-revB
- - const: xlnx,zynqmp-sm-k26-revA
- - const: xlnx,zynqmp-sm-k26
- - const: xlnx,zynqmp
+ enum:
+ - xlnx,zynqmp-sm-k26-rev2
+ - xlnx,zynqmp-sm-k26-rev1
+ - xlnx,zynqmp-sm-k26-revB
+ - xlnx,zynqmp-sm-k26-revA
+ - xlnx,zynqmp-sm-k26
+ - xlnx,zynqmp
+ allOf:
+ - contains:
+ const: xlnx,zynqmp
+ - contains:
+ const: xlnx,zynqmp-sm-k26
- description: Xilinx Kria SOMs (starter)
+ minItems: 3
items:
- - const: xlnx,zynqmp-smk-k26-rev1
- - const: xlnx,zynqmp-smk-k26-revB
- - const: xlnx,zynqmp-smk-k26-revA
- - const: xlnx,zynqmp-smk-k26
- - const: xlnx,zynqmp
+ enum:
+ - xlnx,zynqmp-smk-k26-rev2
+ - xlnx,zynqmp-smk-k26-rev1
+ - xlnx,zynqmp-smk-k26-revB
+ - xlnx,zynqmp-smk-k26-revA
+ - xlnx,zynqmp-smk-k26
+ - xlnx,zynqmp
+ allOf:
+ - contains:
+ const: xlnx,zynqmp
+ - contains:
+ const: xlnx,zynqmp-smk-k26
+
+ - description: Xilinx Kria SOM KV260 revA/Y/Z
+ minItems: 3
+ items:
+ enum:
+ - xlnx,zynqmp-sk-kv260-revA
+ - xlnx,zynqmp-sk-kv260-revY
+ - xlnx,zynqmp-sk-kv260-revZ
+ - xlnx,zynqmp-sk-kv260
+ - xlnx,zynqmp
+ allOf:
+ - contains:
+ const: xlnx,zynqmp-sk-kv260-revA
+ - contains:
+ const: xlnx,zynqmp-sk-kv260
+ - contains:
+ const: xlnx,zynqmp
+
+ - description: Xilinx Kria SOM KV260 rev2/1/B
+ minItems: 3
+ items:
+ enum:
+ - xlnx,zynqmp-sk-kv260-rev2
+ - xlnx,zynqmp-sk-kv260-rev1
+ - xlnx,zynqmp-sk-kv260-revB
+ - xlnx,zynqmp-sk-kv260
+ - xlnx,zynqmp
+ allOf:
+ - contains:
+ const: xlnx,zynqmp-sk-kv260-revB
+ - contains:
+ const: xlnx,zynqmp-sk-kv260
+ - contains:
+ const: xlnx,zynqmp
- description: AMD MicroBlaze V (QEMU)
items:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/atmel,asoc-wm8904.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel wm8904 audio codec complex
+
+maintainers:
+ - Dharma Balasubiramani <dharma.b@microchip.com>
+
+description:
+ The ASoC audio complex configuration for Atmel with WM8904 audio codec.
+
+properties:
+ compatible:
+ const: atmel,asoc-wm8904
+
+ atmel,model:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: The user-visible name of this sound complex.
+
+ atmel,ssc-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of the SSC controller.
+
+ atmel,audio-codec:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of the WM8731 audio codec.
+
+ atmel,audio-routing:
+ description:
+ A list of the connections between audio components. Each entry is a pair
+ of strings, the first being the connection's sink, the second being the
+ connection's source.
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ items:
+ enum:
+ # Board Connectors
+ - Headphone Jack
+ - Line In Jack
+ - Mic
+ # WM8904 CODEC Pins
+ - IN1L
+ - IN1R
+ - IN2L
+ - IN2R
+ - IN3L
+ - IN3R
+ - HPOUTL
+ - HPOUTR
+ - LINEOUTL
+ - LINEOUTR
+ - MICBIAS
+
+required:
+ - compatible
+ - atmel,model
+ - atmel,audio-routing
+ - atmel,ssc-controller
+ - atmel,audio-codec
+
+additionalProperties: false
+
+examples:
+ - |
+ sound {
+ compatible = "atmel,asoc-wm8904";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pck0_as_mck>;
+
+ atmel,model = "wm8904 @ AT91SAM9N12EK";
+
+ atmel,audio-routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "IN2L", "Line In Jack",
+ "IN2R", "Line In Jack",
+ "Mic", "MICBIAS",
+ "IN1L", "Mic";
+
+ atmel,ssc-controller = <&ssc0>;
+ atmel,audio-codec = <&wm8904>;
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/atmel,sam9x5-wm8731-audio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel at91sam9x5ek wm8731 audio complex
+
+maintainers:
+ - Dharma Balasubiramani <dharma.b@microchip.com>
+
+description:
+ The audio complex configuration for Atmel at91sam9x5ek with WM8731 audio codec.
+
+properties:
+ compatible:
+ const: atmel,sam9x5-wm8731-audio
+
+ atmel,model:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: The user-visible name of this sound complex.
+
+ atmel,ssc-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of the SSC controller.
+
+ atmel,audio-codec:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of the WM8731 audio codec.
+
+ atmel,audio-routing:
+ description:
+ A list of the connections between audio components. Each entry is a pair
+ of strings, the first being the connection's sink, the second being the
+ connection's source.
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ items:
+ enum:
+ # Board Connectors
+ - Headphone Jack
+ - Line In Jack
+
+ # CODEC Pins
+ - LOUT
+ - ROUT
+ - LHPOUT
+ - RHPOUT
+ - LLINEIN
+ - RLINEIN
+ - MICIN
+
+required:
+ - compatible
+ - atmel,model
+ - atmel,ssc-controller
+ - atmel,audio-codec
+ - atmel,audio-routing
+
+additionalProperties: false
+
+examples:
+ - |
+ sound {
+ compatible = "atmel,sam9x5-wm8731-audio";
+
+ atmel,model = "wm8731 @ AT91SAM9X5EK";
+
+ atmel,audio-routing =
+ "Headphone Jack", "RHPOUT",
+ "Headphone Jack", "LHPOUT",
+ "LLINEIN", "Line In Jack",
+ "RLINEIN", "Line In Jack";
+
+ atmel,ssc-controller = <&ssc0>;
+ atmel,audio-codec = <&wm8731>;
+ };
properties:
compatible:
- const: atmel,sama5d2-classd
+ oneOf:
+ - items:
+ - const: atmel,sama5d2-classd
+ - items:
+ - const: microchip,sam9x7-classd
+ - const: atmel,sama5d2-classd
reg:
maxItems: 1
+++ /dev/null
-* Atmel at91sam9x5ek wm8731 audio complex
-
-Required properties:
- - compatible: "atmel,sam9x5-wm8731-audio"
- - atmel,model: The user-visible name of this sound complex.
- - atmel,ssc-controller: The phandle of the SSC controller
- - atmel,audio-codec: The phandle of the WM8731 audio codec
- - atmel,audio-routing: A list of the connections between audio components.
- Each entry is a pair of strings, the first being the connection's sink,
- the second being the connection's source.
-
-Available audio endpoints for the audio-routing table:
-
-Board connectors:
- * Headphone Jack
- * Line In Jack
-
-wm8731 pins:
-cf Documentation/devicetree/bindings/sound/wlf,wm8731.yaml
-
-Example:
-sound {
- compatible = "atmel,sam9x5-wm8731-audio";
-
- atmel,model = "wm8731 @ AT91SAM9X5EK";
-
- atmel,audio-routing =
- "Headphone Jack", "RHPOUT",
- "Headphone Jack", "LHPOUT",
- "LLINEIN", "Line In Jack",
- "RLINEIN", "Line In Jack";
-
- atmel,ssc-controller = <&ssc0>;
- atmel,audio-codec = <&wm8731>;
-};
+++ /dev/null
-Atmel ASoC driver with wm8904 audio codec complex
-
-Required properties:
- - compatible: "atmel,asoc-wm8904"
- - atmel,model: The user-visible name of this sound complex.
- - atmel,audio-routing: A list of the connections between audio components.
- Each entry is a pair of strings, the first being the connection's sink,
- the second being the connection's source. Valid names for sources and
- sinks are the WM8904's pins, and the jacks on the board:
-
- WM8904 pins:
-
- * IN1L
- * IN1R
- * IN2L
- * IN2R
- * IN3L
- * IN3R
- * HPOUTL
- * HPOUTR
- * LINEOUTL
- * LINEOUTR
- * MICBIAS
-
- Board connectors:
-
- * Headphone Jack
- * Line In Jack
- * Mic
-
- - atmel,ssc-controller: The phandle of the SSC controller
- - atmel,audio-codec: The phandle of the WM8904 audio codec
-
-Optional properties:
- - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt
-
-Example:
-sound {
- compatible = "atmel,asoc-wm8904";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pck0_as_mck>;
-
- atmel,model = "wm8904 @ AT91SAM9N12EK";
-
- atmel,audio-routing =
- "Headphone Jack", "HPOUTL",
- "Headphone Jack", "HPOUTR",
- "IN2L", "Line In Jack",
- "IN2R", "Line In Jack",
- "Mic", "MICBIAS",
- "IN1L", "Mic";
-
- atmel,ssc-controller = <&ssc0>;
- atmel,audio-codec = <&wm8904>;
-};
- $ref: /schemas/types.yaml#/definitions/phandle
clocks:
description: Indicates system clock
- $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
system-clock-frequency:
$ref: simple-card.yaml#/definitions/system-clock-frequency
system-clock-direction-out:
reg:
maxItems: 1
+ interrupts:
+ maxItems: 1
+
'#sound-dai-cells':
const: 1
gpio-ranges:
items:
- - description: A phandle to the CODEC pinctrl node
- minimum: 0
- - const: 0
- - const: 0
- - const: 3
+ - items:
+ - description: A phandle to the CODEC pinctrl node
+ minimum: 0
+ - const: 0
+ - const: 0
+ - const: 3
patternProperties:
"-state$":
number for SPI.
For required properties on I2C-bus, please consult
-Documentation/devicetree/bindings/i2c/i2c.txt
+dtschema schemas/i2c/i2c-controller.yaml
For required properties on SPI-bus, please consult
Documentation/devicetree/bindings/spi/spi-bus.txt
default: 0x0f
everest,mic1-src:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint8
description:
the value of reg 2A when headset plugged.
default: 0x22
everest,mic2-src:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint8
description:
the value of reg 2A when headset unplugged.
0 means the chip detect jack type again after button released.
minimum: 0
maximum: 0x7f
- default: 0x45
+ default: 0x00
required:
- compatible
clocks = <&clks 10>;
clock-names = "mclk";
#sound-dai-cells = <0>;
- everest,mic1-src = [22];
- everest,mic2-src = [44];
everest,jack-pol = [0e];
everest,interrupt-src = [08];
- everest,interrupt-clk = [45];
+ everest,interrupt-clk = [00];
};
};
+++ /dev/null
-Freescale Asynchronous Sample Rate Converter (ASRC) Controller
-
-The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
-signal associated with an input clock into a signal associated with a different
-output clock. The driver currently works as a Front End of DPCM with other Back
-Ends Audio controller such as ESAI, SSI and SAI. It has three pairs to support
-three substreams within totally 10 channels.
-
-Required properties:
-
- - compatible : Compatible list, should contain one of the following
- compatibles:
- "fsl,imx35-asrc",
- "fsl,imx53-asrc",
- "fsl,imx8qm-asrc",
- "fsl,imx8qxp-asrc",
-
- - reg : Offset and length of the register set for the device.
-
- - interrupts : Contains the spdif interrupt.
-
- - dmas : Generic dma devicetree binding as described in
- Documentation/devicetree/bindings/dma/dma.txt.
-
- - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc".
-
- - clocks : Contains an entry for each entry in clock-names.
-
- - clock-names : Contains the following entries
- "mem" Peripheral access clock to access registers.
- "ipg" Peripheral clock to driver module.
- "asrck_<0-f>" Clock sources for input and output clock.
- "spba" The spba clock is required when ASRC is placed as a
- bus slave of the Shared Peripheral Bus and when two
- or more bus masters (CPU, DMA or DSP) try to access
- it. This property is optional depending on the SoC
- design.
-
- - fsl,asrc-rate : Defines a mutual sample rate used by DPCM Back Ends.
-
- - fsl,asrc-width : Defines a mutual sample width used by DPCM Back Ends.
-
- - fsl,asrc-clk-map : Defines clock map used in driver. which is required
- by imx8qm/imx8qxp platform
- <0> - select the map for asrc0 in imx8qm/imx8qxp
- <1> - select the map for asrc1 in imx8qm/imx8qxp
-
-Optional properties:
-
- - big-endian : If this property is absent, the little endian mode
- will be in use as default. Otherwise, the big endian
- mode will be in use for all the device registers.
-
- - fsl,asrc-format : Defines a mutual sample format used by DPCM Back
- Ends, which can replace the fsl,asrc-width.
- The value is 2 (S16_LE), or 6 (S24_LE).
-
-Example:
-
-asrc: asrc@2034000 {
- compatible = "fsl,imx53-asrc";
- reg = <0x02034000 0x4000>;
- interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks 107>, <&clks 107>, <&clks 0>,
- <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
- <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
- <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
- <&clks 107>, <&clks 0>, <&clks 0>;
- clock-names = "mem", "ipg", "asrck0",
- "asrck_1", "asrck_2", "asrck_3", "asrck_4",
- "asrck_5", "asrck_6", "asrck_7", "asrck_8",
- "asrck_9", "asrck_a", "asrck_b", "asrck_c",
- "asrck_d", "asrck_e", "asrck_f";
- dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
- <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
- dma-names = "rxa", "rxb", "rxc",
- "txa", "txb", "txc";
- fsl,asrc-rate = <48000>;
- fsl,asrc-width = <16>;
-};
- const: ctx3_tx
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
- const: imx/easrc/easrc-imx8mn.bin
+ items:
+ - const: imx/easrc/easrc-imx8mn.bin
description: The coefficient table for the filters
fsl,asrc-rate:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl,imx-asrc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Asynchronous Sample Rate Converter (ASRC) Controller
+
+description:
+ The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of
+ a signal associated with an input clock into a signal associated with a
+ different output clock. The driver currently works as a Front End of DPCM
+ with other Back Ends Audio controller such as ESAI, SSI and SAI. It has
+ three pairs to support three substreams within totally 10 channels.
+
+maintainers:
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - fsl,imx35-asrc
+ - fsl,imx53-asrc
+ - fsl,imx8qm-asrc
+ - fsl,imx8qxp-asrc
+ - items:
+ - enum:
+ - fsl,imx6sx-asrc
+ - fsl,imx6ul-asrc
+ - const: fsl,imx53-asrc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ dmas:
+ maxItems: 6
+
+ dma-names:
+ items:
+ - const: rxa
+ - const: rxb
+ - const: rxc
+ - const: txa
+ - const: txb
+ - const: txc
+
+ clocks:
+ maxItems: 19
+
+ clock-names:
+ items:
+ - const: mem
+ - const: ipg
+ - const: asrck_0
+ - const: asrck_1
+ - const: asrck_2
+ - const: asrck_3
+ - const: asrck_4
+ - const: asrck_5
+ - const: asrck_6
+ - const: asrck_7
+ - const: asrck_8
+ - const: asrck_9
+ - const: asrck_a
+ - const: asrck_b
+ - const: asrck_c
+ - const: asrck_d
+ - const: asrck_e
+ - const: asrck_f
+ - const: spba
+
+ fsl,asrc-rate:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The mutual sample rate used by DPCM Back Ends
+
+ fsl,asrc-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The mutual sample width used by DPCM Back Ends
+ enum: [16, 24]
+
+ fsl,asrc-clk-map:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Defines clock map used in driver
+ <0> - select the map for asrc0 in imx8qm/imx8qxp
+ <1> - select the map for asrc1 in imx8qm/imx8qxp
+ enum: [0, 1]
+
+ big-endian:
+ type: boolean
+ description:
+ If this property is absent, the little endian mode will be in use as
+ default. Otherwise, the big endian mode will be in use for all the
+ device registers.
+
+ fsl,asrc-format:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Defines a mutual sample format used by DPCM Back Ends, which can
+ replace the fsl,asrc-width. The value is 2 (S16_LE), or 6 (S24_LE).
+ enum: [2, 6]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - dmas
+ - dma-names
+ - clocks
+ - clock-names
+ - fsl,asrc-rate
+ - fsl,asrc-width
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qm-asrc
+ - fsl,imx8qxp-asrc
+ then:
+ required:
+ - fsl,asrc-clk-map
+ else:
+ properties:
+ fsl,asrc-clk-map: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/imx6qdl-clock.h>
+ asrc: asrc@2034000 {
+ compatible = "fsl,imx53-asrc";
+ reg = <0x02034000 0x4000>;
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
+ <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
+ <&clks IMX6QDL_CLK_SPBA>;
+ clock-names = "mem", "ipg", "asrck_0",
+ "asrck_1", "asrck_2", "asrck_3", "asrck_4",
+ "asrck_5", "asrck_6", "asrck_7", "asrck_8",
+ "asrck_9", "asrck_a", "asrck_b", "asrck_c",
+ "asrck_d", "asrck_e", "asrck_f", "spba";
+ dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
+ <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
+ dma-names = "rxa", "rxb", "rxc",
+ "txa", "txb", "txc";
+ fsl,asrc-rate = <48000>;
+ fsl,asrc-width = <16>;
+ };
properties:
compatible:
- enum:
- - fsl,imx8mm-micfil
- - fsl,imx8mp-micfil
- - fsl,imx93-micfil
+ oneOf:
+ - items:
+ - enum:
+ - fsl,imx95-micfil
+ - const: fsl,imx93-micfil
+
+ - enum:
+ - fsl,imx8mm-micfil
+ - fsl,imx8mp-micfil
+ - fsl,imx93-micfil
reg:
maxItems: 1
- fsl,imx8qm-sai
- fsl,imx8ulp-sai
- fsl,imx93-sai
+ - fsl,imx95-sai
- fsl,vf610-sai
reg:
- const: pll11k
minItems: 4
+ power-domains:
+ maxItems: 1
+
dmas:
+ minItems: 1
items:
- description: DMA controller phandle and request line for RX
- description: DMA controller phandle and request line for TX
dma-names:
+ minItems: 1
items:
- const: rx
- const: tx
maxItems: 1
firmware-name:
- $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
description:
Filters coefficients file to load. If this property is omitted, internal
filters are disabled.
const: 0
compatible:
- enum:
- - microchip,sam9x60-i2smcc
- - microchip,sama7g5-i2smcc
+ oneOf:
+ - enum:
+ - microchip,sam9x60-i2smcc
+ - microchip,sama7g5-i2smcc
+ - items:
+ - enum:
+ - microchip,sam9x7-i2smcc
+ - const: microchip,sam9x60-i2smcc
reg:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,q6usb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm ASoC DPCM USB backend DAI
+
+maintainers:
+ - Wesley Cheng <quic_wcheng@quicinc.com>
+
+description:
+ The USB port is a supported AFE path on the Q6 DSP. This ASoC DPCM
+ backend DAI will communicate the required settings to initialize the
+ XHCI host controller properly for enabling the offloaded audio stream.
+ Parameters defined under this node will carry settings, which will be
+ passed along during the QMI stream enable request and configuration of
+ the XHCI host controller.
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,q6usb
+
+ iommus:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 1
+
+ qcom,usb-audio-intr-idx:
+ description:
+ Desired XHCI interrupter number to use. Depending on the audio DSP
+ on the platform, it will operate on a specific XHCI interrupter.
+ $ref: /schemas/types.yaml#/definitions/uint16
+ maximum: 8
+
+required:
+ - compatible
+ - "#sound-dai-cells"
+ - qcom,usb-audio-intr-idx
+
+additionalProperties: false
+
+examples:
+ - |
+ dais {
+ compatible = "qcom,q6usb";
+ #sound-dai-cells = <1>;
+ iommus = <&apps_smmu 0x180f 0x0>;
+ qcom,usb-audio-intr-idx = /bits/ 16 <2>;
+ };
properties:
sound-dai:
minItems: 1
- maxItems: 4
+ maxItems: 8
required:
- link-name
allOf:
- $ref: dai-common.yaml#
+ - $ref: qcom,wcd93xx-common.yaml#
properties:
compatible:
- qcom,wcd9380-codec
- qcom,wcd9385-codec
- reset-gpios:
- description: GPIO spec for reset line to use
- maxItems: 1
-
us-euro-gpios:
description: GPIO spec for swapping gnd and mic segments
maxItems: 1
- vdd-buck-supply:
- description: A reference to the 1.8V buck supply
-
- vdd-rxtx-supply:
- description: A reference to the 1.8V rx supply
-
- vdd-io-supply:
- description: A reference to the 1.8V I/O supply
-
- vdd-mic-bias-supply:
- description: A reference to the 3.8V mic bias supply
-
- qcom,tx-device:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- description: A reference to Soundwire tx device phandle
-
- qcom,rx-device:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- description: A reference to Soundwire rx device phandle
-
- qcom,micbias1-microvolt:
- description: micbias1 voltage
- minimum: 1800000
- maximum: 2850000
-
- qcom,micbias2-microvolt:
- description: micbias2 voltage
- minimum: 1800000
- maximum: 2850000
-
- qcom,micbias3-microvolt:
- description: micbias3 voltage
- minimum: 1800000
- maximum: 2850000
-
- qcom,micbias4-microvolt:
- description: micbias4 voltage
- minimum: 1800000
- maximum: 2850000
-
- qcom,hphl-jack-type-normally-closed:
- description: Indicates that HPHL jack switch type is normally closed
- type: boolean
-
- qcom,ground-jack-type-normally-closed:
- description: Indicates that Headset Ground switch type is normally closed
- type: boolean
-
- qcom,mbhc-headset-vthreshold-microvolt:
- description: Voltage threshold value for headset detection
- minimum: 0
- maximum: 2850000
-
- qcom,mbhc-headphone-vthreshold-microvolt:
- description: Voltage threshold value for headphone detection
- minimum: 0
- maximum: 2850000
-
- qcom,mbhc-buttons-vthreshold-microvolt:
- description:
- Array of 8 Voltage threshold values corresponding to headset
- button0 - button7
- minItems: 8
- maxItems: 8
-
- '#sound-dai-cells':
- const: 1
-
required:
- compatible
- - reset-gpios
- - qcom,tx-device
- - qcom,rx-device
- - qcom,micbias1-microvolt
- - qcom,micbias2-microvolt
- - qcom,micbias3-microvolt
- - qcom,micbias4-microvolt
- - "#sound-dai-cells"
unevaluatedProperties: false
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,wcd939x-sdw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SoundWire devices on WCD9390/WCD9395
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC.
+ It has RX and TX Soundwire devices. This bindings is for the devices.
+
+properties:
+ compatible:
+ const: sdw20217010e00
+
+ reg:
+ maxItems: 1
+
+ qcom,tx-port-mapping:
+ description: |
+ Specifies static port mapping between device and host tx ports.
+ In the order of the device port index.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 4
+ maxItems: 4
+
+ qcom,rx-port-mapping:
+ description: |
+ Specifies static port mapping between device and host rx ports.
+ In the order of device port index.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 6
+ maxItems: 6
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ soundwire@3210000 {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ reg = <0x03210000 0x2000>;
+ wcd938x_rx: codec@0,4 {
+ compatible = "sdw20217010e00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5 6>;
+ };
+ };
+
+ soundwire@3230000 {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ reg = <0x03230000 0x2000>;
+ wcd938x_tx: codec@0,3 {
+ compatible = "sdw20217010e00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <2 3 4 5>;
+ };
+ };
+
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,wcd939x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm WCD9380/WCD9385 Audio Codec
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC.
+ It has RX and TX Soundwire devices.
+ The WCD9390/WCD9395 IC has a functionally separate USB-C Mux subsystem
+ accessible over an I2C interface.
+ The Audio Headphone and Microphone data path between the Codec and the USB-C Mux
+ subsystems are external to the IC, thus requiring DT port-endpoint graph description
+ to handle USB-C altmode & orientation switching for Audio Accessory Mode.
+
+allOf:
+ - $ref: dai-common.yaml#
+ - $ref: qcom,wcd93xx-common.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,wcd9390-codec
+ - items:
+ - const: qcom,wcd9395-codec
+ - const: qcom,wcd9390-codec
+
+ mode-switch:
+ description: Flag the port as possible handler of altmode switching
+ type: boolean
+
+ orientation-switch:
+ description: Flag the port as possible handler of orientation switching
+ type: boolean
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ A port node to link the WCD939x Codec node to USB MUX subsystems for the
+ purpose of handling altmode muxing and orientation switching to detect and
+ enable Audio Accessory Mode.
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ codec {
+ compatible = "qcom,wcd9390-codec";
+ reset-gpios = <&tlmm 32 IRQ_TYPE_NONE>;
+ #sound-dai-cells = <1>;
+ qcom,tx-device = <&wcd939x_tx>;
+ qcom,rx-device = <&wcd939x_rx>;
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,hphl-jack-type-normally-closed;
+ qcom,ground-jack-type-normally-closed;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ };
+
+ /* ... */
+
+ soundwire@3210000 {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ reg = <0x03210000 0x2000>;
+ wcd939x_rx: codec@0,4 {
+ compatible = "sdw20217010e00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5 6>;
+ };
+ };
+
+ soundwire@3230000 {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ reg = <0x03230000 0x2000>;
+ wcd938x_tx: codec@0,3 {
+ compatible = "sdw20217010e00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <2 3 4 5>;
+ };
+ };
+
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,wcd93xx-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common properties for Qualcomm WCD93xx Audio Codec
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+properties:
+ reset-gpios:
+ description: GPIO spec for reset line to use
+ maxItems: 1
+
+ vdd-buck-supply:
+ description: A reference to the 1.8V buck supply
+
+ vdd-rxtx-supply:
+ description: A reference to the 1.8V rx supply
+
+ vdd-io-supply:
+ description: A reference to the 1.8V I/O supply
+
+ vdd-mic-bias-supply:
+ description: A reference to the 3.8V mic bias supply
+
+ qcom,tx-device:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: A reference to Soundwire tx device phandle
+
+ qcom,rx-device:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: A reference to Soundwire rx device phandle
+
+ qcom,micbias1-microvolt:
+ description: micbias1 voltage
+ minimum: 1800000
+ maximum: 2850000
+
+ qcom,micbias2-microvolt:
+ description: micbias2 voltage
+ minimum: 1800000
+ maximum: 2850000
+
+ qcom,micbias3-microvolt:
+ description: micbias3 voltage
+ minimum: 1800000
+ maximum: 2850000
+
+ qcom,micbias4-microvolt:
+ description: micbias4 voltage
+ minimum: 1800000
+ maximum: 2850000
+
+ qcom,hphl-jack-type-normally-closed:
+ description: Indicates that HPHL jack switch type is normally closed
+ type: boolean
+
+ qcom,ground-jack-type-normally-closed:
+ description: Indicates that Headset Ground switch type is normally closed
+ type: boolean
+
+ qcom,mbhc-headset-vthreshold-microvolt:
+ description: Voltage threshold value for headset detection
+ minimum: 0
+ maximum: 2850000
+
+ qcom,mbhc-headphone-vthreshold-microvolt:
+ description: Voltage threshold value for headphone detection
+ minimum: 0
+ maximum: 2850000
+
+ qcom,mbhc-buttons-vthreshold-microvolt:
+ description:
+ Array of 8 Voltage threshold values corresponding to headset
+ button0 - button7
+ minItems: 8
+ maxItems: 8
+
+ '#sound-dai-cells':
+ const: 1
+
+required:
+ - reset-gpios
+ - qcom,tx-device
+ - qcom,rx-device
+ - qcom,micbias1-microvolt
+ - qcom,micbias2-microvolt
+ - qcom,micbias3-microvolt
+ - qcom,micbias4-microvolt
+ - "#sound-dai-cells"
+
+additionalProperties: true
description: Powerdown/Shutdown line to use (pin SD_N)
maxItems: 1
+ reset-gpios:
+ description: Powerdown/Shutdown line to use (pin SD_N)
+ maxItems: 1
+
'#sound-dai-cells':
const: 0
required:
- compatible
- reg
- - powerdown-gpios
- '#sound-dai-cells'
- vdd-1p8-supply
- vdd-io-supply
+oneOf:
+ - required:
+ - powerdown-gpios
+ - required:
+ - reset-gpios
+
unevaluatedProperties: false
examples:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/realtek,rt1015.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RT1015 Mono Class D Audio Amplifier
+
+maintainers:
+ - Jack Yu <jack.yu@realtek.com>
+
+properties:
+ compatible:
+ enum:
+ - realtek,rt1015
+
+ reg:
+ maxItems: 1
+
+ realtek,power-up-delay-ms:
+ description: Set a delay time for flush work to be completed,
+ this vlaue is adjustable depending on platform.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec@28 {
+ compatible = "realtek,rt1015";
+ reg = <0x28>;
+ realtek,power-up-delay-ms = <50>;
+ };
+ };
+++ /dev/null
-RT1015 Mono Class D Audio Amplifier
-
-This device supports I2C only.
-
-Required properties:
-
-- compatible : "realtek,rt1015".
-
-- reg : The I2C address of the device.
-
-Optional properties:
-
-- realtek,power-up-delay-ms
- Set a delay time for flush work to be completed,
- this value is adjustable depending on platform.
-
-Example:
-
-rt1015: codec@28 {
- compatible = "realtek,rt1015";
- reg = <0x28>;
- realtek,power-up-delay-ms = <50>;
-};
a GPIO spec for the external headphone detect pin. If jd-mode = 0,
we will get the JD status by getting the value of hp-detect-gpios.
+- cbj-sleeve-gpios:
+ a GPIO spec to control the external combo jack circuit to tie the sleeve/ring2
+ contacts to the ground or floating. It could avoid some electric noise from the
+ active speaker jacks.
+
- realtek,in2-differential
Boolean. Indicate MIC2 input are differential, rather than single-ended.
compatible = "realtek,rt5650";
reg = <0x1a>;
hp-detect-gpios = <&gpio 19 0>;
+ cbj-sleeve-gpios = <&gpio 20 0>;
interrupt-parent = <&gpio>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
realtek,dmic-en = "true";
description: Phandles to the codecs.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- - description: Phandle to the WM5110 audio codec.
- - description: Phandle to the HDMI transmitter node.
+ - items:
+ - description: Phandle to the WM5110 audio codec.
+ - items:
+ - description: Phandle to the HDMI transmitter node.
+
samsung,audio-routing:
description: |
- const: atmel,at91rm9200-spi
- items:
- const: microchip,sam9x7-spi
- - const: microchip,sam9x60-spi
- const: atmel,at91rm9200-spi
reg:
compatible:
oneOf:
- enum:
+ - google,gs101-spi
- samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
- samsung,s3c6410-spi
- samsung,s5pv210-spi # for S5PV210 and S5PC110
- samsung,exynos4210-spi
- samsung,exynos5433-spi
+ - samsung,exynos850-spi
- samsung,exynosautov9-spi
- tesla,fsd-spi
- const: samsung,exynos7-spi
- compatible
- clocks
- clock-names
- - dmas
- - dma-names
- interrupts
- reg
Should be generally avoided and be replaced by
spi-cs-high + ACTIVE_HIGH.
+ fifo-depth:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Size of the RX and TX data FIFOs in bytes.
+
+ rx-fifo-depth:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Size of the RX data FIFO in bytes.
+
+ tx-fifo-depth:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Size of the TX data FIFO in bytes.
+
num-cs:
$ref: /schemas/types.yaml#/definitions/uint32
description:
- compatible
- reg
+dependencies:
+ rx-fifo-depth: [ tx-fifo-depth ]
+ tx-fifo-depth: [ rx-fifo-depth ]
+
allOf:
- if:
not:
properties:
"#address-cells":
const: 0
+ - not:
+ required:
+ - fifo-depth
+ - rx-fifo-depth
+ - not:
+ required:
+ - fifo-depth
+ - tx-fifo-depth
additionalProperties: true
- enum:
- fsl,imx8ulp-spi
- fsl,imx93-spi
+ - fsl,imx95-spi
- const: fsl,imx7ulp-spi
reg:
maxItems: 1
properties:
compatible:
- enum:
- - nxp,imx8dxl-fspi
- - nxp,imx8mm-fspi
- - nxp,imx8mp-fspi
- - nxp,imx8qxp-fspi
- - nxp,lx2160a-fspi
+ oneOf:
+ - enum:
+ - nxp,imx8dxl-fspi
+ - nxp,imx8mm-fspi
+ - nxp,imx8mp-fspi
+ - nxp,imx8qxp-fspi
+ - nxp,lx2160a-fspi
+ - items:
+ - enum:
+ - nxp,imx93-fspi
+ - nxp,imx95-fspi
+ - const: nxp,imx8mm-fspi
reg:
items:
ranges: true
patternProperties:
- "^sram@[a-z0-9]+":
+ "^sram@[a-f0-9]+":
$ref: /schemas/sram/sram.yaml#
unevaluatedProperties: false
"dt-bindings: <binding dir>: ..."
+ Few subsystems, like ASoC, media, regulators and SPI, expect reverse order
+ of the prefixes::
+
+ "<binding dir>: dt-bindings: ..."
+
The 80 characters of the subject are precious. It is recommended to not
use "Documentation" or "doc" because that is implied. All bindings are
docs. Repeating "binding" again should also be avoided.
the code implementing the binding.
6) Any compatible strings used in a chip or board DTS file must be
- previously documented in the corresponding DT binding text file
+ previously documented in the corresponding DT binding file
in Documentation/devicetree/bindings. This rule applies even if
the Linux device driver does not yet match on the compatible
string. [ checkpatch will emit warnings if this step is not
followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864
("checkpatch: add DT compatible string documentation checks"). ]
- 7) The wildcard "<chip>" may be used in compatible strings, as in
- the following example:
-
- - compatible: Must contain '"nvidia,<chip>-pcie",
- "nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ...
-
- As in the above example, the known values of "<chip>" should be
- documented if it is used.
-
- 8) If a documented compatible string is not yet matched by the
+ 7) If a documented compatible string is not yet matched by the
driver, the documentation should also include a compatible
- string that is matched by the driver (as in the "nvidia,tegra20-pcie"
- example above).
+ string that is matched by the driver.
- 9) Bindings are actively used by multiple projects other than the Linux
+ 8) Bindings are actively used by multiple projects other than the Linux
Kernel, extra care and consideration may need to be taken when making changes
to existing bindings.
- allwinner,sun50i-a100-ths
- allwinner,sun50i-h5-ths
- allwinner,sun50i-h6-ths
+ - allwinner,sun50i-h616-ths
clocks:
minItems: 1
nvmem-cell-names:
const: calibration
+ allwinner,sram:
+ maxItems: 1
+ description: phandle to device controlling temperate offset SYS_CFG register
+
# See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details
"#thermal-sensor-cells":
enum:
- allwinner,sun20i-d1-ths
- allwinner,sun50i-a100-ths
- allwinner,sun50i-h6-ths
+ - allwinner,sun50i-h616-ths
then:
properties:
clock-names:
minItems: 2
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun50i-h616-ths
+
+ then:
+ properties:
+ allwinner,sram: false
+
- if:
properties:
compatible:
const: 1
- if:
- properties:
- compatible:
- contains:
- enum:
- - allwinner,sun8i-h3-ths
- - allwinner,sun8i-r40-ths
- - allwinner,sun20i-d1-ths
- - allwinner,sun50i-a64-ths
- - allwinner,sun50i-a100-ths
- - allwinner,sun50i-h5-ths
- - allwinner,sun50i-h6-ths
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - allwinner,sun8i-a83t-ths
then:
required:
+++ /dev/null
-* Dialog DA9062/61 TJUNC Thermal Module
-
-This module is part of the DA9061/DA9062. For more details about entire
-DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt
-
-Junction temperature thermal module uses an interrupt signal to identify
-high THERMAL_TRIP_HOT temperatures for the PMIC device.
-
-Required properties:
-
-- compatible: should be one of the following valid compatible string lines:
- "dlg,da9061-thermal", "dlg,da9062-thermal"
- "dlg,da9062-thermal"
-
-Optional properties:
-
-- polling-delay-passive : Specify the polling period, measured in
- milliseconds, between thermal zone device update checks.
-
-Example: DA9062
-
- pmic0: da9062@58 {
- thermal {
- compatible = "dlg,da9062-thermal";
- polling-delay-passive = <3000>;
- };
- };
-
-Example: DA9061 using a fall-back compatible for the DA9062 onkey driver
-
- pmic0: da9061@58 {
- thermal {
- compatible = "dlg,da9061-thermal", "dlg,da9062-thermal";
- polling-delay-passive = <3000>;
- };
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/dlg,da9062-thermal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Dialog DA9062/61 TJUNC Thermal Module
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ This module is part of the DA9061/DA9062. For more details about entire
+ DA906{1,2} chips see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml
+
+ Junction temperature thermal module uses an interrupt signal to identify
+ high THERMAL_TRIP_HOT temperatures for the PMIC device.
+
+properties:
+ compatible:
+ oneOf:
+ - const: dlg,da9062-thermal
+ - items:
+ - const: dlg,da9061-thermal
+ - const: dlg,da9062-thermal
+
+ polling-delay-passive:
+ description:
+ Specify the polling period, measured in milliseconds, between
+ thermal zone device update checks.
+
+required:
+ - compatible
+
+additionalProperties: false
description: |
The values to be programmed into TTRnCR, as specified by the SoC
reference manual. The first cell is TTR0CR, the second is TTR1CR, etc.
- maxItems: 4
+ minItems: 2
+ maxItems: 7
fsl,tmu-calibration:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
- renesas,r8a779a0-thermal # R-Car V3U
- renesas,r8a779f0-thermal # R-Car S4-8
- renesas,r8a779g0-thermal # R-Car V4H
+ - renesas,r8a779h0-thermal # R-Car V4M
reg: true
enum:
- renesas,r8a779f0-thermal
- renesas,r8a779g0-thermal
+ - renesas,r8a779h0-thermal
then:
required:
- interrupts
additionalProperties: false
required:
- - polling-delay
- - polling-delay-passive
- thermal-sensors
- trips
be implemented in an always-on power domain."
patternProperties:
- '^frame@[0-9a-z]*$':
+ '^frame@[0-9a-f]+$':
type: object
additionalProperties: false
description: A timer node has up to 8 frame sub-nodes, each with the following properties.
description: |
Bit width of the timer, necessary if not 16.
+ "#pwm-cells":
+ const: 3
+
required:
- compatible
- reg
- - interrupts
- clocks
+allOf:
+ - if:
+ not:
+ required:
+ - "#pwm-cells"
+ then:
+ required:
+ - interrupts
+
additionalProperties: false
examples:
clocks = <&cpu_clk 3>;
timer-width = <32>;
};
+
+ - |
+ pwm: pwm@f8002000 {
+ compatible = "cdns,ttc";
+ reg = <0xf8002000 0x1000>;
+ clocks = <&cpu_clk 3>;
+ timer-width = <32>;
+ #pwm-cells = <3>;
+ };
+++ /dev/null
-MediaTek Timers
----------------
-
-MediaTek SoCs have different timers on different platforms,
-- CPUX (ARM/ARM64 System Timer)
-- GPT (General Purpose Timer)
-- SYST (System Timer)
-
-The proper timer will be selected automatically by driver.
-
-Required properties:
-- compatible should contain:
- For those SoCs that use GPT
- * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT)
- * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT)
- * "mediatek,mt6582-timer" for MT6582 compatible timers (GPT)
- * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT)
- * "mediatek,mt7623-timer" for MT7623 compatible timers (GPT)
- * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
- * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
- * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
- * "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
- * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
-
- For those SoCs that use SYST
- * "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
- * "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
- * "mediatek,mt8188-timer" for MT8188 compatible timers (SYST)
- * "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
- * "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
- * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
- * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)
-
- For those SoCs that use CPUX
- * "mediatek,mt6795-systimer" for MT6795 compatible timers (CPUX)
- * "mediatek,mt8365-systimer" for MT8365 compatible timers (CPUX)
-
-- reg: Should contain location and length for timer register.
-- clocks: Should contain system clock.
-
-Examples:
-
- timer@10008000 {
- compatible = "mediatek,mt6577-timer";
- reg = <0x10008000 0x80>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&system_clk>;
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/mediatek,timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek SoC timers
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description:
+ MediaTek SoCs have different timers on different platforms,
+ CPUX (ARM/ARM64 System Timer), GPT (General Purpose Timer)
+ and SYST (System Timer).
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt6577-timer
+ - mediatek,mt6765-timer
+ - mediatek,mt6795-systimer
+ # GPT Timers
+ - items:
+ - enum:
+ - mediatek,mt2701-timer
+ - mediatek,mt6580-timer
+ - mediatek,mt6582-timer
+ - mediatek,mt6589-timer
+ - mediatek,mt7623-timer
+ - mediatek,mt8127-timer
+ - mediatek,mt8135-timer
+ - mediatek,mt8173-timer
+ - mediatek,mt8516-timer
+ - const: mediatek,mt6577-timer
+ # SYST Timers
+ - items:
+ - enum:
+ - mediatek,mt7629-timer
+ - mediatek,mt8183-timer
+ - mediatek,mt8186-timer
+ - mediatek,mt8188-timer
+ - mediatek,mt8192-timer
+ - mediatek,mt8195-timer
+ - mediatek,mt8365-systimer
+ - const: mediatek,mt6765-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: Timer clock
+ - description: RTC or bus clock
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ timer@10008000 {
+ compatible = "mediatek,mt6577-timer";
+ reg = <0x10008000 0x80>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&system_clk>;
+ };
maintainers:
- Daniel Lezcano <daniel.lezcano@linaro.org>
- Thomas Gleixner <tglx@linutronix.de>
- - Rob Herring <robh+dt@kernel.org>
+ - Rob Herring <robh@kernel.org>
properties:
$nodename:
properties:
compatible:
- const: nxp,sysctr-timer
+ enum:
+ - nxp,imx95-sysctr-timer
+ - nxp,sysctr-timer
reg:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/ralink,cevt-systick.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: System tick counter present in Ralink family SoCs
+
+maintainers:
+ - Sergio Paracuellos <sergio.paracuellos@gmail.com>
+
+properties:
+ compatible:
+ const: ralink,cevt-systick
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ systick@d00 {
+ compatible = "ralink,cevt-systick";
+ reg = <0xd00 0x10>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <7>;
+ };
+...
- enum:
- renesas,r7s72100-ostm # RZ/A1H
- renesas,r7s9210-ostm # RZ/A2M
- - renesas,r9a07g043-ostm # RZ/G2UL
+ - renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five
- renesas,r9a07g044-ostm # RZ/G2{L,LC}
- renesas,r9a07g054-ostm # RZ/V2L
- const: renesas,ostm # Generic
interrupts:
minItems: 2
- maxItems: 3
+ items:
+ - description: Underflow interrupt, channel 0
+ - description: Underflow interrupt, channel 1
+ - description: Underflow interrupt, channel 2
+ - description: Input capture interrupt, channel 2
+
+ interrupt-names:
+ minItems: 2
+ items:
+ - const: tuni0
+ - const: tuni1
+ - const: tuni2
+ - const: ticpi2
clocks:
maxItems: 1
reg = <0xffd80000 0x30>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck";
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
- items:
- enum:
- axis,artpec8-mct
+ - google,gs101-mct
- samsung,exynos3250-mct
- samsung,exynos5250-mct
- samsung,exynos5260-mct
contains:
enum:
- axis,artpec8-mct
+ - google,gs101-mct
- samsung,exynos5260-mct
- samsung,exynos5420-mct
- samsung,exynos5433-mct
compatible:
items:
- enum:
+ - atmel,attpm20p
- infineon,slb9670
- st,st33htpm-spi
- st,st33zp24-spi
compatible:
items:
+ # Entries are sorted alphanumerically by the compatible
- enum:
# Acbel fsg032 power supply
- acbel,fsg032
- adi,lt7182s
# AMS iAQ-Core VOC Sensor
- ams,iaq-core
+ # Temperature monitoring of Astera Labs PT5161L PCIe retimer
+ - asteralabs,pt5161l
# i2c serial eeprom (24cxx)
- at,24c08
+ # i2c h/w elliptic curve crypto module
+ - atmel,atecc508a
# ATSHA204 - i2c h/w symmetric crypto module
- atmel,atsha204
# ATSHA204A - i2c h/w symmetric crypto module
- atmel,atsha204a
- # i2c h/w elliptic curve crypto module
- - atmel,atecc508a
# BPA-RS600: Power Supply
- blutek,bpa-rs600
# Bosch Sensortec pressure, temperature, humididty and VOC sensor
- fsl,mpl3115
# MPR121: Proximity Capacitive Touch Sensor Controller
- fsl,mpr121
- # Monolithic Power Systems Inc. multi-phase controller mp2856
- - mps,mp2856
- # Monolithic Power Systems Inc. multi-phase controller mp2857
- - mps,mp2857
- # Monolithic Power Systems Inc. multi-phase controller mp2888
- - mps,mp2888
- # Monolithic Power Systems Inc. multi-phase controller mp2971
- - mps,mp2971
- # Monolithic Power Systems Inc. multi-phase controller mp2973
- - mps,mp2973
- # Monolithic Power Systems Inc. multi-phase controller mp2975
- - mps,mp2975
- # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990
- - mps,mp5990
# Honeywell Humidicon HIH-6130 humidity/temperature sensor
- honeywell,hi6130
# IBM Common Form Factor Power Supply Versions (all versions)
- ibm,cffps1
# IBM Common Form Factor Power Supply Versions 2
- ibm,cffps2
+ # Infineon barometric pressure and temperature sensor
+ - infineon,dps310
# Infineon IR36021 digital POL buck controller
- infineon,ir36021
- # Infineon IR38060 Voltage Regulator
- - infineon,ir38060
- # Infineon IR38064 Voltage Regulator
- - infineon,ir38064
- # Infineon IR38164 Voltage Regulator
- - infineon,ir38164
- # Infineon IR38263 Voltage Regulator
- - infineon,ir38263
# Infineon IRPS5401 Voltage Regulator (PMIC)
- infineon,irps5401
# Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor
- maxim,max1237
# Temperature Sensor, I2C interface
- maxim,max1619
+ # 3-Channel Remote Temperature Sensor
+ - maxim,max31730
# 10-bit 10 kOhm linear programmable voltage divider
- maxim,max5481
# 10-bit 50 kOhm linear programmable voltage divider
- maxim,max6621
# 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
- maxim,max6625
- # 3-Channel Remote Temperature Sensor
- - maxim,max31730
# mCube 3-axis 8-bit digital accelerometer
- mcube,mc3230
# Measurement Specialities I2C temperature and humidity sensor
- memsic,mxc6655
# Menlo on-board CPLD trivial SPI device
- menlo,m53cpld
- # Micron SPI NOR Authenta
- - micron,spi-authenta
# Microchip differential I2C ADC, 1 Channel, 18 bit
- microchip,mcp3421
# Microchip differential I2C ADC, 2 Channel, 18 bit
- microchip,mcp3427
# Microchip differential I2C ADC, 4 Channel, 16 bit
- microchip,mcp3428
- # Microchip 7-bit Single I2C Digital POT (5k)
- - microchip,mcp4017-502
# Microchip 7-bit Single I2C Digital POT (10k)
- microchip,mcp4017-103
- # Microchip 7-bit Single I2C Digital POT (50k)
- - microchip,mcp4017-503
# Microchip 7-bit Single I2C Digital POT (100k)
- microchip,mcp4017-104
# Microchip 7-bit Single I2C Digital POT (5k)
- - microchip,mcp4018-502
+ - microchip,mcp4017-502
+ # Microchip 7-bit Single I2C Digital POT (50k)
+ - microchip,mcp4017-503
# Microchip 7-bit Single I2C Digital POT (10k)
- microchip,mcp4018-103
- # Microchip 7-bit Single I2C Digital POT (50k)
- - microchip,mcp4018-503
# Microchip 7-bit Single I2C Digital POT (100k)
- microchip,mcp4018-104
# Microchip 7-bit Single I2C Digital POT (5k)
- - microchip,mcp4019-502
+ - microchip,mcp4018-502
+ # Microchip 7-bit Single I2C Digital POT (50k)
+ - microchip,mcp4018-503
# Microchip 7-bit Single I2C Digital POT (10k)
- microchip,mcp4019-103
- # Microchip 7-bit Single I2C Digital POT (50k)
- - microchip,mcp4019-503
# Microchip 7-bit Single I2C Digital POT (100k)
- microchip,mcp4019-104
+ # Microchip 7-bit Single I2C Digital POT (5k)
+ - microchip,mcp4019-502
+ # Microchip 7-bit Single I2C Digital POT (50k)
+ - microchip,mcp4019-503
# PWM Fan Speed Controller With Fan Fault Detection
- microchip,tc654
# PWM Fan Speed Controller With Fan Fault Detection
- microchip,tc655
+ # Micron SPI NOR Authenta
+ - micron,spi-authenta
# MiraMEMS DA226 2-axis 14-bit digital accelerometer
- miramems,da226
# MiraMEMS DA280 3-axis 14-bit digital accelerometer
- miramems,da280
# MiraMEMS DA311 3-axis 12-bit digital accelerometer
- miramems,da311
+ # Monolithic Power Systems Inc. multi-phase controller mp2856
+ - mps,mp2856
+ # Monolithic Power Systems Inc. multi-phase controller mp2857
+ - mps,mp2857
+ # Monolithic Power Systems Inc. multi-phase controller mp2888
+ - mps,mp2888
+ # Monolithic Power Systems Inc. multi-phase controller mp2971
+ - mps,mp2971
+ # Monolithic Power Systems Inc. multi-phase controller mp2973
+ - mps,mp2973
+ # Monolithic Power Systems Inc. multi-phase controller mp2975
+ - mps,mp2975
+ # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990
+ - mps,mp5990
+ # Monolithic Power Systems Inc. synchronous step-down converter mpq8785
+ - mps,mpq8785
# Temperature sensor with integrated fan control
- national,lm63
# Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
- samsung,exynos-sataphy-i2c
# Semtech sx1301 baseband processor
- semtech,sx1301
- # Sensirion low power multi-pixel gas sensor with I2C interface
- - sensirion,sgpc3
# Sensirion multi-pixel gas sensor with I2C interface
- sensirion,sgp30
# Sensirion gas sensor with I2C interface
- sensirion,sgp40
+ # Sensirion low power multi-pixel gas sensor with I2C interface
+ - sensirion,sgpc3
# Sensirion temperature & humidity sensor with I2C interface
- sensirion,sht4x
# Sensortek 3 axis accelerometer
- ti,lm74
# Temperature sensor with integrated fan control
- ti,lm96000
- # I2C Touch-Screen Controller
- - ti,tsc2003
# Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
- ti,tmp103
# Thermometer with SPI interface
- ti,tps544b25
- ti,tps544c20
- ti,tps544c25
- # Winbond/Nuvoton H/W Monitor
- - winbond,w83793
+ # I2C Touch-Screen Controller
+ - ti,tsc2003
# Vicor Corporation Digital Supervisor
- vicor,pli1209bc
+ # Winbond/Nuvoton H/W Monitor
+ - winbond,w83793
required:
- compatible
- qcom,msm8996-ufshc
- qcom,msm8998-ufshc
- qcom,sa8775p-ufshc
+ - qcom,sc7180-ufshc
- qcom,sc7280-ufshc
+ - qcom,sc8180x-ufshc
- qcom,sc8280xp-ufshc
- qcom,sdm845-ufshc
- qcom,sm6115-ufshc
+ - qcom,sm6125-ufshc
- qcom,sm6350-ufshc
- qcom,sm8150-ufshc
- qcom,sm8250-ufshc
- const: jedec,ufs-2.0
clocks:
- minItems: 8
+ minItems: 7
maxItems: 11
clock-names:
- minItems: 8
+ minItems: 7
maxItems: 11
dma-coherent: true
allOf:
- $ref: ufs-common.yaml
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7180-ufshc
+ then:
+ properties:
+ clocks:
+ minItems: 7
+ maxItems: 7
+ clock-names:
+ items:
+ - const: core_clk
+ - const: bus_aggr_clk
+ - const: iface_clk
+ - const: core_clk_unipro
+ - const: ref_clk
+ - const: tx_lane0_sync_clk
+ - const: rx_lane0_sync_clk
+ reg:
+ maxItems: 1
+ reg-names:
+ maxItems: 1
+
- if:
properties:
compatible:
- qcom,msm8998-ufshc
- qcom,sa8775p-ufshc
- qcom,sc7280-ufshc
+ - qcom,sc8180x-ufshc
- qcom,sc8280xp-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
contains:
enum:
- qcom,sm6115-ufshc
+ - qcom,sm6125-ufshc
then:
properties:
clocks:
reg:
maxItems: 1
clocks:
- minItems: 8
+ minItems: 7
maxItems: 8
else:
properties:
minItems: 1
maxItems: 2
clocks:
- minItems: 8
+ minItems: 7
maxItems: 11
unevaluatedProperties: false
connector:
type: object
$ref: ../connector/usb-connector.yaml
- unevaluatedProperties: false
-
- description:
- Properties for usb c connector.
properties:
compatible:
const: usb-c-connector
- power-role: true
-
- data-role: true
-
- try-power-role: true
-
- required:
- - compatible
-
required:
- compatible
- reg
usb-phy:
description: phandle for the PHY device. Use "phys" instead.
- $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
deprecated: true
fsl,usbphy:
-# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/cypress,hx3.yaml#
vcc-supply:
description: power supply (2.7V-5.5V)
- mode-switch:
- description: Flag the port as possible handle of altmode switching
- type: boolean
-
- orientation-switch:
- description: Flag the port as possible handler of orientation switching
- type: boolean
+ mode-switch: true
+ orientation-switch: true
port:
$ref: /schemas/graph.yaml#/$defs/port-base
- reg
- port
+allOf:
+ - $ref: usb-switch.yaml#
+
additionalProperties: false
examples:
- const: usb-ehci
- enum:
- generic-ehci
+ - marvell,ac5-ehci
- marvell,armada-3700-ehci
- marvell,orion-ehci
- nuvoton,npcm750-ehci
vcc-supply:
description: power supply
- mode-switch:
- description: Flag the port as possible handle of altmode switching
- type: boolean
-
- orientation-switch:
- description: Flag the port as possible handler of orientation switching
- type: boolean
+ mode-switch: true
+ orientation-switch: true
port:
$ref: /schemas/graph.yaml#/properties/port
- orientation-switch
- port
+allOf:
+ - $ref: usb-switch.yaml#
+
additionalProperties: false
examples:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/hisilicon,hi3798mv200-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Hi3798MV200 DWC3 USB SoC controller
+
+maintainers:
+ - Yang Xiwen <forbidden405@foxmail.com>
+
+properties:
+ compatible:
+ const: hisilicon,hi3798mv200-dwc3
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ ranges: true
+
+ clocks:
+ items:
+ - description: Controller bus clock
+ - description: Controller suspend clock
+ - description: Controller reference clock
+ - description: Controller gm clock
+ - description: Controller gs clock
+ - description: Controller utmi clock
+ - description: Controller pipe clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: suspend
+ - const: ref
+ - const: gm
+ - const: gs
+ - const: utmi
+ - const: pipe
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: soft
+
+patternProperties:
+ '^usb@[0-9a-f]+$':
+ $ref: snps,dwc3.yaml#
+
+required:
+ - compatible
+ - ranges
+ - '#address-cells'
+ - '#size-cells'
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ usb {
+ compatible = "hisilicon,hi3798mv200-dwc3";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&clk_bus>,
+ <&clk_suspend>,
+ <&clk_ref>,
+ <&clk_gm>,
+ <&clk_gs>,
+ <&clk_utmi>,
+ <&clk_pipe>;
+ clock-names = "bus", "suspend", "ref", "gm", "gs", "utmi", "pipe";
+ resets = <&crg 0xb0 12>;
+ reset-names = "soft";
+
+ usb@98a0000 {
+ compatible = "snps,dwc3";
+ reg = <0x98a0000 0x10000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>,
+ <&clk_suspend>,
+ <&clk_ref>;
+ clock-names = "bus_early", "suspend", "ref";
+ phys = <&usb2_phy1_port2>, <&combphy0 0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ maximum-speed = "super-speed";
+ dr_mode = "host";
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/ite,it5205.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ITE IT5202 Type-C USB Alternate Mode Passive MUX
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ - Tianping Fang <tianping.fang@mediatek.com>
+
+properties:
+ compatible:
+ const: ite,it5205
+
+ reg:
+ maxItems: 1
+
+ vcc-supply:
+ description: Power supply for VCC pin (3.3V)
+
+ mode-switch:
+ description: Flag the port as possible handle of altmode switching
+ type: boolean
+
+ orientation-switch:
+ description: Flag the port as possible handler of orientation switching
+ type: boolean
+
+ ite,ovp-enable:
+ description: Enable Over Voltage Protection functionality
+ type: boolean
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ A port node to link the IT5205 to a TypeC controller for the purpose of
+ handling altmode muxing and orientation switching.
+
+required:
+ - compatible
+ - reg
+ - orientation-switch
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ typec-mux@48 {
+ compatible = "ite,it5205";
+ reg = <0x48>;
+
+ mode-switch;
+ orientation-switch;
+
+ vcc-supply = <&mt6359_vibr_ldo_reg>;
+
+ port {
+ it5205_usbss_sbu: endpoint {
+ remote-endpoint = <&typec_controller>;
+ };
+ };
+ };
+ };
+...
2 - used by mt2712 etc, revision 2 with following IPM rule;
101 - used by mt8183, specific 1.01;
102 - used by mt8192, specific 1.02;
- enum: [1, 2, 101, 102]
+ 103 - used by mt8195, IP0, specific 1.03;
+ 105 - used by mt8195, IP2, specific 1.05;
+ 106 - used by mt8195, IP3, specific 1.06;
+ enum: [1, 2, 101, 102, 103, 105, 106]
mediatek,u3p-dis-msk:
$ref: /schemas/types.yaml#/definitions/uint32
i2c-bus: false
else:
$ref: /schemas/usb/usb-device.yaml
- required:
- - peer-hub
additionalProperties: false
vdd18-supply:
description: Power supply for VDD18 pin
- retimer-switch:
- description: Flag the port as possible handle of SuperSpeed signals retiming
- type: boolean
-
- orientation-switch:
- description: Flag the port as possible handler of orientation switching
- type: boolean
+ orientation-switch: true
+ retimer-switch: true
ports:
$ref: /schemas/graph.yaml#/properties/ports
- compatible
- reg
+allOf:
+ - $ref: usb-switch.yaml#
+
additionalProperties: false
examples:
properties:
compatible:
- const: nxp,ptn5110
+ items:
+ - const: nxp,ptn5110
+ - const: tcpci
reg:
maxItems: 1
#size-cells = <0>;
tcpci@50 {
- compatible = "nxp,ptn5110";
+ compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
interrupt-parent = <&gpio3>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
description: power supply (1.8V)
enable-gpios: true
-
- retimer-switch:
- description: Flag the port as possible handle of SuperSpeed signals retiming
- type: boolean
-
- orientation-switch:
- description: Flag the port as possible handler of orientation switching
- type: boolean
+ orientation-switch: true
+ retimer-switch: true
ports:
$ref: /schemas/graph.yaml#/properties/ports
- compatible
- reg
+allOf:
+ - $ref: usb-switch.yaml#
+
additionalProperties: false
examples:
description: |
Different types of interrupts are used based on HS PHY used on target:
- pwr_event: Used for wakeup based on other power events.
- - hs_phY_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
+ - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
hs_phy_irq which is not triggered by default and its
functionality is mutually exclusive to that of
{dp/dm}_hs_phy_irq and qusb2_phy_irq.
properties:
compatible:
- enum:
- - qcom,pm8150b-typec
+ oneOf:
+ - enum:
+ - qcom,pmi632-typec
+ - qcom,pm8150b-typec
+ - items:
+ - enum:
+ - qcom,pm6150-typec
+ - const: qcom,pm8150b-typec
+ - items:
+ - enum:
+ - qcom,pm4125-typec
+ - const: qcom,pmi632-typec
+
connector:
type: object
reg:
description: Type-C port and pdphy SPMI register base offsets
+ minItems: 1
maxItems: 2
interrupts:
+ minItems: 8
items:
- description: Type-C CC attach notification, VBUS error, tCCDebounce done
- description: Type-C VCONN powered
- description: Power Domain Fast Role Swap event
interrupt-names:
+ minItems: 8
items:
- const: or-rid-detect-change
- const: vpd-detect
- interrupts
- interrupt-names
- vdd-vbus-supply
- - vdd-pdphy-supply
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pmi632-typec
+ then:
+ properties:
+ reg:
+ maxItems: 1
+ interrupts:
+ maxItems: 8
+ interrupt-names:
+ maxItems: 8
+ vdd-pdphy-supply: false
+ else:
+ properties:
+ reg:
+ maxItems: 2
+ interrupts:
+ minItems: 16
+ interrupt-names:
+ maxItems: 16
+ required:
+ - vdd-pdphy-supply
additionalProperties: false
vdd-supply:
description: USBSS VDD power supply
- mode-switch:
- description: Flag the port as possible handle of altmode switching
- type: boolean
-
- orientation-switch:
- description: Flag the port as possible handler of orientation switching
- type: boolean
+ mode-switch: true
+ orientation-switch: true
ports:
$ref: /schemas/graph.yaml#/properties/ports
- reg
- ports
+allOf:
+ - $ref: usb-switch.yaml#
+
additionalProperties: false
examples:
reg: true
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
vdd-supply:
description:
phandle to the regulator that provides power to the hub.
description:
phandle to the peer hub on the controller.
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ 1st downstream facing USB port
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ 2nd downstream facing USB port
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ 3rd downstream facing USB port
+
+ port@4:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ 4th downstream facing USB port
+
+patternProperties:
+ '^.*@[1-4]$':
+ description: The hard wired USB devices
+ type: object
+ $ref: /schemas/usb/usb-device.yaml
+
required:
- peer-hub
- compatible
reg = <1>;
vdd-supply = <&pp3300_hub>;
peer-hub = <&hub_3_0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* USB 2.0 device on port 2 */
+ device@2 {
+ compatible = "usb123,4567";
+ reg = <2>;
+ };
};
/* 3.0 hub on port 2 */
reg = <2>;
vdd-supply = <&pp3300_hub>;
peer-hub = <&hub_2_0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* Type-A connector on port 4 */
+ port@4 {
+ reg = <4>;
+ endpoint {
+ remote-endpoint = <&usb_a0_ss>;
+ };
+ };
+ };
};
};
const: ti,am62-usb
reg:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: USB CFG register space
+ - description: USB PHY2 register space
ranges: true
usbss1: usb@f910000 {
compatible = "ti,am62-usb";
- reg = <0x00 0x0f910000 0x00 0x800>;
+ reg = <0x00 0x0f910000 0x00 0x800>,
+ <0x00 0x0f918000 0x00 0x400>;
clocks = <&k3_clks 162 3>;
clock-names = "ref";
ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/ti,usb8020b.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI USB8020B USB 3.0 hub controller
+
+maintainers:
+ - Macpaul Lin <macpaul.lin@mediatek.com>
+
+allOf:
+ - $ref: usb-device.yaml#
+
+properties:
+ compatible:
+ enum:
+ - usb451,8025
+ - usb451,8027
+
+ reg: true
+
+ reset-gpios:
+ items:
+ - description: GPIO specifier for GRST# pin.
+
+ vdd-supply:
+ description:
+ VDD power supply to the hub
+
+ peer-hub:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the peer hub on the controller.
+
+required:
+ - compatible
+ - reg
+ - peer-hub
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ usb {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usb451,8027";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+ vdd-supply = <&usb_hub_fixed_3v3>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub_3_0: hub@2 {
+ compatible = "usb451,8025";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+ vdd-supply = <&usb_hub_fixed_3v3>;
+ };
+ };
description: Should specify the GPIO detecting a VBus insertion
maxItems: 1
- vbus-regulator:
- description: Should specify the regulator supplying current drawn from
- the VBus line.
- $ref: /schemas/types.yaml#/definitions/phandle
+ vbus-supply:
+ description: regulator supplying VBUS. It will be enabled and disabled
+ dynamically in OTG mode. If the regulator is controlled by a
+ GPIO line, this should be modeled as a regulator-fixed and
+ referenced by this supply.
wakeup-source:
description:
vcc-supply = <&hsusb1_vcc_regulator>;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
vbus-detect-gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
- vbus-regulator = <&vbus_regulator>;
+ vbus-supply = <&vbus_regulator>;
#phy-cells = <0>;
};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/usb-switch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: USB Orientation and Mode Switches Common Properties
+
+maintainers:
+ - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+description:
+ Common properties for devices handling USB mode and orientation switching.
+
+properties:
+ mode-switch:
+ description: Possible handler of altmode switching
+ type: boolean
+
+ orientation-switch:
+ description: Possible handler of orientation switching
+ type: boolean
+
+ retimer-switch:
+ description: Possible handler of SuperSpeed signals retiming
+ type: boolean
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ A port node to link the device to a TypeC controller for the purpose of
+ handling altmode muxing and orientation switching.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Super Speed (SS) Output endpoint to the Type-C connector
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ description:
+ Super Speed (SS) Input endpoint from the Super-Speed PHY
+ unevaluatedProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
+ unevaluatedProperties: false
+ properties:
+ data-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 8
+ uniqueItems: true
+ items:
+ maximum: 8
+
+oneOf:
+ - required:
+ - port
+ - required:
+ - ports
+
+additionalProperties: true
usb-phy:
$ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
description:
List of all the USB PHYs on this HCD to be accepted by the legacy USB
Physical Layer subsystem.
description: ShenZhen Asia Better Technology Ltd.
"^acbel,.*":
description: Acbel Polytech Inc.
+ "^acelink,.*":
+ description: Acelink Technology Co., Ltd.
"^acer,.*":
description: Acer Inc.
"^acme,.*":
description: Analog Devices, Inc.
"^adieng,.*":
description: ADI Engineering, Inc.
+ "^admatec,.*":
+ description: admatec GmbH
"^advantech,.*":
description: Advantech Corporation
"^aeroflexgaisler,.*":
description: Amlogic, Inc.
"^ampere,.*":
description: Ampere Computing LLC
+ "^amphenol,.*":
+ description: Amphenol Advanced Sensors
"^ampire,.*":
description: Ampire Co., Ltd.
"^ams,.*":
description: ASPEED Technology Inc.
"^asrock,.*":
description: ASRock Inc.
+ "^asteralabs,.*":
+ description: Astera Labs, Inc.
"^asus,.*":
description: AsusTek Computer Inc.
"^atheros,.*":
description: ByteDance Ltd.
"^calamp,.*":
description: CalAmp Corp.
+ "^calao,.*":
+ description: CALAO Systems SAS
"^calaosystems,.*":
description: CALAO Systems SAS
"^calxeda,.*":
description: EZchip Semiconductor
"^facebook,.*":
description: Facebook
+ "^fairchild,.*":
+ description: Fairchild Semiconductor (deprecated, use 'onnn')
+ deprecated: true
"^fairphone,.*":
description: Fairphone B.V.
"^faraday,.*":
description: FocalTech Systems Co.,Ltd
"^forlinx,.*":
description: Baoding Forlinx Embedded Technology Co., Ltd.
+ "^freebox,.*":
+ description: Freebox SAS
"^freecom,.*":
description: Freecom Gmbh
"^frida,.*":
description: Giantec Semiconductor, Inc.
"^giantplus,.*":
description: Giantplus Technology Co., Ltd.
+ "^glinet,.*":
+ description: GL Intelligence, Inc.
"^globalscale,.*":
description: Globalscale Technologies, Inc.
"^globaltop,.*":
description: Honestar Technologies Co., Ltd.
"^honeywell,.*":
description: Honeywell
+ "^hoperf,.*":
+ description: Shenzhen Hope Microelectronics Co., Ltd.
"^hoperun,.*":
description: Jiangsu HopeRun Software Co., Ltd.
"^hp,.*":
description: Hyundai Technology
"^i2se,.*":
description: I2SE GmbH
+ "^IBM,.*":
+ description: International Business Machines (IBM)
"^ibm,.*":
description: International Business Machines (IBM)
"^icplus,.*":
description: IC Plus Corp.
"^idt,.*":
description: Integrated Device Technologies, Inc.
+ "^iei,.*":
+ description: IEI Integration Corp.
"^ifi,.*":
description: Ingenieurburo Fur Ic-Technologie (I/F/I)
"^ilitek,.*":
description: JetHome (IP Sokolov P.A.)
"^jianda,.*":
description: Jiandangjing Technology Co., Ltd.
+ "^jide,.*":
+ description: Jide Tech
"^joz,.*":
description: JOZ BV
"^kam,.*":
description: LSI Corp. (LSI Logic)
"^lunzn,.*":
description: Shenzhen Lunzn Technology Co., Ltd.
+ "^luxul,.*":
+ description: Lagrand | AV
"^lwn,.*":
description: Liebherr-Werk Nenzing GmbH
"^lxa,.*":
description: Miniand Tech
"^minix,.*":
description: MINIX Technology Ltd.
+ "^mips,.*":
+ description: MIPS Technology (deprecated, use 'mti' or 'img')
+ deprecated: true
"^miramems,.*":
description: MiraMEMS Sensing Technology Co., Ltd.
"^mitsubishi,.*":
description: Miyoo
"^mntre,.*":
description: MNT Research GmbH
+ "^mobileye,.*":
+ description: Mobileye Vision Technologies Ltd.
"^modtronix,.*":
description: Modtronix Engineering
"^moortec,.*":
description: Novatek
"^novtech,.*":
description: NovTech, Inc.
+ "^numonyx,.*":
+ description: Numonyx (deprecated, use micron)
+ deprecated: true
"^nutsboard,.*":
description: NutsBoard
"^nuvoton,.*":
description: Skyworks Solutions, Inc.
"^smartlabs,.*":
description: SmartLabs LLC
+ "^smartrg,.*":
+ description: SmartRG, Inc.
"^smi,.*":
description: Silicon Motion Technology Corporation
"^smsc,.*":
description: Ufi Space Co., Ltd.
"^ugoos,.*":
description: Ugoos Industrial Co., Ltd.
+ "^uni-t,.*":
+ description: Uni-Trend Technology (China) Co., Ltd.
"^uniwest,.*":
description: United Western Technologies Corp (UniWest)
"^upisemi,.*":
description: VoCore Studio
"^voipac,.*":
description: Voipac Technologies s.r.o.
+ "^voltafield,.*":
+ description: Voltafield Technology Corp.
"^vot,.*":
description: Vision Optical Technology Co., Ltd.
+ "^vscom,.*":
+ description: VS Visions Systems GmbH
"^vxt,.*":
description: VXT Ltd
+ "^wacom,.*":
+ description: Wacom
"^wanchanglong,.*":
description: Wanchanglong Electronics Technology（SHENZHEN）Co.，Ltd.
"^wand,.*":
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/w1/w1-uart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UART 1-Wire Bus
+
+maintainers:
+ - Christoph Winklhofer <cj.winklhofer@gmail.com>
+
+description: |
+ UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus
+ to create the 1-Wire timing patterns.
+
+ The UART peripheral must support full-duplex and operate in open-drain
+ mode. The timing patterns are generated by a specific combination of
+ baud-rate and transmitted byte, which corresponds to a 1-Wire read bit,
+ write bit or reset pulse.
+
+ The default baud-rate for reset and presence detection is 9600 and for
+ a 1-Wire read or write operation 115200. In case the actual baud-rate
+ is different from the requested one, the transmitted byte is adapted
+ to generate the 1-Wire timing patterns.
+
+ https://www.analog.com/en/technical-articles/using-a-uart-to-implement-a-1wire-bus-master.html
+
+properties:
+ compatible:
+ const: w1-uart
+
+ reset-bps:
+ default: 9600
+ description:
+ The baud rate for the 1-Wire reset and presence detect.
+
+ write-0-bps:
+ default: 115200
+ description:
+ The baud rate for the 1-Wire write-0 cycle.
+
+ write-1-bps:
+ default: 115200
+ description:
+ The baud rate for the 1-Wire write-1 and read cycle.
+
+required:
+ - compatible
+
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ serial {
+ onewire {
+ compatible = "w1-uart";
+ };
+ };
- const: wdog_clk
- const: apb_pclk
+ resets:
+ maxItems: 1
+ description: WDOGRESn input reset signal for sp805 module.
+
required:
- compatible
- reg
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&wdt_clk>, <&apb_pclk>;
clock-names = "wdog_clk", "apb_pclk";
+ resets = <&wdt_rst>;
};
properties:
compatible:
- enum:
- - atmel,sama5d4-wdt
- - microchip,sam9x60-wdt
- - microchip,sama7g5-wdt
+ oneOf:
+ - enum:
+ - atmel,sama5d4-wdt
+ - microchip,sam9x60-wdt
+ - microchip,sama7g5-wdt
+ - items:
+ - const: microchip,sam9x7-wdt
+ - const: microchip,sam9x60-wdt
reg:
maxItems: 1
+++ /dev/null
-BCM2835 Watchdog timer
-
-Required properties:
-
-- compatible : should be "brcm,bcm2835-pm-wdt"
-- reg : Specifies base physical address and size of the registers.
-
-Optional properties:
-
-- timeout-sec : Contains the watchdog timeout in seconds
-
-Example:
-
-watchdog {
- compatible = "brcm,bcm2835-pm-wdt";
- reg = <0x7e100000 0x28>;
- timeout-sec = <10>;
-};
title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
maintainers:
- - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
+ - Rajendra Nayak <quic_rjendra@quicinc.com>
properties:
$nodename:
- renesas,r8a779a0-wdt # R-Car V3U
- renesas,r8a779f0-wdt # R-Car S4-8
- renesas,r8a779g0-wdt # R-Car V4H
+ - renesas,r8a779h0-wdt # R-Car V4M
- const: renesas,rcar-gen4-wdt # R-Car Gen4
reg:
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/sprd,sp9860-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spreadtrum SP9860 watchdog timer
+
+maintainers:
+ - Orson Zhai <orsonzhai@gmail.com>
+ - Baolin Wang <baolin.wang7@gmail.com>
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+allOf:
+ - $ref: watchdog.yaml#
+
+properties:
+ compatible:
+ const: sprd,sp9860-wdt
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: enable
+ - const: rtc_enable
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - timeout-sec
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/sprd,sc9860-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ watchdog@40310000 {
+ compatible = "sprd,sp9860-wdt";
+ reg = <0 0x40310000 0 0x1000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&aon_gate CLK_APCPU_WDG_EB>, <&aon_gate CLK_AP_WDG_RTC_EB>;
+ clock-names = "enable", "rtc_enable";
+ timeout-sec = <12>;
+ };
+ };
+...
+++ /dev/null
-Spreadtrum SoCs Watchdog timer
-
-Required properties:
-- compatible : Should be "sprd,sp9860-wdt".
-- reg : Specifies base physical address and size of the registers.
-- interrupts : Exactly one interrupt specifier.
-- timeout-sec : Contain the default watchdog timeout in seconds.
-- clock-names : Contain the input clock names.
-- clocks : Phandles to input clocks.
-
-Example:
- watchdog: watchdog@40310000 {
- compatible = "sprd,sp9860-wdt";
- reg = <0 0x40310000 0 0x1000>;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- timeout-sec = <12>;
- clock-names = "enable", "rtc_enable";
- clocks = <&clk_aon_apb_gates1 8>, <&clk_aon_apb_rtc_gates 9>;
- };
isn't cleared, the watchdog will reset the system unless the watchdog
reset is disabled.
-allOf:
- - $ref: watchdog.yaml#
-
properties:
compatible:
- enum:
- - starfive,jh7100-wdt
- - starfive,jh7110-wdt
+ oneOf:
+ - enum:
+ - starfive,jh7100-wdt
+ - starfive,jh7110-wdt
+ - items:
+ - enum:
+ - starfive,jh8100-wdt
+ - const: starfive,jh7110-wdt
reg:
maxItems: 1
- const: core
resets:
- items:
- - description: APB reset
- - description: Core reset
+ minItems: 1
+ maxItems: 2
required:
- compatible
- clock-names
- resets
+allOf:
+ - $ref: watchdog.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jh8100-wdt
+ then:
+ properties:
+ resets:
+ items:
+ - description: Core reset
+ else:
+ properties:
+ resets:
+ items:
+ - description: APB reset
+ - description: Core reset
+
unevaluatedProperties: false
examples:
Indicates the meta-schema the schema file adheres to.
title
- A one-line description on the contents of the binding schema.
+ A one-line description of the hardware being described in the binding schema.
maintainers
A DT specific property. Contains a list of email address(es)
description
Optional. A multi-line text block containing any detailed
- information about this binding. It should contain things such as what the block
+ information about this hardware. It should contain things such as what the block
or device does, standards the device conforms to, and links to datasheets for
more information.
A list of DT properties from the 'properties' section that
must always be present.
+additionalProperties / unevaluatedProperties
+ Keywords controlling how schema will validate properties not matched by this
+ schema's 'properties' or 'patternProperties'. Each schema is supposed to
+ have exactly one of these keywords in top-level part, so either
+ additionalProperties or unevaluatedProperties. Nested nodes, so properties
+ being objects, are supposed to have one as well.
+
+ * additionalProperties: false
+ Most common case, where no additional schema is referenced or if this
+ binding allows subset of properties from other referenced schemas.
+
+ * unevaluatedProperties: false
+ Used when this binding references other schema whose all properties
+ should be allowed.
+
+ * additionalProperties: true
+ Rare case, used for schemas implementing common set of properties. Such
+ schemas are supposed to be referenced by other schemas, which then use
+ 'unevaluatedProperties: false'. Typically bus or common-part schemas.
+
examples
- Optional. A list of one or more DTS hunks implementing the
- binding. Note: YAML doesn't allow leading tabs, so spaces must be used instead.
+ Optional. A list of one or more DTS hunks implementing this binding only.
+ Example should not contain unrelated device nodes, e.g. consumer nodes in a
+ provider binding, other nodes referenced by phandle.
+ Note: YAML doesn't allow leading tabs, so spaces must be used instead.
Unless noted otherwise, all properties are required.
#define QCOM_ID_IPQ9510 521
#define QCOM_ID_QRB4210 523
#define QCOM_ID_QRB2210 524
+#define QCOM_ID_SM8475 530
+#define QCOM_ID_SM8475P 531
#define QCOM_ID_SA8775P 534
#define QCOM_ID_QRU1000 539
+#define QCOM_ID_SM8475_2 540
#define QCOM_ID_QDU1000 545
#define QCOM_ID_SM8650 557
#define QCOM_ID_SM4450 568
#define QCOM_ID_IPQ5322 593
#define QCOM_ID_IPQ5312 594
#define QCOM_ID_IPQ5302 595
+#define QCOM_ID_QCS8550 603
+#define QCOM_ID_QCM8550 604
#define QCOM_ID_IPQ5300 624
/*
#define ASPEED_CLK_MAC3RCLK 69
#define ASPEED_CLK_MAC4RCLK 70
#define ASPEED_CLK_I3C 71
+#define ASPEED_CLK_FSI 72
/* Only list resets here that are not part of a clock gate + reset pair */
#define ASPEED_RESET_ADC 55
#define CLK_MOUT_G3D_SWITCH 76
#define CLK_GOUT_G3D_SWITCH 77
#define CLK_DOUT_G3D_SWITCH 78
+#define CLK_MOUT_CPUCL0_DBG 79
+#define CLK_MOUT_CPUCL0_SWITCH 80
+#define CLK_GOUT_CPUCL0_DBG 81
+#define CLK_GOUT_CPUCL0_SWITCH 82
+#define CLK_DOUT_CPUCL0_DBG 83
+#define CLK_DOUT_CPUCL0_SWITCH 84
+#define CLK_MOUT_CPUCL1_DBG 85
+#define CLK_MOUT_CPUCL1_SWITCH 86
+#define CLK_GOUT_CPUCL1_DBG 87
+#define CLK_GOUT_CPUCL1_SWITCH 88
+#define CLK_DOUT_CPUCL1_DBG 89
+#define CLK_DOUT_CPUCL1_SWITCH 90
/* CMU_APM */
#define CLK_RCO_I3C_PMIC 1
#define CLK_GOUT_CMGP_USI1_PCLK 14
#define CLK_GOUT_SYSREG_CMGP_PCLK 15
+/* CMU_CPUCL0 */
+#define CLK_FOUT_CPUCL0_PLL 1
+#define CLK_MOUT_PLL_CPUCL0 2
+#define CLK_MOUT_CPUCL0_SWITCH_USER 3
+#define CLK_MOUT_CPUCL0_DBG_USER 4
+#define CLK_MOUT_CPUCL0_PLL 5
+#define CLK_DOUT_CPUCL0_CPU 6
+#define CLK_DOUT_CPUCL0_CMUREF 7
+#define CLK_DOUT_CPUCL0_PCLK 8
+#define CLK_DOUT_CLUSTER0_ACLK 9
+#define CLK_DOUT_CLUSTER0_ATCLK 10
+#define CLK_DOUT_CLUSTER0_PCLKDBG 11
+#define CLK_DOUT_CLUSTER0_PERIPHCLK 12
+#define CLK_GOUT_CLUSTER0_ATCLK 13
+#define CLK_GOUT_CLUSTER0_PCLK 14
+#define CLK_GOUT_CLUSTER0_PERIPHCLK 15
+#define CLK_GOUT_CLUSTER0_SCLK 16
+#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK 17
+#define CLK_GOUT_CLUSTER0_CPU 18
+#define CLK_CLUSTER0_SCLK 19
+
+/* CMU_CPUCL1 */
+#define CLK_FOUT_CPUCL1_PLL 1
+#define CLK_MOUT_PLL_CPUCL1 2
+#define CLK_MOUT_CPUCL1_SWITCH_USER 3
+#define CLK_MOUT_CPUCL1_DBG_USER 4
+#define CLK_MOUT_CPUCL1_PLL 5
+#define CLK_DOUT_CPUCL1_CPU 6
+#define CLK_DOUT_CPUCL1_CMUREF 7
+#define CLK_DOUT_CPUCL1_PCLK 8
+#define CLK_DOUT_CLUSTER1_ACLK 9
+#define CLK_DOUT_CLUSTER1_ATCLK 10
+#define CLK_DOUT_CLUSTER1_PCLKDBG 11
+#define CLK_DOUT_CLUSTER1_PERIPHCLK 12
+#define CLK_GOUT_CLUSTER1_ATCLK 13
+#define CLK_GOUT_CLUSTER1_PCLK 14
+#define CLK_GOUT_CLUSTER1_PERIPHCLK 15
+#define CLK_GOUT_CLUSTER1_SCLK 16
+#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK 17
+#define CLK_GOUT_CLUSTER1_CPU 18
+#define CLK_CLUSTER1_SCLK 19
+
/* CMU_G3D */
#define CLK_FOUT_G3D_PLL 1
#define CLK_MOUT_G3D_PLL 2
#define CLK_GOUT_SSS_PCLK 12
#define CLK_GOUT_GPIO_CORE_PCLK 13
#define CLK_GOUT_SYSREG_CORE_PCLK 14
+#define CLK_GOUT_PDMA_CORE_ACLK 15
+#define CLK_GOUT_SPDMA_CORE_ACLK 16
/* CMU_DPU */
#define CLK_MOUT_DPU_USER 1
#define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73
#define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74
+/* CMU_PERIC0 */
+#define CLK_MOUT_PERIC0_BUS_USER 1
+#define CLK_MOUT_PERIC0_I3C_USER 2
+#define CLK_MOUT_PERIC0_USI0_UART_USER 3
+#define CLK_MOUT_PERIC0_USI14_USI_USER 4
+#define CLK_MOUT_PERIC0_USI1_USI_USER 5
+#define CLK_MOUT_PERIC0_USI2_USI_USER 6
+#define CLK_MOUT_PERIC0_USI3_USI_USER 7
+#define CLK_MOUT_PERIC0_USI4_USI_USER 8
+#define CLK_MOUT_PERIC0_USI5_USI_USER 9
+#define CLK_MOUT_PERIC0_USI6_USI_USER 10
+#define CLK_MOUT_PERIC0_USI7_USI_USER 11
+#define CLK_MOUT_PERIC0_USI8_USI_USER 12
+#define CLK_DOUT_PERIC0_I3C 13
+#define CLK_DOUT_PERIC0_USI0_UART 14
+#define CLK_DOUT_PERIC0_USI14_USI 15
+#define CLK_DOUT_PERIC0_USI1_USI 16
+#define CLK_DOUT_PERIC0_USI2_USI 17
+#define CLK_DOUT_PERIC0_USI3_USI 18
+#define CLK_DOUT_PERIC0_USI4_USI 19
+#define CLK_DOUT_PERIC0_USI5_USI 20
+#define CLK_DOUT_PERIC0_USI6_USI 21
+#define CLK_DOUT_PERIC0_USI7_USI 22
+#define CLK_DOUT_PERIC0_USI8_USI 23
+#define CLK_GOUT_PERIC0_IP 24
+#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 25
+#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK 26
+#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK 27
+#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK 28
+#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 29
+#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 30
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 31
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 33
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 34
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 35
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 37
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 38
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 39
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 40
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 42
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 43
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 44
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 45
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 46
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 47
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 48
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 49
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 50
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 51
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 52
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 53
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 54
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 55
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 56
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 57
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 58
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 59
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 60
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 61
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 62
+#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 63
+#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 64
+#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 65
+#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 66
+#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK 67
+#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK 68
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK 70
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK 71
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK 72
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK 73
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK 74
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK 75
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK 76
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK 77
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78
+#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79
+
+/* CMU_PERIC1 */
+#define CLK_MOUT_PERIC1_BUS_USER 1
+#define CLK_MOUT_PERIC1_I3C_USER 2
+#define CLK_MOUT_PERIC1_USI0_USI_USER 3
+#define CLK_MOUT_PERIC1_USI10_USI_USER 4
+#define CLK_MOUT_PERIC1_USI11_USI_USER 5
+#define CLK_MOUT_PERIC1_USI12_USI_USER 6
+#define CLK_MOUT_PERIC1_USI13_USI_USER 7
+#define CLK_MOUT_PERIC1_USI9_USI_USER 8
+#define CLK_DOUT_PERIC1_I3C 9
+#define CLK_DOUT_PERIC1_USI0_USI 10
+#define CLK_DOUT_PERIC1_USI10_USI 11
+#define CLK_DOUT_PERIC1_USI11_USI 12
+#define CLK_DOUT_PERIC1_USI12_USI 13
+#define CLK_DOUT_PERIC1_USI13_USI 14
+#define CLK_DOUT_PERIC1_USI9_USI 15
+#define CLK_GOUT_PERIC1_IP 16
+#define CLK_GOUT_PERIC1_PCLK 17
+#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK 18
+#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK 19
+#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK 20
+#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK 21
+#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 22
+#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 23
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 24
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 25
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 26
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 27
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 28
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 29
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 30
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 31
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 32
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 33
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 34
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 35
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 37
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 38
+#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK 39
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK 40
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK 42
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK 43
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK 44
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
+#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
+
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
#define CLK_RTCREF 33
#define CLK_MSSPLL 34
+#define CLK_MSSPLL0 34
+#define CLK_MSSPLL1 35
+#define CLK_MSSPLL2 36
+#define CLK_MSSPLL3 37
+/* 38 is reserved for MSS PLL internals */
/* Clock Conditioning Circuitry Clock IDs */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2024 Mobileye Vision Technologies Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
+#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
+
+#define EQ5C_PLL_CPU 0
+#define EQ5C_PLL_VMP 1
+#define EQ5C_PLL_PMA 2
+#define EQ5C_PLL_VDI 3
+#define EQ5C_PLL_DDR0 4
+#define EQ5C_PLL_PCI 5
+#define EQ5C_PLL_PER 6
+#define EQ5C_PLL_PMAC 7
+#define EQ5C_PLL_MPC 8
+#define EQ5C_PLL_DDR1 9
+
+#define EQ5C_DIV_OSPI 10
+
+#endif
#define GCC_USB3PHY_PHY_BCR 3
#define GCC_USB3_PHY_BCR 4
#define GCC_USB_30_BCR 5
+#define GCC_MDSS_BCR 6
+#define GCC_CRYPTO_BCR 7
+#define GCC_SDCC1_BCR 8
+#define GCC_SDCC2_BCR 9
/* GDSCs */
#define CPP_GDSC 0
#define GCC_PCIE_3_CLKREF_CLK 236
#define GCC_USB3_PRIM_CLKREF_CLK 237
#define GCC_USB3_SEC_CLKREF_CLK 238
+#define GCC_UFS_MEM_CLKREF_EN 239
+#define GCC_UFS_CARD_CLKREF_EN 240
#define GCC_EMAC_BCR 0
#define GCC_GPU_BCR 1
#define GCC_USB30_PRIM_BCR 26
#define GCC_USB30_SEC_BCR 27
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
+#define GCC_VIDEO_AXIC_CLK_BCR 29
+#define GCC_VIDEO_AXI0_CLK_BCR 30
+#define GCC_VIDEO_AXI1_CLK_BCR 31
/* GCC GDSCRs */
#define PCIE_0_GDSC 0
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H
+
+/* CAM_CC clocks */
+#define CAM_CC_BPS_AHB_CLK 0
+#define CAM_CC_BPS_CLK 1
+#define CAM_CC_BPS_CLK_SRC 2
+#define CAM_CC_BPS_FAST_AHB_CLK 3
+#define CAM_CC_CAMNOC_AXI_NRT_CLK 4
+#define CAM_CC_CAMNOC_AXI_RT_CLK 5
+#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 6
+#define CAM_CC_CAMNOC_DCD_XO_CLK 7
+#define CAM_CC_CAMNOC_XO_CLK 8
+#define CAM_CC_CCI_0_CLK 9
+#define CAM_CC_CCI_0_CLK_SRC 10
+#define CAM_CC_CCI_1_CLK 11
+#define CAM_CC_CCI_1_CLK_SRC 12
+#define CAM_CC_CORE_AHB_CLK 13
+#define CAM_CC_CPAS_AHB_CLK 14
+#define CAM_CC_CPAS_BPS_CLK 15
+#define CAM_CC_CPAS_FAST_AHB_CLK 16
+#define CAM_CC_CPAS_IFE_0_CLK 17
+#define CAM_CC_CPAS_IFE_1_CLK 18
+#define CAM_CC_CPAS_IFE_LITE_CLK 19
+#define CAM_CC_CPAS_IPE_NPS_CLK 20
+#define CAM_CC_CPAS_SFE_0_CLK 21
+#define CAM_CC_CPHY_RX_CLK_SRC 22
+#define CAM_CC_CSI0PHYTIMER_CLK 23
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC 24
+#define CAM_CC_CSI1PHYTIMER_CLK 25
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC 26
+#define CAM_CC_CSI2PHYTIMER_CLK 27
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC 28
+#define CAM_CC_CSI3PHYTIMER_CLK 29
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC 30
+#define CAM_CC_CSI4PHYTIMER_CLK 31
+#define CAM_CC_CSI4PHYTIMER_CLK_SRC 32
+#define CAM_CC_CSI5PHYTIMER_CLK 33
+#define CAM_CC_CSI5PHYTIMER_CLK_SRC 34
+#define CAM_CC_CSID_CLK 35
+#define CAM_CC_CSID_CLK_SRC 36
+#define CAM_CC_CSID_CSIPHY_RX_CLK 37
+#define CAM_CC_CSIPHY0_CLK 38
+#define CAM_CC_CSIPHY1_CLK 39
+#define CAM_CC_CSIPHY2_CLK 40
+#define CAM_CC_CSIPHY3_CLK 41
+#define CAM_CC_CSIPHY4_CLK 42
+#define CAM_CC_CSIPHY5_CLK 43
+#define CAM_CC_FAST_AHB_CLK_SRC 44
+#define CAM_CC_GDSC_CLK 45
+#define CAM_CC_ICP_AHB_CLK 46
+#define CAM_CC_ICP_CLK 47
+#define CAM_CC_ICP_CLK_SRC 48
+#define CAM_CC_IFE_0_CLK 49
+#define CAM_CC_IFE_0_CLK_SRC 50
+#define CAM_CC_IFE_0_DSP_CLK 51
+#define CAM_CC_IFE_0_FAST_AHB_CLK 52
+#define CAM_CC_IFE_1_CLK 53
+#define CAM_CC_IFE_1_CLK_SRC 54
+#define CAM_CC_IFE_1_DSP_CLK 55
+#define CAM_CC_IFE_1_FAST_AHB_CLK 56
+#define CAM_CC_IFE_LITE_AHB_CLK 57
+#define CAM_CC_IFE_LITE_CLK 58
+#define CAM_CC_IFE_LITE_CLK_SRC 59
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK 60
+#define CAM_CC_IFE_LITE_CSID_CLK 61
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC 62
+#define CAM_CC_IPE_NPS_AHB_CLK 63
+#define CAM_CC_IPE_NPS_CLK 64
+#define CAM_CC_IPE_NPS_CLK_SRC 65
+#define CAM_CC_IPE_NPS_FAST_AHB_CLK 66
+#define CAM_CC_IPE_PPS_CLK 67
+#define CAM_CC_IPE_PPS_FAST_AHB_CLK 68
+#define CAM_CC_JPEG_CLK 69
+#define CAM_CC_JPEG_CLK_SRC 70
+#define CAM_CC_MCLK0_CLK 71
+#define CAM_CC_MCLK0_CLK_SRC 72
+#define CAM_CC_MCLK1_CLK 73
+#define CAM_CC_MCLK1_CLK_SRC 74
+#define CAM_CC_MCLK2_CLK 75
+#define CAM_CC_MCLK2_CLK_SRC 76
+#define CAM_CC_MCLK3_CLK 77
+#define CAM_CC_MCLK3_CLK_SRC 78
+#define CAM_CC_MCLK4_CLK 79
+#define CAM_CC_MCLK4_CLK_SRC 80
+#define CAM_CC_MCLK5_CLK 81
+#define CAM_CC_MCLK5_CLK_SRC 82
+#define CAM_CC_MCLK6_CLK 83
+#define CAM_CC_MCLK6_CLK_SRC 84
+#define CAM_CC_MCLK7_CLK 85
+#define CAM_CC_MCLK7_CLK_SRC 86
+#define CAM_CC_PLL0 87
+#define CAM_CC_PLL0_OUT_EVEN 88
+#define CAM_CC_PLL0_OUT_ODD 89
+#define CAM_CC_PLL1 90
+#define CAM_CC_PLL1_OUT_EVEN 91
+#define CAM_CC_PLL2 92
+#define CAM_CC_PLL3 93
+#define CAM_CC_PLL3_OUT_EVEN 94
+#define CAM_CC_PLL4 95
+#define CAM_CC_PLL4_OUT_EVEN 96
+#define CAM_CC_PLL6 97
+#define CAM_CC_PLL6_OUT_EVEN 98
+#define CAM_CC_PLL8 99
+#define CAM_CC_PLL8_OUT_EVEN 100
+#define CAM_CC_SFE_0_CLK 101
+#define CAM_CC_SFE_0_CLK_SRC 102
+#define CAM_CC_SFE_0_FAST_AHB_CLK 103
+#define CAM_CC_SLEEP_CLK 104
+#define CAM_CC_SLEEP_CLK_SRC 105
+#define CAM_CC_SLOW_AHB_CLK_SRC 106
+#define CAM_CC_XO_CLK_SRC 107
+
+/* CAM_CC power domains */
+#define CAM_CC_BPS_GDSC 0
+#define CAM_CC_IFE_0_GDSC 1
+#define CAM_CC_IFE_1_GDSC 2
+#define CAM_CC_IPE_0_GDSC 3
+#define CAM_CC_SFE_0_GDSC 4
+#define CAM_CC_TITAN_TOP_GDSC 5
+
+/* CAM_CC resets */
+#define CAM_CC_BPS_BCR 0
+#define CAM_CC_ICP_BCR 1
+#define CAM_CC_IFE_0_BCR 2
+#define CAM_CC_IFE_1_BCR 3
+#define CAM_CC_IPE_0_BCR 4
+#define CAM_CC_SFE_0_BCR 5
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
+#define _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
+
+/* DISP_CC clocks */
+#define DISP_CC_MDSS_ACCU_CLK 0
+#define DISP_CC_MDSS_AHB1_CLK 1
+#define DISP_CC_MDSS_AHB_CLK 2
+#define DISP_CC_MDSS_AHB_CLK_SRC 3
+#define DISP_CC_MDSS_BYTE0_CLK 4
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
+#define DISP_CC_MDSS_BYTE1_CLK 8
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
+#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
+#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
+#define DISP_CC_MDSS_DPTX0_LINK_CLK 14
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22
+#define DISP_CC_MDSS_DPTX1_AUX_CLK 23
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24
+#define DISP_CC_MDSS_DPTX1_LINK_CLK 25
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 26
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 27
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 28
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 29
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 30
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 31
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 32
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 33
+#define DISP_CC_MDSS_DPTX2_AUX_CLK 34
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 35
+#define DISP_CC_MDSS_DPTX2_LINK_CLK 36
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 37
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 38
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 39
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 40
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 41
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 42
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 43
+#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 44
+#define DISP_CC_MDSS_DPTX3_AUX_CLK 45
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 46
+#define DISP_CC_MDSS_DPTX3_LINK_CLK 47
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 48
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 49
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 50
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 51
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 52
+#define DISP_CC_MDSS_ESC0_CLK 53
+#define DISP_CC_MDSS_ESC0_CLK_SRC 54
+#define DISP_CC_MDSS_ESC1_CLK 55
+#define DISP_CC_MDSS_ESC1_CLK_SRC 56
+#define DISP_CC_MDSS_MDP1_CLK 57
+#define DISP_CC_MDSS_MDP_CLK 58
+#define DISP_CC_MDSS_MDP_CLK_SRC 59
+#define DISP_CC_MDSS_MDP_LUT1_CLK 60
+#define DISP_CC_MDSS_MDP_LUT_CLK 61
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 62
+#define DISP_CC_MDSS_PCLK0_CLK 63
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 64
+#define DISP_CC_MDSS_PCLK1_CLK 65
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 66
+#define DISP_CC_MDSS_RSCC_AHB_CLK 67
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 68
+#define DISP_CC_MDSS_VSYNC1_CLK 69
+#define DISP_CC_MDSS_VSYNC_CLK 70
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 71
+#define DISP_CC_PLL0 72
+#define DISP_CC_PLL1 73
+#define DISP_CC_SLEEP_CLK 74
+#define DISP_CC_SLEEP_CLK_SRC 75
+#define DISP_CC_XO_CLK 76
+#define DISP_CC_XO_CLK_SRC 77
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR 0
+#define DISP_CC_MDSS_CORE_INT2_BCR 1
+#define DISP_CC_MDSS_RSCC_BCR 2
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC 0
+#define MDSS_INT2_GDSC 1
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H
+#define _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CB_CLK 1
+#define GPU_CC_CRC_AHB_CLK 2
+#define GPU_CC_CX_FF_CLK 3
+#define GPU_CC_CX_GMU_CLK 4
+#define GPU_CC_CXO_AON_CLK 5
+#define GPU_CC_CXO_CLK 6
+#define GPU_CC_DEMET_CLK 7
+#define GPU_CC_DEMET_DIV_CLK_SRC 8
+#define GPU_CC_FF_CLK_SRC 9
+#define GPU_CC_FREQ_MEASURE_CLK 10
+#define GPU_CC_GMU_CLK_SRC 11
+#define GPU_CC_GX_GMU_CLK 12
+#define GPU_CC_GX_VSENSE_CLK 13
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
+#define GPU_CC_HUB_AON_CLK 15
+#define GPU_CC_HUB_CLK_SRC 16
+#define GPU_CC_HUB_CX_INT_CLK 17
+#define GPU_CC_MEMNOC_GFX_CLK 18
+#define GPU_CC_MND1X_0_GFX3D_CLK 19
+#define GPU_CC_MND1X_1_GFX3D_CLK 20
+#define GPU_CC_PLL0 21
+#define GPU_CC_PLL1 22
+#define GPU_CC_SLEEP_CLK 23
+#define GPU_CC_XO_CLK_SRC 24
+#define GPU_CC_XO_DIV_CLK_SRC 25
+
+/* GDSCs */
+#define GPU_CX_GDSC 0
+#define GPU_GX_GDSC 1
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H
+#define _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H
+
+/* TCSR CC clocks */
+#define TCSR_PCIE_2L_4_CLKREF_EN 0
+#define TCSR_PCIE_2L_5_CLKREF_EN 1
+#define TCSR_PCIE_8L_CLKREF_EN 2
+#define TCSR_USB3_MP0_CLKREF_EN 3
+#define TCSR_USB3_MP1_CLKREF_EN 4
+#define TCSR_USB2_1_CLKREF_EN 5
+#define TCSR_UFS_PHY_CLKREF_EN 6
+#define TCSR_USB4_1_CLKREF_EN 7
+#define TCSR_USB4_2_CLKREF_EN 8
+#define TCSR_USB2_2_CLKREF_EN 9
+#define TCSR_PCIE_4L_CLKREF_EN 10
+#define TCSR_EDP_CLKREF_EN 11
+
+#endif
#define R8A779G0_CLK_CPEX 74
#define R8A779G0_CLK_CBFUSA 75
#define R8A779G0_CLK_R 76
+#define R8A779G0_CLK_CP 77
#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a779h0 CPG Core Clocks */
+
+#define R8A779H0_CLK_ZX 0
+#define R8A779H0_CLK_ZD 1
+#define R8A779H0_CLK_ZS 2
+#define R8A779H0_CLK_ZT 3
+#define R8A779H0_CLK_ZTR 4
+#define R8A779H0_CLK_S0D2 5
+#define R8A779H0_CLK_S0D3 6
+#define R8A779H0_CLK_S0D4 7
+#define R8A779H0_CLK_S0D1_VIO 8
+#define R8A779H0_CLK_S0D2_VIO 9
+#define R8A779H0_CLK_S0D4_VIO 10
+#define R8A779H0_CLK_S0D8_VIO 11
+#define R8A779H0_CLK_VIOBUSD1 12
+#define R8A779H0_CLK_VIOBUSD2 13
+#define R8A779H0_CLK_S0D1_VC 14
+#define R8A779H0_CLK_S0D2_VC 15
+#define R8A779H0_CLK_S0D4_VC 16
+#define R8A779H0_CLK_VCBUSD1 17
+#define R8A779H0_CLK_VCBUSD2 18
+#define R8A779H0_CLK_S0D2_MM 19
+#define R8A779H0_CLK_S0D4_MM 20
+#define R8A779H0_CLK_S0D2_U3DG 21
+#define R8A779H0_CLK_S0D4_U3DG 22
+#define R8A779H0_CLK_S0D2_RT 23
+#define R8A779H0_CLK_S0D3_RT 24
+#define R8A779H0_CLK_S0D4_RT 25
+#define R8A779H0_CLK_S0D6_RT 26
+#define R8A779H0_CLK_S0D2_PER 27
+#define R8A779H0_CLK_S0D3_PER 28
+#define R8A779H0_CLK_S0D4_PER 29
+#define R8A779H0_CLK_S0D6_PER 30
+#define R8A779H0_CLK_S0D12_PER 31
+#define R8A779H0_CLK_S0D24_PER 32
+#define R8A779H0_CLK_S0D1_HSC 33
+#define R8A779H0_CLK_S0D2_HSC 34
+#define R8A779H0_CLK_S0D4_HSC 35
+#define R8A779H0_CLK_S0D8_HSC 36
+#define R8A779H0_CLK_SVD1_IR 37
+#define R8A779H0_CLK_SVD2_IR 38
+#define R8A779H0_CLK_IMPAD1 39
+#define R8A779H0_CLK_IMPAD4 40
+#define R8A779H0_CLK_IMPB 41
+#define R8A779H0_CLK_SVD1_VIP 42
+#define R8A779H0_CLK_SVD2_VIP 43
+#define R8A779H0_CLK_CL 44
+#define R8A779H0_CLK_CL16M 45
+#define R8A779H0_CLK_CL16M_MM 46
+#define R8A779H0_CLK_CL16M_RT 47
+#define R8A779H0_CLK_CL16M_PER 48
+#define R8A779H0_CLK_CL16M_HSC 49
+#define R8A779H0_CLK_ZC0 50
+#define R8A779H0_CLK_ZC1 51
+#define R8A779H0_CLK_ZC2 52
+#define R8A779H0_CLK_ZC3 53
+#define R8A779H0_CLK_ZB3 54
+#define R8A779H0_CLK_ZB3D2 55
+#define R8A779H0_CLK_ZB3D4 56
+#define R8A779H0_CLK_ZG 57
+#define R8A779H0_CLK_SD0H 58
+#define R8A779H0_CLK_SD0 59
+#define R8A779H0_CLK_RPC 60
+#define R8A779H0_CLK_RPCD2 61
+#define R8A779H0_CLK_MSO 62
+#define R8A779H0_CLK_CANFD 63
+#define R8A779H0_CLK_CSI 64
+#define R8A779H0_CLK_FRAY 65
+#define R8A779H0_CLK_IPC 66
+#define R8A779H0_CLK_SASYNCRT 67
+#define R8A779H0_CLK_SASYNCPERD1 68
+#define R8A779H0_CLK_SASYNCPERD2 69
+#define R8A779H0_CLK_SASYNCPERD4 70
+#define R8A779H0_CLK_DSIEXT 71
+#define R8A779H0_CLK_DSIREF 72
+#define R8A779H0_CLK_ADGH 73
+#define R8A779H0_CLK_OSC 74
+#define R8A779H0_CLK_ZR0 75
+#define R8A779H0_CLK_ZR1 76
+#define R8A779H0_CLK_ZR2 77
+#define R8A779H0_CLK_RGMII 78
+#define R8A779H0_CLK_CPEX 79
+#define R8A779H0_CLK_CP 80
+#define R8A779H0_CLK_CBFUSA 81
+#define R8A779H0_CLK_R 82
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */
#define ACLK_AV1_PRE 718
#define PCLK_AV1_PRE 719
#define HCLK_SDIO_PRE 720
-
-#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1)
+#define PCLK_VO1GRF 721
/* scmi-clocks indices */
#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */
#define KEY_ROTATE_LOCK_TOGGLE 0x231 /* Display rotation lock */
+#define KEY_REFRESH_RATE_TOGGLE 0x232 /* Display refresh rate toggle */
#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */
#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Qualcomm MSM8909 interconnect IDs
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H
+
+/* BIMC fabric */
+#define MAS_APPS_PROC 0
+#define MAS_OXILI 1
+#define MAS_SNOC_BIMC_0 2
+#define MAS_SNOC_BIMC_1 3
+#define MAS_TCU_0 4
+#define MAS_TCU_1 5
+#define SLV_EBI 6
+#define SLV_BIMC_SNOC 7
+
+/* PCNOC fabric */
+#define MAS_AUDIO 0
+#define MAS_SPDM 1
+#define MAS_DEHR 2
+#define MAS_QPIC 3
+#define MAS_BLSP_1 4
+#define MAS_USB_HS 5
+#define MAS_CRYPTO 6
+#define MAS_SDCC_1 7
+#define MAS_SDCC_2 8
+#define MAS_SNOC_PCNOC 9
+#define PCNOC_M_0 10
+#define PCNOC_M_1 11
+#define PCNOC_INT_0 12
+#define PCNOC_INT_1 13
+#define PCNOC_S_0 14
+#define PCNOC_S_1 15
+#define PCNOC_S_2 16
+#define PCNOC_S_3 17
+#define PCNOC_S_4 18
+#define PCNOC_S_5 19
+#define PCNOC_S_7 20
+#define SLV_TCSR 21
+#define SLV_SDCC_1 22
+#define SLV_BLSP_1 23
+#define SLV_CRYPTO_0_CFG 24
+#define SLV_MESSAGE_RAM 25
+#define SLV_PDM 26
+#define SLV_PRNG 27
+#define SLV_USB_HS 28
+#define SLV_QPIC 29
+#define SLV_SPDM 30
+#define SLV_SDCC_2 31
+#define SLV_AUDIO 32
+#define SLV_DEHR_CFG 33
+#define SLV_SNOC_CFG 34
+#define SLV_QDSS_CFG 35
+#define SLV_USB_PHY 36
+#define SLV_CAMERA_SS_CFG 37
+#define SLV_DISP_SS_CFG 38
+#define SLV_VENUS_CFG 39
+#define SLV_TLMM 40
+#define SLV_GPU_CFG 41
+#define SLV_IMEM_CFG 42
+#define SLV_BIMC_CFG 43
+#define SLV_PMIC_ARB 44
+#define SLV_TCU 45
+#define SLV_PCNOC_SNOC 46
+
+/* SNOC fabric */
+#define MAS_QDSS_BAM 0
+#define MAS_BIMC_SNOC 1
+#define MAS_MDP 2
+#define MAS_PCNOC_SNOC 3
+#define MAS_VENUS 4
+#define MAS_VFE 5
+#define MAS_QDSS_ETR 6
+#define MM_INT_0 7
+#define MM_INT_1 8
+#define MM_INT_2 9
+#define MM_INT_BIMC 10
+#define QDSS_INT 11
+#define SNOC_INT_0 12
+#define SNOC_INT_1 13
+#define SNOC_INT_BIMC 14
+#define SLV_KPSS_AHB 15
+#define SLV_SNOC_BIMC_0 16
+#define SLV_SNOC_BIMC_1 17
+#define SLV_IMEM 18
+#define SLV_SNOC_PCNOC 19
+#define SLV_QDSS_STM 20
+#define SLV_CATS_0 21
+#define SLV_CATS_1 22
+
+#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Qualcomm SM7150 interconnect IDs
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H
+
+#define MASTER_A1NOC_CFG 0
+#define MASTER_QUP_0 1
+#define MASTER_TSIF 2
+#define MASTER_EMMC 3
+#define MASTER_SDCC_2 4
+#define MASTER_SDCC_4 5
+#define MASTER_UFS_MEM 6
+#define A1NOC_SNOC_SLV 7
+#define SLAVE_SERVICE_A1NOC 8
+
+#define MASTER_A2NOC_CFG 0
+#define MASTER_QDSS_BAM 1
+#define MASTER_QUP_1 2
+#define MASTER_CNOC_A2NOC 3
+#define MASTER_CRYPTO_CORE_0 4
+#define MASTER_IPA 5
+#define MASTER_PCIE 6
+#define MASTER_QDSS_ETR 7
+#define MASTER_USB3 8
+#define A2NOC_SNOC_SLV 9
+#define SLAVE_ANOC_PCIE_GEM_NOC 10
+#define SLAVE_SERVICE_A2NOC 11
+
+#define MASTER_CAMNOC_HF0_UNCOMP 0
+#define MASTER_CAMNOC_RT_UNCOMP 1
+#define MASTER_CAMNOC_SF_UNCOMP 2
+#define MASTER_CAMNOC_NRT_UNCOMP 3
+#define SLAVE_CAMNOC_UNCOMP 4
+
+#define MASTER_NPU 0
+#define SLAVE_CDSP_GEM_NOC 1
+
+#define MASTER_SPDM 0
+#define SNOC_CNOC_MAS 1
+#define MASTER_QDSS_DAP 2
+#define SLAVE_A1NOC_CFG 3
+#define SLAVE_A2NOC_CFG 4
+#define SLAVE_AHB2PHY_NORTH 5
+#define SLAVE_AHB2PHY_SOUTH 6
+#define SLAVE_AHB2PHY_WEST 7
+#define SLAVE_AOP 8
+#define SLAVE_AOSS 9
+#define SLAVE_CAMERA_CFG 10
+#define SLAVE_CAMERA_NRT_THROTTLE_CFG 11
+#define SLAVE_CAMERA_RT_THROTTLE_CFG 12
+#define SLAVE_CLK_CTL 13
+#define SLAVE_CDSP_CFG 14
+#define SLAVE_RBCPR_CX_CFG 15
+#define SLAVE_RBCPR_MX_CFG 16
+#define SLAVE_CRYPTO_0_CFG 17
+#define SLAVE_CNOC_DDRSS 18
+#define SLAVE_DISPLAY_CFG 19
+#define SLAVE_DISPLAY_THROTTLE_CFG 20
+#define SLAVE_EMMC_CFG 21
+#define SLAVE_GLM 22
+#define SLAVE_GRAPHICS_3D_CFG 23
+#define SLAVE_IMEM_CFG 24
+#define SLAVE_IPA_CFG 25
+#define SLAVE_CNOC_MNOC_CFG 26
+#define SLAVE_PCIE_CFG 27
+#define SLAVE_PDM 28
+#define SLAVE_PIMEM_CFG 29
+#define SLAVE_PRNG 30
+#define SLAVE_QDSS_CFG 31
+#define SLAVE_QUP_0 32
+#define SLAVE_QUP_1 33
+#define SLAVE_SDCC_2 34
+#define SLAVE_SDCC_4 35
+#define SLAVE_SNOC_CFG 36
+#define SLAVE_SPDM_WRAPPER 37
+#define SLAVE_TCSR 38
+#define SLAVE_TLMM_NORTH 39
+#define SLAVE_TLMM_SOUTH 40
+#define SLAVE_TLMM_WEST 41
+#define SLAVE_TSIF 42
+#define SLAVE_UFS_MEM_CFG 43
+#define SLAVE_USB3 44
+#define SLAVE_VENUS_CFG 45
+#define SLAVE_VENUS_CVP_THROTTLE_CFG 46
+#define SLAVE_VENUS_THROTTLE_CFG 47
+#define SLAVE_VSENSE_CTRL_CFG 48
+#define SLAVE_CNOC_A2NOC 49
+#define SLAVE_SERVICE_CNOC 50
+
+#define MASTER_CNOC_DC_NOC 0
+#define SLAVE_GEM_NOC_CFG 1
+#define SLAVE_LLCC_CFG 2
+
+#define MASTER_AMPSS_M0 0
+#define MASTER_SYS_TCU 1
+#define MASTER_GEM_NOC_CFG 2
+#define MASTER_COMPUTE_NOC 3
+#define MASTER_MNOC_HF_MEM_NOC 4
+#define MASTER_MNOC_SF_MEM_NOC 5
+#define MASTER_GEM_NOC_PCIE_SNOC 6
+#define MASTER_SNOC_GC_MEM_NOC 7
+#define MASTER_SNOC_SF_MEM_NOC 8
+#define MASTER_GRAPHICS_3D 9
+#define SLAVE_MSS_PROC_MS_MPU_CFG 10
+#define SLAVE_GEM_NOC_SNOC 11
+#define SLAVE_LLCC 12
+#define SLAVE_SERVICE_GEM_NOC 13
+
+
+#define MASTER_LLCC 0
+#define SLAVE_EBI_CH0 1
+
+#define MASTER_CNOC_MNOC_CFG 0
+#define MASTER_CAMNOC_HF0 1
+#define MASTER_CAMNOC_NRT 2
+#define MASTER_CAMNOC_RT 3
+#define MASTER_CAMNOC_SF 4
+#define MASTER_MDP_PORT0 5
+#define MASTER_MDP_PORT1 6
+#define MASTER_ROTATOR 7
+#define MASTER_VIDEO_P0 8
+#define MASTER_VIDEO_P1 9
+#define MASTER_VIDEO_PROC 10
+#define SLAVE_MNOC_SF_MEM_NOC 11
+#define SLAVE_MNOC_HF_MEM_NOC 12
+#define SLAVE_SERVICE_MNOC 13
+
+#define MASTER_SNOC_CFG 0
+#define A1NOC_SNOC_MAS 1
+#define A2NOC_SNOC_MAS 2
+#define MASTER_GEM_NOC_SNOC 3
+#define MASTER_PIMEM 4
+#define MASTER_GIC 5
+#define SLAVE_APPSS 6
+#define SNOC_CNOC_SLV 7
+#define SLAVE_SNOC_GEM_NOC_GC 8
+#define SLAVE_SNOC_GEM_NOC_SF 9
+#define SLAVE_OCIMEM 10
+#define SLAVE_PIMEM 11
+#define SLAVE_SERVICE_SNOC 12
+#define SLAVE_QDSS_STM 13
+#define SLAVE_TCU 14
+
+#endif
#define SLAVE_GEM_NOC_CNOC 12
#define SLAVE_LLCC 13
#define SLAVE_MEM_NOC_PCIE_SNOC 14
-#define MASTER_MNOC_HF_MEM_NOC_DISP 15
-#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16
-#define SLAVE_LLCC_DISP 17
-#define MASTER_ANOC_PCIE_GEM_NOC_PCIE 18
-#define SLAVE_LLCC_PCIE 19
#define MASTER_LPIAON_NOC 0
#define SLAVE_LPASS_GEM_NOC 1
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
-#define MASTER_LLCC_DISP 2
-#define SLAVE_EBI1_DISP 3
-#define MASTER_LLCC_PCIE 4
-#define SLAVE_EBI1_PCIE 5
#define MASTER_AV1_ENC 0
#define MASTER_CAMNOC_HF 1
#define SLAVE_MNOC_HF_MEM_NOC 10
#define SLAVE_MNOC_SF_MEM_NOC 11
#define SLAVE_SERVICE_MNOC 12
-#define MASTER_MDP_DISP 13
-#define SLAVE_MNOC_HF_MEM_NOC_DISP 14
#define MASTER_CDSP_PROC 0
#define SLAVE_CDSP_MEM_NOC 1
#define MASTER_PCIE_NORTH 0
#define MASTER_PCIE_SOUTH 1
#define SLAVE_ANOC_PCIE_GEM_NOC 2
-#define MASTER_PCIE_NORTH_PCIE 3
-#define MASTER_PCIE_SOUTH_PCIE 4
-#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE 5
#define MASTER_PCIE_3 0
#define MASTER_PCIE_4 1
#define MASTER_PCIE_5 2
#define SLAVE_PCIE_NORTH 3
-#define MASTER_PCIE_3_PCIE 4
-#define MASTER_PCIE_4_PCIE 5
-#define MASTER_PCIE_5_PCIE 6
-#define SLAVE_PCIE_NORTH_PCIE 7
#define MASTER_PCIE_0 0
#define MASTER_PCIE_1 1
#define MASTER_PCIE_6A 3
#define MASTER_PCIE_6B 4
#define SLAVE_PCIE_SOUTH 5
-#define MASTER_PCIE_0_PCIE 6
-#define MASTER_PCIE_1_PCIE 7
-#define MASTER_PCIE_2_PCIE 8
-#define MASTER_PCIE_6A_PCIE 9
-#define MASTER_PCIE_6B_PCIE 10
-#define SLAVE_PCIE_SOUTH_PCIE 11
#define MASTER_A1NOC_SNOC 0
#define MASTER_A2NOC_SNOC 1
#define LED_FUNCTION_TX "tx"
#define LED_FUNCTION_USB "usb"
#define LED_FUNCTION_WAN "wan"
+#define LED_FUNCTION_WAN_ONLINE "wan-online"
#define LED_FUNCTION_WLAN "wlan"
+#define LED_FUNCTION_WLAN_2GHZ "wlan-2ghz"
+#define LED_FUNCTION_WLAN_5GHZ "wlan-5ghz"
+#define LED_FUNCTION_WLAN_6GHZ "wlan-6ghz"
#define LED_FUNCTION_WPS "wps"
#endif /* __DT_BINDINGS_LEDS_H */
#define STM32F7_RCC_APB2_SAI1 22
#define STM32F7_RCC_APB2_SAI2 23
#define STM32F7_RCC_APB2_LTDC 26
+#define STM32F7_RCC_APB2_DSI 27
#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2023 Amlogic, Inc.
* Author: hongyu chen1 <hongyu.chen1@amlogic.com>
#define MSM8953_VDDMX 5
#define MSM8953_VDDMX_AO 6
+/* MSM8974 Power Domain Indexes */
+#define MSM8974_VDDCX 0
+#define MSM8974_VDDCX_AO 1
+#define MSM8974_VDDCX_VFC 2
+#define MSM8974_VDDGFX 3
+#define MSM8974_VDDGFX_VFC 4
+
/* MSM8976 Power Domain Indexes */
#define MSM8976_VDDCX 0
#define MSM8976_VDDCX_AO 1
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__
+#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__
+
+/*
+ * These power domain indices match the Power Domain Register Numbers (PDR)
+ */
+
+#define R8A779H0_PD_A1E0D0C0 0
+#define R8A779H0_PD_A1E0D0C1 1
+#define R8A779H0_PD_A1E0D0C2 2
+#define R8A779H0_PD_A1E0D0C3 3
+#define R8A779H0_PD_A2E0D0 16
+#define R8A779H0_PD_A3CR0 21
+#define R8A779H0_PD_A3CR1 22
+#define R8A779H0_PD_A3CR2 23
+#define R8A779H0_PD_A33DGA 24
+#define R8A779H0_PD_A23DGB 25
+#define R8A779H0_PD_C4 31
+#define R8A779H0_PD_A1DSP0 33
+#define R8A779H0_PD_A2IMP01 34
+#define R8A779H0_PD_A2PSC 35
+#define R8A779H0_PD_A2CV0 36
+#define R8A779H0_PD_A2CV1 37
+#define R8A779H0_PD_A3IMR0 38
+#define R8A779H0_PD_A3IMR1 39
+#define R8A779H0_PD_A3VC 40
+#define R8A779H0_PD_A2CN0 42
+#define R8A779H0_PD_A1CN0 44
+#define R8A779H0_PD_A1DSP1 45
+#define R8A779H0_PD_A2DMA 47
+#define R8A779H0_PD_A2CV2 48
+#define R8A779H0_PD_A2CV3 49
+#define R8A779H0_PD_A3IMR2 50
+#define R8A779H0_PD_A3IMR3 51
+#define R8A779H0_PD_A3PCI 52
+#define R8A779H0_PD_A2PCIPHY 53
+#define R8A779H0_PD_A3VIP0 56
+#define R8A779H0_PD_A3VIP2 58
+#define R8A779H0_PD_A3ISP0 60
+#define R8A779H0_PD_A3DUL 62
+
+/* Always-on power area */
+#define R8A779H0_PD_ALWAYS_ON 64
+
+#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */
/* ETHWARP resets */
#define MT7988_ETHWARP_RST_SWITCH 0
+/* INFRA resets */
+#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0
+#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1
+
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
+
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H
+#define _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H
+
+#define GPUCC_GPU_CC_ACD_BCR 0
+#define GPUCC_GPU_CC_CB_BCR 1
+#define GPUCC_GPU_CC_CX_BCR 2
+#define GPUCC_GPU_CC_FAST_HUB_BCR 3
+#define GPUCC_GPU_CC_FF_BCR 4
+#define GPUCC_GPU_CC_GFX3D_AON_BCR 5
+#define GPUCC_GPU_CC_GMU_BCR 6
+#define GPUCC_GPU_CC_GX_BCR 7
+#define GPUCC_GPU_CC_XO_BCR 8
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_
+#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_
+
+#define RST_MAIN_AP 0
+#define RST_RISCV_CPU 1
+#define RST_RISCV_LOW_SPEED_LOGIC 2
+#define RST_RISCV_CMN 3
+#define RST_HSDMA 4
+#define RST_SYSDMA 5
+#define RST_EFUSE0 6
+#define RST_EFUSE1 7
+#define RST_RTC 8
+#define RST_TIMER 9
+#define RST_WDT 10
+#define RST_AHB_ROM0 11
+#define RST_AHB_ROM1 12
+#define RST_I2C0 13
+#define RST_I2C1 14
+#define RST_I2C2 15
+#define RST_I2C3 16
+#define RST_GPIO0 17
+#define RST_GPIO1 18
+#define RST_GPIO2 19
+#define RST_PWM 20
+#define RST_AXI_SRAM0 21
+#define RST_AXI_SRAM1 22
+#define RST_SF0 23
+#define RST_SF1 24
+#define RST_LPC 25
+#define RST_ETH0 26
+#define RST_EMMC 27
+#define RST_SD 28
+#define RST_UART0 29
+#define RST_UART1 30
+#define RST_UART2 31
+#define RST_UART3 32
+#define RST_SPI0 33
+#define RST_SPI1 34
+#define RST_DBG_I2C 35
+#define RST_PCIE0 36
+#define RST_PCIE1 37
+#define RST_DDR0 38
+#define RST_DDR1 39
+#define RST_DDR2 40
+#define RST_DDR3 41
+#define RST_FAU0 42
+#define RST_FAU1 43
+#define RST_FAU2 44
+#define RST_RXU0 45
+#define RST_RXU1 46
+#define RST_RXU2 47
+#define RST_RXU3 48
+#define RST_RXU4 49
+#define RST_RXU5 50
+#define RST_RXU6 51
+#define RST_RXU7 52
+#define RST_RXU8 53
+#define RST_RXU9 54
+#define RST_RXU10 55
+#define RST_RXU11 56
+#define RST_RXU12 57
+#define RST_RXU13 58
+#define RST_RXU14 59
+#define RST_RXU15 60
+#define RST_RXU16 61
+#define RST_RXU17 62
+#define RST_RXU18 63
+#define RST_RXU19 64
+#define RST_RXU20 65
+#define RST_RXU21 66
+#define RST_RXU22 67
+#define RST_RXU23 68
+#define RST_RXU24 69
+#define RST_RXU25 70
+#define RST_RXU26 71
+#define RST_RXU27 72
+#define RST_RXU28 73
+#define RST_RXU29 74
+#define RST_RXU30 75
+#define RST_RXU31 76
+
+#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */
/*
* The DW APB ICTL intc on MB is connected to CPU intc via a
* DT "invisible" DW APB GPIO block, configured to simply pass thru
- * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
+ * interrupts - setup accordingly in platform init (plat-axs10x/ax10x.c)
*
- * So here we mimic a direct connection betwen them, ignoring the
+ * So here we mimic a direct connection between them, ignoring the
* ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
* instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
*
};
gmac: ethernet@8000 {
- #interrupt-cells = <1>;
compatible = "snps,dwmac";
reg = <0x8000 0x2000>;
interrupts = <10>;
/*
* Embedded Vision subsystem UIO mappings; only relevant for EV VDK
*
- * This node is intentionally put outside of MB above becase
+ * This node is intentionally put outside of MB above because
* it maps areas outside of MB's 0xez-0xfz.
*/
uio_ev: uio@d0000000 {
vcc-pg-supply = <®_dldo1>;
};
+®_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3-tv-usb";
+};
+
®_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
#size-cells = <1>;
ranges;
- cbus: cbus@c1100000 {
+ cbus: bus@c1100000 {
compatible = "simple-bus";
reg = <0xc1100000 0x200000>;
#address-cells = <1>;
};
};
- aobus: aobus@c8100000 {
+ aobus: bus@c8100000 {
compatible = "simple-bus";
reg = <0xc8100000 0x100000>;
#address-cells = <1>;
reg = <0xd9040000 0x10000>;
};
- secbus: secbus@da000000 {
+ secbus: bus@da000000 {
compatible = "simple-bus";
reg = <0xda000000 0x6000>;
#address-cells = <1>;
};
&hwrng {
- compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
};
&hwrng {
- compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
/* Direct-mapped development chip ROM */
pb1176_rom@10200000 {
- compatible = "direct-mapped";
+ compatible = "mtd-rom";
reg = <0x10200000 0x4000>;
bank-width = <1>;
};
bridge {
compatible = "ti,ths8134b", "ti,ths8134";
- #address-cells = <1>;
- #size-cells = <0>;
ports {
#address-cells = <1>;
vga {
compatible = "vga-connector";
+ label = "J30";
port {
vga_con_in: endpoint {
bridge {
compatible = "ti,ths8134b", "ti,ths8134";
- #address-cells = <1>;
- #size-cells = <0>;
ports {
#address-cells = <1>;
vga {
compatible = "vga-connector";
+ label = "J1";
port {
vga_con_in: endpoint {
#address-cells = <1>;
#size-cells = <1>;
- chosen { };
+ chosen {
+ stdout-path = &v2m_serial0;
+ };
aliases {
serial0 = &v2m_serial0;
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
reg-names = "nand", "nand-int-base";
status = "disabled";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "nand";
+ interrupt-names = "nand_ctlrdy";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
};
serial@4400 {
num-cs = <8>;
status = "disabled";
};
+
+ nand_controller: nand-controller@2000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x2000 0x600>, <0xf0 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
};
};
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
num-cs = <8>;
status = "disabled";
};
+
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
};
};
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
};
&nand_controller {
+ brcm,wp-not-connected;
status = "okay";
+};
- nand@0 {
- compatible = "brcm,nandcs";
- reg = <0>;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- brcm,nand-oob-sectors-size = <16>;
- };
+&nandcs {
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ brcm,nand-oob-sector-size = <16>;
+ nand-on-flash-bbt;
};
&ahci {
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
gpio_keys {
compatible = "gpio-keys";
- button-esc {
+ button-reset {
debounce-interval = <100>;
wakeup-source;
- linux,code = <KEY_ESC>;
+ linux,code = <KEY_RESTART>;
label = "reset";
/* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
};
/* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */
- switch {
+ ethernet-switch {
compatible = "realtek,rtl8366rb";
/* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
#interrupt-cells = <1>;
};
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
label = "lan0";
phy-handle = <&phy0>;
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "lan1";
phy-handle = <&phy1>;
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan2";
phy-handle = <&phy2>;
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan3";
phy-handle = <&phy3>;
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "wan";
phy-handle = <&phy4>;
};
- rtl8366rb_cpu_port: port@5 {
+ rtl8366rb_cpu_port: ethernet-port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
#address-cells = <1>;
#size-cells = <0>;
- phy0: phy@0 {
+ phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&switch_intc>;
interrupts = <0>;
};
- phy1: phy@1 {
+ phy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&switch_intc>;
interrupts = <1>;
};
- phy2: phy@2 {
+ phy2: ethernet-phy@2 {
reg = <2>;
interrupt-parent = <&switch_intc>;
interrupts = <2>;
};
- phy3: phy@3 {
+ phy3: ethernet-phy@3 {
reg = <3>;
interrupt-parent = <&switch_intc>;
interrupts = <3>;
};
- phy4: phy@4 {
+ phy4: ethernet-phy@4 {
reg = <4>;
interrupt-parent = <&switch_intc>;
interrupts = <12>;
gpio_keys {
compatible = "gpio-keys";
- button-esc {
+ button-reset {
debounce-interval = <100>;
wakeup-source;
- linux,code = <KEY_ESC>;
+ linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
};
button-setup {
debounce-interval = <50>;
wakeup-source;
- linux,code = <KEY_SETUP>;
+ linux,code = <KEY_RESTART>;
label = "factory reset";
/* Conflict with NAND flash */
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
- switch@0 {
+ ethernet-switch@0 {
compatible = "vitesse,vsc7385";
reg = <0>;
/* Specified for 2.5 MHz or below */
gpio-controller;
#gpio-cells = <2>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
label = "lan1";
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "lan2";
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan3";
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan4";
};
- vsc: port@6 {
+ vsc: ethernet-port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac1>;
button-setup {
debounce-interval = <100>;
wakeup-source;
- linux,code = <KEY_SETUP>;
+ linux,code = <KEY_RESTART>;
label = "factory reset";
/* Conflict with NAND flash */
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
- switch@0 {
+ ethernet-switch@0 {
compatible = "vitesse,vsc7395";
reg = <0>;
/* Specified for 2.5 MHz or below */
gpio-controller;
#gpio-cells = <2>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
label = "lan1";
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "lan2";
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan3";
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan4";
};
- vsc: port@6 {
+ vsc: ethernet-port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac1>;
/ {
model = "Wiliboard WBD-111";
- compatible = "wiliboard,wbd111", "cortina,gemini";
+ compatible = "wiligear,wiliboard-wbd111", "cortina,gemini";
#address-cells = <1>;
#size-cells = <1>;
gpio_keys {
compatible = "gpio-keys";
- button-setup {
+ button-reset {
debounce-interval = <100>;
wakeup-source;
- linux,code = <KEY_SETUP>;
+ linux,code = <KEY_RESTART>;
label = "reset";
/* Conflict with ICE */
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
/ {
model = "Wiliboard WBD-222";
- compatible = "wiliboard,wbd222", "cortina,gemini";
+ compatible = "wiligear,wiliboard-wbd222", "cortina,gemini";
#address-cells = <1>;
#size-cells = <1>;
gpio_keys {
compatible = "gpio-keys";
- button-setup {
+ button-reset {
debounce-interval = <100>;
wakeup-source;
- linux,code = <KEY_SETUP>;
+ linux,code = <KEY_RESTART>;
label = "reset";
/* Conflict with ICE */
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
/ {
model = "SolidRun Clearfog GTR L8";
+ compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
+ "marvell,armada380";
+
+ /* CON25 */
+ sfp1: sfp-1 {
+ compatible = "sff,sfp";
+ pinctrl-0 = <&cf_gtr_sfp1_pins>;
+ pinctrl-names = "default";
+ i2c-bus = <&i2c0>;
+ mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ };
};
&mdio {
ethernet-port@1 {
reg = <1>;
- label = "lan8";
+ label = "lan1";
phy-handle = <&switch0phy0>;
};
ethernet-port@2 {
reg = <2>;
- label = "lan7";
+ label = "lan2";
phy-handle = <&switch0phy1>;
};
ethernet-port@3 {
reg = <3>;
- label = "lan6";
+ label = "lan3";
phy-handle = <&switch0phy2>;
};
ethernet-port@4 {
reg = <4>;
- label = "lan5";
+ label = "lan4";
phy-handle = <&switch0phy3>;
};
ethernet-port@5 {
reg = <5>;
- label = "lan4";
+ label = "lan5";
phy-handle = <&switch0phy4>;
};
ethernet-port@6 {
reg = <6>;
- label = "lan3";
+ label = "lan6";
phy-handle = <&switch0phy5>;
};
ethernet-port@7 {
reg = <7>;
- label = "lan2";
+ label = "lan7";
phy-handle = <&switch0phy6>;
};
ethernet-port@8 {
reg = <8>;
- label = "lan1";
+ label = "lan8";
phy-handle = <&switch0phy7>;
};
+ ethernet-port@9 {
+ reg = <9>;
+ label = "lan-sfp";
+ phy-mode = "sgmii";
+ sfp = <&sfp1>;
+ managed = "in-band-status";
+ };
+
ethernet-port@10 {
reg = <10>;
phy-mode = "2500base-x";
-
ethernet = <ð1>;
+
fixed-link {
speed = <2500>;
full-duplex;
/ {
model = "SolidRun Clearfog GTR S4";
+ compatible = "solidrun,clearfog-gtr-s4", "marvell,armada385",
+ "marvell,armada380";
};
&sfp0 {
};
pinctrl@18000 {
- cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
- marvell,pins = "mpp18";
- marvell,function = "gpio";
- };
-
- cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
- marvell,pins = "mpp22";
+ cf_gtr_fan_pwm: cf-gtr-fan-pwm {
+ marvell,pins = "mpp23";
marvell,function = "gpio";
};
- cf_gtr_fan_pwm: cf-gtr-fan-pwm {
- marvell,pins = "mpp23";
+ cf_gtr_front_button_pins: cf-gtr-front-button-pins {
+ marvell,pins = "mpp53";
marvell,function = "gpio";
};
marvell,function = "i2c1";
};
+ cf_gtr_isolation_pins: cf-gtr-isolation-pins {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_led_pins: led-pins {
+ marvell,pins = "mpp42", "mpp52";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_lte_disable_pins: lte-disable-pins {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_pci_pins: pci-pins {
+ // pci reset
+ marvell,pins = "mpp33", "mpp35", "mpp44";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
+ marvell,pins = "mpp48";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
+ marvell,pins = "mpp36";
+ marvell,function = "gpio";
+ };
+
cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
marvell,pins = "mpp21", "mpp28",
"mpp37", "mpp38",
marvell,function = "sd0";
};
- cf_gtr_isolation_pins: cf-gtr-isolation-pins {
- marvell,pins = "mpp47";
+ cf_gtr_sfp0_pins: sfp0-pins {
+ /* sfp modabs, txdisable */
+ marvell,pins = "mpp25", "mpp46";
marvell,function = "gpio";
};
- cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
- marvell,pins = "mpp48";
+ cf_gtr_sfp1_pins: sfp1-pins {
+ /* sfp modabs, txdisable */
+ marvell,pins = "mpp24", "mpp54";
marvell,function = "gpio";
};
marvell,function = "spi1";
};
- cf_gtr_front_button_pins: cf-gtr-front-button-pins {
- marvell,pins = "mpp53";
+ cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
+ marvell,pins = "mpp18";
marvell,function = "gpio";
};
- cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
- marvell,pins = "mpp36";
+ cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
+ marvell,pins = "mpp22";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_wifi_disable_pins: wifi-disable-pins {
+ marvell,pins = "mpp30", "mpp31";
marvell,function = "gpio";
};
};
};
pcie {
+ pinctrl-0 = <&cf_gtr_pci_pins>;
+ pinctrl-names = "default";
status = "okay";
/*
* The PCIe units are accessible through
* the mini-PCIe connectors on the board.
*/
+ /* CON3 - serdes 0 */
pcie@1,0 {
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
+ /* CON4 - serdes 2 */
pcie@2,0 {
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
+ /* CON2 - serdes 4 */
pcie@3,0 {
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
- sfp0: sfp {
+ /* CON5 */
+ sfp0: sfp-0 {
compatible = "sff,sfp";
+ pinctrl-0 = <&cf_gtr_sfp0_pins>;
+ pinctrl-names = "default";
i2c-bus = <&i2c1>;
- los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
gpio-leds {
compatible = "gpio-leds";
+ pinctrl-0 = <&cf_gtr_led_pins>;
+ pinctrl-names = "default";
led1 {
function = LED_FUNCTION_CPU;
};
&gpio0 {
- pinctrl-0 = <&cf_gtr_fan_pwm>;
+ pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>;
pinctrl-names = "default";
wifi-disable {
};
&gpio1 {
- pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
+ pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>;
pinctrl-names = "default";
lte-disable {
/ {
model = "SolidRun Clearfog A1";
- compatible = "solidrun,clearfog-a1", "marvell,armada388",
- "marvell,armada385", "marvell,armada380";
+ compatible = "solidrun,clearfog-pro-a1", "solidrun,clearfog-a1",
+ "marvell,armada388", "marvell,armada385",
+ "marvell,armada380";
soc {
internal-regs {
/* connect xtal input as source of pll0 and pll1 */
silabs,pll-source = <0 0>, <1 0>;
- clkout0 {
+ clkout@0 {
reg = <0>;
silabs,drive-strength = <8>;
silabs,multisynth-source = <0>;
silabs,pll-master;
};
- clkout2 {
+ clkout@2 {
reg = <2>;
silabs,drive-strength = <8>;
silabs,multisynth-source = <1>;
&twsi1 {
status = "okay";
pmic: max8925@3c {
- compatible = "maxium,max8925";
+ compatible = "maxim,max8925";
reg = <0x3c>;
interrupts = <1>;
interrupt-parent = <&intcmux4>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sama7g54_curiosity.dts - Device Tree file for SAMA7G54 Curiosity Board
+ *
+ * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Mihai Sain <mihai.sain@microchip.com>
+ *
+ */
+/dts-v1/;
+#include "sama7g5-pinfunc.h"
+#include "sama7g5.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/pinctrl/at91.h>
+
+/ {
+ model = "Microchip SAMA7G54 Curiosity";
+ compatible = "microchip,sama7g54-curiosity", "microchip,sama7g5", "microchip,sama7";
+
+ aliases {
+ serial0 = &uart3;
+ i2c0 = &i2c10;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+
+ button-user {
+ label = "user-button";
+ gpios = <&pioA PIN_PD19 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_PROG1>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led_gpio_default>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_BOOT;
+ gpios = <&pioA PIN_PD14 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_CPU;
+ gpios = <&pioA PIN_PB15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x10000000>; /* 256 MiB DDR3L-1066 16-bit */
+ };
+};
+
+&adc {
+ vddana-supply = <&vddout25>;
+ vref-supply = <&vddout25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+};
+
+&dma0 {
+ status = "okay";
+};
+
+&dma1 {
+ status = "okay";
+};
+
+&dma2 {
+ status = "okay";
+};
+
+&ebi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand_default>;
+ status = "okay";
+
+ nand_controller: nand-controller {
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "nand: at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "nand: u-boot";
+ reg = <0x40000 0x100000>;
+ };
+
+ bootloaderenv@140000 {
+ label = "nand: u-boot env";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "nand: device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "nand: kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "nand: rootfs";
+ reg = <0x800000 0x1f800000>;
+ };
+ };
+ };
+ };
+};
+
+&flx3 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+
+ uart3: serial@200 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx3_default>;
+ status = "okay";
+ };
+};
+
+&flx10 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c10: i2c@600 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx10_default>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ size = <256>;
+ vcc-supply = <&vdd_3v3>;
+ };
+
+ pmic@5b {
+ compatible = "microchip,mcp16502";
+ reg = <0x5b>;
+
+ regulators {
+ vdd_3v3: VDD_IO {
+ regulator-name = "VDD_IO";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ vddioddr: VDD_DDR {
+ regulator-name = "VDD_DDR";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1350000>;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1350000>;
+ regulator-mode = <4>;
+ };
+ };
+
+ vddcore: VDD_CORE {
+ regulator-name = "VDD_CORE";
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1150000>;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ vddcpu: VDD_OTHER {
+ regulator-name = "VDD_OTHER";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-ramp-delay = <3125>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1050000>;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ vldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-suspend-microvolt = <1800000>;
+ regulator-on-in-suspend;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vldo2: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-suspend-microvolt = <3300000>;
+ regulator-on-in-suspend;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+ };
+};
+
+&main_xtal {
+ clock-frequency = <24000000>;
+};
+
+&qspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_default>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <100000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ m25p,fast-read;
+ };
+};
+
+&pioA {
+ pinctrl_flx3_default: flx3-default {
+ pinmux = <PIN_PD16__FLEXCOM3_IO0>,
+ <PIN_PD17__FLEXCOM3_IO1>;
+ bias-pull-up;
+ };
+
+ pinctrl_flx10_default: flx10-default {
+ pinmux = <PIN_PC30__FLEXCOM10_IO0>,
+ <PIN_PC31__FLEXCOM10_IO1>;
+ bias-pull-up;
+ };
+
+ pinctrl_key_gpio_default: key-gpio-default {
+ pinmux = <PIN_PD19__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_led_gpio_default: led-gpio-default {
+ pinmux = <PIN_PD13__GPIO>,
+ <PIN_PD14__GPIO>,
+ <PIN_PB15__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_mikrobus1_an_default: mikrobus1-an-default {
+ pinmux = <PIN_PC15__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_an_default: mikrobus2-an-default {
+ pinmux = <PIN_PC13__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_nand_default: nand-default {
+ pinmux = <PIN_PD9__D0>,
+ <PIN_PD10__D1>,
+ <PIN_PD11__D2>,
+ <PIN_PC21__D3>,
+ <PIN_PC22__D4>,
+ <PIN_PC23__D5>,
+ <PIN_PC24__D6>,
+ <PIN_PD2__D7>,
+ <PIN_PD3__NANDRDY>,
+ <PIN_PD4__NCS3_NANDCS>,
+ <PIN_PD5__NWE_NWR0_NANDWE>,
+ <PIN_PD6__NRD_NANDOE>,
+ <PIN_PD7__A21_NANDALE>,
+ <PIN_PD8__A22_NANDCLE>;
+ bias-disable;
+ slew-rate = <0>;
+ };
+
+ pinctrl_qspi1_default: qspi1-default {
+ pinmux = <PIN_PB22__QSPI1_IO3>,
+ <PIN_PB23__QSPI1_IO2>,
+ <PIN_PB24__QSPI1_IO1>,
+ <PIN_PB25__QSPI1_IO0>,
+ <PIN_PB26__QSPI1_CS>,
+ <PIN_PB27__QSPI1_SCK>;
+ bias-pull-up;
+ slew-rate = <0>;
+ };
+
+ pinctrl_sdmmc0_default: sdmmc0-default {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_RSTN>,
+ <PIN_PA3__SDMMC0_DAT0>,
+ <PIN_PA4__SDMMC0_DAT1>,
+ <PIN_PA5__SDMMC0_DAT2>,
+ <PIN_PA6__SDMMC0_DAT3>;
+ bias-pull-up;
+ slew-rate = <0>;
+ };
+
+ pinctrl_sdmmc1_default: sdmmc1-default {
+ pinmux = <PIN_PB29__SDMMC1_CMD>,
+ <PIN_PB30__SDMMC1_CK>,
+ <PIN_PB31__SDMMC1_DAT0>,
+ <PIN_PC0__SDMMC1_DAT1>,
+ <PIN_PC1__SDMMC1_DAT2>,
+ <PIN_PC2__SDMMC1_DAT3>,
+ <PIN_PC4__SDMMC1_CD>;
+ bias-pull-up;
+ slew-rate = <0>;
+ };
+};
+
+&rtt {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+};
+
+/* M.2 slot for wireless card */
+&sdmmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ sdhci-caps-mask = <0x0 0x00200000>;
+ vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&vdd_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default>;
+ status = "okay";
+};
+
+/* micro SD socket */
+&sdmmc1 {
+ bus-width = <4>;
+ disable-wp;
+ sdhci-caps-mask = <0x0 0x00200000>;
+ vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&vdd_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_default>;
+ status = "okay";
+};
+
+&slow_xtal {
+ clock-frequency = <32768>;
+};
+
+&shdwc {
+ debounce-delay-us = <976>;
+ status = "okay";
+
+ input@0 {
+ reg = <0>;
+ };
+};
+
+&tcb0 {
+ timer0: timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer1: timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+};
+
+&trng {
+ status = "okay";
+};
+
+&vddout25 {
+ vin-supply = <&vdd_3v3>;
+ status = "okay";
+};
regulator-state-standby {
regulator-on-in-suspend;
- regulator-suspend-voltage = <1150000>;
+ regulator-suspend-microvolt = <1150000>;
regulator-mode = <4>;
};
regulator-state-standby {
regulator-on-in-suspend;
- regulator-suspend-voltage = <1050000>;
+ regulator-suspend-microvolt = <1050000>;
regulator-mode = <4>;
};
regulator-always-on;
regulator-state-standby {
- regulator-suspend-voltage = <1800000>;
+ regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend;
};
regulator-max-microvolt = <3700000>;
regulator-state-standby {
- regulator-suspend-voltage = <1800000>;
+ regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend;
};
};
&usart3 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
status = "okay";
pinctrl-0 = <&pinctrl_usart3
};
&dbgu {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
status = "okay";
};
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(8))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(9))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(8))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(9))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(8))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(9))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(10))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(11))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(10))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(11))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(10))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(11))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(22))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(23))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(22))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(23))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(24))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(25))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(24))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(25))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(12))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(13))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(12))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(13))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(14))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(15))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(14))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(15))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(16))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(17))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(16))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(17))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(0))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(1))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(0))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(1))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(0))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(1))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(2))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(3))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(2))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(3))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(2))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(3))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(4))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(5))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(4))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(5))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(4))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(5))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(6))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(7))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(6))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(7))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(6))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(7))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(18))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(19))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(18))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(19))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(20))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(21))>;
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(20))>,
- <&dma0
+ <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(21))>;
};
flx0: flexcom@e1818000 {
- compatible = "atmel,sama5d2-flexcom";
+ compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe1818000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
#address-cells = <1>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
clock-names = "usart";
dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>,
- <&dma1 AT91_XDMAC_DT_PERID(5)>;
+ <&dma1 AT91_XDMAC_DT_PERID(5)>;
dma-names = "tx", "rx";
atmel,use-dma-rx;
atmel,use-dma-tx;
};
flx1: flexcom@e181c000 {
- compatible = "atmel,sama5d2-flexcom";
+ compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe181c000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
#address-cells = <1>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>,
- <&dma0 AT91_XDMAC_DT_PERID(7)>;
+ <&dma0 AT91_XDMAC_DT_PERID(7)>;
dma-names = "tx", "rx";
status = "disabled";
};
};
flx3: flexcom@e1824000 {
- compatible = "atmel,sama5d2-flexcom";
+ compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe1824000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
#address-cells = <1>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
clock-names = "usart";
dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>,
- <&dma1 AT91_XDMAC_DT_PERID(11)>;
+ <&dma1 AT91_XDMAC_DT_PERID(11)>;
dma-names = "tx", "rx";
atmel,use-dma-rx;
atmel,use-dma-tx;
};
flx4: flexcom@e2018000 {
- compatible = "atmel,sama5d2-flexcom";
+ compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe2018000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
#address-cells = <1>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
clock-names = "usart";
dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>,
- <&dma1 AT91_XDMAC_DT_PERID(13)>;
+ <&dma1 AT91_XDMAC_DT_PERID(13)>;
dma-names = "tx", "rx";
atmel,use-dma-rx;
atmel,use-dma-tx;
};
flx7: flexcom@e2024000 {
- compatible = "atmel,sama5d2-flexcom";
+ compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe2024000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
#address-cells = <1>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
clock-names = "usart";
dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,
- <&dma1 AT91_XDMAC_DT_PERID(19)>;
+ <&dma1 AT91_XDMAC_DT_PERID(19)>;
dma-names = "tx", "rx";
atmel,use-dma-rx;
atmel,use-dma-tx;
};
flx8: flexcom@e2818000 {
- compatible = "atmel,sama5d2-flexcom";
+ compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe2818000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
#address-cells = <1>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>,
- <&dma0 AT91_XDMAC_DT_PERID(21)>;
+ <&dma0 AT91_XDMAC_DT_PERID(21)>;
dma-names = "tx", "rx";
status = "disabled";
};
};
flx9: flexcom@e281c000 {
- compatible = "atmel,sama5d2-flexcom";
+ compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe281c000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
#address-cells = <1>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>,
- <&dma0 AT91_XDMAC_DT_PERID(23)>;
+ <&dma0 AT91_XDMAC_DT_PERID(23)>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ flx10: flexcom@e2820000 {
+ compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
+ reg = <0xe2820000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe2820000 0x800>;
+ status = "disabled";
+
+ i2c10: i2c@600 {
+ compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
+ atmel,fifo-size = <32>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>,
+ <&dma0 AT91_XDMAC_DT_PERID(25)>;
dma-names = "tx", "rx";
status = "disabled";
};
};
flx11: flexcom@e2824000 {
- compatible = "atmel,sama5d2-flexcom";
+ compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe2824000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
#address-cells = <1>;
#size-cells = <0>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>,
- <&dma0 AT91_XDMAC_DT_PERID(27)>;
+ <&dma0 AT91_XDMAC_DT_PERID(27)>;
dma-names = "tx", "rx";
status = "disabled";
};
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
reg = <0>;
+ wakeup-source;
google,cros-ec-spi-msg-delay = <2000>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
reg = <0>;
+ wakeup-source;
google,cros-ec-spi-msg-delay = <2000>;
reg = <0x1c>;
realtek,dmic1-data-pin = <1>;
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+ clock-names = "mclk";
};
nct72: temperature-sensor@4c {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-lg-x3.dtsi"
+
+/ {
+ model = "LG Optimus 4X HD P880";
+ compatible = "lg,p880", "nvidia,tegra30";
+
+ aliases {
+ mmc1 = &sdmmc3; /* uSD slot */
+ mmc2 = &sdmmc1; /* WiFi */
+ };
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* WLAN SDIO pinmux */
+ host-wlan-wake {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GNSS UART-B pinmux */
+ uartb-rxd {
+ nvidia,pins = "uart2_rxd_pc3";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartb-txd {
+ nvidia,pins = "uart2_txd_pc2";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gps-reset {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* MicroSD pinmux */
+ sdmmc3-clk {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3-data {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ microsd-detect {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO keys pinmux */
+ volume-up {
+ nvidia,pins = "ulpi_data6_po7";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Sensors pinmux */
+ current-alert-irq {
+ nvidia,pins = "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* AUDIO pinmux */
+ sub-mic-ldo {
+ nvidia,pins = "gmi_cs7_n_pi6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
+
+ i2c@7000c400 {
+ touchscreen@20 {
+ rmi4-f11@11 {
+ syna,clip-x-high = <1110>;
+ syna,clip-y-high = <1973>;
+
+ touchscreen-inverted-y;
+ };
+ };
+ };
+
+ memory-controller@7000f000 {
+ emc-timings-0 {
+ /* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */
+ nvidia,ram-code = <0>;
+
+ timing-12750000 {
+ clock-frequency = <12750000>;
+
+ nvidia,emem-configuration = < 0x00050001 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x77230303 0x001f0000 >;
+ };
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00020001 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x73e30303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010001 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x72c30303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000001 0xc0000018
+ 0x00000001 0x00000001 0x00000003 0x00000001
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060403 0x72430504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000025
+ 0x00000001 0x00000001 0x00000006 0x00000003
+ 0x00000005 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000003 0x00000002
+ 0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
+ };
+
+ timing-266500000 {
+ clock-frequency = <266500000>;
+
+ nvidia,emem-configuration = < 0x00000004 0xC0000030
+ 0x00000001 0x00000002 0x00000008 0x00000004
+ 0x00000006 0x00000001 0x00000002 0x00000005
+ 0x00000001 0x00000000 0x00000003 0x00000003
+ 0x03030001 0x00090608 0x70040c09 0x001f0000 >;
+ };
+
+ timing-533000000 {
+ clock-frequency = <533000000>;
+
+ nvidia,emem-configuration = < 0x00000008 0xC0000060
+ 0x00000003 0x00000004 0x00000010 0x0000000a
+ 0x0000000d 0x00000002 0x00000002 0x00000008
+ 0x00000002 0x00000000 0x00000004 0x00000005
+ 0x05040002 0x00110b10 0x70281811 0x001f0000 >;
+ };
+ };
+ };
+
+ memory-controller@7000f400 {
+ emc-timings-0 {
+ /* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */
+ nvidia,ram-code = <0>;
+
+ timing-12750000 {
+ clock-frequency = <12750000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000000
+ 0x00000001 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x0000002f 0x00000000 0x0000000b
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000002 0x00000002
+ 0x00000003 0x00000008 0x00000004 0x00000001
+ 0x00000002 0x00000036 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000009 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000164 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000003 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x00000060 0x00000000 0x00000018
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000004 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000001
+ 0x00000002 0x0000006b 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000000a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000003
+ 0x00000006 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x000000c0 0x00000000 0x00000030
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000008 0x00000008
+ 0x00000003 0x00000008 0x00000004 0x00000001
+ 0x00000002 0x000000d5 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000013 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x0000000a>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000006
+ 0x0000000d 0x00000004 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x00000181 0x00000000 0x00000060
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x0000000f 0x0000000f
+ 0x00000003 0x00000008 0x00000004 0x00000001
+ 0x00000002 0x000001a9 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000025 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010042>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000013>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000c
+ 0x0000001a 0x00000008 0x00000003 0x00000005
+ 0x00000004 0x00000001 0x00000006 0x00000003
+ 0x00000003 0x00000002 0x00000002 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000c
+ 0x0000000a 0x00000303 0x00000000 0x000000c0
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000007 0x0000001d 0x0000001d
+ 0x00000004 0x0000000b 0x00000005 0x00000001
+ 0x00000002 0x00000351 0x00000004 0x00000006
+ 0x00000000 0x00000000 0x00004282 0x004400a4
+ 0x00008000 0x00070000 0x00070000 0x00070000
+ 0x00070000 0x00070000 0x00070000 0x00070000
+ 0x00070000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000e0220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000004a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-266500000 {
+ clock-frequency = <266500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010042>;
+ nvidia,emc-mode-2 = <0x00020002>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000018>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000f
+ 0x00000022 0x0000000b 0x00000004 0x00000005
+ 0x00000005 0x00000001 0x00000007 0x00000004
+ 0x00000004 0x00000002 0x00000002 0x00000000
+ 0x00000002 0x00000005 0x00000002 0x0000000c
+ 0x0000000b 0x000003ef 0x00000000 0x000000fb
+ 0x00000001 0x00000001 0x00000004 0x00000000
+ 0x00000001 0x00000009 0x00000026 0x00000026
+ 0x00000004 0x0000000e 0x00000006 0x00000001
+ 0x00000002 0x00000455 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00006282 0x003200a4
+ 0x00008000 0x00050000 0x00050000 0x00050000
+ 0x00050000 0x00050000 0x00050000 0x00050000
+ 0x00050000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00060000 0x00060000 0x00060000
+ 0x00060000 0x000b0220 0x0800003d 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000060 0x000a000a 0xa0f10000 0x00000000
+ 0x00000000 0x800008ee 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-533000000 {
+ clock-frequency = <533000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x000100c2>;
+ nvidia,emc-mode-2 = <0x00020006>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000030>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000001f
+ 0x00000045 0x00000016 0x00000009 0x00000008
+ 0x00000009 0x00000003 0x0000000d 0x00000009
+ 0x00000009 0x00000005 0x00000003 0x00000000
+ 0x00000004 0x00000009 0x00000006 0x0000000d
+ 0x00000010 0x000007df 0x00000000 0x000001f7
+ 0x00000003 0x00000003 0x00000009 0x00000000
+ 0x00000001 0x0000000f 0x0000004b 0x0000004b
+ 0x00000008 0x0000001b 0x0000000c 0x00000001
+ 0x00000002 0x000008aa 0x00000000 0x00000006
+ 0x00000000 0x00000000 0x00006282 0xf0120091
+ 0x00008000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00090220 0x0800003d 0x00000000
+ 0x77ffc004 0x01f1f408 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x000000c0 0x000e000e 0xa0f10000 0x00000000
+ 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >;
+ };
+ };
+ };
+
+ sdmmc3: mmc@78000400 {
+ status = "okay";
+
+ cd-gpios = <&gpio TEGRA_GPIO(W, 5) GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+
+ vmmc-supply = <&vdd_usd>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ battery: battery-cell {
+ compatible = "simple-battery";
+ device-chemistry = "lithium-ion";
+ charge-full-design-microamp-hours = <2150000>;
+ energy-full-design-microwatt-hours = <8200000>;
+ operating-range-celsius = <0 45>;
+ };
+
+ gpio-keys {
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(O, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ sound {
+ compatible = "lg,tegra-audio-max98089-p880",
+ "nvidia,tegra-audio-max98089";
+ nvidia,model = "LG Optimus 4X HD MAX98089";
+
+ nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-lg-x3.dtsi"
+
+/ {
+ model = "LG Optimus Vu P895";
+ compatible = "lg,p895", "nvidia,tegra30";
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* GNSS UART-B pinmux */
+ uartb-cts-rxd {
+ nvidia,pins = "uart2_cts_n_pj5",
+ "uart2_rxd_pc3";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartb-rts-txd {
+ nvidia,pins = "uart2_rts_n_pj6",
+ "uart2_txd_pc2";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gps-reset {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* GPIO keys pinmux */
+ memo-key {
+ nvidia,pins = "sdmmc3_dat1_pb6";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ volume-up {
+ nvidia,pins = "gmi_cs7_n_pi6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Sensors pinmux */
+ current-alert-irq {
+ nvidia,pins = "spi1_cs0_n_px6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Panel pinmux */
+ panel-vdd {
+ nvidia,pins = "pbb0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* AUDIO pinmux */
+ sub-mic-ldo {
+ nvidia,pins = "gmi_dqs_pi2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Modem pinmux */
+ usim-detect {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive-sdmmc4 {
+ nvidia,pins = "drive_gma",
+ "drive_gmb",
+ "drive_gmc",
+ "drive_gmd";
+ nvidia,pull-down-strength = <9>;
+ nvidia,pull-up-strength = <9>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ };
+ };
+
+ i2c@7000c400 {
+ touchscreen@20 {
+ rmi4-f11@11 {
+ syna,clip-x-high = <1535>;
+ syna,clip-y-high = <2047>;
+ };
+ };
+ };
+
+ memory-controller@7000f000 {
+ emc-timings-2 {
+ /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */
+ nvidia,ram-code = <2>;
+
+ timing-12750000 {
+ clock-frequency = <12750000>;
+
+ nvidia,emem-configuration = < 0x00020001 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x77230303 0x001f0000 >;
+ };
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = < 0x00030003 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x73e30303 0x001f0000 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = < 0x00010003 0xc0000010
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060402 0x72c30303 0x001f0000 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = < 0x00000003 0xc0000018
+ 0x00000001 0x00000001 0x00000003 0x00000001
+ 0x00000003 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000002 0x00000002
+ 0x02020001 0x00060403 0x72430504 0x001f0000 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = < 0x00000006 0xc0000025
+ 0x00000001 0x00000001 0x00000006 0x00000003
+ 0x00000005 0x00000001 0x00000002 0x00000004
+ 0x00000001 0x00000000 0x00000003 0x00000002
+ 0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
+ };
+
+ timing-266500000 {
+ clock-frequency = <266500000>;
+
+ nvidia,emem-configuration = < 0x00000008 0xc0000030
+ 0x00000001 0x00000002 0x00000008 0x00000004
+ 0x00000006 0x00000001 0x00000002 0x00000005
+ 0x00000001 0x00000000 0x00000003 0x00000003
+ 0x03030001 0x00090608 0x70040c09 0x001f0000 >;
+ };
+
+ timing-533000000 {
+ clock-frequency = <533000000>;
+
+ nvidia,emem-configuration = < 0x0000000f 0xc0000060
+ 0x00000003 0x00000004 0x00000010 0x0000000a
+ 0x0000000d 0x00000002 0x00000002 0x00000008
+ 0x00000002 0x00000000 0x00000004 0x00000005
+ 0x05040002 0x00110b10 0x70281811 0x001f0000 >;
+ };
+ };
+ };
+
+ memory-controller@7000f400 {
+ emc-timings-2 {
+ /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */
+ nvidia,ram-code = <2>;
+
+ timing-12750000 {
+ clock-frequency = <12750000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000000
+ 0x00000001 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x0000002f 0x00000000 0x0000000b
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000002 0x00000002
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x00000036 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000009 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000164 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000001
+ 0x00000003 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x00000060 0x00000000 0x00000018
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000004 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x0000006b 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000000a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x800001c5 0xd0000000 0xff00ff00 >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000009>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000003
+ 0x00000006 0x00000002 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x000000c0 0x00000000 0x00000030
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x00000008 0x00000008
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000000d5 0x00000004 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000013 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000287 0xd0000000 0xff00ff00 >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010022>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x0000000a>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x00000006
+ 0x0000000d 0x00000004 0x00000002 0x00000004
+ 0x00000004 0x00000001 0x00000005 0x00000002
+ 0x00000002 0x00000001 0x00000001 0x00000000
+ 0x00000001 0x00000003 0x00000001 0x0000000b
+ 0x00000009 0x00000181 0x00000000 0x00000060
+ 0x00000001 0x00000001 0x00000002 0x00000000
+ 0x00000001 0x00000007 0x0000000f 0x0000000f
+ 0x00000003 0x00000008 0x00000004 0x00000004
+ 0x00000002 0x000001a9 0x00000004 0x00000006
+ 0x00000000 0x00000000 0x00004282 0x007800a4
+ 0x00008000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000fc000 0x000fc000 0x000fc000
+ 0x000fc000 0x00100220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000025 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x8000040b 0xd0000000 0xff00ff00 >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010042>;
+ nvidia,emc-mode-2 = <0x00020001>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000013>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000c
+ 0x0000001a 0x00000008 0x00000003 0x00000005
+ 0x00000004 0x00000001 0x00000006 0x00000003
+ 0x00000003 0x00000002 0x00000002 0x00000000
+ 0x00000001 0x00000004 0x00000001 0x0000000c
+ 0x0000000a 0x00000303 0x00000000 0x000000c0
+ 0x00000001 0x00000001 0x00000003 0x00000000
+ 0x00000001 0x00000007 0x0000001d 0x0000001d
+ 0x00000004 0x0000000b 0x00000005 0x00000004
+ 0x00000002 0x00000351 0x00000005 0x00000004
+ 0x00000000 0x00000000 0x00004282 0x004400a4
+ 0x00008000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x00072000 0x00072000 0x00072000
+ 0x00072000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080000 0x00080000 0x00080000
+ 0x00080000 0x000e0220 0x0800201c 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x0000004a 0x00090009 0xa0f10000 0x00000000
+ 0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-266500000 {
+ clock-frequency = <266500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x00010042>;
+ nvidia,emc-mode-2 = <0x00020002>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000018>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000000f
+ 0x00000022 0x0000000b 0x00000004 0x00000005
+ 0x00000005 0x00000001 0x00000007 0x00000004
+ 0x00000004 0x00000002 0x00000002 0x00000000
+ 0x00000002 0x00000005 0x00000002 0x0000000c
+ 0x0000000b 0x000003ef 0x00000000 0x000000fb
+ 0x00000001 0x00000001 0x00000004 0x00000000
+ 0x00000001 0x00000009 0x00000026 0x00000026
+ 0x00000004 0x0000000e 0x00000006 0x00000004
+ 0x00000002 0x00000455 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00006282 0x003200a4
+ 0x00008000 0x00070000 0x00070000 0x00070000
+ 0x00070000 0x00072000 0x00072000 0x00072000
+ 0x00072000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00080002 0x00080002 0x00080002
+ 0x00080002 0x000e0220 0x0800003d 0x00000000
+ 0x77ffc004 0x01f1f008 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x00000060 0x000a000a 0xa0f10000 0x00000000
+ 0x00000000 0x800008ee 0xe0000000 0xff00ff00 >;
+ };
+
+ timing-533000000 {
+ clock-frequency = <533000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x000100c2>;
+ nvidia,emc-mode-2 = <0x00020006>;
+ nvidia,emc-mode-reset = <0x00000000>;
+ nvidia,emc-zcal-cnt-long = <0x00000030>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = < 0x0000001f
+ 0x00000045 0x00000016 0x00000009 0x00000008
+ 0x00000009 0x00000003 0x0000000d 0x00000009
+ 0x00000009 0x00000005 0x00000003 0x00000000
+ 0x00000004 0x0000000a 0x00000006 0x0000000d
+ 0x00000010 0x000007df 0x00000000 0x000001f7
+ 0x00000003 0x00000003 0x00000009 0x00000000
+ 0x00000001 0x0000000f 0x0000004b 0x0000004b
+ 0x00000008 0x0000001b 0x0000000c 0x00000004
+ 0x00000002 0x000008aa 0x00000000 0x00000004
+ 0x00000000 0x00000000 0x00006282 0xf0120091
+ 0x00008000 0x0000000c 0x0000000c 0x0000000c
+ 0x0000000c 0x0000000a 0x0000000a 0x0000000a
+ 0x0000000a 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x0000000c 0x0000000c 0x0000000c
+ 0x0000000c 0x000c0220 0x0800003d 0x00000000
+ 0x77ffc004 0x01f1f408 0x00000000 0x00000007
+ 0x08000068 0x08000000 0x00000802 0x00064000
+ 0x000000c0 0x000e000e 0xa0f10000 0x00000000
+ 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >;
+ };
+ };
+ };
+
+ battery: battery-cell {
+ compatible = "simple-battery";
+ device-chemistry = "lithium-ion";
+ charge-full-design-microamp-hours = <2080000>;
+ energy-full-design-microwatt-hours = <7700000>;
+ operating-range-celsius = <0 45>;
+ };
+
+ gpio-keys {
+ key-memo {
+ label = "Memo";
+ gpios = <&gpio TEGRA_GPIO(B, 6) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_MEMO>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ gpio-leds {
+ led-power {
+ label = "power::white";
+ gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
+
+ linux,default-trigger = "battery-charging";
+
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_CHARGING;
+ };
+ };
+
+ regulator-lcd3v {
+ gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "lg,tegra-audio-max98089-p895",
+ "nvidia,tegra-audio-max98089";
+ nvidia,model = "LG Optimus Vu MAX98089";
+
+ nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/mfd/max77620.h>
+#include <dt-bindings/thermal/thermal.h>
+
+#include "tegra30.dtsi"
+#include "tegra30-cpu-opp.dtsi"
+#include "tegra30-cpu-opp-microvolt.dtsi"
+
+/ {
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc1; /* WiFi */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ serial0 = &uartd; /* Console */
+ serial1 = &uartc; /* Bluetooth */
+ serial2 = &uartb; /* GPS */
+ };
+
+ /*
+ * The decompressor and also some bootloaders rely on a
+ * pre-existing /chosen node to be available to insert the
+ * command line and merge other ATAGS info.
+ */
+ chosen { };
+
+ firmware {
+ trusted-foundations {
+ compatible = "tlm,trusted-foundations";
+ tlm,version-major = <2>;
+ tlm,version-minor = <8>;
+ };
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,cma@80000000 {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x80000000 0x30000000>;
+ size = <0x10000000>; /* 256MiB */
+ linux,cma-default;
+ reusable;
+ };
+
+ ramoops@bed00000 {
+ compatible = "ramoops";
+ reg = <0xbed00000 0x10000>; /* 64kB */
+ console-size = <0x8000>; /* 32kB */
+ record-size = <0x400>; /* 1kB */
+ ecc-size = <16>;
+ };
+
+ trustzone@bfe00000 {
+ reg = <0xbfe00000 0x200000>; /* 2MB */
+ no-map;
+ };
+ };
+
+ vde@6001a000 {
+ assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
+ assigned-clock-rates = <408000000>;
+ };
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* WLAN SDIO pinmux */
+ sdmmc1-clk {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1-cmd {
+ nvidia,pins = "sdmmc1_cmd_pz1",
+ "sdmmc1_dat3_py4",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat0_py7";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ wlan-reset {
+ nvidia,pins = "pv3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ wlan-host-wake {
+ nvidia,pins = "pu6";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GNSS UART-B pinmux */
+ gps-pwr-en {
+ nvidia,pins = "kb_row6_pr6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gps-ldo-en {
+ nvidia,pins = "ulpi_dir_py1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gps-clk-ref {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Bluetooth UART-C pinmux */
+ uartc-cts-rxd {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uartc-rts-txd {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt-reset {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt-dev-wake {
+ nvidia,pins = "kb_row11_ps3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bt-host-wake {
+ nvidia,pins = "kb_row12_ps4";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ bt-pcm-dap4 {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* EMMC pinmux */
+ sdmmc4-clk {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4-data {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4-reset {
+ nvidia,pins = "sdmmc4_rst_n_pcc3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* I2C pinmux */
+ gen1-i2c {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+ gen2-i2c {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+ cam-i2c {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+ ddc-i2c {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+ pwr-i2c {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ };
+ mhl-i2c {
+ nvidia,pins = "kb_col6_pq6",
+ "kb_col7_pq7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO keys pinmux */
+ power-key {
+ nvidia,pins = "gmi_wp_n_pc7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ volume-down {
+ nvidia,pins = "ulpi_data3_po4";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Sensors pinmux */
+ sen-vdd {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ proxi-vdd {
+ nvidia,pins = "spi2_miso_px1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sen-vio {
+ nvidia,pins = "lcd_dc1_pd2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ nct-irq {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ bat-irq {
+ nvidia,pins = "kb_row8_ps0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ charger-irq {
+ nvidia,pins = "gmi_cs1_n_pj2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mpu-irq {
+ nvidia,pins = "gmi_ad12_ph4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ compass-irq {
+ nvidia,pins = "gmi_ad13_ph5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ light-irq {
+ nvidia,pins = "gmi_cs4_n_pk2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* LED pinmux */
+ backlight-en {
+ nvidia,pins = "lcd_dc0_pn6";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ flash-led-en {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ keypad-led {
+ nvidia,pins = "kb_row2_pr2",
+ "kb_row3_pr3";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* NFC pinmux */
+ nfc-irq {
+ nvidia,pins = "spi2_cs1_n_pw2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ nfc-ven {
+ nvidia,pins = "spi1_sck_px5";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ nfc-firm {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* DC pinmux */
+ lcd-pwr {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pwr1_pc1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd-wr-n {
+ nvidia,pins = "lcd_wr_n_pz3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd-id {
+ nvidia,pins = "lcd_m1_pw1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd-pclk {
+ nvidia,pins = "lcd_pclk_pb3",
+ "lcd_de_pj1",
+ "lcd_hsync_pj3",
+ "lcd_vsync_pj4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd-rgb-blue {
+ nvidia,pins = "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd-rgb-green {
+ nvidia,pins = "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd-rgb-red {
+ nvidia,pins = "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Bridge pinmux */
+ bridge-reset {
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ rgb-ic-en {
+ nvidia,pins = "gmi_a18_pb1";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ bridge-clk {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ rgb-bridge {
+ nvidia,pins = "lcd_sdin_pz2",
+ "lcd_sdout_pn5",
+ "lcd_cs0_n_pn4",
+ "lcd_sck_pz4";
+ nvidia,function = "spi5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Panel pinmux */
+ panel-reset {
+ nvidia,pins = "lcd_cs1_n_pw0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ panel-vio {
+ nvidia,pins = "ulpi_clk_py0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Touchscreen pinmux */
+ touch-vdd {
+ nvidia,pins = "kb_col1_pq1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ touch-vio {
+ nvidia,pins = "spi1_mosi_px4";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ touch-irq-n {
+ nvidia,pins = "kb_col3_pq3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ touch-rst-n {
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ touch-maker-id {
+ nvidia,pins = "kb_col2_pq2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MHL pinmux */
+ mhl-vio {
+ nvidia,pins = "pv2";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ mhl-rst-n {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ mhl-irq {
+ nvidia,pins = "crt_vsync_pv7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ mhl-sel {
+ nvidia,pins = "kb_row10_ps2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ hdmi-hpd {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* AUDIO pinmux */
+ hp-detect {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ hp-hook {
+ nvidia,pins = "ulpi_data4_po5";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ear-mic-en {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ audio-irq {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ audio-mclk {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap-i2s0 {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap-i2s1 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MUIC pinmux */
+ muic-irq {
+ nvidia,pins = "gmi_cs0_n_pj0";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ muic-dp2t {
+ nvidia,pins = "pcc2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ muic-usif {
+ nvidia,pins = "ulpi_stp_py3";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ifx-usb-vbus-en {
+ nvidia,pins = "kb_row4_pr4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcb-rev {
+ nvidia,pins = "gmi_wait_pi7",
+ "gmi_rst_n_pi4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ jtag-rtck {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Camera pinmux */
+ cam-mclk {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam-pmic-en {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ front-cam-rst {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ front-cam-vio {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ rear-cam-rst {
+ nvidia,pins = "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ rear-cam-eprom-pr {
+ nvidia,pins = "gmi_cs2_n_pk3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ rear-cam-vcm-pwdn {
+ nvidia,pins = "kb_row1_pr1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Haptic pinmux */
+ haptic-en {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ haptic-osc {
+ nvidia,pins = "gmi_ad11_ph3";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Modem pinmux */
+ cp2ap-ack1-host-active {
+ nvidia,pins = "pu5";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ cp2ap-ack2-host-wakeup {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ap2cp-ack2-suspend-req {
+ nvidia,pins = "kb_row14_ps6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ap2cp-ack1-slave-wakeup {
+ nvidia,pins = "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ cp-kkp {
+ nvidia,pins = "kb_col0_pq0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cp-crash-irq {
+ nvidia,pins = "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ap2cp-uarta-tx-ipc {
+ nvidia,pins = "pu0";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ap2cp-uarta-rx-ipc {
+ nvidia,pins = "pu1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ fota-ap-cts-cp-rts {
+ nvidia,pins = "pu2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ fota-ap-rts-cp-cts {
+ nvidia,pins = "pu3";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ modem-enable {
+ nvidia,pins = "ulpi_data7_po0";
+ nvidia,function = "hsi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ modem-reset {
+ nvidia,pins = "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap-i2s2 {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_din_pp1",
+ "dap3_dout_pp2",
+ "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* GPIO power/drive control */
+ drive-i2c {
+ nvidia,pins = "drive_dbg",
+ "drive_at5",
+ "drive_gme",
+ "drive_ddc",
+ "drive_ao1";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+
+ drive-uart3 {
+ nvidia,pins = "drive_uart3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+
+ drive-gmi {
+ nvidia,pins = "drive_at3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ };
+ };
+
+ uartb: serial@70006040 {
+ compatible = "nvidia,tegra30-hsuart";
+ reset-names = "serial";
+ /delete-property/ reg-shift;
+ status = "okay";
+
+ /* GNSS GSD5T */
+ };
+
+ uartc: serial@70006200 {
+ compatible = "nvidia,tegra30-hsuart";
+ reset-names = "serial";
+ /delete-property/ reg-shift;
+ status = "okay";
+
+ nvidia,adjust-baud-rates = <0 9600 100>,
+ <9600 115200 200>,
+ <1000000 4000000 136>;
+
+ /* BCM4330B1 37.4 MHz Class 1.5 ExtLNA */
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ max-speed = <4000000>;
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "txco";
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(S, 4) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "host-wakeup";
+
+ device-wakeup-gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
+
+ vbat-supply = <&vdd_3v3_vbat>;
+ vddio-supply = <&vdd_1v8_vio>;
+ };
+ };
+
+ uartd: serial@70006300 {
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+ status = "okay";
+
+ /* Console */
+ };
+
+ pwm@7000a000 {
+ status = "okay";
+ };
+
+ gen1_i2c: i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Aichi AMI306 digital compass */
+ magnetometer@e {
+ compatible = "asahi-kasei,ak8974";
+ reg = <0x0e>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(H, 5) IRQ_TYPE_EDGE_RISING>;
+
+ avdd-supply = <&vdd_3v0_sen>;
+ dvdd-supply = <&vdd_1v8_vio>;
+
+ mount-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "-1";
+ };
+
+ max98089: audio-codec@10 {
+ compatible = "maxim,max98089";
+ reg = <0x10>;
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+ clock-names = "mclk";
+
+ assigned-clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_EXTERN1>;
+ };
+
+ nfc@28 {
+ compatible = "nxp,pn544-i2c";
+ reg = <0x28>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>;
+
+ enable-gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+ };
+
+ imu@68 {
+ compatible = "invensense,mpu6050";
+ reg = <0x68>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&vdd_3v0_sen>;
+ vddio-supply = <&vdd_1v8_sen>;
+
+ mount-matrix = "1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "-1";
+ };
+ };
+
+ gen2_i2c: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Synaptics RMI4 S3203B touchcreen */
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&vdd_3v0_touch>;
+ vio-supply = <&vdd_1v8_touch>;
+
+ syna,reset-delay-ms = <20>;
+ syna,startup-delay-ms = <200>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f11@11 {
+ reg = <0x11>;
+ syna,sensor-type = <1>;
+
+ syna,clip-x-low = <0>;
+ syna,clip-y-low = <0>;
+ };
+ };
+ };
+
+ cam_i2c: i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ dw9714: coil@c {
+ compatible = "dongwoon,dw9714";
+ reg = <0x0c>;
+
+ enable-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>;
+
+ vcc-supply = <&vcc_focuser>;
+ };
+
+ camera-pmic@7d {
+ compatible = "ti,lp8720";
+ reg = <0x7d>;
+
+ enable-gpios = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
+
+ vt_1v2_front: ldo1 {
+ regulator-name = "vt_1v2_dig";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vt_2v7_front: ldo2 {
+ regulator-name = "vt_2v7_vana";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ vdd_2v7_rear: ldo3 {
+ regulator-name = "8m_2v7_vana";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ vio_1v8_rear: ldo4 {
+ regulator-name = "vio_1v8_cam";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_focuser: ldo5 {
+ regulator-name = "8m_2v8_vcm";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ vdd_1v2_rear: buck {
+ regulator-name = "8m_1v2_cam";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ };
+ };
+
+ hdmi_ddc: i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: max77663@1c {
+ compatible = "maxim,max77663";
+ reg = <0x1c>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ system-power-controller;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&max77663_default>;
+
+ max77663_default: pinmux {
+ gpio1 {
+ pins = "gpio1";
+ function = "gpio";
+ drive-open-drain = <1>;
+ };
+
+ gpio4 {
+ pins = "gpio4";
+ function = "32k-out1";
+ };
+ };
+
+ fps {
+ fps0 {
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+ };
+
+ fps1 {
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
+ };
+
+ fps2 {
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+ };
+ };
+
+ regulators {
+ in-sd0-supply = <&vdd_5v0_vbus>;
+ in-sd1-supply = <&vdd_5v0_vbus>;
+ in-sd2-supply = <&vdd_5v0_vbus>;
+ in-sd3-supply = <&vdd_5v0_vbus>;
+
+ in-ldo0-1-supply = <&vdd_1v8_vio>;
+ in-ldo2-supply = <&vdd_3v3_vbat>;
+ in-ldo3-5-supply = <&vdd_3v3_vbat>;
+ in-ldo4-6-supply = <&vdd_3v3_vbat>;
+ in-ldo7-8-supply = <&vdd_1v8_vio>;
+
+ vdd_cpu: sd0 {
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-coupled-with = <&vdd_core>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ nvidia,tegra-cpu-regulator;
+ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+ };
+
+ vdd_core: sd1 {
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-coupled-with = <&vdd_cpu>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ nvidia,tegra-core-regulator;
+ maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+ };
+
+ vdd_1v8_vio: sd2 {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+ };
+
+ sd3 {
+ regulator-name = "vddio_ddr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+ };
+
+ ldo0 {
+ regulator-name = "avdd_pll";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
+ };
+
+ ldo1 {
+ regulator-name = "vdd_ddr_hs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+ };
+
+ avdd_3v3_periph: ldo2 {
+ regulator-name = "avdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+ };
+
+ vdd_usd: ldo3 {
+ regulator-name = "vdd_sdmmc3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+
+ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+ };
+
+ ldo4 {
+ regulator-name = "vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+ };
+
+ vcore_emmc: ldo5 {
+ regulator-name = "vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
+ };
+
+ avdd_1v8_hdmi_pll: ldo6 {
+ regulator-name = "avdd_osc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+ };
+
+ vdd_1v2_mhl: ldo7 {
+ regulator-name = "vdd_1v2_mhl";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1250000>;
+
+ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+ };
+
+ ldo8 {
+ regulator-name = "avdd_dsi_csi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
+ };
+ };
+ };
+
+ fuel-gauge@36 {
+ compatible = "maxim,max17043";
+ reg = <0x36>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_FALLING>;
+
+ monitored-battery = <&battery>;
+
+ maxim,alert-low-soc-level = <10>;
+ wakeup-source;
+ };
+
+ power-sensor@40 {
+ compatible = "ti,ina230";
+ reg = <0x40>;
+
+ vs-supply = <&vdd_3v0_sen>;
+ };
+
+ nct72: temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(I, 5) IRQ_TYPE_EDGE_FALLING>;
+
+ vcc-supply = <&vdd_3v0_sen>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ i2c-mhl {
+ compatible = "i2c-gpio";
+
+ sda-gpios = <&gpio TEGRA_GPIO(Q, 7) (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio TEGRA_GPIO(Q, 6) (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ i2c-gpio,delay-us = <5>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi@7000dc00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ /* DSI bridge */
+ };
+
+ pmc@7000e400 {
+ status = "okay";
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <2>;
+ nvidia,cpu-pwr-good-time = <2000>;
+ nvidia,cpu-pwr-off-time = <200>;
+ nvidia,core-pwr-good-time = <3845 3845>;
+ nvidia,core-pwr-off-time = <0>;
+ nvidia,core-power-req-active-high;
+ nvidia,sys-clock-req-active-high;
+ core-supply = <&vdd_core>;
+
+ i2c-thermtrip {
+ nvidia,i2c-controller-id = <4>;
+ nvidia,bus-addr = <0x1c>;
+ nvidia,reg-addr = <0x41>;
+ nvidia,reg-data = <0x02>;
+ };
+ };
+
+ hda@70030000 {
+ status = "okay";
+ };
+
+ ahub@70080000 {
+ /* HIFI CODEC */
+ i2s@70080300 { /* i2s0 */
+ status = "okay";
+ };
+
+ /* BASEBAND */
+ i2s@70080500 { /* i2s2 */
+ status = "okay";
+ };
+
+ /* BT SCO */
+ i2s@70080600 { /* i2s3 */
+ status = "okay";
+ };
+ };
+
+ sdmmc1: mmc@78000000 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
+ assigned-clock-rates = <50000000>;
+
+ max-frequency = <50000000>;
+ keep-power-in-suspend;
+ bus-width = <4>;
+ non-removable;
+
+ mmc-pwrseq = <&brcm_wifi_pwrseq>;
+ vmmc-supply = <&vdd_3v3_vbat>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+
+ /* BCM4330B1 37.4 MHz Class 1.5 ExtLNA */
+ wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+ };
+
+ sdmmc4: mmc@78000600 {
+ status = "okay";
+ bus-width = <8>;
+
+ non-removable;
+ mmc-ddr-1_8v;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ /* Micro USB */
+ usb@7d000000 {
+ compatible = "nvidia,tegra30-udc";
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ usb-phy@7d000000 {
+ status = "okay";
+ dr_mode = "peripheral";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ vbus-supply = <&avdd_3v3_periph>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ gps_refclk: clock-gps {
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ clock-accuracy = <100>;
+ #clock-cells = <0>;
+ };
+
+ gps_osc: clock-gps-osc-gate {
+ compatible = "gpio-gate-clock";
+ enable-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
+ clocks = <&gps_refclk>;
+ #clock-cells = <0>;
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ cpu1: cpu@1 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ cpu2: cpu@2 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ cpu3: cpu@3 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(O, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led-keypad {
+ label = "keypad::white";
+ gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_KBD_BACKLIGHT;
+ };
+ };
+
+ opp-table-actmon {
+ /delete-node/ opp-625000000;
+ /delete-node/ opp-667000000;
+ /delete-node/ opp-750000000;
+ /delete-node/ opp-800000000;
+ /delete-node/ opp-900000000;
+ };
+
+ opp-table-emc {
+ /delete-node/ opp-625000000-1200;
+ /delete-node/ opp-625000000-1250;
+ /delete-node/ opp-667000000-1200;
+ /delete-node/ opp-750000000-1300;
+ /delete-node/ opp-800000000-1300;
+ /delete-node/ opp-900000000-1350;
+ };
+
+ brcm_wifi_pwrseq: pwrseq-wifi {
+ compatible = "mmc-pwrseq-simple";
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "ext_clock";
+
+ reset-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <300>;
+ power-off-delay-us = <300>;
+ };
+
+ vdd_5v0_vbus: regulator-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_3v3_vbat: regulator-vbat {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_vbat";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_5v0_vbus>;
+ };
+
+ vdd_3v0_sen: regulator-sen3v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v0_sensor";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_vbat>;
+ };
+
+ vdd_3v0_proxi: regulator-proxi {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v0_proxi";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_vbat>;
+ };
+
+ vdd_1v8_sen: regulator-sen1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v8_sensor";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_vbat>;
+ };
+
+ vcc_3v0_lcd: regulator-lcd3v {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v0_lcd";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ vin-supply = <&vdd_3v3_vbat>;
+ };
+
+ iovcc_1v8_lcd: regulator-lcd1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "iovcc_1v8_lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_vbat>;
+ };
+
+ vio_1v8_mhl: regulator-mhl1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vio_1v8_mhl";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_vbat>;
+ };
+
+ vdd_3v0_touch: regulator-touchpwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v0_touch";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_vbat>;
+ };
+
+ vdd_1v8_touch: regulator-touchvio {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v8_touch";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_vbat>;
+ };
+
+ vcc_1v8_gps: regulator-gps {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8_gps";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(Y, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_vbat>;
+ };
+
+ vio_1v8_front: regulator-frontvio {
+ compatible = "regulator-fixed";
+ regulator-name = "vt_1v8_cam_vio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio TEGRA_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_vbat>;
+ };
+
+ sound {
+ nvidia,audio-routing =
+ "Headphone Jack", "HPL",
+ "Headphone Jack", "HPR",
+ "Int Spk", "SPKL",
+ "Int Spk", "SPKR",
+ "Earpiece", "RECL",
+ "Earpiece", "RECR",
+ "INA1", "Mic Jack",
+ "MIC1", "MICBIAS",
+ "MICBIAS", "Internal Mic 1",
+ "MIC2", "Internal Mic 2";
+
+ nvidia,i2s-controller = <&tegra_i2s0>;
+ nvidia,audio-codec = <&max98089>;
+
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(BB, 6) GPIO_ACTIVE_LOW>;
+ nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_HIGH>;
+ nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>;
+ nvidia,coupled-mic-hp-det;
+
+ clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+ <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
+ };
+
+ thermal-zones {
+ /*
+ * NCT72 has two sensors:
+ *
+ * 0: internal that monitors ambient/skin temperature
+ * 1: external that is connected to the CPU's diode
+ *
+ * Ideally we should use userspace thermal governor,
+ * but it's a much more complex solution. The "skin"
+ * zone exists as a simpler solution which prevents
+ * this device from getting too hot from a user's
+ * tactile perspective. The CPU zone is intended to
+ * protect silicon from damage.
+ */
+
+ skin-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&nct72 0>;
+
+ trips {
+ trip0: skin-alert {
+ /* throttle at 50C until temperature drops to 49.8C */
+ temperature = <50000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+
+ trip1: skin-crit {
+ /* shut down at 60C */
+ temperature = <60000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&trip0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&actmon THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&nct72 1>;
+
+ trips {
+ trip2: cpu-alert {
+ /* throttle at 75C until temperature drops to 74.8C */
+ temperature = <75000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+
+ trip3: cpu-crit {
+ /* shut down at 90C */
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&trip2>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&actmon THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+};
#size-cells = <1>;
};
- eth: eth@4,c00000 {
+ eth: ethernet@4,c00000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth>;
compatible = "davicom,dm9000";
};
};
- weim: weim@220000 {
+ weim: memory-controller@220000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx1-weim";
status = "disabled";
};
- weim: weim@d8002000 {
+ weim: memory-controller@d8002000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx27-weim";
status = "disabled";
};
- weim: weim@b8002000 {
+ weim: memory-controller@b8002000 {
compatible = "fsl,imx31-weim", "fsl,imx27-weim";
reg = <0xb8002000 0x1000>;
clocks = <&clks 56>;
status = "disabled";
};
- weim: weim@b8002000 {
+ weim: memory-controller@b8002000 {
#address-cells = <2>;
#size-cells = <1>;
clocks = <&clks 0>;
reg = <0x83fd8000 0x1000>;
};
- weim: weim@83fda000 {
+ weim: memory-controller@83fda000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx51-weim";
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * DT overlay for MCIMXHDMICARD as used with the iMX53 QSB or QSRB boards
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ /delete-node/ panel;
+
+ hdmi: connector-hdmi {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&sii9022_out>;
+ };
+ };
+ };
+
+ reg_1p2v: regulator-1p2v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ vin-supply = <®_3p2v>;
+ };
+};
+
+&display0 {
+ status = "okay";
+};
+
+&display0 {
+ port@1 {
+ display0_out: endpoint {
+ remote-endpoint = <&sii9022_in>;
+ };
+ };
+};
+
+&i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sii9022: bridge-hdmi@39 {
+ compatible = "sil,sii9022";
+ reg = <0x39>;
+ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ interrupts-extended = <&gpio3 31 IRQ_TYPE_LEVEL_LOW>;
+ iovcc-supply = <®_3p2v>;
+ #sound-dai-cells = <0>;
+ sil,i2s-data-lanes = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sii9022_in: endpoint {
+ remote-endpoint = <&display0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ sii9022_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+};
+
+&tve {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Sielaff i.MX6 Solo";
+ compatible = "sielaff,imx6dl-board", "fsl,imx6dl";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ pwms = <&pwm3 0 50000 0>;
+ brightness-levels = <0 0 64 88 112 136 184 232 255>;
+ default-brightness-level = <4>;
+ enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+ power-supply = <®_backlight>;
+ };
+
+ cec {
+ compatible = "cec-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi_cec>;
+ cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ hdmi-phandle = <&hdmi>;
+ };
+
+ enet_ref: clock-enet-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "enet-ref";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ key-0 {
+ gpios = <&gpio2 16 0>;
+ debounce-interval = <10>;
+ linux,code = <1>;
+ };
+
+ key-1 {
+ gpios = <&gpio3 27 0>;
+ debounce-interval = <10>;
+ linux,code = <2>;
+ };
+
+ key-2 {
+ gpios = <&gpio5 4 0>;
+ debounce-interval = <10>;
+ linux,code = <3>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-debug {
+ label = "debug-led";
+ gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ device_type = "memory";
+ };
+
+ osc_eth_phy: clock-osc-eth-phy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "osc-eth-phy";
+ };
+
+ panel {
+ compatible = "lg,lb070wv8";
+ backlight = <&backlight>;
+ power-supply = <®_3v3>;
+
+ port {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&lvds_out>;
+ };
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_backlight: regulator-backlight {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_backlight>;
+ enable-active-high;
+ gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ regulator-name = "backlight";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
+ enable-active-high;
+ gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+&fec {
+ /*
+ * Set PTP clock to external instead of internal reference, as the
+ * REF_CLK from the PHY is fed back into the i.MX6 and the GPR
+ * register needs to be set accordingly (see mach-imx6q.c).
+ */
+ clocks = <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET>,
+ <&enet_ref>,
+ <&clks IMX6QDL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp", "enet_out";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-connection-type = "rmii";
+ phy-handle = <ðphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&osc_eth_phy>;
+ clock-names = "rmii-ref";
+ micrel,led-mode = <1>;
+ reset-assert-us = <500>;
+ reset-deassert-us = <100>;
+ reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "key-out", "key-in",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "lan9500a-rst", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c4>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ touchscreen@55 {
+ compatible = "sitronix,st1633";
+ reg = <0x55>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpio5>;
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+ };
+
+ touchscreen@5d {
+ compatible = "goodix,gt928";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch>;
+ interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio5>;
+ irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&ldb {
+ status = "okay";
+
+ lvds: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds_out: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ disable-over-current;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb1@1 {
+ compatible = "usb4b4,6570";
+ reg = <1>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+
+ assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
+ <&clks IMX6QDL_CLK_CKO2_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
+ <&clks IMX6QDL_CLK_OSC>;
+ assigned-clock-rates = <12000000 0>;
+ };
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ dr_mode = "host";
+ over-current-active-low;
+ vbus-supply = <®_usb_otg_vbus>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
+ >;
+ };
+
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
+ MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
+ MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080
+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
+ };
+
+ pinctrl_hdmi_cec: hdmicecgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_reg_backlight: regbacklightgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1
+ >;
+ };
+
+ pinctrl_reg_usbotg_vbus: regusbotgvbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1
+ >;
+ };
+
+ pinctrl_touch: touchgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
+ >;
+ };
+};
#address-cells = <1>;
#size-cells = <0>;
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
switch@10 {
compatible = "qca,qca8334";
- reg = <10>;
+ reg = <0x10>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
switch_ports: ports {
eth2: port@2 {
reg = <2>;
label = "eth2";
+ phy-mode = "internal";
phy-handle = <&phy_port2>;
};
eth1: port@3 {
reg = <3>;
label = "eth1";
+ phy-mode = "internal";
phy-handle = <&phy_port3>;
};
};
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy_port2: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy_port3: ethernet-phy@2 {
+ reg = <2>;
+ };
+ };
};
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2024 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6q-apalis-eval.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board v1.2";
+ compatible = "toradex,apalis_imx6q-eval-v1.2", "toradex,apalis_imx6q",
+ "fsl,imx6q";
+
+ reg_3v3_mmc: regulator-3v3-mmc {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_3v3_mmc>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3.3V_MMC";
+ startup-delay-us = <10000>;
+ };
+
+ reg_3v3_sd: regulator-3v3-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_3v3_sd>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3.3V_SD";
+ startup-delay-us = <10000>;
+ };
+
+ reg_can1: regulator-can1 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_can1_power>;
+ regulator-name = "5V_SW_CAN1";
+ startup-delay-us = <10000>;
+ };
+
+ reg_can2: regulator-can2 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_can2_power>;
+ regulator-name = "5V_SW_CAN2";
+ startup-delay-us = <10000>;
+ };
+
+ sound-carrier {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,name = "apalis-nau8822";
+ simple-audio-card,routing =
+ "Headphones", "LHP",
+ "Headphones", "RHP",
+ "Speaker", "LSPK",
+ "Speaker", "RSPK",
+ "Line Out", "AUXOUT1",
+ "Line Out", "AUXOUT2",
+ "LAUX", "Line In",
+ "RAUX", "Line In",
+ "LMICP", "Mic In",
+ "RMICP", "Mic In";
+ simple-audio-card,widgets =
+ "Headphones", "Headphones",
+ "Line Out", "Line Out",
+ "Speaker", "Speaker",
+ "Microphone", "Mic In",
+ "Line", "Line In";
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&nau8822_1a>;
+ system-clock-frequency = <12288000>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&ssi2>;
+ };
+ };
+};
+
+&can1 {
+ xceiver-supply = <®_can1>;
+ status = "okay";
+};
+
+&can2 {
+ xceiver-supply = <®_can2>;
+ status = "okay";
+};
+
+/* I2C1_SDA/SCL on MXM3 209/211 */
+&i2c1 {
+ /* Audio Codec */
+ nau8822_1a: audio-codec@1a {
+ compatible = "nuvoton,nau8822";
+ reg = <0x1a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nau8822>;
+ #sound-dai-cells = <0>;
+ };
+
+ /* Current measurement into module VCC */
+ hwmon@40 {
+ compatible = "ti,ina219";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+
+ /* Temperature Sensor */
+ temperature-sensor@4f {
+ compatible = "ti,tmp75c";
+ reg = <0x4f>;
+ };
+
+ /* EEPROM */
+ eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ size = <256>;
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&ssi2 {
+ status = "okay";
+};
+
+/* MMC1 */
+&usdhc1 {
+ bus-width = <4>;
+ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
+ vmmc-supply = <®_3v3_mmc>;
+ status = "okay";
+};
+
+/* SD1 */
+&usdhc2 {
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
+ vmmc-supply = <®_3v3_sd>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_enable_3v3_mmc: enable3v3mmcgrp {
+ fsl,pins = <
+ /* MMC1_PWR_CTRL */
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_enable_3v3_sd: enable3v3sdgrp {
+ fsl,pins = <
+ /* SD1_PWR_CTRL */
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ >;
+ };
+
+ pinctrl_enable_can1_power: enablecan1powergrp {
+ fsl,pins = <
+ /* CAN1_PWR_EN */
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ >;
+ };
+
+ pinctrl_enable_can2_power: enablecan2powergrp {
+ fsl,pins = <
+ /* CAN2_PWR_EN */
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ >;
+ };
+
+ pinctrl_nau8822: nau8822grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x130b0
+ MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
+ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
+ >;
+ };
+};
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include "imx6q.dtsi"
-#include "imx6qdl-apalis.dtsi"
+#include "imx6q-apalis-eval.dtsi"
/ {
model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board";
compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q",
"fsl,imx6q";
- aliases {
- i2c0 = &i2c1;
- i2c1 = &i2c3;
- i2c2 = &i2c2;
- rtc0 = &rtc_i2c;
- rtc1 = &snvs_rtc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
reg_pcie_switch: regulator-pcie-switch {
compatible = "regulator-fixed";
enable-active-high;
startup-delay-us = <100000>;
status = "okay";
};
-
- reg_3v3_sw: regulator-3v3-sw {
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "3.3V_SW";
- };
};
&can1 {
/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
&i2c1 {
- status = "okay";
-
+ /* PCIe Switch */
pcie-switch@58 {
compatible = "plx,pex8605";
reg = <0x58>;
};
-
- /* M41T0M6 real time clock on carrier board */
- rtc_i2c: rtc@68 {
- compatible = "st,m41t0";
- reg = <0x68>;
- };
-};
-
-/*
- * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
- * board)
- */
-&i2c3 {
- status = "okay";
};
&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reset_moci>;
- /* active-high meaning opposite of regular PERST# active-low polarity */
- reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- reset-gpio-active-high;
vpcie-supply = <®_pcie_switch>;
status = "okay";
};
-&pwm1 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&pwm3 {
- status = "okay";
-};
-
-&pwm4 {
- status = "okay";
-};
-
-®_usb_host_vbus {
- status = "okay";
-};
-
-®_usb_otg_vbus {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
&sound_spdif {
status = "okay";
};
-&spdif {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&uart4 {
- status = "okay";
-};
-
-&uart5 {
- status = "okay";
-};
-
-&usbh1 {
- disable-over-current;
- vbus-supply = <®_usb_host_vbus>;
- status = "okay";
-};
-
-&usbotg {
- disable-over-current;
- vbus-supply = <®_usb_otg_vbus>;
- status = "okay";
-};
-
/* MMC1 */
&usdhc1 {
status = "okay";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2014-2024 Toradex
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6q.dtsi"
+#include "imx6qdl-apalis.dtsi"
+
+/ {
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c3;
+ i2c2 = &i2c2;
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_3v3_sw: regulator-3v3-sw {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3.3V_SW";
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+/*
+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
+ * board)
+ */
+&i2c3 {
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reset_moci>;
+ /* active-high meaning opposite of regular PERST# active-low polarity */
+ reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ reset-gpio-active-high;
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+®_usb_host_vbus {
+ status = "okay";
+};
+
+®_usb_otg_vbus {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&spdif {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbh1 {
+ disable-over-current;
+ vbus-supply = <®_usb_host_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ disable-over-current;
+ vbus-supply = <®_usb_otg_vbus>;
+ status = "okay";
+};
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
+ aliases {
+ rtc0 = &carrier_rtc;
+ rtc1 = &snvs_rtc;
+ };
+
/* Will be filled by the bootloader */
memory@10000000 {
device_type = "memory";
status = "okay";
/* Pro baseboard model */
- rtc@68 {
+ carrier_rtc: rtc@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
+ aliases {
+ rtc0 = &pcf8523;
+ rtc1 = &snvs_rtc;
+ };
+
/* Will be filled by the bootloader */
memory@10000000 {
device_type = "memory";
aliases {
can0 = &can1;
can1 = &can2;
+ ethernet0 = &fec;
+ ethernet1 = &lan1;
+ ethernet2 = &lan2;
mdio-gpio0 = &mdio;
nand = &gpmi;
rtc0 = &i2c_rtc;
rtc1 = &snvs;
+ switch0 = &switch;
usb0 = &usbh1;
usb1 = &usbotg;
};
gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>,
<&gpio1 22 GPIO_ACTIVE_HIGH>;
- switch@0 {
+ switch: switch@0 {
compatible = "microchip,ksz8873";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_switch>;
#address-cells = <1>;
#size-cells = <0>;
- ports@0 {
+ lan1: ports@0 {
reg = <0>;
phy-mode = "internal";
label = "lan1";
};
- ports@1 {
+ lan2: ports@1 {
reg = <1>;
phy-mode = "internal";
label = "lan2";
status = "disabled";
};
- weim: weim@21b8000 {
+ weim: memory-controller@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6q-weim";
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&ldo1_reg>;
reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
- x-size = <1072>;
- y-size = <1448>;
+ touchscreen-size-x = <1072>;
+ touchscreen-size-y = <1448>;
+ touchscreen-swapped-x-y;
+ touchscreen-inverted-x;
};
/* TODO: TPS65185 PMIC for E Ink at 0x68 */
clocks = <&clks IMX6SL_CLK_DUMMY>;
};
- weim: weim@21b8000 {
+ weim: memory-controller@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
reg = <0x021b8000 0x4000>;
status = "disabled";
};
- weim: weim@21b8000 {
+ weim: memory-controller@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xfff>;
status = "okay";
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
};
&sai2 {
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xffff>;
status = "okay";
};
};
- tsc: tsc@2040000 {
+ tsc: touchscreen@2040000 {
compatible = "fsl,imx6ul-tsc";
reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 4>;
fsl,magic-packet;
+ nvmem-cells = <&fec2_mac_addr>;
+ nvmem-cell-names = "mac-address";
status = "disabled";
};
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
+ #thermal-sensor-cells = <0>;
};
};
clocks = <&clks IMX6UL_CLK_USBOH3>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
- fsl,anatop = <&anatop>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 3>;
fsl,magic-packet;
+ nvmem-cells = <&fec1_mac_addr>;
+ nvmem-cell-names = "mac-address";
status = "disabled";
};
clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
};
- weim: weim@21b8000 {
+ weim: memory-controller@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
+
+ fec1_mac_addr: mac-addr@88 {
+ reg = <0x88 6>;
+ };
+
+ fec2_mac_addr: mac-addr@8e {
+ reg = <0x8e 6>;
+ };
};
csi: csi@21c4000 {
*/
/*
- * To use usdhc1 as SD card, the WiFi node must be deleted.
+ * To use usdhc1 as SD card, the WiFi node must be deleted. The associated
+ * pwrseq node is also deleted in order to ensure that GPIO H is released.
* BT is also not available, so remove BT from the UART node.
*/
/delete-node/ &brcmf;
+/delete-node/ &usdhc1_pwrseq;
/delete-node/ &bluetooth;
/ {
};
/* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */
- /omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq {
+ usdhc1_pwrseq: usdhc1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */
};
pinctrl-names = "default";
pre-charge-time = <0xfff>;
touchscreen-average-samples = <32>;
- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
};
/* DHCOM UART1 */
/*
* Due to the design as a solderable SOM, there are no capacitors
* below the SoC, therefore higher voltages are required.
+ * Due to CPU lifetime consideration of the SoC manufacturer and
+ * the preferred area of operation in the industrial related
+ * environment, set the maximum frequency for each DHCOM i.MX6ULL
+ * to 792MHz, as with the industrial type.
*/
+ clock-frequency = <792000000>;
operating-points = <
/* kHz uV */
- 900000 1275000
792000 1250000 /* Voltage increased */
528000 1175000
396000 1025000
>;
fsl,soc-operating-points = <
/* KHz uV */
- 900000 1250000
792000 1250000 /* Voltage increased */
528000 1175000
396000 1175000
&pinctrl_usb_pwr>;
dr_mode = "host";
power-active-high;
+ over-current-active-low;
disable-over-current;
status = "okay";
};
clocks = <&clks IMX6UL_CLK_DUMMY>;
};
- iomuxc_snvs: iomuxc-snvs@2290000 {
+ iomuxc_snvs: pinctrl@2290000 {
compatible = "fsl,imx6ull-iomuxc-snvs";
reg = <0x02290000 0x4000>;
};
mmc0 = &usdhc3;
mmc1 = &usdhc1;
/delete-property/ mmc2;
+ rtc0 = &ds1339;
+ rtc1 = &snvs_rtc;
};
beeper {
gpio_buttons: gpio-keys {
compatible = "gpio-keys";
+ /*
+ * NOTE: These buttons are attached to a GPIO-expander.
+ * Enabling wakeup-source, enables wakeup on all inputs.
+ * If PE_GPIO[3..6] are used as inputs, they cause a
+ * wakeup as well.
+ */
button-0 {
/* #SWITCH_A */
label = "S11";
linux,code = <KEY_1>;
gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
+ wakeup-source;
};
button-1 {
label = "S12";
linux,code = <KEY_2>;
gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
+ wakeup-source;
};
button-2 {
label = "S13";
linux,code = <KEY_3>;
gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
+ wakeup-source;
};
};
regulator-always-on;
};
+ reg_vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
model = "imx-audio-tlv320aic32x4";
&ecspi1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
+ pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>;
cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
- <&gpio4 2 GPIO_ACTIVE_LOW>;
+ <&gpio4 2 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>;
status = "okay";
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rgmii-id";
- phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <1>;
phy-supply = <®_fec1_pwdn>;
phy-handle = <ðphy1_0>;
fsl,magic-packet;
ethphy1_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1_phy>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <500>;
};
};
};
lm75: temperature-sensor@49 {
compatible = "national,lm75";
reg = <0x49>;
+ vs-supply = <®_vcc_3v3>;
};
};
&i2c2 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_recovery>;
+ scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
tlv320aic32x4: audio-codec@18 {
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
+ vcc-supply = <®_vcc_3v3>;
};
};
&i2c3 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_recovery>;
+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
pinctrl-0 = <&pinctrl_hog_mba7_1>;
pinctrl_ecspi1: ecspi1grp {
+ fsl,pins =
+ <MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c>,
+ <MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74>,
+ <MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74>,
+ <MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74>,
+ <MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74>,
+ <MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74>;
+ };
+
+ pinctrl_ecspi1_ss0: ecspi1ss0grp {
fsl,pins = <
- MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c
- MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74
- MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74
- MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74
- MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74
- MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74
+ MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x74
>;
};
pinctrl_ecspi2: ecspi2grp {
- fsl,pins = <
- MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c
- MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74
- MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74
- MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74
- >;
+ fsl,pins =
+ <MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c>,
+ <MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74>,
+ <MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74>,
+ <MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74>;
};
pinctrl_enet1: enet1grp {
- fsl,pins = <
- MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02
- MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00
- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71
- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71
- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71
- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71
- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71
- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79
- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79
- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79
- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79
- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79
- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79
+ fsl,pins =
+ <MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02>,
+ <MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00>,
+ <MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71>,
+ <MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71>,
+ <MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71>,
+ <MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71>,
+ <MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71>,
+ <MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71>,
+ <MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79>,
+ <MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79>,
+ <MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79>,
+ <MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79>,
+ <MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79>,
+ <MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79>;
+ };
+
+ pinctrl_enet1_phy: enet1phygrp {
+ fsl,pins =
/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
- MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070
+ <MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070>,
/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
- MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078
- >;
+ <MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078>;
};
pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a
- MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52
- >;
+ fsl,pins =
+ <MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a>,
+ <MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52>;
};
pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a
- MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52
- >;
+ fsl,pins =
+ <MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a>,
+ <MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52>;
};
pinctrl_hog_mba7_1: hogmba71grp {
- fsl,pins = <
+ fsl,pins =
/* Limitation: WDOG2_B / WDOG2_RESET not usable */
- MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c
- MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074
+ <MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c>,
+ <MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074>,
/* #BOOT_EN */
- MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010
- >;
+ <MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010>;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078
- MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078
- >;
+ fsl,pins =
+ <MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078>,
+ <MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078>;
+ };
+
+ pinctrl_i2c2_recovery: i2c2recoverygrp {
+ fsl,pins =
+ <MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x40000078>,
+ <MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x40000078>;
};
pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078
- MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078
- >;
+ fsl,pins =
+ <MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078>,
+ <MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078>;
+ };
+
+ pinctrl_i2c3_recovery: i2c3recoverygrp {
+ fsl,pins =
+ <MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x40000078>,
+ <MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x40000078>;
};
pinctrl_pca9555: pca95550grp {
- fsl,pins = <
- MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78
- >;
+ fsl,pins =
+ <MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78>;
};
pinctrl_sai1: sai1grp {
- fsl,pins = <
- MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11
- MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c
- MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c
- MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c
-
- MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c
- MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14
- MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14
- >;
+ fsl,pins =
+ <MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11>,
+ <MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c>,
+ <MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c>,
+ <MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c>,
+
+ <MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c>,
+ <MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14>,
+ <MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14>;
};
pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e
- MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76
- MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76
- MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e
- >;
+ fsl,pins =
+ <MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e>,
+ <MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76>,
+ <MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76>,
+ <MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e>;
};
pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e
- MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76
- MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76
- MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e
- >;
+ fsl,pins =
+ <MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e>,
+ <MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76>,
+ <MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76>,
+ <MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e>;
};
pinctrl_uart5: uart5grp {
- fsl,pins = <
- MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e
- MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76
- >;
+ fsl,pins =
+ <MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e>,
+ <MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76>;
};
pinctrl_uart6: uart6grp {
- fsl,pins = <
- MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d
- MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75
- MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75
- MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d
- >;
+ fsl,pins =
+ <MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d>,
+ <MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75>,
+ <MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75>,
+ <MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d>;
};
pinctrl_uart7: uart7grp {
- fsl,pins = <
- MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e
- MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76
- MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76
+ fsl,pins =
+ <MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e>,
+ <MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76>,
+ <MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76>,
/* Limitation: RTS is not connected */
- MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e
- >;
+ <MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e>;
};
- pinctrl_usdhc1_gpio: usdhc1grp_gpio {
- fsl,pins = <
+ pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
+ fsl,pins =
/* WP */
- MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c
+ <MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c>,
/* CD */
- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c
+ <MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c>,
/* VSELECT */
- MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59
- >;
+ <MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59>;
};
pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX7D_PAD_SD1_CMD__SD1_CMD 0x5e
- MX7D_PAD_SD1_CLK__SD1_CLK 0x57
- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e
- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e
- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e
- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
- fsl,pins = <
- MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
- MX7D_PAD_SD1_CLK__SD1_CLK 0x57
- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
- fsl,pins = <
- MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
- MX7D_PAD_SD1_CLK__SD1_CLK 0x57
- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
- >;
+ fsl,pins =
+ <MX7D_PAD_SD1_CMD__SD1_CMD 0x5e>,
+ <MX7D_PAD_SD1_CLK__SD1_CLK 0x57>,
+ <MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e>,
+ <MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e>,
+ <MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e>,
+ <MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e>;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1_100mhzgrp {
+ fsl,pins =
+ <MX7D_PAD_SD1_CMD__SD1_CMD 0x5a>,
+ <MX7D_PAD_SD1_CLK__SD1_CLK 0x57>,
+ <MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a>,
+ <MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a>,
+ <MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a>,
+ <MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a>;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1_200mhzgrp {
+ fsl,pins =
+ <MX7D_PAD_SD1_CMD__SD1_CMD 0x5b>,
+ <MX7D_PAD_SD1_CLK__SD1_CLK 0x57>,
+ <MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b>,
+ <MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b>,
+ <MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b>,
+ <MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b>;
};
};
&iomuxc_lpsr {
pinctrl_pwm1: pwm1grp {
- fsl,pins = <
+ fsl,pins =
/* LCD_CONTRAST */
- MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50
- >;
+ <MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50>;
};
pinctrl_usbotg1: usbotg1grp {
- fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c
- MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59
- >;
+ fsl,pins =
+ <MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c>,
+ <MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59>;
};
pinctrl_wdog1: wdog1grp {
- fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
- >;
+ fsl,pins =
+ <MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30>;
};
};
status = "okay";
};
+&snvs_pwrkey {
+ status = "okay";
+};
+
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
};
&usbh {
+ disable-over-current;
status = "okay";
};
vmmc-supply = <®_sd1_vmmc>;
bus-width = <4>;
no-1-8-v;
+ no-sdio;
+ no-mmc;
status = "okay";
};
};
&i2c1 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_recovery>;
+ scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
status = "okay";
};
vgen4_reg: v33 {
- regulator-min-microvolt = <2850000>;
+ regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
/* NXP SE97BTP with temperature sensor + eeprom, TQMa7x 02xx */
- se97b: temperature-sensor-eeprom@1e {
+ se97b: temperature-sensor@1e {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1e>;
};
/* ST M24C64 */
m24c64: eeprom@50 {
compatible = "atmel,24c64";
+ read-only;
reg = <0x50>;
pagesize = <32>;
+ vcc-supply = <&vgen4_reg>;
status = "okay";
};
at24c02: eeprom@56 {
- compatible = "atmel,24c02";
+ compatible = "nxp,se97b", "atmel,24c02";
reg = <0x56>;
pagesize = <16>;
+ vcc-supply = <&vgen4_reg>;
status = "okay";
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078
- MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078
- >;
+ fsl,pins =
+ <MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078>,
+ <MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078>;
+ };
+
+ pinctrl_i2c1_recovery: i2c1recoverygrp {
+ fsl,pins =
+ <MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x40000078>,
+ <MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x40000078>;
};
pinctrl_pmic1: pmic1grp {
- fsl,pins = <
- MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C
- >;
+ fsl,pins =
+ <MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C>;
};
pinctrl_qspi: qspigrp {
- fsl,pins = <
- MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A
- MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A
- MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A
- MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A
- MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11
- MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54
- MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54
- >;
+ fsl,pins =
+ <MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A>,
+ <MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A>,
+ <MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A>,
+ <MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A>,
+ <MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11>,
+ <MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54>,
+ <MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54>;
};
pinctrl_qspi_reset: qspi_resetgrp {
- fsl,pins = <
+ fsl,pins =
/* #QSPI_RESET */
- MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52
- >;
+ <MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52>;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX7D_PAD_SD3_CMD__SD3_CMD 0x59
- MX7D_PAD_SD3_CLK__SD3_CLK 0x56
- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
- >;
+ fsl,pins =
+ <MX7D_PAD_SD3_CMD__SD3_CMD 0x59>,
+ <MX7D_PAD_SD3_CLK__SD3_CLK 0x56>,
+ <MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59>,
+ <MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59>,
+ <MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59>,
+ <MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59>,
+ <MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59>,
+ <MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59>,
+ <MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59>,
+ <MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59>,
+ <MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19>;
};
- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
- fsl,pins = <
- MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
- MX7D_PAD_SD3_CLK__SD3_CLK 0x51
- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
- >;
+ pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp {
+ fsl,pins =
+ <MX7D_PAD_SD3_CMD__SD3_CMD 0x5a>,
+ <MX7D_PAD_SD3_CLK__SD3_CLK 0x51>,
+ <MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a>,
+ <MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a>,
+ <MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a>,
+ <MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a>,
+ <MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a>,
+ <MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a>,
+ <MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a>,
+ <MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a>,
+ <MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a>;
};
- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
- fsl,pins = <
- MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
- MX7D_PAD_SD3_CLK__SD3_CLK 0x51
- MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
- MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
- MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
- MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
- MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
- MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
- MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
- MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
- MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
- >;
+ pinctrl_usdhc3_200mhz: usdhc3_200mhzgrp {
+ fsl,pins =
+ <MX7D_PAD_SD3_CMD__SD3_CMD 0x5b>,
+ <MX7D_PAD_SD3_CLK__SD3_CLK 0x51>,
+ <MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b>,
+ <MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b>,
+ <MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b>,
+ <MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b>,
+ <MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b>,
+ <MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b>,
+ <MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b>,
+ <MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b>,
+ <MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b>;
};
};
&iomuxc_lpsr {
pinctrl_wdog1: wdog1grp {
- fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
- >;
+ fsl,pins =
+ <MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30>;
};
};
};
};
-&sdma {
- status = "okay";
-};
-
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
non-removable;
+ no-sd;
+ no-sdio;
vmmc-supply = <&vgen4_reg>;
vqmmc-supply = <&sw2_reg>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rgmii-id";
- phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <1>;
phy-supply = <®_fec2_pwdn>;
phy-handle = <ðphy2_0>;
fsl,magic-packet;
ethphy2_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2_phy>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <500>;
};
};
};
+&gpio2 {
+ pcie-dis-hog {
+ gpio-hog;
+ gpios = <29 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "pcie-dis";
+ };
+
+ pcie-rst-hog {
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "pcie-rst";
+ };
+};
+
&iomuxc {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog_mba7_1>;
+ pinctrl-0 = <&pinctrl_hog_mba7_1>, <&pinctrl_hog_pcie>;
pinctrl_enet2: enet2grp {
- fsl,pins = <
- MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02
- MX7D_PAD_SD2_WP__ENET2_MDC 0x00
- MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71
- MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71
- MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71
- MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71
- MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71
- MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71
- MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79
- MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79
- MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79
- MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79
- MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79
- MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79
+ fsl,pins =
+ <MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02>,
+ <MX7D_PAD_SD2_WP__ENET2_MDC 0x00>,
+ <MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71>,
+ <MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71>,
+ <MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71>,
+ <MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71>,
+ <MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71>,
+ <MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71>,
+ <MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79>,
+ <MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79>,
+ <MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79>,
+ <MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79>,
+ <MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79>,
+ <MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79>;
+ };
+
+ pinctrl_enet2_phy: enet2phygrp {
+ fsl,pins =
/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
- MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070
+ <MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070>,
/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
- MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078
- >;
+ <MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078>;
};
- pinctrl_pcie: pciegrp {
- fsl,pins = <
- /* #pcie_wake */
- MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70
+ pinctrl_hog_pcie: hogpciegrp {
+ fsl,pins =
/* #pcie_rst */
- MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70
+ <MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70>,
/* #pcie_dis */
- MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70
- >;
+ <MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70>;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins =
+ /* #pcie_wake */
+ <MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70>;
};
};
&iomuxc_lpsr {
pinctrl_usbotg2: usbotg2grp {
- fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c
- MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59
- >;
+ fsl,pins =
+ <MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c>,
+ <MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59>;
};
};
/* probe deferral not supported */
/* pcie-bus-supply = <®_mpcie_1v5>; */
reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
- status = "okay";
+ status = "disabled";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2>;
vbus-supply = <®_usb_otg2_vbus>;
- srp-disable;
- hnp-disable;
- adp-disable;
+ disable-over-current;
dr_mode = "host";
status = "okay";
};
remote-endpoint = <&mipi_from_sensor>;
clock-lanes = <0>;
data-lanes = <1>;
+ link-frequencies = /bits/ 64 <330000000>;
};
};
};
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
};
pcie@3400000 {
clocks = <&saif0>;
};
- at24@51 {
+ eeprom@51 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x51>;
#include "qcom-msm8226.dtsi"
#include "pm8226.dtsi"
+#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
/delete-node/ &adsp_region;
pinctrl-names = "default";
pinctrl-0 = <&wlan_regulator_default_state>;
};
+
+ pwm_vibrator: pwm {
+ compatible = "clk-pwm";
+ clocks = <&mmcc CAMSS_GP0_CLK>;
+
+ pinctrl-0 = <&vibrator_clk_default_state>;
+ pinctrl-names = "default";
+
+ #pwm-cells = <2>;
+ };
+
+ vibrator {
+ compatible = "pwm-vibrator";
+
+ pwms = <&pwm_vibrator 0 10000>;
+ pwm-names = "enable";
+
+ vcc-supply = <&pm8226_l28>;
+ enable-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&vibrator_en_default_state>;
+ pinctrl-names = "default";
+ };
};
&adsp {
};
};
+ vibrator_clk_default_state: vibrator-clk-default-state {
+ pins = "gpio33";
+ function = "gp0_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ vibrator_en_default_state: vibrator-en-default-state {
+ pins = "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
wlan_hostwake_default_state: wlan-hostwake-default-state {
pins = "gpio37";
function = "gpio";
/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include "qcom-msm8226.dtsi"
-#include "pm8226.dtsi"
-
-/delete-node/ &adsp_region;
-/delete-node/ &smem_region;
+#include "qcom-msm8226-samsung-matisse-common.dtsi"
/ {
model = "Samsung Galaxy Tab 4 10.1";
compatible = "samsung,matisse-wifi", "qcom,apq8026";
chassis-type = "tablet";
- aliases {
- mmc0 = &sdhc_1; /* SDC1 eMMC slot */
- mmc1 = &sdhc_2; /* SDC2 SD card slot */
- display0 = &framebuffer0;
- };
-
- chosen {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- stdout-path = "display0";
-
- framebuffer0: framebuffer@3200000 {
- compatible = "simple-framebuffer";
- reg = <0x03200000 0x800000>;
- width = <1280>;
- height = <800>;
- stride = <(1280 * 3)>;
- format = "r8g8b8";
- };
- };
-
- gpio-hall-sensor {
- compatible = "gpio-keys";
-
- event-hall-sensor {
- label = "Hall Effect Sensor";
- gpios = <&tlmm 110 GPIO_ACTIVE_LOW>;
- linux,input-type = <EV_SW>;
- linux,code = <SW_LID>;
- debounce-interval = <15>;
- linux,can-disable;
- wakeup-source;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
-
- key-home {
- label = "Home";
- gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_HOMEPAGE>;
- debounce-interval = <15>;
- };
-
- key-volume-down {
- label = "Volume Down";
- gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEDOWN>;
- debounce-interval = <15>;
- };
-
- key-volume-up {
- label = "Volume Up";
- gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEUP>;
- debounce-interval = <15>;
- };
- };
-
- i2c-backlight {
- compatible = "i2c-gpio";
- sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
- scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
-
- pinctrl-0 = <&backlight_i2c_default_state>;
- pinctrl-names = "default";
-
- i2c-gpio,delay-us = <4>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- backlight@2c {
- compatible = "ti,lp8556";
- reg = <0x2c>;
-
- dev-ctrl = /bits/ 8 <0x80>;
- init-brt = /bits/ 8 <0x3f>;
-
- pwms = <&backlight_pwm 0 100000>;
- pwm-names = "lp8556";
-
- rom-a0h {
- rom-addr = /bits/ 8 <0xa0>;
- rom-val = /bits/ 8 <0x44>;
- };
-
- rom-a1h {
- rom-addr = /bits/ 8 <0xa1>;
- rom-val = /bits/ 8 <0x6c>;
- };
-
- rom-a5h {
- rom-addr = /bits/ 8 <0xa5>;
- rom-val = /bits/ 8 <0x24>;
- };
- };
- };
-
- backlight_pwm: pwm {
- compatible = "clk-pwm";
- #pwm-cells = <2>;
- clocks = <&mmcc CAMSS_GP0_CLK>;
- pinctrl-0 = <&backlight_pwm_default_state>;
- pinctrl-names = "default";
- };
-
- reg_tsp_1p8v: regulator-tsp-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "tsp_1p8v";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
- enable-active-high;
-
- pinctrl-names = "default";
- pinctrl-0 = <&tsp_en_default_state>;
- };
-
reg_tsp_3p3v: regulator-tsp-3p3v {
compatible = "regulator-fixed";
regulator-name = "tsp_3p3v";
pinctrl-names = "default";
pinctrl-0 = <&tsp_en1_default_state>;
};
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- framebuffer@3200000 {
- reg = <0x03200000 0x800000>;
- no-map;
- };
-
- mpss@8400000 {
- reg = <0x08400000 0x1f00000>;
- no-map;
- };
-
- mba@a300000 {
- reg = <0x0a300000 0x100000>;
- no-map;
- };
-
- reserved@cb00000 {
- reg = <0x0cb00000 0x700000>;
- no-map;
- };
-
- wcnss@d200000 {
- reg = <0x0d200000 0x700000>;
- no-map;
- };
-
- adsp_region: adsp@d900000 {
- reg = <0x0d900000 0x1800000>;
- no-map;
- };
-
- venus@f100000 {
- reg = <0x0f100000 0x500000>;
- no-map;
- };
-
- smem_region: smem@fa00000 {
- reg = <0x0fa00000 0x100000>;
- no-map;
- };
-
- reserved@fb00000 {
- reg = <0x0fb00000 0x260000>;
- no-map;
- };
-
- rfsa@fd60000 {
- reg = <0x0fd60000 0x20000>;
- no-map;
- };
-
- rmtfs@fd80000 {
- compatible = "qcom,rmtfs-mem";
- reg = <0x0fd80000 0x180000>;
- no-map;
-
- qcom,client-id = <1>;
- };
- };
-};
-
-&adsp {
- status = "okay";
};
&blsp1_i2c2 {
};
};
-&blsp1_i2c4 {
- status = "okay";
-
- muic: usb-switch@25 {
- compatible = "siliconmitus,sm5502-muic";
- reg = <0x25>;
-
- interrupt-parent = <&tlmm>;
- interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&muic_int_default_state>;
- };
-};
-
&blsp1_i2c5 {
status = "okay";
interrupt-parent = <&tlmm>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ linux,keycodes = <KEY_RESERVED>,
+ <KEY_RESERVED>,
+ <KEY_RESERVED>,
+ <KEY_RESERVED>,
+ <KEY_APPSELECT>,
+ <KEY_BACK>;
+
pinctrl-names = "default";
pinctrl-0 = <&tsp_int_rst_default_state>;
};
};
-&rpm_requests {
- regulators {
- compatible = "qcom,rpm-pm8226-regulators";
-
- pm8226_s3: s3 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1300000>;
- };
-
- pm8226_s4: s4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- pm8226_s5: s5 {
- regulator-min-microvolt = <1150000>;
- regulator-max-microvolt = <1150000>;
- };
-
- pm8226_l1: l1 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- pm8226_l2: l2 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- pm8226_l3: l3 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1337500>;
- regulator-always-on;
- };
-
- pm8226_l4: l4 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- pm8226_l5: l5 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- pm8226_l6: l6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- pm8226_l7: l7 {
- regulator-min-microvolt = <1850000>;
- regulator-max-microvolt = <1850000>;
- };
-
- pm8226_l8: l8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- pm8226_l9: l9 {
- regulator-min-microvolt = <2050000>;
- regulator-max-microvolt = <2050000>;
- };
-
- pm8226_l10: l10 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- pm8226_l12: l12 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- pm8226_l14: l14 {
- regulator-min-microvolt = <2750000>;
- regulator-max-microvolt = <2750000>;
- };
-
- pm8226_l15: l15 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- pm8226_l16: l16 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3350000>;
- };
-
- pm8226_l17: l17 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-system-load = <200000>;
- regulator-allow-set-load;
- regulator-always-on;
- };
-
- pm8226_l18: l18 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
- };
-
- pm8226_l19: l19 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <3000000>;
- };
-
- pm8226_l20: l20 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3075000>;
- };
-
- pm8226_l21: l21 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- pm8226_l22: l22 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- };
-
- pm8226_l23: l23 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- pm8226_l24: l24 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1350000>;
- };
-
- pm8226_l25: l25 {
- regulator-min-microvolt = <1775000>;
- regulator-max-microvolt = <2125000>;
- };
-
- pm8226_l26: l26 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1300000>;
- };
-
- pm8226_l27: l27 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- pm8226_l28: l28 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- pm8226_lvs1: lvs1 {};
- };
-};
-
-&sdhc_1 {
- vmmc-supply = <&pm8226_l17>;
- vqmmc-supply = <&pm8226_l6>;
-
- bus-width = <8>;
- non-removable;
-
- status = "okay";
+&pm8226_l3 {
+ regulator-max-microvolt = <1337500>;
};
-&sdhc_2 {
- vmmc-supply = <&pm8226_l18>;
- vqmmc-supply = <&pm8226_l21>;
-
- bus-width = <4>;
- cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
-
- status = "okay";
+&pm8226_s4 {
+ regulator-max-microvolt = <1800000>;
};
&tlmm {
- accel_int_default_state: accel-int-default-state {
- pins = "gpio54";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- backlight_i2c_default_state: backlight-i2c-default-state {
- pins = "gpio20", "gpio21";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- backlight_pwm_default_state: backlight-pwm-default-state {
- pins = "gpio33";
- function = "gp0_clk";
- };
-
- muic_int_default_state: muic-int-default-state {
- pins = "gpio67";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- tsp_en_default_state: tsp-en-default-state {
- pins = "gpio31";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
tsp_en1_default_state: tsp-en1-default-state {
pins = "gpio73";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
-
- tsp_int_rst_default_state: tsp-int-rst-default-state {
- pins = "gpio17";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
-};
-
-&usb {
- extcon = <&muic>, <&muic>;
- status = "okay";
-};
-
-&usb_hs_phy {
- extcon = <&muic>;
- v1p8-supply = <&pm8226_l10>;
- v3p3-supply = <&pm8226_l20>;
};
cpu-pmu {
compatible = "qcom,krait-pmu";
- interrupts = <1 10 0x304>;
+ interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
clocks {
modem_smsm: modem@1 {
reg = <1>;
- interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
q6_smsm: q6@2 {
reg = <2>;
- interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
wcnss_smsm: wcnss@3 {
reg = <3>;
- interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
dsps_smsm: dsps@4 {
reg = <4>;
- interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&ps_hold>;
timer@200a000 {
compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
"qcom,msm-timer";
- interrupts = <1 1 0x301>,
- <1 2 0x301>,
- <1 3 0x301>;
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>;
clock-frequency = <27000000>;
cpu-offset = <0x80000>;
#clock-cells = <0>;
};
- saw0: power-controller@2089000 {
+ saw0: power-manager@2089000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw0_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
- saw1: power-controller@2099000 {
+ saw1: power-manager@2099000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw1_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
- saw2: power-controller@20a9000 {
+ saw2: power-manager@20a9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw2_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
- saw3: power-controller@20b9000 {
+ saw3: power-manager@20b9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw3_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
sps_sic_non_secure: sps-sic-non-secure@12100000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x12450000 0x100>,
<0x12400000 0x03>;
- interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
pinctrl-1 = <&i2c1_pins_sleep>;
pinctrl-names = "default", "sleep";
reg = <0x12460000 0x1000>;
- interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-1 = <&i2c2_pins_sleep>;
pinctrl-names = "default", "sleep";
- interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a240000 0x100>,
<0x1a200000 0x03>;
- interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
gsbi5_spi: spi@1a280000 {
compatible = "qcom,spi-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
- interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&spi5_default>;
pinctrl-1 = <&spi5_sleep>;
pinctrl-names = "default", "sleep";
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16540000 0x100>,
<0x16500000 0x03>;
- interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16640000 0x1000>,
<0x16600000 0x1000>;
- interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
sdcc3bam: dma-controller@12182000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
- interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
sdcc4bam: dma-controller@121c2000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x121c2000 0x8000>;
- interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC4_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
sdcc1bam: dma-controller@12402000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12402000 0x8000>;
- interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
};
};
- saw0: power-controller@f9089000 {
+ saw0: power-manager@f9089000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
};
- saw1: power-controller@f9099000 {
+ saw1: power-manager@f9099000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
};
- saw2: power-controller@f90a9000 {
+ saw2: power-manager@f90a9000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
};
- saw3: power-controller@f90b9000 {
+ saw3: power-manager@f90b9000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
};
- saw_l2: power-controller@f9012000 {
- compatible = "qcom,saw2";
+ saw_l2: power-manager@f9012000 {
+ compatible = "qcom,apq8084-saw2-v2.1-l2", "qcom,saw2";
reg = <0xf9012000 0x1000>;
- regulator;
};
acc0: power-manager@f9088000 {
chosen {
stdout-path = "serial0:115200n8";
};
+};
- soc {
- rng@22000 {
- status = "okay";
- };
-
- pinctrl@1000000 {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio54";
- };
- pinconf {
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
- };
+&prng {
+ status = "okay";
+};
- blsp_dma: dma-controller@7884000 {
- status = "okay";
+&tlmm {
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "blsp_uart0";
+ bias-disable;
};
+ };
- spi@78b5000 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- mx25l25635e@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "mx25l25635e";
- spi-max-frequency = <24000000>;
- };
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio55", "gpio56", "gpio57";
};
-
- serial@78af000 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio54";
};
-
- cryptobam: dma-controller@8e04000 {
- status = "okay";
+ pinconf {
+ pins = "gpio55", "gpio56", "gpio57";
+ drive-strength = <12>;
+ bias-disable;
};
-
- crypto@8e3a000 {
- status = "okay";
+ pinconf_cs {
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
};
+ };
+};
- watchdog@b017000 {
- status = "okay";
- };
+&blsp_dma {
+ status = "okay";
+};
- wifi@a000000 {
- status = "okay";
- };
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
- wifi@a800000 {
- status = "okay";
- };
+ flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <24000000>;
};
};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&wifi0 {
+ status = "okay";
+};
+
+&wifi1 {
+ status = "okay";
+};
timer {
compatible = "arm,armv7-timer";
- interrupts = <1 2 0xf08>,
- <1 3 0xf08>,
- <1 4 0xf08>,
- <1 1 0xf08>;
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <48000000>;
always-on;
};
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
};
- saw0: regulator@b089000 {
- compatible = "qcom,saw2";
+ saw0: power-manager@b089000 {
+ compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
- regulator;
};
- saw1: regulator@b099000 {
- compatible = "qcom,saw2";
+ saw1: power-manager@b099000 {
+ compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
- regulator;
};
- saw2: regulator@b0a9000 {
- compatible = "qcom,saw2";
+ saw2: power-manager@b0a9000 {
+ compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
- regulator;
};
- saw3: regulator@b0b9000 {
- compatible = "qcom,saw2";
+ saw3: power-manager@b0b9000 {
+ compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
- regulator;
};
- saw_l2: regulator@b012000 {
- compatible = "qcom,saw2";
+ saw_l2: power-manager@b012000 {
+ compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2";
reg = <0xb012000 0x1000>;
- regulator;
};
blsp1_uart1: serial@78af000 {
clocks = <&gcc GCC_USB2_MASTER_CLK>,
<&gcc GCC_USB2_SLEEP_CLK>,
<&gcc GCC_USB2_MOCK_UTMI_CLK>;
- clock-names = "master", "sleep", "mock_utmi";
+ clock-names = "core", "sleep", "mock_utmi";
ranges;
status = "disabled";
#clock-cells = <0>;
};
- saw0: regulator@2089000 {
- compatible = "qcom,saw2";
+ saw0: power-manager@2089000 {
+ compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- regulator;
};
acc1: clock-controller@2098000 {
#clock-cells = <0>;
};
- saw1: regulator@2099000 {
- compatible = "qcom,saw2";
+ saw1: power-manager@2099000 {
+ compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
};
nss_common: syscon@3000000 {
ranges;
resets = <&gcc USB30_0_MASTER_RESET>;
- reset-names = "master";
status = "disabled";
ranges;
resets = <&gcc USB30_1_MASTER_RESET>;
- reset-names = "master";
status = "disabled";
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Matti Lehtimäki <matti.lehtimaki@gmail.com>
+ */
+
+#include <dt-bindings/input/input.h>
+#include "qcom-msm8226.dtsi"
+#include "pm8226.dtsi"
+
+/delete-node/ &adsp_region;
+/delete-node/ &smem_region;
+
+/ {
+ aliases {
+ mmc0 = &sdhc_1; /* SDC1 eMMC slot */
+ mmc1 = &sdhc_2; /* SDC2 SD card slot */
+ display0 = &framebuffer0;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ stdout-path = "display0";
+
+ framebuffer0: framebuffer@3200000 {
+ compatible = "simple-framebuffer";
+ reg = <0x03200000 0x800000>;
+ width = <1280>;
+ height = <800>;
+ stride = <(1280 * 3)>;
+ format = "r8g8b8";
+ };
+ };
+
+ gpio-hall-sensor {
+ compatible = "gpio-keys";
+
+ event-hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&tlmm 110 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ key-home {
+ label = "Home";
+ gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOMEPAGE>;
+ debounce-interval = <15>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <15>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ };
+ };
+
+ i2c-backlight {
+ compatible = "i2c-gpio";
+ sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+ pinctrl-0 = <&backlight_i2c_default_state>;
+ pinctrl-names = "default";
+
+ i2c-gpio,delay-us = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ backlight@2c {
+ compatible = "ti,lp8556";
+ reg = <0x2c>;
+
+ dev-ctrl = /bits/ 8 <0x80>;
+ init-brt = /bits/ 8 <0x3f>;
+
+ pwms = <&backlight_pwm 0 100000>;
+ pwm-names = "lp8556";
+
+ rom-a0h {
+ rom-addr = /bits/ 8 <0xa0>;
+ rom-val = /bits/ 8 <0x44>;
+ };
+
+ rom-a1h {
+ rom-addr = /bits/ 8 <0xa1>;
+ rom-val = /bits/ 8 <0x6c>;
+ };
+
+ rom-a5h {
+ rom-addr = /bits/ 8 <0xa5>;
+ rom-val = /bits/ 8 <0x24>;
+ };
+ };
+ };
+
+ backlight_pwm: pwm {
+ compatible = "clk-pwm";
+ #pwm-cells = <2>;
+ clocks = <&mmcc CAMSS_GP0_CLK>;
+ pinctrl-0 = <&backlight_pwm_default_state>;
+ pinctrl-names = "default";
+ };
+
+ reg_tsp_1p8v: regulator-tsp-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "tsp_1p8v";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tsp_en_default_state>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@3200000 {
+ reg = <0x03200000 0x800000>;
+ no-map;
+ };
+
+ mpss@8400000 {
+ reg = <0x08400000 0x1f00000>;
+ no-map;
+ };
+
+ mba@a300000 {
+ reg = <0x0a300000 0x100000>;
+ no-map;
+ };
+
+ reserved@cb00000 {
+ reg = <0x0cb00000 0x700000>;
+ no-map;
+ };
+
+ wcnss@d200000 {
+ reg = <0x0d200000 0x700000>;
+ no-map;
+ };
+
+ adsp_region: adsp@d900000 {
+ reg = <0x0d900000 0x1800000>;
+ no-map;
+ };
+
+ venus@f100000 {
+ reg = <0x0f100000 0x500000>;
+ no-map;
+ };
+
+ smem_region: smem@fa00000 {
+ reg = <0x0fa00000 0x100000>;
+ no-map;
+ };
+
+ reserved@fb00000 {
+ reg = <0x0fb00000 0x260000>;
+ no-map;
+ };
+
+ rfsa@fd60000 {
+ reg = <0x0fd60000 0x20000>;
+ no-map;
+ };
+
+ rmtfs@fd80000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0fd80000 0x180000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ };
+ };
+};
+
+&adsp {
+ status = "okay";
+};
+
+&blsp1_i2c4 {
+ status = "okay";
+
+ muic: usb-switch@25 {
+ compatible = "siliconmitus,sm5502-muic";
+ reg = <0x25>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&muic_int_default_state>;
+ };
+};
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ regulator-always-on;
+ };
+
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2125000>;
+ };
+
+ pm8226_l26: l26 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_lvs1: lvs1 {};
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8226_l17>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ bus-width = <8>;
+ non-removable;
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ vmmc-supply = <&pm8226_l18>;
+ vqmmc-supply = <&pm8226_l21>;
+
+ bus-width = <4>;
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&tlmm {
+ accel_int_default_state: accel-int-default-state {
+ pins = "gpio54";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ backlight_i2c_default_state: backlight-i2c-default-state {
+ pins = "gpio20", "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ backlight_pwm_default_state: backlight-pwm-default-state {
+ pins = "gpio33";
+ function = "gp0_clk";
+ };
+
+ muic_int_default_state: muic-int-default-state {
+ pins = "gpio67";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tsp_en_default_state: tsp-en-default-state {
+ pins = "gpio31";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tsp_int_rst_default_state: tsp-int-rst-default-state {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+};
+
+&usb {
+ extcon = <&muic>, <&muic>;
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&muic>;
+ v1p8-supply = <&pm8226_l10>;
+ v3p3-supply = <&pm8226_l20>;
+};
chosen { };
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0>;
- };
-
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
};
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ enable-method = "qcom,msm8226-smp";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ qcom,acc = <&acc0>;
+ qcom,saw = <&saw0>;
+ };
+
+ CPU1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ enable-method = "qcom,msm8226-smp";
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ qcom,acc = <&acc1>;
+ qcom,saw = <&saw1>;
+ };
+
+ CPU2: cpu@2 {
+ compatible = "arm,cortex-a7";
+ enable-method = "qcom,msm8226-smp";
+ device_type = "cpu";
+ reg = <2>;
+ next-level-cache = <&L2>;
+ qcom,acc = <&acc2>;
+ qcom,saw = <&saw2>;
+ };
+
+ CPU3: cpu@3 {
+ compatible = "arm,cortex-a7";
+ enable-method = "qcom,msm8226-smp";
+ device_type = "cpu";
+ reg = <3>;
+ next-level-cache = <&L2>;
+ qcom,acc = <&acc3>;
+ qcom,saw = <&saw3>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
firmware {
scm {
compatible = "qcom,scm-msm8226", "qcom,scm";
};
};
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
reg = <0xf9011000 0x1000>;
};
+ saw_l2: power-manager@f9012000 {
+ compatible = "qcom,msm8226-saw2-v2.1-l2", "qcom,saw2";
+ reg = <0xf9012000 0x1000>;
+ };
+
+ watchdog@f9017000 {
+ compatible = "qcom,apss-wdt-msm8226", "qcom,kpss-wdt";
+ reg = <0xf9017000 0x1000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&sleep_clk>;
+ };
+
+ timer@f9020000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xf9020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ frame@f9021000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9021000 0x1000>,
+ <0xf9022000 0x1000>;
+ };
+
+ frame@f9023000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9023000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9024000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9024000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9025000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9025000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9026000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9026000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9027000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9027000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f9028000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9028000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ acc0: power-manager@f9088000 {
+ compatible = "qcom,kpss-acc-v2";
+ reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
+ };
+
+ saw0: power-manager@f9089000 {
+ compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
+ reg = <0xf9089000 0x1000>;
+ };
+
+ acc1: power-manager@f9098000 {
+ compatible = "qcom,kpss-acc-v2";
+ reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
+ };
+
+ saw1: power-manager@f9099000 {
+ compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
+ reg = <0xf9099000 0x1000>;
+ };
+
+ acc2: power-manager@f90a8000 {
+ compatible = "qcom,kpss-acc-v2";
+ reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
+ };
+
+ saw2: power-manager@f90a9000 {
+ compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
+ reg = <0xf90a9000 0x1000>;
+ };
+
+ acc3: power-manager@f90b8000 {
+ compatible = "qcom,kpss-acc-v2";
+ reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
+ };
+
+ saw3: power-manager@f90b9000 {
+ compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
+ reg = <0xf90b9000 0x1000>;
+ };
+
sdhc_1: mmc@f9824900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
status = "disabled";
};
- sdhc_2: mmc@f98a4900 {
+ sdhc_3: mmc@f9864900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
- reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
+ reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
reg-names = "hc", "core";
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_AHB_CLK>,
- <&gcc GCC_SDCC2_APPS_CLK>,
+ clocks = <&gcc GCC_SDCC3_AHB_CLK>,
+ <&gcc GCC_SDCC3_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
pinctrl-names = "default";
- pinctrl-0 = <&sdhc2_default_state>;
+ pinctrl-0 = <&sdhc3_default_state>;
status = "disabled";
};
- sdhc_3: mmc@f9864900 {
+ sdhc_2: mmc@f98a4900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
- reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
+ reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc", "core";
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC3_AHB_CLK>,
- <&gcc GCC_SDCC3_APPS_CLK>,
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
pinctrl-names = "default";
- pinctrl-0 = <&sdhc3_default_state>;
+ pinctrl-0 = <&sdhc2_default_state>;
status = "disabled";
};
};
blsp1_i2c1: i2c@f9923000 {
- status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9923000 0x1000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&blsp1_i2c1_pins>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
blsp1_i2c2: i2c@f9924000 {
- status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9924000 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&blsp1_i2c2_pins>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
blsp1_i2c3: i2c@f9925000 {
- status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9925000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&blsp1_i2c3_pins>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
blsp1_i2c4: i2c@f9926000 {
- status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9926000 0x1000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&blsp1_i2c4_pins>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
blsp1_i2c5: i2c@f9927000 {
- status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9927000 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&blsp1_i2c5_pins>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
blsp1_i2c6: i2c@f9928000 {
status = "disabled";
};
- cci: cci@fda0c000 {
- compatible = "qcom,msm8226-cci";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xfda0c000 0x1000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
- clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
- <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
- <&mmcc CAMSS_CCI_CCI_CLK>;
- clock-names = "camss_top_ahb",
- "cci_ahb",
- "cci";
-
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cci_default>;
- pinctrl-1 = <&cci_sleep>;
-
- status = "disabled";
-
- cci_i2c0: i2c-bus@0 {
- reg = <0>;
- clock-frequency = <400000>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
usb: usb@f9a55000 {
compatible = "qcom,ci-hdrc";
reg = <0xf9a55000 0x200>,
};
};
+ rng@f9bff000 {
+ compatible = "qcom,prng";
+ reg = <0xf9bff000 0x200>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ };
+
+ sram@fc190000 {
+ compatible = "qcom,msm8226-rpm-stats";
+ reg = <0xfc190000 0x10000>;
+ };
+
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8226";
reg = <0xfc400000 0x4000>;
"sleep_clk";
};
- mmcc: clock-controller@fd8c0000 {
- compatible = "qcom,mmcc-msm8226";
- reg = <0xfd8c0000 0x6000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
-
- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
- <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
- <&gcc GPLL0_VOTE>,
- <&gcc GPLL1_VOTE>,
- <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
- <&mdss_dsi0_phy 1>,
- <&mdss_dsi0_phy 0>;
- clock-names = "xo",
- "mmss_gpll0_vote",
- "gpll0_vote",
- "gpll1_vote",
- "gfx3d_clk_src",
- "dsi0pll",
- "dsi0pllbyte";
- };
-
- tlmm: pinctrl@fd510000 {
- compatible = "qcom,msm8226-pinctrl";
- reg = <0xfd510000 0x4000>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&tlmm 0 0 117>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ rpm_msg_ram: sram@fc428000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0xfc428000 0x4000>;
- blsp1_i2c1_pins: blsp1-i2c1-state {
- pins = "gpio2", "gpio3";
- function = "blsp_i2c1";
- drive-strength = <2>;
- bias-disable;
- };
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xfc428000 0x4000>;
- blsp1_i2c2_pins: blsp1-i2c2-state {
- pins = "gpio6", "gpio7";
- function = "blsp_i2c2";
- drive-strength = <2>;
- bias-disable;
+ apss_master_stats: sram@150 {
+ reg = <0x150 0x14>;
};
- blsp1_i2c3_pins: blsp1-i2c3-state {
- pins = "gpio10", "gpio11";
- function = "blsp_i2c3";
- drive-strength = <2>;
- bias-disable;
+ mpss_master_stats: sram@b50 {
+ reg = <0xb50 0x14>;
};
- blsp1_i2c4_pins: blsp1-i2c4-state {
- pins = "gpio14", "gpio15";
- function = "blsp_i2c4";
- drive-strength = <2>;
- bias-disable;
+ lpss_master_stats: sram@1550 {
+ reg = <0x1550 0x14>;
};
- blsp1_i2c5_pins: blsp1-i2c5-state {
- pins = "gpio18", "gpio19";
- function = "blsp_i2c5";
- drive-strength = <2>;
- bias-disable;
+ pronto_master_stats: sram@1f50 {
+ reg = <0x1f50 0x14>;
};
-
- blsp1_i2c6_pins: blsp1-i2c6-state {
- pins = "gpio22", "gpio23";
- function = "blsp_i2c6";
- drive-strength = <2>;
- bias-disable;
- };
-
- cci_default: cci-default-state {
- pins = "gpio29", "gpio30";
- function = "cci_i2c0";
-
- drive-strength = <2>;
- bias-disable;
- };
-
- cci_sleep: cci-sleep-state {
- pins = "gpio29", "gpio30";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- };
-
- sdhc1_default_state: sdhc1-default-state {
- clk-pins {
- pins = "sdc1_clk";
- drive-strength = <10>;
- bias-disable;
- };
-
- cmd-data-pins {
- pins = "sdc1_cmd", "sdc1_data";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- sdhc2_default_state: sdhc2-default-state {
- clk-pins {
- pins = "sdc2_clk";
- drive-strength = <10>;
- bias-disable;
- };
-
- cmd-data-pins {
- pins = "sdc2_cmd", "sdc2_data";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- sdhc3_default_state: sdhc3-default-state {
- clk-pins {
- pins = "gpio44";
- function = "sdc3";
- drive-strength = <8>;
- bias-disable;
- };
-
- cmd-pins {
- pins = "gpio43";
- function = "sdc3";
- drive-strength = <8>;
- bias-pull-up;
- };
-
- data-pins {
- pins = "gpio39", "gpio40", "gpio41", "gpio42";
- function = "sdc3";
- drive-strength = <8>;
- bias-pull-up;
- };
- };
- };
+ };
tsens: thermal-sensor@fc4a9000 {
compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1";
#interrupt-cells = <4>;
};
- rng@f9bff000 {
- compatible = "qcom,prng";
- reg = <0xf9bff000 0x200>;
- clocks = <&gcc GCC_PRNG_AHB_CLK>;
- clock-names = "core";
+ tcsr_mutex: hwlock@fd484000 {
+ compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
+ reg = <0xfd484000 0x1000>;
+ #hwlock-cells = <1>;
};
- timer@f9020000 {
- compatible = "arm,armv7-timer-mem";
- reg = <0xf9020000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- frame@f9021000 {
- frame-number = <0>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9021000 0x1000>,
- <0xf9022000 0x1000>;
- };
+ tlmm: pinctrl@fd510000 {
+ compatible = "qcom,msm8226-pinctrl";
+ reg = <0xfd510000 0x4000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 117>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- frame@f9023000 {
- frame-number = <1>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9023000 0x1000>;
- status = "disabled";
+ blsp1_i2c1_pins: blsp1-i2c1-state {
+ pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
+ drive-strength = <2>;
+ bias-disable;
};
- frame@f9024000 {
- frame-number = <2>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9024000 0x1000>;
- status = "disabled";
+ blsp1_i2c2_pins: blsp1-i2c2-state {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ drive-strength = <2>;
+ bias-disable;
};
- frame@f9025000 {
- frame-number = <3>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9025000 0x1000>;
- status = "disabled";
+ blsp1_i2c3_pins: blsp1-i2c3-state {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ drive-strength = <2>;
+ bias-disable;
};
- frame@f9026000 {
- frame-number = <4>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9026000 0x1000>;
- status = "disabled";
+ blsp1_i2c4_pins: blsp1-i2c4-state {
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+ drive-strength = <2>;
+ bias-disable;
};
- frame@f9027000 {
- frame-number = <5>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9027000 0x1000>;
- status = "disabled";
+ blsp1_i2c5_pins: blsp1-i2c5-state {
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c5";
+ drive-strength = <2>;
+ bias-disable;
};
- frame@f9028000 {
- frame-number = <6>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9028000 0x1000>;
- status = "disabled";
+ blsp1_i2c6_pins: blsp1-i2c6-state {
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+ drive-strength = <2>;
+ bias-disable;
};
- };
-
- sram@fc190000 {
- compatible = "qcom,msm8226-rpm-stats";
- reg = <0xfc190000 0x10000>;
- };
- rpm_msg_ram: sram@fc428000 {
- compatible = "qcom,rpm-msg-ram";
- reg = <0xfc428000 0x4000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0xfc428000 0x4000>;
-
- apss_master_stats: sram@150 {
- reg = <0x150 0x14>;
- };
+ cci_default: cci-default-state {
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c0";
- mpss_master_stats: sram@b50 {
- reg = <0xb50 0x14>;
+ drive-strength = <2>;
+ bias-disable;
};
- lpss_master_stats: sram@1550 {
- reg = <0x1550 0x14>;
- };
+ cci_sleep: cci-sleep-state {
+ pins = "gpio29", "gpio30";
+ function = "gpio";
- pronto_master_stats: sram@1f50 {
- reg = <0x1f50 0x14>;
+ drive-strength = <2>;
+ bias-disable;
};
- };
-
- tcsr_mutex: hwlock@fd484000 {
- compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
- reg = <0xfd484000 0x1000>;
- #hwlock-cells = <1>;
- };
-
- adsp: remoteproc@fe200000 {
- compatible = "qcom,msm8226-adsp-pil";
- reg = <0xfe200000 0x100>;
-
- interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
-
- power-domains = <&rpmpd MSM8226_VDDCX>;
- power-domain-names = "cx";
-
- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
- clock-names = "xo";
-
- memory-region = <&adsp_region>;
-
- qcom,smem-states = <&adsp_smp2p_out 0>;
- qcom,smem-state-names = "stop";
- status = "disabled";
+ sdhc1_default_state: sdhc1-default-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <10>;
+ bias-disable;
+ };
- smd-edge {
- interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+ cmd-data-pins {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
- qcom,ipc = <&apcs 8 8>;
- qcom,smd-edge = <1>;
+ sdhc2_default_state: sdhc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <10>;
+ bias-disable;
+ };
- label = "lpass";
+ cmd-data-pins {
+ pins = "sdc2_cmd", "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
};
- };
- sram@fdd00000 {
- compatible = "qcom,msm8226-ocmem";
- reg = <0xfdd00000 0x2000>,
- <0xfec00000 0x20000>;
- reg-names = "ctrl", "mem";
- ranges = <0 0xfec00000 0x20000>;
- clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>;
- clock-names = "core";
+ sdhc3_default_state: sdhc3-default-state {
+ clk-pins {
+ pins = "gpio44";
+ function = "sdc3";
+ drive-strength = <8>;
+ bias-disable;
+ };
- #address-cells = <1>;
- #size-cells = <1>;
+ cmd-pins {
+ pins = "gpio43";
+ function = "sdc3";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
- gmu_sram: gmu-sram@0 {
- reg = <0x0 0x20000>;
+ data-pins {
+ pins = "gpio39", "gpio40", "gpio41", "gpio42";
+ function = "sdc3";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
};
};
- sram@fe805000 {
- compatible = "qcom,msm8226-imem", "syscon", "simple-mfd";
- reg = <0xfe805000 0x1000>;
-
- reboot-mode {
- compatible = "syscon-reboot-mode";
- offset = <0x65c>;
+ mmcc: clock-controller@fd8c0000 {
+ compatible = "qcom,mmcc-msm8226";
+ reg = <0xfd8c0000 0x6000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
- mode-bootloader = <0x77665500>;
- mode-normal = <0x77665501>;
- mode-recovery = <0x77665502>;
- };
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
+ <&gcc GPLL0_VOTE>,
+ <&gcc GPLL1_VOTE>,
+ <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi0_phy 0>;
+ clock-names = "xo",
+ "mmss_gpll0_vote",
+ "gpll0_vote",
+ "gpll1_vote",
+ "gfx3d_clk_src",
+ "dsi0pll",
+ "dsi0pllbyte";
};
mdss: display-subsystem@fd900000 {
};
};
+ cci: cci@fda0c000 {
+ compatible = "qcom,msm8226-cci";
+ reg = <0xfda0c000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+ <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
+ <&mmcc CAMSS_CCI_CCI_CLK>;
+ clock-names = "camss_top_ahb",
+ "cci_ahb",
+ "cci";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cci_default>;
+ pinctrl-1 = <&cci_sleep>;
+
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
gpu: adreno@fdb00000 {
compatible = "qcom,adreno-305.18", "qcom,adreno";
reg = <0xfdb00000 0x10000>;
};
};
};
+
+ sram@fdd00000 {
+ compatible = "qcom,msm8226-ocmem";
+ reg = <0xfdd00000 0x2000>,
+ <0xfec00000 0x20000>;
+ reg-names = "ctrl", "mem";
+ ranges = <0 0xfec00000 0x20000>;
+ clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>;
+ clock-names = "core";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gmu_sram: gmu-sram@0 {
+ reg = <0x0 0x20000>;
+ };
+ };
+
+ adsp: remoteproc@fe200000 {
+ compatible = "qcom,msm8226-adsp-pil";
+ reg = <0xfe200000 0x100>;
+
+ interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+ power-domains = <&rpmpd MSM8226_VDDCX>;
+ power-domain-names = "cx";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ memory-region = <&adsp_region>;
+
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ smd-edge {
+ interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 8>;
+ qcom,smd-edge = <1>;
+
+ label = "lpass";
+ };
+ };
+
+ sram@fe805000 {
+ compatible = "qcom,msm8226-imem", "syscon", "simple-mfd";
+ reg = <0xfe805000 0x1000>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x65c>;
+
+ mode-bootloader = <0x77665500>;
+ mode-normal = <0x77665501>;
+ mode-recovery = <0x77665502>;
+ };
+ };
};
thermal-zones {
cpu-pmu {
compatible = "qcom,scorpion-mp-pmu";
- interrupts = <1 9 0x304>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
clocks {
timer@2000000 {
compatible = "qcom,scss-timer", "qcom,msm-timer";
- interrupts = <1 0 0x301>,
- <1 1 0x301>,
- <1 2 0x301>;
+ interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
reg = <0x02000000 0x100>;
- clock-frequency = <27000000>,
- <32768>;
+ clock-frequency = <27000000>;
cpu-offset = <0x40000>;
};
gpio-controller;
gpio-ranges = <&tlmm 0 0 173>;
#gpio-cells = <2>;
- interrupts = <0 16 0x4>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>;
- interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
gsbi12_i2c: i2c@19c80000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x19c80000 0x1000>;
- interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
};
unknown@fb00000 {
- reg = <0x0fb00000 0x1b00000>;
+ reg = <0x0fb00000 0x280000>;
+ no-map;
+ };
+
+ rmtfs@fd80000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0fd80000 0x180000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ };
+
+ unknown@ff00000 {
+ reg = <0x0ff00000 0x1700000>;
no-map;
};
};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Matti Lehtimäki <matti.lehtimaki@gmail.com>
+ * Copyright (c) 2023, Stefan Hansson <newbyte@postmarketos.org>
+ */
+
+/dts-v1/;
+
+#include "qcom-msm8226-samsung-matisse-common.dtsi"
+
+/ {
+ model = "Samsung Galaxy Tab 4 10.1 LTE";
+ compatible = "samsung,matisselte", "qcom,msm8926", "qcom,msm8226";
+ chassis-type = "tablet";
+
+ reg_tsp_3p3v: regulator-tsp-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "tsp_3p3v";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tsp_en1_default_state>;
+ };
+};
+
+&tlmm {
+ tsp_en1_default_state: tsp-en1-default-state {
+ pins = "gpio32";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+
+&msmgpio {
+ i2c3_default_state: i2c3-default-state {
+ i2c3-pins {
+ pins = "gpio16", "gpio17";
+ function = "gsbi3";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ i2c3_sleep_state: i2c3-sleep-state {
+ i2c3-pins {
+ pins = "gpio16", "gpio17";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+ };
+};
#include "qcom-msm8960.dtsi"
#include "pm8921.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
/ {
model = "Samsung Galaxy Express SGH-I437";
chosen {
stdout-path = "serial0:115200n8";
};
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pin_a>;
+
+ key-home {
+ label = "Home";
+ gpios = <&msmgpio 40 GPIO_ACTIVE_LOW>;
+ debounce-interval = <5>;
+ linux,code = <KEY_HOMEPAGE>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&msmgpio 50 GPIO_ACTIVE_LOW>;
+ debounce-interval = <5>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&msmgpio 81 GPIO_ACTIVE_LOW>;
+ debounce-interval = <5>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
};
&gsbi5 {
status = "okay";
};
+&gsbi3 {
+ qcom,mode = <GSBI_PROT_I2C>;
+ status = "okay";
+};
+
+&gsbi3_i2c {
+ status = "okay";
+
+ // Atmel mXT224S touchscreen
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ vdda-supply = <&pm8921_lvs6>;
+ vdd-supply = <&pm8921_l17>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen>;
+ };
+};
+
&msmgpio {
spi1_default: spi1-default-state {
mosi-pins {
bias-disable;
};
};
+
+ gpio_keys_pin_a: gpio-keys-active-state {
+ pins = "gpio40", "gpio50", "gpio81";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ touchscreen: touchscreen-int-state {
+ pins = "gpio11";
+ function = "gpio";
+ output-enable;
+ bias-disable;
+ drive-strength = <2>;
+ };
};
&pm8921 {
};
pm8921_l17: l17 {
- regulator-min-microvolt = <1800000>;
+ regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
bias-pull-down;
};
#clock-cells = <0>;
};
- saw0: regulator@2089000 {
- compatible = "qcom,saw2";
+ saw0: power-manager@2089000 {
+ compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw0_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
- saw1: regulator@2099000 {
- compatible = "qcom,saw2";
+ saw1: power-manager@2099000 {
+ compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw1_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
gsbi5: gsbi@16400000 {
};
};
};
+
+ gsbi3: gsbi@16200000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x16200000 0x100>;
+ ranges;
+ cell-index = <3>;
+ clocks = <&gcc GSBI3_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ gsbi3_i2c: i2c@16280000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16280000 0x1000>;
+ pinctrl-0 = <&i2c3_default_state>;
+ pinctrl-1 = <&i2c3_sleep_state>;
+ pinctrl-names = "default", "sleep";
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI3_QUP_CLK>,
+ <&gcc GSBI3_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
};
};
+#include "qcom-msm8960-pins.dtsi"
cpus {
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_PPI 9 0xf04>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
CPU0: cpu@0 {
compatible = "qcom,krait";
pmu {
compatible = "qcom,krait-pmu";
- interrupts = <GIC_PPI 7 0xf04>;
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
rpm: remoteproc {
reg = <0xf9011000 0x1000>;
};
- saw_l2: power-controller@f9012000 {
- compatible = "qcom,saw2";
+ saw_l2: power-manager@f9012000 {
+ compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2";
reg = <0xf9012000 0x1000>;
- regulator;
};
watchdog@f9017000 {
reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
};
- saw0: power-controller@f9089000 {
+ saw0: power-manager@f9089000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
};
reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
};
- saw1: power-controller@f9099000 {
+ saw1: power-manager@f9099000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
};
reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
};
- saw2: power-controller@f90a9000 {
+ saw2: power-manager@f90a9000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
};
reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
};
- saw3: power-controller@f90b9000 {
+ saw3: power-manager@f90b9000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
};
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9923000 0x1000>;
- interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9925000 0x1000>;
- interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9968000 0x1000>;
- interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
qfprom: qfprom@fc4bc000 {
compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
- reg = <0xfc4bc000 0x1000>;
+ reg = <0xfc4bc000 0x2100>;
#address-cells = <1>;
#size-cells = <1>;
timer {
compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 2 0xf08>,
- <GIC_PPI 3 0xf08>,
- <GIC_PPI 4 0xf08>,
- <GIC_PPI 1 0xf08>;
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
};
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 51 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 10 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <&pdc 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_GDSC>;
frame@17821000 {
frame-number = <0>;
- interrupts = <GIC_SPI 7 0x4>,
- <GIC_SPI 6 0x4>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17821000 0x1000>,
<0x17822000 0x1000>;
};
frame@17823000 {
frame-number = <1>;
- interrupts = <GIC_SPI 8 0x4>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17823000 0x1000>;
status = "disabled";
};
frame@17824000 {
frame-number = <2>;
- interrupts = <GIC_SPI 9 0x4>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17824000 0x1000>;
status = "disabled";
};
frame@17825000 {
frame-number = <3>;
- interrupts = <GIC_SPI 10 0x4>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17825000 0x1000>;
status = "disabled";
};
frame@17826000 {
frame-number = <4>;
- interrupts = <GIC_SPI 11 0x4>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17826000 0x1000>;
status = "disabled";
};
frame@17827000 {
frame-number = <5>;
- interrupts = <GIC_SPI 12 0x4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17827000 0x1000>;
status = "disabled";
};
frame@17828000 {
frame-number = <6>;
- interrupts = <GIC_SPI 13 0x4>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17828000 0x1000>;
status = "disabled";
};
frame@17829000 {
frame-number = <7>;
- interrupts = <GIC_SPI 14 0x4>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17829000 0x1000>;
status = "disabled";
};
clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_USB30_MSTR_AXI_CLK>,
- <&gcc GCC_USB30_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_SLEEP_CLK>;
- clock-names = "cfg_noc", "core", "iface", "mock_utmi",
- "sleep";
+ <&gcc GCC_USB30_SLEEP_CLK>,
+ <&gcc GCC_USB30_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "sleep",
+ "mock_utmi";
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 76 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 19 IRQ_TYPE_EDGE_BOTH>,
<&pdc 18 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 19 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_GDSC>;
frame@17821000 {
frame-number = <0>;
- interrupts = <GIC_SPI 7 0x4>,
- <GIC_SPI 6 0x4>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17821000 0x1000>,
<0x17822000 0x1000>;
};
frame@17823000 {
frame-number = <1>;
- interrupts = <GIC_SPI 8 0x4>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17823000 0x1000>;
status = "disabled";
};
frame@17824000 {
frame-number = <2>;
- interrupts = <GIC_SPI 9 0x4>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17824000 0x1000>;
status = "disabled";
};
frame@17825000 {
frame-number = <3>;
- interrupts = <GIC_SPI 10 0x4>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17825000 0x1000>;
status = "disabled";
};
frame@17826000 {
frame-number = <4>;
- interrupts = <GIC_SPI 11 0x4>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17826000 0x1000>;
status = "disabled";
};
frame@17827000 {
frame-number = <5>;
- interrupts = <GIC_SPI 12 0x4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17827000 0x1000>;
status = "disabled";
};
frame@17828000 {
frame-number = <6>;
- interrupts = <GIC_SPI 13 0x4>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17828000 0x1000>;
status = "disabled";
};
frame@17829000 {
frame-number = <7>;
- interrupts = <GIC_SPI 14 0x4>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17829000 0x1000>;
status = "disabled";
};
timer {
compatible = "arm,armv7-timer";
- interrupts = <1 13 0xf08>,
- <1 12 0xf08>,
- <1 10 0xf08>,
- <1 11 0xf08>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
};
status = "okay";
};
+&extal1_clk {
+ clock-frequency = <26000000>;
+};
+
+&extal2_clk {
+ clock-frequency = <48000000>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
&pfc {
scifa0_pins: scifa0 {
groups = "scifa0_data";
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <32768>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
};
extal1_clk: extal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <25000000>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
};
extal2_clk: extal2 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <48000000>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
};
fsiack_clk: fsiack {
compatible = "fixed-clock";
clock-div = <2>;
clock-mult = <1>;
};
+ cp_clk: cp {
+ compatible = "fixed-factor-clock";
+ clocks = <&main_div2_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
pll0_div2_clk: pll0_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
- clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
- <&main_div2_clk>,
- <&cpg_clocks R8A73A4_CLK_HP>,
+ clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
+ <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
<&cpg_clocks R8A73A4_CLK_HP>;
#clock-cells = <1>;
clock-indices = <
mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
- clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
+ clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
#clock-cells = <1>;
clock-indices = <
R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
clock-names = "fck";
power-domains = <&pd_a4r>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
clock-names = "fck";
power-domains = <&pd_a4r>;
reg = <0xffd80000 0x30>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
reg = <0xffd81000 0x30>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
reg = <0xffd90000 0x1000>, /* SRU */
<0xffd91000 0x240>, /* SSI */
<0xfffe0000 0x24>; /* ADG */
+ reg-names = "sru", "ssi", "adg";
+
clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
<&mstp3_clks R8A7778_CLK_SSI7>,
<&mstp3_clks R8A7778_CLK_SSI6>,
reg = <0xffd80000 0x30>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck";
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
reg = <0xffd81000 0x30>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
clock-names = "fck";
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
clock-names = "fck";
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
regulator-boot-on;
};
+ hdmi-connnector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_connector_out>;
+ };
+ };
+ };
+
/*
* This is a vbus-supply, which also supplies the GL852G usb hub,
* thus has to be always-on
cpu-supply = <&vdd_arm>;
};
+&display_subsystem {
+ status = "okay";
+};
+
&emmc {
bus-width = <8>;
vmmc-supply = <&vcc_io>;
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_connector_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
&mdio {
phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
&usb2phy_otg {
status = "okay";
};
+
+&vop {
+ status = "okay";
+};
};
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ status = "disabled";
+ };
+
gpu_opp_table: opp-table-1 {
compatible = "operating-points-v2";
};
};
+ vop: vop@1010e000 {
+ compatible = "rockchip,rk3126-vop";
+ reg = <0x1010e000 0x300>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>,
+ <&cru HCLK_LCDC0>;
+ clock-names = "aclk_vop", "dclk_vop",
+ "hclk_vop";
+ resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>,
+ <&cru SRST_VOP_D>;
+ reset-names = "axi", "ahb",
+ "dclk";
+ power-domains = <&power RK3128_PD_VIO>;
+ status = "disabled";
+
+ vop_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vop_out_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hdmi_in_vop>;
+ };
+ };
+ };
+
qos_gpu: qos@1012d000 {
compatible = "rockchip,rk3128-qos", "syscon";
reg = <0x1012d000 0x20>;
};
};
+ hdmi: hdmi@20034000 {
+ compatible = "rockchip,rk3128-inno-hdmi";
+ reg = <0x20034000 0x4000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>;
+ clock-names = "pclk", "ref";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
+ power-domains = <&power RK3128_PD_VIO>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+ hdmi_in_vop: endpoint {
+ remote-endpoint = <&vop_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
timer0: timer@20044000 {
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044000 0x20>;
status = "disabled";
ports {
- hdmi_in: port {
- #address-cells = <1>;
- #size-cells = <0>;
- hdmi_in_vop: endpoint@0 {
- reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
+ hdmi_in_vop: endpoint {
remote-endpoint = <&vop_out_hdmi>;
};
};
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
};
};
compatible = "rockchip,rk3288-dw-hdmi";
reg = <0x0 0xff980000 0x0 0x20000>;
reg-io-width = <4>;
- #sound-dai-cells = <0>;
- rockchip,grf = <&grf>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
clock-names = "iahb", "isfr", "cec";
power-domains = <&power RK3288_PD_VIO>;
+ rockchip,grf = <&grf>;
+ #sound-dai-cells = <0>;
status = "disabled";
ports {
- hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+
hdmi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_hdmi>;
};
+
hdmi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_hdmi>;
};
};
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
};
};
aliases {
ethernet0 = &gmac;
mmc0 = &emmc;
+ mmc1 = &sdio;
+ mmc2 = &sdmmc;
};
chosen {
pmuio1-supply = <&vcc3v3_sys>;
vccio1-supply = <&vcc_1v8>;
vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_1v8>;
+ vccio3-supply = <&vcc3v3_sd>;
vccio4-supply = <&vcc_dovdd>;
vccio5-supply = <&vcc_1v8>;
vccio6-supply = <&vcc_1v8>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
- max-frequency = <100000000>;
+ max-frequency = <50000000>;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
rockchip,default-sample-phase = <90>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sys>;
+ sd-uhs-sdr50;
+ vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x40000000>;
+ reg = <0x40000000 0x3fc00000>;
};
};
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x80000000>;
+ reg = <0x40000000 0x7fc00000>;
};
};
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x80000000>;
+ reg = <0x40000000 0x7fc00000>;
};
/* bootargs are passed in by bootloader */
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x80000000>;
+ reg = <0x40000000 0x7fc00000>;
};
aliases {
status = "okay";
};
+&i2c_1 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <400000>;
+ pinctrl-0 = <&i2c1_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ accelerometer@19 {
+ compatible = "st,lsm330dlc-accel";
+ reg = <0x19>;
+ interrupt-parent = <&gpx0>;
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-0 = <&accelerometer_irq>;
+ pinctrl-names = "default";
+ mount-matrix = "1", "0", "0",
+ "0", "-1", "0",
+ "0", "0", "-1";
+ };
+
+ gyro@6b {
+ compatible = "st,lsm330dlc-gyro";
+ reg = <0x6b>;
+ interrupt-parent = <&gpx0>;
+ interrupts = <6 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-0 = <&gyro_data_enable &gyro_irq>;
+ pinctrl-names = "default";
+ mount-matrix = "1", "0", "0",
+ "0", "-1", "0",
+ "0", "0", "-1";
+ };
+};
+
&i2c_3 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-slave-addr = <0x10>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
+ gyro_data_enable: gyro-data-enable-pins {
+ samsung,pins = "gpl2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
uart_sel: uart-sel-pins {
samsung,pins = "gpl2-7";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
};
+ accelerometer_irq: accelerometer-irq-pins {
+ samsung,pins = "gpx0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
stmpe_adc_irq: stmpe-adc-irq-pins {
samsung,pins = "gpx0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
+ gyro_irq: gyro-irq-pins {
+ samsung,pins = "gpx0-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
max77686_irq: max77686-irq-pins {
samsung,pins = "gpx0-7";
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
aliases {
mmc0 = &mmc_0;
+ mmc1 = &mmc_1;
mmc2 = &mmc_2;
};
memory@20000000 {
device_type = "memory";
- reg = <0x20000000 0xc0000000>;
+ reg = <0x20000000 0xbfa00000>;
};
firmware@2073000 {
linux,code = <KEY_VOLUMEDOWN>;
};
};
+
+ mmc1_pwrseq: pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpy7 7 GPIO_ACTIVE_LOW>;
+ clocks = <&s2mps11_osc S2MPS11_CLK_BT>;
+ clock-names = "ext_clock";
+ };
};
&cci {
vqmmc-supply = <&ldo3_reg>;
};
+/* WiFi */
+&mmc_1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ card-detect-delay = <200>;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&mmc1_pwrseq>;
+ non-removable;
+ pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>,
+ <&sd1_bus4>, <&wifi_en>;
+ pinctrl-names = "default";
+ vqmmc-supply = <&ldo2_reg>;
+ samsung,dw-mshc-ciu-div = <1>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ samsung,dw-mshc-sdr-timing = <0 1>;
+ status = "okay";
+};
+
/* External sdcard */
&mmc_2 {
status = "okay";
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
+
+ wifi_en: wifi-en-pins {
+ samsung,pins = "gpy7-7";
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
};
&rtc {
reg = <0>;
spi-max-frequency = <3125000>;
google,has-vbc-nvram;
+ wakeup-source;
controller-data {
samsung,spi-feedback-delay = <1>;
thermal-zones {
cpu0_thermal: cpu0-thermal {
thermal-sensors = <&tmu_cpu0>;
- polling-delay-passive = <250>;
+ polling-delay-passive = <0>;
polling-delay = <0>;
trips {
cpu0_alert0: cpu-alert-0 {
hysteresis = <0>; /* millicelsius */
type = "critical";
};
- /*
- * Exynos542x supports only 4 trip-points
- * so for these polling mode is required.
- * Start polling at temperature level of last
- * interrupt-driven trip: cpu0_alert2
- */
cpu0_alert3: cpu-alert-3 {
temperature = <70000>; /* millicelsius */
hysteresis = <10000>; /* millicelsius */
};
cpu1_thermal: cpu1-thermal {
thermal-sensors = <&tmu_cpu1>;
- polling-delay-passive = <250>;
+ polling-delay-passive = <0>;
polling-delay = <0>;
trips {
cpu1_alert0: cpu-alert-0 {
};
cpu2_thermal: cpu2-thermal {
thermal-sensors = <&tmu_cpu2>;
- polling-delay-passive = <250>;
+ polling-delay-passive = <0>;
polling-delay = <0>;
trips {
cpu2_alert0: cpu-alert-0 {
};
cpu3_thermal: cpu3-thermal {
thermal-sensors = <&tmu_cpu3>;
- polling-delay-passive = <250>;
+ polling-delay-passive = <0>;
polling-delay = <0>;
trips {
cpu3_alert0: cpu-alert-0 {
};
gpu_thermal: gpu-thermal {
thermal-sensors = <&tmu_gpu>;
- polling-delay-passive = <250>;
+ polling-delay-passive = <0>;
polling-delay = <0>;
trips {
gpu_alert0: gpu-alert-0 {
reg = <0>;
spi-max-frequency = <3125000>;
google,has-vbc-nvram;
+ wakeup-source;
controller-data {
samsung,spi-feedback-delay = <1>;
serial0 {
pinctrl_serial0: serial0-0 {
st,pins {
- tx = <&pio17 0 ALT1 OUT>;
- rx = <&pio17 1 ALT1 IN>;
+ tx = <&pio17 0 ALT1 OUT>;
+ rx = <&pio17 1 ALT1 IN>;
};
};
pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl {
st,pins {
- tx = <&pio17 0 ALT1 OUT>;
- rx = <&pio17 1 ALT1 IN>;
+ tx = <&pio17 0 ALT1 OUT>;
+ rx = <&pio17 1 ALT1 IN>;
cts = <&pio17 2 ALT1 IN>;
rts = <&pio17 3 ALT1 OUT>;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ */
+
+#include "stm32f769-disco.dts"
+
+&panel0 {
+ compatible = "frida,frd400b25025", "novatek,nt35510";
+ vddi-supply = <&vcc_3v3>;
+ vdd-supply = <&vcc_3v3>;
+ /delete-property/power-supply;
+};
*/
/dts-v1/;
-#include "stm32f746.dtsi"
+#include "stm32f769.dtsi"
#include "stm32f769-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
reg = <0xC0000000 0x1000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,dma {
+ compatible = "shared-dma-pool";
+ linux,dma-default;
+ no-map;
+ size = <0x100000>;
+ };
+ };
+
aliases {
serial0 = &usart1;
};
clock-names = "main_clk";
};
- mmc_vcard: mmc_vcard {
+ vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
+ regulator-name = "vcc_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
clock-frequency = <25000000>;
};
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <<dc_out_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_panel_in>;
+ };
+ };
+ };
+
+ panel0: panel@0 {
+ compatible = "orisetech,otm8009a";
+ reg = <0>; /* dsi virtual channel (0..3) */
+ reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>;
+ power-supply = <&vcc_3v3>;
+ status = "okay";
+
+ port {
+ dsi_panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
&i2c1 {
pinctrl-0 = <&i2c1_pins_b>;
pinctrl-names = "default";
status = "okay";
};
+<dc {
+ status = "okay";
+
+ port {
+ ltdc_out_dsi: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
+
&rtc {
status = "okay";
};
&sdio2 {
status = "okay";
- vmmc-supply = <&mmc_vcard>;
+ vmmc-supply = <&vcc_3v3>;
cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
broken-cd;
pinctrl-names = "default", "opendrain", "sleep";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ */
+
+#include "stm32f746.dtsi"
+
+/ {
+ soc {
+ dsi: dsi@40016c00 {
+ compatible = "st,stm32-dsi";
+ reg = <0x40016c00 0x800>;
+ clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
+ clock-names = "pclk", "ref";
+ resets = <&rcc STM32F7_APB2_RESET(DSI)>;
+ reset-names = "apb";
+ status = "disabled";
+ };
+ };
+};
status = "disabled";
};
+ crc1: crc@58009000 {
+ compatible = "st,stm32f7-crc";
+ reg = <0x58009000 0x400>;
+ clocks = <&rcc CRC1>;
+ status = "disabled";
+ };
+
usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
};
};
+&crc1 {
+ status = "okay";
+};
+
+&cryp {
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
dsi: dsi@5a000000 {
compatible = "st,stm32-dsi";
reg = <0x5a000000 0x800>;
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>;
clock-names = "pclk", "ref", "px_clk";
phy-dsi-supply = <®18>;
resets = <&rcc DSI_R>;
};
&dsi {
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
&dsi {
phy-dsi-supply = <&scmi_reg18>;
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
};
&dsi {
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
&dsi {
phy-dsi-supply = <&scmi_reg18>;
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
compatible = "ti,lmp92064";
reg = <0>;
- reset-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
shunt-resistor-micro-ohms = <15000>;
spi-max-frequency = <5000000>;
vdd-supply = <®_pb_3v3>;
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_c>;
- cs-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpiof 12 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
status = "okay";
};
interrupt-parent = <&gpioa>;
interrupts = <6 IRQ_TYPE_EDGE_RISING>;
+ /* Reduce RGMII EMI emissions by reducing drive strength */
+ microchip,hi-drive-strength-microamp = <2000>;
+ microchip,lo-drive-strength-microamp = <8000>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40000 0x1000>;
cap-sd-highspeed;
cap-mmc-highspeed;
- interrupts = <16>;
+ interrupts = <16>, <17>;
dmas = <&edma0 16 0>, <&edma0 17 0>;
dma-names = "rx", "tx";
clocks = <&psc0 5>;
reg = <0x21b000 0x1000>;
cap-sd-highspeed;
cap-mmc-highspeed;
- interrupts = <72>;
+ interrupts = <72>, <73>;
dmas = <&edma1 28 0>, <&edma1 29 0>;
dma-names = "rx", "tx";
clocks = <&psc1 18>;
/*
* Device Tree Source for Keystone 2 clock tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {
/*
* Keystone 2 Edison SoC specific device tree
*
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {
/*
* Keystone 2 Edison EVM device tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/*
* Device Tree Source for Keystone 2 Edison Netcp driver
*
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@2a40000 {
/*
* Keystone 2 Edison soc device tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/reset/ti-syscon.h>
/*
* Device Tree Source for K2G EVM
*
- * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/*
* Device Tree Source for K2G Industrial Communication Engine EVM
*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/*
* Device Tree Source for K2G Netcp driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@4020000 {
/*
* Device Tree Source for K2G SOC
*
- * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/*
* Keystone 2 Kepler/Hawking SoC clock nodes
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {
/*
* Keystone 2 Kepler/Hawking EVM device tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/*
* Device Tree Source for Keystone 2 Hawking Netcp driver
*
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@2a40000 {
/*
* Keystone 2 Kepler/Hawking soc specific device tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/reset/ti-syscon.h>
/*
* Keystone 2 lamarr SoC clock nodes
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {
/*
* Keystone 2 Lamarr EVM device tree
*
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/*
* Device Tree Source for Keystone 2 Lamarr Netcp driver
*
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@2a40000 {
/*
* Keystone 2 Lamarr SoC specific device tree
*
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/reset/ti-syscon.h>
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/*
* VScom OnRISC
- * http://www.vscom.de
+ * https://www.vscom.de
*/
/dts-v1/;
/*
* VScom OnRISC
- * http://www.vscom.de
+ * https://www.vscom.de
*/
/dts-v1/;
/*
* VScom OnRISC
- * http://www.vscom.de
+ * https://www.vscom.de
*/
/dts-v1/;
/*
* VScom OnRISC
- * http://www.vscom.de
+ * https://www.vscom.de
*/
/*#include "am33xx.dtsi"*/
/*
* VScom OnRISC
- * http://www.vscom.de
+ * https://www.vscom.de
*/
#include "am33xx.dtsi"
/*
* am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION
*
- * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
+ * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz
*/
#include "am335x-igep0033.dtsi"
* For details, see linux-omap mailing list May 2015 thread
* [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
* In particular, messages:
- * http://www.spinics.net/lists/linux-omap/msg118585.html
- * http://www.spinics.net/lists/linux-omap/msg118615.html
+ * https://www.spinics.net/lists/linux-omap/msg118585.html
+ * https://www.spinics.net/lists/linux-omap/msg118615.html
*
* You can override this later with
* &tps { /delete-property/ ti,pmic-shutdown-controller; }
/*
* am335x-cm-t335.dts - Device Tree file for Compulab CM-T335
*
- * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/
+ * Copyright (C) 2014 - 2015 CompuLab Ltd. - https://www.compulab.co.il/
*/
/dts-v1/;
/*
* AM335x Starter Kit
- * http://www.ti.com/tool/tmdssk3358
+ * https://www.ti.com/tool/tmdssk3358
*/
/dts-v1/;
* For details, see linux-omap mailing list May 2015 thread
* [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
* In particular, messages:
- * http://www.spinics.net/lists/linux-omap/msg118585.html
- * http://www.spinics.net/lists/linux-omap/msg118615.html
+ * https://www.spinics.net/lists/linux-omap/msg118585.html
+ * https://www.spinics.net/lists/linux-omap/msg118615.html
*
* You can override this later with
* &tps { /delete-property/ ti,pmic-shutdown-controller; }
/*
* AM335x ICE V2 board
- * http://www.ti.com/tool/tmdsice3359
+ * https://www.ti.com/tool/tmdsice3359
*/
/dts-v1/;
/*
* am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
*
- * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
+ * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz
*/
/dts-v1/;
/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
/* Based on code by myc_c335x.dts, MYiRtech.com */
-/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */
+/* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */
/dts-v1/;
// SPDX-License-Identifier: GPL-2.0-or-later
/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
/* Based on code by myd_c335x.dts, MYiRtech.com */
-/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */
+/* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */
/dts-v1/;
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
+ * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
*/
/dts-v1/;
/*
* VScom OnRISC
- * http://www.vscom.de
+ * https://www.vscom.de
*/
/dts-v1/;
/*
* VScom OnRISC
- * http://www.vscom.de
+ * https://www.vscom.de
*/
/dts-v1/;
/*
* VScom OnRISC
- * http://www.vscom.de
+ * https://www.vscom.de
*/
/dts-v1/;
*
* EETS GmbH PDU001 board device tree file
*
- * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+ * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
*
* Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2021 Sancloud Ltd
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2021 SanCloud Ltd
*/
/dts-v1/;
/*
* am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335
*
- * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/
+ * Copyright (C) 2014 - 2015 CompuLab Ltd. - https://www.compulab.co.il/
*/
#include "am335x-cm-t335.dts"
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/
+ * Copyright (C) 2015 Toby Churchill - https://www.toby-churchill.com/
+ * url above is defunct
*/
/dts-v1/;
compatible = "ti,clksel";
reg = <0x664>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- ehrpwm0_tbclk: clock-ehrpwm0-tbclk {
+ ehrpwm0_tbclk: clock-ehrpwm0-tbclk@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "ehrpwm0_tbclk";
clocks = <&l4ls_gclk>;
- ti,bit-shift = <0>;
};
- ehrpwm1_tbclk: clock-ehrpwm1-tbclk {
+ ehrpwm1_tbclk: clock-ehrpwm1-tbclk@1 {
+ reg = <1>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "ehrpwm1_tbclk";
clocks = <&l4ls_gclk>;
- ti,bit-shift = <1>;
};
- ehrpwm2_tbclk: clock-ehrpwm2-tbclk {
+ ehrpwm2_tbclk: clock-ehrpwm2-tbclk@2 {
+ reg = <2>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "ehrpwm2_tbclk";
clocks = <&l4ls_gclk>;
- ti,bit-shift = <2>;
};
};
};
compatible = "ti,clksel";
reg = <0x52c>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
+ gfx_fclk_clksel_ck: clock-gfx-fclk-clksel@1 {
+ reg = <1>;
#clock-cells = <0>;
compatible = "ti,mux-clock";
clock-output-names = "gfx_fclk_clksel_ck";
clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
- ti,bit-shift = <1>;
};
- gfx_fck_div_ck: clock-gfx-fck-div {
+ gfx_fck_div_ck: clock-gfx-fck-div@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "gfx_fck_div_ck";
compatible = "ti,clksel";
reg = <0x700>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- sysclkout_pre_ck: clock-sysclkout-pre {
+ sysclkout_pre_ck: clock-sysclkout-pre@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,mux-clock";
clock-output-names = "sysclkout_pre_ck";
clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
};
- clkout2_div_ck: clock-clkout2-div {
+ clkout2_div_ck: clock-clkout2-div@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "clkout2_div_ck";
clocks = <&sysclkout_pre_ck>;
- ti,bit-shift = <3>;
ti,max-div = <8>;
};
- clkout2_ck: clock-clkout2 {
+ clkout2_ck: clock-clkout2@7 {
+ reg = <7>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "clkout2_ck";
clocks = <&clkout2_div_ck>;
- ti,bit-shift = <7>;
};
};
};
#size-cells = <1>;
ranges = <0 0x56000000 0x1000000>;
- /*
- * Closed source PowerVR driver, no child device
- * binding or driver in mainline
- */
+ gpu@0 {
+ compatible = "ti,omap3630-gpu", "img,powervr-sgx530";
+ reg = <0x0 0x10000>; /* 64kB */
+ interrupts = <37>;
+ };
};
};
};
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x50000000 0x4000>;
+ ranges = <0 0x50000000 0x10000>;
- /*
- * Closed source PowerVR driver, no child device
- * binding or driver in mainline
- */
+ gpu@0 {
+ compatible = "ti,omap3430-gpu", "img,powervr-sgx530";
+ reg = <0x0 0x10000>; /* 64kB */
+ interrupts = <21>;
+ };
};
};
};
compatible = "ti,clksel";
reg = <0xa10>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- ipss_ick: clock-ipss-ick {
+ ipss_ick: clock-ipss-ick@4 {
+ reg = <4>;
#clock-cells = <0>;
compatible = "ti,am35xx-interface-clock";
clock-output-names = "ipss_ick";
clocks = <&core_l3_ick>;
- ti,bit-shift = <4>;
};
- uart4_ick_am35xx: clock-uart4-ick-am35xx {
+ uart4_ick_am35xx: clock-uart4-ick-am35xx@23 {
+ reg = <23>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "uart4_ick_am35xx";
clocks = <&core_l4_ick>;
- ti,bit-shift = <23>;
};
};
compatible = "ti,clksel";
reg = <0xa00>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- uart4_fck_am35xx: clock-uart4-fck-am35xx {
+ uart4_fck_am35xx: clock-uart4-fck-am35xx@23 {
+ reg = <23>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "uart4_fck_am35xx";
clocks = <&core_48m_fck>;
- ti,bit-shift = <23>;
};
};
};
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x1000000>;
+
+ gpu@0 {
+ compatible = "ti,omap3630-gpu", "img,powervr-sgx530";
+ reg = <0x0 0x10000>; /* 64kB */
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
};
};
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/
+ * Copyright (C) 2015 CompuLab, Ltd. - https://www.compulab.co.il/
*/
/dts-v1/;
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/
+ * Copyright (C) 2015 CompuLab, Ltd. - https://www.compulab.co.il/
*/
#include "am437x-cm-t43.dts"
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/*
* Support for CompuLab CL-SOM-AM57x System-on-Module
*
- * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
+ * Copyright (C) 2015 CompuLab Ltd. - https://www.compulab.co.il/
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*/
/*
* Support for CompuLab SBC-AM57x single board computer
*
- * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
+ * Copyright (C) 2015 CompuLab Ltd. - https://www.compulab.co.il/
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*/
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/
+ * Copyright (C) 2015 CompuLab, Ltd. - https://www.compulab.co.il/
*/
/ {
};
};
- phy_gmii_sel: phy-gmii-sel {
+ phy_gmii_sel: phy-gmii-sel@554 {
compatible = "ti,dra7xx-phy-gmii-sel";
reg = <0x554 0x4>;
#phy-cells = <1>;
};
};
- abb_mpu: regulator-abb-mpu {
+ abb_mpu: regulator-abb-mpu@4ae07ddc {
compatible = "ti,abb-v3";
regulator-name = "abb_mpu";
#address-cells = <0>;
>;
};
- abb_ivahd: regulator-abb-ivahd {
+ abb_ivahd: regulator-abb-ivahd@4ae07e34 {
compatible = "ti,abb-v3";
regulator-name = "abb_ivahd";
#address-cells = <0>;
>;
};
- abb_dspeve: regulator-abb-dspeve {
+ abb_dspeve: regulator-abb-dspeve@4ae07e30 {
compatible = "ti,abb-v3";
regulator-name = "abb_dspeve";
#address-cells = <0>;
>;
};
- abb_gpu: regulator-abb-gpu {
+ abb_gpu: regulator-abb-gpu@4ae07de4 {
compatible = "ti,abb-v3";
regulator-name = "abb_gpu";
#address-cells = <0>;
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x2000000>;
+
+ gpu@0 {
+ compatible = "ti,am5728-gpu", "img,powervr-sgx544";
+ reg = <0x0 0x10000>; /* 64kB */
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
crossbar_mpu: crossbar@4a002a48 {
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
reg = <0x0558>;
};
- sys_32k_ck: clock-sys-32k {
+ sys_32k_ck: clock-sys-32k@6c4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clock-output-names = "sys_32k_ck";
compatible = "ti,clksel";
reg = <0xa00>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- d2d_26m_fck: clock-d2d-26m-fck {
+ d2d_26m_fck: clock-d2d-26m-fck@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "d2d_26m_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <3>;
};
- fshostusb_fck: clock-fshostusb-fck {
+ fshostusb_fck: clock-fshostusb-fck@5 {
+ reg = <5>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "fshostusb_fck";
clocks = <&core_48m_fck>;
- ti,bit-shift = <5>;
};
- ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 {
+ ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clock-output-names = "ssi_ssr_gate_fck_3430es1";
clocks = <&corex2_fck>;
- ti,bit-shift = <0>;
};
};
compatible = "ti,clksel";
reg = <0xa40>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 {
+ ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 {
+ reg = <8>;
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clock-output-names = "ssi_ssr_div_fck_3430es1";
clocks = <&corex2_fck>;
- ti,bit-shift = <8>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
- usb_l4_div_ick: clock-usb-l4-div-ick {
+ usb_l4_div_ick: clock-usb-l4-div-ick@4 {
+ reg = <4>;
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clock-output-names = "usb_l4_div_ick";
clocks = <&l4_ick>;
- ti,bit-shift = <4>;
ti,max-div = <1>;
ti,index-starts-at-one;
};
compatible = "ti,clksel";
reg = <0xa10>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 {
+ hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 {
+ reg = <4>;
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clock-output-names = "hsotgusb_ick_3430es1";
clocks = <&core_l3_ick>;
- ti,bit-shift = <4>;
};
- fac_ick: clock-fac-ick {
+ fac_ick: clock-fac-ick@8 {
+ reg = <8>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "fac_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <8>;
};
- ssi_ick: clock-ssi-ick-3430es1 {
+ ssi_ick: clock-ssi-ick-3430es1@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clock-output-names = "ssi_ick_3430es1";
clocks = <&ssi_l4_ick>;
- ti,bit-shift = <0>;
};
- usb_l4_gate_ick: clock-usb-l4-gate-ick {
+ usb_l4_gate_ick: clock-usb-l4-gate-ick@5 {
+ reg = <5>;
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clock-output-names = "usb_l4_gate_ick";
clocks = <&l4_ick>;
- ti,bit-shift = <5>;
};
};
compatible = "ti,clksel";
reg = <0xe00>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 {
+ dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "dss1_alwon_fck_3430es1";
clocks = <&dpll4_m4x2_ck>;
- ti,bit-shift = <0>;
ti,set-rate-parent;
};
};
compatible = "ti,clksel";
reg = <0xa14>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- aes1_ick: clock-aes1-ick {
+ aes1_ick: clock-aes1-ick@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "aes1_ick";
clocks = <&security_l4_ick2>;
- ti,bit-shift = <3>;
};
- rng_ick: clock-rng-ick {
+ rng_ick: clock-rng-ick@2 {
+ reg = <2>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "rng_ick";
clocks = <&security_l4_ick2>;
- ti,bit-shift = <2>;
};
- sha11_ick: clock-sha11-ick {
+ sha11_ick: clock-sha11-ick@1 {
+ reg = <1>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "sha11_ick";
clocks = <&security_l4_ick2>;
- ti,bit-shift = <1>;
};
- des1_ick: clock-des1-ick {
+ des1_ick: clock-des1-ick@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "des1_ick";
clocks = <&security_l4_ick2>;
- ti,bit-shift = <0>;
};
- pka_ick: clock-pka-ick {
+ pka_ick: clock-pka-ick@4 {
+ reg = <4>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "pka_ick";
clocks = <&security_l3_ick>;
- ti,bit-shift = <4>;
};
};
compatible = "ti,clksel";
reg = <0xf00>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- cam_mclk: clock-cam-mclk {
+ cam_mclk: clock-cam-mclk@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "cam_mclk";
clocks = <&dpll4_m5x2_ck>;
- ti,bit-shift = <0>;
ti,set-rate-parent;
};
- csi2_96m_fck: clock-csi2-96m-fck {
+ csi2_96m_fck: clock-csi2-96m-fck@1 {
+ reg = <1>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "csi2_96m_fck";
clocks = <&core_96m_fck>;
- ti,bit-shift = <1>;
};
};
compatible = "ti,clksel";
reg = <0xa10>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- icr_ick: clock-icr-ick {
+ icr_ick: clock-icr-ick@29 {
+ reg = <29>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "icr_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <29>;
};
- des2_ick: clock-des2-ick {
+ des2_ick: clock-des2-ick@26 {
+ reg = <26>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "des2_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <26>;
};
- mspro_ick: clock-mspro-ick {
+ mspro_ick: clock-mspro-ick@23 {
+ reg = <23>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mspro_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <23>;
};
- mailboxes_ick: clock-mailboxes-ick {
+ mailboxes_ick: clock-mailboxes-ick@7 {
+ reg = <7>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mailboxes_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <7>;
};
- sad2d_ick: clock-sad2d-ick {
+ sad2d_ick: clock-sad2d-ick@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "sad2d_ick";
clocks = <&l3_ick>;
- ti,bit-shift = <3>;
};
};
compatible = "ti,clksel";
reg = <0xc00>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- sr1_fck: clock-sr1-fck {
+ sr1_fck: clock-sr1-fck@6 {
+ reg = <6>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "sr1_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <6>;
};
- sr2_fck: clock-sr2-fck {
+ sr2_fck: clock-sr2-fck@7 {
+ reg = <7>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "sr2_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <7>;
};
};
compatible = "ti,clksel";
reg = <0xa00>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- modem_fck: clock-modem-fck {
+ modem_fck: clock-modem-fck@31 {
+ reg = <31>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "modem_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <31>;
};
- mspro_fck: clock-mspro-fck {
+ mspro_fck: clock-mspro-fck@23 {
+ reg = <23>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "mspro_fck";
clocks = <&core_96m_fck>;
- ti,bit-shift = <23>;
};
};
compatible = "ti,clksel";
reg = <0xa18>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #ssize-cells = <0>;
- mad2d_ick: clock-mad2d-ick {
+ mad2d_ick: clock-mad2d-ick@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mad2d_ick";
clocks = <&l3_ick>;
- ti,bit-shift = <3>;
};
};
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x50000000 0x4000>;
+ ranges = <0 0x50000000 0x10000>;
- /*
- * Closed source PowerVR driver, no child device
- * binding or driver in mainline
- */
+ gpu@0 {
+ compatible = "ti,omap3430-gpu", "img,powervr-sgx530";
+ reg = <0x0 0x10000>; /* 64kB */
+ interrupts = <21>;
+ };
};
};
compatible = "ti,clksel";
reg = <0xa18>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- usbtll_ick: clock-usbtll-ick {
+ usbtll_ick: clock-usbtll-ick@2 {
+ reg = <2>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "usbtll_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <2>;
};
};
compatible = "ti,clksel";
reg = <0xa10>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- mmchs3_ick: clock-mmchs3-ick {
+ mmchs3_ick: clock-mmchs3-ick@30 {
+ reg = <30>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mmchs3_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <30>;
};
};
compatible = "ti,clksel";
reg = <0xa00>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- mmchs3_fck: clock-mmchs3-fck {
+ mmchs3_fck: clock-mmchs3-fck@30 {
+ reg = <30>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "mmchs3_fck";
clocks = <&core_96m_fck>;
- ti,bit-shift = <30>;
};
};
compatible = "ti,clksel";
reg = <0xe00>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 {
+ dss1_alwon_fck: clock-dss1-alwon-fck-3430es2@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clock-output-names = "dss1_alwon_fck_3430es2";
clocks = <&dpll4_m4x2_ck>;
- ti,bit-shift = <0>;
ti,set-rate-parent;
};
};
compatible = "ti,clksel";
reg = <0x1000>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- uart4_fck: clock-uart4-fck {
+ uart4_fck: clock-uart4-fck@18 {
+ reg = <18>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "uart4_fck";
clocks = <&per_48m_fck>;
- ti,bit-shift = <18>;
};
};
};
compatible = "ti,clksel";
reg = <0xa00>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
+ ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clock-output-names = "ssi_ssr_gate_fck_3430es2";
clocks = <&corex2_fck>;
- ti,bit-shift = <0>;
};
};
compatible = "ti,clksel";
reg = <0xa40>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
+ ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2@8 {
+ reg = <8>;
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clock-output-names = "ssi_ssr_div_fck_3430es2";
clocks = <&corex2_fck>;
- ti,bit-shift = <8>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
};
compatible = "ti,clksel";
reg = <0xa10>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 {
+ hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2@4 {
+ reg = <4>;
#clock-cells = <0>;
compatible = "ti,omap3-hsotgusb-interface-clock";
clock-output-names = "hsotgusb_ick_3430es2";
clocks = <&core_l3_ick>;
- ti,bit-shift = <4>;
};
- ssi_ick: clock-ssi-ick-3430es2 {
+ ssi_ick: clock-ssi-ick-3430es2@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,omap3-ssi-interface-clock";
clock-output-names = "ssi_ick_3430es2";
clocks = <&ssi_l4_ick>;
- ti,bit-shift = <0>;
};
};
compatible = "ti,clksel";
reg = <0xc00>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- usim_gate_fck: clock-usim-gate-fck {
+ usim_gate_fck: clock-usim-gate-fck@9 {
+ reg = <9>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "usim_gate_fck";
clocks = <&omap_96m_fck>;
- ti,bit-shift = <9>;
};
};
compatible = "ti,clksel";
reg = <0xc40>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- usim_mux_fck: clock-usim-mux-fck {
+ usim_mux_fck: clock-usim-mux-fck@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "usim_mux_fck";
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
- ti,bit-shift = <3>;
ti,index-starts-at-one;
};
};
compatible = "ti,clksel";
reg = <0xc10>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- usim_ick: clock-usim-ick {
+ usim_ick: clock-usim-ick@9 {
+ reg = <9>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "usim_ick";
clocks = <&wkup_l4_ick>;
- ti,bit-shift = <9>;
};
};
};
#size-cells = <1>;
ranges = <0 0x50000000 0x2000000>;
- /*
- * Closed source PowerVR driver, no child device
- * binding or driver in mainline
- */
+ gpu@0 {
+ compatible = "ti,omap3630-gpu", "img,powervr-sgx530";
+ reg = <0x0 0x2000000>; /* 32MB */
+ interrupts = <21>;
+ };
};
};
compatible = "ti,clksel";
reg = <0x68>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- mcbsp5_mux_fck: clock-mcbsp5-mux-fck {
+ mcbsp5_mux_fck: clock-mcbsp5-mux-fck@4 {
+ reg = <4>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "mcbsp5_mux_fck";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <4>;
};
- mcbsp3_mux_fck: clock-mcbsp3-mux-fck {
+ mcbsp3_mux_fck: clock-mcbsp3-mux-fck@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "mcbsp3_mux_fck";
clocks = <&per_96m_fck>, <&mcbsp_clks>;
};
- mcbsp4_mux_fck: clock-mcbsp4-mux-fck {
+ mcbsp4_mux_fck: clock-mcbsp4-mux-fck@2 {
+ reg = <2>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "mcbsp4_mux_fck";
clocks = <&per_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <2>;
};
};
compatible = "ti,clksel";
reg = <0x4>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- mcbsp1_mux_fck: clock-mcbsp1-mux-fck {
+ mcbsp1_mux_fck: clock-mcbsp1-mux-fck@2 {
+ reg = <2>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "mcbsp1_mux_fck";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <2>;
};
- mcbsp2_mux_fck: clock-mcbsp2-mux-fck {
+ mcbsp2_mux_fck: clock-mcbsp2-mux-fck@6 {
+ reg = <6>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "mcbsp2_mux_fck";
clocks = <&per_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <6>;
};
};
compatible = "ti,clksel";
reg = <0x1140>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- dpll3_m3_ck: clock-dpll3-m3 {
+ dpll3_m3_ck: clock-dpll3-m3@16 {
+ reg = <16>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "dpll3_m3_ck";
clocks = <&dpll3_ck>;
- ti,bit-shift = <16>;
ti,max-div = <31>;
ti,index-starts-at-one;
};
- dpll4_m6_ck: clock-dpll4-m6 {
+ dpll4_m6_ck: clock-dpll4-m6@24 {
+ reg = <24>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "dpll4_m6_ck";
clocks = <&dpll4_ck>;
- ti,bit-shift = <24>;
ti,max-div = <63>;
ti,index-starts-at-one;
};
- emu_src_mux_ck: clock-emu-src-mux {
+ emu_src_mux_ck: clock-emu-src-mux@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,mux-clock";
clock-output-names = "emu_src_mux_ck";
clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
};
- pclk_fck: clock-pclk-fck {
+ pclk_fck: clock-pclk-fck@8 {
+ reg = <8>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "pclk_fck";
clocks = <&emu_src_ck>;
- ti,bit-shift = <8>;
ti,max-div = <7>;
ti,index-starts-at-one;
};
- pclkx2_fck: clock-pclkx2-fck {
+ pclkx2_fck: clock-pclkx2-fck@6 {
+ reg = <6>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "pclkx2_fck";
clocks = <&emu_src_ck>;
- ti,bit-shift = <6>;
ti,max-div = <3>;
ti,index-starts-at-one;
};
- atclk_fck: clock-atclk-fck {
+ atclk_fck: clock-atclk-fck@4 {
+ reg = <4>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "atclk_fck";
clocks = <&emu_src_ck>;
- ti,bit-shift = <4>;
ti,max-div = <3>;
ti,index-starts-at-one;
};
- traceclk_src_fck: clock-traceclk-src-fck {
+ traceclk_src_fck: clock-traceclk-src-fck@2 {
+ reg = <2>;
#clock-cells = <0>;
compatible = "ti,mux-clock";
clock-output-names = "traceclk_src_fck";
clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
- ti,bit-shift = <2>;
};
- traceclk_fck: clock-traceclk-fck {
+ traceclk_fck: clock-traceclk-fck@11 {
+ reg = <11>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "traceclk_fck";
clocks = <&traceclk_src_fck>;
- ti,bit-shift = <11>;
ti,max-div = <7>;
ti,index-starts-at-one;
};
compatible = "ti,clksel";
reg = <0xd40>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- dpll3_m2_ck: clock-dpll3-m2 {
+ dpll3_m2_ck: clock-dpll3-m2@27 {
+ reg = <27>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "dpll3_m2_ck";
clocks = <&dpll3_ck>;
- ti,bit-shift = <27>;
ti,max-div = <31>;
ti,index-starts-at-one;
};
- omap_96m_fck: clock-omap-96m-fck {
+ omap_96m_fck: clock-omap-96m-fck@6 {
+ reg = <6>;
#clock-cells = <0>;
compatible = "ti,mux-clock";
clock-output-names = "omap_96m_fck";
clocks = <&cm_96m_fck>, <&sys_ck>;
- ti,bit-shift = <6>;
};
- omap_54m_fck: clock-omap-54m-fck {
+ omap_54m_fck: clock-omap-54m-fck@5 {
+ reg = <5>;
#clock-cells = <0>;
compatible = "ti,mux-clock";
clock-output-names = "omap_54m_fck";
clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
- ti,bit-shift = <5>;
};
- omap_48m_fck: clock-omap-48m-fck {
+ omap_48m_fck: clock-omap-48m-fck@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,mux-clock";
clock-output-names = "omap_48m_fck";
clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
- ti,bit-shift = <3>;
};
};
compatible = "ti,clksel";
reg = <0xe40>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- dpll4_m3_ck: clock-dpll4-m3 {
+ dpll4_m3_ck: clock-dpll4-m3@8 {
+ reg = <8>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "dpll4_m3_ck";
clocks = <&dpll4_ck>;
- ti,bit-shift = <8>;
ti,max-div = <32>;
ti,index-starts-at-one;
};
- dpll4_m4_ck: clock-dpll4-m4 {
+ dpll4_m4_ck: clock-dpll4-m4@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "dpll4_m4_ck";
compatible = "ti,clksel";
reg = <0xd70>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- clkout2_src_gate_ck: clock-clkout2-src-gate {
+ clkout2_src_gate_ck: clock-clkout2-src-gate@7 {
+ reg = <7>;
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clock-output-names = "clkout2_src_gate_ck";
clocks = <&core_ck>;
- ti,bit-shift = <7>;
};
- clkout2_src_mux_ck: clock-clkout2-src-mux {
+ clkout2_src_mux_ck: clock-clkout2-src-mux@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "clkout2_src_mux_ck";
clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
};
- sys_clkout2: clock-sys-clkout2 {
+ sys_clkout2: clock-sys-clkout2@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "sys_clkout2";
clocks = <&clkout2_src_ck>;
- ti,bit-shift = <3>;
ti,max-div = <64>;
ti,index-power-of-two;
};
compatible = "ti,clksel";
reg = <0xa40>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- l3_ick: clock-l3-ick {
+ l3_ick: clock-l3-ick@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "l3_ick";
ti,index-starts-at-one;
};
- l4_ick: clock-l4-ick {
+ l4_ick: clock-l4-ick@2 {
+ reg = <2>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "l4_ick";
clocks = <&l3_ick>;
- ti,bit-shift = <2>;
ti,max-div = <3>;
ti,index-starts-at-one;
};
- gpt10_mux_fck: clock-gpt10-mux-fck {
+ gpt10_mux_fck: clock-gpt10-mux-fck@6 {
+ reg = <6>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt10_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <6>;
};
- gpt11_mux_fck: clock-gpt11-mux-fck {
+ gpt11_mux_fck: clock-gpt11-mux-fck@7 {
+ reg = <7>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt11_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <7>;
};
};
compatible = "ti,clksel";
reg = <0xc40>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- rm_ick: clock-rm-ick {
+ rm_ick: clock-rm-ick@1 {
+ reg = <1>;
#clock-cells = <0>;
compatible = "ti,divider-clock";
clock-output-names = "rm_ick";
clocks = <&l4_ick>;
- ti,bit-shift = <1>;
ti,max-div = <3>;
ti,index-starts-at-one;
};
- gpt1_mux_fck: clock-gpt1-mux-fck {
+ gpt1_mux_fck: clock-gpt1-mux-fck@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt1_mux_fck";
compatible = "ti,clksel";
reg = <0xa00>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- gpt10_gate_fck: clock-gpt10-gate-fck {
+ gpt10_gate_fck: clock-gpt10-gate-fck@11 {
+ reg = <11>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "gpt10_gate_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <11>;
};
- gpt11_gate_fck: clock-gpt11-gate-fck {
+ gpt11_gate_fck: clock-gpt11-gate-fck@12 {
+ reg = <12>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "gpt11_gate_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <12>;
};
- mmchs2_fck: clock-mmchs2-fck {
+ mmchs2_fck: clock-mmchs2-fck@25 {
+ reg = <25>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "mmchs2_fck";
clocks = <&core_96m_fck>;
- ti,bit-shift = <25>;
};
- mmchs1_fck: clock-mmchs1-fck {
+ mmchs1_fck: clock-mmchs1-fck@24 {
+ reg = <24>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "mmchs1_fck";
clocks = <&core_96m_fck>;
- ti,bit-shift = <24>;
};
- i2c3_fck: clock-i2c3-fck {
+ i2c3_fck: clock-i2c3-fck@17 {
+ reg = <17>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "i2c3_fck";
clocks = <&core_96m_fck>;
- ti,bit-shift = <17>;
};
- i2c2_fck: clock-i2c2-fck {
+ i2c2_fck: clock-i2c2-fck@16 {
+ reg = <16>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "i2c2_fck";
clocks = <&core_96m_fck>;
- ti,bit-shift = <16>;
};
- i2c1_fck: clock-i2c1-fck {
+ i2c1_fck: clock-i2c1-fck@15 {
+ reg = <15>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "i2c1_fck";
clocks = <&core_96m_fck>;
- ti,bit-shift = <15>;
};
- mcbsp5_gate_fck: clock-mcbsp5-gate-fck {
+ mcbsp5_gate_fck: clock-mcbsp5-gate-fck@10 {
+ reg = <10>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "mcbsp5_gate_fck";
clocks = <&mcbsp_clks>;
- ti,bit-shift = <10>;
};
- mcbsp1_gate_fck: clock-mcbsp1-gate-fck {
+ mcbsp1_gate_fck: clock-mcbsp1-gate-fck@9 {
+ reg = <9>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "mcbsp1_gate_fck";
clocks = <&mcbsp_clks>;
- ti,bit-shift = <9>;
};
- mcspi4_fck: clock-mcspi4-fck {
+ mcspi4_fck: clock-mcspi4-fck@21 {
+ reg = <21>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "mcspi4_fck";
clocks = <&core_48m_fck>;
- ti,bit-shift = <21>;
};
- mcspi3_fck: clock-mcspi3-fck {
+ mcspi3_fck: clock-mcspi3-fck@20 {
+ reg = <20>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "mcspi3_fck";
clocks = <&core_48m_fck>;
- ti,bit-shift = <20>;
};
- mcspi2_fck: clock-mcspi2-fck {
+ mcspi2_fck: clock-mcspi2-fck@19 {
+ reg = <19>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "mcspi2_fck";
clocks = <&core_48m_fck>;
- ti,bit-shift = <19>;
};
- mcspi1_fck: clock-mcspi1-fck {
+ mcspi1_fck: clock-mcspi1-fck@18 {
+ reg = <18>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "mcspi1_fck";
clocks = <&core_48m_fck>;
- ti,bit-shift = <18>;
};
- uart2_fck: clock-uart2-fck {
+ uart2_fck: clock-uart2-fck@14 {
+ reg = <14>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "uart2_fck";
clocks = <&core_48m_fck>;
- ti,bit-shift = <14>;
};
- uart1_fck: clock-uart1-fck {
+ uart1_fck: clock-uart1-fck@13 {
+ reg = <13>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "uart1_fck";
clocks = <&core_48m_fck>;
- ti,bit-shift = <13>;
};
- hdq_fck: clock-hdq-fck {
+ hdq_fck: clock-hdq-fck@22 {
+ reg = <22>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "hdq_fck";
clocks = <&core_12m_fck>;
- ti,bit-shift = <22>;
};
};
compatible = "ti,clksel";
reg = <0xa10>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- sdrc_ick: clock-sdrc-ick {
+ sdrc_ick: clock-sdrc-ick@1 {
+ reg = <1>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "sdrc_ick";
clocks = <&core_l3_ick>;
- ti,bit-shift = <1>;
};
- mmchs2_ick: clock-mmchs2-ick {
+ mmchs2_ick: clock-mmchs2-ick@25 {
+ reg = <25>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mmchs2_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <25>;
};
- mmchs1_ick: clock-mmchs1-ick {
+ mmchs1_ick: clock-mmchs1-ick@24 {
+ reg = <24>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mmchs1_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <24>;
};
- hdq_ick: clock-hdq-ick {
+ hdq_ick: clock-hdq-ick@22 {
+ reg = <22>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "hdq_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <22>;
};
- mcspi4_ick: clock-mcspi4-ick {
+ mcspi4_ick: clock-mcspi4-ick@21 {
+ reg = <21>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mcspi4_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <21>;
};
- mcspi3_ick: clock-mcspi3-ick {
+ mcspi3_ick: clock-mcspi3-ick@20 {
+ reg = <20>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mcspi3_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <20>;
};
- mcspi2_ick: clock-mcspi2-ick {
+ mcspi2_ick: clock-mcspi2-ick@19 {
+ reg = <19>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mcspi2_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <19>;
};
- mcspi1_ick: clock-mcspi1-ick {
+ mcspi1_ick: clock-mcspi1-ick@18 {
+ reg = <18>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mcspi1_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <18>;
};
- i2c3_ick: clock-i2c3-ick {
+ i2c3_ick: clock-i2c3-ick@17 {
+ reg = <17>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "i2c3_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <17>;
};
- i2c2_ick: clock-i2c2-ick {
+ i2c2_ick: clock-i2c2-ick@16 {
+ reg = <16>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "i2c2_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <16>;
};
- i2c1_ick: clock-i2c1-ick {
+ i2c1_ick: clock-i2c1-ick@15 {
+ reg = <15>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "i2c1_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <15>;
};
- uart2_ick: clock-uart2-ick {
+ uart2_ick: clock-uart2-ick@14 {
+ reg = <14>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "uart2_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <14>;
};
- uart1_ick: clock-uart1-ick {
+ uart1_ick: clock-uart1-ick@13 {
+ reg = <13>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "uart1_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <13>;
};
- gpt11_ick: clock-gpt11-ick {
+ gpt11_ick: clock-gpt11-ick@12 {
+ reg = <12>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpt11_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <12>;
};
- gpt10_ick: clock-gpt10-ick {
+ gpt10_ick: clock-gpt10-ick@11 {
+ reg = <11>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpt10_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <11>;
};
- mcbsp5_ick: clock-mcbsp5-ick {
+ mcbsp5_ick: clock-mcbsp5-ick@10 {
+ reg = <10>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mcbsp5_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <10>;
};
- mcbsp1_ick: clock-mcbsp1-ick {
+ mcbsp1_ick: clock-mcbsp1-ick@9 {
+ reg = <9>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mcbsp1_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <9>;
};
- omapctrl_ick: clock-omapctrl-ick {
+ omapctrl_ick: clock-omapctrl-ick@6 {
+ reg = <6>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "omapctrl_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <6>;
};
- aes2_ick: clock-aes2-ick {
+ aes2_ick: clock-aes2-ick@28 {
+ reg = <28>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "aes2_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <28>;
};
- sha12_ick: clock-sha12-ick {
+ sha12_ick: clock-sha12-ick@27 {
+ reg = <27>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "sha12_ick";
clocks = <&core_l4_ick>;
- ti,bit-shift = <27>;
};
};
compatible = "ti,clksel";
reg = <0xc00>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- gpt1_gate_fck: clock-gpt1-gate-fck {
+ gpt1_gate_fck: clock-gpt1-gate-fck@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "gpt1_gate_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <0>;
};
- gpio1_dbck: clock-gpio1-dbck {
+ gpio1_dbck: clock-gpio1-dbck@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "gpio1_dbck";
clocks = <&wkup_32k_fck>;
- ti,bit-shift = <3>;
};
- wdt2_fck: clock-wdt2-fck {
+ wdt2_fck: clock-wdt2-fck@5 {
+ reg = <5>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "wdt2_fck";
clocks = <&wkup_32k_fck>;
- ti,bit-shift = <5>;
};
};
compatible = "ti,clksel";
reg = <0xc10>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- wdt2_ick: clock-wdt2-ick {
+ wdt2_ick: clock-wdt2-ick@5 {
+ reg = <5>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "wdt2_ick";
clocks = <&wkup_l4_ick>;
- ti,bit-shift = <5>;
};
- wdt1_ick: clock-wdt1-ick {
+ wdt1_ick: clock-wdt1-ick@4 {
+ reg = <4>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "wdt1_ick";
clocks = <&wkup_l4_ick>;
- ti,bit-shift = <4>;
};
- gpio1_ick: clock-gpio1-ick {
+ gpio1_ick: clock-gpio1-ick@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpio1_ick";
clocks = <&wkup_l4_ick>;
- ti,bit-shift = <3>;
};
- omap_32ksync_ick: clock-omap-32ksync-ick {
+ omap_32ksync_ick: clock-omap-32ksync-ick@2 {
+ reg = <2>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "omap_32ksync_ick";
clocks = <&wkup_l4_ick>;
- ti,bit-shift = <2>;
};
- gpt12_ick: clock-gpt12-ick {
+ gpt12_ick: clock-gpt12-ick@1 {
+ reg = <1>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpt12_ick";
clocks = <&wkup_l4_ick>;
- ti,bit-shift = <1>;
};
- gpt1_ick: clock-gpt1-ick {
+ gpt1_ick: clock-gpt1-ick@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpt1_ick";
clocks = <&wkup_l4_ick>;
- ti,bit-shift = <0>;
};
};
compatible = "ti,clksel";
reg = <0x1000>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- uart3_fck: clock-uart3-fck {
+ uart3_fck: clock-uart3-fck@11 {
+ reg = <11>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "uart3_fck";
clocks = <&per_48m_fck>;
- ti,bit-shift = <11>;
};
- gpt2_gate_fck: clock-gpt2-gate-fck {
+ gpt2_gate_fck: clock-gpt2-gate-fck@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "gpt2_gate_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <3>;
};
- gpt3_gate_fck: clock-gpt3-gate-fck {
+ gpt3_gate_fck: clock-gpt3-gate-fck@4 {
+ reg = <4>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "gpt3_gate_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <4>;
};
- gpt4_gate_fck: clock-gpt4-gate-fck {
+ gpt4_gate_fck: clock-gpt4-gate-fck@5 {
+ reg = <5>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "gpt4_gate_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <5>;
};
- gpt5_gate_fck: clock-gpt5-gate-fck {
+ gpt5_gate_fck: clock-gpt5-gate-fck@6 {
+ reg = <6>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "gpt5_gate_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <6>;
};
- gpt6_gate_fck: clock-gpt6-gate-fck {
+ gpt6_gate_fck: clock-gpt6-gate-fck@7 {
+ reg = <7>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "gpt6_gate_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <7>;
};
- gpt7_gate_fck: clock-gpt7-gate-fck {
+ gpt7_gate_fck: clock-gpt7-gate-fck@8 {
+ reg = <8>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "gpt7_gate_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <8>;
};
- gpt8_gate_fck: clock-gpt8-gate-fck {
+ gpt8_gate_fck: clock-gpt8-gate-fck@9 {
+ reg = <9>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "gpt8_gate_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <9>;
};
- gpt9_gate_fck: clock-gpt9-gate-fck {
+ gpt9_gate_fck: clock-gpt9-gate-fck@10 {
+ reg = <10>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "gpt9_gate_fck";
clocks = <&sys_ck>;
- ti,bit-shift = <10>;
};
- gpio6_dbck: clock-gpio6-dbck {
+ gpio6_dbck: clock-gpio6-dbck@17 {
+ reg = <17>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "gpio6_dbck";
clocks = <&per_32k_alwon_fck>;
- ti,bit-shift = <17>;
};
- gpio5_dbck: clock-gpio5-dbck {
+ gpio5_dbck: clock-gpio5-dbck@16 {
+ reg = <16>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "gpio5_dbck";
clocks = <&per_32k_alwon_fck>;
- ti,bit-shift = <16>;
};
- gpio4_dbck: clock-gpio4-dbck {
+ gpio4_dbck: clock-gpio4-dbck@15 {
+ reg = <15>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "gpio4_dbck";
clocks = <&per_32k_alwon_fck>;
- ti,bit-shift = <15>;
};
- gpio3_dbck: clock-gpio3-dbck {
+ gpio3_dbck: clock-gpio3-dbck@14 {
+ reg = <14>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "gpio3_dbck";
clocks = <&per_32k_alwon_fck>;
- ti,bit-shift = <14>;
};
- gpio2_dbck: clock-gpio2-dbck {
+ gpio2_dbck: clock-gpio2-dbck@13 {
+ reg = <13>;
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "gpio2_dbck";
clocks = <&per_32k_alwon_fck>;
- ti,bit-shift = <13>;
};
- wdt3_fck: clock-wdt3-fck {
+ wdt3_fck: clock-wdt3-fck@12 {
+ reg = <12>;
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clock-output-names = "wdt3_fck";
clocks = <&per_32k_alwon_fck>;
- ti,bit-shift = <12>;
};
- mcbsp2_gate_fck: clock-mcbsp2-gate-fck {
+ mcbsp2_gate_fck: clock-mcbsp2-gate-fck@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "mcbsp2_gate_fck";
clocks = <&mcbsp_clks>;
- ti,bit-shift = <0>;
};
- mcbsp3_gate_fck: clock-mcbsp3-gate-fck {
+ mcbsp3_gate_fck: clock-mcbsp3-gate-fck@1 {
+ reg = <1>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "mcbsp3_gate_fck";
clocks = <&mcbsp_clks>;
- ti,bit-shift = <1>;
};
- mcbsp4_gate_fck: clock-mcbsp4-gate-fck {
+ mcbsp4_gate_fck: clock-mcbsp4-gate-fck@2 {
+ reg = <2>;
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clock-output-names = "mcbsp4_gate_fck";
clocks = <&mcbsp_clks>;
- ti,bit-shift = <2>;
};
};
compatible = "ti,clksel";
reg = <0x1040>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- gpt2_mux_fck: clock-gpt2-mux-fck {
+ gpt2_mux_fck: clock-gpt2-mux-fck@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt2_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
};
- gpt3_mux_fck: clock-gpt3-mux-fck {
+ gpt3_mux_fck: clock-gpt3-mux-fck@1 {
+ reg = <1>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt3_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <1>;
};
- gpt4_mux_fck: clock-gpt4-mux-fck {
+ gpt4_mux_fck: clock-gpt4-mux-fck@2 {
+ reg = <2>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt4_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <2>;
};
- gpt5_mux_fck: clock-gpt5-mux-fck {
+ gpt5_mux_fck: clock-gpt5-mux-fck@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt5_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <3>;
};
- gpt6_mux_fck: clock-gpt6-mux-fck {
+ gpt6_mux_fck: clock-gpt6-mux-fck@4 {
+ reg = <4>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt6_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <4>;
};
- gpt7_mux_fck: clock-gpt7-mux-fck {
+ gpt7_mux_fck: clock-gpt7-mux-fck@5 {
+ reg = <5>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt7_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <5>;
};
- gpt8_mux_fck: clock-gpt8-mux-fck {
+ gpt8_mux_fck: clock-gpt8-mux-fck@6 {
+ reg = <6>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt8_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <6>;
};
- gpt9_mux_fck: clock-gpt9-mux-fck {
+ gpt9_mux_fck: clock-gpt9-mux-fck@7 {
+ reg = <7>;
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clock-output-names = "gpt9_mux_fck";
clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <7>;
};
};
compatible = "ti,clksel";
reg = <0x1010>;
#clock-cells = <2>;
- #address-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- gpio6_ick: clock-gpio6-ick {
+ gpio6_ick: clock-gpio6-ick@17 {
+ reg = <17>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpio6_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <17>;
};
- gpio5_ick: clock-gpio5-ick {
+ gpio5_ick: clock-gpio5-ick@16 {
+ reg = <16>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpio5_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <16>;
};
- gpio4_ick: clock-gpio4-ick {
+ gpio4_ick: clock-gpio4-ick@15 {
+ reg = <15>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpio4_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <15>;
};
- gpio3_ick: clock-gpio3-ick {
+ gpio3_ick: clock-gpio3-ick@14 {
+ reg = <14>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpio3_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <14>;
};
- gpio2_ick: clock-gpio2-ick {
+ gpio2_ick: clock-gpio2-ick@13 {
+ reg = <13>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpio2_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <13>;
};
- wdt3_ick: clock-wdt3-ick {
+ wdt3_ick: clock-wdt3-ick@12 {
+ reg = <12>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "wdt3_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <12>;
};
- uart3_ick: clock-uart3-ick {
+ uart3_ick: clock-uart3-ick@11 {
+ reg = <11>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "uart3_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <11>;
};
- uart4_ick: clock-uart4-ick {
+ uart4_ick: clock-uart4-ick@18 {
+ reg = <18>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "uart4_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <18>;
};
- gpt9_ick: clock-gpt9-ick {
+ gpt9_ick: clock-gpt9-ick@10 {
+ reg = <10>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpt9_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <10>;
};
- gpt8_ick: clock-gpt8-ick {
+ gpt8_ick: clock-gpt8-ick@9 {
+ reg = <9>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpt8_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <9>;
};
- gpt7_ick: clock-gpt7-ick {
+ gpt7_ick: clock-gpt7-ick@8 {
+ reg = <8>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpt7_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <8>;
};
- gpt6_ick: clock-gpt6-ick {
+ gpt6_ick: clock-gpt6-ick@7 {
+ reg = <7>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpt6_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <7>;
};
- gpt5_ick: clock-gpt5-ick {
+ gpt5_ick: clock-gpt5-ick@6 {
+ reg = <6>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpt5_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <6>;
};
- gpt4_ick: clock-gpt4-ick {
+ gpt4_ick: clock-gpt4-ick@5 {
+ reg = <5>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpt4_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <5>;
};
- gpt3_ick: clock-gpt3-ick {
+ gpt3_ick: clock-gpt3-ick@4 {
+ reg = <4>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpt3_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <4>;
};
- gpt2_ick: clock-gpt2-ick {
+ gpt2_ick: clock-gpt2-ick@3 {
+ reg = <3>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "gpt2_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <3>;
};
- mcbsp2_ick: clock-mcbsp2-ick {
+ mcbsp2_ick: clock-mcbsp2-ick@0 {
+ reg = <0>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mcbsp2_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <0>;
};
- mcbsp3_ick: clock-mcbsp3-ick {
+ mcbsp3_ick: clock-mcbsp3-ick@1 {
+ reg = <1>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mcbsp3_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <1>;
};
- mcbsp4_ick: clock-mcbsp4-ick {
+ mcbsp4_ick: clock-mcbsp4-ick@2 {
+ reg = <2>;
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clock-output-names = "mcbsp4_ick";
clocks = <&per_l4_ick>;
- ti,bit-shift = <2>;
};
};
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
interrupt-controller;
#interrupt-cells = <1>;
+ system-power-controller;
rtc {
compatible = "ti,twl4030-rtc";
reg = <0x48>;
/* IRQ# = 7 */
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
+ system-power-controller;
};
twl6040: twl@4b {
/*
* Ambient Light Sensor
- * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf
+ * https://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf (defunct)
*/
bh1780@29 {
compatible = "rohm,bh1780";
#size-cells = <1>;
ranges = <0 0x56000000 0x2000000>;
- /*
- * Closed source PowerVR driver, no child device
- * binding or driver in mainline
- */
+ gpu@0 {
+ compatible = "ti,omap4430-gpu", "img,powervr-sgx540";
+ reg = <0x0 0x2000000>; /* 32MB */
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
/*
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz/
+ * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz/
*/
/dts-v1/;
#size-cells = <1>;
ranges = <0 0x56000000 0x2000000>;
- /*
- * Closed source PowerVR driver, no child device
- * binding or driver in mainline
- */
+ gpu@0 {
+ compatible = "ti,omap5432-gpu", "img,powervr-sgx544";
+ reg = <0x0 0x2000000>; /* 32MB */
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
target-module@58000000 {
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
* Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/twl6030.pdf
+ * https://www.ti.com/lit/ds/symlink/twl6030.pdf
*/
&twl {
compatible = "ti,twl6030";
# Add any required device tree compiler flags here
DTC_FLAGS += -a 0x8
+ifdef CONFIG_RCAR_64
+DTC_FLAGS += -R 4 -p 0x1000
+endif
+
PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:
};
&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pin>;
status = "okay";
};
};
&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pin>;
status = "okay";
};
function = "spi1";
};
+ /omit-if-no-ref/
spdif_tx_pin: spdif-tx-pin {
pins = "PH7";
function = "spdif";
clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
clock-names = "apb", "spdif";
resets = <&ccu RST_BUS_SPDIF>;
- dmas = <&dma 2>;
- dma-names = "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spdif_tx_pin>;
+ dmas = <&dma 2>, <&dma 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>.
*/
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>.
*/
interrupt-controller;
#interrupt-cells = <1>;
- regulators{
+ regulators {
reg_dcdc1: dcdc1 {
regulator-name = "vdd-gpu-sys";
regulator-min-microvolt = <810000>;
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Martin Botka <martin@biqu3d.com>.
*/
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/reset/sun50i-h616-ccu.h>
#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
#reset-cells = <1>;
};
+ dma: dma-controller@3002000 {
+ compatible = "allwinner,sun50i-h616-dma",
+ "allwinner,sun50i-a100-dma";
+ reg = <0x03002000 0x1000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
+ clock-names = "bus", "mbus";
+ dma-channels = <16>;
+ dma-requests = <49>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
sid: efuse@3006000 {
compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";
reg = <0x03006000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ ths_calibration: thermal-sensor-calibration@14 {
+ reg = <0x14 0x8>;
+ };
};
watchdog: watchdog@30090a0 {
function = "spi1";
};
+ spdif_tx_pin: spdif-tx-pin {
+ pins = "PH4";
+ function = "spdif";
+ };
+
uart0_ph_pins: uart0-ph-pins {
pins = "PH0", "PH1";
function = "uart0";
pins = "PG8", "PG9";
function = "uart1";
};
+
+ /omit-if-no-ref/
+ x32clk_fanout_pin: x32clk-fanout-pin {
+ pins = "PG10";
+ function = "clock";
+ };
};
gic: interrupt-controller@3021000 {
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>;
+ dmas = <&dma 14>, <&dma 14>;
+ dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>;
+ dmas = <&dma 15>, <&dma 15>;
+ dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
+ dmas = <&dma 16>, <&dma 16>;
+ dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART3>;
+ dmas = <&dma 17>, <&dma 17>;
+ dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART3>;
status = "disabled";
};
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART4>;
+ dmas = <&dma 18>, <&dma 18>;
+ dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART4>;
status = "disabled";
};
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART5>;
+ dmas = <&dma 19>, <&dma 19>;
+ dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART5>;
status = "disabled";
};
reg = <0x05002000 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
+ dmas = <&dma 43>, <&dma 43>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
reg = <0x05002400 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
+ dmas = <&dma 44>, <&dma 44>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
reg = <0x05002800 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
+ dmas = <&dma 45>, <&dma 45>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_I2C2>;
status = "disabled";
#address-cells = <1>;
reg = <0x05002c00 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C3>;
+ dmas = <&dma 46>, <&dma 46>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_I2C3>;
status = "disabled";
#address-cells = <1>;
reg = <0x05003000 0x400>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C4>;
+ dmas = <&dma 47>, <&dma 47>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_I2C4>;
status = "disabled";
#address-cells = <1>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
+ dmas = <&dma 22>, <&dma 22>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_SPI0>;
status = "disabled";
#address-cells = <1>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_SPI1>;
status = "disabled";
#address-cells = <1>;
};
};
+ spdif: spdif@5093000 {
+ compatible = "allwinner,sun50i-h616-spdif";
+ reg = <0x05093000 0x400>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
+ clock-names = "apb", "spdif";
+ resets = <&ccu RST_BUS_SPDIF>;
+ dmas = <&dma 2>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pin>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ths: thermal-sensor@5070400 {
+ compatible = "allwinner,sun50i-h616-ths";
+ reg = <0x05070400 0x400>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_THS>;
+ clock-names = "bus";
+ resets = <&ccu RST_BUS_THS>;
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ allwinner,sram = <&syscon>;
+ #thermal-sensor-cells = <1>;
+ };
+
usbotg: usb@5100000 {
compatible = "allwinner,sun50i-h616-musb",
"allwinner,sun8i-h3-musb";
reg = <0x07081400 0x400>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB2_I2C>;
+ dmas = <&dma 48>, <&dma 48>;
+ dma-names = "rx", "tx";
resets = <&r_ccu RST_R_APB2_I2C>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <500>;
+ polling-delay = <1000>;
+ thermal-sensors = <&ths 2>;
+ sustainable-power = <1000>;
+
+ trips {
+ cpu_threshold: cpu-trip-0 {
+ temperature = <60000>;
+ type = "passive";
+ hysteresis = <0>;
+ };
+ cpu_target: cpu-trip-1 {
+ temperature = <70000>;
+ type = "passive";
+ hysteresis = <0>;
+ };
+ cpu_critical: cpu-trip-2 {
+ temperature = <110000>;
+ type = "critical";
+ hysteresis = <0>;
+ };
+ };
+ };
+
+ gpu-thermal {
+ polling-delay-passive = <500>;
+ polling-delay = <1000>;
+ thermal-sensors = <&ths 0>;
+ sustainable-power = <1100>;
+
+ trips {
+ gpu_temp_critical: gpu-trip-0 {
+ temperature = <110000>;
+ type = "critical";
+ hysteresis = <0>;
+ };
+ };
+ };
+
+ ve-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 1>;
+
+ trips {
+ ve_temp_critical: ve-trip-0 {
+ temperature = <110000>;
+ type = "critical";
+ hysteresis = <0>;
+ };
+ };
+ };
+
+ ddr-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 3>;
+
+ trips {
+ ddr_temp_critical: ddr-trip-0 {
+ temperature = <110000>;
+ type = "critical";
+ hysteresis = <0>;
+ };
+ };
+ };
+ };
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include "sun50i-h616.dtsi"
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <®_dldo1>;
+ vqmmc-supply = <®_aldo1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp313: pmic@36 {
+ compatible = "x-powers,axp313a";
+ reg = <0x36>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-1v8-pll";
+ };
+
+ reg_dldo1: dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3-io";
+ };
+
+ reg_dcdc1: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <990000>;
+ regulator-name = "vdd-gpu-sys";
+ };
+
+ reg_dcdc2: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-dram";
+ };
+ };
+ };
+};
+
+&pio {
+ vcc-pc-supply = <®_dldo1>;
+ vcc-pf-supply = <®_dldo1>;
+ vcc-pg-supply = <®_aldo1>;
+ vcc-ph-supply = <®_dldo1>;
+ vcc-pi-supply = <®_dldo1>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "sun50i-h618-longan-module-3h.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Sipeed Longan Pi 3H";
+ compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618";
+
+ aliases {
+ ethernet0 = &emac0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_ORANGE>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <0>;
+ gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_ORANGE>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <1>;
+ gpios = <&pio 6 4 GPIO_ACTIVE_LOW>; /* PG4 */
+ };
+ };
+
+ reg_vcc5v: regulator-vcc5v {
+ /* board wide 5V supply directly from the USB-C socket */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_vcc3v3: regulator-vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <®_vcc5v>;
+ };
+};
+
+&axp313 {
+ vin1-supply = <®_vcc5v>;
+ vin2-supply = <®_vcc5v>;
+ vin3-supply = <®_vcc5v>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+/* WiFi & BT combo module is connected to this Host */
+&ehci3 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&emac0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ phy-supply = <®_vcc3v3>;
+ status = "okay";
+};
+
+&mdio0 {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ vmmc-supply = <®_vcc3v3>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usbotg {
+ /*
+ * PHY0 pins are connected to a USB-C socket, but a role switch
+ * is not implemented: both CC pins are pulled to GND.
+ * The VBUS pins power the device, so a fixed peripheral mode
+ * is the best choice.
+ * The board can be powered via GPIOs, in this case port0 *can*
+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
+ * then provided by the GPIOs. Any user of this setup would
+ * need to adjust the DT accordingly: dr_mode set to "host",
+ * enabling OHCI0 and EHCI0.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_vcc5v>;
+ usb2_vbus-supply = <®_vcc5v>;
+ status = "okay";
+};
compatible = "transpeed,8k618-t", "allwinner,sun50i-h618";
aliases {
+ ethernet1 = &sdio_wifi;
serial0 = &uart0;
};
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
+ clock-names = "ext_clock";
+ pinctrl-0 = <&x32clk_fanout_pin>;
+ pinctrl-names = "default";
+ reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
+ };
};
&ehci0 {
status = "okay";
};
+&mmc1 {
+ vmmc-supply = <®_dldo1>;
+ vqmmc-supply = <®_aldo1>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ sdio_wifi: wifi@1 {
+ reg = <1>;
+ };
+};
+
&mmc2 {
vmmc-supply = <®_dldo1>;
vqmmc-supply = <®_aldo1>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2023 ARM Ltd.
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Remix Mini PC";
+ compatible = "jide,remix-mini-pc", "allwinner,sun50i-h64",
+ "allwinner,sun50i-a64";
+
+ aliases {
+ ethernet1 = &rtl8723bs;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ reg_vcc5v: regulator-5v {
+ /* board wide 5V supply directly from the DC input */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&codec {
+ status = "okay";
+};
+
+&codec_analog {
+ cpvdd-supply = <®_eldo1>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&dai {
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+/* Connects to the AC200 chip */
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&i2c0_pins {
+ bias-pull-up;
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_dcdc1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <®_aldo1>;
+ vqmmc-supply = <®_dldo4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8723bs: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_eldo1>;
+ bus-width = <8>;
+ non-removable;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pb-supply = <®_dcdc1>;
+ vcc-pc-supply = <®_dcdc1>;
+ vcc-pd-supply = <®_dcdc1>;
+ vcc-pe-supply = <®_dcdc1>;
+ vcc-pf-supply = <®_dcdc1>;
+ vcc-pg-supply = <®_dldo4>;
+ vcc-ph-supply = <®_dcdc1>;
+};
+
+&r_ir {
+ status = "okay";
+};
+
+&r_pio {
+ /*
+ * We cannot add that supply for now since it would create a circular
+ * dependency between pinctrl, the regulator and the RSB Bus.
+ *
+ * vcc-pl-supply = <®_aldo2>;
+ */
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_LOW>;
+ x-powers,drive-vbus-en;
+
+ vin1-supply = <®_vcc5v>;
+ vin2-supply = <®_vcc5v>;
+ vin3-supply = <®_vcc5v>;
+ vin5-supply = <®_vcc5v>;
+ vin6-supply = <®_vcc5v>;
+ aldoin-supply = <®_vcc5v>;
+ dldoin-supply = <®_vcc5v>;
+ eldoin-supply = <®_vcc5v>;
+ fldoin-supply = <®_vcc5v>;
+ drivevbus-supply = <®_vcc5v>;
+ ips-supply = <®_vcc5v>;
+
+ status = "okay";
+ };
+};
+
+#include "axp803.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+/* Deviates from the reset default of 1.1V. */
+®_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd-sys";
+};
+
+®_aldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_aldo2 {
+ /* Specifying R_PIO consumer would create circular dependency. */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+/* AC200 power supply */
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-ave-33";
+};
+
+®_dldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+®_drivevbus {
+ regulator-name = "usb0-vbus";
+ status = "okay";
+};
+
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-cpvdd-dram-emmc";
+};
+
+/* Supplies the arisc management core, needed by TF-A to power off cores. */
+®_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&simplefb_hdmi {
+ vcc-hdmi-supply = <®_dcdc1>;
+};
+
+&sound {
+ simple-audio-card,aux-devs = <&codec_analog>;
+ simple-audio-card,widgets = "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
+ "Headphone Jack", "HP",
+ "ADCL", "Left ADC",
+ "ADCR", "Right ADC",
+ "MIC2", "Microphone Jack";
+ status = "okay";
+};
+
+/* On the (unpopulated) UART pads. */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723bs-bt";
+ enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ max-speed = <1500000>;
+ };
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_vbus-supply = <®_drivevbus>;
+ usb1_vbus-supply = <®_drivevbus>;
+ status = "okay";
+};
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/amlogic,c3-reset.h>
/ {
cpus {
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
+ reset: reset-controller@2000 {
+ compatible = "amlogic,c3-reset";
+ reg = <0x0 0x2000 0x0 0x98>;
+ #reset-cells = <1>;
+ };
+
watchdog@2100 {
compatible = "amlogic,c3-wdt", "amlogic,t7-wdt";
reg = <0x0 0x2100 0x0 0x10>;
enable-method = "psci";
};
- cpu101: cpu@101{
+ cpu101: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
};
};
+ gpio_intc: interrupt-controller@4080 {
+ compatible = "amlogic,t7-gpio-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0x4080 0x0 0x20>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts =
+ <10 11 12 13 14 15 16 17 18 19 20 21>;
+ };
+
uart_a: serial@78000 {
compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
reg = <0x0 0x78000 0x0 0x18>;
pinctrl-0 = <&spifc_pins>;
pinctrl-names = "default";
- spi_nand@0 {
+ flash@0 {
compatible = "spi-nand";
status = "okay";
reg = <0>;
<&clkc_periphs CLKID_USB_BUS>,
<&clkc_periphs CLKID_USB_CTRL_IN>;
clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
+ assigned-clocks = <&clkc_periphs CLKID_USB_BUS>;
+ assigned-clock-rates = <64000000>;
resets = <&reset RESET_USBCTRL>;
reset-name = "usb_ctrl";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vcc_5v: regulator-vcc_5v {
+ vcc_5v: regulator-vcc-5v {
compatible = "regulator-fixed";
regulator-name = "VCC5V";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vccq_1v8: regulator-vccq_1v8 {
+ vccq_1v8: regulator-vccq-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCCQ_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- usb_pwr: regulator-usb_pwr {
+ usb_pwr: regulator-usb-pwr {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
regulator-min-microvolt = <5000000>;
"", "", "", "", "", // 80 - 84
"", ""; // 85-86
};
-
-&cpu0 {
- #cooling-cells = <2>;
-};
-
-&cpu1 {
- #cooling-cells = <2>;
-};
-
-&cpu2 {
- #cooling-cells = <2>;
-};
-
-&cpu3 {
- #cooling-cells = <2>;
-};
compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";
model = "Amlogic Meson AXG S400 Development Board";
- adc_keys {
+ keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
reg = <0x0 0x0 0x0 0x40000000>;
};
- main_12v: regulator-main_12v {
+ main_12v: regulator-main-12v {
compatible = "regulator-fixed";
regulator-name = "12V";
regulator-min-microvolt = <12000000>;
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vcc_5v: regulator-vcc_5v {
+ vcc_5v: regulator-vcc-5v {
compatible = "regulator-fixed";
regulator-name = "VCC5V";
regulator-min-microvolt = <5000000>;
enable-active-high;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- usb_pwr: regulator-usb_pwr {
+ usb_pwr: regulator-usb-pwr {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
regulator-min-microvolt = <5000000>;
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
+ dynamic-power-coefficient = <140>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
+ dynamic-power-coefficient = <140>;
+ #cooling-cells = <2>;
};
cpu2: cpu@2 {
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
+ dynamic-power-coefficient = <140>;
+ #cooling-cells = <2>;
};
cpu3: cpu@3 {
enable-method = "psci";
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
+ dynamic-power-coefficient = <140>;
+ #cooling-cells = <2>;
};
l2: l2-cache0 {
clocks = <&clkc CLKID_NNA_CORE_CLK>,
<&clkc CLKID_NNA_AXI_CLK>;
clock-names = "core", "bus";
+ assigned-clocks = <&clkc CLKID_NNA_CORE_CLK>,
+ <&clkc CLKID_NNA_AXI_CLK>;
+ assigned-clock-rates = <800000000>, <800000000>;
resets = <&reset RESET_NNA>;
status = "disabled";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2024 Freebox SAS
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+&uart_A {
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ vbat-supply = <&vddao_3v3>;
+ vddio-supply = <&vddio_ao1v8>;
+ };
+};
+
+&sd_emmc_a {
+ /* Per mmc-controller.yaml */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* NB: may be either AP6398S or AP6398SR3 wifi module */
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2024 Freebox SAS
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+&uart_A {
+ bluetooth {
+ compatible = "realtek,rtl8822cs-bt";
+ enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
+ device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&sd_emmc_a {
+ /* No explicit compatible for rtl8822cs sdio */
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2024 Freebox SAS
+
+/*
+ * SEI codename: SEI530FB (based on SEI510)
+ * Freebox codename: fbx8am
+ * Commercial names: Freebox Pop, Player TV Free 4K
+ */
+
+/dts-v1/;
+
+#include "meson-g12a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "freebox,fbx8am", "amlogic,g12a";
+ model = "Freebox Player Pop";
+ chassis-type = "embedded";
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ /* Physical user-accessible reset button near USB port */
+ power-button {
+ label = "Reset";
+ linux,code = <BTN_MISC>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ spdif_dit: audio-codec-2 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ sound-name-prefix = "DIT";
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ao_5v: regulator-ao-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc-in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ };
+
+ emmc_1v8: regulator-emmc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vddao_3v3_t: regulator-vddao-3v3-t {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3_T";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ };
+
+ vddcpu: regulator-vddcpu {
+ /*
+ * SY8120B1ABC DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <721000>;
+ regulator-max-microvolt = <1022000>;
+
+ pwm-supply = <&ao_5v>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddio_ao1v8: regulator-vddio-ao1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <10>; /* required for 43752 */
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "fbx8am";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "SPDIFOUT_A IN 0", "FRDDR_A OUT 3",
+ "SPDIFOUT_A IN 1", "FRDDR_B OUT 3",
+ "SPDIFOUT_A IN 2", "FRDDR_C OUT 3";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* spdif hdmi or toslink interface */
+ dai-link-4 {
+ sound-dai = <&spdifout_a>;
+
+ codec-0 {
+ sound-dai = <&spdif_dit>;
+ };
+
+ codec-1 {
+ sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>;
+ };
+ };
+
+ /* spdif hdmi interface */
+ dai-link-5 {
+ sound-dai = <&spdifout_b>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-6 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+ðmac {
+ status = "okay";
+ phy-handle = <&internal_ephy>;
+ phy-mode = "rmii";
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&spdifout_a {
+ pinctrl-0 = <&spdif_out_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&spdifout_b {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+};
+
+&pdm {
+ pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>,
+ <&pdm_din2_z_pins>, <&pdm_din3_z_pins>,
+ <&pdm_dclk_z_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_ao1v8>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
clock-names = "ext_clock";
};
- ao_5v: regulator-ao_5v {
+ ao_5v: regulator-ao-5v {
compatible = "regulator-fixed";
regulator-name = "AO_5V";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- vcc_1v8: regulator-vcc_1v8 {
+ vcc_1v8: regulator-vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- hdmi_pw: regulator-hdmi_pw {
+ hdmi_pw: regulator-hdmi-pw {
compatible = "regulator-fixed";
regulator-name = "HDMI_PW";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- vddao_1v8: regulator-vddao_1v8 {
+ vddao_1v8: regulator-vddao-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
compatible = "seirobotics,sei510", "amlogic,g12a";
model = "SEI Robotics SEI510";
- adc_keys {
+ keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
reg = <0x0 0x0 0x0 0x40000000>;
};
- ao_5v: regulator-ao_5v {
+ ao_5v: regulator-ao-5v {
compatible = "regulator-fixed";
regulator-name = "AO_5V";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- dc_in: regulator-dc_in {
+ dc_in: regulator-dc-in {
compatible = "regulator-fixed";
regulator-name = "DC_IN";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- emmc_1v8: regulator-emmc_1v8 {
+ emmc_1v8: regulator-emmc-1v8 {
compatible = "regulator-fixed";
regulator-name = "EMMC_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vddao_3v3_t: regultor-vddao_3v3_t {
+ vddao_3v3_t: regulator-vddao-3v3-t {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3_T";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vddio_ao1v8: regulator-vddio_ao1v8 {
+ vddio_ao1v8: regulator-vddio-ao1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO1V8";
regulator-min-microvolt = <1800000>;
reg = <0x0 0x0 0x0 0x40000000>;
};
- flash_1v8: regulator-flash_1v8 {
+ flash_1v8: regulator-flash-1v8 {
compatible = "regulator-fixed";
regulator-name = "FLASH_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- main_12v: regulator-main_12v {
+ main_12v: regulator-main-12v {
compatible = "regulator-fixed";
regulator-name = "12V";
regulator-min-microvolt = <12000000>;
regulator-always-on;
};
- usb_pwr_en: regulator-usb_pwr_en {
+ usb_pwr_en: regulator-usb-pwr-en {
compatible = "regulator-fixed";
regulator-name = "USB_PWR_EN";
regulator-min-microvolt = <5000000>;
enable-active-high;
};
- vcc_1v8: regulator-vcc_1v8 {
+ vcc_1v8: regulator-vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
/* FIXME: actually controlled by VDDCPU_B_EN */
};
- vcc_5v: regulator-vcc_5v {
+ vcc_5v: regulator-vcc-5v {
compatible = "regulator-fixed";
regulator-name = "VCC_5V";
regulator-min-microvolt = <5000000>;
enable-active-high;
};
- vddao_1v8: regulator-vddao_1v8 {
+ vddao_1v8: regulator-vddao-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
clock-names = "ext_clock";
};
- flash_1v8: regulator-flash_1v8 {
+ flash_1v8: regulator-flash-1v8 {
compatible = "regulator-fixed";
regulator-name = "FLASH_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- dc_in: regulator-dc_in {
+ dc_in: regulator-dc-in {
compatible = "regulator-fixed";
regulator-name = "DC_IN";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- vcc_1v8: regulator-vcc_1v8 {
+ vcc_1v8: regulator-vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
/* FIXME: actually controlled by VDDCPU_B_EN */
};
- vcc_5v: regulator-vcc_5v {
+ vcc_5v: regulator-vcc-5v {
compatible = "regulator-fixed";
regulator-name = "VCC_5V";
regulator-min-microvolt = <5000000>;
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
};
- vddao_1v8: regulator-vddao_1v8 {
+ vddao_1v8: regulator-vddao-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
status = "okay";
};
- hub_5v: regulator-hub_5v {
+ hub_5v: regulator-hub-5v {
compatible = "regulator-fixed";
regulator-name = "HUB_5V";
regulator-min-microvolt = <5000000>;
};
};
- tflash_vdd: regulator-tflash_vdd {
+ tflash_vdd: regulator-tflash-vdd {
compatible = "regulator-fixed";
regulator-name = "TFLASH_VDD";
regulator-always-on;
};
- tf_io: gpio-regulator-tf_io {
+ tf_io: gpio-regulator-tf-io {
compatible = "regulator-gpio";
regulator-name = "TF_IO";
<1800000 1>;
};
- flash_1v8: regulator-flash_1v8 {
+ flash_1v8: regulator-flash-1v8 {
compatible = "regulator-fixed";
regulator-name = "FLASH_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- main_12v: regulator-main_12v {
+ main_12v: regulator-main-12v {
compatible = "regulator-fixed";
regulator-name = "12V";
regulator-min-microvolt = <12000000>;
regulator-always-on;
};
- usb_pwr_en: regulator-usb_pwr_en {
+ usb_pwr_en: regulator-usb-pwr-en {
compatible = "regulator-fixed";
regulator-name = "USB_PWR_EN";
regulator-min-microvolt = <5000000>;
enable-active-high;
};
- vcc_5v: regulator-vcc_5v {
+ vcc_5v: regulator-vcc-5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
enable-active-high;
};
- vcc_1v8: regulator-vcc_1v8 {
+ vcc_1v8: regulator-vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vddao_1v8: regulator-vddao_1v8 {
+ vddao_1v8: regulator-vddao-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
clock-names = "ext_clock";
};
- flash_1v8: regulator-flash_1v8 {
+ flash_1v8: regulator-flash-1v8 {
compatible = "regulator-fixed";
regulator-name = "FLASH_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- main_12v: regulator-main_12v {
+ main_12v: regulator-main-12v {
compatible = "regulator-fixed";
regulator-name = "12V";
regulator-min-microvolt = <12000000>;
regulator-always-on;
};
- vcc_5v: regulator-vcc_5v {
+ vcc_5v: regulator-vcc-5v {
compatible = "regulator-fixed";
regulator-name = "VCC_5V";
regulator-min-microvolt = <5000000>;
enable-active-high;
};
- vcc_1v8: regulator-vcc_1v8 {
+ vcc_1v8: regulator-vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
reg = <0x0 0x0 0x0 0x80000000>;
};
- ao_5v: regulator-ao_5v {
+ ao_5v: regulator-ao-5v {
compatible = "regulator-fixed";
regulator-name = "AO_5V";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- dc_in: regulator-dc_in {
+ dc_in: regulator-dc-in {
compatible = "regulator-fixed";
regulator-name = "DC_IN";
regulator-min-microvolt = <5000000>;
};
};
- vcc_card: regulator-vcc_card {
+ vcc_card: regulator-vcc-card {
compatible = "regulator-fixed";
regulator-name = "VCC_CARD";
regulator-min-microvolt = <3300000>;
gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddio_ao3v3: regulator-vddio_ao3v3 {
+ vddio_ao3v3: regulator-vddio-ao3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
<3300000 1>;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- hdmi_p5v0: regulator-hdmi_p5v0 {
+ hdmi_p5v0: regulator-hdmi-p5v0 {
compatible = "regulator-fixed";
regulator-name = "HDMI_P5V0";
regulator-min-microvolt = <5000000>;
vin-supply = <&p5v0>;
};
- tflash_vdd: regulator-tflash_vdd {
+ tflash_vdd: regulator-tflash-vdd {
compatible = "regulator-fixed";
regulator-name = "TFLASH_VDD";
vin-supply = <&vddio_ao3v3>;
};
- tf_io: gpio-regulator-tf_io {
+ tf_io: gpio-regulator-tf-io {
compatible = "regulator-gpio";
regulator-name = "TF_IO";
vin-supply = <&p5v0>;
};
- ddr3_1v5: regulator-ddr3_1v5 {
+ ddr3_1v5: regulator-ddr3-1v5 {
compatible = "regulator-fixed";
regulator-name = "DDR3_1V5";
regulator-min-microvolt = <1500000>;
sound-name-prefix = "DIT";
};
- avdd18_usb_adc: regulator-avdd18_usb_adc {
+ avdd18_usb_adc: regulator-avdd18-usb-adc {
compatible = "regulator-fixed";
regulator-name = "AVDD18_USB_ADC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- adc_keys {
+ keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
regulator-settling-time-down-us = <150000>;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
enable-active-high;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
enable-active-high;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
};
};
- dc_5v: regulator-dc_5v {
+ dc_5v: regulator-dc-5v {
compatible = "regulator-fixed";
regulator-name = "DC_5V";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
reg = <0x0 0x0 0x0 0x20000000>;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
stdout-path = "serial0:115200n8";
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
<3300000 1>;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
reg = <0x0 0x0 0x0 0x80000000>;
};
- ao_5v: regulator-ao_5v {
+ ao_5v: regulator-ao-5v {
compatible = "regulator-fixed";
regulator-name = "AO_5V";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- dc_in: regulator-dc_in {
+ dc_in: regulator-dc-in {
compatible = "regulator-fixed";
regulator-name = "DC_IN";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- vcc_card: regulator-vcc_card {
+ vcc_card: regulator-vcc-card {
compatible = "regulator-fixed";
regulator-name = "VCC_CARD";
regulator-min-microvolt = <3300000>;
gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>;
};
- vddio_ao3v3: regulator-vddio_ao3v3 {
+ vddio_ao3v3: regulator-vddio-ao3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO3V3";
regulator-min-microvolt = <3300000>;
regulator-settling-time-down-us = <50000>;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vcc_1v8: regulator-vcc_1v8 {
+ vcc_1v8: regulator-vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC 1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-settling-time-down-us = <50000>;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
};
/* This is provided by LDOs on the eMMC daugther card */
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
<3300000 1>;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddio_boot: regulator-vddio_boot {
+ vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
"amlogic,meson-gxm";
model = "Libre Computer AML-S912-PC";
- typec2_vbus: regulator-typec2_vbus {
+ typec2_vbus: regulator-typec2-vbus {
compatible = "regulator-fixed";
regulator-name = "TYPEC2_VBUS";
regulator-min-microvolt = <5000000>;
clock-names = "ext_clock";
};
- dc_in: regulator-dc_in {
+ dc_in: regulator-dc-in {
compatible = "regulator-fixed";
regulator-name = "DC_IN";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- vcc_5v: regulator-vcc_5v {
+ vcc_5v: regulator-vcc-5v {
compatible = "regulator-fixed";
regulator-name = "VCC_5V";
regulator-min-microvolt = <5000000>;
enable-active-high;
};
- vcc_1v8: regulator-vcc_1v8 {
+ vcc_1v8: regulator-vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
/* FIXME: actually controlled by VDDCPU_B_EN */
};
- vddao_1v8: regulator-vddao_1v8 {
+ vddao_1v8: regulator-vddao-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- emmc_1v8: regulator-emmc_1v8 {
+ emmc_1v8: regulator-emmc-1v8 {
compatible = "regulator-fixed";
regulator-name = "EMMC_AO1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vsys_3v3: regulator-vsys_3v3 {
+ vsys_3v3: regulator-vsys-3v3 {
compatible = "regulator-fixed";
regulator-name = "VSYS_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- usb_pwr: regulator-usb_pwr {
+ usb_pwr: regulator-usb-pwr {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
regulator-min-microvolt = <5000000>;
gpio-open-drain;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
pwm-dutycycle-range = <100 0>;
};
- vddio_ao18: regulator-vddio_ao18 {
+ vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
};
- vddio_c: regulator-vddio_c {
+ vddio_c: regulator-vddio-c {
compatible = "regulator-gpio";
regulator-name = "VDDIO_C";
regulator-min-microvolt = <1800000>;
reg = <0x0 0x0 0x0 0x40000000>;
};
- ao_5v: regulator-ao_5v {
+ ao_5v: regulator-ao-5v {
compatible = "regulator-fixed";
regulator-name = "AO_5V";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- dc_in: regulator-dc_in {
+ dc_in: regulator-dc-in {
compatible = "regulator-fixed";
regulator-name = "DC_IN";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- emmc_1v8: regulator-emmc_1v8 {
+ emmc_1v8: regulator-emmc-1v8 {
compatible = "regulator-fixed";
regulator-name = "EMMC_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vddio_ao1v8: regulator-vddio_ao1v8 {
+ vddio_ao1v8: regulator-vddio-ao1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO1V8";
regulator-min-microvolt = <1800000>;
reg = <0x0 0x0 0x0 0x40000000>;
};
- emmc_1v8: regulator-emmc_1v8 {
+ emmc_1v8: regulator-emmc-1v8 {
compatible = "regulator-fixed";
regulator-name = "EMMC_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- dc_in: regulator-dc_in {
+ dc_in: regulator-dc-in {
compatible = "regulator-fixed";
regulator-name = "DC_IN";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- vddio_c: regulator-vddio_c {
+ vddio_c: regulator-vddio-c {
compatible = "regulator-gpio";
regulator-name = "VDDIO_C";
regulator-min-microvolt = <1800000>;
<3300000 1>;
};
- tflash_vdd: regulator-tflash_vdd {
+ tflash_vdd: regulator-tflash-vdd {
compatible = "regulator-fixed";
regulator-name = "TFLASH_VDD";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vddao_1v8: regulator-vddao_1v8 {
+ vddao_1v8: regulator-vddao-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
};
/* USB Hub Power Enable */
- vl_pwr_en: regulator-vl_pwr_en {
+ vl_pwr_en: regulator-vl-pwr-en {
compatible = "regulator-fixed";
regulator-name = "VL_PWR_EN";
regulator-min-microvolt = <5000000>;
};
/* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */
- p12v_0: regulator-p12v_0 {
+ p12v_0: regulator-p12v-0 {
compatible = "regulator-fixed";
regulator-name = "P12V_0";
regulator-min-microvolt = <12000000>;
};
/* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */
- p12v_1: regulator-p12v_1 {
+ p12v_1: regulator-p12v-1 {
compatible = "regulator-fixed";
regulator-name = "P12V_1";
regulator-min-microvolt = <12000000>;
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
- tflash_vdd: regulator-tflash_vdd {
+ tflash_vdd: regulator-tflash-vdd {
compatible = "regulator-fixed";
regulator-name = "TFLASH_VDD";
regulator-always-on;
};
- tf_io: gpio-regulator-tf_io {
+ tf_io: gpio-regulator-tf-io {
compatible = "regulator-gpio";
regulator-name = "TF_IO";
<1800000 1>;
};
- flash_1v8: regulator-flash_1v8 {
+ flash_1v8: regulator-flash-1v8 {
compatible = "regulator-fixed";
regulator-name = "FLASH_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- main_12v: regulator-main_12v {
+ main_12v: regulator-main-12v {
compatible = "regulator-fixed";
regulator-name = "12V";
regulator-min-microvolt = <12000000>;
regulator-always-on;
};
- vcc_5v: regulator-vcc_5v {
+ vcc_5v: regulator-vcc-5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
enable-active-high;
};
- vcc_1v8: regulator-vcc_1v8 {
+ vcc_1v8: regulator-vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- usb_pwr_en: regulator-usb_pwr_en {
+ usb_pwr_en: regulator-usb-pwr-en {
compatible = "regulator-fixed";
regulator-name = "USB_PWR_EN";
regulator-min-microvolt = <5000000>;
enable-active-high;
};
- vddao_1v8: regulator-vddao_1v8 {
+ vddao_1v8: regulator-vddao-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
reg = <0x0 0x0 0x0 0x40000000>;
};
- ao_5v: regulator-ao_5v {
+ ao_5v: regulator-ao-5v {
compatible = "regulator-fixed";
regulator-name = "AO_5V";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- dc_in: regulator-dc_in {
+ dc_in: regulator-dc-in {
compatible = "regulator-fixed";
regulator-name = "DC_IN";
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
- emmc_1v8: regulator-emmc_1v8 {
+ emmc_1v8: regulator-emmc-1v8 {
compatible = "regulator-fixed";
regulator-name = "EMMC_1V8";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- vddao_3v3: regulator-vddao_3v3 {
+ vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
};
/* Used by Tuner, RGB Led & IR Emitter LED array */
- vddao_3v3_t: regulator-vddao_3v3_t {
+ vddao_3v3_t: regulator-vddao-3v3-t {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3_T";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- vddio_ao1v8: regulator-vddio_ao1v8 {
+ vddio_ao1v8: regulator-vddio-ao1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO1V8";
regulator-min-microvolt = <1800000>;
};
};
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
&nandcs {
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
};
};
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
&nandcs {
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
};
};
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
&nandcs {
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
- brcm,nand-has-wp;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
partition@0 {
- compatible = "nvmem-cells";
label = "cferom";
reg = <0x0 0x100000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x100000>;
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
- base_mac_addr: mac@106a0 {
- reg = <0x106a0 0x6>;
+ base_mac_addr: mac@106a0 {
+ reg = <0x106a0 0x6>;
+ };
};
};
brcm,num-gphy = <5>;
brcm,num-rgmii-ports = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
ports: ports {
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- nand-controller@1800 {
+ nand_controller: nand-controller@1800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
reg-names = "nand", "nand-int-base";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "nand_ctlrdy";
- status = "okay";
+ status = "disabled";
nandcs: nand@0 {
compatible = "brcm,nandcs";
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
num-cs = <8>;
status = "disabled";
};
+
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
};
};
num-cs = <8>;
status = "disabled";
};
+
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ };
+ };
};
};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ brcm,wp-not-connected;
+ status = "okay";
+};
+
+&nandcs {
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+};
clock-names = "fin_pll", "mct";
};
+ pdma0: dma-controller@120c0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x120c0000 0x1000>;
+ clocks = <&cmu_core CLK_GOUT_PDMA_CORE_ACLK>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-broken-no-flushp;
+ };
+
gic: interrupt-controller@12a01000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
<&cmu_peri CLK_GOUT_SPI0_IPCLK>;
clock-names = "pclk", "ipclk";
status = "disabled";
+
+ spi_0: spi@13940000 {
+ compatible = "samsung,exynos850-spi";
+ reg = <0x13940000 0x30>;
+ clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
+ <&cmu_peri CLK_GOUT_SPI0_IPCLK>;
+ clock-names = "spi", "spi_busclk0";
+ dmas = <&pdma0 5>, <&pdma0 4>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+ num-cs = <1>;
+ samsung,spi-src-clk = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
usi_cmgp0: usi@11d000c0 {
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
+
+ spi_1: spi@11d00000 {
+ compatible = "samsung,exynos850-spi";
+ reg = <0x11d00000 0x30>;
+ clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
+ <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
+ clock-names = "spi", "spi_busclk0";
+ dmas = <&pdma0 12>, <&pdma0 13>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+ num-cs = <1>;
+ samsung,spi-src-clk = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
usi_cmgp1: usi@11d200c0 {
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
+
+ spi_2: spi@11d20000 {
+ compatible = "samsung,exynos850-spi";
+ reg = <0x11d20000 0x30>;
+ clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
+ <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
+ clock-names = "spi", "spi_busclk0";
+ dmas = <&pdma0 14>, <&pdma0 15>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&spi2_pins>;
+ pinctrl-names = "default";
+ num-cs = <1>;
+ samsung,spi-src-clk = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
};
};
clock-frequency = <200000000>;
};
+&hsi2c_8 {
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ };
+};
+
+&hsi2c_12 {
+ status = "okay";
+ /* TODO: add the devices once drivers exist */
+};
+
&pinctrl_far_alive {
key_voldown: key-voldown-pins {
samsung,pins = "gpa7-3";
status = "okay";
};
+&usi8 {
+ samsung,mode = <USI_V2_I2C>;
+ status = "okay";
+};
+
+&usi12 {
+ samsung,mode = <USI_V2_I2C>;
+ status = "okay";
+};
+
&watchdog_cl0 {
timeout-sec = <30>;
status = "okay";
#interrupt-cells = <2>;
};
- pcie0_clkreq: pcie0-clkreq-pins{
+ pcie0_clkreq: pcie0-clkreq-pins {
samsung,pins = "gph0-1";
samsung,pin-function = <GS101_PIN_FUNC_2>;
samsung,pin-pud = <GS101_PIN_PULL_UP>;
compatible = "arm,cortex-a55";
reg = <0x0000>;
enable-method = "psci";
- cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
};
compatible = "arm,cortex-a55";
reg = <0x0100>;
enable-method = "psci";
- cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
};
compatible = "arm,cortex-a55";
reg = <0x0200>;
enable-method = "psci";
- cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
};
compatible = "arm,cortex-a55";
reg = <0x0300>;
enable-method = "psci";
- cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
};
compatible = "arm,cortex-a76";
reg = <0x0400>;
enable-method = "psci";
- cpu-idle-states = <&ENYO_CPU_SLEEP>;
+ cpu-idle-states = <&ENYO_CPU_SLEEP>;
capacity-dmips-mhz = <620>;
dynamic-power-coefficient = <284>;
};
compatible = "arm,cortex-a76";
reg = <0x0500>;
enable-method = "psci";
- cpu-idle-states = <&ENYO_CPU_SLEEP>;
+ cpu-idle-states = <&ENYO_CPU_SLEEP>;
capacity-dmips-mhz = <620>;
dynamic-power-coefficient = <284>;
};
compatible = "arm,cortex-x1";
reg = <0x0600>;
enable-method = "psci";
- cpu-idle-states = <&HERA_CPU_SLEEP>;
+ cpu-idle-states = <&HERA_CPU_SLEEP>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <650>;
};
compatible = "arm,cortex-x1";
reg = <0x0700>;
enable-method = "psci";
- cpu-idle-states = <&HERA_CPU_SLEEP>;
+ cpu-idle-states = <&HERA_CPU_SLEEP>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <650>;
};
};
};
- /* TODO replace with CCF clock */
- dummy_clk: clock-3 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12345>;
- clock-output-names = "pclk";
- };
-
/* ect node is required to be present by bootloader */
ect {
};
clock-names = "bus", "sss";
};
+ timer@10050000 {
+ compatible = "google,gs101-mct",
+ "samsung,exynos4210-mct";
+ reg = <0x10050000 0x800>;
+ interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>;
+ clock-names = "fin_pll", "mct";
+ };
+
watchdog_cl0: watchdog@10060000 {
compatible = "google,gs101-wdt";
reg = <0x10060000 0x100>;
};
};
+ cmu_peric0: clock-controller@10800000 {
+ compatible = "google,gs101-cmu-peric0";
+ reg = <0x10800000 0x4000>;
+ #clock-cells = <1>;
+ clocks = <&ext_24_5m>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_IP>;
+ clock-names = "oscclk", "bus", "ip";
+ };
+
sysreg_peric0: syscon@10820000 {
compatible = "google,gs101-peric0-sysreg", "syscon";
reg = <0x10820000 0x10000>;
+ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>;
};
pinctrl_peric0: pinctrl@10840000 {
interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ usi8: usi@109700c0 {
+ compatible = "google,gs101-usi",
+ "samsung,exynos850-usi";
+ reg = <0x109700c0 0x20>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>,
+ <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>;
+ clock-names = "pclk", "ipclk";
+ samsung,sysreg = <&sysreg_peric0 0x101c>;
+ status = "disabled";
+
+ hsi2c_8: i2c@10970000 {
+ compatible = "google,gs101-hsi2c",
+ "samsung,exynosautov9-hsi2c";
+ reg = <0x10970000 0xc0>;
+ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsi2c8_bus>;
+ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>,
+ <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>;
+ clock-names = "hsi2c", "hsi2c_pclk";
+ status = "disabled";
+ };
+ };
+
usi_uart: usi@10a000c0 {
compatible = "google,gs101-usi",
"samsung,exynos850-usi";
ranges;
#address-cells = <1>;
#size-cells = <1>;
- clocks = <&dummy_clk>, <&dummy_clk>;
+ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>,
+ <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>;
clock-names = "pclk", "ipclk";
samsung,sysreg = <&sysreg_peric0 0x1020>;
samsung,mode = <USI_V2_UART>;
serial_0: serial@10a00000 {
compatible = "google,gs101-uart";
reg = <0x10a00000 0xc0>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 634
IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&dummy_clk 0>, <&dummy_clk 0>;
+ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>,
+ <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>;
clock-names = "uart", "clk_uart_baud0";
samsung,uart-fifosize = <256>;
status = "disabled";
};
};
+ cmu_peric1: clock-controller@10c00000 {
+ compatible = "google,gs101-cmu-peric1";
+ reg = <0x10c00000 0x4000>;
+ #clock-cells = <1>;
+ clocks = <&ext_24_5m>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
+ clock-names = "oscclk", "bus", "ip";
+ };
+
sysreg_peric1: syscon@10c20000 {
compatible = "google,gs101-peric1-sysreg", "syscon";
reg = <0x10c20000 0x10000>;
+ clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>;
};
pinctrl_peric1: pinctrl@10c40000 {
interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ usi12: usi@10d500c0 {
+ compatible = "google,gs101-usi",
+ "samsung,exynos850-usi";
+ reg = <0x10d500c0 0x20>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>,
+ <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>;
+ clock-names = "pclk", "ipclk";
+ samsung,sysreg = <&sysreg_peric1 0x1010>;
+ status = "disabled";
+
+ hsi2c_12: i2c@10d50000 {
+ compatible = "google,gs101-hsi2c",
+ "samsung,exynosautov9-hsi2c";
+ reg = <0x10d50000 0xc0>;
+ interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&hsi2c12_bus>;
+ pinctrl-names = "default";
+ clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>,
+ <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>;
+ clock-names = "hsi2c", "hsi2c_pclk";
+ status = "disabled";
+ };
+ };
+
pinctrl_hsi1: pinctrl@11840000 {
compatible = "google,gs101-pinctrl";
reg = <0x11840000 0x00001000>;
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1012a-dcfg",
"syscon";
- reg = <0x0 0x1ee0000 0x0 0x10000>;
+ reg = <0x0 0x1ee0000 0x0 0x1000>;
big-endian;
};
};
i2c0: i2c@2180000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
+ scl-gpios = <&gpio0 2 0>;
status = "disabled";
};
i2c1: i2c@2190000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
+ scl-gpios = <&gpio0 13 0>;
status = "disabled";
};
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
};
sata: sata@3200000 {
<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
<0x00030005 0x00000042>,
<0x00030006 0x0000004c>,
<0x00030007 0x00000056>;
- big-endian;
#thermal-sensor-cells = <1>;
};
reg = <0x00 0x03400000 0x0 0x00100000>,
<0x20 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
num-ib-windows = <24>;
num-ob-windows = <256>;
max-functions = /bits/ 8 <2>;
reg = <0x00 0x03500000 0x0 0x00100000>,
<0x28 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <6>;
status = "disabled";
reg = <0x00 0x03600000 0x0 0x00100000>,
<0x30 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <6>;
status = "disabled";
};
uart0: serial@21c0000 {
- compatible = "arm,sbsa-uart","arm,pl011";
+ compatible = "arm,pl011", "arm,primecell";
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(8)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(8)>;
+ clock-names = "uartclk", "apb_pclk";
reg = <0x0 0x21c0000 0x0 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
status = "disabled";
};
uart1: serial@21d0000 {
- compatible = "arm,sbsa-uart","arm,pl011";
+ compatible = "arm,pl011", "arm,primecell";
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(8)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(8)>;
+ clock-names = "uartclk", "apb_pclk";
reg = <0x0 0x21d0000 0x0 0x1000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
status = "disabled";
};
uart2: serial@21e0000 {
- compatible = "arm,sbsa-uart","arm,pl011";
+ compatible = "arm,pl011", "arm,primecell";
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(8)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(8)>;
+ clock-names = "uartclk", "apb_pclk";
reg = <0x0 0x21e0000 0x0 0x1000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
status = "disabled";
};
uart3: serial@21f0000 {
- compatible = "arm,sbsa-uart","arm,pl011";
+ compatible = "arm,pl011", "arm,primecell";
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(8)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(8)>;
+ clock-names = "uartclk", "apb_pclk";
reg = <0x0 0x21f0000 0x0 0x1000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
status = "disabled";
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2024 Toradex
+ */
+
+#include "imx8-apalis-eval.dtsi"
+
+/* Apalis CAN1 */
+&flexcan1 {
+ status = "okay";
+};
+
+/* Apalis CAN2 */
+&flexcan2 {
+ status = "okay";
+};
+
+/* Apalis MMC1 */
+&usdhc2 {
+ status = "okay";
+};
+
+/* Apalis SD1 */
+&usdhc3 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2024 Toradex
+ */
+
+#include "imx8-apalis-eval.dtsi"
+
+/ {
+ reg_3v3_mmc: regulator-3v3-mmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_3v3_mmc>;
+ enable-active-high;
+ gpio = <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <100000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3.3V_MMC";
+ startup-delay-us = <10000>;
+ };
+
+ reg_3v3_sd: regulator-3v3-sd {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_3v3_sd>;
+ enable-active-high;
+ gpio = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <100000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3.3V_SD";
+ startup-delay-us = <10000>;
+ };
+
+ reg_can1: regulator-can1 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_can1_power>;
+ enable-active-high;
+ gpio = <&lsio_gpio5 22 GPIO_ACTIVE_HIGH>;
+ regulator-name = "5V_SW_CAN1";
+ startup-delay-us = <10000>;
+ };
+
+ reg_can2: regulator-can2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_can2_power>;
+ enable-active-high;
+ gpio = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
+ regulator-name = "5V_SW_CAN2";
+ startup-delay-us = <10000>;
+ };
+};
+
+/* Apalis CAN1 */
+&flexcan1 {
+ xceiver-supply = <®_can1>;
+ status = "okay";
+};
+
+/* Apalis CAN2 */
+&flexcan2 {
+ xceiver-supply = <®_can2>;
+ status = "okay";
+};
+
+/* Apalis I2C1 */
+&i2c2 {
+ status = "okay";
+
+ /* Power/Current Measurement Sensor */
+ hwmon@40 {
+ compatible = "ti,ina219";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+
+ temperature-sensor@4f {
+ compatible = "ti,tmp75c";
+ reg = <0x4f>;
+ };
+
+ eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ };
+};
+
+/* Apalis MMC1 */
+&usdhc2 {
+ pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>;
+ pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>;
+ pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>;
+ pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>;
+ bus-width = <4>;
+ vmmc-supply = <®_3v3_mmc>;
+ status = "okay";
+};
+
+/* Apalis SD1 */
+&usdhc3 {
+ vmmc-supply = <®_3v3_sd>;
+ status = "okay";
+};
+
+&iomuxc {
+
+ pinctrl_enable_3v3_mmc: enable3v3mmcgrp {
+ fsl,pins = <IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 0x00000021>; /* MXM3_148 */
+ };
+
+ pinctrl_enable_3v3_sd: enable3v3sdgrp {
+ fsl,pins = <IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x00000021>; /* MXM3_152 */
+ };
+
+ pinctrl_enable_can1_power: enablecan1powergrp {
+ fsl,pins = <IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021>; /* MXM3_158 */
+ };
+
+ pinctrl_enable_can2_power: enablecan2powergrp {
+ fsl,pins = <IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021>; /* MXM3_156 */
+ };
+};
status = "okay";
};
-/* Apalis CAN1 */
-&flexcan1 {
- status = "okay";
-};
-
-/* Apalis CAN2 */
-&flexcan2 {
- status = "okay";
-};
-
-/* TODO: GPU */
-
/* Apalis I2C1 */
&i2c2 {
status = "okay";
};
/* TODO: Apalis USBH4 SuperSpeed */
-
-/* Apalis MMC1 */
-&usdhc2 {
- status = "okay";
-};
-
-/* Apalis SD1 */
-&usdhc3 {
- status = "okay";
-};
reset-assert-us = <2>;
reset-deassert-us = <2>;
reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
- reset-names = "phy";
};
};
};
* Dong Aisheng <aisheng.dong@nxp.com>
*/
+#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
clock-output-names = "audio_ipg_clk";
};
+clk_ext_aud_mclk0: clock-ext-aud-mclk0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ext_aud_mclk0";
+};
+
+clk_ext_aud_mclk1: clock-ext-aud-mclk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ext_aud_mclk1";
+};
+
+clk_esai0_rx_clk: clock-esai0-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "esai0_rx_clk";
+};
+
+clk_esai0_rx_hf_clk: clock-esai0-rx-hf {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "esai0_rx_hf_clk";
+};
+
+clk_esai0_tx_clk: clock-esai0-tx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "esai0_tx_clk";
+};
+
+clk_esai0_tx_hf_clk: clock-esai0-tx-hf {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "esai0_tx_hf_clk";
+};
+
+clk_spdif0_rx: clock-spdif0-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "spdif0_rx";
+};
+
+clk_sai0_rx_bclk: clock-sai0-rx-bclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "sai0_rx_bclk";
+};
+
+clk_sai0_tx_bclk: clock-sai0-tx-bclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "sai0_tx_bclk";
+};
+
+clk_sai1_rx_bclk: clock-sai1-rx-bclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "sai1_rx_bclk";
+};
+
+clk_sai1_tx_bclk: clock-sai1-tx-bclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "sai1_tx_bclk";
+};
+
+clk_sai2_rx_bclk: clock-sai2-rx-bclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "sai2_rx_bclk";
+};
+
+clk_sai3_rx_bclk: clock-sai3-rx-bclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "sai3_rx_bclk";
+};
+
+clk_sai4_rx_bclk: clock-sai4-rx-bclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "sai4_rx_bclk";
+};
+
audio_subsys: bus@59000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x59000000 0x0 0x59000000 0x1000000>;
+ sai0: sai@59040000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59040000 0x10000>;
+ interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai0_lpcg 1>,
+ <&clk_dummy>,
+ <&sai0_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
+ power-domains = <&pd IMX_SC_R_SAI_0>;
+ status = "disabled";
+ };
+
+ sai1: sai@59050000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59050000 0x10000>;
+ interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai1_lpcg 1>,
+ <&clk_dummy>,
+ <&sai1_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
+ power-domains = <&pd IMX_SC_R_SAI_1>;
+ status = "disabled";
+ };
+
+ sai2: sai@59060000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59060000 0x10000>;
+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai2_lpcg 1>,
+ <&clk_dummy>,
+ <&sai2_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx";
+ dmas = <&edma0 16 0 1>;
+ power-domains = <&pd IMX_SC_R_SAI_2>;
+ status = "disabled";
+ };
+
+ sai3: sai@59070000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59070000 0x10000>;
+ interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai3_lpcg 1>,
+ <&clk_dummy>,
+ <&sai3_lpcg 0>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx";
+ dmas = <&edma0 17 0 1>;
+ power-domains = <&pd IMX_SC_R_SAI_3>;
+ status = "disabled";
+ };
+
edma0: dma-controller@591f0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x591f0000 0x190000>;
<&pd IMX_SC_R_DMA_0_CH23>;
};
+ sai0_lpcg: clock-controller@59440000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59440000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "sai0_lpcg_mclk",
+ "sai0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_0>;
+ };
+
+ sai1_lpcg: clock-controller@59450000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59450000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "sai1_lpcg_mclk",
+ "sai1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_1>;
+ };
+
+ sai2_lpcg: clock-controller@59460000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59460000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "sai2_lpcg_mclk",
+ "sai2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_2>;
+ };
+
+ sai3_lpcg: clock-controller@59470000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59470000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "sai3_lpcg_mclk",
+ "sai3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_3>;
+ };
+
dsp_lpcg: clock-controller@59580000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59580000 0x10000>;
<&pd IMX_SC_R_DMA_1_CH9>,
<&pd IMX_SC_R_DMA_1_CH10>;
};
+
+ aud_rec0_lpcg: clock-controller@59d00000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59d00000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "aud_rec_clk0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
+ };
+
+ aud_rec1_lpcg: clock-controller@59d10000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59d10000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "aud_rec_clk1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
+ };
+
+ aud_pll_div0_lpcg: clock-controller@59d20000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59d20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "aud_pll_div_clk0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
+ };
+
+ aud_pll_div1_lpcg: clock-controller@59d30000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59d30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "aud_pll_div_clk1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
+ };
+
+ mclkout0_lpcg: clock-controller@59d50000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59d50000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mclkout0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MCLK_OUT_0>;
+ };
+
+ mclkout1_lpcg: clock-controller@59d60000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59d60000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mclkout1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MCLK_OUT_1>;
+ };
+
+ acm: acm@59e00000 {
+ compatible = "fsl,imx8qxp-acm";
+ reg = <0x59e00000 0x1d0000>;
+ #clock-cells = <1>;
+ power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
+ <&pd IMX_SC_R_AUDIO_CLK_1>,
+ <&pd IMX_SC_R_MCLK_OUT_0>,
+ <&pd IMX_SC_R_MCLK_OUT_1>,
+ <&pd IMX_SC_R_AUDIO_PLL_0>,
+ <&pd IMX_SC_R_AUDIO_PLL_1>,
+ <&pd IMX_SC_R_ASRC_0>,
+ <&pd IMX_SC_R_ASRC_1>,
+ <&pd IMX_SC_R_ESAI_0>,
+ <&pd IMX_SC_R_SAI_0>,
+ <&pd IMX_SC_R_SAI_1>,
+ <&pd IMX_SC_R_SAI_2>,
+ <&pd IMX_SC_R_SAI_3>,
+ <&pd IMX_SC_R_SAI_4>,
+ <&pd IMX_SC_R_SAI_5>,
+ <&pd IMX_SC_R_SPDIF_0>,
+ <&pd IMX_SC_R_MQS_0>;
+ clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
+ <&aud_rec1_lpcg IMX_LPCG_CLK_0>,
+ <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
+ <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
+ <&clk_ext_aud_mclk0>,
+ <&clk_ext_aud_mclk1>,
+ <&clk_esai0_rx_clk>,
+ <&clk_esai0_rx_hf_clk>,
+ <&clk_esai0_tx_clk>,
+ <&clk_esai0_tx_hf_clk>,
+ <&clk_spdif0_rx>,
+ <&clk_sai0_rx_bclk>,
+ <&clk_sai0_tx_bclk>,
+ <&clk_sai1_rx_bclk>,
+ <&clk_sai1_tx_bclk>,
+ <&clk_sai2_rx_bclk>,
+ <&clk_sai3_rx_bclk>,
+ <&clk_sai4_rx_bclk>;
+ clock-names = "aud_rec_clk0_lpcg_clk",
+ "aud_rec_clk1_lpcg_clk",
+ "aud_pll_div_clk0_lpcg_clk",
+ "aud_pll_div_clk1_lpcg_clk",
+ "ext_aud_mclk0",
+ "ext_aud_mclk1",
+ "esai0_rx_clk",
+ "esai0_rx_hf_clk",
+ "esai0_tx_clk",
+ "esai0_tx_hf_clk",
+ "spdif0_rx",
+ "sai0_rx_bclk",
+ "sai0_tx_bclk",
+ "sai1_rx_bclk",
+ "sai1_tx_bclk",
+ "sai2_rx_bclk",
+ "sai3_rx_bclk",
+ "sai4_rx_bclk";
+ };
};
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
- clocks = <&usb2_lpcg 0>;
+ clocks = <&usb2_lpcg IMX_LPCG_CLK_6>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
usbphy1: usbphy@5b100000 {
compatible = "fsl,imx7ulp-usbphy";
reg = <0x5b100000 0x1000>;
- clocks = <&usb2_lpcg 1>;
+ clocks = <&usb2_lpcg IMX_LPCG_CLK_7>;
power-domains = <&pd IMX_SC_R_USB_0_PHY>;
status = "disabled";
};
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
- <&sdhc0_lpcg IMX_LPCG_CLK_0>,
- <&sdhc0_lpcg IMX_LPCG_CLK_5>;
+ <&sdhc0_lpcg IMX_LPCG_CLK_5>,
+ <&sdhc0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_0>;
status = "disabled";
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b020000 0x10000>;
clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
- <&sdhc1_lpcg IMX_LPCG_CLK_0>,
- <&sdhc1_lpcg IMX_LPCG_CLK_5>;
+ <&sdhc1_lpcg IMX_LPCG_CLK_5>,
+ <&sdhc1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b030000 0x10000>;
clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
- <&sdhc2_lpcg IMX_LPCG_CLK_0>,
- <&sdhc2_lpcg IMX_LPCG_CLK_5>;
+ <&sdhc2_lpcg IMX_LPCG_CLK_5>,
+ <&sdhc2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_2>;
status = "disabled";
*/
#include <dt-bindings/clock/imx8-lpcg.h>
+#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/firmware/imx/rsrc.h>
dma_ipg_clk: clock-dma-ipg {
#size-cells = <0>;
interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&spi0_lpcg 0>,
- <&spi0_lpcg 1>;
+ clocks = <&spi0_lpcg IMX_LPCG_CLK_0>,
+ <&spi0_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <60000000>;
#size-cells = <0>;
interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&spi1_lpcg 0>,
- <&spi1_lpcg 1>;
+ clocks = <&spi1_lpcg IMX_LPCG_CLK_0>,
+ <&spi1_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <60000000>;
#size-cells = <0>;
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&spi2_lpcg 0>,
- <&spi2_lpcg 1>;
+ clocks = <&spi2_lpcg IMX_LPCG_CLK_0>,
+ <&spi2_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <60000000>;
#size-cells = <0>;
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&spi3_lpcg 0>,
- <&spi3_lpcg 1>;
+ clocks = <&spi3_lpcg IMX_LPCG_CLK_0>,
+ <&spi3_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <60000000>;
assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_0>;
- dma-names = "tx","rx";
- dmas = <&edma2 9 0 0>, <&edma2 8 0 1>;
+ dma-names = "rx", "tx";
+ dmas = <&edma2 8 0 FSL_EDMA_RX>, <&edma2 9 0 0>;
status = "disabled";
};
assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_1>;
- dma-names = "tx","rx";
- dmas = <&edma2 11 0 0>, <&edma2 10 0 1>;
+ dma-names = "rx", "tx";
+ dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 11 0 0>;
status = "disabled";
};
assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_2>;
- dma-names = "tx","rx";
- dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
+ dma-names = "rx", "tx";
+ dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>;
status = "disabled";
};
assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_3>;
- dma-names = "tx","rx";
- dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
+ dma-names = "rx", "tx";
+ dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>;
status = "disabled";
};
compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
reg = <0x5a190000 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&adma_pwm_lpcg 1>,
- <&adma_pwm_lpcg 0>;
+ clocks = <&adma_pwm_lpcg IMX_LPCG_CLK_4>,
+ <&adma_pwm_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
<&pd IMX_SC_R_DMA_2_CH15>;
};
- edma3: dma-controller@5a9f0000 {
- compatible = "fsl,imx8qm-edma";
- reg = <0x5a9f0000 0x90000>;
- #dma-cells = <3>;
- dma-channels = <8>;
- interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
- <&pd IMX_SC_R_DMA_3_CH1>,
- <&pd IMX_SC_R_DMA_3_CH2>,
- <&pd IMX_SC_R_DMA_3_CH3>,
- <&pd IMX_SC_R_DMA_3_CH4>,
- <&pd IMX_SC_R_DMA_3_CH5>,
- <&pd IMX_SC_R_DMA_3_CH6>,
- <&pd IMX_SC_R_DMA_3_CH7>;
- };
-
spi0_lpcg: clock-controller@5a400000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a400000 0x10000>;
reg = <0x5a880000 0x10000>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adc0_lpcg 0>,
- <&adc0_lpcg 1>;
+ clocks = <&adc0_lpcg IMX_LPCG_CLK_0>,
+ <&adc0_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
reg = <0x5a890000 0x10000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adc1_lpcg 0>,
- <&adc1_lpcg 1>;
+ clocks = <&adc1_lpcg IMX_LPCG_CLK_0>,
+ <&adc1_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
reg = <0x5a8d0000 0x10000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&can0_lpcg 1>,
- <&can0_lpcg 0>;
+ clocks = <&can0_lpcg IMX_LPCG_CLK_4>,
+ <&can0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <40000000>;
* CAN1 shares CAN0's clock and to enable CAN0's clock it
* has to be powered on.
*/
- clocks = <&can0_lpcg 1>,
- <&can0_lpcg 0>;
+ clocks = <&can0_lpcg IMX_LPCG_CLK_4>,
+ <&can0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <40000000>;
* CAN2 shares CAN0's clock and to enable CAN0's clock it
* has to be powered on.
*/
- clocks = <&can0_lpcg 1>,
- <&can0_lpcg 0>;
+ clocks = <&can0_lpcg IMX_LPCG_CLK_4>,
+ <&can0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <40000000>;
status = "disabled";
};
+ edma3: dma-controller@5a9f0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x5a9f0000 0x90000>;
+ #dma-cells = <3>;
+ dma-channels = <8>;
+ interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
+ <&pd IMX_SC_R_DMA_3_CH1>,
+ <&pd IMX_SC_R_DMA_3_CH2>,
+ <&pd IMX_SC_R_DMA_3_CH3>,
+ <&pd IMX_SC_R_DMA_3_CH4>,
+ <&pd IMX_SC_R_DMA_3_CH5>,
+ <&pd IMX_SC_R_DMA_3_CH6>,
+ <&pd IMX_SC_R_DMA_3_CH7>;
+ };
+
i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+gpu0_subsys: bus@53000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x53000000 0x0 0x53000000 0x1000000>;
+
+ gpu_3d0: gpu@53100000 {
+ compatible = "vivante,gc";
+ reg = <0x53100000 0x40000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
+ clock-names = "core", "shader";
+ assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
+ assigned-clock-rates = <700000000>, <850000000>;
+ power-domains = <&pd IMX_SC_R_GPU_0_PID0>;
+ };
+};
compatible = "fsl,imx27-pwm";
reg = <0x5d000000 0x10000>;
clock-names = "ipg", "per";
- clocks = <&pwm0_lpcg 4>,
- <&pwm0_lpcg 1>;
+ clocks = <&pwm0_lpcg IMX_LPCG_CLK_6>,
+ <&pwm0_lpcg IMX_LPCG_CLK_1>;
assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <3>;
compatible = "fsl,imx27-pwm";
reg = <0x5d010000 0x10000>;
clock-names = "ipg", "per";
- clocks = <&pwm1_lpcg 4>,
- <&pwm1_lpcg 1>;
+ clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>,
+ <&pwm1_lpcg IMX_LPCG_CLK_1>;
assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <3>;
compatible = "fsl,imx27-pwm";
reg = <0x5d020000 0x10000>;
clock-names = "ipg", "per";
- clocks = <&pwm2_lpcg 4>,
- <&pwm2_lpcg 1>;
+ clocks = <&pwm2_lpcg IMX_LPCG_CLK_6>,
+ <&pwm2_lpcg IMX_LPCG_CLK_1>;
assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <3>;
compatible = "fsl,imx27-pwm";
reg = <0x5d030000 0x10000>;
clock-names = "ipg", "per";
- clocks = <&pwm3_lpcg 4>,
- <&pwm3_lpcg 1>;
+ clocks = <&pwm3_lpcg IMX_LPCG_CLK_6>,
+ <&pwm3_lpcg IMX_LPCG_CLK_1>;
assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <3>;
status = "disabled";
};
+ reg_can0_stby: regulator-4 {
+ compatible = "regulator-fixed";
+ regulator-name = "can0-stby";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can1_stby: regulator-5 {
+ compatible = "regulator-fixed";
+ regulator-name = "can1-stby";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_usdhc2_vmmc: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
};
};
+&i2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ pca6416_3: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&lsio_gpio2>;
+ interrupts = <5 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pca9548_2: i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+ };
+ };
+};
+
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_can0_stby>;
+ status = "okay";
+};
+
+&flexcan3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan3>;
+ xceiver-supply = <®_can1_stby>;
+ status = "okay";
+};
+
&lsio_gpio4 {
status = "okay";
};
>;
};
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021
+ IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021
+ >;
+ };
+
+ pinctrl_flexcan3: flexcan3grp {
+ fsl,pins = <
+ IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021
+ IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021
+ >;
+ };
+
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
};
+&edma0 {
+ reg = <0x591f0000 0x1a0000>;
+ #dma-cells = <3>;
+ dma-channels = <25>;
+ dma-channel-mask = <0x1c0cc0>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */
+ power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
+ <&pd IMX_SC_R_DMA_0_CH1>,
+ <&pd IMX_SC_R_DMA_0_CH2>,
+ <&pd IMX_SC_R_DMA_0_CH3>,
+ <&pd IMX_SC_R_DMA_0_CH4>,
+ <&pd IMX_SC_R_DMA_0_CH5>,
+ <&pd IMX_SC_R_DMA_0_CH6>,
+ <&pd IMX_SC_R_DMA_0_CH7>,
+ <&pd IMX_SC_R_DMA_0_CH8>,
+ <&pd IMX_SC_R_DMA_0_CH9>,
+ <&pd IMX_SC_R_DMA_0_CH10>,
+ <&pd IMX_SC_R_DMA_0_CH11>,
+ <&pd IMX_SC_R_DMA_0_CH12>,
+ <&pd IMX_SC_R_DMA_0_CH13>,
+ <&pd IMX_SC_R_DMA_0_CH14>,
+ <&pd IMX_SC_R_DMA_0_CH15>,
+ <&pd IMX_SC_R_DMA_0_CH16>,
+ <&pd IMX_SC_R_DMA_0_CH17>,
+ <&pd IMX_SC_R_DMA_0_CH18>,
+ <&pd IMX_SC_R_DMA_0_CH19>,
+ <&pd IMX_SC_R_DMA_0_CH20>,
+ <&pd IMX_SC_R_DMA_0_CH21>,
+ <&pd IMX_SC_R_DMA_0_CH22>,
+ <&pd IMX_SC_R_DMA_0_CH23>,
+ <&pd IMX_SC_R_DMA_0_CH24>;
+};
+
&edma2 {
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
};
+&flexcan1 {
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&flexcan2 {
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&flexcan3 {
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&i2c0 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ dma-names = "tx","rx";
+ dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL_EDMA_RX>;
};
&i2c1 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ dma-names = "tx","rx";
+ dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL_EDMA_RX>;
};
&i2c2 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ dma-names = "tx","rx";
+ dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL_EDMA_RX>;
};
&i2c3 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ dma-names = "tx","rx";
+ dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL_EDMA_RX>;
};
&lpuart0 {
*/
#include <dt-bindings/clock/imx8-clock.h>
+#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
+/*
+ * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+/dts-v1/;
+
+#include "imx8dxp-tqma8xdp.dtsi"
+#include "mba8xx.dtsi"
+
+/ {
+ model = "TQ-Systems i.MX8DXP TQMa8XDP on MBa8Xx";
+ compatible = "tq,imx8dxp-tqma8xdp-mba8xx", "tq,imx8dxp-tqma8xdp", "fsl,imx8dxp";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
+/*
+ * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+#include "imx8dxp.dtsi"
+#include "tqma8xx.dtsi"
+
+/ {
+ model = "TQ-Systems i.MX8DXP TQMa8XDP";
+ compatible = "tq,imx8dxp-tqma8xdp", "fsl,imx8dxp";
+};
+
+&pmic_thermal {
+ cooling-maps {
+ map0 {
+ cooling-device =
+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8qxp.dtsi"
+
+/delete-node/ &A35_2;
+/delete-node/ &A35_3;
+
+&thermal_zones {
+ cpu0-thermal {
+ cooling-maps {
+ map0 {
+ cooling-device =
+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
};
};
+
+ sound-micfil {
+ compatible = "fsl,imx-audio-card";
+ model = "micfil-audio";
+
+ pri-dai-link {
+ link-name = "micfil hifi";
+ format = "i2s";
+
+ cpu {
+ sound-dai = <&micfil>;
+ };
+ };
+ };
+
+ sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif1>;
+ spdif-out;
+ spdif-in;
+ };
};
&A53_0 {
status = "okay";
};
+&micfil {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pdm>;
+ assigned-clocks = <&clk IMX8MM_CLK_PDM>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <196608000>;
+ status = "okay";
+};
+
&mipi_csi {
status = "okay";
status = "okay";
};
+&spdif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spdif1>;
+ assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
+ <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
+ <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
+ <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
+ clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
+ "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba",
+ "pll8k", "pll11k";
+ status = "okay";
+};
+
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
>;
};
+ pinctrl_pdm: pdmgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
+ MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
+ MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
+ MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
+ MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
+ MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
+ >;
+ };
+
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
>;
};
+ pinctrl_spdif1: spdif1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
+ MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
+ >;
+ };
+
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_led>;
led1 {
label = "led1";
- gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led2 {
label = "led2";
- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
};
led3 {
label = "led3";
- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
};
};
reg_rst_eth2: regulator-rst-eth2 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_eth2>;
- gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-name = "rst-usb-eth2";
};
- reg_usb1_vbus: regulator-usb1-vbus {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb1_vbus>;
- gpio = <&gpio3 25 GPIO_ACTIVE_LOW>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-name = "usb1-vbus";
- };
-
reg_vdd_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-always-on;
};
&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
can@0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
clocks = <&osc_can>;
- interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>;
/*
* Limit the SPI clock to 15 MHz to prevent issues
* with corrupted data due to chip errata.
};
&ecspi3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi3>;
- cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
status = "okay";
eeram@0 {
&fec1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
- phy-connection-type = "rgmii-rxid";
+ pinctrl-0 = <&pinctrl_enet_rgmii>;
+ phy-connection-type = "rgmii-id";
phy-handle = <ðphy>;
status = "okay";
#size-cells = <0>;
ethphy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id4f51.e91b";
reg = <0>;
- reset-assert-us = <1>;
- reset-deassert-us = <15000>;
- reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
};
};
};
+/*
+ * Rename SoM signals according to board usage:
+ * GPIO_B_0 -> DIO1_OUT
+ * GPIO_B_1 -> DIO2_OUT
+ */
&gpio1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio1>;
- gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out",
- "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
+ gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1",
+ "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4",
+ "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "DIO1_OUT",
+ "DIO2_OUT", "USB_A_OC#", "CAM_MCK", "USB_B_OC#",
+ "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3",
+ "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1",
+ "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)",
+ "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)",
+ "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0",
+ "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2",
+ "ETH_A_(R)(G)MII_RXD3";
};
-&gpio5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio5>;
- gpio-line-names = "", "", "dio4-in", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
+/*
+ * Rename SoM signals according to board usage:
+ * GPIO_B_2 -> DIO3_OUT
+ * GPIO_B_3 -> DIO4_OUT
+ */
+&gpio3 {
+ gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5",
+ "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1",
+ "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1",
+ "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4",
+ "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "DIO3_OUT",
+ "USB_B_EN", "DIO4_OUT", "PCIe_CLKREQ#", "PCIe_A_PERST#",
+ "PCIe_WAKE#", "USB_A_EN";
};
-&i2c4 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
+/*
+ * Rename SoM signals according to board usage:
+ * GPIO_B_4 -> DIO1_IN
+ * GPIO_B_5 -> DIO2_IN
+ * GPIO_B_6 -> DIO3_IN
+ * GPIO_B_7 -> DIO4_IN
+ */
+&gpio4 {
+ gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN",
+ "DIO1_IN", "BOOT_SEL0#", "BOOT_SEL1#", "",
+ "", "", "I2S_LRCLK", "I2S_BITCLK",
+ "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "DIO2_IN", "DIO3_IN",
+ "DIO4_IN", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6",
+ "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS",
+ "UART_A_RTS", "", "", "",
+ "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX";
+};
+
+&i2c3 {
status = "okay";
+
+ usb-hub@2c {
+ compatible = "microchip,usb2514b";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_hub>;
+ reg = <0x2c>;
+ non-removable-ports = <0>, <3>;
+ reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ };
};
&pwm2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
+®_usb2_vbus {
+ status = "disabled";
+};
+
+®_usdhc2_vcc {
+ status = "disabled";
+};
+
+®_usdhc3_vcc {
+ status = "disabled";
+};
+
&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
uart-has-rtscts;
status = "okay";
&usbotg1 {
dr_mode = "otg";
- disable-over-current;
- vbus-supply = <®_usb1_vbus>;
status = "okay";
};
#size-cells = <0>;
status = "okay";
+ /* VBUS is controlled by the hub */
+ /delete-property/ vbus-supply;
+
usb1@1 {
- compatible = "usb424,9514";
+ compatible = "usb424,2514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
usbnet: ethernet@1 {
- compatible = "usb424,ec00";
+ compatible = "usbb95,772b";
reg = <1>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vmmc-supply = <®_vdd_3v3>;
- vqmmc-supply = <®_nvcc_sd>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
&iomuxc {
pinctrl_can: cangrp {
fsl,pins = <
- MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
- >;
- };
-
- pinctrl_ecspi2: ecspi2grp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
- >;
- };
-
- pinctrl_ecspi3: ecspi3grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
- MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
- MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
- MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
- >;
- };
-
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */
- MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */
- >;
- };
-
- pinctrl_gpio_led: gpioledgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19
- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
- >;
- };
-
- pinctrl_gpio1: gpio1grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
- MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
- >;
- };
-
- pinctrl_gpio5: gpio5grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
- >;
- };
-
- pinctrl_pwm2: pwm2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
- >;
- };
-
- pinctrl_reg_usb1_vbus: regusb1vbusgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
- MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
- MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
- MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
- MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
- MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
- >;
- };
-
- pinctrl_usb_eth2: usbeth2grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */
>;
};
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ pinctrl_usb_hub: usbhubgrp {
fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */
>;
};
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
- MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
- MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
- MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
- MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
+ MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0
+ MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0
+ MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0
+ MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
- MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
- MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
- MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
+ MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0
+ MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0
+ MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0
+ MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
};
* Copyright (C) 2022 Kontron Electronics GmbH
*/
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx8mm.dtsi"
chosen {
stdout-path = &uart3;
};
+
+ reg_vdd_carrier: regulator-vdd-carrier {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_vdd_carrier>;
+ gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "VDD_CARRIER";
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+
+ regulator-state-disk {
+ regulator-off-in-suspend;
+ };
+ };
+
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1_vbus>;
+ enable-active-high;
+ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "VBUS_USB1";
+ };
+
+ reg_usb2_vbus: regulator-usb2-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2_vbus>;
+ enable-active-high;
+ gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "VBUS_USB2";
+ };
+
+ reg_usdhc2_vcc: regulator-usdhc2-vcc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>;
+ enable-active-high;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "VCC_SDIO_A";
+ };
+
+ reg_usdhc3_vcc: regulator-usdhc3-vcc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc3_vcc>;
+ enable-active-high;
+ gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "VCC_SDIO_B";
+ };
};
&A53_0 {
};
};
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_ecspi2_gpio>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>;
+ gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1",
+ "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4",
+ "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "GPIO_B_0",
+ "GPIO_B_1", "USB_A_OC#", "CAM_MCK", "USB_B_OC#",
+ "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3",
+ "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1",
+ "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)",
+ "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)",
+ "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0",
+ "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2",
+ "ETH_A_(R)(G)MII_RXD3";
+};
+
+&gpio2 {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "SDIO_A_CD#", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",
+ "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN",
+ "SDIO_A_WP";
+};
+
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio3>;
+ gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5",
+ "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1",
+ "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1",
+ "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4",
+ "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_2",
+ "USB_B_EN", "GPIO_B_3", "PCIe_CLKREQ#", "PCIe_A_PERST#",
+ "PCIe_WAKE#", "USB_A_EN";
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio4>;
+ gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN",
+ "GPIO_B_4", "BOOT_SEL0#", "BOOT_SEL1#", "",
+ "", "", "I2S_LRCLK", "I2S_BITCLK",
+ "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "GPIO_B_5", "GPIO_B_6",
+ "GPIO_B_7", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6",
+ "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS",
+ "UART_A_RTS", "", "", "",
+ "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX";
+};
+
+&gpio5 {
+ gpio-line-names = "UART_B_TX", "SDIO_B_PWR_EN", "SDIO_B_WP", "PWM_2",
+ "PWM_1", "PWM_0", "", "",
+ "", "", "SPI_A_SCK", "SPI_A_SDO_(IO1)",
+ "SPI_A_SCK", "SPI_A_CS0#", "", "",
+ "I2C_A_SCL", "I2C_A_SDA", "I2C_B_SCL", "I2C_B_SDA",
+ "PCIe_SMCLK", "PCIe_SMDAT", "SPI_B_SCK", "SPI_B_SDO",
+ "SPI_B_SDI", "SPI_B_CS0#", "UART_CON_RX", "UART_CON_TX",
+ "UART_C_RX", "UART_C_TX";
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
};
};
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ address-width = <16>;
+ pagesize = <32>;
+ size = <8192>;
+ };
+
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
- interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>;
- trickle-diode-disable;
+ interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_LOW>;
};
};
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+};
+
&uart3 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ vbus-supply = <®_usb1_vbus>;
+};
+
+&usbotg2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ vbus-supply = <®_usb2_vbus>;
+};
+
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
status = "okay";
};
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ vmmc-supply = <®_usdhc2_vcc>;
+ vqmmc-supply = <®_nvcc_sd>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
+ vmmc-supply = <®_usdhc3_vcc>;
+ vqmmc-supply = <®_nvcc_sd>;
+ cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
+};
+
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
};
&iomuxc {
+ pinctrl_csi_mck: csimckgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 /* CAM_MCK */
+ >;
+ };
+
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
>;
};
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 /* SPI_A_SDI_(IO0) */
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 /* SPI_A_SDO_(IO1) */
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 /* SPI_A_SCK */
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* SPI_A_CS0# */
+ >;
+ };
+
+ pinctrl_ecspi2_gpio: ecspi2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* SPI_A_/WP_(IO2) */
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* SPI_A_/HOLD_(IO3) */
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 /* SPI_B_SDI */
+ MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 /* SPI_B_SDO */
+ MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 /* SPI_B_SCK */
+ MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* SPI_B_CS0# */
+ >;
+ };
+
+ pinctrl_enet_rgmii: enetrgmiigrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */
+ >;
+ };
+
+ pinctrl_enet_rmii: enetrmiigrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */
+ MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f /* ETH_A_(S)(R)(G)MII_TXD2 */
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 /* ETH_A_(S)(R)(G)MII_TXD1 */
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 /* ETH_A_(S)(R)(G)MII_TXD0 */
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 /* ETH_A_(S)(R)(G)MII_RXD1 */
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 /* ETH_A_(S)(R)(G)MII_RXD0 */
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 /* ETH_A_(R)(G)MII_RX_CLK */
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 /* ETH_A_(R)(G)MII_RX_DV(_ER) */
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 /* ETH_A_(R)(G)MII_TX_EN(_ER) */
+ >;
+ };
+
+ pinctrl_gpio1: gpio1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* GPIO_A_0 */
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* GPIO_A_1 */
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* GPIO_A_2 */
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* GPIO_A_3 */
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* GPIO_A_4 */
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 /* GPIO_A_5 */
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* GPIO_A_6 */
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* GPIO_A_7 */
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* GPIO_B_0 */
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* GPIO_B_1 */
+ >;
+ };
+
+ pinctrl_gpio3: gpio3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* GPIO_C_5 */
+ MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* GPIO_C_4 */
+ MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* GPIO_C_0 */
+ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* GPIO_C_1 */
+ MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* GPIO_C_2 */
+ MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* GPIO_C_3 */
+ MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* GPIO_B_2 */
+ MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* GPIO_B_3 */
+ >;
+ };
+
+ pinctrl_gpio4: gpio4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* GPIO_C_7 */
+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* GPIO_B_4 */
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* BOOT_SEL0# */
+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* BOOT_SEL1# */
+ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* GPIO_B_5 */
+ MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* GPIO_B_6 */
+ MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* GPIO_B_7 */
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* GPIO_C_6 */
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 /* I2C_B_SCL */
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 /* I2C_B_SDA */
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 /* PCIe_SMCLK and I2C_CAM_SCL/CSI_TX_P */
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 /* PCIe_SMDAT and I2C_CAM_SDA/CSI_TX_N */
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* PCIe_CLKREQ# */
+ MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* PCIe_A_PERST# */
+ MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* PCIe_WAKE# */
+ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* PCIe_SM_ALERT */
>;
};
>;
};
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19 /* PWM_0 */
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 /* PWM_1 */
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x19 /* PWM_2 */
+ >;
+ };
+
+ pinctrl_reg_usb1_vbus: regusb1vbusgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* USB_A_EN */
+ >;
+ };
+
+ pinctrl_reg_usb2_vbus: regusb2vbusgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* USB_B_EN */
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19 /* SDIO_A_PWR_EN */
+ >;
+ };
+
+ pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */
+ >;
+ };
+
+ pinctrl_reg_vdd_carrier: regvddcarriergrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* CARRIER_PWR_EN */
+ >;
+ };
+
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19
>;
};
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 /* I2S_A_DATA_IN */
+ MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 /* I2S_A_DATA_OUT */
+ MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 /* I2S_B_DATA_IN */
+ MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 /* I2S_B_DATA_OUT */
+ MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 /* I2S_MCLK */
+ MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 /* I2S_LRCLK */
+ MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 /* I2S_BITCLK */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 /* UART_A_RX */
+ MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 /* UART_A_TX */
+ MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 /* UART_A_CTS */
+ MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 /* UART_A_RTS */
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 /* UART_B_RX */
+ MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 /* UART_B_TX */
+ MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 /* UART_B_CTS */
+ MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 /* UART_B_RTS */
+ >;
+ };
+
pinctrl_uart3: uart3grp {
fsl,pins = <
- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 /* UART_CON_RX */
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 /* UART_CON_TX */
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x0 /* UART_C_RX */
+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0 /* UART_C_TX */
+ >;
+ };
+
+ pinctrl_usb1: usb1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 /* USB_A_OC# */
+ >;
+ };
+
+ pinctrl_usb2: usb2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x19 /* USB_B_OC# */
>;
};
>;
};
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 /* SDIO_A_CLK */
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SDIO_A_CMD */
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */
+ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 /* SDIO_A_CLK */
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 /* SDIO_A_CMD */
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */
+ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 /* SDIO_A_CLK */
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 /* SDIO_A_CMD */
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */
+ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 /* SDIO_A_CD# */
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x90 /* SDIO_B_CLK */
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x90 /* SDIO_B_CMD */
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x90 /* SDIO_B_D0 */
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x90 /* SDIO_B_D1 */
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x90 /* SDIO_B_D2 */
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x90 /* SDIO_B_D3 */
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x90 /* SDIO_B_D4 */
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x90 /* SDIO_B_D5 */
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x90 /* SDIO_B_D6 */
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x90 /* SDIO_B_D7 */
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x94 /* SDIO_B_CLK */
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x94 /* SDIO_B_CMD */
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x94 /* SDIO_B_D0 */
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x94 /* SDIO_B_D1 */
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x94 /* SDIO_B_D2 */
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x94 /* SDIO_B_D3 */
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x94 /* SDIO_B_D4 */
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x94 /* SDIO_B_D5 */
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x94 /* SDIO_B_D6 */
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x94 /* SDIO_B_D7 */
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x96 /* SDIO_B_CLK */
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x96 /* SDIO_B_CMD */
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x96 /* SDIO_B_D0 */
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x96 /* SDIO_B_D1 */
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x96 /* SDIO_B_D2 */
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x96 /* SDIO_B_D3 */
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x96 /* SDIO_B_D4 */
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x96 /* SDIO_B_D5 */
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x96 /* SDIO_B_D6 */
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x96 /* SDIO_B_D7 */
+ >;
+ };
+
+ pinctrl_usdhc3_gpio: usdhc3gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* SDIO_B_CD# */
+ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */
+ >;
+ };
+
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
pinctrl_i2c1: i2c1grp {
fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083
>;
};
/dts-v1/;
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
#include "imx8mm-tqma8mqml.dtsi"
#include "mba8mx.dtsi"
};
&pcie_phy {
- clocks = <&pcie0_refclk>;
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,clkreq-unsupported;
+ clocks = <&pcieclk 2>;
+ clock-names = "ref";
status = "okay";
};
+/* PCIe slot on X36 */
&pcie0 {
reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 3>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
+ <&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
-
- reg_usb_otg1_vbus: regulator-usb-otg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb1_en>;
- compatible = "regulator-fixed";
- regulator-name = "usb_otg1_vbus";
- gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
};
-/* off-board header */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio1 {
};
&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
dr_mode = "otg";
over-current-active-low;
- vbus-supply = <®_usb_otg1_vbus>;
status = "okay";
};
>;
};
- pinctrl_reg_usb1_en: regusb1grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141
- MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
- >;
- };
-
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141
+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
+ >;
+ };
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
+ <&gpio4 24 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
spi-max-frequency = <40000000>;
status = "okay";
};
+
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&fec1 {
&gpio4 {
gpio-line-names = "", "", "", "",
- "", "", "uart3_rs232#", "uart3_rs422#",
+ "dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#",
"uart3_rs485#", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
pinctrl_hog: hoggrp {
fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIG1_CTL */
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000041 /* DIG2_CTL */
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
+ MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140
>;
};
};
&lcdif {
- assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>;
- assigned-clock-rates = <594000000>;
status = "okay";
};
spdif-out;
spdif-in;
};
+
+ sound-micfil {
+ compatible = "fsl,imx-audio-card";
+ model = "micfil-audio";
+
+ pri-dai-link {
+ link-name = "micfil hifi";
+ format = "i2s";
+
+ cpu {
+ sound-dai = <&micfil>;
+ };
+ };
+ };
};
&easrc {
status = "okay";
};
+&micfil {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pdm>;
+ assigned-clocks = <&clk IMX8MN_CLK_PDM>;
+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <196608000>;
+ status = "okay";
+};
+
&mipi_csi {
status = "okay";
>;
};
+ pinctrl_pdm: pdmgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
+ MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
+ MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
+ MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6
+ MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6
+ MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6
+ MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6
+ >;
+ };
+
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
/ {
model = "RVE gateway";
- compatible = "rve,rve-gateway", "variscite,var-som-mx8mn", "fsl,imx8mn";
+ compatible = "rve,gateway", "variscite,var-som-mx8mn", "fsl,imx8mn";
crystal_duart_24m: crystal-duart-24m {
compatible = "fixed-clock";
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mn-pinfunc.h"
+
+&{/} {
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ label = "X19";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_connector>;
+ id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+};
+
+&rst_usb_hub_hog {
+ output-low;
+};
+
+&sel_usb_hub_hog {
+ output-low;
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ power-active-high;
+ /delete-property/ disable-over-current;
+ over-current-active-low;
+ usb-role-switch;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_usb1_connector: usb1-connectorgrp {
+ fsl,pins = <MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c0>;
+ };
+};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0hub_sel>;
- sel-usb-hub-hog {
+ sel_usb_hub_hog: sel-usb-hub-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-high;
pinctrl_usbotg: usbotggrp {
fsl,pins = <MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x84>,
- <MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x84>,
- <MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x1C4>;
+ <MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x84>;
};
pinctrl_usdhc2: usdhc2grp {
<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rates = <266000000>,
<24000000>,
- <594000000>,
+ <24000000>,
<500000000>,
<200000000>;
#power-domain-cells = <1>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
snps,force_thresh_dma_mode;
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
status = "okay";
mdio {
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
};
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <5>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0xf0>;
+ snps,map-to-dma-channel = <4>;
+ };
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <5>;
+ snps,tx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0xf0>;
+ };
+ };
};
&flexspi {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8997-bt";
+ };
};
&usdhc1 {
/dts-v1/;
#include <dt-bindings/net/qca-ar803x.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp.dtsi"
/ {
clock-frequency = <25000000>;
};
+ clk_pwm4: clock-pwm4 {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ clock-output-names = "codec-pwm4";
+ /*
+ * 1 / 83 ns ~= 12 MHz , but since the PWM input clock is 24 MHz
+ * and the calculated PWM period is 1 and duty cycle is 50%, the
+ * result is exactly 12 MHz, which is fine for SGTL5000 MCLK.
+ */
+ pwms = <&pwm4 0 83 0>;
+ };
+
panel: panel {
/* Compatible string is filled in by panel board DT Overlay. */
backlight = <&backlight>;
vin-supply = <&buck4>;
};
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SGTL5000-Card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,widgets = "Headphone", "Headphone Jack";
+ simple-audio-card,routing = "Headphone Jack", "HP_OUT";
+
+ cpu_dai: simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ };
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ };
+ };
+
watchdog { /* TPS3813 */
compatible = "linux,wdt-gpio";
pinctrl-names = "default";
flash@0 { /* W25Q128JVEI */
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <100000000>; /* Up to 133 MHz */
+ spi-max-frequency = <40000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
+ sgtl5000: audio-codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ clocks = <&clk_pwm4>;
+ VDDA-supply = <&buck4>;
+ VDDIO-supply = <&buck4>;
+ };
+
usb-hub@2c {
compatible = "microchip,usb2514bi";
reg = <0x2c>;
status = "okay";
};
+&pcie_phy {
+ clocks = <&pcieclk 0>;
+ clock-names = "ref";
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ fsl,max-link-speed = <3>;
+ reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel_pwm>;
status = "disabled";
};
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&sai3 {
+ #clock-cells = <0>;
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <12288000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ status = "okay";
+};
+
/* SD slot */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
>;
};
+ pinctrl_pwm4: pwm4-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0xd6
+ >;
+ };
+
pinctrl_rtc: rtc-grp {
fsl,pins = <
/* RTC_IRQ# */
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
- MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
>;
};
port {
hdmi_connector_in: endpoint {
- remote-endpoint = <&adv7533_out>;
+ remote-endpoint = <&adv7535_out>;
};
};
};
enable-active-high;
};
+ reg_vext_3v3: regulator-vext-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VEXT_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8960-audio";
regulator-always-on;
};
- BUCK5 {
+ reg_buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
hdmi@3d {
compatible = "adi,adv7535";
- reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
- reg-names = "main", "cec", "edid", "packet";
+ reg = <0x3d>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
adi,dsi-lanes = <4>;
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
+ avdd-supply = <®_buck5>;
+ dvdd-supply = <®_buck5>;
+ pvdd-supply = <®_buck5>;
+ a2vdd-supply = <®_buck5>;
+ v3p3-supply = <®_vext_3v3>;
+ v1p2-supply = <®_buck5>;
ports {
#address-cells = <1>;
port@0 {
reg = <0>;
- adv7533_in: endpoint {
+ adv7535_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
port@1 {
reg = <1>;
- adv7533_out: endpoint {
+ adv7535_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
reg = <1>;
dsi_out: endpoint {
- remote-endpoint = <&adv7533_in>;
+ remote-endpoint = <&adv7535_in>;
data-lanes = <1 2 3 4>;
};
};
stdout-path = &uart1;
};
+ backlight_lvds: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds1>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <11>;
+ enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
+ num-interpolated-steps = <2>;
+ power-supply = <®_lvds1_reg_en>;
+ pwms = <&pwm3 0 50000 0>;
+ };
+
+ panel1_lvds: panel-lvds {
+ compatible = "edt,etml1010g3dra";
+ backlight = <&backlight_lvds>;
+ power-supply = <®_vcc_3v3_sw>;
+
+ port {
+ panel1_in: endpoint {
+ remote-endpoint = <&ldb_lvds_ch1>;
+ };
+ };
+ };
+
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
pinctrl-names = "default";
regulator-name = "can2-stby";
};
+ reg_lvds1_reg_en: regulator-lvds1 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-name = "lvds1_reg_en";
+ };
+
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
+
+ reg_vcc_3v3_sw: regulator-vcc-3v3-sw {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3_SW";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&eqos {
};
};
+&lcdif2 {
+ status = "okay";
+};
+
+&lvds_bridge {
+ status = "okay";
+
+ ports {
+ port@2 {
+ ldb_lvds_ch1: endpoint {
+ remote-endpoint = <&panel1_in>;
+ };
+ };
+ };
+};
+
&snvs_pwrkey {
status = "okay";
};
+&pwm3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+};
+
+&rv3028 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+ trickle-resistor-ohms = <3000>;
+};
+
/* debug console */
&uart1 {
pinctrl-names = "default";
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
>;
};
>;
};
+ pinctrl_lvds1: lvds1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
+ pinctrl_rtc: rtcgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
>;
};
pinctrl_usdhc2_pins: usdhc2-gpiogrp {
fsl,pins = <
- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40
>;
};
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
- trickle-resistor-ohms = <3000>;
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio4 {
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};
pinctrl-0 = <&pinctrl_usbcon1>;
type = "micro";
label = "otg";
+ vbus-supply = <®_usb1_vbus>;
id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
port {
};
&usb3_phy0 {
- vbus-supply = <®_usb1_vbus>;
status = "okay";
};
pinctrl-0 = <&pinctrl_usbcon1>;
type = "micro";
label = "otg";
+ vbus-supply = <®_usb1_vbus>;
id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
port {
};
&usb3_phy0 {
- vbus-supply = <®_usb1_vbus>;
status = "okay";
};
regulator-name = "On-module +V3.3_ADC (LDO4)";
};
- LDO5 {
+ reg_vdd_sdio: LDO5 {
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
vmmc-supply = <®_usdhc2_vmmc>;
+ vqmmc-supply = <®_vdd_sdio>;
};
/* On-module eMMC */
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
- assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
+ <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <500000000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
status = "disabled";
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
- assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
+ <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <266000000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
status = "disabled";
id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- pcie1_refclk: pcie1-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
reg_otg_vbus: regulator-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
};
+/* PCIe slot on X36 */
&pcie0 {
reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
- <&pcie0_refclk>,
- <&clk IMX8MQ_CLK_PCIE1_PHY>,
+ <&pcieclk 3>,
+ <&pcieclk 2>,
<&clk IMX8MQ_CLK_PCIE1_AUX>;
status = "okay";
};
/*
- * miniPCIe, also usable for cards with USB. Therefore configure the reset as
+ * miniPCIe on X28, also usable for cards with USB. Therefore configure the reset as
* static gpio hog.
*/
&pcie1 {
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
- <&pcie1_refclk>,
- <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&pcieclk 1>,
+ <&pcieclk 0>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
status = "okay";
};
};
&usb3_phy1 {
+ vbus-supply = <®_hub_vbus>;
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2024 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8qm-apalis.dtsi"
+#include "imx8-apalis-eval-v1.2.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board V1.2";
+ compatible = "toradex,apalis-imx8-eval-v1.2",
+ "toradex,apalis-imx8",
+ "fsl,imx8qm";
+};
/dts-v1/;
#include "imx8qm-apalis.dtsi"
-#include "imx8-apalis-eval.dtsi"
+#include "imx8-apalis-eval-v1.1.dtsi"
/ {
model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2024 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8qm-apalis-v1.1.dtsi"
+#include "imx8-apalis-eval-v1.2.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board V1.2";
+ compatible = "toradex,apalis-imx8-v1.1-eval-v1.2",
+ "toradex,apalis-imx8-v1.1",
+ "fsl,imx8qm";
+};
+
+/* Apalis MMC1 */
+&usdhc2 {
+ /delete-property/ no-1-8-v;
+};
+
+/* Apalis SD1 */
+&usdhc3 {
+ /delete-property/ no-1-8-v;
+};
/dts-v1/;
#include "imx8qm-apalis-v1.1.dtsi"
-#include "imx8-apalis-eval.dtsi"
+#include "imx8-apalis-eval-v1.1.dtsi"
/ {
model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board";
};
};
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
};
&iomuxc {
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
+ IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1gpio-grp {
+ fsl,pins = <
+ IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c
+ IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c
+ >;
+ };
+
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
&fec1 {
compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
+ iommus = <&smmu 0x12 0x7f80>;
};
&fec2 {
compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
+ iommus = <&smmu 0x12 0x7f80>;
};
&usdhc1 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
+ iommus = <&smmu 0x11 0x7f80>;
};
&usdhc2 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
+ iommus = <&smmu 0x11 0x7f80>;
};
&usdhc3 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
+ iommus = <&smmu 0x11 0x7f80>;
};
power-domains = <&pd IMX_SC_R_UART_4>;
};
+ i2c4: i2c@5a840000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x5a840000 0x4000>;
+ interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&i2c4_lpcg 0>,
+ <&i2c4_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_4>;
+ status = "disabled";
+ };
+
+ i2c4_lpcg: clock-controller@5ac40000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac40000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c4_lpcg_clk",
+ "i2c4_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_4>;
+ };
+
can1_lpcg: clock-controller@5ace0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ace0000 0x10000>;
status = "okay";
};
+/* It is eDMA1 in 8QM RM, but 8QXP it is eDMA3 */
&edma3 {
+ reg = <0x5a9f0000 0x210000>;
+ dma-channels = <10>;
+ interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
- <&pd IMX_SC_R_DMA_1_CH1>,
- <&pd IMX_SC_R_DMA_1_CH2>,
- <&pd IMX_SC_R_DMA_1_CH3>,
- <&pd IMX_SC_R_DMA_1_CH4>,
- <&pd IMX_SC_R_DMA_1_CH5>,
- <&pd IMX_SC_R_DMA_1_CH6>,
- <&pd IMX_SC_R_DMA_1_CH7>;
+ <&pd IMX_SC_R_DMA_1_CH1>,
+ <&pd IMX_SC_R_DMA_1_CH2>,
+ <&pd IMX_SC_R_DMA_1_CH3>,
+ <&pd IMX_SC_R_DMA_1_CH4>,
+ <&pd IMX_SC_R_DMA_1_CH5>,
+ <&pd IMX_SC_R_DMA_1_CH6>,
+ <&pd IMX_SC_R_DMA_1_CH7>,
+ <&pd IMX_SC_R_DMA_1_CH8>,
+ <&pd IMX_SC_R_DMA_1_CH9>;
};
&flexcan1 {
};
&flexcan2 {
- clocks = <&can1_lpcg 1>,
- <&can1_lpcg 0>;
+ clocks = <&can1_lpcg IMX_LPCG_CLK_4>,
+ <&can1_lpcg IMX_LPCG_CLK_0>;
assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>;
fsl,clk-source = /bits/ 8 <1>;
};
&flexcan3 {
- clocks = <&can2_lpcg 1>,
- <&can2_lpcg 0>;
+ clocks = <&can2_lpcg IMX_LPCG_CLK_4>,
+ <&can2_lpcg IMX_LPCG_CLK_0>;
assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>;
fsl,clk-source = /bits/ 8 <1>;
};
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
};
+ smmu: iommu@51400000 {
+ compatible = "arm,mmu-500";
+ interrupt-parent = <&gic>;
+ reg = <0 0x51400000 0 0x40000>;
+ #global-interrupts = <1>;
+ #iommu-cells = <2>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
system-controller {
compatible = "fsl,imx-scu";
mbox-names = "tx0",
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
+/*
+ * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+/dts-v1/;
+
+#include "imx8qxp-tqma8xqp.dtsi"
+#include "mba8xx.dtsi"
+
+/ {
+ model = "TQ-Systems i.MX8QXP TQMa8XQP on MBa8Xx";
+ compatible = "tq,imx8qxp-tqma8xqp-mba8xx", "tq,imx8qxp-tqma8xqp", "fsl,imx8qxp";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
+/*
+ * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+#include "imx8qxp.dtsi"
+#include "tqma8xx.dtsi"
+
+/ {
+ model = "TQ-Systems i.MX8QXP TQMa8XQP";
+ compatible = "tq,imx8qxp-tqma8xqp", "fsl,imx8qxp";
+};
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
};
+ clk_dummy: clock-dummy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "clk_dummy";
+ };
+
xtal32k: clock-xtal32k {
compatible = "fixed-clock";
#clock-cells = <0>;
/* sorted in register address */
#include "imx8-ss-img.dtsi"
#include "imx8-ss-vpu.dtsi"
+ #include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"
no-map;
};
- rsc_table: rsc-table@1fff8000{
+ rsc_table: rsc-table@1fff8000 {
reg = <0 0x1fff8000 0 0x1000>;
no-map;
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
+ * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
+ *
+ * Product homepage:
+ * phyBOARD-Segin carrier board is reused for the i.MX93 design.
+ * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
+ */
+/dts-v1/;
+
+#include "imx93-phycore-som.dtsi"
+
+/{
+ model = "PHYTEC phyBOARD-Segin-i.MX93";
+ compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som",
+ "fsl,imx93";
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "VCC_SD";
+ };
+};
+
+/* Console */
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc1 {
+ no-1-8-v;
+};
+
+/* SD-Card */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
+ bus-width = <4>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ no-mmc;
+ no-sdio;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x30e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_cd: usdhc2cdgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_default: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
+ * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
+ *
+ * Product homepage:
+ * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
+ */
+
+#include <dt-bindings/leds/common.h>
+
+#include "imx93.dtsi"
+
+/{
+ model = "PHYTEC phyCORE-i.MX93";
+ compatible = "phytec,imx93-phycore-som", "fsl,imx93";
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ alloc-ranges = <0 0x80000000 0 0x40000000>;
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds>;
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+/* Ethernet */
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ fsl,magic-packet;
+ assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
+ <&clk IMX93_CLK_ENET_REF>,
+ <&clk IMX93_CLK_ENET_REF_PHY>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+ <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+ <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <100000000>, <50000000>, <50000000>;
+ status = "okay";
+
+ mdio: mdio {
+ clock-frequency = <5000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+/* eMMC */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+/* Watchdog */
+&wdog3 {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e
+ MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e
+ MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e
+ >;
+ };
+
+ pinctrl_leds: ledsgrp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
+ >;
+ };
+};
/* protectable identification memory (part of M24C64-D @57) */
eeprom@5f {
- compatible = "st,24c64", "atmel,24c64";
+ compatible = "atmel,24c64d-wl";
reg = <0x5f>;
- size = <32>;
- pagesize = <32>;
vcc-supply = <®_v3v3>;
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ * Copyright 2023 Variscite Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "imx93-var-som.dtsi"
+
+/{
+ model = "Variscite VAR-SOM-MX93 on Symphony evaluation board";
+ compatible = "variscite,var-som-mx93-symphony",
+ "variscite,var-som-mx93", "fsl,imx93";
+
+ aliases {
+ ethernet0 = &eqos;
+ ethernet1 = &fec;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ /*
+ * Needed only for Symphony <= v1.5
+ */
+ reg_fec_phy: regulator-fec-phy {
+ compatible = "regulator-fixed";
+ regulator-name = "fec-phy";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <20000>;
+ gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <20000>;
+ enable-active-high;
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ethosu_mem: ethosu-region@88000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x0 0x88000000 0x0 0x8000000>;
+ };
+
+ vdev0vring0: vdev0vring0@87ee0000 {
+ reg = <0 0x87ee0000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@87ee8000 {
+ reg = <0 0x87ee8000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@87ef0000 {
+ reg = <0 0x87ef0000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@87ef8000 {
+ reg = <0 0x87ef8000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table: rsc-table@2021f000 {
+ reg = <0 0x2021f000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@87f00000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x87f00000 0 0x100000>;
+ no-map;
+ };
+
+ ele_reserved: ele-reserved@87de0000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x87de0000 0 0x100000>;
+ no-map;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-back {
+ label = "Back";
+ gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_BACK>;
+ };
+
+ key-home {
+ label = "Home";
+ gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOME>;
+ };
+
+ key-menu {
+ label = "Menu";
+ gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_MENU>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+/* Use external instead of internal RTC*/
+&bbnsm_rtc {
+ status = "disabled";
+};
+
+&eqos {
+ mdio {
+ ethphy1: ethernet-phy@5 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <5>;
+ qca,disable-smarteee;
+ eee-broken-1000t;
+ reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <20000>;
+ vddio-supply = <&vddio1>;
+
+ vddio1: vddio-regulator {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy1>;
+ phy-supply = <®_fec_phy>;
+ status = "okay";
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&lpi2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
+ pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
+ scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ /* DS1337 RTC module */
+ rtc@68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ };
+};
+
+&lpi2c5 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c5>;
+ pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
+ pinctrl-2 = <&pinctrl_lpi2c5_gpio>;
+ scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ pca9534: gpio@20 {
+ compatible = "nxp,pca9534";
+ reg = <0x20>;
+ gpio-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca9534>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+ #gpio-cells = <2>;
+ wakeup-source;
+ };
+};
+
+/* Console */
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* J18.7, J18.9 */
+&lpuart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart6>;
+ status = "okay";
+};
+
+/* SD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+ no-sdio;
+ no-mmc;
+};
+
+/* Watchdog */
+&wdog3 {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX93_PAD_PDM_CLK__CAN1_TX 0x139e
+ MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c1_gpio: lpi2c1gpiogrp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e
+ MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
+ >;
+ };
+
+ pinctrl_lpi2c5: lpi2c5grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
+ MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e
+ MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e
+ >;
+ };
+
+ pinctrl_pca9534: pca9534grp {
+ fsl,pins = <
+ MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart6: uart6grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e
+ MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ * Copyright 2023 Variscite Ltd.
+ */
+
+/dts-v1/;
+
+#include "imx93.dtsi"
+
+/{
+ model = "Variscite VAR-SOM-MX93 module";
+ compatible = "variscite,var-som-mx93", "fsl,imx93";
+
+ mmc_pwrseq: mmc-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <10000>;
+ reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
+ <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
+ };
+
+ reg_eqos_phy: regulator-eqos-phy {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_eqos_phy>;
+ regulator-name = "eth_phy_pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100000>;
+ regulator-always-on;
+ };
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <1000000>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ eee-broken-1000t;
+ };
+ };
+};
+
+/* eMMC */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_reg_eqos_phy: regeqosgrp {
+ fsl,pins = <
+ MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+};
status = "disabled";
};
- i3c1: i3c-master@44330000 {
+ i3c1: i3c@44330000 {
compatible = "silvaco,i3c-master-v1";
reg = <0x44330000 0x10000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- i3c2: i3c-master@42520000 {
+ i3c2: i3c@42520000 {
compatible = "silvaco,i3c-master-v1";
reg = <0x42520000 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
stdout-path = &uart3;
};
+ clk_xtal25: clk-xtal25 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
};
};
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
reg_12v: regulator-12v {
compatible = "regulator-fixed";
regulator-name = "MBA8MX_12V";
line-name = "BOOT_CFG_OE#";
};
- rst-usb-hub-hog {
+ rst_usb_hub_hog: rst-usb-hub-hog {
gpio-hog;
gpios = <13 0>;
output-high;
pagesize = <16>;
vcc-supply = <®_vcc_3v3>;
};
+
+ pcieclk: clk@68 {
+ compatible = "renesas,9fgv0441";
+ reg = <0x68>;
+ clocks = <&clk_xtal25>;
+ #clock-cells = <1>;
+ };
};
&i2c3 {
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
+/*
+ * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ adc {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>;
+ };
+
+ aliases {
+ rtc0 = &pcf85063;
+ rtc1 = &rtc;
+ };
+
+ backlight_lvds: backlight-lvds {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bl_lvds>;
+ pwms = <&adma_pwm 0 5000000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <®_12v0>;
+ enable-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiobuttons>;
+ autorepeat;
+
+ switch-a {
+ label = "switcha";
+ linux,code = <BTN_0>;
+ gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>;
+ };
+
+ switch-b {
+ label = "switchb";
+ linux,code = <BTN_1>;
+ gpios = <&lsio_gpio1 14 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&expander 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ led2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&expander 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ /* TODO LVDS panels */
+
+ reg_12v0: regulator-12v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&expander 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_pcie_1v5: regulator-pcie-1v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "MBA8XX_PCIE_1V5";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_pcie_1v5>;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&lsio_gpio0 30 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <1000>;
+ enable-active-high;
+ };
+
+ reg_pcie_3v3: regulator-pcie-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "MBA8XX_PCIE_3V3";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_pcie_3v3>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <1000>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_3v3_mb: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_MB";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-tlv320aic32x4";
+ model = "tqm-tlv320aic32";
+ audio-codec = <&tlv320aic3x04>;
+ ssi-controller = <&sai1>;
+ };
+};
+
+&adc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0>;
+ vref-supply = <®_1v8>;
+ #io-channel-cells = <1>;
+ status = "okay";
+};
+
+&adma_pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_admapwm>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ethphy0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ reset-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500000>;
+ reset-deassert-us = <50000>;
+ enet-phy-lane-no-swap;
+ interrupt-parent = <&lsio_gpio3>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ ethphy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ethphy3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500000>;
+ reset-deassert-us = <50000>;
+ enet-phy-lane-no-swap;
+ interrupt-parent = <&lsio_gpio3>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec2>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy3>;
+ status = "okay";
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0>;
+ xceiver-supply = <®_3v3>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1>;
+ xceiver-supply = <®_3v3>;
+ status = "okay";
+};
+
+&i2c1 {
+ tlv320aic3x04: audio-codec@18 {
+ compatible = "ti,tlv320aic32x4";
+ reg = <0x18>;
+ clocks = <&mclkout0_lpcg 0>;
+ clock-names = "mclk";
+ iov-supply = <®_1v8>;
+ ldoin-supply = <®_3v3>;
+ };
+
+ se97b_1c: temperature-sensor@1c {
+ compatible = "nxp,se97b", "jedec,jc-42.4-temp";
+ reg = <0x1c>;
+ };
+
+ at24c02_54: eeprom@54 {
+ compatible = "nxp,se97b", "atmel,24c02";
+ reg = <0x54>;
+ pagesize = <16>;
+ vcc-supply = <®_3v3>;
+ };
+
+ expander: gpio@70 {
+ compatible = "nxp,pca9538";
+ reg = <0x70>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca9538>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&lsio_gpio4>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ vcc-supply = <®_1v8>;
+
+ gpio-line-names = "", "LED_A",
+ "LED_B", "",
+ "DSI_EN", "USB_RESET#",
+ "V_12V_EN", "PCIE_DIS#";
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-1 = <&pinctrl_lpi2c2gpio>;
+ scl-gpios = <&lsio_gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&lsio_gpio2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+/* TODO LDB */
+
+&lpspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&lpspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&lpspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi3>;
+ num-cs = <2>;
+ cs-gpios = <&lsio_gpio0 16 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&lpuart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart3>;
+ status = "okay";
+};
+
+&lsio_gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lsgpio3>;
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "X4_15",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+/* TODO: Mini-PCIe */
+
+&sai1 {
+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&sai1_lpcg 0>;
+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ power-active-high;
+ over-current-active-low;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbotg3 {
+ status = "okay";
+};
+
+&usbotg3_cdns3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_3v3_mb>;
+ no-1-8-v;
+ no-sdio;
+ no-mmc;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_adc0: adc0grp {
+ fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x02000060>,
+ <IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x02000060>,
+ <IMX8QXP_ADC_IN2_ADMA_ADC_IN2 0x02000060>,
+ <IMX8QXP_ADC_IN3_ADMA_ADC_IN3 0x02000060>;
+ };
+
+ pinctrl_admapwm: admapwmgrp {
+ fsl,pins = <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000021>;
+ };
+
+ pinctrl_bl_lvds: bllvdsgrp {
+ fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 0x00000021>;
+ };
+
+ pinctrl_can0: can0grp {
+ fsl,pins = <IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX 0x00000021>,
+ <IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX 0x00000021>;
+ };
+
+ pinctrl_can1: can1grp {
+ fsl,pins = <IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021>,
+ <IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021>;
+ };
+
+ pinctrl_ethphy0: ethphy0grp {
+ fsl,pins = <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x00000040>,
+ <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x00000040>;
+ };
+
+ pinctrl_ethphy3: ethphy3grp {
+ fsl,pins = <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x00000040>,
+ <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x00000040>;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000041>,
+ <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000041>,
+ <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000040>,
+ <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000040>,
+ <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000040>,
+ <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000040>,
+ <IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000040>,
+ <IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000040>,
+ <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000040>,
+ <IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000040>,
+ <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000040>,
+ <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000040>,
+ <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000040>,
+ <IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000040>;
+ };
+
+ pinctrl_fec2: fec2grp {
+ fsl,pins = <IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000040>,
+ <IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000040>,
+ <IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000040>,
+ <IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000040>,
+ <IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000040>,
+ <IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000040>,
+ <IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000040>,
+ <IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000040>,
+ <IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000040>,
+ <IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000040>,
+ <IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000040>,
+ <IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000040>;
+ };
+
+ pinctrl_gpiobuttons: gpiobuttonsgrp {
+ fsl,pins = <IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 0x00000020>,
+ <IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 0x00000020>;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL 0x06000021>,
+ <IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA 0x06000021>;
+ };
+
+ pinctrl_lpi2c2gpio: lpi2c2gpiogrp {
+ fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021>,
+ <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x06000021>;
+ };
+
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020>,
+ <IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020>;
+ };
+
+ pinctrl_lpuart3: lpuart3grp {
+ fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020>,
+ <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>;
+ };
+
+ pinctrl_lsgpio3: lsgpio3grp {
+ fsl,pins = <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000021>;
+ };
+
+ pinctrl_pca9538: pca9538grp {
+ fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000020>;
+ };
+
+ pinctrl_pcieb: pcieagrp {
+ fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>,
+ <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>,
+ <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>;
+ };
+
+ pinctrl_reg_pcie_1v5: regpcie1v5grp {
+ fsl,pins = <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x00000021>;
+ };
+
+ pinctrl_reg_pcie_3v3: regpcie3v3grp {
+ fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000021>;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x06000041>,
+ <IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000041>,
+ <IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000041>,
+ <IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000041>,
+ <IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000041>;
+ };
+
+ pinctrl_spi1: spi1grp {
+ fsl,pins = <IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI 0x00000041>,
+ <IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO 0x00000041>,
+ <IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK 0x00000041>,
+ <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x00000021>,
+ <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x00000021>;
+ };
+
+ pinctrl_spi2: spi2grp {
+ fsl,pins = <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x00000041>,
+ <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x00000041>,
+ <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x00000041>,
+ <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x00000021>;
+ };
+
+ pinctrl_spi3: spi3grp {
+ fsl,pins = <IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK 0x00000041>,
+ <IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI 0x00000041>,
+ <IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO 0x00000041>,
+ <IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 0x00000021>,
+ <IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 0x00000021>;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>,
+ <IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC 0x00000021>;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021>,
+ <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021>;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>,
+ <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>,
+ <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>,
+ <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>,
+ <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>,
+ <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>,
+ <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
+ <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
+ <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
+ <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
+ <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
+ <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
+ <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
+ <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
+ <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
+ <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
+ <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
+ <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
+ <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
+/*
+ * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * global autoconfigured region for contiguous allocations
+ * must not exceed memory size and region
+ */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x20000000>;
+ alloc-ranges = <0 0x96000000 0 0x30000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+/* TQMa8Xx only uses industrial grade, reduce trip points accordingly */
+&cpu_alert0 {
+ temperature = <95000>;
+};
+
+&cpu_crit0 {
+ temperature = <100000>;
+};
+/* end of temperature grade adjustments */
+
+&flexspi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ flash0: flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <66000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+/* TODO GPU */
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-1 = <&pinctrl_lpi2c1gpio>;
+ scl-gpios = <&lsio_gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&lsio_gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ se97: temperature-sensor@1b {
+ compatible = "nxp,se97b", "jedec,jc-42.4-temp";
+ reg = <0x1b>;
+ };
+
+ pcf85063: rtc@51 {
+ compatible = "nxp,pcf85063a";
+ reg = <0x51>;
+ quartz-load-femtofarads = <7000>;
+ };
+
+ at24c02: eeprom@53 {
+ compatible = "nxp,se97b", "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <®_3v3>;
+ };
+
+ m24c64: eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <32>;
+ vcc-supply = <®_3v3>;
+ };
+};
+
+&mu_m0 {
+ status = "okay";
+};
+
+&mu1_m0 {
+ status = "okay";
+};
+
+&thermal_zones {
+ pmic_thermal: pmic-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
+
+ trips {
+ pmic_alert0: trip0 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ pmic_crit0: trip1 {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&pmic_alert0>;
+ cooling-device =
+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ vqmmc-supply = <®_1v8>;
+ vmmc-supply = <®_3v3>;
+ bus-width = <8>;
+ non-removable;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&vpu {
+ compatible = "nxp,imx8qxp-vpu";
+ status = "okay";
+};
+
+&vpu_core0 {
+ memory-region = <&decoder_boot>, <&decoder_rpc>;
+ status = "okay";
+};
+
+&vpu_core1 {
+ memory-region = <&encoder_boot>, <&encoder_rpc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004d
+ IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004d
+ IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004d
+ IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004d
+ IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004d
+ IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004d
+ IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004d
+ IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004d
+ IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004d
+ IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004d
+ IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004d
+ IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004d
+ IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004d
+ IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004d
+ IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004d
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021
+ IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021
+ >;
+ };
+
+ pinctrl_lpi2c1gpio: lpi2c1gpiogrp {
+ fsl,pins = <
+ IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 0x06000021
+ IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
+ >;
+ };
+};
status = "disabled";
};
- i3c0: i3c-master@10da0000 {
+ i3c0: i3c@10da0000 {
compatible = "snps,dw-i3c-master-1.00a";
reg = <0x10da0000 0x1000>;
#address-cells = <3>;
status = "disabled";
};
- i3c1: i3c-master@10da1000 {
+ i3c1: i3c@10da1000 {
compatible = "snps,dw-i3c-master-1.00a";
reg = <0x10da1000 0x1000>;
#address-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
- dma-ranges;
internal-regs@7f000000 {
#address-cells = <1>;
};
};
+ mmc_dma: bus@80500000 {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ reg = <0x0 0x80500000 0x0 0x100000>;
+ dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>;
+ dma-coherent;
+
+ sdhci: mmc@805c0000 {
+ compatible = "marvell,ac5-sdhci",
+ "marvell,armada-ap806-sdhci";
+ reg = <0x0 0x805c0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&emmc_clock>, <&cnm_clock>;
+ clock-names = "core", "axi";
+ bus-width = <8>;
+ non-removable;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ };
+ };
+
/*
* Dedicated section for devices behind 32bit controllers so we
* can configure specific DMA mapping for them
#clock-cells = <0>;
clock-frequency = <400000000>;
};
+
+ emmc_clock: emmc-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ };
};
};
};
};
};
+
+&sdhci {
+ status = "okay";
+};
crypto: crypto@90000 {
compatible = "inside-secure,safexcel-eip97ies";
reg = <0x90000 0x20000>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mem", "ring0", "ring1",
- "ring2", "ring3", "eip";
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ring0", "ring1", "ring2",
+ "ring3", "eip", "mem";
clocks = <&nb_periph_clk 15>;
};
"marvell,armada-ap806-sdhci"; /* Backward compatibility */
};
+&ap_thermal {
+ compatible = "marvell,armada-ap807-thermal";
+};
CP11X_LABEL(crypto): crypto@800000 {
compatible = "inside-secure,safexcel-eip197b";
reg = <0x800000 0x200000>;
- interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
- <88 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <88 IRQ_TYPE_LEVEL_HIGH>,
<89 IRQ_TYPE_LEVEL_HIGH>,
<90 IRQ_TYPE_LEVEL_HIGH>,
<91 IRQ_TYPE_LEVEL_HIGH>,
- <92 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mem", "ring0", "ring1",
- "ring2", "ring3", "eip";
+ <92 IRQ_TYPE_LEVEL_HIGH>,
+ <87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ring0", "ring1", "ring2", "ring3",
+ "eip", "mem";
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 26>,
<&CP11X_LABEL(clk) 1 17>;
extcon_usb: extcon_iddig {
compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pio 12 GPIO_ACTIVE_HIGH>;
+ id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
};
extcon_usb1: extcon_iddig1 {
compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>;
+ id-gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
};
usb_p0_vbus: regulator-usb-p0-vbus {
};
&pio {
- eth_default: eth_default {
+ eth_default: eth-default-pins {
tx_pins {
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
<MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
};
};
- eth_sleep: eth_sleep {
+ eth_sleep: eth-sleep-pins {
tx_pins {
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
<MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
};
};
- usb0_id_pins_float: usb0_iddig {
+ usb0_id_pins_float: usb0-iddig-pins {
pins_iddig {
pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
bias-pull-up;
};
};
- usb1_id_pins_float: usb1_iddig {
+ usb1_id_pins_float: usb1-iddig-pins {
pins_iddig {
pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
bias-pull-up;
#clock-cells = <1>;
};
- infracfg: syscon@10001000 {
+ infracfg: clock-controller@10001000 {
compatible = "mediatek,mt2712-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
pericfg: syscon@10003000 {
#clock-cells = <1>;
};
- syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ syscfg_pctl_a: syscon@10005000 {
compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
#clock-cells = <1>;
};
- infrasys: infracfg_ao@10001000 {
+ infrasys: syscon@10001000 {
compatible = "mediatek,mt6797-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#clock-cells = <1>;
};
- imgsys: imgsys_config@15000000 {
+ imgsys: syscon@15000000 {
compatible = "mediatek,mt6797-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
- vdecsys: vdec_gcon@16000000 {
+ vdecsys: syscon@16000000 {
compatible = "mediatek,mt6797-vdecsys", "syscon";
reg = <0 0x16000000 0 0x10000>;
#clock-cells = <1>;
};
- vencsys: venc_gcon@17000000 {
+ vencsys: syscon@17000000 {
compatible = "mediatek,mt6797-vencsys", "syscon";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
+ device_type = "memory";
};
reg_1p8v: regulator-1p8v {
label = "lan3";
};
+ port@5 {
+ reg = <5>;
+ ethernet = <&gmac1>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
port@6 {
reg = <6>;
label = "cpu";
memory@40000000 {
reg = <0 0x40000000 0 0x20000000>;
+ device_type = "memory";
};
reg_1p8v: regulator-1p8v {
};
};
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
label = "wan";
};
+ port@5 {
+ reg = <5>;
+ ethernet = <&gmac1>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
port@6 {
reg = <6>;
label = "cpu";
clock-names = "hif_sel";
};
- cir: cir@10009000 {
+ cir: ir-receiver@10009000 {
compatible = "mediatek,mt7622-cir";
reg = <0 0x10009000 0 0x1000>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
};
};
- apmixedsys: apmixedsys@10209000 {
- compatible = "mediatek,mt7622-apmixedsys",
- "syscon";
+ apmixedsys: clock-controller@10209000 {
+ compatible = "mediatek,mt7622-apmixedsys";
reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>;
};
- topckgen: topckgen@10210000 {
- compatible = "mediatek,mt7622-topckgen",
- "syscon";
+ topckgen: clock-controller@10210000 {
+ compatible = "mediatek,mt7622-topckgen";
reg = <0 0x10210000 0 0x1000>;
#clock-cells = <1>;
};
<&pericfg CLK_PERI_AUXADC_PD>;
clock-names = "therm", "auxadc";
resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
- reset-names = "therm";
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
nvmem-cells = <&thermal_calibration>;
power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
};
- ssusbsys: ssusbsys@1a000000 {
- compatible = "mediatek,mt7622-ssusbsys",
- "syscon";
+ ssusbsys: clock-controller@1a000000 {
+ compatible = "mediatek,mt7622-ssusbsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};
- pciesys: pciesys@1a100800 {
- compatible = "mediatek,mt7622-pciesys",
- "syscon";
+ pciesys: clock-controller@1a100800 {
+ compatible = "mediatek,mt7622-pciesys";
reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};
- hifsys: syscon@1af00000 {
- compatible = "mediatek,mt7622-hifsys", "syscon";
+ hifsys: clock-controller@1af00000 {
+ compatible = "mediatek,mt7622-hifsys";
reg = <0 0x1af00000 0 0x70>;
+ #clock-cells = <1>;
};
- ethsys: syscon@1b000000 {
+ ethsys: clock-controller@1b000000 {
compatible = "mediatek,mt7622-ethsys",
"syscon";
reg = <0 0x1b000000 0 0x1000>;
};
eth: ethernet@1b100000 {
- compatible = "mediatek,mt7622-eth",
- "mediatek,mt2701-eth",
- "syscon";
+ compatible = "mediatek,mt7622-eth";
reg = <0 0x1b100000 0 0x20000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+
+/dts-v1/;
+
+#include "mt7981b.dtsi"
+
+/ {
+ compatible = "xiaomi,ax3000t", "mediatek,mt7981b";
+ model = "Xiaomi AX3000T";
+
+ memory@40000000 {
+ reg = <0 0x40000000 0 0x10000000>;
+ device_type = "memory";
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+
+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt7981b";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+ };
+
+ oscillator-40m {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ clock-output-names = "clkxtal";
+ #clock-cells = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c080000 0 0x200000>; /* GICR */
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ infracfg: clock-controller@10001000 {
+ compatible = "mediatek,mt7981-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@1001b000 {
+ compatible = "mediatek,mt7981-topckgen", "syscon";
+ reg = <0 0x1001b000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@1001e000 {
+ compatible = "mediatek,mt7981-apmixedsys";
+ reg = <0 0x1001e000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pwm@10048000 {
+ compatible = "mediatek,mt7981-pwm";
+ reg = <0 0x10048000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_PWM_STA>,
+ <&infracfg CLK_INFRA_PWM_HCK>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>,
+ <&infracfg CLK_INFRA_PWM3_CK>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
+ #pwm-cells = <2>;
+ };
+
+ clock-controller@15000000 {
+ compatible = "mediatek,mt7981-ethsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+#include "mt7986a.dtsi"
+
+/ {
+ compatible = "acelink,ew-7886cax", "mediatek,mt7986a";
+ model = "Acelink EW-7886CAX";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ reg = <0 0x40000000 0 0x20000000>;
+ device_type = "memory";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ key-restart {
+ label = "Reset";
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-2 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+ð {
+ status = "okay";
+
+ mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "2500base-x";
+ phy-handle = <&phy6>;
+ nvmem-cells = <&macaddr>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ mdio-bus {
+ reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <50000>;
+ reset-post-delay-us = <20000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy6: phy@6 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <6>;
+ };
+ };
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x0 0x100000>;
+ label = "bootloader";
+ read-only;
+ };
+
+ partition@100000 {
+ reg = <0x100000 0x80000>;
+ label = "u-boot-env";
+ };
+
+ partition@180000 {
+ compatible = "nvmem-cells";
+ reg = <0x180000 0x200000>;
+ label = "factory";
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom: eeprom@0 {
+ reg = <0x0 0x1000>;
+ };
+
+ macaddr: macaddr@4 {
+ reg = <0x4 0x6>;
+ };
+ };
+ };
+
+ partition@380000 {
+ reg = <0x380000 0x200000>;
+ label = "fip";
+ };
+
+ partition@580000 {
+ reg = <0x580000 0x4000000>;
+ label = "ubi";
+ };
+ };
+ };
+};
+
+&trng {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&wifi {
+ nvmem-cells = <&eeprom>;
+ nvmem-cell-names = "eeprom";
+ status = "okay";
+};
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
- spi_nand: spi_nand@0 {
+ spi_nand: flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <10000000>;
#cooling-cells = <2>;
/* cooling level (0, 1, 2) - pwm inverted */
cooling-levels = <255 96 0>;
- pwms = <&pwm 0 10000 0>;
+ pwms = <&pwm 0 10000>;
status = "okay";
};
&cpu_thermal {
cooling-maps {
- cpu-active-high {
+ map-cpu-active-high {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_high>;
};
- cpu-active-med {
+ map-cpu-active-med {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_med>;
};
- cpu-active-low {
+ map-cpu-active-low {
/* active: set fan to cooling level 0 */
cooling-device = <&fan 0 0>;
trip = <&cpu_trip_active_low>;
};
};
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&spi_flash_pins>;
cs-gpios = <0>, <0>;
status = "okay";
- spi_nand: spi_nand@0 {
+
+ spi_nand: flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <10000000>;
- spi-tx-buswidth = <4>;
- spi-rx-buswidth = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
};
};
label = "lan4";
};
+ port@5 {
+ reg = <5>;
+ ethernet = <&gmac1>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
port@6 {
reg = <6>;
label = "cpu";
#address-cells = <2>;
#size-cells = <2>;
- clk40m: oscillator-40m {
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- #clock-cells = <0>;
- clock-output-names = "clkxtal";
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
- device_type = "cpu";
compatible = "arm,cortex-a53";
- enable-method = "psci";
reg = <0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
#cooling-cells = <2>;
};
cpu1: cpu@1 {
- device_type = "cpu";
compatible = "arm,cortex-a53";
- enable-method = "psci";
reg = <0x1>;
+ device_type = "cpu";
+ enable-method = "psci";
#cooling-cells = <2>;
};
cpu2: cpu@2 {
- device_type = "cpu";
compatible = "arm,cortex-a53";
- enable-method = "psci";
reg = <0x2>;
+ device_type = "cpu";
+ enable-method = "psci";
#cooling-cells = <2>;
};
cpu3: cpu@3 {
- device_type = "cpu";
- enable-method = "psci";
compatible = "arm,cortex-a53";
reg = <0x3>;
+ device_type = "cpu";
+ enable-method = "psci";
#cooling-cells = <2>;
};
};
+ clk40m: oscillator-40m {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ #clock-cells = <0>;
+ clock-output-names = "clkxtal";
+ };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- };
-
soc {
- #address-cells = <2>;
- #size-cells = <2>;
compatible = "simple-bus";
ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- interrupt-controller;
reg = <0 0x0c000000 0 0x10000>, /* GICD */
<0 0x0c080000 0 0x80000>, /* GICR */
<0 0x0c400000 0 0x2000>, /* GICC */
<0 0x0c410000 0 0x1000>, /* GICH */
<0 0x0c420000 0 0x2000>; /* GICV */
+ interrupt-parent = <&gic>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
infracfg: infracfg@10001000 {
compatible = "mediatek,mt7986-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
wed_pcie: wed-pcie@10003000 {
#interrupt-cells = <2>;
};
+ pwm: pwm@10048000 {
+ compatible = "mediatek,mt7986-pwm";
+ reg = <0 0x10048000 0 0x1000>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_STA>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>;
+ clock-names = "top", "main", "pwm1", "pwm2";
+ status = "disabled";
+ };
+
sgmiisys0: syscon@10060000 {
compatible = "mediatek,mt7986-sgmiisys_0",
"syscon";
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ring0", "ring1", "ring2", "ring3";
clocks = <&infracfg CLK_INFRA_EIP97_CK>;
- clock-names = "infra_eip97_ck";
assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
status = "disabled";
};
- pwm: pwm@10048000 {
- compatible = "mediatek,mt7986-pwm";
- reg = <0 0x10048000 0 0x1000>;
- #clock-cells = <1>;
- #pwm-cells = <2>;
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_PWM_SEL>,
- <&infracfg CLK_INFRA_PWM_STA>,
- <&infracfg CLK_INFRA_PWM1_CK>,
- <&infracfg CLK_INFRA_PWM2_CK>;
- clock-names = "top", "main", "pwm1", "pwm2";
- status = "disabled";
- };
-
uart0: serial@11002000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
spi0: spi@1100a000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+ reg = <0 0x1100a000 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_MPLL_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
spi1: spi@1100b000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+ reg = <0 0x1100b000 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- reg = <0 0x1100b000 0 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_MPLL_D2>,
<&topckgen CLK_TOP_SPIM_MST_SEL>,
status = "disabled";
};
+ thermal: thermal@1100c800 {
+ compatible = "mediatek,mt7986-thermal";
+ reg = <0 0x1100c800 0 0x800>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_THERM_CK>,
+ <&infracfg CLK_INFRA_ADC_26M_CK>;
+ clock-names = "therm", "auxadc";
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ #thermal-sensor-cells = <1>;
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ };
+
auxadc: adc@1100d000 {
compatible = "mediatek,mt7986-auxadc";
reg = <0 0x1100d000 0 0x1000>;
status = "disabled";
};
- thermal: thermal@1100c800 {
- #thermal-sensor-cells = <1>;
- compatible = "mediatek,mt7986-thermal";
- reg = <0 0x1100c800 0 0x800>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_THERM_CK>,
- <&infracfg CLK_INFRA_ADC_26M_CK>,
- <&infracfg CLK_INFRA_ADC_FRC_CK>;
- clock-names = "therm", "auxadc", "adc_32k";
- mediatek,auxadc = <&auxadc>;
- mediatek,apmixedsys = <&apmixedsys>;
- nvmem-cells = <&thermal_calibration>;
- nvmem-cell-names = "calibration-data";
- };
-
pcie: pcie@11280000 {
compatible = "mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
+ reg = <0x00 0x11280000 0x00 0x4000>;
+ reg-names = "pcie-mac";
+ ranges = <0x82000000 0x00 0x20000000 0x00
+ 0x20000000 0x00 0x10000000>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
- reg = <0x00 0x11280000 0x00 0x4000>;
- reg-names = "pcie-mac";
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
- ranges = <0x82000000 0x00 0x20000000 0x00
- 0x20000000 0x00 0x10000000>;
clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
<&infracfg CLK_INFRA_IPCIE_CK>,
<&infracfg CLK_INFRA_IPCIER_CK>,
<&infracfg CLK_INFRA_IPCIEB_CK>;
clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
- status = "disabled";
phys = <&pcie_port PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
+ status = "disabled";
+
pcie_intc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
pcie_phy: t-phy {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";
+ ranges;
#address-cells = <2>;
#size-cells = <2>;
- ranges;
status = "disabled";
pcie_port: pcie-phy@11c00000 {
usb_phy: t-phy@11e10000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";
+ ranges = <0 0 0x11e10000 0x1700>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0 0x11e10000 0x1700>;
status = "disabled";
u2port0: usb-phy@0 {
};
ethsys: syscon@15000000 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "mediatek,mt7986-ethsys",
"syscon";
reg = <0 0x15000000 0 0x1000>;
mediatek,wo-ccif = <&wo_ccif1>;
};
- wo_ccif0: syscon@151a5000 {
- compatible = "mediatek,mt7986-wo-ccif", "syscon";
- reg = <0 0x151a5000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wo_ccif1: syscon@151ad000 {
- compatible = "mediatek,mt7986-wo-ccif", "syscon";
- reg = <0 0x151ad000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- };
-
eth: ethernet@15100000 {
compatible = "mediatek,mt7986-eth";
reg = <0 0x15100000 0 0x80000>;
<&topckgen CLK_TOP_SGM_325M_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
<&apmixedsys CLK_APMIXED_SGMPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
mediatek,ethsys = <ðsys>;
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
mediatek,wed-pcie = <&wed_pcie>;
mediatek,wed = <&wed0>, <&wed1>;
- #reset-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
};
+ wo_ccif0: syscon@151a5000 {
+ compatible = "mediatek,mt7986-wo-ccif", "syscon";
+ reg = <0 0x151a5000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wo_ccif1: syscon@151ad000 {
+ compatible = "mediatek,mt7986-wo-ccif", "syscon";
+ reg = <0 0x151ad000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
wifi: wifi@18000000 {
compatible = "mediatek,mt7986-wmac";
+ reg = <0 0x18000000 0 0x1000000>,
+ <0 0x10003000 0 0x1000>,
+ <0 0x11d10000 0 0x1000>;
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
reset-names = "consys";
clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
clock-names = "mcu", "ap2conn";
- reg = <0 0x18000000 0 0x1000000>,
- <0 0x10003000 0 0x1000>,
- <0 0x11d10000 0 0x1000>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
};
};
};
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
};
};
};
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
label = "lan4";
};
+ port@5 {
+ reg = <5>;
+ ethernet = <&gmac1>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
port@6 {
reg = <6>;
label = "cpu";
pinctrl-0 = <&spi_flash_pins>;
cs-gpios = <0>, <0>;
status = "okay";
- spi_nand: spi_nand@0 {
+
+ spi_nand: flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <10000000>;
- spi-tx-buswidth = <4>;
- spi-rx-buswidth = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+
+/dts-v1/;
+
+#include "mt7988a.dtsi"
+
+/ {
+ compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+ model = "Banana Pi BPI-R4";
+ chassis-type = "embedded";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt7988a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a73";
+ reg = <0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a73";
+ reg = <0x1>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a73";
+ reg = <0x2>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a73";
+ reg = <0x3>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+ };
+
+ oscillator-40m {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ #clock-cells = <0>;
+ clock-output-names = "clkxtal";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a73-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c080000 0 0x200000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x1000>, /* GICH */
+ <0 0x0c420000 0 0x2000>; /* GICV */
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ clock-controller@10001000 {
+ compatible = "mediatek,mt7988-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@1001b000 {
+ compatible = "mediatek,mt7988-topckgen", "syscon";
+ reg = <0 0x1001b000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ watchdog: watchdog@1001c000 {
+ compatible = "mediatek,mt7988-wdt";
+ reg = <0 0x1001c000 0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ clock-controller@1001e000 {
+ compatible = "mediatek,mt7988-apmixedsys";
+ reg = <0 0x1001e000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@11f40000 {
+ compatible = "mediatek,mt7988-xfi-pll";
+ reg = <0 0x11f40000 0 0x1000>;
+ resets = <&watchdog 16>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@15000000 {
+ compatible = "mediatek,mt7988-ethsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock-controller@15031000 {
+ compatible = "mediatek,mt7988-ethwarp";
+ reg = <0 0x15031000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
&cpu_thermal {
trips {
- cpu_crit: cpu_crit0 {
+ cpu_crit: cpu-crit0 {
temperature = <100000>;
type = "critical";
};
compatible = "mediatek,mt6397-rtc";
};
- syscfg_pctl_pmic: syscfg_pctl_pmic@c000 {
+ syscfg_pctl_pmic: syscon@c000 {
compatible = "mediatek,mt6397-pctl-pmic-syscfg",
"syscon";
reg = <0 0x0000c000 0 0x0108>;
spi-max-frequency = <12000000>;
interrupts-extended = <&pio 0 IRQ_TYPE_LEVEL_LOW>;
google,cros-ec-spi-msg-delay = <500>;
+ wakeup-source;
i2c_tunnel: i2c-tunnel0 {
compatible = "google,cros-ec-i2c-tunnel";
extcon_usb: extcon_iddig {
compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
+ id-gpios = <&pio 16 GPIO_ACTIVE_HIGH>;
};
usb_p1_vbus: regulator-usb-p1 {
};
};
- pmu_a53 {
+ pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
- pmu_a72 {
+ pmu-a72 {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
type = "passive";
};
- cpu_crit: cpu_crit0 {
+ cpu_crit: cpu-crit0 {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
#address-cells = <2>;
#size-cells = <2>;
ranges;
- vpu_dma_reserved: vpu_dma_mem_region@b7000000 {
+ vpu_dma_reserved: vpu-dma-mem@b7000000 {
compatible = "shared-dma-pool";
reg = <0 0xb7000000 0 0x500000>;
alignment = <0x1000>;
#reset-cells = <1>;
};
- syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ syscfg_pctl_a: syscon@10005000 {
compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
reg = <0 0x10206000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ socinfo-data1@40 {
+ reg = <0x040 0x4>;
+ };
+
+ socinfo-data2@44 {
+ reg = <0x044 0x4>;
+ };
+
thermal_calibration: calib@528 {
reg = <0x528 0xc>;
};
};
&mmc1 {
- bt_reset: bt-reset {
+ bluetooth@2 {
+ reg = <2>;
compatible = "mediatek,mt7921s-bluetooth";
pinctrl-names = "default";
pinctrl-0 = <&bt_pins_reset>;
};
&cros_ec {
+ cbas {
+ compatible = "google,cros-cbas";
+ };
+
keyboard-controller {
compatible = "google,cros-ec-keyb-switches";
};
};
&cros_ec {
+ cbas {
+ compatible = "google,cros-cbas";
+ };
+
keyboard-controller {
compatible = "google,cros-ec-keyb-switches";
};
};
&cros_ec {
+ cbas {
+ compatible = "google,cros-cbas";
+ };
+
keyboard-controller {
compatible = "google,cros-ec-keyb-switches";
};
};
&mt6358_vgpu_reg {
- regulator-min-microvolt = <625000>;
regulator-max-microvolt = <900000>;
regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ec_ap_int_odl>;
+ wakeup-source;
i2c_tunnel: i2c-tunnel {
compatible = "google,cros-ec-i2c-tunnel";
google,usb-port-id = <0>;
};
- cbas {
- compatible = "google,cros-cbas";
- };
-
typec {
compatible = "google,cros-ec-typec";
#address-cells = <1>;
#size-cells = <2>;
ranges;
- scp_mem_reserved: scp_mem_region@50000000 {
+ scp_mem_reserved: scp-mem@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
reg = <0 0x11f10000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ socinfo-data1@4c {
+ reg = <0x04c 0x4>;
+ };
+
+ socinfo-data2@60 {
+ reg = <0x060 0x4>;
+ };
+
thermal_calibration: calib@180 {
reg = <0x180 0xc>;
};
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>;
};
gpu: gpu@13040000 {
power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
};
- venc_jpg: venc_jpg@17030000 {
+ venc_jpg: jpeg-encoder@17030000 {
compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
reg = <0 0x17030000 0 0x1000>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ i2c4 = &i2c4;
+ };
+};
+
+&dsi_out {
+ remote-endpoint = <&ps8640_in>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+
+ edp-bridge@8 {
+ compatible = "parade,ps8640";
+ reg = <0x8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ps8640_pins>;
+ powerdown-gpios = <&pio 96 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 98 GPIO_ACTIVE_LOW>;
+ vdd12-supply = <&mt6366_vrf12_reg>;
+ vdd33-supply = <&mt6366_vcn33_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ power-supply = <&pp3300_disp_x>;
+ backlight = <&backlight_lcd0>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&ps8640_out>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&i2c1 {
+ i2c-scl-internal-delay-ns = <10000>;
+
+ touchscreen: touchscreen@10 {
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+ post-power-on-delay-ms = <10>;
+ hid-descr-addr = <0x0001>;
+ vdd-supply = <&pp3300_s3>;
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ proximity@28 {
+ compatible = "semtech,sx9324";
+ reg = <0x28>;
+ #io-channel-cells = <1>;
+ interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sar_sensor_pins>;
+ vdd-supply = <&mt6366_vio18_reg>;
+ svdd-supply = <&mt6366_vio18_reg>;
+ };
+};
+
+&pio {
+ i2c4_pins: i2c4-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO136__FUNC_SDA4>,
+ <PINMUX_GPIO135__FUNC_SCL4>;
+ bias-disable;
+ drive-strength = <4>;
+ input-enable;
+ };
+ };
+
+ ps8640_pins: ps8640-pins {
+ pins-pwrdn-rst {
+ pinmux = <PINMUX_GPIO96__FUNC_GPIO96>,
+ <PINMUX_GPIO98__FUNC_GPIO98>;
+ output-low;
+ };
+ };
+
+ sar_sensor_pins: sar-sensor-pins {
+ pins-irq {
+ pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
+ input-enable;
+ bias-pull-up;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-steelix.dtsi"
+
+/ {
+ model = "Google Magneton board";
+ compatible = "google,steelix-sku393219", "google,steelix-sku393216",
+ "google,steelix", "mediatek,mt8186";
+ chassis-type = "laptop";
+};
+
+&gpio_keys {
+ status = "disabled";
+};
+
+&i2c1 {
+ touchscreen@10 {
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+ vdd-supply = <&pp3300_s3>;
+ post-power-on-delay-ms = <350>;
+ hid-descr-addr = <0x0001>;
+ };
+};
+
+&touchscreen {
+ status = "disabled";
+};
+
+&usb_c1 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-steelix.dtsi"
+
+/ {
+ model = "Google Magneton board";
+ compatible = "google,steelix-sku393220", "google,steelix-sku393217",
+ "google,steelix", "mediatek,mt8186";
+ chassis-type = "laptop";
+};
+
+&gpio_keys {
+ status = "disabled";
+};
+
+&i2c1 {
+ touchscreen@40 {
+ compatible = "hid-over-i2c";
+ reg = <0x40>;
+ interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+ vdd-supply = <&pp3300_s3>;
+ post-power-on-delay-ms = <450>;
+ hid-descr-addr = <0x0001>;
+ };
+};
+
+&touchscreen {
+ status = "disabled";
+};
+
+&usb_c1 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-steelix.dtsi"
+
+/ {
+ model = "Google Magneton board";
+ compatible = "google,steelix-sku393221", "google,steelix-sku393218",
+ "google,steelix", "mediatek,mt8186";
+ chassis-type = "laptop";
+};
+
+&gpio_keys {
+ status = "disabled";
+};
+
+&touchscreen {
+ status = "disabled";
+};
+
+&usb_c1 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-steelix.dtsi"
+
+/ {
+ model = "Google Rusty board";
+ compatible = "google,steelix-sku196609", "google,steelix-sku196608",
+ "google,steelix", "mediatek,mt8186";
+ chassis-type = "laptop";
+};
+
+&gpio_keys {
+ status = "disabled";
+};
+
+&i2c1 {
+ status = "disabled";
+};
+
+&touchscreen {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-steelix.dtsi"
+
+/ {
+ model = "Google Steelix board";
+ compatible = "google,steelix-sku131072", "google,steelix",
+ "mediatek,mt8186";
+ chassis-type = "convertible";
+};
+
+&mt6366codec {
+ mediatek,dmic-mode = <0>; /* two-wire */
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-steelix.dtsi"
+
+/ {
+ model = "Google Steelix board";
+ compatible = "google,steelix-sku131073", "google,steelix",
+ "mediatek,mt8186";
+ chassis-type = "convertible";
+};
+
+&mt6366codec {
+ mediatek,dmic-mode = <1>; /* one-wire */
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/{
+ pp1000_edpbrdg: regulator-pp1000-edpbrdg {
+ compatible = "regulator-fixed";
+ regulator-name = "pp1000_edpbrdg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&en_pp1000_edpbrdg>;
+ enable-active-high;
+ regulator-boot-on;
+ gpio = <&pio 29 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&pp3300_z2>;
+ };
+
+ pp1800_edpbrdg_dx: regulator-pp1800-edpbrdg-dx {
+ compatible = "regulator-fixed";
+ regulator-name = "pp1800_edpbrdg_dx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&en_pp1800_edpbrdg>;
+ enable-active-high;
+ regulator-boot-on;
+ gpio = <&pio 30 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&mt6366_vio18_reg>;
+ };
+
+ pp3300_edp_dx: regulator-pp3300-edp-dx {
+ compatible = "regulator-fixed";
+ regulator-name = "pp3300_edp_dx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&en_pp3300_edpbrdg>;
+ enable-active-high;
+ regulator-boot-on;
+ gpio = <&pio 31 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&pp3300_z2>;
+ };
+};
+
+&dsi_out {
+ remote-endpoint = <&anx7625_in>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+
+ anx_bridge: anx7625@58 {
+ compatible = "analogix,anx7625";
+ reg = <0x58>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&anx7625_pins>;
+ enable-gpios = <&pio 96 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>;
+ vdd10-supply = <&pp1000_edpbrdg>;
+ vdd18-supply = <&pp1800_edpbrdg_dx>;
+ vdd33-supply = <&pp3300_edp_dx>;
+ analogix,lane0-swing = /bits/ 8 <0x70 0x30>;
+ analogix,lane1-swing = /bits/ 8 <0x70 0x30>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ anx7625_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ anx7625_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ aux-bus {
+ panel: panel {
+ compatible = "edp-panel";
+ power-supply = <&pp3300_disp_x>;
+ backlight = <&backlight_lcd0>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&anx7625_out>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&i2c1 {
+ touchscreen: touchscreen@5d {
+ compatible = "goodix,gt7375p";
+ reg = <0x5d>;
+ interrupts-extended = <&pio 12 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+ reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&pp3300_s3>;
+ goodix,no-reset-during-suspend;
+ };
+};
+
+&i2c2 {
+ i2c-scl-internal-delay-ns = <22000>;
+
+ /* second source component */
+ trackpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ hid-descr-addr = <0x20>;
+ interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>;
+ vdd-supply = <&pp3300_s3>;
+ wakeup-source;
+ };
+};
+
+&keyboard_controller {
+ function-row-physmap = <
+ MATRIX_KEY(0x00, 0x02, 0) /* T1 */
+ MATRIX_KEY(0x03, 0x02, 0) /* T2 */
+ MATRIX_KEY(0x02, 0x02, 0) /* T3 */
+ MATRIX_KEY(0x01, 0x02, 0) /* T4 */
+ MATRIX_KEY(0x03, 0x04, 0) /* T5 */
+ MATRIX_KEY(0x02, 0x04, 0) /* T6 */
+ MATRIX_KEY(0x01, 0x04, 0) /* T7 */
+ MATRIX_KEY(0x02, 0x09, 0) /* T8 */
+ MATRIX_KEY(0x01, 0x09, 0) /* T9 */
+ MATRIX_KEY(0x00, 0x04, 0) /* T10 */
+ >;
+
+ linux,keymap = <
+ MATRIX_KEY(0x00, 0x02, KEY_BACK)
+ MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+ MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
+ MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+ MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN)
+ MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP)
+ MATRIX_KEY(0x01, 0x04, KEY_MICMUTE)
+ MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+ MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+ CROS_STD_MAIN_KEYMAP
+ >;
+};
+
+&pio {
+ anx7625_pins: anx7625-pins {
+ pins-int {
+ pinmux = <PINMUX_GPIO9__FUNC_GPIO9>;
+ input-enable;
+ bias-disable;
+ };
+
+ pins-reset {
+ pinmux = <PINMUX_GPIO98__FUNC_GPIO98>;
+ output-low;
+ };
+
+ pins-power-en {
+ pinmux = <PINMUX_GPIO96__FUNC_GPIO96>;
+ output-low;
+ };
+ };
+
+ en_pp1000_edpbrdg: pp1000-edpbrdg-en-pins {
+ pins-vreg-en {
+ pinmux = <PINMUX_GPIO29__FUNC_GPIO29>;
+ output-low;
+ };
+ };
+
+ en_pp1800_edpbrdg: pp1800-edpbrdg-en-pins {
+ pins-vreg-en {
+ pinmux = <PINMUX_GPIO30__FUNC_GPIO30>;
+ output-low;
+ };
+ };
+
+ en_pp3300_edpbrdg: pp3300-edpbrdg-en-pins {
+ pins-vreg-en {
+ pinmux = <PINMUX_GPIO31__FUNC_GPIO31>;
+ output-low;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-krabby.dtsi"
+
+/ {
+ model = "Google Tentacool board";
+ compatible = "google,tentacruel-sku327681", "google,tentacruel", "mediatek,mt8186";
+ chassis-type = "laptop";
+};
+
+/* Tentacool omits the pen. */
+&gpio_keys {
+ status = "disabled";
+};
+
+/* Tentacool omits the touchscreen; nothing else is on i2c1. */
+&i2c1 {
+ status = "disabled";
+};
+
+&keyboard_controller {
+ function-row-physmap = <
+ MATRIX_KEY(0x00, 0x02, 0) /* T1 */
+ MATRIX_KEY(0x03, 0x02, 0) /* T2 */
+ MATRIX_KEY(0x02, 0x02, 0) /* T3 */
+ MATRIX_KEY(0x01, 0x02, 0) /* T4 */
+ MATRIX_KEY(0x03, 0x04, 0) /* T5 */
+ MATRIX_KEY(0x02, 0x04, 0) /* T6 */
+ MATRIX_KEY(0x01, 0x04, 0) /* T7 */
+ MATRIX_KEY(0x02, 0x09, 0) /* T8 */
+ MATRIX_KEY(0x01, 0x09, 0) /* T9 */
+ MATRIX_KEY(0x00, 0x04, 0) /* T10 */
+ >;
+
+ linux,keymap = <
+ MATRIX_KEY(0x00, 0x02, KEY_BACK)
+ MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+ MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
+ MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+ MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
+ MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+ MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+ MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+ MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+ CROS_STD_MAIN_KEYMAP
+ >;
+};
+
+/* Tentacool omits the touchscreen. */
+&touchscreen {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+#include "mt8186-corsola-tentacool-sku327681.dts"
+
+/ {
+ compatible = "google,tentacruel-sku327683", "google,tentacruel", "mediatek,mt8186";
+};
+
+/* This variant replaces only the trackpad controller. */
+&i2c2 {
+ /delete-node/ trackpad@15;
+
+ trackpad@15 {
+ compatible = "hid-over-i2c";
+ reg = <0x15>;
+ interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>;
+ hid-descr-addr = <0x0001>;
+ vdd-supply = <&pp3300_s3>;
+ wakeup-source;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-krabby.dtsi"
+
+/ {
+ model = "Google Tentacruel board";
+ compatible = "google,tentacruel-sku262147", "google,tentacruel-sku262146",
+ "google,tentacruel-sku262145", "google,tentacruel-sku262144",
+ "google,tentacruel", "mediatek,mt8186";
+ chassis-type = "convertible";
+};
+
+&keyboard_controller {
+ function-row-physmap = <
+ MATRIX_KEY(0x00, 0x02, 0) /* T1 */
+ MATRIX_KEY(0x03, 0x02, 0) /* T2 */
+ MATRIX_KEY(0x02, 0x02, 0) /* T3 */
+ MATRIX_KEY(0x01, 0x02, 0) /* T4 */
+ MATRIX_KEY(0x03, 0x04, 0) /* T5 */
+ MATRIX_KEY(0x02, 0x04, 0) /* T6 */
+ MATRIX_KEY(0x01, 0x04, 0) /* T7 */
+ MATRIX_KEY(0x02, 0x09, 0) /* T8 */
+ MATRIX_KEY(0x01, 0x09, 0) /* T9 */
+ MATRIX_KEY(0x00, 0x04, 0) /* T10 */
+ >;
+
+ linux,keymap = <
+ MATRIX_KEY(0x00, 0x02, KEY_BACK)
+ MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+ MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
+ MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+ MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
+ MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+ MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+ MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+ MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+ CROS_STD_MAIN_KEYMAP
+ >;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+#include "mt8186-corsola-tentacruel-sku262144.dts"
+
+/ {
+ compatible = "google,tentacruel-sku262151", "google,tentacruel-sku262150",
+ "google,tentacruel-sku262149", "google,tentacruel-sku262148",
+ "google,tentacruel", "mediatek,mt8186";
+};
+
+/* This variant replaces only the trackpad controller. */
+&i2c2 {
+ /delete-node/ trackpad@15;
+
+ trackpad@15 {
+ compatible = "hid-over-i2c";
+ reg = <0x15>;
+ interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>;
+ hid-descr-addr = <0x0001>;
+ vdd-supply = <&pp3300_s3>;
+ wakeup-source;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+/dts-v1/;
+#include "mt8186.dtsi"
+#include <dt-bindings/pinctrl/mt8186-pinfunc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/regulator/mediatek,mt6397-regulator.h>
+
+/ {
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c5 = &i2c5;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ /* The size should be filled in by the bootloader. */
+ reg = <0 0x40000000 0 0>;
+ };
+
+ backlight_lcd0: backlight-lcd0 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 500000>;
+ power-supply = <&ppvar_sys>;
+ enable-gpios = <&pio 152 0>;
+ brightness-levels = <0 1023>;
+ num-interpolated-steps = <1023>;
+ default-brightness-level = <576>;
+ };
+
+ bt-sco-codec {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <0>;
+ };
+
+ dmic-codec {
+ compatible = "dmic-codec";
+ #sound-dai-cells = <0>;
+ num-channels = <2>;
+ wakeup-delay-ms = <50>;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pen_eject>;
+
+ pen_insert: pen-insert-switch {
+ label = "Pen Insert";
+ /* Insert = low, eject = high */
+ gpios = <&pio 18 GPIO_ACTIVE_LOW>;
+ wakeup-event-action = <EV_ACT_DEASSERTED>;
+ wakeup-source;
+ linux,code = <SW_PEN_INSERTED>;
+ linux,input-type = <EV_SW>;
+ };
+ };
+
+ pp1800_dpbrdg_dx: regulator-pp1800-dpbrdg-dx {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&en_pp1800_dpbrdg>;
+ gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+ regulator-name = "pp1800_dpbrdg_dx";
+ enable-active-high;
+ vin-supply = <&mt6366_vio18_reg>;
+ };
+
+ pp3300_disp_x: regulator-pp3300-disp-x {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_panel_fixed_pins>;
+ gpios = <&pio 153 GPIO_ACTIVE_HIGH>;
+ regulator-name = "pp3300_disp_x";
+ enable-active-high;
+ regulator-boot-on;
+ vin-supply = <&pp3300_z2>;
+ };
+
+ /* system wide LDO 3.3V power rail */
+ pp3300_z5: regulator-pp3300-ldo-z5 {
+ compatible = "regulator-fixed";
+ regulator-name = "pp3300_ldo_z5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&ppvar_sys>;
+ };
+
+ /* separately switched 3.3V power rail */
+ pp3300_s3: regulator-pp3300-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "pp3300_s3";
+ /* automatically sequenced by PMIC EXT_PMIC_EN2 */
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&pp3300_z2>;
+ };
+
+ /* system wide 3.3V power rail */
+ pp3300_z2: regulator-pp3300-z2 {
+ compatible = "regulator-fixed";
+ regulator-name = "pp3300_z2";
+ /* EN pin tied to pp4200_z2, which is controlled by EC */
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&ppvar_sys>;
+ };
+
+ /* system wide 4.2V power rail */
+ pp4200_z2: regulator-pp4200-z2 {
+ compatible = "regulator-fixed";
+ regulator-name = "pp4200_z2";
+ /* controlled by EC */
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4200000>;
+ regulator-max-microvolt = <4200000>;
+ vin-supply = <&ppvar_sys>;
+ };
+
+ /* system wide switching 5.0V power rail */
+ pp5000_z2: regulator-pp5000-z2 {
+ compatible = "regulator-fixed";
+ regulator-name = "pp5000_z2";
+ /* controlled by EC */
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&ppvar_sys>;
+ };
+
+ /* system wide semi-regulated power rail from battery or USB */
+ ppvar_sys: regulator-ppvar-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "ppvar_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ adsp_dma_mem: memory@61000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x61000000 0 0x100000>;
+ no-map;
+ };
+
+ adsp_mem: memory@60000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x60000000 0 0xA00000>;
+ no-map;
+ };
+
+ scp_mem: memory@50000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x50000000 0 0x10a0000>;
+ no-map;
+ };
+ };
+
+ sound: sound {
+ compatible = "mediatek,mt8186-mt6366-rt1019-rt5682s-sound";
+ pinctrl-names = "aud_clk_mosi_off",
+ "aud_clk_mosi_on",
+ "aud_clk_miso_off",
+ "aud_clk_miso_on",
+ "aud_dat_miso_off",
+ "aud_dat_miso_on",
+ "aud_dat_mosi_off",
+ "aud_dat_mosi_on",
+ "aud_gpio_i2s0_off",
+ "aud_gpio_i2s0_on",
+ "aud_gpio_i2s1_off",
+ "aud_gpio_i2s1_on",
+ "aud_gpio_i2s2_off",
+ "aud_gpio_i2s2_on",
+ "aud_gpio_i2s3_off",
+ "aud_gpio_i2s3_on",
+ "aud_gpio_pcm_off",
+ "aud_gpio_pcm_on",
+ "aud_gpio_dmic_sec";
+ pinctrl-0 = <&aud_clk_mosi_off>;
+ pinctrl-1 = <&aud_clk_mosi_on>;
+ pinctrl-2 = <&aud_clk_miso_off>;
+ pinctrl-3 = <&aud_clk_miso_on>;
+ pinctrl-4 = <&aud_dat_miso_off>;
+ pinctrl-5 = <&aud_dat_miso_on>;
+ pinctrl-6 = <&aud_dat_mosi_off>;
+ pinctrl-7 = <&aud_dat_mosi_on>;
+ pinctrl-8 = <&aud_gpio_i2s0_off>;
+ pinctrl-9 = <&aud_gpio_i2s0_on>;
+ pinctrl-10 = <&aud_gpio_i2s1_off>;
+ pinctrl-11 = <&aud_gpio_i2s1_on>;
+ pinctrl-12 = <&aud_gpio_i2s2_off>;
+ pinctrl-13 = <&aud_gpio_i2s2_on>;
+ pinctrl-14 = <&aud_gpio_i2s3_off>;
+ pinctrl-15 = <&aud_gpio_i2s3_on>;
+ pinctrl-16 = <&aud_gpio_pcm_off>;
+ pinctrl-17 = <&aud_gpio_pcm_on>;
+ pinctrl-18 = <&aud_gpio_dmic_sec>;
+ mediatek,adsp = <&adsp>;
+ mediatek,platform = <&afe>;
+
+ playback-codecs {
+ sound-dai = <&it6505dptx>, <&rt1019p>;
+ };
+
+ headset-codec {
+ sound-dai = <&rt5682s 0>;
+ };
+ };
+
+ rt1019p: speaker-codec {
+ compatible = "realtek,rt1019p";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rt1019p_pins_default>;
+ #sound-dai-cells = <0>;
+ sdb-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
+ };
+
+ usb_p1_vbus: regulator-usb-p1-vbus {
+ compatible = "regulator-fixed";
+ gpio = <&pio 148 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vbus1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ vin-supply = <&pp5000_z2>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_pin>;
+ post-power-on-delay-ms = <50>;
+ reset-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi_wakeup: wifi-wakeup {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_wakeup_pin>;
+
+ wowlan-event {
+ label = "Wake on WiFi";
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+};
+
+&adsp {
+ memory-region = <&adsp_dma_mem>, <&adsp_mem>;
+ status = "okay";
+};
+
+&afe {
+ status = "okay";
+};
+
+&cci {
+ proc-supply = <&mt6366_vproc12_reg>;
+};
+
+&cpu0 {
+ proc-supply = <&mt6366_vproc12_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6366_vproc12_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6366_vproc12_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6366_vproc12_reg>;
+};
+
+&cpu4 {
+ proc-supply = <&mt6366_vproc12_reg>;
+};
+
+&cpu5 {
+ proc-supply = <&mt6366_vproc12_reg>;
+};
+
+&cpu6 {
+ proc-supply = <&mt6366_vproc11_reg>;
+};
+
+&cpu7 {
+ proc-supply = <&mt6366_vproc11_reg>;
+};
+
+&dpi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dpi_pins_default>;
+ pinctrl-1 = <&dpi_pins_sleep>;
+ status = "okay";
+};
+
+&dpi_out {
+ remote-endpoint = <&it6505_in>;
+};
+
+&dsi0 {
+ status = "okay";
+};
+
+&gic {
+ mediatek,broken-save-restore-fw;
+};
+
+&gpu {
+ mali-supply = <&mt6366_vgpu_reg>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+ i2c-scl-internal-delay-ns = <8000>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ /*
+ * Trackpad pin put here to work around second source components
+ * sharing the pinmux in steelix designs.
+ */
+ pinctrl-0 = <&i2c2_pins>, <&trackpad_pin>;
+ clock-frequency = <400000>;
+ i2c-scl-internal-delay-ns = <10000>;
+ status = "okay";
+
+ trackpad@15 {
+ compatible = "elan,ekth3000";
+ reg = <0x15>;
+ interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>;
+ vcc-supply = <&pp3300_s3>;
+ wakeup-source;
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ it6505dptx: dp-bridge@5c {
+ compatible = "ite,it6505";
+ reg = <0x5c>;
+ interrupts-extended = <&pio 8 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&it6505_pins>;
+ #sound-dai-cells = <0>;
+ ovdd-supply = <&mt6366_vsim2_reg>;
+ pwr18-supply = <&pp1800_dpbrdg_dx>;
+ reset-gpios = <&pio 177 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ it6505_in: endpoint {
+ link-frequencies = /bits/ 64 <150000000>;
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ status = "okay";
+
+ rt5682s: codec@1a {
+ compatible = "realtek,rt5682s";
+ reg = <0x1a>;
+ interrupts-extended = <&pio 17 IRQ_TYPE_EDGE_BOTH>;
+ #sound-dai-cells = <1>;
+ AVDD-supply = <&mt6366_vio18_reg>;
+ DBVDD-supply = <&mt6366_vio18_reg>;
+ LDO1-IN-supply = <&mt6366_vio18_reg>;
+ MICVDD-supply = <&pp3300_z2>;
+ realtek,jd-src = <1>;
+ };
+};
+
+&mfg0 {
+ domain-supply = <&mt6366_vsram_gpu_reg>;
+};
+
+&mfg1 {
+ domain-supply = <&mt6366_vgpu_reg>;
+};
+
+&mipi_tx0 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ supports-cqe;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
+ hs400-ds-delay = <0x11814>;
+ mediatek,hs400-ds-dly3 = <0x14>;
+ vmmc-supply = <&mt6366_vemc_reg>;
+ vqmmc-supply = <&mt6366_vio18_reg>;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default", "state_uhs", "state_eint";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_uhs>;
+ pinctrl-2 = <&mmc1_pins_eint>;
+ /delete-property/ interrupts;
+ interrupt-names = "msdc", "sdio_wakeup";
+ interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&pio 87 IRQ_TYPE_LEVEL_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-sd-highspeed;
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ keep-power-in-suspend;
+ wakeup-source;
+ cap-sdio-irq;
+ no-mmc;
+ no-sd;
+ non-removable;
+ vmmc-supply = <&pp3300_s3>;
+ vqmmc-supply = <&mt6366_vio18_reg>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ status = "okay";
+
+ bluetooth@2 {
+ compatible = "mediatek,mt7921s-bluetooth";
+ reg = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_pins_reset>;
+ reset-gpios = <&pio 155 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&nor_flash {
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D7_D4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&nor_pins_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <39000000>;
+ };
+};
+
+&pio {
+ /* 185 lines */
+ gpio-line-names = "TP",
+ "TP",
+ "TP",
+ "I2S0_HP_DI",
+ "I2S3_DP_SPKR_DO",
+ "SAR_INT_ODL",
+ "BT_WAKE_AP_ODL",
+ "WIFI_INT_ODL",
+ "DPBRDG_INT_ODL",
+ "EDPBRDG_INT_ODL",
+ "EC_AP_HPD_OD",
+ "TCHPAD_INT_ODL",
+ "TCHSCR_INT_1V8_ODL",
+ "EC_AP_INT_ODL",
+ "EC_IN_RW_ODL",
+ "GSC_AP_INT_ODL",
+ /* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */
+ "AP_FLASH_WP_L",
+ "HP_INT_ODL",
+ "PEN_EJECT_OD",
+ "WCAM_PWDN_L",
+ "WCAM_RST_L",
+ "UCAM_SEN_EN",
+ "UCAM_RST_L",
+ "LTE_RESET_L",
+ "LTE_SAR_DETECT_L",
+ "I2S2_DP_SPK_MCK",
+ "I2S2_DP_SPKR_BCK",
+ "I2S2_DP_SPKR_LRCK",
+ "I2S2_DP_SPKR_DI (TP)",
+ "EN_PP1000_EDPBRDG",
+ "EN_PP1800_EDPBRDG",
+ "EN_PP3300_EDPBRDG",
+ "UART_GSC_TX_AP_RX",
+ "UART_AP_TX_GSC_RX",
+ "UART_DBGCON_TX_ADSP_RX",
+ "UART_ADSP_TX_DBGCON_RX",
+ "EN_PP1000_DPBRDG",
+ "TCHSCR_REPORT_DISABLE",
+ "EN_PP3300_DPBRDG",
+ "EN_PP1800_DPBRDG",
+ "SPI_AP_CLK_EC",
+ "SPI_AP_CS_EC_L",
+ "SPI_AP_DO_EC_DI",
+ "SPI_AP_DI_EC_DO",
+ "SPI_AP_CLK_GSC",
+ "SPI_AP_CS_GSC_L",
+ "SPI_AP_DO_GSC_DI",
+ "SPI_AP_DI_GSC_DO",
+ "UART_DBGCON_TX_SCP_RX",
+ "UART_SCP_TX_DBGCON_RX",
+ "EN_PP1200_CAM_X",
+ "EN_PP2800A_VCM_X",
+ "EN_PP2800A_UCAM_X",
+ "EN_PP2800A_WCAM_X",
+ "WLAN_MODULE_RST_L",
+ "EN_PP1200_UCAM_X",
+ "I2S1_HP_DO",
+ "I2S1_HP_BCK",
+ "I2S1_HP_LRCK",
+ "I2S1_HP_MCK",
+ "TCHSCR_RST_1V8_L",
+ "SPI_AP_CLK_ROM",
+ "SPI_AP_CS_ROM_L",
+ "SPI_AP_DO_ROM_DI",
+ "SPI_AP_DI_ROM_DO",
+ "NC",
+ "NC",
+ "EMMC_STRB",
+ "EMMC_CLK",
+ "EMMC_CMD",
+ "EMMC_RST_L",
+ "EMMC_DATA0",
+ "EMMC_DATA1",
+ "EMMC_DATA2",
+ "EMMC_DATA3",
+ "EMMC_DATA4",
+ "EMMC_DATA5",
+ "EMMC_DATA6",
+ "EMMC_DATA7",
+ "AP_KPCOL0",
+ "NC",
+ "NC",
+ "NC",
+ "TP",
+ "SDIO_CLK",
+ "SDIO_CMD",
+ "SDIO_DATA0",
+ "SDIO_DATA1",
+ "SDIO_DATA2",
+ "SDIO_DATA3",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "EDPBRDG_PWREN",
+ "BL_PWM_1V8",
+ "EDPBRDG_RST_L",
+ "MIPI_DPI_CLK",
+ "MIPI_DPI_VSYNC",
+ "MIPI_DPI_HSYNC",
+ "MIPI_DPI_DE",
+ "MIPI_DPI_D0",
+ "MIPI_DPI_D1",
+ "MIPI_DPI_D2",
+ "MIPI_DPI_D3",
+ "MIPI_DPI_D4",
+ "MIPI_DPI_D5",
+ "MIPI_DPI_D6",
+ "MIPI_DPI_DA7",
+ "MIPI_DPI_D8",
+ "MIPI_DPI_D9",
+ "MIPI_DPI_D10",
+ "MIPI_DPI_D11",
+ "PCM_BT_CLK",
+ "PCM_BT_SYNC",
+ "PCM_BT_DI",
+ "PCM_BT_DO",
+ "JTAG_TMS_TP",
+ "JTAG_TCK_TP",
+ "JTAG_TDI_TP",
+ "JTAG_TDO_TP",
+ "JTAG_TRSTN_TP",
+ "CLK_24M_WCAM",
+ "CLK_24M_UCAM",
+ "UCAM_DET_ODL",
+ "AP_I2C_EDPBRDG_SCL_1V8",
+ "AP_I2C_EDPBRDG_SDA_1V8",
+ "AP_I2C_TCHSCR_SCL_1V8",
+ "AP_I2C_TCHSCR_SDA_1V8",
+ "AP_I2C_TCHPAD_SCL_1V8",
+ "AP_I2C_TCHPAD_SDA_1V8",
+ "AP_I2C_DPBRDG_SCL_1V8",
+ "AP_I2C_DPBRDG_SDA_1V8",
+ "AP_I2C_WLAN_SCL_1V8",
+ "AP_I2C_WLAN_SDA_1V8",
+ "AP_I2C_AUD_SCL_1V8",
+ "AP_I2C_AUD_SDA_1V8",
+ "AP_I2C_TPM_SCL_1V8",
+ "AP_I2C_UCAM_SDA_1V8",
+ "AP_I2C_UCAM_SCL_1V8",
+ "AP_I2C_UCAM_SDA_1V8",
+ "AP_I2C_WCAM_SCL_1V8",
+ "AP_I2C_WCAM_SDA_1V8",
+ "SCP_I2C_SENSOR_SCL_1V8",
+ "SCP_I2C_SENSOR_SDA_1V8",
+ "AP_EC_WARM_RST_REQ",
+ "AP_XHCI_INIT_DONE",
+ "USB3_HUB_RST_L",
+ "EN_SPKR",
+ "BEEP_ON",
+ "AP_EDP_BKLTEN",
+ "EN_PP3300_DISP_X",
+ "EN_PP3300_SDBRDG_X",
+ "BT_KILL_1V8_L",
+ "WIFI_KILL_1V8_L",
+ "PWRAP_SPI0_CSN",
+ "PWRAP_SPI0_CK",
+ "PWRAP_SPI0_MO",
+ "PWRAP_SPI0_MI",
+ "SRCLKENA0",
+ "SRCLKENA1",
+ "SCP_VREQ_VAO",
+ "AP_RTC_CLK32K",
+ "AP_PMIC_WDTRST_L",
+ "AUD_CLK_MOSI",
+ "AUD_SYNC_MOSI",
+ "AUD_DAT_MOSI0",
+ "AUD_DAT_MOSI1",
+ "AUD_CLK_MISO",
+ "AUD_SYNC_MISO",
+ "AUD_DAT_MISO0",
+ "AUD_DAT_MISO1",
+ "NC",
+ "NC",
+ "DPBRDG_PWREN",
+ "DPBRDG_RST_L",
+ "LTE_W_DISABLE_L",
+ "LTE_SAR_DETECT_L",
+ "EN_PP3300_LTE_X",
+ "LTE_PWR_OFF_L",
+ "LTE_RESET_L",
+ "TP",
+ "TP";
+
+ aud_clk_mosi_off: aud-clk-mosi-off-pins {
+ pins-clk-sync {
+ pinmux = <PINMUX_GPIO166__FUNC_GPIO166>,
+ <PINMUX_GPIO167__FUNC_GPIO167>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ aud_clk_mosi_on: aud-clk-mosi-on-pins {
+ pins-clk-sync {
+ pinmux = <PINMUX_GPIO166__FUNC_AUD_CLK_MOSI>,
+ <PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI>;
+ };
+ };
+
+ aud_clk_miso_off: aud-clk-miso-off-pins {
+ pins-clk-sync {
+ pinmux = <PINMUX_GPIO170__FUNC_GPIO170>,
+ <PINMUX_GPIO171__FUNC_GPIO171>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ aud_clk_miso_on: aud-clk-miso-on-pins {
+ pins-clk-sync {
+ pinmux = <PINMUX_GPIO170__FUNC_AUD_CLK_MISO>,
+ <PINMUX_GPIO171__FUNC_AUD_SYNC_MISO>;
+ };
+ };
+
+ aud_dat_mosi_off: aud-dat-mosi-off-pins {
+ pins-dat {
+ pinmux = <PINMUX_GPIO168__FUNC_GPIO168>,
+ <PINMUX_GPIO169__FUNC_GPIO169>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ aud_dat_mosi_on: aud-dat-mosi-on-pins {
+ pins-dat {
+ pinmux = <PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0>,
+ <PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1>;
+ };
+ };
+
+ aud_dat_miso_off: aud-dat-miso-off-pins {
+ pins-dat {
+ pinmux = <PINMUX_GPIO172__FUNC_GPIO172>,
+ <PINMUX_GPIO173__FUNC_GPIO173>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ aud_dat_miso_on: aud-dat-miso-on-pins {
+ pins-dat {
+ pinmux = <PINMUX_GPIO172__FUNC_AUD_DAT_MISO0>,
+ <PINMUX_GPIO173__FUNC_AUD_DAT_MISO1>;
+ input-schmitt-enable;
+ bias-disable;
+ };
+ };
+
+ aud_gpio_i2s0_off: aud-gpio-i2s0-off-pins {
+ pins-sdata {
+ pinmux = <PINMUX_GPIO3__FUNC_GPIO3>;
+ };
+ };
+
+ aud_gpio_i2s0_on: aud-gpio-i2s0-on-pins {
+ pins-sdata {
+ pinmux = <PINMUX_GPIO3__FUNC_I2S0_DI>;
+ };
+ };
+
+ aud_gpio_i2s1_off: aud-gpio-i2s-off-pins {
+ pins-clk-sdata {
+ pinmux = <PINMUX_GPIO56__FUNC_GPIO56>,
+ <PINMUX_GPIO57__FUNC_GPIO57>,
+ <PINMUX_GPIO58__FUNC_GPIO58>,
+ <PINMUX_GPIO59__FUNC_GPIO59>;
+ output-low;
+ };
+ };
+
+ aud_gpio_i2s1_on: aud-gpio-i2s1-on-pins {
+ pins-clk-sdata {
+ pinmux = <PINMUX_GPIO56__FUNC_I2S1_DO>,
+ <PINMUX_GPIO57__FUNC_I2S1_BCK>,
+ <PINMUX_GPIO58__FUNC_I2S1_LRCK>,
+ <PINMUX_GPIO59__FUNC_I2S1_MCK>;
+ };
+ };
+
+ aud_gpio_i2s2_off: aud-gpio-i2s2-off-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO26__FUNC_GPIO26>,
+ <PINMUX_GPIO27__FUNC_GPIO27>;
+ output-low;
+ };
+ };
+
+ aud_gpio_i2s2_on: aud-gpio-i2s2-on-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO26__FUNC_I2S2_BCK>,
+ <PINMUX_GPIO27__FUNC_I2S2_LRCK>;
+ drive-strength = <4>;
+ };
+ };
+
+ aud_gpio_i2s3_off: aud-gpio-i2s3-off-pins {
+ pins-sdata {
+ pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
+ output-low;
+ };
+ };
+
+ aud_gpio_i2s3_on: aud-gpio-i2s3-on-pins {
+ pins-sdata {
+ pinmux = <PINMUX_GPIO4__FUNC_I2S3_DO>;
+ drive-strength = <4>;
+ };
+ };
+
+ aud_gpio_pcm_off: aud-gpio-pcm-off-pins {
+ pins-clk-sdata {
+ pinmux = <PINMUX_GPIO115__FUNC_GPIO115>,
+ <PINMUX_GPIO116__FUNC_GPIO116>,
+ <PINMUX_GPIO117__FUNC_GPIO117>,
+ <PINMUX_GPIO118__FUNC_GPIO118>;
+ output-low;
+ };
+ };
+
+ aud_gpio_pcm_on: aud-gpio-pcm-on-pins {
+ pins-clk-sdata {
+ pinmux = <PINMUX_GPIO115__FUNC_PCM_CLK>,
+ <PINMUX_GPIO116__FUNC_PCM_SYNC>,
+ <PINMUX_GPIO117__FUNC_PCM_DI>,
+ <PINMUX_GPIO118__FUNC_PCM_DO>;
+ };
+ };
+
+ aud_gpio_dmic_sec: aud-gpio-dmic-sec-pins {
+ pins {
+ pinmux = <PINMUX_GPIO23__FUNC_GPIO23>;
+ output-low;
+ };
+ };
+
+ bt_pins_reset: bt-reset-pins {
+ pins-bt-reset {
+ pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
+ output-high;
+ };
+ };
+
+ dpi_pins_sleep: dpi-sleep-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO103__FUNC_GPIO103>,
+ <PINMUX_GPIO104__FUNC_GPIO104>,
+ <PINMUX_GPIO105__FUNC_GPIO105>,
+ <PINMUX_GPIO106__FUNC_GPIO106>,
+ <PINMUX_GPIO107__FUNC_GPIO107>,
+ <PINMUX_GPIO108__FUNC_GPIO108>,
+ <PINMUX_GPIO109__FUNC_GPIO109>,
+ <PINMUX_GPIO110__FUNC_GPIO110>,
+ <PINMUX_GPIO111__FUNC_GPIO111>,
+ <PINMUX_GPIO112__FUNC_GPIO112>,
+ <PINMUX_GPIO113__FUNC_GPIO113>,
+ <PINMUX_GPIO114__FUNC_GPIO114>,
+ <PINMUX_GPIO101__FUNC_GPIO101>,
+ <PINMUX_GPIO100__FUNC_GPIO100>,
+ <PINMUX_GPIO102__FUNC_GPIO102>,
+ <PINMUX_GPIO99__FUNC_GPIO99>;
+ drive-strength = <10>;
+ output-low;
+ };
+ };
+
+ dpi_pins_default: dpi-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO103__FUNC_DPI_DATA0>,
+ <PINMUX_GPIO104__FUNC_DPI_DATA1>,
+ <PINMUX_GPIO105__FUNC_DPI_DATA2>,
+ <PINMUX_GPIO106__FUNC_DPI_DATA3>,
+ <PINMUX_GPIO107__FUNC_DPI_DATA4>,
+ <PINMUX_GPIO108__FUNC_DPI_DATA5>,
+ <PINMUX_GPIO109__FUNC_DPI_DATA6>,
+ <PINMUX_GPIO110__FUNC_DPI_DATA7>,
+ <PINMUX_GPIO111__FUNC_DPI_DATA8>,
+ <PINMUX_GPIO112__FUNC_DPI_DATA9>,
+ <PINMUX_GPIO113__FUNC_DPI_DATA10>,
+ <PINMUX_GPIO114__FUNC_DPI_DATA11>,
+ <PINMUX_GPIO101__FUNC_DPI_HSYNC>,
+ <PINMUX_GPIO100__FUNC_DPI_VSYNC>,
+ <PINMUX_GPIO102__FUNC_DPI_DE>,
+ <PINMUX_GPIO99__FUNC_DPI_PCLK>;
+ drive-strength = <10>;
+ };
+ };
+
+ ec_ap_int: cros-ec-int-pins {
+ pins-ec-ap-int-odl {
+ pinmux = <PINMUX_GPIO13__FUNC_GPIO13>;
+ input-enable;
+ };
+ };
+
+ edp_panel_fixed_pins: edp-panel-fixed-pins {
+ pins-vreg-en {
+ pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
+ output-high;
+ };
+ };
+
+ en_pp1800_dpbrdg: en-pp1800-dpbrdg-pins {
+ pins-vreg-en {
+ pinmux = <PINMUX_GPIO39__FUNC_GPIO39>;
+ output-low;
+ };
+ };
+
+ gsc_int: gsc-int-pins {
+ pins-gsc-ap-int-odl {
+ pinmux = <PINMUX_GPIO15__FUNC_GPIO15>;
+ input-enable;
+ };
+ };
+
+ i2c0_pins: i2c0-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>,
+ <PINMUX_GPIO127__FUNC_SCL0>;
+ bias-disable;
+ drive-strength = <4>;
+ input-enable;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO130__FUNC_SDA1>,
+ <PINMUX_GPIO129__FUNC_SCL1>;
+ bias-disable;
+ drive-strength = <4>;
+ input-enable;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO132__FUNC_SDA2>,
+ <PINMUX_GPIO131__FUNC_SCL2>;
+ bias-disable;
+ drive-strength = <4>;
+ input-enable;
+ };
+ };
+
+ i2c3_pins: i2c3-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO134__FUNC_SDA3>,
+ <PINMUX_GPIO133__FUNC_SCL3>;
+ bias-disable;
+ drive-strength = <4>;
+ input-enable;
+ };
+ };
+
+ i2c5_pins: i2c5-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO138__FUNC_SDA5>,
+ <PINMUX_GPIO137__FUNC_SCL5>;
+ bias-disable;
+ drive-strength = <4>;
+ input-enable;
+ };
+ };
+
+ it6505_pins: it6505-pins {
+ pins-hpd {
+ pinmux = <PINMUX_GPIO10__FUNC_GPIO10>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-int {
+ pinmux = <PINMUX_GPIO8__FUNC_GPIO8>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-reset {
+ pinmux = <PINMUX_GPIO177__FUNC_GPIO177>;
+ output-low;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_pins_default: mmc0-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO72__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO73__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO74__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO75__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO76__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO77__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO78__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO69__FUNC_MSDC0_CMD>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO72__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO73__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO74__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO75__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO76__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO77__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO78__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO69__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-ds {
+ pinmux = <PINMUX_GPIO67__FUNC_MSDC0_DSL>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_pins_default: mmc1-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO87__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO88__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO89__FUNC_MSDC1_DAT3>,
+ <PINMUX_GPIO85__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_pins_uhs: mmc1-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO87__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO88__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO89__FUNC_MSDC1_DAT3>,
+ <PINMUX_GPIO85__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_pins_eint: mmc1-eint-pins {
+ pins-dat1 {
+ pinmux = <PINMUX_GPIO87__FUNC_GPIO87>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ nor_pins_default: nor-default-pins {
+ pins-clk-dat {
+ pinmux = <PINMUX_GPIO63__FUNC_SPINOR_IO0>,
+ <PINMUX_GPIO61__FUNC_SPINOR_CK>,
+ <PINMUX_GPIO64__FUNC_SPINOR_IO1>;
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ pins-cs-dat {
+ pinmux = <PINMUX_GPIO62__FUNC_SPINOR_CS>,
+ <PINMUX_GPIO65__FUNC_SPINOR_IO2>,
+ <PINMUX_GPIO66__FUNC_SPINOR_IO3>;
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
+
+ pen_eject: pen-eject-pins {
+ pins {
+ pinmux = <PINMUX_GPIO18__FUNC_GPIO18>;
+ input-enable;
+ /* External pull-up. */
+ bias-disable;
+ };
+ };
+
+ pwm0_pin: disp-pwm-pins {
+ pins {
+ pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM>;
+ output-high;
+ };
+ };
+
+ rt1019p_pins_default: rt1019p-default-pins {
+ pins-sdb {
+ pinmux = <PINMUX_GPIO150__FUNC_GPIO150>;
+ output-low;
+ };
+ };
+
+ scp_pins: scp-default-pins {
+ pins-scp-uart {
+ pinmux = <PINMUX_GPIO48__FUNC_TP_URXD2_AO>,
+ <PINMUX_GPIO49__FUNC_TP_UTXD2_AO>;
+ };
+ };
+
+ spi1_pins: spi1-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO40__FUNC_SPI1_CLK_A>,
+ <PINMUX_GPIO41__FUNC_SPI1_CSB_A>,
+ <PINMUX_GPIO42__FUNC_SPI1_MO_A>,
+ <PINMUX_GPIO43__FUNC_SPI1_MI_A>;
+ bias-disable;
+ input-enable;
+ };
+ };
+
+ spi2_pins: spi2-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO44__FUNC_SPI2_CLK_A>,
+ <PINMUX_GPIO45__FUNC_GPIO45>,
+ <PINMUX_GPIO46__FUNC_SPI2_MO_A>,
+ <PINMUX_GPIO47__FUNC_SPI2_MI_A>;
+ bias-disable;
+ input-enable;
+ };
+ };
+
+ spmi_pins: spmi-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO183__FUNC_SPMI_SCL>,
+ <PINMUX_GPIO184__FUNC_SPMI_SDA>;
+ };
+ };
+
+ touchscreen_pins: touchscreen-pins {
+ pins-irq {
+ pinmux = <PINMUX_GPIO12__FUNC_GPIO12>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-reset {
+ pinmux = <PINMUX_GPIO60__FUNC_GPIO60>;
+ output-high;
+ };
+
+ pins-report-sw {
+ pinmux = <PINMUX_GPIO37__FUNC_GPIO37>;
+ output-low;
+ };
+ };
+
+ trackpad_pin: trackpad-default-pins {
+ pins-int-n {
+ pinmux = <PINMUX_GPIO11__FUNC_GPIO11>;
+ input-enable;
+ bias-disable; /* pulled externally */
+ };
+ };
+
+ wifi_enable_pin: wifi-enable-pins {
+ pins-wifi-enable {
+ pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
+ };
+ };
+
+ wifi_wakeup_pin: wifi-wakeup-pins {
+ pins-wifi-wakeup {
+ pinmux = <PINMUX_GPIO7__FUNC_GPIO7>;
+ input-enable;
+ };
+ };
+};
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ status = "okay";
+};
+
+&pwrap {
+ pmic {
+ compatible = "mediatek,mt6366", "mediatek,mt6358";
+ interrupt-controller;
+ interrupts-extended = <&pio 201 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+
+ mt6366codec: codec {
+ compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound";
+ Avdd-supply = <&mt6366_vaud28_reg>;
+ mediatek,dmic-mode = <1>; /* one-wire */
+ };
+
+ mt6366_regulators: regulators {
+ compatible = "mediatek,mt6366-regulator", "mediatek,mt6358-regulator";
+ vsys-ldo1-supply = <&pp4200_z2>;
+ vsys-ldo2-supply = <&pp4200_z2>;
+ vsys-ldo3-supply = <&pp4200_z2>;
+ vsys-vcore-supply = <&pp4200_z2>;
+ vsys-vdram1-supply = <&pp4200_z2>;
+ vsys-vgpu-supply = <&pp4200_z2>;
+ vsys-vmodem-supply = <&pp4200_z2>;
+ vsys-vpa-supply = <&pp4200_z2>;
+ vsys-vproc11-supply = <&pp4200_z2>;
+ vsys-vproc12-supply = <&pp4200_z2>;
+ vsys-vs1-supply = <&pp4200_z2>;
+ vsys-vs2-supply = <&pp4200_z2>;
+ vs1-ldo1-supply = <&mt6366_vs1_reg>;
+ vs2-ldo1-supply = <&mt6366_vdram1_reg>;
+ vs2-ldo2-supply = <&mt6366_vs2_reg>;
+ vs2-ldo3-supply = <&mt6366_vs2_reg>;
+
+ vcore {
+ regulator-name = "pp0750_dvdd_core";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <800000>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO
+ MT6397_BUCK_MODE_FORCE_PWM>;
+ regulator-always-on;
+ };
+
+ mt6366_vdram1_reg: vdram1 {
+ regulator-name = "pp1125_emi_vdd2";
+ regulator-min-microvolt = <1125000>;
+ regulator-max-microvolt = <1125000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO
+ MT6397_BUCK_MODE_FORCE_PWM>;
+ regulator-always-on;
+ };
+
+ mt6366_vgpu_reg: vgpu {
+ /*
+ * Called "ppvar_dvdd_gpu" in the schematic.
+ * Called "ppvar_dvdd_vgpu" here to match
+ * regulator coupling requirements.
+ */
+ regulator-name = "ppvar_dvdd_vgpu";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO
+ MT6397_BUCK_MODE_FORCE_PWM>;
+ regulator-coupled-with = <&mt6366_vsram_gpu_reg>;
+ regulator-coupled-max-spread = <10000>;
+ };
+
+ mt6366_vproc11_reg: vproc11 {
+ regulator-name = "ppvar_dvdd_proc_bc_mt6366";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO
+ MT6397_BUCK_MODE_FORCE_PWM>;
+ regulator-always-on;
+ };
+
+ mt6366_vproc12_reg: vproc12 {
+ regulator-name = "ppvar_dvdd_proc_lc";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO
+ MT6397_BUCK_MODE_FORCE_PWM>;
+ regulator-always-on;
+ };
+
+ mt6366_vs1_reg: vs1 {
+ regulator-name = "pp2000_vs1";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+
+ mt6366_vs2_reg: vs2 {
+ regulator-name = "pp1350_vs2";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+
+ va12 {
+ regulator-name = "pp1200_va12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <270>;
+ regulator-always-on;
+ };
+
+ mt6366_vaud28_reg: vaud28 {
+ regulator-name = "pp2800_vaud28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6366_vaux18_reg: vaux18 {
+ regulator-name = "pp1840_vaux18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1840000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6366_vbif28_reg: vbif28 {
+ regulator-name = "pp2800_vbif28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6366_vcn18_reg: vcn18 {
+ regulator-name = "pp1800_vcn18_x";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6366_vcn28_reg: vcn28 {
+ regulator-name = "pp2800_vcn28_x";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6366_vefuse_reg: vefuse {
+ regulator-name = "pp1800_vefuse";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6366_vfe28_reg: vfe28 {
+ regulator-name = "pp2800_vfe28_x";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6366_vemc_reg: vemc {
+ regulator-name = "pp3000_vemc";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <60>;
+ };
+
+ mt6366_vibr_reg: vibr {
+ regulator-name = "pp2800_vibr_x";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <60>;
+ };
+
+ mt6366_vio18_reg: vio18 {
+ regulator-name = "pp1800_vio18_s3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <2700>;
+ regulator-always-on;
+ };
+
+ mt6366_vio28_reg: vio28 {
+ regulator-name = "pp2800_vio28_x";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ mt6366_vm18_reg: vm18 {
+ regulator-name = "pp1800_emi_vdd1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1840000>;
+ regulator-enable-ramp-delay = <325>;
+ regulator-always-on;
+ };
+
+ mt6366_vmc_reg: vmc {
+ regulator-name = "pp3000_vmc";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <60>;
+ };
+
+ mt6366_vmddr_reg: vmddr {
+ regulator-name = "pm0750_emi_vmddr";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <750000>;
+ regulator-enable-ramp-delay = <325>;
+ regulator-always-on;
+ };
+
+ mt6366_vmch_reg: vmch {
+ regulator-name = "pp3000_vmch";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <60>;
+ };
+
+ mt6366_vcn33_reg: vcn33 {
+ regulator-name = "pp3300_vcn33_x";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <270>;
+ };
+
+ vdram2 {
+ regulator-name = "pp0600_emi_vddq";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <600000>;
+ regulator-enable-ramp-delay = <3300>;
+ regulator-always-on;
+ };
+
+ mt6366_vrf12_reg: vrf12 {
+ regulator-name = "pp1200_vrf12_x";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ mt6366_vrf18_reg: vrf18 {
+ regulator-name = "pp1800_vrf18_x";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ vsim1 {
+ regulator-name = "pp1860_vsim1_x";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1860000>;
+ regulator-enable-ramp-delay = <540>;
+ };
+
+ mt6366_vsim2_reg: vsim2 {
+ regulator-name = "pp2760_vsim2_x";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2760000>;
+ regulator-enable-ramp-delay = <540>;
+ };
+
+ mt6366_vsram_gpu_reg: vsram-gpu {
+ regulator-name = "pp0900_dvdd_sram_gpu";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-coupled-with = <&mt6366_vgpu_reg>;
+ regulator-coupled-max-spread = <10000>;
+ };
+
+ mt6366_vsram_others_reg: vsram-others {
+ regulator-name = "pp0900_dvdd_sram_core";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+
+ mt6366_vsram_proc11_reg: vsram-proc11 {
+ regulator-name = "pp0900_dvdd_sram_bc";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+
+ mt6366_vsram_proc12_reg: vsram-proc12 {
+ regulator-name = "pp0900_dvdd_sram_lc";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-ramp-delay = <6250>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+
+ vusb {
+ regulator-name = "pp3070_vusb";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3070000>;
+ regulator-enable-ramp-delay = <270>;
+ regulator-always-on;
+ };
+
+ vxo22 {
+ regulator-name = "pp2240_vxo22";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2240000>;
+ regulator-enable-ramp-delay = <120>;
+ /* Feeds DCXO internally */
+ regulator-always-on;
+ };
+ };
+
+ rtc {
+ compatible = "mediatek,mt6366-rtc", "mediatek,mt6358-rtc";
+ };
+ };
+};
+
+&scp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&scp_pins>;
+ firmware-name = "mediatek/mt8186/scp.img";
+ memory-region = <&scp_mem>;
+ status = "okay";
+
+ cros-ec-rpmsg {
+ compatible = "google,cros-ec-rpmsg";
+ mediatek,rpmsg-name = "cros-ec-rpmsg";
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+
+ cros_ec: ec@0 {
+ compatible = "google,cros-ec-spi";
+ reg = <0>;
+ interrupts-extended = <&pio 13 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ec_ap_int>;
+ spi-max-frequency = <1000000>;
+
+ i2c_tunnel: i2c-tunnel {
+ compatible = "google,cros-ec-i2c-tunnel";
+ google,remote-bus = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ typec {
+ compatible = "google,cros-ec-typec";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_c0: connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ label = "left";
+ power-role = "dual";
+ data-role = "host";
+ try-power-role = "source";
+ };
+
+ usb_c1: connector@1 {
+ compatible = "usb-c-connector";
+ reg = <1>;
+ label = "right";
+ power-role = "dual";
+ data-role = "host";
+ try-power-role = "source";
+ };
+ };
+ };
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins>;
+ cs-gpios = <&pio 45 GPIO_ACTIVE_LOW>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "google,cr50";
+ reg = <0>;
+ interrupts-extended = <&pio 15 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsc_int>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&ssusb0 {
+ status = "okay";
+};
+
+&ssusb1 {
+ status = "okay";
+};
+
+&u3phy0 {
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb_host0 {
+ vbus-supply = <&pp3300_s3>;
+ status = "okay";
+};
+
+&usb_host1 {
+ vbus-supply = <&usb_p1_vbus>;
+ status = "okay";
+};
+
+&watchdog {
+ mediatek,reset-by-toprgu;
+};
+
+#include <arm/cros-ec-keyboard.dtsi>
+#include <arm/cros-ec-sbs.dtsi>
power-domain@MT8186_POWER_DOMAIN_SSUSB {
reg = <MT8186_POWER_DOMAIN_SSUSB>;
+ clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>;
+ clock-names = "sys_ck", "ref_ck";
#power-domain-cells = <0>;
};
power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
reg = <MT8186_POWER_DOMAIN_SSUSB_P1>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>;
+ clock-names = "sys_ck", "ref_ck";
#power-domain-cells = <0>;
};
reg = <MT8186_POWER_DOMAIN_VENC>;
clocks = <&topckgen CLK_TOP_VENC>,
<&vencsys CLK_VENC_CKE1_VENC>;
- clock-names = "venc0", "larb";
+ clock-names = "venc0", "subsys-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
clocks = <&topckgen CLK_TOP_USB_TOP>,
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
- <&infracfg_ao CLK_INFRA_AO_ICUSB>;
- clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ <&infracfg_ao CLK_INFRA_AO_ICUSB>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&u2port0 PHY_TYPE_USB2>;
power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
- <&clk26m>;
- clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ <&clk26m>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
reg = <0x59c 0x4>;
bits = <0 3>;
};
+
+ socinfo-data1@7a0 {
+ reg = <0x7a0 0x4>;
+ };
};
mipi_tx0: dsi-phy@11cc0000 {
power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
};
+ video_decoder: video-decoder@16000000 {
+ compatible = "mediatek,mt8186-vcodec-dec";
+ reg = <0 0x16000000 0 0x1000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>;
+ mediatek,scp = <&scp>;
+
+ vcodec_core: video-codec@16025000 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0 0x16025000 0 0x1000>;
+ interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PP_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_TILE_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD2_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC>,
+ <&vdecsys CLK_VDEC_CKEN>,
+ <&vdecsys CLK_VDEC_LARB1_CKEN>,
+ <&topckgen CLK_TOP_UNIVPLL_D3>;
+ clock-names = "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
+ };
+ };
+
larb4: smi@1602e000 {
compatible = "mediatek,mt8186-smi-larb";
reg = <0 0x1602e000 0 0x1000>;
power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
};
+ venc: video-encoder@17020000 {
+ compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc";
+ reg = <0 0x17020000 0 0x2000>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_REC>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>;
+ clocks = <&vencsys CLK_VENC_CKE1_VENC>;
+ clock-names = "venc_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
+ mediatek,scp = <&scp>;
+ };
+
+ jpgenc: jpeg-encoder@17030000 {
+ compatible = "mediatek,mt8186-jpgenc", "mediatek,mtk-jpgenc";
+ reg = <0 0x17030000 0 0x10000>;
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vencsys CLK_VENC_CKE2_JPGENC>;
+ clock-names = "jpgenc";
+ iommus = <&iommu_mm IOMMU_PORT_L7_JPGENC_Y_RDMA>,
+ <&iommu_mm IOMMU_PORT_L7_JPGENC_C_RDMA>,
+ <&iommu_mm IOMMU_PORT_L7_JPGENC_Q_TABLE>,
+ <&iommu_mm IOMMU_PORT_L7_JPGENC_BSDMA>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
+ };
+
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8186-camsys";
reg = <0 0x1a000000 0 0x1000>;
spi-max-frequency = <3000000>;
pinctrl-names = "default";
pinctrl-0 = <&cros_ec_int>;
+ wakeup-source;
#address-cells = <1>;
#size-cells = <0>;
- base_detection: cbas {
- compatible = "google,cros-cbas";
- };
-
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
- regulator-min-microvolt = <300000>;
+ regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
mt6315_6_vbuck3: vbuck3 {
regulator-compatible = "vbuck3";
regulator-name = "Vlcpu";
- regulator-min-microvolt = <300000>;
+ regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
- regulator-min-microvolt = <606250>;
+ regulator-min-microvolt = <400000>;
regulator-max-microvolt = <800000>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
#address-cells = <1>;
#size-cells = <1>;
+ socinfo-data1@44 {
+ reg = <0x044 0x4>;
+ };
+
+ socinfo-data2@50 {
+ reg = <0x050 0x4>;
+ };
+
lvts_e_data1: data1@1c0 {
reg = <0x1c0 0x58>;
};
reg = <0 0x14001000 0 0x1000>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
<CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
mediatek,scp = <&scp>;
power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC_SET1_VENC>;
- clock-names = "venc-set1";
+ clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
};
&ts_10 {
status = "okay";
};
+
+&watchdog {
+ /delete-property/ mediatek,disable-extrst;
+};
&ts_10 {
status = "okay";
};
+
+&watchdog {
+ /delete-property/ mediatek,disable-extrst;
+};
&ts_10 {
status = "okay";
};
+
+&watchdog {
+ /delete-property/ mediatek,disable-extrst;
+};
status = "okay";
};
+&cpu0 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu1 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu2 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu3 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&mt6315_6_vbuck1>;
+};
+
+&cpu5 {
+ cpu-supply = <&mt6315_6_vbuck1>;
+};
+
+&cpu6 {
+ cpu-supply = <&mt6315_6_vbuck1>;
+};
+
+&cpu7 {
+ cpu-supply = <&mt6315_6_vbuck1>;
+};
+
&dp_intf0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cros_ec_int>;
spi-max-frequency = <3000000>;
+ wakeup-source;
keyboard-backlight {
compatible = "google,cros-kbd-led-backlight";
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
- regulator-min-microvolt = <300000>;
+ regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-ramp-delay = <6250>;
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
- regulator-min-microvolt = <625000>;
+ regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-ramp-delay = <6250>;
status = "okay";
};
+/*
+ * For the USB Type-C ports the role and alternate modes switching is
+ * done by the EC so we set dr_mode to host to avoid interfering.
+ */
+&ssusb0 {
+ dr_mode = "host";
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&ssusb2 {
+ dr_mode = "host";
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&ssusb3 {
+ dr_mode = "host";
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
&xhci0 {
status = "okay";
rx-fifo-depth = <3072>;
- vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&usb_vbus>;
};
&xhci2 {
status = "okay";
-
- vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&usb_vbus>;
};
/* MT7921's USB Bluetooth has issues with USB2 LPM */
usb2-lpm-disable;
- vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&usb_vbus>;
};
status = "okay";
};
-&xhci0 {
+&ssusb0 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&ssusb2 {
vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&ssusb3 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&xhci0 {
vbus-supply = <&otg_vbus_regulator>;
status = "okay";
};
};
&xhci2 {
- vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
&xhci3 {
- vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
status = "okay";
};
+&ssusb0 {
+ status = "okay";
+};
+
+&ssusb2 {
+ status = "okay";
+};
+
+&ssusb3 {
+ status = "okay";
+};
+
&xhci0 {
status = "okay";
};
};
};
- xhci0: usb@11200000 {
- compatible = "mediatek,mt8195-xhci",
- "mediatek,mtk-xhci";
- reg = <0 0x11200000 0 0x1000>,
- <0 0x11203e00 0 0x0100>;
+ ssusb0: usb@11201000 {
+ compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
- phys = <&u2port0 PHY_TYPE_USB2>,
- <&u3port0 PHY_TYPE_USB3>;
- assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
- <&topckgen CLK_TOP_SSUSB_XHCI>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
- <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ ranges = <0 0 0 0x11200000 0 0x3f00>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
<&topckgen CLK_TOP_SSUSB_REF>,
- <&apmixedsys CLK_APMIXED_USB1PLL>,
- <&clk26m>,
<&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
- clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
- "xhci_ck";
- mediatek,syscon-wakeup = <&pericfg 0x400 103>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x400 103>;
status = "disabled";
+
+ xhci0: usb@0 {
+ compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
+ reg = <0 0 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&topckgen CLK_TOP_SSUSB_XHCI>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
+ <&topckgen CLK_TOP_SSUSB_REF>,
+ <&apmixedsys CLK_APMIXED_USB1PLL>,
+ <&clk26m>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ status = "disabled";
+ };
};
mmc0: mmc@11230000 {
status = "disabled";
};
- xhci2: usb@112a0000 {
- compatible = "mediatek,mt8195-xhci",
- "mediatek,mtk-xhci";
- reg = <0 0x112a0000 0 0x1000>,
- <0 0x112a3e00 0 0x0100>;
+ ssusb2: usb@112a1000 {
+ compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
+ reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>;
reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
- phys = <&u2port2 PHY_TYPE_USB2>;
- assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
- <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
- <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ ranges = <0 0 0 0x112a0000 0 0x3f00>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
<&topckgen CLK_TOP_SSUSB_P2_REF>,
- <&clk26m>,
- <&clk26m>,
<&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
- clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
- "xhci_ck";
- mediatek,syscon-wakeup = <&pericfg 0x400 105>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ phys = <&u2port2 PHY_TYPE_USB2>;
wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x400 105>;
status = "disabled";
+
+ xhci2: usb@0 {
+ compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
+ reg = <0 0 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
+ clock-names = "sys_ck";
+ status = "disabled";
+ };
};
- xhci3: usb@112b0000 {
- compatible = "mediatek,mt8195-xhci",
- "mediatek,mtk-xhci";
- reg = <0 0x112b0000 0 0x1000>,
- <0 0x112b3e00 0 0x0100>;
+ ssusb3: usb@112b1000 {
+ compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
+ reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>;
reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
- phys = <&u2port3 PHY_TYPE_USB2>;
- assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
- <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
- <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ ranges = <0 0 0 0x112b0000 0 0x3f00>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
<&topckgen CLK_TOP_SSUSB_P3_REF>,
- <&clk26m>,
- <&clk26m>,
<&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
- clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
- "xhci_ck";
- mediatek,syscon-wakeup = <&pericfg 0x400 106>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ phys = <&u2port3 PHY_TYPE_USB2>;
wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x400 106>;
status = "disabled";
+
+ xhci3: usb@0 {
+ compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
+ reg = <0 0 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
+ clock-names = "sys_ck";
+ status = "disabled";
+ };
};
pcie0: pcie@112f0000 {
svs_calib_data: svs-calib@580 {
reg = <0x580 0x64>;
};
+ socinfo-data1@7a0 {
+ reg = <0x7a0 0x4>;
+ };
};
u3phy2: t-phy@11c40000 {
compatible = "mediatek,mt8195-vppsys0", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
};
dma-controller@14001000 {
compatible = "mediatek,mt8195-vppsys1", "syscon";
reg = <0 0x14f00000 0 0x1000>;
#clock-cells = <1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
};
mutex@14f01000 {
reg = <0 0x1c01a000 0 0x1000>;
mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
};
interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
};
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
clock-names = "vdo1_mutex";
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
};
status = "disabled";
};
+&ssusb0 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&ssusb2 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&ssusb3 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
&xhci0 {
status = "okay";
};
};
&xhci2 {
- vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
&xhci3 {
- vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Radxa Limited
+ * Copyright (C) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include "mt8195.dtsi"
+#include "mt6359.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
+#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/usb/pd.h>
+
+/ {
+ model = "Radxa NIO 12L";
+ chassis-type = "embedded";
+ compatible = "radxa,nio-12l", "mediatek,mt8395", "mediatek,mt8195";
+
+ aliases {
+ i2c0 = &i2c2;
+ i2c1 = &i2c3;
+ i2c2 = &i2c4;
+ i2c3 = &i2c0;
+ i2c4 = &i2c1;
+ ethernet0 = ð
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi1;
+ spi1 = &spi2;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0x1 0x0>;
+ };
+
+ wifi_vreg: regulator-wifi-3v3-en {
+ compatible = "regulator-fixed";
+ regulator-name = "wifi_3v3_en";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 67 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_vreg_pins>;
+ vin-supply = <&vsys>;
+ };
+
+ /* system wide switching 5.0V power rail */
+ vsys: regulator-vsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_vsys>;
+ };
+
+ vsys_buck: regulator-vsys-buck {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_buck";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_vsys>;
+ };
+
+ /* Rail from power-only "TYPE C DC" port */
+ vcc5v0_vsys: regulator-vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ reg = <0 0x43200000 0 0xc00000>;
+ no-map;
+ };
+
+ scp_mem: memory@50000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x50000000 0 0x2900000>;
+ no-map;
+ };
+
+ vpu_mem: memory@53000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
+ };
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_mem: memory@54600000 {
+ reg = <0 0x54600000 0x0 0x200000>;
+ no-map;
+ };
+
+ afe_mem: memory@60000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x60000000 0 0x1100000>;
+ no-map;
+ };
+
+ apu_mem: memory@62000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
+ };
+ };
+};
+
+ð {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&rgmii_phy>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <ð_default_pins>;
+ pinctrl-1 = <ð_sleep_pins>;
+ mediatek,tx-delay-ps = <2030>;
+ mediatek,mac-wol;
+ snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
+ snps,reset-delays-us = <0 20000 100000>;
+ status = "okay";
+
+ mdio {
+ rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x1>;
+ };
+ };
+};
+
+&gpu {
+ mali-supply = <&mt6315_7_vbuck1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ typec-mux@48 {
+ compatible = "ite,it5205";
+ reg = <0x48>;
+
+ mode-switch;
+ orientation-switch;
+
+ vcc-supply = <&mt6359_vibr_ldo_reg>;
+
+ port {
+ it5205_sbu_mux: endpoint {
+ remote-endpoint = <&typec_con_mux>;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* I2C4 exposed at 39-pins MIPI-LCD connector */
+};
+
+&i2c6 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c6_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mt6360: pmic@34 {
+ compatible = "mediatek,mt6360";
+ reg = <0x34>;
+ interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "IRQB";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ pinctrl-0 = <&mt6360_pins>;
+
+ charger {
+ compatible = "mediatek,mt6360-chg";
+ richtek,vinovp-microvolt = <14500000>;
+
+ otg_vbus_regulator: usb-otg-vbus-regulator {
+ regulator-name = "usb-otg-vbus";
+ regulator-min-microvolt = <4425000>;
+ regulator-max-microvolt = <5825000>;
+ };
+ };
+
+ regulator {
+ compatible = "mediatek,mt6360-regulator";
+ LDO_VIN1-supply = <&vsys_buck>;
+ LDO_VIN3-supply = <&mt6360_buck2>;
+
+ mt6360_buck1: buck1 {
+ regulator-name = "emi_vdd2";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP
+ MT6360_OPMODE_ULP>;
+ regulator-always-on;
+ };
+
+ mt6360_buck2: buck2 {
+ regulator-name = "emi_vddq";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP
+ MT6360_OPMODE_ULP>;
+ regulator-always-on;
+ };
+
+ mt6360_ldo1: ldo1 {
+ regulator-name = "ext_lcd_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ regulator-always-on;
+ };
+
+ mt6360_ldo2: ldo2 {
+ regulator-name = "panel1_p1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo3: ldo3 {
+ regulator-name = "vmc_pmu";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo5: ldo5 {
+ regulator-name = "vmch_pmu";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ regulator-always-on;
+ };
+
+ mt6360_ldo6: ldo6 {
+ regulator-name = "mt6360_ldo6"; /* Test point */
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2100000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo7: ldo7 {
+ regulator-name = "emi_vmddr_en";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2100000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ regulator-always-on;
+ };
+ };
+
+ typec {
+ compatible = "mediatek,mt6360-tcpc";
+ interrupts-extended = <&pio 100 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "PD_IRQB";
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ op-sink-microwatt = <10000000>;
+ power-role = "dual";
+ try-power-role = "sink";
+
+ source-pdos = <PDO_FIXED(5000, 1000,
+ PDO_FIXED_DUAL_ROLE |
+ PDO_FIXED_DATA_SWAP)>;
+ sink-pdos = <PDO_FIXED(5000, 3000,
+ PDO_FIXED_DUAL_ROLE |
+ PDO_FIXED_DATA_SWAP)>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ typec_con_hs: endpoint {
+ remote-endpoint = <&mtu3_hs0_role_sw>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ typec_con_mux: endpoint {
+ remote-endpoint = <&it5205_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+ };
+};
+
+/* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */
+&mmc0 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_default_pins>;
+ pinctrl-1 = <&mmc0_uhs_pins>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ hs400-ds-delay = <0x14c11>;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ no-sdio;
+ no-sd;
+ non-removable;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ status = "okay";
+};
+
+/* MMC1 Controller: MicroSD card slot */
+&mmc1 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc1_default_pins>, <&mmc1_pins_detect>;
+ pinctrl-1 = <&mmc1_default_pins>;
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-sd-highspeed;
+ cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
+ no-mmc;
+ no-sdio;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&mt6360_ldo5>;
+ vqmmc-supply = <&mt6360_ldo3>;
+ status = "okay";
+};
+
+&mt6359_vaud18_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vbbck_ldo_reg {
+ regulator-always-on;
+};
+
+/* For USB Hub */
+&mt6359_vcamio_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vcn33_2_bt_ldo_reg {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+};
+
+&mt6359_vcore_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vgpu11_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vproc1_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vproc2_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vpu_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vrf12_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vsram_md_ldo_reg {
+ regulator-always-on;
+};
+
+/* for GPU SRAM */
+&mt6359_vsram_others_ldo_reg {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+};
+
+&pio {
+ eth_default_pins: eth-default-pins {
+ pins-cc {
+ pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
+ <PINMUX_GPIO86__FUNC_GBE_RXC>,
+ <PINMUX_GPIO87__FUNC_GBE_RXDV>,
+ <PINMUX_GPIO88__FUNC_GBE_TXEN>;
+ drive-strength = <8>;
+ };
+
+ pins-mdio {
+ pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
+ <PINMUX_GPIO90__FUNC_GBE_MDIO>;
+ input-enable;
+ };
+
+ pins-power {
+ pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+ <PINMUX_GPIO92__FUNC_GPIO92>;
+ output-high;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
+ };
+
+ pins-rxd {
+ pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
+ <PINMUX_GPIO82__FUNC_GBE_RXD2>,
+ <PINMUX_GPIO83__FUNC_GBE_RXD1>,
+ <PINMUX_GPIO84__FUNC_GBE_RXD0>;
+ };
+
+ pins-txd {
+ pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
+ <PINMUX_GPIO78__FUNC_GBE_TXD2>,
+ <PINMUX_GPIO79__FUNC_GBE_TXD1>,
+ <PINMUX_GPIO80__FUNC_GBE_TXD0>;
+ drive-strength = <8>;
+ };
+ };
+
+ eth_sleep_pins: eth-sleep-pins {
+ pins-cc {
+ pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
+ <PINMUX_GPIO86__FUNC_GPIO86>,
+ <PINMUX_GPIO87__FUNC_GPIO87>,
+ <PINMUX_GPIO88__FUNC_GPIO88>;
+ };
+
+ pins-mdio {
+ pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
+ <PINMUX_GPIO90__FUNC_GPIO90>;
+ bias-disable;
+ input-disable;
+ };
+
+ pins-rxd {
+ pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
+ <PINMUX_GPIO82__FUNC_GPIO82>,
+ <PINMUX_GPIO83__FUNC_GPIO83>,
+ <PINMUX_GPIO84__FUNC_GPIO84>;
+ };
+
+ pins-txd {
+ pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
+ <PINMUX_GPIO78__FUNC_GPIO78>,
+ <PINMUX_GPIO79__FUNC_GPIO79>,
+ <PINMUX_GPIO80__FUNC_GPIO80>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
+ <PINMUX_GPIO13__FUNC_SCL2>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_111>;
+ drive-strength = <6>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
+ <PINMUX_GPIO17__FUNC_SCL4>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_111>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c6_pins: i2c6-pins {
+ pins {
+ pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
+ <PINMUX_GPIO26__FUNC_SCL6>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_111>;
+ };
+ };
+
+ mmc0_default_pins: mmc0-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ drive-strength = <6>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ drive-strength = <6>;
+ input-enable;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ drive-strength = <6>;
+ };
+ };
+
+ mmc0_uhs_pins: mmc0-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ drive-strength = <8>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ drive-strength = <8>;
+ input-enable;
+ };
+
+ pins-ds {
+ pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ drive-strength = <8>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ drive-strength = <8>;
+ };
+ };
+
+ mmc1_default_pins: mmc1-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ drive-strength = <8>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
+ <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ mmc1_pins_detect: mmc1-detect-pins {
+ pins-insert {
+ pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
+ bias-pull-up;
+ };
+ };
+
+ mt6360_pins: mt6360-pins {
+ pins-irq {
+ pinmux = <PINMUX_GPIO100__FUNC_GPIO100>,
+ <PINMUX_GPIO101__FUNC_GPIO101>;
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_default_pins: pcie0-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
+ <PINMUX_GPIO20__FUNC_PERSTN>,
+ <PINMUX_GPIO21__FUNC_CLKREQN>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default_pins: pcie1-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO0__FUNC_PERSTN_1>,
+ <PINMUX_GPIO1__FUNC_CLKREQN_1>,
+ <PINMUX_GPIO2__FUNC_WAKEN_1>;
+ bias-disable;
+ };
+ };
+
+ spi1_pins: spi1-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>,
+ <PINMUX_GPIO137__FUNC_SPIM1_CLK>,
+ <PINMUX_GPIO138__FUNC_SPIM1_MO>,
+ <PINMUX_GPIO139__FUNC_SPIM1_MI>;
+ bias-disable;
+ };
+ };
+
+ spi2_pins: spi2-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>,
+ <PINMUX_GPIO141__FUNC_SPIM2_CLK>,
+ <PINMUX_GPIO142__FUNC_SPIM2_MO>,
+ <PINMUX_GPIO143__FUNC_SPIM2_MI>;
+ bias-disable;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
+ <PINMUX_GPIO99__FUNC_URXD0>;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
+ <PINMUX_GPIO103__FUNC_URXD1>;
+ };
+ };
+
+ wifi_vreg_pins: wifi-vreg-pins {
+ pins-wifi-pmu-en {
+ pinmux = <PINMUX_GPIO65__FUNC_GPIO65>;
+ output-high;
+ };
+
+ pins-wifi-vreg-en {
+ pinmux = <PINMUX_GPIO67__FUNC_GPIO67>;
+ };
+ };
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_pins>;
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_pins>;
+ status = "okay";
+};
+
+&pmic {
+ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&scp {
+ memory-region = <&scp_mem>;
+ status = "okay";
+};
+
+&spi1 {
+ /* Exposed at 40 pin connector */
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+ mediatek,pad-select = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+};
+
+&spi2 {
+ /* Exposed at 40 pin connector */
+ pinctrl-0 = <&spi2_pins>;
+ pinctrl-names = "default";
+ mediatek,pad-select = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+};
+
+&spmi {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ mt6315_6: pmic@6 {
+ compatible = "mediatek,mt6315-regulator";
+ reg = <0x6 SPMI_USID>;
+
+ regulators {
+ mt6315_6_vbuck1: vbuck1 {
+ regulator-compatible = "vbuck1";
+ regulator-name = "Vbcpu";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ mt6315_7: pmic@7 {
+ compatible = "mediatek,mt6315-regulator";
+ reg = <0x7 SPMI_USID>;
+
+ regulators {
+ mt6315_7_vbuck1: vbuck1 {
+ regulator-compatible = "vbuck1";
+ regulator-name = "Vgpu";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ };
+ };
+};
+
+&uart0 {
+ /* Exposed at 40 pin connector */
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ /* Exposed at 40 pin connector */
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&ssusb0 {
+ role-switch-default-mode = "host";
+ usb-role-switch;
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+
+ port {
+ mtu3_hs0_role_sw: endpoint {
+ remote-endpoint = <&typec_con_hs>;
+ };
+ };
+};
+
+&ssusb2 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&xhci0 {
+ vbus-supply = <&otg_vbus_regulator>;
+ status = "okay";
+};
+
+&xhci1 {
+ /* MT7921's USB Bluetooth has issues with USB2 LPM */
+ usb2-lpm-disable;
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ vbus-supply = <&vsys>;
+ status = "okay";
+};
+
+&xhci2 {
+ vbus-supply = <&vsys>;
+ status = "okay";
+};
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
reg = <0>;
+ wakeup-source;
google,cros-ec-spi-msg-delay = <2000>;
status = "okay";
};
+ i2c@c240000 {
+ status = "okay";
+
+ power-sensor@40 {
+ compatible = "ti,ina3221";
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ reg = <0x0>;
+ label = "GPU";
+ shunt-resistor-micro-ohms = <5000>;
+ };
+ input@1 {
+ reg = <0x1>;
+ label = "CPU";
+ shunt-resistor-micro-ohms = <5000>;
+ };
+ input@2 {
+ reg = <0x2>;
+ label = "SOC";
+ shunt-resistor-micro-ohms = <5000>;
+ };
+ };
+
+ power-sensor@41 {
+ compatible = "ti,ina3221";
+ reg = <0x41>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ reg = <0x0>;
+ label = "CV";
+ shunt-resistor-micro-ohms = <5000>;
+ };
+ input@1 {
+ reg = <0x1>;
+ label = "VDDRQ";
+ shunt-resistor-micro-ohms = <5000>;
+ };
+ input@2 {
+ reg = <0x2>;
+ label = "SYS5V";
+ shunt-resistor-micro-ohms = <5000>;
+ };
+ };
+ };
+
serial@3110000 {
status = "okay";
};
ports {
usb2-0 {
- mode = "host";
+ mode = "otg";
+ usb-role-switch;
status = "okay";
+
+ port {
+ hs_typec_p0: endpoint {
+ remote-endpoint = <&hs_ucsi_ccg_p0>;
+ };
+ };
};
usb2-1 {
};
};
+ usb@3550000 {
+ status = "okay";
+
+ phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+ <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
+ phy-names = "usb2-0", "usb3-0";
+ };
+
usb@3610000 {
status = "okay";
phy-names = "usb2-0", "usb2-1", "usb2-3", "usb3-0", "usb3-2", "usb3-3";
};
+ i2c@c240000 {
+ typec@8 {
+ compatible = "cypress,cypd4226";
+ reg = <0x08>;
+ interrupt-parent = <&gpio_aon>;
+ interrupts = <TEGRA194_AON_GPIO(BB, 2) IRQ_TYPE_LEVEL_LOW>;
+ firmware-name = "nvidia,jetson-agx-xavier";
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ccg_typec_con0: connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ label = "USB-C";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hs_ucsi_ccg_p0: endpoint {
+ remote-endpoint = <&hs_typec_p0>;
+ };
+ };
+ };
+ };
+ };
+ };
+
i2c@c250000 {
status = "okay";
status = "okay";
};
+ i2c@c250000 {
+ status = "okay";
+
+ power-sensor@40 {
+ compatible = "ti,ina3221";
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ reg = <0x0>;
+ label = "VDD_IN";
+ shunt-resistor-micro-ohms = <5000>;
+ };
+ input@1 {
+ reg = <0x1>;
+ label = "VDD_CPU_GPU_CV";
+ shunt-resistor-micro-ohms = <5000>;
+ };
+ input@2 {
+ reg = <0x2>;
+ label = "VDD_SOC";
+ shunt-resistor-micro-ohms = <5000>;
+ };
+ };
+ };
+
serial@3100000 {
status = "okay";
};
/ {
compatible = "nvidia,p3701", "nvidia,tegra234";
+ aliases {
+ mmc0 = "/bus@0/mmc@3460000";
+ mmc1 = "/bus@0/mmc@3400000";
+ };
+
bus@0 {
aconnect@2900000 {
status = "okay";
i2s@2901000 {
status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- i2s1_cif: endpoint {
- remote-endpoint = <&xbar_i2s1>;
- };
- };
-
- i2s1_port: port@1 {
- reg = <1>;
-
- i2s1_dap: endpoint {
- dai-format = "i2s";
- /* placeholder for external codec */
- };
- };
- };
};
i2s@2901100 {
status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- i2s2_cif: endpoint {
- remote-endpoint = <&xbar_i2s2>;
- };
- };
-
- i2s2_port: port@1 {
- reg = <1>;
-
- i2s2_dap: endpoint {
- dai-format = "i2s";
- /* placeholder for external codec */
- };
- };
- };
};
i2s@2901300 {
status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- i2s4_cif: endpoint {
- remote-endpoint = <&xbar_i2s4>;
- };
- };
-
- i2s4_port: port@1 {
- reg = <1>;
-
- i2s4_dap: endpoint {
- dai-format = "i2s";
- /* placeholder for external codec */
- };
- };
- };
};
i2s@2901500 {
status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- i2s6_cif: endpoint {
- remote-endpoint = <&xbar_i2s6>;
- };
- };
-
- i2s6_port: port@1 {
- reg = <1>;
-
- i2s6_dap: endpoint {
- dai-format = "i2s";
- /* placeholder for external codec */
- };
- };
- };
- };
-
- sfc@2902000 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sfc1_cif_in: endpoint {
- remote-endpoint = <&xbar_sfc1_in>;
- };
- };
-
- sfc1_out_port: port@1 {
- reg = <1>;
-
- sfc1_cif_out: endpoint {
- remote-endpoint = <&xbar_sfc1_out>;
- };
- };
- };
- };
-
- sfc@2902200 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sfc2_cif_in: endpoint {
- remote-endpoint = <&xbar_sfc2_in>;
- };
- };
-
- sfc2_out_port: port@1 {
- reg = <1>;
-
- sfc2_cif_out: endpoint {
- remote-endpoint = <&xbar_sfc2_out>;
- };
- };
- };
- };
-
- sfc@2902400 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sfc3_cif_in: endpoint {
- remote-endpoint = <&xbar_sfc3_in>;
- };
- };
-
- sfc3_out_port: port@1 {
- reg = <1>;
-
- sfc3_cif_out: endpoint {
- remote-endpoint = <&xbar_sfc3_out>;
- };
- };
- };
- };
-
- sfc@2902600 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sfc4_cif_in: endpoint {
- remote-endpoint = <&xbar_sfc4_in>;
- };
- };
-
- sfc4_out_port: port@1 {
- reg = <1>;
-
- sfc4_cif_out: endpoint {
- remote-endpoint = <&xbar_sfc4_out>;
- };
- };
- };
- };
-
- amx@2903000 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- amx1_in1: endpoint {
- remote-endpoint = <&xbar_amx1_in1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- amx1_in2: endpoint {
- remote-endpoint = <&xbar_amx1_in2>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- amx1_in3: endpoint {
- remote-endpoint = <&xbar_amx1_in3>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- amx1_in4: endpoint {
- remote-endpoint = <&xbar_amx1_in4>;
- };
- };
-
- amx1_out_port: port@4 {
- reg = <4>;
-
- amx1_out: endpoint {
- remote-endpoint = <&xbar_amx1_out>;
- };
- };
- };
- };
-
- amx@2903100 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- amx2_in1: endpoint {
- remote-endpoint = <&xbar_amx2_in1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- amx2_in2: endpoint {
- remote-endpoint = <&xbar_amx2_in2>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- amx2_in3: endpoint {
- remote-endpoint = <&xbar_amx2_in3>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- amx2_in4: endpoint {
- remote-endpoint = <&xbar_amx2_in4>;
- };
- };
-
- amx2_out_port: port@4 {
- reg = <4>;
-
- amx2_out: endpoint {
- remote-endpoint = <&xbar_amx2_out>;
- };
- };
- };
- };
-
- amx@2903200 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- amx3_in1: endpoint {
- remote-endpoint = <&xbar_amx3_in1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- amx3_in2: endpoint {
- remote-endpoint = <&xbar_amx3_in2>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- amx3_in3: endpoint {
- remote-endpoint = <&xbar_amx3_in3>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- amx3_in4: endpoint {
- remote-endpoint = <&xbar_amx3_in4>;
- };
- };
-
- amx3_out_port: port@4 {
- reg = <4>;
-
- amx3_out: endpoint {
- remote-endpoint = <&xbar_amx3_out>;
- };
- };
- };
- };
-
- amx@2903300 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- amx4_in1: endpoint {
- remote-endpoint = <&xbar_amx4_in1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- amx4_in2: endpoint {
- remote-endpoint = <&xbar_amx4_in2>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- amx4_in3: endpoint {
- remote-endpoint = <&xbar_amx4_in3>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- amx4_in4: endpoint {
- remote-endpoint = <&xbar_amx4_in4>;
- };
- };
-
- amx4_out_port: port@4 {
- reg = <4>;
-
- amx4_out: endpoint {
- remote-endpoint = <&xbar_amx4_out>;
- };
- };
- };
- };
-
- adx@2903800 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- adx1_in: endpoint {
- remote-endpoint = <&xbar_adx1_in>;
- };
- };
-
- adx1_out1_port: port@1 {
- reg = <1>;
-
- adx1_out1: endpoint {
- remote-endpoint = <&xbar_adx1_out1>;
- };
- };
-
- adx1_out2_port: port@2 {
- reg = <2>;
-
- adx1_out2: endpoint {
- remote-endpoint = <&xbar_adx1_out2>;
- };
- };
-
- adx1_out3_port: port@3 {
- reg = <3>;
-
- adx1_out3: endpoint {
- remote-endpoint = <&xbar_adx1_out3>;
- };
- };
-
- adx1_out4_port: port@4 {
- reg = <4>;
-
- adx1_out4: endpoint {
- remote-endpoint = <&xbar_adx1_out4>;
- };
- };
- };
- };
-
- adx@2903900 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- adx2_in: endpoint {
- remote-endpoint = <&xbar_adx2_in>;
- };
- };
-
- adx2_out1_port: port@1 {
- reg = <1>;
-
- adx2_out1: endpoint {
- remote-endpoint = <&xbar_adx2_out1>;
- };
- };
-
- adx2_out2_port: port@2 {
- reg = <2>;
-
- adx2_out2: endpoint {
- remote-endpoint = <&xbar_adx2_out2>;
- };
- };
-
- adx2_out3_port: port@3 {
- reg = <3>;
-
- adx2_out3: endpoint {
- remote-endpoint = <&xbar_adx2_out3>;
- };
- };
-
- adx2_out4_port: port@4 {
- reg = <4>;
-
- adx2_out4: endpoint {
- remote-endpoint = <&xbar_adx2_out4>;
- };
- };
- };
- };
-
- adx@2903a00 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- adx3_in: endpoint {
- remote-endpoint = <&xbar_adx3_in>;
- };
- };
-
- adx3_out1_port: port@1 {
- reg = <1>;
-
- adx3_out1: endpoint {
- remote-endpoint = <&xbar_adx3_out1>;
- };
- };
-
- adx3_out2_port: port@2 {
- reg = <2>;
-
- adx3_out2: endpoint {
- remote-endpoint = <&xbar_adx3_out2>;
- };
- };
-
- adx3_out3_port: port@3 {
- reg = <3>;
-
- adx3_out3: endpoint {
- remote-endpoint = <&xbar_adx3_out3>;
- };
- };
-
- adx3_out4_port: port@4 {
- reg = <4>;
-
- adx3_out4: endpoint {
- remote-endpoint = <&xbar_adx3_out4>;
- };
- };
- };
- };
-
- adx@2903b00 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- adx4_in: endpoint {
- remote-endpoint = <&xbar_adx4_in>;
- };
- };
-
- adx4_out1_port: port@1 {
- reg = <1>;
-
- adx4_out1: endpoint {
- remote-endpoint = <&xbar_adx4_out1>;
- };
- };
-
- adx4_out2_port: port@2 {
- reg = <2>;
-
- adx4_out2: endpoint {
- remote-endpoint = <&xbar_adx4_out2>;
- };
- };
-
- adx4_out3_port: port@3 {
- reg = <3>;
-
- adx4_out3: endpoint {
- remote-endpoint = <&xbar_adx4_out3>;
- };
- };
-
- adx4_out4_port: port@4 {
- reg = <4>;
-
- adx4_out4: endpoint {
- remote-endpoint = <&xbar_adx4_out4>;
- };
- };
- };
};
dmic@2904200 {
status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- dmic3_cif: endpoint {
- remote-endpoint = <&xbar_dmic3>;
- };
- };
-
- dmic3_port: port@1 {
- reg = <1>;
-
- dmic3_dap: endpoint {
- /* placeholder for external codec */
- };
- };
- };
- };
-
- processing-engine@2908000 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0x0>;
-
- ope1_cif_in_ep: endpoint {
- remote-endpoint = <&xbar_ope1_in_ep>;
- };
- };
-
- ope1_out_port: port@1 {
- reg = <0x1>;
-
- ope1_cif_out_ep: endpoint {
- remote-endpoint = <&xbar_ope1_out_ep>;
- };
- };
- };
- };
-
- mvc@290a000 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- mvc1_cif_in: endpoint {
- remote-endpoint = <&xbar_mvc1_in>;
- };
- };
-
- mvc1_out_port: port@1 {
- reg = <1>;
-
- mvc1_cif_out: endpoint {
- remote-endpoint = <&xbar_mvc1_out>;
- };
- };
- };
- };
-
- mvc@290a200 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- mvc2_cif_in: endpoint {
- remote-endpoint = <&xbar_mvc2_in>;
- };
- };
-
- mvc2_out_port: port@1 {
- reg = <1>;
-
- mvc2_cif_out: endpoint {
- remote-endpoint = <&xbar_mvc2_out>;
- };
- };
- };
- };
-
- amixer@290bb00 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0x0>;
-
- mix_in1: endpoint {
- remote-endpoint = <&xbar_mix_in1>;
- };
- };
-
- port@1 {
- reg = <0x1>;
-
- mix_in2: endpoint {
- remote-endpoint = <&xbar_mix_in2>;
- };
- };
-
- port@2 {
- reg = <0x2>;
-
- mix_in3: endpoint {
- remote-endpoint = <&xbar_mix_in3>;
- };
- };
-
- port@3 {
- reg = <0x3>;
-
- mix_in4: endpoint {
- remote-endpoint = <&xbar_mix_in4>;
- };
- };
-
- port@4 {
- reg = <0x4>;
-
- mix_in5: endpoint {
- remote-endpoint = <&xbar_mix_in5>;
- };
- };
-
- port@5 {
- reg = <0x5>;
-
- mix_in6: endpoint {
- remote-endpoint = <&xbar_mix_in6>;
- };
- };
-
- port@6 {
- reg = <0x6>;
-
- mix_in7: endpoint {
- remote-endpoint = <&xbar_mix_in7>;
- };
- };
-
- port@7 {
- reg = <0x7>;
-
- mix_in8: endpoint {
- remote-endpoint = <&xbar_mix_in8>;
- };
- };
-
- port@8 {
- reg = <0x8>;
-
- mix_in9: endpoint {
- remote-endpoint = <&xbar_mix_in9>;
- };
- };
-
- port@9 {
- reg = <0x9>;
-
- mix_in10: endpoint {
- remote-endpoint = <&xbar_mix_in10>;
- };
- };
-
- mix_out1_port: port@a {
- reg = <0xa>;
-
- mix_out1: endpoint {
- remote-endpoint = <&xbar_mix_out1>;
- };
- };
-
- mix_out2_port: port@b {
- reg = <0xb>;
-
- mix_out2: endpoint {
- remote-endpoint = <&xbar_mix_out2>;
- };
- };
-
- mix_out3_port: port@c {
- reg = <0xc>;
-
- mix_out3: endpoint {
- remote-endpoint = <&xbar_mix_out3>;
- };
- };
-
- mix_out4_port: port@d {
- reg = <0xd>;
-
- mix_out4: endpoint {
- remote-endpoint = <&xbar_mix_out4>;
- };
- };
-
- mix_out5_port: port@e {
- reg = <0xe>;
-
- mix_out5: endpoint {
- remote-endpoint = <&xbar_mix_out5>;
- };
- };
- };
- };
-
- admaif@290f000 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- admaif0_port: port@0 {
- reg = <0x0>;
-
- admaif0: endpoint {
- remote-endpoint = <&xbar_admaif0>;
- };
- };
-
- admaif1_port: port@1 {
- reg = <0x1>;
-
- admaif1: endpoint {
- remote-endpoint = <&xbar_admaif1>;
- };
- };
-
- admaif2_port: port@2 {
- reg = <0x2>;
-
- admaif2: endpoint {
- remote-endpoint = <&xbar_admaif2>;
- };
- };
-
- admaif3_port: port@3 {
- reg = <0x3>;
-
- admaif3: endpoint {
- remote-endpoint = <&xbar_admaif3>;
- };
- };
-
- admaif4_port: port@4 {
- reg = <0x4>;
-
- admaif4: endpoint {
- remote-endpoint = <&xbar_admaif4>;
- };
- };
-
- admaif5_port: port@5 {
- reg = <0x5>;
-
- admaif5: endpoint {
- remote-endpoint = <&xbar_admaif5>;
- };
- };
-
- admaif6_port: port@6 {
- reg = <0x6>;
-
- admaif6: endpoint {
- remote-endpoint = <&xbar_admaif6>;
- };
- };
-
- admaif7_port: port@7 {
- reg = <0x7>;
-
- admaif7: endpoint {
- remote-endpoint = <&xbar_admaif7>;
- };
- };
-
- admaif8_port: port@8 {
- reg = <0x8>;
-
- admaif8: endpoint {
- remote-endpoint = <&xbar_admaif8>;
- };
- };
-
- admaif9_port: port@9 {
- reg = <0x9>;
-
- admaif9: endpoint {
- remote-endpoint = <&xbar_admaif9>;
- };
- };
-
- admaif10_port: port@a {
- reg = <0xa>;
-
- admaif10: endpoint {
- remote-endpoint = <&xbar_admaif10>;
- };
- };
-
- admaif11_port: port@b {
- reg = <0xb>;
-
- admaif11: endpoint {
- remote-endpoint = <&xbar_admaif11>;
- };
- };
-
- admaif12_port: port@c {
- reg = <0xc>;
-
- admaif12: endpoint {
- remote-endpoint = <&xbar_admaif12>;
- };
- };
-
- admaif13_port: port@d {
- reg = <0xd>;
-
- admaif13: endpoint {
- remote-endpoint = <&xbar_admaif13>;
- };
- };
-
- admaif14_port: port@e {
- reg = <0xe>;
-
- admaif14: endpoint {
- remote-endpoint = <&xbar_admaif14>;
- };
- };
-
- admaif15_port: port@f {
- reg = <0xf>;
-
- admaif15: endpoint {
- remote-endpoint = <&xbar_admaif15>;
- };
- };
-
- admaif16_port: port@10 {
- reg = <0x10>;
-
- admaif16: endpoint {
- remote-endpoint = <&xbar_admaif16>;
- };
- };
-
- admaif17_port: port@11 {
- reg = <0x11>;
-
- admaif17: endpoint {
- remote-endpoint = <&xbar_admaif17>;
- };
- };
-
- admaif18_port: port@12 {
- reg = <0x12>;
-
- admaif18: endpoint {
- remote-endpoint = <&xbar_admaif18>;
- };
- };
-
- admaif19_port: port@13 {
- reg = <0x13>;
-
- admaif19: endpoint {
- remote-endpoint = <&xbar_admaif19>;
- };
- };
- };
- };
-
- asrc@2910000 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0x0>;
-
- asrc_in1_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in1_ep>;
- };
- };
-
- port@1 {
- reg = <0x1>;
-
- asrc_in2_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in2_ep>;
- };
- };
-
- port@2 {
- reg = <0x2>;
-
- asrc_in3_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in3_ep>;
- };
- };
-
- port@3 {
- reg = <0x3>;
-
- asrc_in4_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in4_ep>;
- };
- };
-
- port@4 {
- reg = <0x4>;
-
- asrc_in5_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in5_ep>;
- };
- };
-
- port@5 {
- reg = <0x5>;
-
- asrc_in6_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in6_ep>;
- };
- };
-
- port@6 {
- reg = <0x6>;
-
- asrc_in7_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in7_ep>;
- };
- };
-
- asrc_out1_port: port@7 {
- reg = <0x7>;
-
- asrc_out1_ep: endpoint {
- remote-endpoint = <&xbar_asrc_out1_ep>;
- };
- };
-
- asrc_out2_port: port@8 {
- reg = <0x8>;
-
- asrc_out2_ep: endpoint {
- remote-endpoint = <&xbar_asrc_out2_ep>;
- };
- };
-
- asrc_out3_port: port@9 {
- reg = <0x9>;
-
- asrc_out3_ep: endpoint {
- remote-endpoint = <&xbar_asrc_out3_ep>;
- };
- };
-
- asrc_out4_port: port@a {
- reg = <0xa>;
-
- asrc_out4_ep: endpoint {
- remote-endpoint = <&xbar_asrc_out4_ep>;
- };
- };
-
- asrc_out5_port: port@b {
- reg = <0xb>;
-
- asrc_out5_ep: endpoint {
- remote-endpoint = <&xbar_asrc_out5_ep>;
- };
- };
-
- asrc_out6_port: port@c {
- reg = <0xc>;
-
- asrc_out6_ep: endpoint {
- remote-endpoint = <&xbar_asrc_out6_ep>;
- };
- };
- };
- };
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0x0>;
-
- xbar_admaif0: endpoint {
- remote-endpoint = <&admaif0>;
- };
- };
-
- port@1 {
- reg = <0x1>;
-
- xbar_admaif1: endpoint {
- remote-endpoint = <&admaif1>;
- };
- };
-
- port@2 {
- reg = <0x2>;
-
- xbar_admaif2: endpoint {
- remote-endpoint = <&admaif2>;
- };
- };
-
- port@3 {
- reg = <0x3>;
-
- xbar_admaif3: endpoint {
- remote-endpoint = <&admaif3>;
- };
- };
-
- port@4 {
- reg = <0x4>;
-
- xbar_admaif4: endpoint {
- remote-endpoint = <&admaif4>;
- };
- };
-
- port@5 {
- reg = <0x5>;
-
- xbar_admaif5: endpoint {
- remote-endpoint = <&admaif5>;
- };
- };
-
- port@6 {
- reg = <0x6>;
-
- xbar_admaif6: endpoint {
- remote-endpoint = <&admaif6>;
- };
- };
-
- port@7 {
- reg = <0x7>;
-
- xbar_admaif7: endpoint {
- remote-endpoint = <&admaif7>;
- };
- };
-
- port@8 {
- reg = <0x8>;
-
- xbar_admaif8: endpoint {
- remote-endpoint = <&admaif8>;
- };
- };
-
- port@9 {
- reg = <0x9>;
-
- xbar_admaif9: endpoint {
- remote-endpoint = <&admaif9>;
- };
- };
-
- port@a {
- reg = <0xa>;
-
- xbar_admaif10: endpoint {
- remote-endpoint = <&admaif10>;
- };
- };
-
- port@b {
- reg = <0xb>;
-
- xbar_admaif11: endpoint {
- remote-endpoint = <&admaif11>;
- };
- };
-
- port@c {
- reg = <0xc>;
-
- xbar_admaif12: endpoint {
- remote-endpoint = <&admaif12>;
- };
- };
-
- port@d {
- reg = <0xd>;
-
- xbar_admaif13: endpoint {
- remote-endpoint = <&admaif13>;
- };
- };
-
- port@e {
- reg = <0xe>;
-
- xbar_admaif14: endpoint {
- remote-endpoint = <&admaif14>;
- };
- };
-
- port@f {
- reg = <0xf>;
-
- xbar_admaif15: endpoint {
- remote-endpoint = <&admaif15>;
- };
- };
-
- port@10 {
- reg = <0x10>;
-
- xbar_admaif16: endpoint {
- remote-endpoint = <&admaif16>;
- };
- };
-
- port@11 {
- reg = <0x11>;
-
- xbar_admaif17: endpoint {
- remote-endpoint = <&admaif17>;
- };
- };
-
- port@12 {
- reg = <0x12>;
-
- xbar_admaif18: endpoint {
- remote-endpoint = <&admaif18>;
- };
- };
-
- port@13 {
- reg = <0x13>;
-
- xbar_admaif19: endpoint {
- remote-endpoint = <&admaif19>;
- };
- };
-
- xbar_i2s1_port: port@14 {
- reg = <0x14>;
-
- xbar_i2s1: endpoint {
- remote-endpoint = <&i2s1_cif>;
- };
- };
-
- xbar_i2s2_port: port@15 {
- reg = <0x15>;
-
- xbar_i2s2: endpoint {
- remote-endpoint = <&i2s2_cif>;
- };
- };
-
- xbar_i2s4_port: port@17 {
- reg = <0x17>;
-
- xbar_i2s4: endpoint {
- remote-endpoint = <&i2s4_cif>;
- };
- };
-
- xbar_i2s6_port: port@19 {
- reg = <0x19>;
-
- xbar_i2s6: endpoint {
- remote-endpoint = <&i2s6_cif>;
- };
- };
-
- xbar_dmic3_port: port@1c {
- reg = <0x1c>;
-
- xbar_dmic3: endpoint {
- remote-endpoint = <&dmic3_cif>;
- };
- };
-
- xbar_sfc1_in_port: port@20 {
- reg = <0x20>;
-
- xbar_sfc1_in: endpoint {
- remote-endpoint = <&sfc1_cif_in>;
- };
- };
-
- port@21 {
- reg = <0x21>;
-
- xbar_sfc1_out: endpoint {
- remote-endpoint = <&sfc1_cif_out>;
- };
- };
-
- xbar_sfc2_in_port: port@22 {
- reg = <0x22>;
-
- xbar_sfc2_in: endpoint {
- remote-endpoint = <&sfc2_cif_in>;
- };
- };
-
- port@23 {
- reg = <0x23>;
-
- xbar_sfc2_out: endpoint {
- remote-endpoint = <&sfc2_cif_out>;
- };
- };
-
- xbar_sfc3_in_port: port@24 {
- reg = <0x24>;
-
- xbar_sfc3_in: endpoint {
- remote-endpoint = <&sfc3_cif_in>;
- };
- };
-
- port@25 {
- reg = <0x25>;
-
- xbar_sfc3_out: endpoint {
- remote-endpoint = <&sfc3_cif_out>;
- };
- };
-
- xbar_sfc4_in_port: port@26 {
- reg = <0x26>;
-
- xbar_sfc4_in: endpoint {
- remote-endpoint = <&sfc4_cif_in>;
- };
- };
-
- port@27 {
- reg = <0x27>;
-
- xbar_sfc4_out: endpoint {
- remote-endpoint = <&sfc4_cif_out>;
- };
- };
-
- xbar_mvc1_in_port: port@28 {
- reg = <0x28>;
-
- xbar_mvc1_in: endpoint {
- remote-endpoint = <&mvc1_cif_in>;
- };
- };
-
- port@29 {
- reg = <0x29>;
-
- xbar_mvc1_out: endpoint {
- remote-endpoint = <&mvc1_cif_out>;
- };
- };
-
- xbar_mvc2_in_port: port@2a {
- reg = <0x2a>;
-
- xbar_mvc2_in: endpoint {
- remote-endpoint = <&mvc2_cif_in>;
- };
- };
-
- port@2b {
- reg = <0x2b>;
-
- xbar_mvc2_out: endpoint {
- remote-endpoint = <&mvc2_cif_out>;
- };
- };
-
- xbar_amx1_in1_port: port@2c {
- reg = <0x2c>;
-
- xbar_amx1_in1: endpoint {
- remote-endpoint = <&amx1_in1>;
- };
- };
-
- xbar_amx1_in2_port: port@2d {
- reg = <0x2d>;
-
- xbar_amx1_in2: endpoint {
- remote-endpoint = <&amx1_in2>;
- };
- };
-
- xbar_amx1_in3_port: port@2e {
- reg = <0x2e>;
-
- xbar_amx1_in3: endpoint {
- remote-endpoint = <&amx1_in3>;
- };
- };
-
- xbar_amx1_in4_port: port@2f {
- reg = <0x2f>;
-
- xbar_amx1_in4: endpoint {
- remote-endpoint = <&amx1_in4>;
- };
- };
-
- port@30 {
- reg = <0x30>;
-
- xbar_amx1_out: endpoint {
- remote-endpoint = <&amx1_out>;
- };
- };
-
- xbar_amx2_in1_port: port@31 {
- reg = <0x31>;
-
- xbar_amx2_in1: endpoint {
- remote-endpoint = <&amx2_in1>;
- };
- };
-
- xbar_amx2_in2_port: port@32 {
- reg = <0x32>;
-
- xbar_amx2_in2: endpoint {
- remote-endpoint = <&amx2_in2>;
- };
- };
-
- xbar_amx2_in3_port: port@33 {
- reg = <0x33>;
-
- xbar_amx2_in3: endpoint {
- remote-endpoint = <&amx2_in3>;
- };
- };
-
- xbar_amx2_in4_port: port@34 {
- reg = <0x34>;
-
- xbar_amx2_in4: endpoint {
- remote-endpoint = <&amx2_in4>;
- };
- };
-
- port@35 {
- reg = <0x35>;
-
- xbar_amx2_out: endpoint {
- remote-endpoint = <&amx2_out>;
- };
- };
-
- xbar_amx3_in1_port: port@36 {
- reg = <0x36>;
-
- xbar_amx3_in1: endpoint {
- remote-endpoint = <&amx3_in1>;
- };
- };
-
- xbar_amx3_in2_port: port@37 {
- reg = <0x37>;
-
- xbar_amx3_in2: endpoint {
- remote-endpoint = <&amx3_in2>;
- };
- };
-
- xbar_amx3_in3_port: port@38 {
- reg = <0x38>;
-
- xbar_amx3_in3: endpoint {
- remote-endpoint = <&amx3_in3>;
- };
- };
-
- xbar_amx3_in4_port: port@39 {
- reg = <0x39>;
-
- xbar_amx3_in4: endpoint {
- remote-endpoint = <&amx3_in4>;
- };
- };
-
- port@3a {
- reg = <0x3a>;
-
- xbar_amx3_out: endpoint {
- remote-endpoint = <&amx3_out>;
- };
- };
-
- xbar_amx4_in1_port: port@3b {
- reg = <0x3b>;
-
- xbar_amx4_in1: endpoint {
- remote-endpoint = <&amx4_in1>;
- };
- };
-
- xbar_amx4_in2_port: port@3c {
- reg = <0x3c>;
-
- xbar_amx4_in2: endpoint {
- remote-endpoint = <&amx4_in2>;
- };
- };
-
- xbar_amx4_in3_port: port@3d {
- reg = <0x3d>;
-
- xbar_amx4_in3: endpoint {
- remote-endpoint = <&amx4_in3>;
- };
- };
-
- xbar_amx4_in4_port: port@3e {
- reg = <0x3e>;
-
- xbar_amx4_in4: endpoint {
- remote-endpoint = <&amx4_in4>;
- };
- };
-
- port@3f {
- reg = <0x3f>;
-
- xbar_amx4_out: endpoint {
- remote-endpoint = <&amx4_out>;
- };
- };
-
- xbar_adx1_in_port: port@40 {
- reg = <0x40>;
-
- xbar_adx1_in: endpoint {
- remote-endpoint = <&adx1_in>;
- };
- };
-
- port@41 {
- reg = <0x41>;
-
- xbar_adx1_out1: endpoint {
- remote-endpoint = <&adx1_out1>;
- };
- };
-
- port@42 {
- reg = <0x42>;
-
- xbar_adx1_out2: endpoint {
- remote-endpoint = <&adx1_out2>;
- };
- };
-
- port@43 {
- reg = <0x43>;
-
- xbar_adx1_out3: endpoint {
- remote-endpoint = <&adx1_out3>;
- };
- };
-
- port@44 {
- reg = <0x44>;
-
- xbar_adx1_out4: endpoint {
- remote-endpoint = <&adx1_out4>;
- };
- };
-
- xbar_adx2_in_port: port@45 {
- reg = <0x45>;
-
- xbar_adx2_in: endpoint {
- remote-endpoint = <&adx2_in>;
- };
- };
-
- port@46 {
- reg = <0x46>;
-
- xbar_adx2_out1: endpoint {
- remote-endpoint = <&adx2_out1>;
- };
- };
-
- port@47 {
- reg = <0x47>;
-
- xbar_adx2_out2: endpoint {
- remote-endpoint = <&adx2_out2>;
- };
- };
-
- port@48 {
- reg = <0x48>;
-
- xbar_adx2_out3: endpoint {
- remote-endpoint = <&adx2_out3>;
- };
- };
-
- port@49 {
- reg = <0x49>;
-
- xbar_adx2_out4: endpoint {
- remote-endpoint = <&adx2_out4>;
- };
- };
-
- xbar_adx3_in_port: port@4a {
- reg = <0x4a>;
-
- xbar_adx3_in: endpoint {
- remote-endpoint = <&adx3_in>;
- };
- };
-
- port@4b {
- reg = <0x4b>;
-
- xbar_adx3_out1: endpoint {
- remote-endpoint = <&adx3_out1>;
- };
- };
-
- port@4c {
- reg = <0x4c>;
-
- xbar_adx3_out2: endpoint {
- remote-endpoint = <&adx3_out2>;
- };
- };
-
- port@4d {
- reg = <0x4d>;
-
- xbar_adx3_out3: endpoint {
- remote-endpoint = <&adx3_out3>;
- };
- };
-
- port@4e {
- reg = <0x4e>;
-
- xbar_adx3_out4: endpoint {
- remote-endpoint = <&adx3_out4>;
- };
- };
-
- xbar_adx4_in_port: port@4f {
- reg = <0x4f>;
-
- xbar_adx4_in: endpoint {
- remote-endpoint = <&adx4_in>;
- };
- };
-
- port@50 {
- reg = <0x50>;
-
- xbar_adx4_out1: endpoint {
- remote-endpoint = <&adx4_out1>;
- };
- };
-
- port@51 {
- reg = <0x51>;
-
- xbar_adx4_out2: endpoint {
- remote-endpoint = <&adx4_out2>;
- };
- };
-
- port@52 {
- reg = <0x52>;
-
- xbar_adx4_out3: endpoint {
- remote-endpoint = <&adx4_out3>;
- };
- };
-
- port@53 {
- reg = <0x53>;
-
- xbar_adx4_out4: endpoint {
- remote-endpoint = <&adx4_out4>;
- };
- };
-
- xbar_mix_in1_port: port@54 {
- reg = <0x54>;
-
- xbar_mix_in1: endpoint {
- remote-endpoint = <&mix_in1>;
- };
- };
-
- xbar_mix_in2_port: port@55 {
- reg = <0x55>;
-
- xbar_mix_in2: endpoint {
- remote-endpoint = <&mix_in2>;
- };
- };
-
- xbar_mix_in3_port: port@56 {
- reg = <0x56>;
-
- xbar_mix_in3: endpoint {
- remote-endpoint = <&mix_in3>;
- };
- };
-
- xbar_mix_in4_port: port@57 {
- reg = <0x57>;
-
- xbar_mix_in4: endpoint {
- remote-endpoint = <&mix_in4>;
- };
- };
-
- xbar_mix_in5_port: port@58 {
- reg = <0x58>;
-
- xbar_mix_in5: endpoint {
- remote-endpoint = <&mix_in5>;
- };
- };
-
- xbar_mix_in6_port: port@59 {
- reg = <0x59>;
-
- xbar_mix_in6: endpoint {
- remote-endpoint = <&mix_in6>;
- };
- };
-
- xbar_mix_in7_port: port@5a {
- reg = <0x5a>;
-
- xbar_mix_in7: endpoint {
- remote-endpoint = <&mix_in7>;
- };
- };
-
- xbar_mix_in8_port: port@5b {
- reg = <0x5b>;
-
- xbar_mix_in8: endpoint {
- remote-endpoint = <&mix_in8>;
- };
- };
-
- xbar_mix_in9_port: port@5c {
- reg = <0x5c>;
-
- xbar_mix_in9: endpoint {
- remote-endpoint = <&mix_in9>;
- };
- };
-
- xbar_mix_in10_port: port@5d {
- reg = <0x5d>;
-
- xbar_mix_in10: endpoint {
- remote-endpoint = <&mix_in10>;
- };
- };
-
- port@5e {
- reg = <0x5e>;
-
- xbar_mix_out1: endpoint {
- remote-endpoint = <&mix_out1>;
- };
- };
-
- port@5f {
- reg = <0x5f>;
-
- xbar_mix_out2: endpoint {
- remote-endpoint = <&mix_out2>;
- };
- };
-
- port@60 {
- reg = <0x60>;
-
- xbar_mix_out3: endpoint {
- remote-endpoint = <&mix_out3>;
- };
- };
-
- port@61 {
- reg = <0x61>;
-
- xbar_mix_out4: endpoint {
- remote-endpoint = <&mix_out4>;
- };
- };
-
- port@62 {
- reg = <0x62>;
-
- xbar_mix_out5: endpoint {
- remote-endpoint = <&mix_out5>;
- };
- };
-
- xbar_asrc_in1_port: port@63 {
- reg = <0x63>;
-
- xbar_asrc_in1_ep: endpoint {
- remote-endpoint = <&asrc_in1_ep>;
- };
- };
-
- port@64 {
- reg = <0x64>;
-
- xbar_asrc_out1_ep: endpoint {
- remote-endpoint = <&asrc_out1_ep>;
- };
- };
-
- xbar_asrc_in2_port: port@65 {
- reg = <0x65>;
-
- xbar_asrc_in2_ep: endpoint {
- remote-endpoint = <&asrc_in2_ep>;
- };
- };
-
- port@66 {
- reg = <0x66>;
-
- xbar_asrc_out2_ep: endpoint {
- remote-endpoint = <&asrc_out2_ep>;
- };
- };
-
- xbar_asrc_in3_port: port@67 {
- reg = <0x67>;
-
- xbar_asrc_in3_ep: endpoint {
- remote-endpoint = <&asrc_in3_ep>;
- };
- };
-
- port@68 {
- reg = <0x68>;
-
- xbar_asrc_out3_ep: endpoint {
- remote-endpoint = <&asrc_out3_ep>;
- };
- };
-
- xbar_asrc_in4_port: port@69 {
- reg = <0x69>;
-
- xbar_asrc_in4_ep: endpoint {
- remote-endpoint = <&asrc_in4_ep>;
- };
- };
-
- port@6a {
- reg = <0x6a>;
-
- xbar_asrc_out4_ep: endpoint {
- remote-endpoint = <&asrc_out4_ep>;
- };
- };
-
- xbar_asrc_in5_port: port@6b {
- reg = <0x6b>;
-
- xbar_asrc_in5_ep: endpoint {
- remote-endpoint = <&asrc_in5_ep>;
- };
- };
-
- port@6c {
- reg = <0x6c>;
-
- xbar_asrc_out5_ep: endpoint {
- remote-endpoint = <&asrc_out5_ep>;
- };
- };
-
- xbar_asrc_in6_port: port@6d {
- reg = <0x6d>;
-
- xbar_asrc_in6_ep: endpoint {
- remote-endpoint = <&asrc_in6_ep>;
- };
- };
-
- port@6e {
- reg = <0x6e>;
-
- xbar_asrc_out6_ep: endpoint {
- remote-endpoint = <&asrc_out6_ep>;
- };
- };
-
- xbar_asrc_in7_port: port@6f {
- reg = <0x6f>;
-
- xbar_asrc_in7_ep: endpoint {
- remote-endpoint = <&asrc_in7_ep>;
- };
- };
-
- xbar_ope1_in_port: port@70 {
- reg = <0x70>;
-
- xbar_ope1_in_ep: endpoint {
- remote-endpoint = <&ope1_cif_in_ep>;
- };
- };
-
- port@71 {
- reg = <0x71>;
-
- xbar_ope1_out_ep: endpoint {
- remote-endpoint = <&ope1_cif_out_ep>;
- };
- };
};
};
compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";
aliases {
- mmc3 = "/bus@0/mmc@3460000";
serial0 = &tcu;
serial1 = &uarta;
};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-
-#include "tegra234-p3767.dtsi"
-
-/ {
- compatible = "nvidia,p3767-0000", "nvidia,tegra234";
- model = "NVIDIA Jetson Orin NX";
-
- bus@0 {
- hda@3510000 {
- nvidia,model = "NVIDIA Jetson Orin NX HDA";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-
-#include "tegra234-p3767.dtsi"
-
-/ {
- compatible = "nvidia,p3767-0005", "nvidia,tegra234";
- model = "NVIDIA Jetson Orin Nano";
-
- bus@0 {
- hda@3510000 {
- nvidia,model = "NVIDIA Jetson Orin Nano HDA";
- };
- };
-};
/ {
compatible = "nvidia,p3767", "nvidia,tegra234";
+ aliases {
+ mmc0 = "/bus@0/mmc@3400000";
+ };
+
bus@0 {
+ aconnect@2900000 {
+ status = "okay";
+
+ ahub@2900800 {
+ status = "okay";
+
+ i2s@2901100 {
+ status = "okay";
+ };
+
+ i2s@2901300 {
+ status = "okay";
+ };
+ };
+
+ dma-controller@2930000 {
+ status = "okay";
+ };
+
+ interrupt-controller@2a40000 {
+ status = "okay";
+ };
+ };
+
i2c@3160000 {
status = "okay";
vin-supply = <&vdd_5v0_sys>;
};
+ sound {
+ compatible = "nvidia,tegra186-audio-graph-card";
+ status = "okay";
+
+ dais = /* ADMAIF (FE) Ports */
+ <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+ <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
+ <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
+ <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
+ <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
+ /* XBAR Ports */
+ <&xbar_i2s2_port>, <&xbar_i2s4_port>,
+ <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
+ <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
+ <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
+ <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
+ <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
+ <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
+ <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
+ <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
+ <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
+ <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
+ <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
+ <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
+ <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
+ <&xbar_mix_in1_port>, <&xbar_mix_in2_port>,
+ <&xbar_mix_in3_port>, <&xbar_mix_in4_port>,
+ <&xbar_mix_in5_port>, <&xbar_mix_in6_port>,
+ <&xbar_mix_in7_port>, <&xbar_mix_in8_port>,
+ <&xbar_mix_in9_port>, <&xbar_mix_in10_port>,
+ <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
+ <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
+ <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
+ <&xbar_asrc_in7_port>,
+ <&xbar_ope1_in_port>,
+ /* HW accelerators */
+ <&sfc1_out_port>, <&sfc2_out_port>,
+ <&sfc3_out_port>, <&sfc4_out_port>,
+ <&mvc1_out_port>, <&mvc2_out_port>,
+ <&amx1_out_port>, <&amx2_out_port>,
+ <&amx3_out_port>, <&amx4_out_port>,
+ <&adx1_out1_port>, <&adx1_out2_port>,
+ <&adx1_out3_port>, <&adx1_out4_port>,
+ <&adx2_out1_port>, <&adx2_out2_port>,
+ <&adx2_out3_port>, <&adx2_out4_port>,
+ <&adx3_out1_port>, <&adx3_out2_port>,
+ <&adx3_out3_port>, <&adx3_out4_port>,
+ <&adx4_out1_port>, <&adx4_out2_port>,
+ <&adx4_out3_port>, <&adx4_out4_port>,
+ <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>,
+ <&mix_out4_port>, <&mix_out5_port>,
+ <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
+ <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+ <&ope1_out_port>,
+ /* BE I/O Ports */
+ <&i2s2_port>, <&i2s4_port>;
+ };
+
thermal-zones {
tj-thermal {
polling-delay = <1000>;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/input/gpio-keys.h>
-#include "tegra234-p3767-0000.dtsi"
+#include "tegra234-p3767.dtsi"
#include "tegra234-p3768-0000.dtsi"
/ {
hda@3510000 {
nvidia,model = "NVIDIA Jetson Orin NX HDA";
- status = "okay";
};
padctl@3520000 {
enable-active-high;
};
+ sound {
+ label = "NVIDIA Jetson Orin NX APE";
+ };
+
thermal-zones {
tj-thermal {
cooling-maps {
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/input/gpio-keys.h>
-#include "tegra234-p3767-0005.dtsi"
+#include "tegra234-p3767.dtsi"
#include "tegra234-p3768-0000.dtsi"
/ {
compatible = "nvidia,p3768-0000+p3767-0005", "nvidia,p3767-0005", "nvidia,tegra234";
model = "NVIDIA Jetson Orin Nano Developer Kit";
+ bus@0 {
+ hda@3510000 {
+ nvidia,model = "NVIDIA Jetson Orin Nano HDA";
+ };
+ };
+
pwm-fan {
cooling-levels = <0 88 187 255>;
};
+ sound {
+ label = "NVIDIA Jetson Orin Nano APE";
+ };
+
thermal-zones {
tj-thermal {
cooling-maps {
compatible = "nvidia,tegra234-vdk", "nvidia,tegra234";
aliases {
- mmc3 = "/bus@0/mmc@3460000";
serial0 = &uarta;
};
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S1";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s1_cif: endpoint {
+ remote-endpoint = <&xbar_i2s1>;
+ };
+ };
+
+ i2s1_port: port@1 {
+ reg = <1>;
+
+ i2s1_dap: endpoint {
+ dai-format = "i2s";
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_i2s2: i2s@2901100 {
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S2";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s2_cif: endpoint {
+ remote-endpoint = <&xbar_i2s2>;
+ };
+ };
+
+ i2s2_port: port@1 {
+ reg = <1>;
+
+ i2s2_dap: endpoint {
+ dai-format = "i2s";
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_i2s3: i2s@2901200 {
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S3";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s3_cif: endpoint {
+ remote-endpoint = <&xbar_i2s3>;
+ };
+ };
+
+ i2s3_port: port@1 {
+ reg = <1>;
+
+ i2s3_dap: endpoint {
+ dai-format = "i2s";
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_i2s4: i2s@2901300 {
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S4";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s4_cif: endpoint {
+ remote-endpoint = <&xbar_i2s4>;
+ };
+ };
+
+ i2s4_port: port@1 {
+ reg = <1>;
+
+ i2s4_dap: endpoint {
+ dai-format = "i2s";
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_i2s5: i2s@2901400 {
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S5";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s5_cif: endpoint {
+ remote-endpoint = <&xbar_i2s5>;
+ };
+ };
+
+ i2s5_port: port@1 {
+ reg = <1>;
+
+ i2s5_dap: endpoint {
+ dai-format = "i2s";
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_i2s6: i2s@2901500 {
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S6";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s6_cif: endpoint {
+ remote-endpoint = <&xbar_i2s6>;
+ };
+ };
+
+ i2s6_port: port@1 {
+ reg = <1>;
+
+ i2s6_dap: endpoint {
+ dai-format = "i2s";
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_sfc1: sfc@2902000 {
"nvidia,tegra210-sfc";
reg = <0x0 0x2902000 0x0 0x200>;
sound-name-prefix = "SFC1";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc1_cif_in: endpoint {
+ remote-endpoint = <&xbar_sfc1_in>;
+ };
+ };
+
+ sfc1_out_port: port@1 {
+ reg = <1>;
+
+ sfc1_cif_out: endpoint {
+ remote-endpoint = <&xbar_sfc1_out>;
+ };
+ };
+ };
};
tegra_sfc2: sfc@2902200 {
"nvidia,tegra210-sfc";
reg = <0x0 0x2902200 0x0 0x200>;
sound-name-prefix = "SFC2";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc2_cif_in: endpoint {
+ remote-endpoint = <&xbar_sfc2_in>;
+ };
+ };
+
+ sfc2_out_port: port@1 {
+ reg = <1>;
+
+ sfc2_cif_out: endpoint {
+ remote-endpoint = <&xbar_sfc2_out>;
+ };
+ };
+ };
};
tegra_sfc3: sfc@2902400 {
"nvidia,tegra210-sfc";
reg = <0x0 0x2902400 0x0 0x200>;
sound-name-prefix = "SFC3";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc3_cif_in: endpoint {
+ remote-endpoint = <&xbar_sfc3_in>;
+ };
+ };
+
+ sfc3_out_port: port@1 {
+ reg = <1>;
+
+ sfc3_cif_out: endpoint {
+ remote-endpoint = <&xbar_sfc3_out>;
+ };
+ };
+ };
};
tegra_sfc4: sfc@2902600 {
"nvidia,tegra210-sfc";
reg = <0x0 0x2902600 0x0 0x200>;
sound-name-prefix = "SFC4";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc4_cif_in: endpoint {
+ remote-endpoint = <&xbar_sfc4_in>;
+ };
+ };
+
+ sfc4_out_port: port@1 {
+ reg = <1>;
+
+ sfc4_cif_out: endpoint {
+ remote-endpoint = <&xbar_sfc4_out>;
+ };
+ };
+ };
};
tegra_amx1: amx@2903000 {
"nvidia,tegra194-amx";
reg = <0x0 0x2903000 0x0 0x100>;
sound-name-prefix = "AMX1";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx1_in1: endpoint {
+ remote-endpoint = <&xbar_amx1_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx1_in2: endpoint {
+ remote-endpoint = <&xbar_amx1_in2>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx1_in3: endpoint {
+ remote-endpoint = <&xbar_amx1_in3>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx1_in4: endpoint {
+ remote-endpoint = <&xbar_amx1_in4>;
+ };
+ };
+
+ amx1_out_port: port@4 {
+ reg = <4>;
+
+ amx1_out: endpoint {
+ remote-endpoint = <&xbar_amx1_out>;
+ };
+ };
+ };
+ };
+
+ tegra_amx2: amx@2903100 {
+ compatible = "nvidia,tegra234-amx",
+ "nvidia,tegra194-amx";
+ reg = <0x0 0x2903100 0x0 0x100>;
+ sound-name-prefix = "AMX2";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx2_in1: endpoint {
+ remote-endpoint = <&xbar_amx2_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx2_in2: endpoint {
+ remote-endpoint = <&xbar_amx2_in2>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx2_in3: endpoint {
+ remote-endpoint = <&xbar_amx2_in3>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx2_in4: endpoint {
+ remote-endpoint = <&xbar_amx2_in4>;
+ };
+ };
+
+ amx2_out_port: port@4 {
+ reg = <4>;
+
+ amx2_out: endpoint {
+ remote-endpoint = <&xbar_amx2_out>;
+ };
+ };
+ };
+ };
+
+ tegra_amx3: amx@2903200 {
+ compatible = "nvidia,tegra234-amx",
+ "nvidia,tegra194-amx";
+ reg = <0x0 0x2903200 0x0 0x100>;
+ sound-name-prefix = "AMX3";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx3_in1: endpoint {
+ remote-endpoint = <&xbar_amx3_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx3_in2: endpoint {
+ remote-endpoint = <&xbar_amx3_in2>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx3_in3: endpoint {
+ remote-endpoint = <&xbar_amx3_in3>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx3_in4: endpoint {
+ remote-endpoint = <&xbar_amx3_in4>;
+ };
+ };
+
+ amx3_out_port: port@4 {
+ reg = <4>;
+
+ amx3_out: endpoint {
+ remote-endpoint = <&xbar_amx3_out>;
+ };
+ };
+ };
+ };
+
+ tegra_amx4: amx@2903300 {
+ compatible = "nvidia,tegra234-amx",
+ "nvidia,tegra194-amx";
+ reg = <0x0 0x2903300 0x0 0x100>;
+ sound-name-prefix = "AMX4";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx4_in1: endpoint {
+ remote-endpoint = <&xbar_amx4_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx4_in2: endpoint {
+ remote-endpoint = <&xbar_amx4_in2>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx4_in3: endpoint {
+ remote-endpoint = <&xbar_amx4_in3>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx4_in4: endpoint {
+ remote-endpoint = <&xbar_amx4_in4>;
+ };
+ };
+
+ amx4_out_port: port@4 {
+ reg = <4>;
+
+ amx4_out: endpoint {
+ remote-endpoint = <&xbar_amx4_out>;
+ };
+ };
+ };
+ };
+
+ tegra_adx1: adx@2903800 {
+ compatible = "nvidia,tegra234-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x0 0x2903800 0x0 0x100>;
+ sound-name-prefix = "ADX1";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx1_in: endpoint {
+ remote-endpoint = <&xbar_adx1_in>;
+ };
+ };
+
+ adx1_out1_port: port@1 {
+ reg = <1>;
+
+ adx1_out1: endpoint {
+ remote-endpoint = <&xbar_adx1_out1>;
+ };
+ };
+
+ adx1_out2_port: port@2 {
+ reg = <2>;
+
+ adx1_out2: endpoint {
+ remote-endpoint = <&xbar_adx1_out2>;
+ };
+ };
+
+ adx1_out3_port: port@3 {
+ reg = <3>;
+
+ adx1_out3: endpoint {
+ remote-endpoint = <&xbar_adx1_out3>;
+ };
+ };
+
+ adx1_out4_port: port@4 {
+ reg = <4>;
+
+ adx1_out4: endpoint {
+ remote-endpoint = <&xbar_adx1_out4>;
+ };
+ };
+ };
+ };
+
+ tegra_adx2: adx@2903900 {
+ compatible = "nvidia,tegra234-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x0 0x2903900 0x0 0x100>;
+ sound-name-prefix = "ADX2";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx2_in: endpoint {
+ remote-endpoint = <&xbar_adx2_in>;
+ };
+ };
+
+ adx2_out1_port: port@1 {
+ reg = <1>;
+
+ adx2_out1: endpoint {
+ remote-endpoint = <&xbar_adx2_out1>;
+ };
+ };
+
+ adx2_out2_port: port@2 {
+ reg = <2>;
+
+ adx2_out2: endpoint {
+ remote-endpoint = <&xbar_adx2_out2>;
+ };
+ };
+
+ adx2_out3_port: port@3 {
+ reg = <3>;
+
+ adx2_out3: endpoint {
+ remote-endpoint = <&xbar_adx2_out3>;
+ };
+ };
+
+ adx2_out4_port: port@4 {
+ reg = <4>;
+
+ adx2_out4: endpoint {
+ remote-endpoint = <&xbar_adx2_out4>;
+ };
+ };
+ };
+ };
+
+ tegra_adx3: adx@2903a00 {
+ compatible = "nvidia,tegra234-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x0 0x2903a00 0x0 0x100>;
+ sound-name-prefix = "ADX3";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx3_in: endpoint {
+ remote-endpoint = <&xbar_adx3_in>;
+ };
+ };
+
+ adx3_out1_port: port@1 {
+ reg = <1>;
+
+ adx3_out1: endpoint {
+ remote-endpoint = <&xbar_adx3_out1>;
+ };
+ };
+
+ adx3_out2_port: port@2 {
+ reg = <2>;
+
+ adx3_out2: endpoint {
+ remote-endpoint = <&xbar_adx3_out2>;
+ };
+ };
+
+ adx3_out3_port: port@3 {
+ reg = <3>;
+
+ adx3_out3: endpoint {
+ remote-endpoint = <&xbar_adx3_out3>;
+ };
+ };
+
+ adx3_out4_port: port@4 {
+ reg = <4>;
+
+ adx3_out4: endpoint {
+ remote-endpoint = <&xbar_adx3_out4>;
+ };
+ };
+ };
};
- tegra_amx2: amx@2903100 {
- compatible = "nvidia,tegra234-amx",
- "nvidia,tegra194-amx";
- reg = <0x0 0x2903100 0x0 0x100>;
- sound-name-prefix = "AMX2";
- status = "disabled";
- };
+ tegra_adx4: adx@2903b00 {
+ compatible = "nvidia,tegra234-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x0 0x2903b00 0x0 0x100>;
+ sound-name-prefix = "ADX4";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx4_in: endpoint {
+ remote-endpoint = <&xbar_adx4_in>;
+ };
+ };
+
+ adx4_out1_port: port@1 {
+ reg = <1>;
+
+ adx4_out1: endpoint {
+ remote-endpoint = <&xbar_adx4_out1>;
+ };
+ };
+
+ adx4_out2_port: port@2 {
+ reg = <2>;
+
+ adx4_out2: endpoint {
+ remote-endpoint = <&xbar_adx4_out2>;
+ };
+ };
+
+ adx4_out3_port: port@3 {
+ reg = <3>;
+
+ adx4_out3: endpoint {
+ remote-endpoint = <&xbar_adx4_out3>;
+ };
+ };
+
+ adx4_out4_port: port@4 {
+ reg = <4>;
+
+ adx4_out4: endpoint {
+ remote-endpoint = <&xbar_adx4_out4>;
+ };
+ };
+ };
+ };
+
+
+ tegra_dmic1: dmic@2904000 {
+ compatible = "nvidia,tegra234-dmic",
+ "nvidia,tegra210-dmic";
+ reg = <0x0 0x2904000 0x0 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_DMIC1>;
+ clock-names = "dmic";
+ assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <3072000>;
+ sound-name-prefix = "DMIC1";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic1_cif: endpoint {
+ remote-endpoint = <&xbar_dmic1>;
+ };
+ };
+
+ dmic1_port: port@1 {
+ reg = <1>;
+
+ dmic1_dap: endpoint {
+ /* placeholder for external codec */
+ };
+ };
+ };
+ };
+
+ tegra_dmic2: dmic@2904100 {
+ compatible = "nvidia,tegra234-dmic",
+ "nvidia,tegra210-dmic";
+ reg = <0x0 0x2904100 0x0 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_DMIC2>;
+ clock-names = "dmic";
+ assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <3072000>;
+ sound-name-prefix = "DMIC2";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic2_cif: endpoint {
+ remote-endpoint = <&xbar_dmic2>;
+ };
+ };
+
+ dmic2_port: port@1 {
+ reg = <1>;
+
+ dmic2_dap: endpoint {
+ /* placeholder for external codec */
+ };
+ };
+ };
+ };
+
+ tegra_dmic3: dmic@2904200 {
+ compatible = "nvidia,tegra234-dmic",
+ "nvidia,tegra210-dmic";
+ reg = <0x0 0x2904200 0x0 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_DMIC3>;
+ clock-names = "dmic";
+ assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <3072000>;
+ sound-name-prefix = "DMIC3";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic3_cif: endpoint {
+ remote-endpoint = <&xbar_dmic3>;
+ };
+ };
+
+ dmic3_port: port@1 {
+ reg = <1>;
+
+ dmic3_dap: endpoint {
+ /* placeholder for external codec */
+ };
+ };
+ };
+ };
+
+ tegra_dmic4: dmic@2904300 {
+ compatible = "nvidia,tegra234-dmic",
+ "nvidia,tegra210-dmic";
+ reg = <0x0 0x2904300 0x0 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_DMIC4>;
+ clock-names = "dmic";
+ assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <3072000>;
+ sound-name-prefix = "DMIC4";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic4_cif: endpoint {
+ remote-endpoint = <&xbar_dmic4>;
+ };
+ };
+
+ dmic4_port: port@1 {
+ reg = <1>;
+
+ dmic4_dap: endpoint {
+ /* placeholder for external codec */
+ };
+ };
+ };
+ };
+
+ tegra_dspk1: dspk@2905000 {
+ compatible = "nvidia,tegra234-dspk",
+ "nvidia,tegra186-dspk";
+ reg = <0x0 0x2905000 0x0 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_DSPK1>;
+ clock-names = "dspk";
+ assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <12288000>;
+ sound-name-prefix = "DSPK1";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk1_cif: endpoint {
+ remote-endpoint = <&xbar_dspk1>;
+ };
+ };
+
+ dspk1_port: port@1 {
+ reg = <1>;
+
+ dspk1_dap: endpoint {
+ /* placeholder for external codec */
+ };
+ };
+ };
+ };
+
+ tegra_dspk2: dspk@2905100 {
+ compatible = "nvidia,tegra234-dspk",
+ "nvidia,tegra186-dspk";
+ reg = <0x0 0x2905100 0x0 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_DSPK2>;
+ clock-names = "dspk";
+ assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <12288000>;
+ sound-name-prefix = "DSPK2";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk2_cif: endpoint {
+ remote-endpoint = <&xbar_dspk2>;
+ };
+ };
+
+ dspk2_port: port@1 {
+ reg = <1>;
+
+ dspk2_dap: endpoint {
+ /* placeholder for external codec */
+ };
+ };
+ };
+ };
+
+ tegra_ope1: processing-engine@2908000 {
+ compatible = "nvidia,tegra234-ope",
+ "nvidia,tegra210-ope";
+ reg = <0x0 0x2908000 0x0 0x100>;
+ sound-name-prefix = "OPE1";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ equalizer@2908100 {
+ compatible = "nvidia,tegra234-peq",
+ "nvidia,tegra210-peq";
+ reg = <0x0 0x2908100 0x0 0x100>;
+ };
+
+ dynamic-range-compressor@2908200 {
+ compatible = "nvidia,tegra234-mbdrc",
+ "nvidia,tegra210-mbdrc";
+ reg = <0x0 0x2908200 0x0 0x200>;
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint =
+ <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port@1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint =
+ <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
+ tegra_mvc1: mvc@290a000 {
+ compatible = "nvidia,tegra234-mvc",
+ "nvidia,tegra210-mvc";
+ reg = <0x0 0x290a000 0x0 0x200>;
+ sound-name-prefix = "MVC1";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc1_cif_in: endpoint {
+ remote-endpoint = <&xbar_mvc1_in>;
+ };
+ };
+
+ mvc1_out_port: port@1 {
+ reg = <1>;
+
+ mvc1_cif_out: endpoint {
+ remote-endpoint = <&xbar_mvc1_out>;
+ };
+ };
+ };
+ };
+
+ tegra_mvc2: mvc@290a200 {
+ compatible = "nvidia,tegra234-mvc",
+ "nvidia,tegra210-mvc";
+ reg = <0x0 0x290a200 0x0 0x200>;
+ sound-name-prefix = "MVC2";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc2_cif_in: endpoint {
+ remote-endpoint = <&xbar_mvc2_in>;
+ };
+ };
+
+ mvc2_out_port: port@1 {
+ reg = <1>;
+
+ mvc2_cif_out: endpoint {
+ remote-endpoint = <&xbar_mvc2_out>;
+ };
+ };
+ };
+ };
+
+ tegra_amixer: amixer@290bb00 {
+ compatible = "nvidia,tegra234-amixer",
+ "nvidia,tegra210-amixer";
+ reg = <0x0 0x290bb00 0x0 0x800>;
+ sound-name-prefix = "MIXER1";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ mix_in1: endpoint {
+ remote-endpoint = <&xbar_mix_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ mix_in2: endpoint {
+ remote-endpoint = <&xbar_mix_in2>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ mix_in3: endpoint {
+ remote-endpoint = <&xbar_mix_in3>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ mix_in4: endpoint {
+ remote-endpoint = <&xbar_mix_in4>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ mix_in5: endpoint {
+ remote-endpoint = <&xbar_mix_in5>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ mix_in6: endpoint {
+ remote-endpoint = <&xbar_mix_in6>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ mix_in7: endpoint {
+ remote-endpoint = <&xbar_mix_in7>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ mix_in8: endpoint {
+ remote-endpoint = <&xbar_mix_in8>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ mix_in9: endpoint {
+ remote-endpoint = <&xbar_mix_in9>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ mix_in10: endpoint {
+ remote-endpoint = <&xbar_mix_in10>;
+ };
+ };
+
+ mix_out1_port: port@a {
+ reg = <0xa>;
+
+ mix_out1: endpoint {
+ remote-endpoint = <&xbar_mix_out1>;
+ };
+ };
+
+ mix_out2_port: port@b {
+ reg = <0xb>;
+
+ mix_out2: endpoint {
+ remote-endpoint = <&xbar_mix_out2>;
+ };
+ };
+
+ mix_out3_port: port@c {
+ reg = <0xc>;
+
+ mix_out3: endpoint {
+ remote-endpoint = <&xbar_mix_out3>;
+ };
+ };
+
+ mix_out4_port: port@d {
+ reg = <0xd>;
+
+ mix_out4: endpoint {
+ remote-endpoint = <&xbar_mix_out4>;
+ };
+ };
+
+ mix_out5_port: port@e {
+ reg = <0xe>;
+
+ mix_out5: endpoint {
+ remote-endpoint = <&xbar_mix_out5>;
+ };
+ };
+ };
+ };
+
+ tegra_admaif: admaif@290f000 {
+ compatible = "nvidia,tegra234-admaif",
+ "nvidia,tegra186-admaif";
+ reg = <0x0 0x0290f000 0x0 0x1000>;
+ dmas = <&adma 1>, <&adma 1>,
+ <&adma 2>, <&adma 2>,
+ <&adma 3>, <&adma 3>,
+ <&adma 4>, <&adma 4>,
+ <&adma 5>, <&adma 5>,
+ <&adma 6>, <&adma 6>,
+ <&adma 7>, <&adma 7>,
+ <&adma 8>, <&adma 8>,
+ <&adma 9>, <&adma 9>,
+ <&adma 10>, <&adma 10>,
+ <&adma 11>, <&adma 11>,
+ <&adma 12>, <&adma 12>,
+ <&adma 13>, <&adma 13>,
+ <&adma 14>, <&adma 14>,
+ <&adma 15>, <&adma 15>,
+ <&adma 16>, <&adma 16>,
+ <&adma 17>, <&adma 17>,
+ <&adma 18>, <&adma 18>,
+ <&adma 19>, <&adma 19>,
+ <&adma 20>, <&adma 20>;
+ dma-names = "rx1", "tx1",
+ "rx2", "tx2",
+ "rx3", "tx3",
+ "rx4", "tx4",
+ "rx5", "tx5",
+ "rx6", "tx6",
+ "rx7", "tx7",
+ "rx8", "tx8",
+ "rx9", "tx9",
+ "rx10", "tx10",
+ "rx11", "tx11",
+ "rx12", "tx12",
+ "rx13", "tx13",
+ "rx14", "tx14",
+ "rx15", "tx15",
+ "rx16", "tx16",
+ "rx17", "tx17",
+ "rx18", "tx18",
+ "rx19", "tx19",
+ "rx20", "tx20";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_APE>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ admaif0_port: port@0 {
+ reg = <0x0>;
+
+ admaif0: endpoint {
+ remote-endpoint = <&xbar_admaif0>;
+ };
+ };
+
+ admaif1_port: port@1 {
+ reg = <0x1>;
+
+ admaif1: endpoint {
+ remote-endpoint = <&xbar_admaif1>;
+ };
+ };
+
+ admaif2_port: port@2 {
+ reg = <0x2>;
+
+ admaif2: endpoint {
+ remote-endpoint = <&xbar_admaif2>;
+ };
+ };
+
+ admaif3_port: port@3 {
+ reg = <0x3>;
+
+ admaif3: endpoint {
+ remote-endpoint = <&xbar_admaif3>;
+ };
+ };
+
+ admaif4_port: port@4 {
+ reg = <0x4>;
+
+ admaif4: endpoint {
+ remote-endpoint = <&xbar_admaif4>;
+ };
+ };
+
+ admaif5_port: port@5 {
+ reg = <0x5>;
+
+ admaif5: endpoint {
+ remote-endpoint = <&xbar_admaif5>;
+ };
+ };
+
+ admaif6_port: port@6 {
+ reg = <0x6>;
+
+ admaif6: endpoint {
+ remote-endpoint = <&xbar_admaif6>;
+ };
+ };
+
+ admaif7_port: port@7 {
+ reg = <0x7>;
+
+ admaif7: endpoint {
+ remote-endpoint = <&xbar_admaif7>;
+ };
+ };
+
+ admaif8_port: port@8 {
+ reg = <0x8>;
+
+ admaif8: endpoint {
+ remote-endpoint = <&xbar_admaif8>;
+ };
+ };
+
+ admaif9_port: port@9 {
+ reg = <0x9>;
+
+ admaif9: endpoint {
+ remote-endpoint = <&xbar_admaif9>;
+ };
+ };
+
+ admaif10_port: port@a {
+ reg = <0xa>;
+
+ admaif10: endpoint {
+ remote-endpoint = <&xbar_admaif10>;
+ };
+ };
+
+ admaif11_port: port@b {
+ reg = <0xb>;
+
+ admaif11: endpoint {
+ remote-endpoint = <&xbar_admaif11>;
+ };
+ };
+
+ admaif12_port: port@c {
+ reg = <0xc>;
+
+ admaif12: endpoint {
+ remote-endpoint = <&xbar_admaif12>;
+ };
+ };
+
+ admaif13_port: port@d {
+ reg = <0xd>;
+
+ admaif13: endpoint {
+ remote-endpoint = <&xbar_admaif13>;
+ };
+ };
+
+ admaif14_port: port@e {
+ reg = <0xe>;
+
+ admaif14: endpoint {
+ remote-endpoint = <&xbar_admaif14>;
+ };
+ };
+
+ admaif15_port: port@f {
+ reg = <0xf>;
+
+ admaif15: endpoint {
+ remote-endpoint = <&xbar_admaif15>;
+ };
+ };
+
+ admaif16_port: port@10 {
+ reg = <0x10>;
+
+ admaif16: endpoint {
+ remote-endpoint = <&xbar_admaif16>;
+ };
+ };
+
+ admaif17_port: port@11 {
+ reg = <0x11>;
+
+ admaif17: endpoint {
+ remote-endpoint = <&xbar_admaif17>;
+ };
+ };
+
+ admaif18_port: port@12 {
+ reg = <0x12>;
+
+ admaif18: endpoint {
+ remote-endpoint = <&xbar_admaif18>;
+ };
+ };
+
+ admaif19_port: port@13 {
+ reg = <0x13>;
+
+ admaif19: endpoint {
+ remote-endpoint = <&xbar_admaif19>;
+ };
+ };
+ };
+ };
+
+ tegra_asrc: asrc@2910000 {
+ compatible = "nvidia,tegra234-asrc",
+ "nvidia,tegra186-asrc";
+ reg = <0x0 0x2910000 0x0 0x2000>;
+ sound-name-prefix = "ASRC1";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ asrc_in1_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ asrc_in2_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ asrc_in3_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ asrc_in4_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in4_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ asrc_in5_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in5_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ asrc_in6_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in6_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ asrc_in7_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in7_ep>;
+ };
+ };
+
+ asrc_out1_port: port@7 {
+ reg = <0x7>;
+
+ asrc_out1_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_out1_ep>;
+ };
+ };
+
+ asrc_out2_port: port@8 {
+ reg = <0x8>;
+
+ asrc_out2_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_out2_ep>;
+ };
+ };
+
+ asrc_out3_port: port@9 {
+ reg = <0x9>;
+
+ asrc_out3_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_out3_ep>;
+ };
+ };
+
+ asrc_out4_port: port@a {
+ reg = <0xa>;
+
+ asrc_out4_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_out4_ep>;
+ };
+ };
+
+ asrc_out5_port: port@b {
+ reg = <0xb>;
+
+ asrc_out5_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_out5_ep>;
+ };
+ };
+
+ asrc_out6_port: port@c {
+ reg = <0xc>;
+
+ asrc_out6_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_out6_ep>;
+ };
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ xbar_admaif0: endpoint {
+ remote-endpoint = <&admaif0>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ xbar_admaif1: endpoint {
+ remote-endpoint = <&admaif1>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ xbar_admaif2: endpoint {
+ remote-endpoint = <&admaif2>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ xbar_admaif3: endpoint {
+ remote-endpoint = <&admaif3>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ xbar_admaif4: endpoint {
+ remote-endpoint = <&admaif4>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ xbar_admaif5: endpoint {
+ remote-endpoint = <&admaif5>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ xbar_admaif6: endpoint {
+ remote-endpoint = <&admaif6>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ xbar_admaif7: endpoint {
+ remote-endpoint = <&admaif7>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ xbar_admaif8: endpoint {
+ remote-endpoint = <&admaif8>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ xbar_admaif9: endpoint {
+ remote-endpoint = <&admaif9>;
+ };
+ };
+
+ port@a {
+ reg = <0xa>;
+
+ xbar_admaif10: endpoint {
+ remote-endpoint = <&admaif10>;
+ };
+ };
+
+ port@b {
+ reg = <0xb>;
+
+ xbar_admaif11: endpoint {
+ remote-endpoint = <&admaif11>;
+ };
+ };
+
+ port@c {
+ reg = <0xc>;
+
+ xbar_admaif12: endpoint {
+ remote-endpoint = <&admaif12>;
+ };
+ };
+
+ port@d {
+ reg = <0xd>;
+
+ xbar_admaif13: endpoint {
+ remote-endpoint = <&admaif13>;
+ };
+ };
+
+ port@e {
+ reg = <0xe>;
+
+ xbar_admaif14: endpoint {
+ remote-endpoint = <&admaif14>;
+ };
+ };
+
+ port@f {
+ reg = <0xf>;
+
+ xbar_admaif15: endpoint {
+ remote-endpoint = <&admaif15>;
+ };
+ };
+
+ port@10 {
+ reg = <0x10>;
+
+ xbar_admaif16: endpoint {
+ remote-endpoint = <&admaif16>;
+ };
+ };
+
+ port@11 {
+ reg = <0x11>;
+
+ xbar_admaif17: endpoint {
+ remote-endpoint = <&admaif17>;
+ };
+ };
+
+ port@12 {
+ reg = <0x12>;
+
+ xbar_admaif18: endpoint {
+ remote-endpoint = <&admaif18>;
+ };
+ };
+
+ port@13 {
+ reg = <0x13>;
+
+ xbar_admaif19: endpoint {
+ remote-endpoint = <&admaif19>;
+ };
+ };
+
+ xbar_i2s1_port: port@14 {
+ reg = <0x14>;
+
+ xbar_i2s1: endpoint {
+ remote-endpoint = <&i2s1_cif>;
+ };
+ };
+
+ xbar_i2s2_port: port@15 {
+ reg = <0x15>;
+
+ xbar_i2s2: endpoint {
+ remote-endpoint = <&i2s2_cif>;
+ };
+ };
+
+ xbar_i2s3_port: port@16 {
+ reg = <0x16>;
+
+ xbar_i2s3: endpoint {
+ remote-endpoint = <&i2s3_cif>;
+ };
+ };
+
+ xbar_i2s4_port: port@17 {
+ reg = <0x17>;
+
+ xbar_i2s4: endpoint {
+ remote-endpoint = <&i2s4_cif>;
+ };
+ };
+
+ xbar_i2s5_port: port@18 {
+ reg = <0x18>;
+
+ xbar_i2s5: endpoint {
+ remote-endpoint = <&i2s5_cif>;
+ };
+ };
+
+ xbar_i2s6_port: port@19 {
+ reg = <0x19>;
+
+ xbar_i2s6: endpoint {
+ remote-endpoint = <&i2s6_cif>;
+ };
+ };
+
+ xbar_dmic1_port: port@1a {
+ reg = <0x1a>;
+
+ xbar_dmic1: endpoint {
+ remote-endpoint = <&dmic1_cif>;
+ };
+ };
+
+ xbar_dmic2_port: port@1b {
+ reg = <0x1b>;
+
+ xbar_dmic2: endpoint {
+ remote-endpoint = <&dmic2_cif>;
+ };
+ };
+
+ xbar_dmic3_port: port@1c {
+ reg = <0x1c>;
+
+ xbar_dmic3: endpoint {
+ remote-endpoint = <&dmic3_cif>;
+ };
+ };
+
+ xbar_dmic4_port: port@1d {
+ reg = <0x1d>;
+
+ xbar_dmic4: endpoint {
+ remote-endpoint = <&dmic4_cif>;
+ };
+ };
+
+ xbar_dspk1_port: port@1e {
+ reg = <0x1e>;
+
+ xbar_dspk1: endpoint {
+ remote-endpoint = <&dspk1_cif>;
+ };
+ };
+
+ xbar_dspk2_port: port@1f {
+ reg = <0x1f>;
+
+ xbar_dspk2: endpoint {
+ remote-endpoint = <&dspk2_cif>;
+ };
+ };
+
+ xbar_sfc1_in_port: port@20 {
+ reg = <0x20>;
+
+ xbar_sfc1_in: endpoint {
+ remote-endpoint = <&sfc1_cif_in>;
+ };
+ };
+
+ port@21 {
+ reg = <0x21>;
+
+ xbar_sfc1_out: endpoint {
+ remote-endpoint = <&sfc1_cif_out>;
+ };
+ };
+
+ xbar_sfc2_in_port: port@22 {
+ reg = <0x22>;
+
+ xbar_sfc2_in: endpoint {
+ remote-endpoint = <&sfc2_cif_in>;
+ };
+ };
+
+ port@23 {
+ reg = <0x23>;
+
+ xbar_sfc2_out: endpoint {
+ remote-endpoint = <&sfc2_cif_out>;
+ };
+ };
+
+ xbar_sfc3_in_port: port@24 {
+ reg = <0x24>;
+
+ xbar_sfc3_in: endpoint {
+ remote-endpoint = <&sfc3_cif_in>;
+ };
+ };
+
+ port@25 {
+ reg = <0x25>;
+
+ xbar_sfc3_out: endpoint {
+ remote-endpoint = <&sfc3_cif_out>;
+ };
+ };
+
+ xbar_sfc4_in_port: port@26 {
+ reg = <0x26>;
+
+ xbar_sfc4_in: endpoint {
+ remote-endpoint = <&sfc4_cif_in>;
+ };
+ };
+
+ port@27 {
+ reg = <0x27>;
+
+ xbar_sfc4_out: endpoint {
+ remote-endpoint = <&sfc4_cif_out>;
+ };
+ };
+
+ xbar_mvc1_in_port: port@28 {
+ reg = <0x28>;
+
+ xbar_mvc1_in: endpoint {
+ remote-endpoint = <&mvc1_cif_in>;
+ };
+ };
+
+ port@29 {
+ reg = <0x29>;
+
+ xbar_mvc1_out: endpoint {
+ remote-endpoint = <&mvc1_cif_out>;
+ };
+ };
+
+ xbar_mvc2_in_port: port@2a {
+ reg = <0x2a>;
+
+ xbar_mvc2_in: endpoint {
+ remote-endpoint = <&mvc2_cif_in>;
+ };
+ };
+
+ port@2b {
+ reg = <0x2b>;
+
+ xbar_mvc2_out: endpoint {
+ remote-endpoint = <&mvc2_cif_out>;
+ };
+ };
+
+ xbar_amx1_in1_port: port@2c {
+ reg = <0x2c>;
+
+ xbar_amx1_in1: endpoint {
+ remote-endpoint = <&amx1_in1>;
+ };
+ };
+
+ xbar_amx1_in2_port: port@2d {
+ reg = <0x2d>;
+
+ xbar_amx1_in2: endpoint {
+ remote-endpoint = <&amx1_in2>;
+ };
+ };
+
+ xbar_amx1_in3_port: port@2e {
+ reg = <0x2e>;
+
+ xbar_amx1_in3: endpoint {
+ remote-endpoint = <&amx1_in3>;
+ };
+ };
+
+ xbar_amx1_in4_port: port@2f {
+ reg = <0x2f>;
+
+ xbar_amx1_in4: endpoint {
+ remote-endpoint = <&amx1_in4>;
+ };
+ };
+
+ port@30 {
+ reg = <0x30>;
+
+ xbar_amx1_out: endpoint {
+ remote-endpoint = <&amx1_out>;
+ };
+ };
+
+ xbar_amx2_in1_port: port@31 {
+ reg = <0x31>;
+
+ xbar_amx2_in1: endpoint {
+ remote-endpoint = <&amx2_in1>;
+ };
+ };
+
+ xbar_amx2_in2_port: port@32 {
+ reg = <0x32>;
+
+ xbar_amx2_in2: endpoint {
+ remote-endpoint = <&amx2_in2>;
+ };
+ };
+
+ xbar_amx2_in3_port: port@33 {
+ reg = <0x33>;
+
+ xbar_amx2_in3: endpoint {
+ remote-endpoint = <&amx2_in3>;
+ };
+ };
+
+ xbar_amx2_in4_port: port@34 {
+ reg = <0x34>;
+
+ xbar_amx2_in4: endpoint {
+ remote-endpoint = <&amx2_in4>;
+ };
+ };
+
+ port@35 {
+ reg = <0x35>;
+
+ xbar_amx2_out: endpoint {
+ remote-endpoint = <&amx2_out>;
+ };
+ };
+
+ xbar_amx3_in1_port: port@36 {
+ reg = <0x36>;
+
+ xbar_amx3_in1: endpoint {
+ remote-endpoint = <&amx3_in1>;
+ };
+ };
+
+ xbar_amx3_in2_port: port@37 {
+ reg = <0x37>;
+
+ xbar_amx3_in2: endpoint {
+ remote-endpoint = <&amx3_in2>;
+ };
+ };
+
+ xbar_amx3_in3_port: port@38 {
+ reg = <0x38>;
+
+ xbar_amx3_in3: endpoint {
+ remote-endpoint = <&amx3_in3>;
+ };
+ };
+
+ xbar_amx3_in4_port: port@39 {
+ reg = <0x39>;
+
+ xbar_amx3_in4: endpoint {
+ remote-endpoint = <&amx3_in4>;
+ };
+ };
+
+ port@3a {
+ reg = <0x3a>;
+
+ xbar_amx3_out: endpoint {
+ remote-endpoint = <&amx3_out>;
+ };
+ };
+
+ xbar_amx4_in1_port: port@3b {
+ reg = <0x3b>;
+
+ xbar_amx4_in1: endpoint {
+ remote-endpoint = <&amx4_in1>;
+ };
+ };
+
+ xbar_amx4_in2_port: port@3c {
+ reg = <0x3c>;
+
+ xbar_amx4_in2: endpoint {
+ remote-endpoint = <&amx4_in2>;
+ };
+ };
+
+ xbar_amx4_in3_port: port@3d {
+ reg = <0x3d>;
+
+ xbar_amx4_in3: endpoint {
+ remote-endpoint = <&amx4_in3>;
+ };
+ };
+
+ xbar_amx4_in4_port: port@3e {
+ reg = <0x3e>;
+
+ xbar_amx4_in4: endpoint {
+ remote-endpoint = <&amx4_in4>;
+ };
+ };
+
+ port@3f {
+ reg = <0x3f>;
+
+ xbar_amx4_out: endpoint {
+ remote-endpoint = <&amx4_out>;
+ };
+ };
+
+ xbar_adx1_in_port: port@40 {
+ reg = <0x40>;
+
+ xbar_adx1_in: endpoint {
+ remote-endpoint = <&adx1_in>;
+ };
+ };
+
+ port@41 {
+ reg = <0x41>;
+
+ xbar_adx1_out1: endpoint {
+ remote-endpoint = <&adx1_out1>;
+ };
+ };
+
+ port@42 {
+ reg = <0x42>;
+
+ xbar_adx1_out2: endpoint {
+ remote-endpoint = <&adx1_out2>;
+ };
+ };
+
+ port@43 {
+ reg = <0x43>;
+
+ xbar_adx1_out3: endpoint {
+ remote-endpoint = <&adx1_out3>;
+ };
+ };
+
+ port@44 {
+ reg = <0x44>;
+
+ xbar_adx1_out4: endpoint {
+ remote-endpoint = <&adx1_out4>;
+ };
+ };
+
+ xbar_adx2_in_port: port@45 {
+ reg = <0x45>;
+
+ xbar_adx2_in: endpoint {
+ remote-endpoint = <&adx2_in>;
+ };
+ };
+
+ port@46 {
+ reg = <0x46>;
+
+ xbar_adx2_out1: endpoint {
+ remote-endpoint = <&adx2_out1>;
+ };
+ };
+
+ port@47 {
+ reg = <0x47>;
+
+ xbar_adx2_out2: endpoint {
+ remote-endpoint = <&adx2_out2>;
+ };
+ };
+
+ port@48 {
+ reg = <0x48>;
+
+ xbar_adx2_out3: endpoint {
+ remote-endpoint = <&adx2_out3>;
+ };
+ };
+
+ port@49 {
+ reg = <0x49>;
+
+ xbar_adx2_out4: endpoint {
+ remote-endpoint = <&adx2_out4>;
+ };
+ };
+
+ xbar_adx3_in_port: port@4a {
+ reg = <0x4a>;
+
+ xbar_adx3_in: endpoint {
+ remote-endpoint = <&adx3_in>;
+ };
+ };
+
+ port@4b {
+ reg = <0x4b>;
+
+ xbar_adx3_out1: endpoint {
+ remote-endpoint = <&adx3_out1>;
+ };
+ };
+
+ port@4c {
+ reg = <0x4c>;
+
+ xbar_adx3_out2: endpoint {
+ remote-endpoint = <&adx3_out2>;
+ };
+ };
+
+ port@4d {
+ reg = <0x4d>;
+
+ xbar_adx3_out3: endpoint {
+ remote-endpoint = <&adx3_out3>;
+ };
+ };
+
+ port@4e {
+ reg = <0x4e>;
+
+ xbar_adx3_out4: endpoint {
+ remote-endpoint = <&adx3_out4>;
+ };
+ };
+
+ xbar_adx4_in_port: port@4f {
+ reg = <0x4f>;
+
+ xbar_adx4_in: endpoint {
+ remote-endpoint = <&adx4_in>;
+ };
+ };
+
+ port@50 {
+ reg = <0x50>;
+
+ xbar_adx4_out1: endpoint {
+ remote-endpoint = <&adx4_out1>;
+ };
+ };
+
+ port@51 {
+ reg = <0x51>;
+
+ xbar_adx4_out2: endpoint {
+ remote-endpoint = <&adx4_out2>;
+ };
+ };
+
+ port@52 {
+ reg = <0x52>;
+
+ xbar_adx4_out3: endpoint {
+ remote-endpoint = <&adx4_out3>;
+ };
+ };
+
+ port@53 {
+ reg = <0x53>;
+
+ xbar_adx4_out4: endpoint {
+ remote-endpoint = <&adx4_out4>;
+ };
+ };
+
+ xbar_mix_in1_port: port@54 {
+ reg = <0x54>;
+
+ xbar_mix_in1: endpoint {
+ remote-endpoint = <&mix_in1>;
+ };
+ };
+
+ xbar_mix_in2_port: port@55 {
+ reg = <0x55>;
+
+ xbar_mix_in2: endpoint {
+ remote-endpoint = <&mix_in2>;
+ };
+ };
+
+ xbar_mix_in3_port: port@56 {
+ reg = <0x56>;
+
+ xbar_mix_in3: endpoint {
+ remote-endpoint = <&mix_in3>;
+ };
+ };
+
+ xbar_mix_in4_port: port@57 {
+ reg = <0x57>;
+
+ xbar_mix_in4: endpoint {
+ remote-endpoint = <&mix_in4>;
+ };
+ };
+
+ xbar_mix_in5_port: port@58 {
+ reg = <0x58>;
+
+ xbar_mix_in5: endpoint {
+ remote-endpoint = <&mix_in5>;
+ };
+ };
+
+ xbar_mix_in6_port: port@59 {
+ reg = <0x59>;
+
+ xbar_mix_in6: endpoint {
+ remote-endpoint = <&mix_in6>;
+ };
+ };
+
+ xbar_mix_in7_port: port@5a {
+ reg = <0x5a>;
+
+ xbar_mix_in7: endpoint {
+ remote-endpoint = <&mix_in7>;
+ };
+ };
+
+ xbar_mix_in8_port: port@5b {
+ reg = <0x5b>;
+
+ xbar_mix_in8: endpoint {
+ remote-endpoint = <&mix_in8>;
+ };
+ };
+
+ xbar_mix_in9_port: port@5c {
+ reg = <0x5c>;
+
+ xbar_mix_in9: endpoint {
+ remote-endpoint = <&mix_in9>;
+ };
+ };
+
+ xbar_mix_in10_port: port@5d {
+ reg = <0x5d>;
+
+ xbar_mix_in10: endpoint {
+ remote-endpoint = <&mix_in10>;
+ };
+ };
+
+ port@5e {
+ reg = <0x5e>;
+
+ xbar_mix_out1: endpoint {
+ remote-endpoint = <&mix_out1>;
+ };
+ };
+
+ port@5f {
+ reg = <0x5f>;
+
+ xbar_mix_out2: endpoint {
+ remote-endpoint = <&mix_out2>;
+ };
+ };
+
+ port@60 {
+ reg = <0x60>;
+
+ xbar_mix_out3: endpoint {
+ remote-endpoint = <&mix_out3>;
+ };
+ };
+
+ port@61 {
+ reg = <0x61>;
+
+ xbar_mix_out4: endpoint {
+ remote-endpoint = <&mix_out4>;
+ };
+ };
+
+ port@62 {
+ reg = <0x62>;
+
+ xbar_mix_out5: endpoint {
+ remote-endpoint = <&mix_out5>;
+ };
+ };
+
+ xbar_asrc_in1_port: port@63 {
+ reg = <0x63>;
+
+ xbar_asrc_in1_ep: endpoint {
+ remote-endpoint = <&asrc_in1_ep>;
+ };
+ };
+
+ port@64 {
+ reg = <0x64>;
- tegra_amx3: amx@2903200 {
- compatible = "nvidia,tegra234-amx",
- "nvidia,tegra194-amx";
- reg = <0x0 0x2903200 0x0 0x100>;
- sound-name-prefix = "AMX3";
- status = "disabled";
- };
+ xbar_asrc_out1_ep: endpoint {
+ remote-endpoint = <&asrc_out1_ep>;
+ };
+ };
- tegra_amx4: amx@2903300 {
- compatible = "nvidia,tegra234-amx",
- "nvidia,tegra194-amx";
- reg = <0x0 0x2903300 0x0 0x100>;
- sound-name-prefix = "AMX4";
- status = "disabled";
- };
+ xbar_asrc_in2_port: port@65 {
+ reg = <0x65>;
- tegra_adx1: adx@2903800 {
- compatible = "nvidia,tegra234-adx",
- "nvidia,tegra210-adx";
- reg = <0x0 0x2903800 0x0 0x100>;
- sound-name-prefix = "ADX1";
- status = "disabled";
- };
+ xbar_asrc_in2_ep: endpoint {
+ remote-endpoint = <&asrc_in2_ep>;
+ };
+ };
- tegra_adx2: adx@2903900 {
- compatible = "nvidia,tegra234-adx",
- "nvidia,tegra210-adx";
- reg = <0x0 0x2903900 0x0 0x100>;
- sound-name-prefix = "ADX2";
- status = "disabled";
- };
+ port@66 {
+ reg = <0x66>;
- tegra_adx3: adx@2903a00 {
- compatible = "nvidia,tegra234-adx",
- "nvidia,tegra210-adx";
- reg = <0x0 0x2903a00 0x0 0x100>;
- sound-name-prefix = "ADX3";
- status = "disabled";
- };
+ xbar_asrc_out2_ep: endpoint {
+ remote-endpoint = <&asrc_out2_ep>;
+ };
+ };
- tegra_adx4: adx@2903b00 {
- compatible = "nvidia,tegra234-adx",
- "nvidia,tegra210-adx";
- reg = <0x0 0x2903b00 0x0 0x100>;
- sound-name-prefix = "ADX4";
- status = "disabled";
- };
+ xbar_asrc_in3_port: port@67 {
+ reg = <0x67>;
+ xbar_asrc_in3_ep: endpoint {
+ remote-endpoint = <&asrc_in3_ep>;
+ };
+ };
- tegra_dmic1: dmic@2904000 {
- compatible = "nvidia,tegra234-dmic",
- "nvidia,tegra210-dmic";
- reg = <0x0 0x2904000 0x0 0x100>;
- clocks = <&bpmp TEGRA234_CLK_DMIC1>;
- clock-names = "dmic";
- assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
- assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
- assigned-clock-rates = <3072000>;
- sound-name-prefix = "DMIC1";
- status = "disabled";
- };
+ port@68 {
+ reg = <0x68>;
- tegra_dmic2: dmic@2904100 {
- compatible = "nvidia,tegra234-dmic",
- "nvidia,tegra210-dmic";
- reg = <0x0 0x2904100 0x0 0x100>;
- clocks = <&bpmp TEGRA234_CLK_DMIC2>;
- clock-names = "dmic";
- assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
- assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
- assigned-clock-rates = <3072000>;
- sound-name-prefix = "DMIC2";
- status = "disabled";
- };
+ xbar_asrc_out3_ep: endpoint {
+ remote-endpoint = <&asrc_out3_ep>;
+ };
+ };
- tegra_dmic3: dmic@2904200 {
- compatible = "nvidia,tegra234-dmic",
- "nvidia,tegra210-dmic";
- reg = <0x0 0x2904200 0x0 0x100>;
- clocks = <&bpmp TEGRA234_CLK_DMIC3>;
- clock-names = "dmic";
- assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
- assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
- assigned-clock-rates = <3072000>;
- sound-name-prefix = "DMIC3";
- status = "disabled";
- };
+ xbar_asrc_in4_port: port@69 {
+ reg = <0x69>;
- tegra_dmic4: dmic@2904300 {
- compatible = "nvidia,tegra234-dmic",
- "nvidia,tegra210-dmic";
- reg = <0x0 0x2904300 0x0 0x100>;
- clocks = <&bpmp TEGRA234_CLK_DMIC4>;
- clock-names = "dmic";
- assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
- assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
- assigned-clock-rates = <3072000>;
- sound-name-prefix = "DMIC4";
- status = "disabled";
- };
+ xbar_asrc_in4_ep: endpoint {
+ remote-endpoint = <&asrc_in4_ep>;
+ };
+ };
- tegra_dspk1: dspk@2905000 {
- compatible = "nvidia,tegra234-dspk",
- "nvidia,tegra186-dspk";
- reg = <0x0 0x2905000 0x0 0x100>;
- clocks = <&bpmp TEGRA234_CLK_DSPK1>;
- clock-names = "dspk";
- assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
- assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
- assigned-clock-rates = <12288000>;
- sound-name-prefix = "DSPK1";
- status = "disabled";
- };
+ port@6a {
+ reg = <0x6a>;
- tegra_dspk2: dspk@2905100 {
- compatible = "nvidia,tegra234-dspk",
- "nvidia,tegra186-dspk";
- reg = <0x0 0x2905100 0x0 0x100>;
- clocks = <&bpmp TEGRA234_CLK_DSPK2>;
- clock-names = "dspk";
- assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
- assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
- assigned-clock-rates = <12288000>;
- sound-name-prefix = "DSPK2";
- status = "disabled";
- };
+ xbar_asrc_out4_ep: endpoint {
+ remote-endpoint = <&asrc_out4_ep>;
+ };
+ };
- tegra_ope1: processing-engine@2908000 {
- compatible = "nvidia,tegra234-ope",
- "nvidia,tegra210-ope";
- reg = <0x0 0x2908000 0x0 0x100>;
- sound-name-prefix = "OPE1";
- status = "disabled";
+ xbar_asrc_in5_port: port@6b {
+ reg = <0x6b>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ xbar_asrc_in5_ep: endpoint {
+ remote-endpoint = <&asrc_in5_ep>;
+ };
+ };
- equalizer@2908100 {
- compatible = "nvidia,tegra234-peq",
- "nvidia,tegra210-peq";
- reg = <0x0 0x2908100 0x0 0x100>;
+ port@6c {
+ reg = <0x6c>;
+
+ xbar_asrc_out5_ep: endpoint {
+ remote-endpoint = <&asrc_out5_ep>;
+ };
};
- dynamic-range-compressor@2908200 {
- compatible = "nvidia,tegra234-mbdrc",
- "nvidia,tegra210-mbdrc";
- reg = <0x0 0x2908200 0x0 0x200>;
+ xbar_asrc_in6_port: port@6d {
+ reg = <0x6d>;
+
+ xbar_asrc_in6_ep: endpoint {
+ remote-endpoint = <&asrc_in6_ep>;
+ };
};
- };
- tegra_mvc1: mvc@290a000 {
- compatible = "nvidia,tegra234-mvc",
- "nvidia,tegra210-mvc";
- reg = <0x0 0x290a000 0x0 0x200>;
- sound-name-prefix = "MVC1";
- status = "disabled";
- };
+ port@6e {
+ reg = <0x6e>;
- tegra_mvc2: mvc@290a200 {
- compatible = "nvidia,tegra234-mvc",
- "nvidia,tegra210-mvc";
- reg = <0x0 0x290a200 0x0 0x200>;
- sound-name-prefix = "MVC2";
- status = "disabled";
- };
+ xbar_asrc_out6_ep: endpoint {
+ remote-endpoint = <&asrc_out6_ep>;
+ };
+ };
- tegra_amixer: amixer@290bb00 {
- compatible = "nvidia,tegra234-amixer",
- "nvidia,tegra210-amixer";
- reg = <0x0 0x290bb00 0x0 0x800>;
- sound-name-prefix = "MIXER1";
- status = "disabled";
- };
+ xbar_asrc_in7_port: port@6f {
+ reg = <0x6f>;
- tegra_admaif: admaif@290f000 {
- compatible = "nvidia,tegra234-admaif",
- "nvidia,tegra186-admaif";
- reg = <0x0 0x0290f000 0x0 0x1000>;
- dmas = <&adma 1>, <&adma 1>,
- <&adma 2>, <&adma 2>,
- <&adma 3>, <&adma 3>,
- <&adma 4>, <&adma 4>,
- <&adma 5>, <&adma 5>,
- <&adma 6>, <&adma 6>,
- <&adma 7>, <&adma 7>,
- <&adma 8>, <&adma 8>,
- <&adma 9>, <&adma 9>,
- <&adma 10>, <&adma 10>,
- <&adma 11>, <&adma 11>,
- <&adma 12>, <&adma 12>,
- <&adma 13>, <&adma 13>,
- <&adma 14>, <&adma 14>,
- <&adma 15>, <&adma 15>,
- <&adma 16>, <&adma 16>,
- <&adma 17>, <&adma 17>,
- <&adma 18>, <&adma 18>,
- <&adma 19>, <&adma 19>,
- <&adma 20>, <&adma 20>;
- dma-names = "rx1", "tx1",
- "rx2", "tx2",
- "rx3", "tx3",
- "rx4", "tx4",
- "rx5", "tx5",
- "rx6", "tx6",
- "rx7", "tx7",
- "rx8", "tx8",
- "rx9", "tx9",
- "rx10", "tx10",
- "rx11", "tx11",
- "rx12", "tx12",
- "rx13", "tx13",
- "rx14", "tx14",
- "rx15", "tx15",
- "rx16", "tx16",
- "rx17", "tx17",
- "rx18", "tx18",
- "rx19", "tx19",
- "rx20", "tx20";
- interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>,
- <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>;
- interconnect-names = "dma-mem", "write";
- iommus = <&smmu_niso0 TEGRA234_SID_APE>;
- status = "disabled";
- };
+ xbar_asrc_in7_ep: endpoint {
+ remote-endpoint = <&asrc_in7_ep>;
+ };
+ };
- tegra_asrc: asrc@2910000 {
- compatible = "nvidia,tegra234-asrc",
- "nvidia,tegra186-asrc";
- reg = <0x0 0x2910000 0x0 0x2000>;
- sound-name-prefix = "ASRC1";
- status = "disabled";
+ xbar_ope1_in_port: port@70 {
+ reg = <0x70>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port@71 {
+ reg = <0x71>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
};
};
iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
status = "disabled";
+
+ snps,axi-config = <&mgbe0_axi_setup>;
+
+ mgbe0_axi_setup: stmmac-axi-config {
+ snps,blen = <256 128 64 32>;
+ snps,rd_osr_lmt = <63>;
+ snps,wr_osr_lmt = <63>;
+ };
};
ethernet@6900000 {
iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
status = "disabled";
+
+ snps,axi-config = <&mgbe1_axi_setup>;
+
+ mgbe1_axi_setup: stmmac-axi-config {
+ snps,blen = <256 128 64 32>;
+ snps,rd_osr_lmt = <63>;
+ snps,wr_osr_lmt = <63>;
+ };
};
ethernet@6a00000 {
iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
status = "disabled";
+
+ snps,axi-config = <&mgbe2_axi_setup>;
+
+ mgbe2_axi_setup: stmmac-axi-config {
+ snps,blen = <256 128 64 32>;
+ snps,rd_osr_lmt = <63>;
+ snps,wr_osr_lmt = <63>;
+ };
};
ethernet@6b00000 {
#include "apq8016-sbc.dts"
/ {
- camera_vdddo_1v8: camera-vdddo-1v8 {
+ camera_vdddo_1v8: regulator-camera-vdddo {
compatible = "regulator-fixed";
regulator-name = "camera_vdddo";
regulator-min-microvolt = <1800000>;
regulator-always-on;
};
- camera_vdda_2v8: camera-vdda-2v8 {
+ camera_vdda_2v8: regulator-camera-vdda {
compatible = "regulator-fixed";
regulator-name = "camera_vdda";
regulator-min-microvolt = <2800000>;
regulator-always-on;
};
- camera_vddd_1v5: camera-vddd-1v5 {
+ camera_vddd_1v5: regulator-camera-vddd {
compatible = "regulator-fixed";
regulator-name = "camera_vddd";
regulator-min-microvolt = <1500000>;
};
&cci_i2c0 {
- camera_rear@3b {
+ camera@3b {
compatible = "ovti,ov5640";
reg = <0x3b>;
compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
reg = <0x08af8800 0x400>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_EDGE_BOTH>,
+ <GIC_SPI 52 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq";
clocks = <&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_SNOC_USB_CLK>,
#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
#include <dt-bindings/clock/qcom,apss-ipq.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
#address-cells = <2>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
+ #cooling-cells = <2>;
};
CPU1: cpu@1 {
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
+ #cooling-cells = <2>;
};
CPU2: cpu@2 {
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
+ #cooling-cells = <2>;
};
CPU3: cpu@3 {
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
+ #cooling-cells = <2>;
};
L2_0: l2-cache {
clock-names = "core";
};
+ tsens: thermal-sensor@4a9000 {
+ compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens";
+ reg = <0x0 0x004a9000 0x0 0x1000>,
+ <0x0 0x004a8000 0x0 0x1000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "combined";
+ #qcom,sensors = <16>;
+ #thermal-sensor-cells = <1>;
+ };
+
cryptobam: dma-controller@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x00704000 0x0 0x20000>;
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<24000000>;
+
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy";
+
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
status = "disabled";
};
+ blsp1_i2c6: i2c@78ba000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x078ba000 0x0 0x600>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ clock-frequency = <400000>;
+ dmas = <&blsp_dma 22>, <&blsp_dma 23>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x07984000 0x0 0x1a000>;
<133330000>,
<24000000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
};
};
+ thermal-zones {
+ nss-top-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 4>;
+
+ trips {
+ nss-top-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nss-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 5>;
+
+ trips {
+ nss-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ wcss-phya0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 7>;
+
+ trips {
+ wcss-phya0-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ wcss-phya1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 8>;
+
+ trips {
+ wcss-phya1-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 13>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+
+ cpu_alert: cpu-passive {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ lpass-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 14>;
+
+ trips {
+ lpass-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddrss-top-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 15>;
+
+ trips {
+ ddrss-top-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
clocks = <&gcc GCC_MDIO_AHB_CLK>;
clock-names = "gcc_mdio_ahb_clk";
+ clock-frequency = <6250000>;
+
status = "disabled";
};
<133330000>,
<19200000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
power-domains = <&gcc USB0_GDSC>;
resets = <&gcc GCC_USB0_BCR>;
<133330000>,
<19200000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
power-domains = <&gcc USB1_GDSC>;
resets = <&gcc GCC_USB1_BCR>;
sdhc_1: mmc@7804000 {
compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
- reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
- reg-names = "hc", "cqhci";
+ reg = <0x07804000 0x1000>,
+ <0x07805000 0x1000>,
+ <0x07808000 0x2000>;
+ reg-names = "hc", "cqhci", "ice";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
- <&xo_board_clk>;
- clock-names = "iface", "core", "xo";
+ <&xo_board_clk>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface", "core", "xo", "ice";
non-removable;
+ supports-cqe;
status = "disabled";
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "msm8916-samsung-fortuna-common.dtsi"
+
+/ {
+ model = "Samsung Galaxy Grand Prime (SM-G530H)";
+ compatible = "samsung,fortuna3g", "qcom,msm8916";
+ chassis-type = "handset";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ aliases {
+ mmc0 = &sdhc_1; /* eMMC */
+ mmc1 = &sdhc_2; /* SD card */
+ serial0 = &blsp_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ reserved-memory {
+ /* Additional memory used by Samsung firmware modifications */
+ tz-apps@85a00000 {
+ reg = <0x0 0x85a00000 0x0 0x600000>;
+ no-map;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_keys_default>;
+ pinctrl-names = "default";
+
+ label = "GPIO Buttons";
+
+ button-volume-up {
+ label = "Volume Up";
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ button-home {
+ label = "Home";
+ gpios = <&tlmm 109 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOMEPAGE>;
+ };
+ };
+
+ haptic {
+ compatible = "regulator-haptic";
+ haptic-supply = <®_motor_vdd>;
+ min-microvolt = <3300000>;
+ max-microvolt = <3300000>;
+ };
+
+ reg_motor_vdd: regulator-motor-vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "motor_vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&motor_en_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp_i2c1 {
+ status = "okay";
+
+ muic: extcon@25 {
+ compatible = "siliconmitus,sm5502-muic";
+ reg = <0x25>;
+ interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&muic_int_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp_i2c4 {
+ status = "okay";
+
+ fuel-gauge@35 {
+ compatible = "richtek,rt5033-battery";
+ reg = <0x35>;
+
+ interrupts-extended = <&tlmm 121 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&fg_alert_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp_uart2 {
+ status = "okay";
+};
+
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5000000>;
+};
+
+&pm8916_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&pm8916_rpm_regulators {
+ pm8916_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&sound {
+ model = "msm8916-1mic";
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+};
+
+&usb {
+ extcon = <&muic>, <&muic>;
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&muic>;
+};
+
+&venus {
+ status = "okay";
+};
+
+&venus_mem {
+ status = "okay";
+};
+
+&wcnss {
+ status = "okay";
+};
+
+&wcnss_iris {
+ compatible = "qcom,wcn3620";
+};
+
+&wcnss_mem {
+ status = "okay";
+};
+
+&tlmm {
+ fg_alert_default: fg-alert-default-state {
+ pins = "gpio121";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ gpio_keys_default: gpio-keys-default-state {
+ pins = "gpio107", "gpio109";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ motor_en_default: motor-en-default-state {
+ pins = "gpio72";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ muic_int_default: muic-int-default-state {
+ pins = "gpio12";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc2_cd_default: sdc2-cd-default-state {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "msm8916-samsung-fortuna-common.dtsi"
+
+/ {
+ model = "Samsung Galaxy Grand Prime (SM-G530W)";
+ compatible = "samsung,gprimeltecan", "qcom,msm8916";
+ chassis-type = "handset";
+
+ reserved-memory {
+ /* Firmware for gprimeltecan needs more space */
+ /delete-node/ tz-apps@85a00000;
+
+ /* Additional memory used by Samsung firmware modifications */
+ tz-apps@85500000 {
+ reg = <0x0 0x85500000 0x0 0xb00000>;
+ no-map;
+ };
+ };
+};
+
+&mpss_mem {
+ /* Firmware for gprimeltecan needs more space */
+ reg = <0x0 0x86800000 0x0 0x5400000>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "msm8916-samsung-fortuna-common.dtsi"
+
+/ {
+ model = "Samsung Galaxy Grand Prime (SM-G530FZ)";
+ compatible = "samsung,grandprimelte", "qcom,msm8916";
+ chassis-type = "handset";
+};
+
+&mpss_mem {
+ /* Firmware for grandprimelte needs more space */
+ reg = <0x0 0x86800000 0x0 0x5400000>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "msm8916-samsung-fortuna-common.dtsi"
+
+/* SM5504 MUIC instead of SM5502 */
+/delete-node/ &muic;
+
+&blsp_i2c1 {
+ muic: extcon@14 {
+ compatible = "siliconmitus,sm5504-muic";
+ reg = <0x14>;
+ interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&muic_int_default>;
+ pinctrl-names = "default";
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "msm8916-samsung-rossa-common.dtsi"
+
+/ {
+ model = "Samsung Galaxy Core Prime LTE";
+ compatible = "samsung,rossa", "qcom,msm8916";
+ chassis-type = "handset";
+};
+
+&mpss_mem {
+ /* Firmware for rossa needs more space */
+ reg = <0x0 0x86800000 0x0 0x5800000>;
+};
power-domains = <&gcc OXILI_GDSC>;
operating-points-v2 = <&gpu_opp_table>;
iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+ #cooling-cells = <2>;
+
status = "disabled";
gpu_opp_table: opp-table {
thermal-sensors = <&tsens 2>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
gpu_alert0: trip-point0 {
temperature = <75000>;
power-domains = <&gcc OXILI_GDSC>;
operating-points-v2 = <&opp_table>;
iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+ #cooling-cells = <2>;
+
status = "disabled";
opp_table: opp-table {
thermal-sensors = <&tsens 3>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
gpu_alert0: trip-point0 {
temperature = <75000>;
type = "passive";
};
- gpu_crit: gpu_crit {
+ gpu_crit: gpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
"vsync",
"core";
+ resets = <&gcc GCC_MDSS_BCR>;
+
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
};
+ gpu: gpu@1c00000 {
+ compatible = "qcom,adreno-506.0", "qcom,adreno";
+ reg = <0x01c00000 0x40000>;
+ reg-names = "kgsl_3d0_reg_memory";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
+ <&gcc GCC_OXILI_AHB_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&gcc GCC_BIMC_GPU_CLK>,
+ <&gcc GCC_OXILI_TIMER_CLK>,
+ <&gcc GCC_OXILI_AON_CLK>;
+ clock-names = "core",
+ "iface",
+ "mem_iface",
+ "alt_mem_iface",
+ "rbbmtimer",
+ "alwayson";
+ power-domains = <&gcc OXILI_GX_GDSC>;
+
+ iommus = <&gpu_iommu 0>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ zap-shader {
+ memory-region = <&zap_shader_region>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ opp-supported-hw = <0xff>;
+ required-opps = <&rpmpd_opp_min_svs>;
+ };
+
+ opp-133300000 {
+ opp-hz = /bits/ 64 <133300000>;
+ opp-supported-hw = <0xff>;
+ required-opps = <&rpmpd_opp_min_svs>;
+ };
+
+ opp-216000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-supported-hw = <0xff>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ opp-supported-hw = <0xff>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-supported-hw = <0xff>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ };
+
+ opp-510000000 {
+ opp-hz = /bits/ 64 <510000000>;
+ opp-supported-hw = <0xff>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+
+ opp-560000000 {
+ opp-hz = /bits/ 64 <560000000>;
+ opp-supported-hw = <0xff>;
+ required-opps = <&rpmpd_opp_nom_plus>;
+ };
+
+ /*
+ * This opp is only available on msm8953 and
+ * sdm632, the max for sdm450 is 600MHz.
+ */
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-supported-hw = <0xff>;
+ required-opps = <&rpmpd_opp_turbo>;
+ };
+ };
+ };
+
+ gpu_iommu: iommu@1c48000 {
+ compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v2";
+ ranges = <0 0x01c48000 0x8000>;
+
+ clocks = <&gcc GCC_OXILI_AHB_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>;
+ clock-names = "iface", "bus";
+
+ power-domains = <&gcc OXILI_CX_GDSC>;
+
+ qcom,iommu-secure-id = <18>;
+
+ #address-cells = <1>;
+ #iommu-cells = <1>;
+ #size-cells = <1>;
+
+ /* gfx3d_user */
+ iommu-ctx@0 {
+ compatible = "qcom,msm-iommu-v2-ns";
+ reg = <0x0000 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* gfx3d_secure */
+ iommu-ctx@2000 {
+ compatible = "qcom,msm-iommu-v2-sec";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
apps_iommu: iommu@1e20000 {
compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
ranges = <0 0x01e20000 0x20000>;
#size-cells = <1>;
ranges;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
};
};
};
+
+ gpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens0 15>;
+
+ trips {
+ gpu_alert: trip-point0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu_crit: crit {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
};
timer {
&blsp2_i2c1 {
status = "okay";
- sideinteraction: ad7147_captouch@2c {
+ sideinteraction: touch@2c {
compatible = "ad,ad7147_captouch";
reg = <0x2c>;
pmsg-size = <0x80000>;
};
- fb_region: fb_region@40000000 {
+ fb_region: fb@40000000 {
reg = <0 0x40000000 0 0x1000000>;
no-map;
};
#size-cells = <2>;
ranges;
- dfps_data_mem: dfps_data_mem@3400000 {
+ dfps_data_mem: dfps-data@3400000 {
reg = <0 0x03400000 0 0x1000>;
no-map;
};
no-map;
};
- smem_mem: smem_region@6a00000 {
+ smem_mem: smem@6a00000 {
reg = <0 0x06a00000 0 0x200000>;
no-map;
};
#address-cells = <1>;
#size-cells = <1>;
- qusb2p_hstx_trim: hstx_trim@24e {
+ qusb2p_hstx_trim: hstx-trim@24e {
reg = <0x24e 0x2>;
bits = <5 4>;
};
- qusb2s_hstx_trim: hstx_trim@24f {
+ qusb2s_hstx_trim: hstx-trim@24f {
reg = <0x24f 0x1>;
bits = <1 4>;
};
<0 0>,
<0 0>,
<150000000 300000000>,
- <0 0>,
+ <75000000 150000000>,
<0 0>,
<0 0>,
<0 0>,
compatible = "qcom,msm8996-qmp-ufs-phy";
reg = <0x00627000 0x1000>;
- clocks = <&gcc GCC_UFS_CLKREF_CLK>;
- clock-names = "ref";
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>;
+ clock-names = "ref", "qref";
resets = <&ufshc 0>;
reset-names = "ufsphy";
#size-cells = <1>;
ranges;
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "hs_phy_irq";
clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
<&gcc GCC_USB20_MASTER_CLK>,
compatible = "qcom,msm8998-qmp-ufs-phy";
reg = <0x01da7000 0x1000>;
- clock-names =
- "ref",
- "ref_aux";
- clocks =
- <&gcc GCC_UFS_CLKREF_CLK>,
- <&gcc GCC_UFS_PHY_AUX_CLK>;
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>,
+ <&gcc GCC_UFS_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_CLKREF_CLK>;
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
reset-names = "ufsphy";
resets = <&ufshc 0>;
reg = <0x01f60000 0x20000>;
};
+ tcsr_regs_2: syscon@1fc0000 {
+ compatible = "qcom,msm8998-tcsr", "syscon";
+ reg = <0x01fc0000 0x26000>;
+ };
+
tlmm: pinctrl@3400000 {
compatible = "qcom,msm8998-pinctrl";
reg = <0x03400000 0xc00000>;
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <120000000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
power-domains = <&gcc USB_30_GDSC>;
reset-names = "phy",
"phy_phy";
+ qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
+
status = "disabled";
};
compatible = "qcom,pm8916-pon";
reg = <0x800>;
- pm2250_pwrkey: pwrkey {
+ pm4125_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts-extended = <&spmi_bus 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
bias-pull-up;
};
- pm2250_resin: resin {
+ pm4125_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts-extended = <&spmi_bus 0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
};
};
+ pm4125_vbus: usb-vbus-regulator@1100 {
+ compatible = "qcom,pm4125-vbus-reg", "qcom,pm8150b-vbus-reg";
+ reg = <0x1100>;
+ status = "disabled";
+ };
+
+ pm4125_typec: typec@1500 {
+ compatible = "qcom,pm4125-typec", "qcom,pmi632-typec";
+ reg = <0x1500>;
+ interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x15 0x03 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x15 0x04 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x15 0x05 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x15 0x06 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x15 0x07 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "or-rid-detect-change",
+ "vpd-detect",
+ "cc-state-change",
+ "vconn-oc",
+ "vbus-change",
+ "attach-detach",
+ "legacy-cable-detect",
+ "try-snk-src-detect";
+ vdd-vbus-supply = <&pm4125_vbus>;
+
+ status = "disabled";
+ };
+
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
interrupts-extended = <&spmi_bus 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
- pm2250_gpios: gpio@c000 {
+ pm4125_gpios: gpio@c000 {
compatible = "qcom,pm2250-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
- gpio-ranges = <&pm2250_gpios 0 0 10>;
+ gpio-ranges = <&pm4125_gpios 0 0 10>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
+ pm6150_vbus: usb-vbus-regulator@1100 {
+ compatible = "qcom,pm6150-vbus-reg,
+ qcom,pm8150b-vbus-reg";
+ reg = <0x1100>;
+ status = "disabled";
+ };
+
+ pm6150_typec: typec@1500 {
+ compatible = "qcom,pm6150-typec,
+ qcom,pm8150b-typec";
+ reg = <0x1500>, <0x1700>;
+ interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x15 0x03 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x15 0x04 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x15 0x05 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x15 0x06 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x15 0x07 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x00 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x01 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x02 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x03 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x04 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x05 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x06 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x07 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "or-rid-detect-change",
+ "vpd-detect",
+ "cc-state-change",
+ "vconn-oc",
+ "vbus-change",
+ "attach-detach",
+ "legacy-cable-detect",
+ "try-snk-src-detect",
+ "sig-tx",
+ "sig-rx",
+ "msg-tx",
+ "msg-rx",
+ "msg-tx-failed",
+ "msg-tx-discarded",
+ "msg-rx-discarded",
+ "fr-swap";
+ status = "disabled";
+ };
+
pm6150_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
#address-cells = <1>;
#size-cells = <0>;
+ pmi632_vbus: usb-vbus-regulator@1100 {
+ compatible = "qcom,pmi632-vbus-reg", "qcom,pm8150b-vbus-reg";
+ reg = <0x1100>;
+ status = "disabled";
+ };
+
+ pmi632_typec: typec@1500 {
+ compatible = "qcom,pmi632-typec";
+ reg = <0x1500>;
+ interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x03 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x15 0x04 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x05 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x06 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x15 0x07 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "or-rid-detect-change",
+ "vpd-detect",
+ "cc-state-change",
+ "vconn-oc",
+ "vbus-change",
+ "attach-detach",
+ "legacy-cable-detect",
+ "try-snk-src-detect";
+ vdd-vbus-supply = <&pmi632_vbus>;
+
+ status = "disabled";
+ };
+
pmi632_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
status = "disabled";
};
+ pmi632_pbs_client3: pbs@7400 {
+ compatible = "qcom,pmi632-pbs", "qcom,pbs";
+ reg = <0x7400>;
+ };
+
pmi632_sdam_7: nvram@b600 {
compatible = "qcom,spmi-sdam";
reg = <0xb600>;
pmi632_lpg: pwm {
compatible = "qcom,pmi632-lpg";
+ nvmem = <&pmi632_sdam_7>;
+ nvmem-names = "lpg_chan_sdam";
+ qcom,pbs = <&pmi632_pbs_client3>;
+
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <2>;
#hwlock-cells = <1>;
};
+ tcsr_regs: syscon@3c0000 {
+ compatible = "qcom,qcm2290-tcsr", "syscon";
+ reg = <0x0 0x003c0000 0x0 0x40000>;
+ };
+
tlmm: pinctrl@500000 {
compatible = "qcom,qcm2290-tlmm";
reg = <0x0 0x00500000 0x0 0x300000>;
#phy-cells = <0>;
+ qcom,tcsr-reg = <&tcsr_regs 0xb244>;
+
status = "disabled";
};
};
};
+ pmic-glink {
+ compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+ };
+ };
+ };
+
reserved-memory {
cont_splash_mem: cont-splash@e1000000 {
reg = <0x0 0xe1000000 0x0 0x2300000>;
no-map;
};
+ removed_mem: removed@c0000000 {
+ reg = <0x0 0xc0000000 0x0 0x5100000>;
+ no-map;
+ };
+
rmtfs_mem: memory@f8500000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0xf8500000 0x0 0x600000>;
};
&usb_1_dwc3 {
- dr_mode = "peripheral";
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&pmic_glink_ss_in>;
};
&usb_1_hsphy {
status = "okay";
};
+&venus {
+ firmware-name = "qcom/qcm6490/fairphone5/venus.mbn";
+ status = "okay";
+};
+
&wifi {
qcom,ath11k-calibration-variant = "Fairphone_5";
status = "okay";
/dts-v1/;
+/* PM7250B is configured to use SID8/9 */
+#define PM7250B_SID 8
+#define PM7250B_SID1 9
+
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7280.dtsi"
+#include "pm7250b.dtsi"
#include "pm7325.dtsi"
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
no-map;
};
- trusted_apps_mem: trusted_apps@c1800000 {
+ trusted_apps_mem: trusted-apps@c1800000 {
reg = <0x0 0xc1800000 0x0 0x1c00000>;
no-map;
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <4350000>;
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
};
};
};
};
+&pm8350c_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "qusb2_phy";
+
status = "disabled";
usb3_dwc3: usb@7580000 {
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_USB_HS_SYSTEM_CLK>;
assigned-clock-rates = <19200000>, <133333333>;
+
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "qusb2_phy";
+
status = "disabled";
usb@78c0000 {
no-map;
};
- trusted_apps_mem: trusted_apps@c1800000 {
+ trusted_apps_mem: trusted-apps@c1800000 {
reg = <0x0 0xc1800000 0x0 0x1c00000>;
no-map;
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <4350000>;
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
};
};
};
};
+&gcc {
+ protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
+ <GCC_MSS_CFG_AHB_CLK>,
+ <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
+ <GCC_MSS_OFFLINE_AXI_CLK>,
+ <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+ <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+ <GCC_MSS_SNOC_AXI_CLK>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_SEC_CTRL_CLK_SRC>,
+ <GCC_WPSS_AHB_BDG_MST_CLK>,
+ <GCC_WPSS_AHB_CLK>,
+ <GCC_WPSS_RSCP_CLK>;
+};
+
&qupv3_id_0 {
status = "okay";
};
#include <dt-bindings/leds/common.h>
#include "qcm2290.dtsi"
-#include "pm2250.dtsi"
+#include "pm4125.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Robotics RB1";
};
};
+&CPU_PD0 {
+ /delete-property/ power-domains;
+};
+
+&CPU_PD1 {
+ /delete-property/ power-domains;
+};
+
+&CPU_PD2 {
+ /delete-property/ power-domains;
+};
+
+&CPU_PD3 {
+ /delete-property/ power-domains;
+};
+
+/delete-node/ &CLUSTER_PD;
+
&gpi_dma0 {
status = "okay";
};
};
&mdss_dsi0 {
- vdda-supply = <&pm2250_l5>;
+ vdda-supply = <&pm4125_l5>;
status = "okay";
};
status = "okay";
};
-&pm2250_resin {
+&pm4125_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
compatible = "qcom,rpm-pm2250-regulators";
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
- vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm2250_s3>;
+ vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm4125_s3>;
vdd_l4_l17_l18_l19_l20_l21_l22-supply = <&vph_pwr>;
- vdd_l13_l14_l15_l16-supply = <&pm2250_s4>;
+ vdd_l13_l14_l15_l16-supply = <&pm4125_s4>;
/*
* S1 - VDD_APC
* S2 - VDD_CX
*/
- pm2250_s3: s3 {
+ pm4125_s3: s3 {
/* 0.4V-1.6625V -> 1.3V (Power tree requirements) */
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
regulator-boot-on;
};
- pm2250_s4: s4 {
+ pm4125_s4: s4 {
/* 1.2V-2.35V -> 2.05V (Power tree requirements) */
regulator-min-microvolt = <2072000>;
regulator-max-microvolt = <2072000>;
/* L1 - VDD_MX */
- pm2250_l2: l2 {
+ pm4125_l2: l2 {
/* LPDDR4X VDD2 */
regulator-min-microvolt = <1136000>;
regulator-max-microvolt = <1136000>;
regulator-boot-on;
};
- pm2250_l3: l3 {
+ pm4125_l3: l3 {
/* LPDDR4X VDDQ */
regulator-min-microvolt = <616000>;
regulator-max-microvolt = <616000>;
regulator-boot-on;
};
- pm2250_l4: l4 {
+ pm4125_l4: l4 {
/* max = 3.05V -> max = 2.7 to disable 3V signaling (SDHCI2) */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2700000>;
regulator-allow-set-load;
};
- pm2250_l5: l5 {
+ pm4125_l5: l5 {
/* CSI/DSI */
regulator-min-microvolt = <1232000>;
regulator-max-microvolt = <1232000>;
regulator-boot-on;
};
- pm2250_l6: l6 {
+ pm4125_l6: l6 {
/* DRAM PLL */
regulator-min-microvolt = <928000>;
regulator-max-microvolt = <928000>;
regulator-boot-on;
};
- pm2250_l7: l7 {
+ pm4125_l7: l7 {
/* Wi-Fi CX/MX */
regulator-min-microvolt = <664000>;
regulator-max-microvolt = <664000>;
* L9 - VDD_LPI_MX
*/
- pm2250_l10: l10 {
+ pm4125_l10: l10 {
/* Wi-Fi RFA */
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1304000>;
};
- pm2250_l11: l11 {
+ pm4125_l11: l11 {
/* GPS RF1 */
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
};
- pm2250_l12: l12 {
+ pm4125_l12: l12 {
/* USB PHYs */
regulator-min-microvolt = <928000>;
regulator-max-microvolt = <928000>;
regulator-boot-on;
};
- pm2250_l13: l13 {
+ pm4125_l13: l13 {
/* USB/QFPROM/PLLs */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
- pm2250_l14: l14 {
+ pm4125_l14: l14 {
/* SDHCI1 VQMMC */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
- pm2250_l15: l15 {
+ pm4125_l15: l15 {
/* WCD/DSI/BT VDDIO */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
- pm2250_l16: l16 {
+ pm4125_l16: l16 {
/* GPS RF2 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
- pm2250_l17: l17 {
+ pm4125_l17: l17 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
- pm2250_l18: l18 {
+ pm4125_l18: l18 {
/* VDD_PXn */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- pm2250_l19: l19 {
+ pm4125_l19: l19 {
/* VDD_PXn */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- pm2250_l20: l20 {
+ pm4125_l20: l20 {
/* SDHCI1 VMMC */
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3600000>;
regulator-allow-set-load;
};
- pm2250_l21: l21 {
+ pm4125_l21: l21 {
/* SDHCI2 VMMC */
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
- pm2250_l22: l22 {
+ pm4125_l22: l22 {
/* Wi-Fi */
regulator-min-microvolt = <3312000>;
regulator-max-microvolt = <3312000>;
};
&sdhc_1 {
- vmmc-supply = <&pm2250_l20>;
- vqmmc-supply = <&pm2250_l14>;
+ vmmc-supply = <&pm4125_l20>;
+ vqmmc-supply = <&pm4125_l14>;
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
pinctrl-names = "default", "sleep";
};
&sdhc_2 {
- vmmc-supply = <&pm2250_l21>;
- vqmmc-supply = <&pm2250_l4>;
+ vmmc-supply = <&pm4125_l21>;
+ vqmmc-supply = <&pm4125_l4>;
cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&sdc2_state_on &sd_det_in_on>;
pinctrl-1 = <&sdc2_state_off &sd_det_in_off>;
};
&usb_qmpphy {
- vdda-phy-supply = <&pm2250_l12>;
- vdda-pll-supply = <&pm2250_l13>;
+ vdda-phy-supply = <&pm4125_l12>;
+ vdda-pll-supply = <&pm4125_l13>;
status = "okay";
};
};
&usb_hsphy {
- vdd-supply = <&pm2250_l12>;
- vdda-pll-supply = <&pm2250_l13>;
- vdda-phy-dpdm-supply = <&pm2250_l21>;
+ vdd-supply = <&pm4125_l12>;
+ vdda-pll-supply = <&pm4125_l13>;
+ vdda-phy-dpdm-supply = <&pm4125_l21>;
status = "okay";
};
&wifi {
- vdd-0.8-cx-mx-supply = <&pm2250_l7>;
- vdd-1.8-xo-supply = <&pm2250_l13>;
- vdd-1.3-rfa-supply = <&pm2250_l10>;
- vdd-3.3-ch0-supply = <&pm2250_l22>;
+ vdd-0.8-cx-mx-supply = <&pm4125_l7>;
+ vdd-1.8-xo-supply = <&pm4125_l13>;
+ vdd-1.3-rfa-supply = <&pm4125_l10>;
+ vdd-3.3-ch0-supply = <&pm4125_l22>;
qcom,ath10k-calibration-variant = "Thundercomm_RB1";
status = "okay";
};
/dts-v1/;
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/usb/pd.h>
#include "sm4250.dtsi"
#include "pm6125.dtsi"
+#include "pmi632.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QRB4210 RB2";
};
};
+&pmi632_typec {
+ status = "okay";
+
+ connector {
+ compatible = "usb-c-connector";
+
+ power-role = "dual";
+ data-role = "dual";
+ self-powered;
+
+ typec-power-opmode = "default";
+ pd-disable;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ pmi632_hs_in: endpoint {
+ remote-endpoint = <&usb_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ pmi632_ss_in: endpoint {
+ remote-endpoint = <&usb_qmpphy_out>;
+ };
+ };
+ };
+ };
+};
+
+&pmi632_vbus {
+ regulator-min-microamp = <500000>;
+ regulator-max-microamp = <3000000>;
+ status = "okay";
+};
+
&pon_pwrkey {
status = "okay";
};
status = "okay";
};
-&usb_dwc3 {
- maximum-speed = "super-speed";
+&usb_dwc3_hs {
+ remote-endpoint = <&pmi632_hs_in>;
};
&usb_hsphy {
status = "okay";
};
+&usb_qmpphy_out {
+ remote-endpoint = <&pmi632_ss_in>;
+};
+
&wifi {
vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>;
vdd-1.8-xo-supply = <&vreg_l16a_1p3>;
};
};
+&pmm8155au_1_gpios {
+ pmm8155au_1_sdc2_cd: sdc2-cd-default-state {
+ pins = "gpio4";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+};
+
&qupv3_id_1 {
status = "okay";
};
&sdhc_2 {
status = "okay";
- cd-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&pmm8155au_1_gpios 4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdc2_on>;
- pinctrl-1 = <&sdc2_off>;
+ pinctrl-0 = <&sdc2_on &pmm8155au_1_sdc2_cd>;
+ pinctrl-1 = <&sdc2_off &pmm8155au_1_sdc2_cd>;
vqmmc-supply = <&vreg_l13c_2p96>; /* IO line power */
vmmc-supply = <&vreg_l17a_2p96>; /* Card power line */
bus-width = <4>;
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
-
- sd-cd-pins {
- pins = "gpio96";
- function = "gpio";
- bias-pull-up; /* pull up */
- drive-strength = <2>; /* 2 MA */
- };
};
sdc2_off: sdc2-off-state {
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
-
- sd-cd-pins {
- pins = "gpio96";
- function = "gpio";
- bias-pull-up; /* pull up */
- drive-strength = <2>; /* 2 MA */
- };
};
usb2phy_ac_en1_default: usb2phy-ac-en1-default-state {
};
};
};
+
+ reserved-memory {
+ gpu_mem: gpu-mem@8bf00000 {
+ reg = <0 0x8bf00000 0 0x2000>;
+ no-map;
+ };
+ };
};
&apps_rsc {
status = "okay";
};
+&i2c12 {
+ pinctrl-0 = <&qup1_i2c4_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ vdd_gfx: regulator@39 {
+ compatible = "maxim,max20411";
+ reg = <0x39>;
+
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+
+ enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&max20411_en>;
+ pinctrl-names = "default";
+ };
+};
+
+&gpucc {
+ vdd-gfx-supply = <&vdd_gfx>;
+ status = "okay";
+};
+
+&gmu {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ memory-region = <&gpu_mem>;
+ firmware-name = "qcom/sa8295p/a690_zap.mbn";
+ };
+};
+
+&gpu_smmu {
+ status = "okay";
+};
+
&mdss0 {
status = "okay";
};
status = "okay";
};
+&qup1 {
+ status = "okay";
+};
+
&qup2 {
status = "okay";
};
/* PINCTRL */
+&pmm8540a_gpios {
+ max20411_en: max20411-en-state {
+ pins = "gpio2";
+ function = "normal";
+ output-enable;
+ };
+};
+
&tlmm {
pcie2a_default: pcie2a-default-state {
clkreq-n-pins {
bias-pull-up;
};
};
+
+ qup1_i2c4_state: qup1-i2c4-state {
+ pins = "gpio0", "gpio1";
+ function = "qup12";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
};
pinctrl-names = "default";
pinctrl-0 = <&pcie2a_default>;
- status = "okay";
+ status = "disabled";
};
&pcie2a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
- status = "okay";
+ status = "disabled";
};
&pcie3a {
};
&gpucc {
+ /* SA8295P and SA8540P doesn't provide gfx.lvl */
+ /delete-property/ power-domains;
+
status = "disabled";
};
no-map;
};
+ ddr_training_checksum: ddr-training-checksum@908c0000 {
+ reg = <0x0 0x908c0000 0x0 0x1000>;
+ no-map;
+ };
+
reserved_mem: reserved@908f0000 {
- reg = <0x0 0x908f0000 0x0 0xf000>;
+ reg = <0x0 0x908f0000 0x0 0xe000>;
no-map;
};
- secdata_apss_mem: secdata-apss@908ff000 {
- reg = <0x0 0x908ff000 0x0 0x1000>;
+ secdata_apss_mem: secdata-apss@908fe000 {
+ reg = <0x0 0x908fe000 0x0 0x2000>;
no-map;
};
hwlocks = <&tcsr_mutex 3>;
};
- cpucp_fw_mem: cpucp-fw@90b00000 {
- reg = <0x0 0x90b00000 0x0 0x100000>;
+ tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
+ reg = <0x0 0x90c00000 0x0 0x100000>;
+ no-map;
+ };
+
+ sail_mailbox_mem: sail-ss@90d00000 {
+ reg = <0x0 0x90d00000 0x0 0x100000>;
+ no-map;
+ };
+
+ sail_ota_mem: sail-ss@90e00000 {
+ reg = <0x0 0x90e00000 0x0 0x300000>;
+ no-map;
+ };
+
+ aoss_backup_mem: aoss-backup@91b00000 {
+ reg = <0x0 0x91b00000 0x0 0x40000>;
+ no-map;
+ };
+
+ cpucp_backup_mem: cpucp-backup@91b40000 {
+ reg = <0x0 0x91b40000 0x0 0x40000>;
+ no-map;
+ };
+
+ tz_config_backup_mem: tz-config-backup@91b80000 {
+ reg = <0x0 0x91b80000 0x0 0x10000>;
+ no-map;
+ };
+
+ ddr_training_data_mem: ddr-training-data@91b90000 {
+ reg = <0x0 0x91b90000 0x0 0x10000>;
+ no-map;
+ };
+
+ cdt_data_backup_mem: cdt-data-backup@91ba0000 {
+ reg = <0x0 0x91ba0000 0x0 0x1000>;
no-map;
};
no-map;
};
+ audio_mdf_mem: audio-mdf-region@ae000000 {
+ reg = <0x0 0xae000000 0x0 0x1000000>;
+ no-map;
+ };
+
+ firmware_mem: firmware-region@b0000000 {
+ reg = <0x0 0xb0000000 0x0 0x800000>;
+ no-map;
+ };
+
hyptz_reserved_mem: hyptz-reserved@beb00000 {
reg = <0x0 0xbeb00000 0x0 0x11500000>;
no-map;
};
- tz_stat_mem: tz-stat@d0000000 {
- reg = <0x0 0xd0000000 0x0 0x100000>;
+ scmi_mem: scmi-region@d0000000 {
+ reg = <0x0 0xd0000000 0x0 0x40000>;
+ no-map;
+ };
+
+ firmware_logs_mem: firmware-logs@d0040000 {
+ reg = <0x0 0xd0040000 0x0 0x10000>;
+ no-map;
+ };
+
+ firmware_audio_mem: firmware-audio@d0050000 {
+ reg = <0x0 0xd0050000 0x0 0x4000>;
+ no-map;
+ };
+
+ firmware_reserved_mem: firmware-reserved@d0054000 {
+ reg = <0x0 0xd0054000 0x0 0x9c000>;
+ no-map;
+ };
+
+ firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
+ reg = <0x0 0xd00f0000 0x0 0x10000>;
no-map;
};
no-map;
};
- trusted_apps_mem: trusted-apps@d1800000 {
- reg = <0x0 0xd1800000 0x0 0x3900000>;
+ deepsleep_backup_mem: deepsleep-backup@d1800000 {
+ reg = <0x0 0xd1800000 0x0 0x100000>;
+ no-map;
+ };
+
+ trusted_apps_mem: trusted-apps@d1900000 {
+ reg = <0x0 0xd1900000 0x0 0x3800000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat@db100000 {
+ reg = <0x0 0xdb100000 0x0 0x100000>;
+ no-map;
+ };
+
+ cpucp_fw_mem: cpucp-fw@db200000 {
+ reg = <0x0 0xdb200000 0x0 0x100000>;
no-map;
};
};
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
+ "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc 7 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
+ "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pwr_event",
+ "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
<0x0 0x23016000 0x0 0x100>;
reg-names = "stmmaceth", "rgmii";
- interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "sfty";
clocks = <&gcc GCC_EMAC1_AXI_CLK>,
<&gcc GCC_EMAC1_SLV_AHB_CLK>,
<0x0 0x23056000 0x0 0x100>;
reg-names = "stmmaceth", "rgmii";
- interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "sfty";
clocks = <&gcc GCC_EMAC0_AXI_CLK>,
<&gcc GCC_EMAC0_SLV_AHB_CLK>,
pinctrl-names = "default";
pinctrl-0 = <&ap_ec_int_l>;
spi-max-frequency = <3000000>;
+ wakeup-source;
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
vddrf-supply = <&pp1300_l2c>;
vddch0-supply = <&pp3300_l10c>;
max-speed = <3200000>;
+
+ qcom,local-bd-address-broken;
};
};
bits = <1 3>;
};
- gpu_speed_bin: gpu_speed_bin@1d2 {
+ gpu_speed_bin: gpu-speed-bin@1d2 {
reg = <0x1d2 0x2>;
bits = <5 8>;
};
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,sc7180-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0 0x01d84000 0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <1>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
+ iommus = <&apps_smmu 0xa0 0x0>;
+
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk";
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
+ freq-table-hz = <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ufs-ddr", "cpu-ufs";
+
+ qcom,ice = <&ice>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sc7180-qmp-ufs-phy",
+ "qcom,sm7150-qmp-ufs-phy";
+ reg = <0 0x01d87000 0 0x1000>;
+ clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ clock-names = "ref", "ref_aux";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ ice: crypto@1d90000 {
+ compatible = "qcom,sc7180-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0 0x01d90000 0 0x8000>;
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ };
+
ipa: ipa@1e40000 {
compatible = "qcom,sc7180-ipa";
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
*/
/delete-node/ &cdsp_mem;
+/delete-node/ &domain_idle_states;
/delete-node/ &gpu_zap_mem;
/delete-node/ &gpu_zap_shader;
/delete-node/ &hyp_mem;
/delete-node/ &sec_apps_mem;
/ {
+ cpus {
+ domain_idle_states: domain-idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x40003444>;
+ entry-latency-us = <2752>;
+ exit-latency-us = <6562>;
+ min-residency-us = <9926>;
+ };
+ };
+ };
+
reserved-memory {
camera_mem: memory@8ad00000 {
reg = <0x0 0x8ad00000 0x0 0x500000>;
};
};
+&CLUSTER_PD {
+ domain-idle-states = <&CLUSTER_SLEEP_0>;
+};
+
&lpass_aon {
status = "okay";
};
dma-coherent;
};
+&venus {
+ iommus = <&apps_smmu 0x2180 0x20>,
+ <&apps_smmu 0x2184 0x20>;
+
+ status = "okay";
+
+ video-firmware {
+ iommus = <&apps_smmu 0x21a2 0x0>;
+ };
+};
+
&watchdog {
status = "okay";
};
pinctrl-names = "default";
pinctrl-0 = <&ap_ec_int_l>;
spi-max-frequency = <3000000>;
+ wakeup-source;
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
pinctrl-names = "default";
pinctrl-0 = <&ap_ec_int_l>;
spi-max-frequency = <3000000>;
+ wakeup-source;
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
power-domain-names = "psci";
next-level-cache = <&L2_0>;
operating-points-v2 = <&cpu0_opp_table>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domain-names = "psci";
next-level-cache = <&L2_100>;
operating-points-v2 = <&cpu0_opp_table>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domain-names = "psci";
next-level-cache = <&L2_200>;
operating-points-v2 = <&cpu0_opp_table>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domain-names = "psci";
next-level-cache = <&L2_300>;
operating-points-v2 = <&cpu0_opp_table>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domain-names = "psci";
next-level-cache = <&L2_400>;
operating-points-v2 = <&cpu4_opp_table>;
+ capacity-dmips-mhz = <1946>;
+ dynamic-power-coefficient = <520>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domain-names = "psci";
next-level-cache = <&L2_500>;
operating-points-v2 = <&cpu4_opp_table>;
+ capacity-dmips-mhz = <1946>;
+ dynamic-power-coefficient = <520>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domain-names = "psci";
next-level-cache = <&L2_600>;
operating-points-v2 = <&cpu4_opp_table>;
+ capacity-dmips-mhz = <1946>;
+ dynamic-power-coefficient = <520>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domain-names = "psci";
next-level-cache = <&L2_700>;
operating-points-v2 = <&cpu7_opp_table>;
+ capacity-dmips-mhz = <1985>;
+ dynamic-power-coefficient = <552>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 2>;
};
};
- domain-idle-states {
- CLUSTER_SLEEP_0: cluster-sleep-0 {
+ domain_idle_states: domain-idle-states {
+ CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
compatible = "domain-idle-state";
- idle-state-name = "cluster-power-down";
- arm,psci-suspend-param = <0x40003444>;
+ arm,psci-suspend-param = <0x41000044>;
+ entry-latency-us = <2752>;
+ exit-latency-us = <3048>;
+ min-residency-us = <6118>;
+ };
+
+ CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x41001344>;
entry-latency-us = <3263>;
+ exit-latency-us = <4562>;
+ min-residency-us = <8467>;
+ };
+
+ CLUSTER_SLEEP_LLCC_OFF: cluster-sleep-2 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x4100b344>;
+ entry-latency-us = <3638>;
exit-latency-us = <6562>;
- min-residency-us = <9926>;
- local-timer-stop;
+ min-residency-us = <9826>;
};
};
};
CLUSTER_PD: power-domain-cluster {
#power-domain-cells = <0>;
- domain-idle-states = <&CLUSTER_SLEEP_0>;
+ domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_CX_RET &CLUSTER_SLEEP_LLCC_OFF>;
};
};
#address-cells = <1>;
#size-cells = <1>;
- gpu_speed_bin: gpu_speed_bin@1e9 {
+ gpu_speed_bin: gpu-speed-bin@1e9 {
reg = <0x1e9 0x2>;
bits = <5 8>;
};
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
<&apps_smmu 0x4e6 0x0011>;
qcom,ee = <0>;
qcom,controlled-remotely;
+ num-channels = <16>;
+ qcom,num-ees = <4>;
};
crypto: crypto@1dfa000 {
status = "disabled";
};
+ slimbam: dma-controller@3a84000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0 0x03a84000 0 0x20000>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,controlled-remotely;
+ num-channels = <31>;
+ qcom,ee = <1>;
+ qcom,num-ees = <2>;
+ iommus = <&apps_smmu 0x1826 0x0>;
+ status = "disabled";
+ };
+
+ slim: slim-ngd@3ac0000 {
+ compatible = "qcom,slim-ngd-v1.5.0";
+ reg = <0 0x03ac0000 0 0x2c000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&slimbam 3>, <&slimbam 4>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x1826 0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
lpass_hm: clock-controller@3c00000 {
compatible = "qcom,sc7280-lpasshm";
reg = <0 0x03c00000 0 0x28>;
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
compatible = "qcom,sc7280-adsp-pas";
reg = <0 0x03700000 0 0x100>;
- interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
compatible = "qcom,sc7280-cdsp-pas";
reg = <0 0x0a300000 0 0x10000>;
- interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq",
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ };
+ };
+ };
};
};
<&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "cpu-cfg", "video-mem";
- iommus = <&apps_smmu 0x2180 0x20>,
- <&apps_smmu 0x2184 0x20>;
+ iommus = <&apps_smmu 0x2180 0x20>;
memory-region = <&video_mem>;
+ status = "disabled";
+
video-decoder {
compatible = "venus-decoder";
};
compatible = "venus-encoder";
};
- video-firmware {
- iommus = <&apps_smmu 0x21a2 0x0>;
- };
-
venus_opp_table: opp-table {
compatible = "operating-points-v2";
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000004>;
- entry-latency-us = <241>;
+ entry-latency-us = <2411>;
exit-latency-us = <1461>;
min-residency-us = <4488>;
local-timer-stop;
};
domain-idle-states {
- CLUSTER_SLEEP_0: cluster-sleep-0 {
+ CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x41000044>;
+ entry-latency-us = <3300>;
+ exit-latency-us = <3300>;
+ min-residency-us = <6000>;
+ };
+
+ CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100a344>;
entry-latency-us = <3263>;
CLUSTER_PD: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
- domain-idle-states = <&CLUSTER_SLEEP_0>;
+ domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
};
};
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"sleep_clk";
+ power-domains = <&rpmhpd SC8180X_CX>;
};
qupv3_id_0: geniqup@8c0000 {
ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
<0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
- interrupts = <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
<0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
- interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
reg = <0 0x01d87000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_MEM_CLKREF_EN>;
clock-names = "ref",
- "ref_aux";
+ "ref_aux",
+ "qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
interconnect-names = "gfx-mem";
qcom,gmu = <&gmu>;
+ #cooling-cells = <2>;
+
status = "disabled";
gpu_opp_table: opp-table {
resets = <&gcc GCC_USB30_SEC_BCR>;
power-domains = <&gcc USB30_SEC_GDSC>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 40 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
interrupt-controller;
#interrupt-cells = <1>;
- interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
- <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
- interconnect-names = "mdp0-mem", "mdp1-mem";
+ interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
iommus = <&apps_smmu 0x800 0x420>;
"rot",
"lut";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
- <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
- assigned-clock-rates = <460000000>,
- <19200000>;
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SC8180X_MMCX>;
<&dispcc DISP_CC_MDSS_AHB_CLK>;
clock-names = "aux", "cfg_ahb";
- power-domains = <&dispcc MDSS_GDSC>;
+ power-domains = <&rpmhpd SC8180X_MX>;
#clock-cells = <1>;
#phy-cells = <0>;
"edp_phy_pll_link_clk",
"edp_phy_pll_vco_div_clk";
power-domains = <&rpmhpd SC8180X_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
- reg = <0x0 0x0c300000 0x0 0x100000>;
+ reg = <0x0 0x0c300000 0x0 0x400>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 0>;
#power-domain-cells = <1>;
};
+ sram@c3f0000 {
+ compatible = "qcom,rpmh-stats";
+ reg = <0x0 0x0c3f0000 0x0 0x400>;
+ };
+
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c440000 0x0 0x0001100>,
thermal-sensors = <&tsens0 15>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_top_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
thermal-sensors = <&tsens1 11>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_bottom_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
};
&pmk8280_vadc {
- status = "okay";
-
- channel@3 {
- reg = <PMK8350_ADC7_DIE_TEMP>;
- qcom,pre-scaling = <1 1>;
- label = "pmk8350_die_temp";
- };
-
- channel@44 {
- reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
- qcom,hw-settle-time = <200>;
- qcom,ratiometric;
- label = "pmk8350_xo_therm";
- };
-
- channel@103 {
- reg = <PM8350_ADC7_DIE_TEMP(1)>;
- qcom,pre-scaling = <1 1>;
- label = "pmc8280_1_die_temp";
- };
-
channel@144 {
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
qcom,hw-settle-time = <200>;
label = "sys_therm4";
};
- channel@303 {
- reg = <PM8350_ADC7_DIE_TEMP(3)>;
- qcom,pre-scaling = <1 1>;
- label = "pmc8280_2_die_temp";
- };
-
channel@344 {
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm8";
};
-
- channel@403 {
- reg = <PMR735A_ADC7_DIE_TEMP>;
- qcom,pre-scaling = <1 1>;
- label = "pmr735a_die_temp";
- };
};
&qup0 {
};
&vamacro {
- pinctrl-0 = <&dmic01_default>, <&dmic02_default>;
+ pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
vdd-micb-supply = <&vreg_s10b>;
* Copyright (c) 2022, Linaro Limited
*/
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
- status = "disabled";
+
+ channel@3 {
+ reg = <PMK8350_ADC7_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ label = "pmk8350_die_temp";
+ };
+
+ channel@44 {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ label = "pmk8350_xo_therm";
+ };
+
+ channel@103 {
+ reg = <PM8350_ADC7_DIE_TEMP(1)>;
+ qcom,pre-scaling = <1 1>;
+ label = "pmc8280_1_die_temp";
+ };
+
+ channel@303 {
+ reg = <PM8350_ADC7_DIE_TEMP(3)>;
+ qcom,pre-scaling = <1 1>;
+ label = "pmc8280_2_die_temp";
+ };
+
+ channel@403 {
+ reg = <PMR735A_ADC7_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ label = "pmr735a_die_temp";
+ };
};
pmk8280_adc_tm: adc-tm@3400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pmk8280_vadc PM8350_ADC7_DIE_TEMP(1)>;
+ io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pmk8280_vadc PM8350_ADC7_DIE_TEMP(3)>;
+ io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
reset-names = "pci";
power-domains = <&gcc PCIE_4_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie4_phy>;
phy-names = "pciephy";
reset-names = "pci";
power-domains = <&gcc PCIE_3B_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie3b_phy>;
phy-names = "pciephy";
reset-names = "pci";
power-domains = <&gcc PCIE_3A_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie3a_phy>;
phy-names = "pciephy";
reset-names = "pci";
power-domains = <&gcc PCIE_2B_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie2b_phy>;
phy-names = "pciephy";
reset-names = "pci";
power-domains = <&gcc PCIE_2A_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie2a_phy>;
phy-names = "pciephy";
compatible = "qcom,sc8280xp-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
- clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
- clock-names = "ref", "ref_aux";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_CARD_CLKREF_CLK>;
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
power-domains = <&gcc UFS_PHY_GDSC>;
compatible = "qcom,sc8280xp-qmp-ufs-phy";
reg = <0 0x01da7000 0 0x1000>;
- clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
- <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
- clock-names = "ref", "ref_aux";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_CARD_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_1_CARD_CLKREF_CLK>;
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
power-domains = <&gcc UFS_CARD_GDSC>;
compatible = "qcom,sc8280xp-adsp-pas";
reg = <0 0x03000000 0 0x100>;
- interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
};
};
- dmic02_default: dmic02-default-state {
+ dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
};
};
- dmic02_sleep: dmic02-sleep-state {
+ dmic23_sleep: dmic23-sleep-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
};
};
+ cci0: cci@ac4a000 {
+ compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac4a000 0 0x1000>;
+
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CCI_0_CLK>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci";
+
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci0_default>;
+ pinctrl-1 = <&cci0_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac4b000 {
+ compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac4b000 0 0x1000>;
+
+ interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CCI_1_CLK>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci";
+
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci1_default>;
+ pinctrl-1 = <&cci1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci2: cci@ac4c000 {
+ compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac4c000 0 0x1000>;
+
+ interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CCI_2_CLK>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci";
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci2_default>;
+ pinctrl-1 = <&cci2_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci2_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci2_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci3: cci@ac4d000 {
+ compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac4d000 0 0x1000>;
+
+ interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CCI_3_CLK>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci";
+
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci3_default>;
+ pinctrl-1 = <&cci3_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci3_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci3_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ camss: camss@ac5a000 {
+ compatible = "qcom,sc8280xp-camss";
+
+ reg = <0 0x0ac5a000 0 0x2000>,
+ <0 0x0ac5c000 0 0x2000>,
+ <0 0x0ac65000 0 0x2000>,
+ <0 0x0ac67000 0 0x2000>,
+ <0 0x0acaf000 0 0x4000>,
+ <0 0x0acb3000 0 0x1000>,
+ <0 0x0acb6000 0 0x4000>,
+ <0 0x0acba000 0 0x1000>,
+ <0 0x0acbd000 0 0x4000>,
+ <0 0x0acc1000 0 0x1000>,
+ <0 0x0acc4000 0 0x4000>,
+ <0 0x0acc8000 0 0x1000>,
+ <0 0x0accb000 0 0x4000>,
+ <0 0x0accf000 0 0x1000>,
+ <0 0x0acd2000 0 0x4000>,
+ <0 0x0acd6000 0 0x1000>,
+ <0 0x0acd9000 0 0x4000>,
+ <0 0x0acdd000 0 0x1000>,
+ <0 0x0ace0000 0 0x4000>,
+ <0 0x0ace4000 0 0x1000>;
+ reg-names = "csiphy2",
+ "csiphy3",
+ "csiphy0",
+ "csiphy1",
+ "vfe0",
+ "csid0",
+ "vfe1",
+ "csid1",
+ "vfe2",
+ "csid2",
+ "vfe_lite0",
+ "csid0_lite",
+ "vfe_lite1",
+ "csid1_lite",
+ "vfe_lite2",
+ "csid2_lite",
+ "vfe_lite3",
+ "csid3_lite",
+ "vfe3",
+ "csid3";
+
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid1_lite",
+ "vfe_lite1",
+ "csiphy3",
+ "csid0",
+ "vfe0",
+ "csid1",
+ "vfe1",
+ "csid0_lite",
+ "vfe_lite0",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csid2",
+ "vfe2",
+ "csid3_lite",
+ "csid2_lite",
+ "vfe_lite3",
+ "vfe_lite2",
+ "csid3",
+ "vfe3";
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc IFE_2_GDSC>,
+ <&camcc IFE_3_GDSC>,
+ <&camcc TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "ife3",
+ "top";
+
+ clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CSIPHY0_CLK>,
+ <&camcc CAMCC_CSI0PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY1_CLK>,
+ <&camcc CAMCC_CSI1PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY2_CLK>,
+ <&camcc CAMCC_CSI2PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY3_CLK>,
+ <&camcc CAMCC_CSI3PHYTIMER_CLK>,
+ <&camcc CAMCC_IFE_0_AXI_CLK>,
+ <&camcc CAMCC_IFE_0_CLK>,
+ <&camcc CAMCC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_0_CSID_CLK>,
+ <&camcc CAMCC_IFE_1_AXI_CLK>,
+ <&camcc CAMCC_IFE_1_CLK>,
+ <&camcc CAMCC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_1_CSID_CLK>,
+ <&camcc CAMCC_IFE_2_AXI_CLK>,
+ <&camcc CAMCC_IFE_2_CLK>,
+ <&camcc CAMCC_IFE_2_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_2_CSID_CLK>,
+ <&camcc CAMCC_IFE_3_AXI_CLK>,
+ <&camcc CAMCC_IFE_3_CLK>,
+ <&camcc CAMCC_IFE_3_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_3_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_0_CLK>,
+ <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_0_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_1_CLK>,
+ <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_1_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_2_CLK>,
+ <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_2_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_3_CLK>,
+ <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_3_CSID_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "vfe0_axi",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe0_csid",
+ "vfe1_axi",
+ "vfe1",
+ "vfe1_cphy_rx",
+ "vfe1_csid",
+ "vfe2_axi",
+ "vfe2",
+ "vfe2_cphy_rx",
+ "vfe2_csid",
+ "vfe3_axi",
+ "vfe3",
+ "vfe3_cphy_rx",
+ "vfe3_csid",
+ "vfe_lite0",
+ "vfe_lite0_cphy_rx",
+ "vfe_lite0_csid",
+ "vfe_lite1",
+ "vfe_lite1_cphy_rx",
+ "vfe_lite1_csid",
+ "vfe_lite2",
+ "vfe_lite2_cphy_rx",
+ "vfe_lite2_csid",
+ "vfe_lite3",
+ "vfe_lite3_cphy_rx",
+ "vfe_lite3_csid",
+ "gcc_axi_hf",
+ "gcc_axi_sf";
+
+ iommus = <&apps_smmu 0x2000 0x4e0>,
+ <&apps_smmu 0x2020 0x4e0>,
+ <&apps_smmu 0x2040 0x4e0>,
+ <&apps_smmu 0x2060 0x4e0>,
+ <&apps_smmu 0x2080 0x4e0>,
+ <&apps_smmu 0x20e0 0x4e0>,
+ <&apps_smmu 0x20c0 0x4e0>,
+ <&apps_smmu 0x20a0 0x4e0>,
+ <&apps_smmu 0x2400 0x4e0>,
+ <&apps_smmu 0x2420 0x4e0>,
+ <&apps_smmu 0x2440 0x4e0>,
+ <&apps_smmu 0x2460 0x4e0>,
+ <&apps_smmu 0x2480 0x4e0>,
+ <&apps_smmu 0x24e0 0x4e0>,
+ <&apps_smmu 0x24c0 0x4e0>,
+ <&apps_smmu 0x24a0 0x4e0>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
+ <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "cam_ahb",
+ "cam_hf_mnoc",
+ "cam_sf_mnoc",
+ "cam_sf_icp_mnoc";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sc8280xp-camcc";
reg = <0 0x0ad00000 0 0x20000>;
interrupt-controller;
};
+ tsens2: thermal-sensor@c251000 {
+ compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c251000 0 0x1ff>,
+ <0 0x0c224000 0 0x8>;
+ #qcom,sensors = <11>;
+ interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens3: thermal-sensor@c252000 {
+ compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c252000 0 0x1ff>,
+ <0 0x0c225000 0 0x8>;
+ #qcom,sensors = <5>;
+ interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 230>;
wakeup-parent = <&pdc>;
+
+ cci0_default: cci0-default-state {
+ cci0_i2c0_default: cci0-i2c0-default-pins {
+ /* cci_i2c_sda0, cci_i2c_scl0 */
+ pins = "gpio113", "gpio114";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_i2c1_default: cci0-i2c1-default-pins {
+ /* cci_i2c_sda1, cci_i2c_scl1 */
+ pins = "gpio115", "gpio116";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_sleep: cci0-sleep-state {
+ cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
+ /* cci_i2c_sda0, cci_i2c_scl0 */
+ pins = "gpio113", "gpio114";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
+ /* cci_i2c_sda1, cci_i2c_scl1 */
+ pins = "gpio115", "gpio116";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_default: cci1-default-state {
+ cci1_i2c0_default: cci1-i2c0-default-pins {
+ /* cci_i2c_sda2, cci_i2c_scl2 */
+ pins = "gpio10","gpio11";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci1_i2c1_default: cci1-i2c1-default-pins {
+ /* cci_i2c_sda3, cci_i2c_scl3 */
+ pins = "gpio123","gpio124";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_sleep: cci1-sleep-state {
+ cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
+ /* cci_i2c_sda2, cci_i2c_scl2 */
+ pins = "gpio10","gpio11";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
+ /* cci_i2c_sda3, cci_i2c_scl3 */
+ pins = "gpio123","gpio124";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci2_default: cci2-default-state {
+ cci2_i2c0_default: cci2-i2c0-default-pins {
+ /* cci_i2c_sda4, cci_i2c_scl4 */
+ pins = "gpio117","gpio118";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci2_i2c1_default: cci2-i2c1-default-pins {
+ /* cci_i2c_sda5, cci_i2c_scl5 */
+ pins = "gpio12","gpio13";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci2_sleep: cci2-sleep-state {
+ cci2_i2c0_sleep: cci2-i2c0-sleep-pins {
+ /* cci_i2c_sda4, cci_i2c_scl4 */
+ pins = "gpio117","gpio118";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci2_i2c1_sleep: cci2-i2c1-sleep-pins {
+ /* cci_i2c_sda5, cci_i2c_scl5 */
+ pins = "gpio12","gpio13";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci3_default: cci3-default-state {
+ cci3_i2c0_default: cci3-i2c0-default-pins {
+ /* cci_i2c_sda6, cci_i2c_scl6 */
+ pins = "gpio145","gpio146";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci3_i2c1_default: cci3-i2c1-default-pins {
+ /* cci_i2c_sda7, cci_i2c_scl7 */
+ pins = "gpio164","gpio165";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci3_sleep: cci3-sleep-state {
+ cci3_i2c0_sleep: cci3-i2c0-sleep-pins {
+ /* cci_i2c_sda6, cci_i2c_scl6 */
+ pins = "gpio145","gpio146";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
+ /* cci_i2c_sda7, cci_i2c_scl7 */
+ pins = "gpio164","gpio165";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sc8280xp-nsp0-pas";
reg = <0 0x1b300000 0 0x100>;
- interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
compatible = "qcom,sc8280xp-nsp1-pas";
reg = <0 0x21300000 0 0x100>;
- interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
};
};
+ gpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 2>;
+
+ trips {
+ gpu-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
mem-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
dr_mode = "peripheral";
extcon = <&extcon_usb>;
};
+
+&usb3_qmpphy {
+ vdda-phy-supply = <&vreg_l1b_0p925>;
+ status = "okay";
+};
*/
/dts-v1/;
-#include "msm8953.dtsi"
+#include "sdm450.dtsi"
#include "pm8953.dtsi"
#include "pmi8950.dtsi"
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/* Copyright (c) 2023, Luca Weiss <luca@z3ntu.xyz> */
+
+#include "msm8953.dtsi"
+
+&gpu_opp_table {
+ /delete-node/ opp-650000000;
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0xff>;
+ required-opps = <&rpmpd_opp_turbo>;
+ };
+};
};
};
+&pm660l_wled {
+ status = "okay";
+
+ qcom,switching-freq = <800>;
+ qcom,ovp-millivolt = <29600>;
+ qcom,current-boost-limit = <970>;
+ qcom,current-limit-microamp = <17500>;
+ qcom,num-strings = <2>;
+};
+
&pon_pwrkey {
status = "okay";
};
};
&usb3 {
+ qcom,select-utmi-as-pipe-clk;
+
status = "okay";
};
&usb3_dwc3 {
+ maximum-speed = "high-speed";
+ phys = <&qusb2phy0>;
+ phy-names = "usb2-phy";
+
dr_mode = "peripheral";
extcon = <&extcon_usb>;
};
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/soc/qcom,apr.h>
/ {
interconnect-names = "gfx-mem";
operating-points-v2 = <&gpu_sdm630_opp_table>;
+ #cooling-cells = <2>;
status = "disabled";
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <120000000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB_30_GDSC>;
- qcom,select-utmi-as-pipe-clk;
resets = <&gcc GCC_USB_30_BCR>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- /*
- * SDM630 technically supports USB3 but I
- * haven't seen any devices making use of it.
- */
- maximum-speed = "high-speed";
- phys = <&qusb2phy0>;
- phy-names = "usb2-phy";
+ phys = <&qusb2phy0>, <&usb3_qmpphy>;
+ phy-names = "usb2-phy", "usb3-phy";
snps,hird-threshold = /bits/ 8 <0>;
};
};
+ usb3_qmpphy: phy@c010000 {
+ compatible = "qcom,sdm660-qmp-usb3-phy";
+ reg = <0x0c010000 0x1000>;
+
+ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_CLKREF_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
+
+ status = "disabled";
+ };
+
qusb2phy0: phy@c012000 {
compatible = "qcom,sdm660-qusb2-phy";
reg = <0x0c012000 0x180>;
<&gcc GCC_USB20_MASTER_CLK>;
assigned-clock-rates = <19200000>, <60000000>;
- interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq";
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "hs_phy_irq";
qcom,select-utmi-as-pipe-clk;
thermal-sensors = <&tsens 8>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device = <&adreno_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
gpu_alert0: trip-point0 {
temperature = <90000>;
compatible = "qcom,kryo250";
capacity-dmips-mhz = <1980>;
};
+
+&gpu_opp_table {
+ opp-725000000 {
+ opp-hz = /bits/ 64 <725000000>;
+ opp-supported-hw = <0xff>;
+ required-opps = <&rpmpd_opp_turbo>;
+ };
+};
};
&usb3 {
+ qcom,select-utmi-as-pipe-clk;
+
status = "okay";
};
&usb3_dwc3 {
+ maximum-speed = "high-speed";
+ phys = <&qusb2phy0>;
+ phy-names = "usb2-phy";
+
dr_mode = "peripheral";
extcon = <&extcon_usb>;
};
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
pinctrl-names = "default";
pinctrl-0 = <&ec_ap_int_l>;
spi-max-frequency = <3000000>;
+ wakeup-source;
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
&pcie0 {
status = "okay";
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
vddpe-3v3-supply = <&pcie0_3p3v_dual>;
};
&q6afedai {
- qi2s@22 {
- reg = <22>;
+ dai@22 {
+ reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <1>;
};
- qi2s@23 {
- reg = <23>;
+ dai@23 {
+ reg = <QUATERNARY_MI2S_TX>;
qcom,sd-lines = <0>;
};
};
};
reserved-memory {
- framebuffer_region@9d400000 {
+ framebuffer@9d400000 {
reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>;
no-map;
};
compatible = "qcom,sdm845-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_MEM_CLKREF_CLK>;
clock-names = "ref",
- "ref_aux";
- clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ "ref_aux",
+ "qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
qcom,qmp = <&aoss_qmp>;
- power-domains = <&rpmhpd SDM845_CX>,
- <&rpmhpd SDM845_MX>;
+ power-domains = <&rpmhpd SDM845_LCX>,
+ <&rpmhpd SDM845_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>,
<&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>,
- <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>,
<&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>,
- <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
+ #cooling-cells = <2>;
interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
interconnect-names = "gfx-mem";
hysteresis = <2000>;
type = "hot";
};
- cluster0_crit: cluster0_crit {
+ cluster0_crit: cluster0-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
hysteresis = <2000>;
type = "hot";
};
- cluster1_crit: cluster1_crit {
+ cluster1_crit: cluster1-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
thermal-sensors = <&tsens0 11>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_top_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- gpu1_alert0: trip-point0 {
+ gpu_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
thermal-sensors = <&tsens0 12>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_bottom_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- gpu2_alert0: trip-point0 {
+ gpu_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
chosen { };
- clocks{
+ clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <76800000>;
#include <dt-bindings/interconnect/qcom,sm6115.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
#hwlock-cells = <1>;
};
+ tcsr_regs: syscon@3c0000 {
+ compatible = "qcom,sm6115-tcsr", "syscon";
+ reg = <0x0 0x003c0000 0x0 0x40000>;
+ };
+
tlmm: pinctrl@500000 {
compatible = "qcom,sm6115-tlmm";
reg = <0x0 0x00500000 0x0 0x400000>,
clock-output-names = "usb3_phy_pipe_clk_src";
#phy-cells = <0>;
+ orientation-switch;
+
+ qcom,tcsr-reg = <&tcsr_regs 0xb244>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_dwc3_ss>;
+ };
+ };
+ };
};
system_noc: interconnect@1880000 {
compatible = "qcom,sm6115-qmp-ufs-phy";
reg = <0x0 0x04807000 0x0 0x1000>;
- clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
- clock-names = "ref", "ref_aux";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_CLKREF_CLK>;
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <66666667>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "hs_phy_irq",
+ "ss_phy_irq";
resets = <&gcc GCC_USB30_PRIM_BCR>;
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
interconnect-names = "usb-ddr",
"apps-usb";
- qcom,select-utmi-as-pipe-clk;
status = "disabled";
usb_dwc3: usb@4e00000 {
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
+
+ usb-role-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_qmpphy_usb_ss_in>;
+ };
+ };
+ };
};
};
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
+ #cooling-cells = <2>;
status = "disabled";
type = "passive";
};
- cpu4_crit: cpu_crit {
+ cpu4_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
type = "passive";
};
- cpu5_crit: cpu_crit {
+ cpu5_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
type = "passive";
};
- cpu6_crit: cpu_crit {
+ cpu6_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
type = "passive";
};
- cpu7_crit: cpu_crit {
+ cpu7_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
type = "passive";
};
- cpu45_crit: cpu_crit {
+ cpu45_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
type = "passive";
};
- cpu67_crit: cpu_crit {
+ cpu67_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
type = "passive";
};
- cpu0123_crit: cpu_crit {
+ cpu0123_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
polling-delay = <0>;
thermal-sensors = <&tsens0 15>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu_alert0: trip-point0 {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
trip-point1 {
temperature = <125000>;
hysteresis = <1000>;
- type = "passive";
+ type = "critical";
};
};
};
compatible = "qcom,sm6125-qmp-ufs-phy";
reg = <0x04807000 0xdb8>;
- clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_MEM_CLKREF_CLK>;
clock-names = "ref",
- "ref_aux";
+ "ref_aux",
+ "qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <66666667>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
qcom,select-utmi-as-pipe-clk;
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
compatible = "qcom,sm6350-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_MEM_CLKREF_CLK>;
clock-names = "ref",
- "ref_aux";
- clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ "ref_aux",
+ "qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
compatible = "qcom,sm6350-adsp-pas";
reg = <0 0x03000000 0 0x100>;
- interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
qcom,gmu = <&gmu>;
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
+ #cooling-cells = <2>;
status = "disabled";
- zap-shader {
+ gpu_zap_shader: zap-shader {
memory-region = <&pil_gpu_mem>;
};
operating-points-v2 = <&gmu_opp_table>;
- status = "disabled";
-
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
compatible = "qcom,sm6350-cdsp-pas";
reg = <0 0x08300000 0 0x10000>;
- interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
"mock_utmi";
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
-
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
interrupt-controller;
#interrupt-cells = <1>;
+ interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
};
};
+ thermal-zones {
+ aoss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ aoss0-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ aoss1-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ audio-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ audio-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ camera-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ cpu0_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ cpu1_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert0>;
+ cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ cpu2_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert0>;
+ cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ cpu3_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert0>;
+ cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu4-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ cpu4_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu4_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu5-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ cpu5_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu5_alert0>;
+ cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu6-left-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ cpu6_left_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6-left-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu6_left_alert0>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu6-right-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ cpu6_right_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6-right-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu6_right_alert0>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu7-left-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ cpu7_left_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7-left-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu7_left_alert0>;
+ cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu7-right-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ cpu7_right_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7-right-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu7_right_alert0>;
+ cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ cpuss0-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ cpuss1-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cwlan-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ cwlan-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ ddr-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 13>;
+
+ trips {
+ gpuss0_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpuss0-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpuss0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpuss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 14>;
+
+ trips {
+ gpuss1_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpuss1-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpuss1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ modem-core0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ modem-core0-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem-core1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ modem-core1-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem-scl-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 9>;
+
+ trips {
+ modem-scl-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem-vec-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ modem-vec-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ npu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 10>;
+
+ trips {
+ npu-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ q6-hvx-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ q6-hvx-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 11>;
+
+ trips {
+ video-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
clock-frequency = <19200000>;
assigned-clock-rates = <19200000>, <133333333>;
interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
- <&mpm 12 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <&mpm 94 IRQ_TYPE_EDGE_BOTH>,
<&mpm 93 IRQ_TYPE_EDGE_BOTH>,
- <&mpm 94 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&mpm 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
compatible = "qcom,sm6375-adsp-pas";
reg = <0 0x0a400000 0 0x100>;
- interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
regulator-min-microvolt = <824000>;
regulator-max-microvolt = <928000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a_2p7: ldo5 {
regulator-min-microvolt = <1696000>;
regulator-max-microvolt = <1952000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13a_1p8: ldo13 {
regulator-min-microvolt = <2696000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
};
regulator-min-microvolt = <1144000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c_1p8: ldo4 {
};
};
+&ufs_mem_hc {
+ vcc-supply = <&vreg_l19a_3p0>;
+ vcc-max-microamp = <600000>;
+ vccq2-supply = <&vreg_l12a_1p8>;
+ vccq2-max-microamp = <600000>;
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l4a_0p88>;
+ vdda-pll-supply = <&vreg_l3c_1p23>;
+ status = "okay";
+};
+
&usb_1 {
qcom,select-utmi-as-pipe-clk;
status = "okay";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023, Joe Mason <buddyjojo06@outlook.com>
+ */
+
+/dts-v1/;
+
+#include "sm7125-xiaomi-common.dtsi"
+
+/ {
+ model = "Xiaomi Redmi Note 9S";
+ compatible = "xiaomi,curtana", "qcom,sm7125";
+
+ /* required for bootloader to select correct board */
+ qcom,board-id = <0x20022 1>;
+};
};
};
+ /* Dummy regulator until PM6150L has LCDB VSP/VSN support */
+ lcdb_dummy: regulator-lcdb-dummy {
+ compatible = "regulator-fixed";
+ regulator-name = "lcdb_dummy";
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+ };
+
reserved-memory {
/*
* The rmtfs memory region in downstream is 'dynamically allocated'
};
&adsp {
- firmware-name = "qcom/sm7225/fairphone4/adsp.mdt";
+ firmware-name = "qcom/sm7225/fairphone4/adsp.mbn";
status = "okay";
};
};
&cdsp {
- firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt";
+ firmware-name = "qcom/sm7225/fairphone4/cdsp.mbn";
status = "okay";
};
status = "okay";
};
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/sm7225/fairphone4/a615_zap.mbn";
+};
+
&i2c0 {
clock-frequency = <400000>;
status = "okay";
&ipa {
qcom,gsi-loader = "self";
memory-region = <&pil_ipa_fw_mem>;
- firmware-name = "qcom/sm7225/fairphone4/ipa_fws.mdt";
+ firmware-name = "qcom/sm7225/fairphone4/ipa_fws.mbn";
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l22a>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "djn,9a-3r063-1102b";
+ reg = <0>;
+
+ backlight = <&pm6150l_wled>;
+ reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>;
+
+ vdd1-supply = <&vreg_l1e>;
+ vsn-supply = <&lcdb_dummy>;
+ vsp-supply = <&lcdb_dummy>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&panel_in>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l18a>;
status = "okay";
};
&mpss {
- firmware-name = "qcom/sm7225/fairphone4/modem.mdt";
+ firmware-name = "qcom/sm7225/fairphone4/modem.mbn";
status = "okay";
};
#address-cells = <1>;
#size-cells = <1>;
- gpu_speed_bin: gpu_speed_bin@133 {
+ gpu_speed_bin: gpu-speed-bin@133 {
reg = <0x133 0x1>;
bits = <5 3>;
};
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
- <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
- "tbu";
+ "tbu",
+ "ref";
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
<0x100 &apps_smmu 0x1d81 0x1>;
phy-names = "pciephy";
perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
- enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
- <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
- "tbu";
+ "tbu",
+ "ref";
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
compatible = "qcom,sm8150-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_MEM_CLKREF_CLK>;
clock-names = "ref",
- "ref_aux";
- clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ "ref_aux",
+ "qref";
power-domains = <&gcc UFS_PHY_GDSC>;
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
+ #cooling-cells = <2>;
status = "disabled";
bias-disable;
};
- qup_spi6_default: qup-spi6_default-state {
+ qup_spi6_default: qup-spi6-default-state {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "qup6";
drive-strength = <6>;
bias-disable;
};
- qup_spi7_default: qup-spi7_default-state {
+ qup_spi7_default: qup-spi7-default-state {
pins = "gpio98", "gpio99", "gpio100", "gpio101";
function = "qup7";
drive-strength = <6>;
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 11 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <&pdc 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
hysteresis = <2000>;
type = "hot";
};
- cluster0_crit: cluster0_crit {
+ cluster0_crit: cluster0-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
hysteresis = <2000>;
type = "hot";
};
- cluster1_crit: cluster1_crit {
+ cluster1_crit: cluster1-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
thermal-sensors = <&tsens0 15>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_top_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- gpu1_alert0: trip-point0 {
+ gpu_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
thermal-sensors = <&tsens1 11>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_bottom_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- gpu2_alert0: trip-point0 {
+ gpu_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
// SPDX-License-Identifier: BSD-3-Clause
/*
- * Copyright (c) 2022, 2023 Jianhua Lu <lujianhua000@gmail.com>
+ * Copyright (c) 2022-2024 Jianhua Lu <lujianhua000@gmail.com>
*/
#include <dt-bindings/arm/qcom,ids.h>
vddio-supply = <&vreg_l14a_1p88>;
reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
backlight = <&backlight>;
+ rotation = <90>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
- gpu_speed_bin: gpu_speed_bin@19b {
+ gpu_speed_bin: gpu-speed-bin@19b {
reg = <0x19b 0x1>;
bits = <5 3>;
};
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi0", "msi1", "msi2", "msi3",
- "msi4", "msi5", "msi6", "msi7";
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
<0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
compatible = "qcom,sm8250-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
- clock-names = "ref",
- "ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_1X_CLKREF_EN>;
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
+ #cooling-cells = <2>;
status = "disabled";
compatible = "qcom,sm8250-slpi-pas";
reg = <0 0x05c00000 0 0x4000>;
- interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
compatible = "qcom,sm8250-cdsp-pas";
reg = <0 0x08300000 0 0x10000>;
- interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
wakeup-source;
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
wakeup-source;
compatible = "qcom,sm8250-adsp-pas";
reg = <0 0x17300000 0 0x100>;
- interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
hysteresis = <2000>;
type = "hot";
};
- cluster0_crit: cluster0_crit {
+ cluster0_crit: cluster0-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
hysteresis = <2000>;
type = "hot";
};
- cluster1_crit: cluster1_crit {
+ cluster1_crit: cluster1-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
thermal-sensors = <&tsens0 15>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_top_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- gpu1_alert0: trip-point0 {
+ gpu_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
thermal-sensors = <&tsens1 8>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_bottom_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- gpu2_alert0: trip-point0 {
+ gpu_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi0", "msi1", "msi2", "msi3",
- "msi4", "msi5", "msi6", "msi7";
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
compatible = "qcom,sm8350-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
- clock-names = "ref",
- "ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_1_CLKREF_EN>;
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
+ #cooling-cells = <2>;
status = "disabled";
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
hysteresis = <2000>;
type = "hot";
};
- cluster0_crit: cluster0_crit {
+ cluster0_crit: cluster0-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
hysteresis = <2000>;
type = "hot";
};
- cluster1_crit: cluster1_crit {
+ cluster1_crit: cluster1-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
thermal-sensors = <&tsens1 1>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_top_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- gpu1_alert0: trip-point0 {
+ gpu_top_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
thermal-sensors = <&tsens1 2>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_bottom_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- gpu2_alert0: trip-point0 {
+ gpu_bottom_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
"TX DMIC3", "MIC BIAS1",
"TX SWR_INPUT0", "ADC1_OUTPUT",
"TX SWR_INPUT1", "ADC2_OUTPUT",
- "TX SWR_INPUT2", "ADC3_OUTPUT",
- "TX SWR_INPUT3", "ADC4_OUTPUT";
+ "TX SWR_INPUT0", "ADC3_OUTPUT",
+ "TX SWR_INPUT1", "ADC4_OUTPUT";
wcd-playback-dai-link {
link-name = "WCD Playback";
};
&vamacro {
- pinctrl-0 = <&dmic01_default>, <&dmic02_default>;
+ pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
vdd-micb-supply = <&vreg_s10b_1p8>;
qcom,dmic-sample-rate = <600000>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart20_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
status = "disabled";
};
};
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
- /*
- * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
- * Hence, the IDs are swapped.
- */
- msi-map = <0x0 &gic_its 0x5981 0x1>,
- <0x100 &gic_its 0x5980 0x1>;
+ msi-map = <0x0 &gic_its 0x5980 0x1>,
+ <0x100 &gic_its 0x5981 0x1>;
msi-map-mask = <0xff00>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
- /*
- * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
- * Hence, the IDs are swapped.
- */
- msi-map = <0x0 &gic_its 0x5a01 0x1>,
- <0x100 &gic_its 0x5a00 0x1>;
+ msi-map = <0x0 &gic_its 0x5a00 0x1>,
+ <0x100 &gic_its 0x5a01 0x1>;
msi-map-mask = <0xff00>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
+ #cooling-cells = <2>;
status = "disabled";
};
};
- dmic02_default: dmic02-default-state {
+ dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_top_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
thermal-engine-config {
temperature = <125000>;
type = "passive";
};
- gpu0_tj_cfg: tj-cfg {
+ gpu_top_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
polling-delay = <0>;
thermal-sensors = <&tsens0 15>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_bottom_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
thermal-engine-config {
temperature = <125000>;
type = "passive";
};
- gpu1_tj_cfg: tj-cfg {
+ gpu_bottom_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8550.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SM8550 HDK";
+ compatible = "qcom,sm8550-hdk", "qcom,sm8550";
+ chassis-type = "embedded";
+
+ aliases {
+ serial0 = &uart7;
+ serial1 = &uart14;
+ };
+
+ wcd938x: audio-codec {
+ compatible = "qcom,wcd9385-codec";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcd_default>;
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ reset-gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+
+ vdd-buck-supply = <&vreg_l15b_1p8>;
+ vdd-rxtx-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob1>;
+
+ #sound-dai-cells = <1>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_out: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_BLUETOOTH;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&tlmm 159 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ default-state = "off";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&tlmm 160 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ panic-indicator;
+ };
+
+ led-2 {
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_ORANGE>;
+ gpios = <&tlmm 162 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&fsa4480_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ lt9611_1v2: regulator-lt9611-1v2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "LT9611_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ vin-supply = <&vph_pwr>;
+ gpio = <&tlmm 152 GPIO_ACTIVE_HIGH>;
+
+ enable-active-high;
+ };
+
+ lt9611_3v3: regulator-lt9611-3v3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "LT9611_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&vreg_bob_3v3>;
+ gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>;
+
+ enable-active-high;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_bob_3v3: regulator-vreg-bob-3v3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_BOB_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ sound {
+ compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
+ model = "SM8550-HDK";
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC1", "MIC BIAS1",
+ "AMIC2", "MIC BIAS2",
+ "AMIC5", "MIC BIAS4",
+ "TX SWR_INPUT0", "ADC1_OUTPUT",
+ "TX SWR_INPUT1", "ADC2_OUTPUT",
+ "TX SWR_INPUT1", "ADC4_OUTPUT";
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ codec {
+ sound-dai = <&lpass_vamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s4g_1p25>;
+ vdd-l12-supply = <&vreg_s6g_1p86>;
+ vdd-l15-supply = <&vreg_s6g_1p86>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ qcom,pmic-id = "b";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ qcom,pmic-id = "c";
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ qcom,pmic-id = "d";
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* ldo2 supplies SM8550 VDD_LPI_MX */
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "e";
+
+ vreg_s4e_0p95: smps4 {
+ regulator-name = "vreg_s4e_0p95";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p08: smps5 {
+ regulator-name = "vreg_s5e_1p08";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "f";
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p88: ldo3 {
+ regulator-name = "vreg_l3f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "g";
+
+ vreg_s1g_1p25: smps1 {
+ regulator-name = "vreg_s1g_1p25";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p85: smps2 {
+ regulator-name = "vreg_s2g_0p85";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p8: smps3 {
+ regulator-name = "vreg_s3g_0p8";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p25: smps4 {
+ regulator-name = "vreg_s4g_1p25";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5g_0p85: smps5 {
+ regulator-name = "vreg_s5g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p86: smps6 {
+ regulator-name = "vreg_s6g_1p86";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ vdd-l1-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6g_1p86>;
+ vdd-l6-supply = <&vreg_s6g_1p86>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ qcom,pmic-id = "m";
+
+ vreg_l1m_1p056: ldo1 {
+ regulator-name = "vreg_l1m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_1p8: ldo6 {
+ regulator-name = "vreg_l6m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p9: ldo7 {
+ regulator-name = "vreg_l7m_2p9";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ vdd-l1-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6g_1p86>;
+ vdd-l6-supply = <&vreg_bob1>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ qcom,pmic-id = "n";
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p1: ldo2 {
+ regulator-name = "vreg_l2n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_2p8: ldo3 {
+ regulator-name = "vreg_l3n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_2p8: ldo4 {
+ regulator-name = "vreg_l4n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_1p8: ldo5 {
+ regulator-name = "vreg_l5n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_3p3: ldo6 {
+ regulator-name = "vreg_l6n_3p3";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_2p96: ldo7 {
+ regulator-name = "vreg_l7n_2p96";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = <&tlmm 8 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-0 = <<9611_irq_pin>, <<9611_rst_pin>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_connector_out>;
+ };
+ };
+ };
+ };
+};
+
+&i2c_hub_2 {
+ status = "okay";
+
+ typec-mux@42 {
+ compatible = "fcs,fsa4480";
+ reg = <0x42>;
+
+ vcc-supply = <&vreg_bob1>;
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ fsa4480_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&ipa {
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
+ firmware-name = "qcom/sm8550/ipa_fws.mbn";
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/sm8550/a740_zap.mbn";
+ };
+};
+
+&lpass_tlmm {
+ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ spkr_2_sd_n_active: spkr-2-sd-n-active-state {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+ data-lanes = <0 1>;
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie1 {
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3c_0p9>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-qref-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&pcie_1_phy_aux_clk {
+ clock-frequency = <1000>;
+};
+
+&pm8550_gpios {
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio12";
+ function = "normal";
+ input-enable;
+ output-disable;
+ bias-pull-up;
+ power-source = <1>; /* 1.8 V */
+ };
+
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+/* The RGB signals are routed to 3 separate LEDs on the HDK8550 */
+&pm8550_pwm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ };
+
+ led@2 {
+ reg = <2>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ };
+
+ led@3 {
+ reg = <3>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/adsp.mbn",
+ "qcom/sm8550/adsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8550/cdsp.mbn",
+ "qcom/sm8550/cdsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm8550/modem.mbn",
+ "qcom/sm8550/modem_dtb.mbn";
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&swr0 {
+ status = "okay";
+
+ /* WSA8845, Speaker North */
+ north_spkr: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-names = "default";
+
+ powerdown-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>;
+
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ };
+
+ /* WSA8845, Speaker South */
+ south_spkr: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+
+ pinctrl-0 = <&spkr_2_sd_n_active>;
+ pinctrl-names = "default";
+
+ powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>;
+
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ /* WCD9385 RX */
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+
+ /*
+ * WCD9385 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R)
+ * WCD9385 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH)
+ * WCD9385 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R)
+ * WCD9385 RX Port 4 (LO) <=> SWR1 Port 4 (LO)
+ * WCD9385 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R)
+ */
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ /* WCD9385 TX */
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+
+ /*
+ * WCD9385 TX Port 1 (ADC1,2) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
+ * WCD9385 TX Port 2 (ADC3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
+ * WCD9385 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7)
+ * WCD9385 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11)
+ */
+ qcom,tx-port-mapping = <2 2 3 4>;
+ };
+};
+
+&tlmm {
+ /* Reserved I/Os for NFC */
+ gpio-reserved-ranges = <32 8>;
+
+ bt_default: bt-default-state {
+ bt-en-pins {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sw-ctrl-pins {
+ pins = "gpio82";
+ function = "gpio";
+ bias-pull-down;
+ };
+ };
+
+ lt9611_irq_pin: lt9611-irq-state {
+ pins = "gpio8";
+ function = "gpio";
+ bias-disable;
+ };
+
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio7";
+ function = "gpio";
+ output-high;
+ };
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio108";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_s4e_0p95>;
+ vdddig-supply = <&vreg_s4e_0p95>;
+ vddrfa0p8-supply = <&vreg_s4e_0p95>;
+ vddrfa1p2-supply = <&vreg_s4g_1p25>;
+ vddrfa1p9-supply = <&vreg_s6g_1p86>;
+
+ max-speed = <3200000>;
+
+ enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&bt_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ phys = <&pm8550b_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p88>;
+
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_dp_in {
+ remote-endpoint = <&mdss_dp0_out>;
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&usb_dp_qmpphy_usb_ss_in {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
"SpkrRight IN", "WSA_SPK2 OUT",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
+ "AMIC1", "MIC BIAS1",
"AMIC2", "MIC BIAS2",
+ "AMIC3", "MIC BIAS3",
+ "AMIC4", "MIC BIAS3",
+ "AMIC5", "MIC BIAS4",
"VA DMIC0", "MIC BIAS1",
"VA DMIC1", "MIC BIAS1",
"VA DMIC2", "MIC BIAS3",
"TX DMIC0", "MIC BIAS1",
"TX DMIC1", "MIC BIAS2",
"TX DMIC2", "MIC BIAS3",
- "TX SWR_ADC1", "ADC2_OUTPUT";
+ "TX SWR_INPUT0", "ADC1_OUTPUT",
+ "TX SWR_INPUT1", "ADC2_OUTPUT",
+ "TX SWR_INPUT0", "ADC3_OUTPUT",
+ "TX SWR_INPUT1", "ADC4_OUTPUT";
wcd-playback-dai-link {
link-name = "WCD Playback";
wcd_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
- qcom,tx-port-mapping = <1 1 2 3>;
+ qcom,tx-port-mapping = <2 2 3 4>;
};
};
"SpkrRight IN", "WSA_SPK2 OUT",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
+ "AMIC1", "MIC BIAS1",
"AMIC2", "MIC BIAS2",
+ "AMIC3", "MIC BIAS3",
+ "AMIC4", "MIC BIAS3",
+ "AMIC5", "MIC BIAS4",
"VA DMIC0", "MIC BIAS1",
"VA DMIC1", "MIC BIAS1",
"VA DMIC2", "MIC BIAS3",
"TX DMIC0", "MIC BIAS1",
"TX DMIC1", "MIC BIAS2",
"TX DMIC2", "MIC BIAS3",
- "TX SWR_ADC1", "ADC2_OUTPUT";
+ "TX SWR_INPUT0", "ADC1_OUTPUT",
+ "TX SWR_INPUT1", "ADC2_OUTPUT",
+ "TX SWR_INPUT0", "ADC3_OUTPUT",
+ "TX SWR_INPUT1", "ADC4_OUTPUT";
wcd-playback-dai-link {
link-name = "WCD Playback";
<&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
};
+&gpi_dma1 {
+ status = "okay";
+};
+
&gpu {
status = "okay";
};
};
+&spi4 {
+ status = "okay";
+
+ touchscreen@0 {
+ compatible = "goodix,gt9916";
+ reg = <0>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&vreg_l14b_3p2>;
+
+ spi-max-frequency = <1000000>;
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <2400>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_irq>, <&ts_reset>;
+ };
+};
+
&swr1 {
status = "okay";
wcd_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
- qcom,tx-port-mapping = <1 1 2 3>;
+ qcom,tx-port-mapping = <2 2 3 4>;
};
};
bias-pull-down;
};
+ ts_irq: ts-irq-state {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ ts_reset: ts-reset-state {
+ pins = "gpio24";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
wcd_default: wcd-reset-n-active-state {
pins = "gpio108";
function = "gpio";
linux,pci-domain = <0>;
num-lanes = <2>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
-
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
+ msi-map = <0x0 &gic_its 0x1400 0x1>,
+ <0x100 &gic_its 0x1401 0x1>;
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>;
linux,pci-domain = <1>;
num-lanes = <2>;
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
-
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
+ msi-map = <0x0 &gic_its 0x1480 0x1>,
+ <0x100 &gic_its 0x1481 0x1>;
iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
<0x100 &apps_smmu 0x1481 0x1>;
ufs_mem_phy: phy@1d80000 {
compatible = "qcom,sm8550-qmp-ufs-phy";
reg = <0x0 0x01d80000 0x0 0x2000>;
- clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
- clock-names = "ref", "ref_aux";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&tcsr TCSR_UFS_CLKREF_EN>;
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
power-domains = <&gcc UFS_MEM_PHY_GDSC>;
iommus = <&apps_smmu 0x60 0x0>;
dma-coherent;
+ operating-points-v2 = <&ufs_opp_table>;
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
- freq-table-hz =
- <75000000 300000000>,
- <0 0>,
- <0 0>,
- <75000000 300000000>,
- <100000000 403000000>,
- <0 0>,
- <0 0>,
- <0 0>;
qcom,ice = <&ice>;
status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <75000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <150000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
ice: crypto@1d88000 {
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
+ #cooling-cells = <2>;
status = "disabled";
};
};
- dmic02_default: dmic02-default-state {
+ dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
spmi_bus: spmi@c400000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c400000 0 0x3000>,
- <0 0x0c500000 0 0x4000000>,
+ <0 0x0c500000 0 0x400000>,
<0 0x0c440000 0 0x80000>,
<0 0x0c4c0000 0 0x20000>,
<0 0x0c42d000 0 0x4000>;
reg = <3>;
iommus = <&apps_smmu 0x1003 0x80>,
<&apps_smmu 0x1063 0x0>;
+ dma-coherent;
};
compute-cb@4 {
reg = <4>;
iommus = <&apps_smmu 0x1004 0x80>,
<&apps_smmu 0x1064 0x0>;
+ dma-coherent;
};
compute-cb@5 {
reg = <5>;
iommus = <&apps_smmu 0x1005 0x80>,
<&apps_smmu 0x1065 0x0>;
+ dma-coherent;
};
compute-cb@6 {
reg = <6>;
iommus = <&apps_smmu 0x1006 0x80>,
<&apps_smmu 0x1066 0x0>;
+ dma-coherent;
};
compute-cb@7 {
reg = <7>;
iommus = <&apps_smmu 0x1007 0x80>,
<&apps_smmu 0x1067 0x0>;
+ dma-coherent;
};
};
iommus = <&apps_smmu 0x1961 0x0>,
<&apps_smmu 0x0c01 0x20>,
<&apps_smmu 0x19c1 0x10>;
+ dma-coherent;
};
compute-cb@2 {
iommus = <&apps_smmu 0x1962 0x0>,
<&apps_smmu 0x0c02 0x20>,
<&apps_smmu 0x19c2 0x10>;
+ dma-coherent;
};
compute-cb@3 {
iommus = <&apps_smmu 0x1963 0x0>,
<&apps_smmu 0x0c03 0x20>,
<&apps_smmu 0x19c3 0x10>;
+ dma-coherent;
};
compute-cb@4 {
iommus = <&apps_smmu 0x1964 0x0>,
<&apps_smmu 0x0c04 0x20>,
<&apps_smmu 0x19c4 0x10>;
+ dma-coherent;
};
compute-cb@5 {
iommus = <&apps_smmu 0x1965 0x0>,
<&apps_smmu 0x0c05 0x20>,
<&apps_smmu 0x19c5 0x10>;
+ dma-coherent;
};
compute-cb@6 {
iommus = <&apps_smmu 0x1966 0x0>,
<&apps_smmu 0x0c06 0x20>,
<&apps_smmu 0x19c6 0x10>;
+ dma-coherent;
};
compute-cb@7 {
iommus = <&apps_smmu 0x1967 0x0>,
<&apps_smmu 0x0c07 0x20>,
<&apps_smmu 0x19c7 0x10>;
+ dma-coherent;
};
compute-cb@8 {
iommus = <&apps_smmu 0x1968 0x0>,
<&apps_smmu 0x0c08 0x20>,
<&apps_smmu 0x19c8 0x10>;
+ dma-coherent;
};
/* note: secure cb9 in downstream */
polling-delay = <0>;
thermal-sensors = <&tsens2 1>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu0_junction_config>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
thermal-engine-config {
temperature = <125000>;
polling-delay = <0>;
thermal-sensors = <&tsens2 2>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu1_junction_config>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
thermal-engine-config {
temperature = <125000>;
polling-delay = <0>;
thermal-sensors = <&tsens2 3>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu2_junction_config>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
thermal-engine-config {
temperature = <125000>;
polling-delay = <0>;
thermal-sensors = <&tsens2 4>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu3_junction_config>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
thermal-engine-config {
temperature = <125000>;
polling-delay = <0>;
thermal-sensors = <&tsens2 5>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu4_junction_config>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
thermal-engine-config {
temperature = <125000>;
polling-delay = <0>;
thermal-sensors = <&tsens2 6>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu5_junction_config>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
thermal-engine-config {
temperature = <125000>;
polling-delay = <0>;
thermal-sensors = <&tsens2 7>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu6_junction_config>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
thermal-engine-config {
temperature = <125000>;
polling-delay = <0>;
thermal-sensors = <&tsens2 8>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu7_junction_config>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
thermal-engine-config {
temperature = <125000>;
};
};
+ sound {
+ compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard";
+ model = "SM8650-MTP";
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT";
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
RPMH_REGULATOR_MODE_HPM>;
};
};
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "m";
+
+ vdd-l1-l2-supply = <&vreg_s1c_1p2>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6c_1p8>;
+ vdd-l6-supply = <&vreg_bob1>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1m_1p1: ldo1 {
+ regulator-name = "vreg_l1m_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_2p8: ldo6 {
+ regulator-name = "vreg_l6m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p96: ldo7 {
+ regulator-name = "vreg_l7m_2p96";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "n";
+
+ vdd-l1-l2-supply = <&vreg_s1c_1p2>;
+ vdd-l3-l4-supply = <&vreg_s6c_1p8>;
+ vdd-l5-supply = <&vreg_bob2>;
+ vdd-l6-supply = <&vreg_bob2>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p056: ldo2 {
+ regulator-name = "vreg_l2n_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_1p8: ldo3 {
+ regulator-name = "vreg_l3n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_1p8: ldo4 {
+ regulator-name = "vreg_l4n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_2p8: ldo5 {
+ regulator-name = "vreg_l5n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_2p8: ldo6 {
+ regulator-name = "vreg_l6n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_3p3: ldo7 {
+ regulator-name = "vreg_l7n_3p3";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
};
&dispcc {
reg = <1>;
pmic_glink_ss_in: endpoint {
- remote-endpoint = <&usb_1_dwc3_ss>;
+ remote-endpoint = <&redriver_ss_out>;
};
};
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&wcd_usbss_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ sound {
+ compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard";
+ model = "SM8650-QRD";
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC1", "MIC BIAS1",
+ "AMIC2", "MIC BIAS2",
+ "AMIC3", "MIC BIAS3",
+ "AMIC4", "MIC BIAS3",
+ "AMIC5", "MIC BIAS4",
+ "TX SWR_INPUT0", "ADC1_OUTPUT",
+ "TX SWR_INPUT1", "ADC2_OUTPUT",
+ "TX SWR_INPUT2", "ADC3_OUTPUT",
+ "TX SWR_INPUT3", "ADC4_OUTPUT";
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ codec {
+ sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
};
};
};
regulator-always-on;
regulator-boot-on;
};
+
+ wcd939x: audio-codec {
+ compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec";
+
+ pinctrl-0 = <&wcd_default>;
+ pinctrl-names = "default";
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ reset-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+
+ vdd-buck-supply = <&vreg_l15b_1p8>;
+ vdd-rxtx-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob1>;
+
+ #sound-dai-cells = <1>;
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ wcd_codec_headset_in: endpoint {
+ remote-endpoint = <&wcd_usbss_headset_out>;
+ };
+ };
+ };
};
&apps_rsc {
RPMH_REGULATOR_MODE_HPM>;
};
};
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "m";
+
+ vdd-l1-l2-supply = <&vreg_s1c_1p2>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6c_1p8>;
+ vdd-l6-supply = <&vreg_bob1>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1m_1p1: ldo1 {
+ regulator-name = "vreg_l1m_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_2p8: ldo6 {
+ regulator-name = "vreg_l6m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p96: ldo7 {
+ regulator-name = "vreg_l7m_2p96";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "n";
+
+ vdd-l1-l2-supply = <&vreg_s1c_1p2>;
+ vdd-l3-l4-supply = <&vreg_s6c_1p8>;
+ vdd-l5-supply = <&vreg_bob2>;
+ vdd-l6-supply = <&vreg_bob2>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p056: ldo2 {
+ regulator-name = "vreg_l2n_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_1p8: ldo3 {
+ regulator-name = "vreg_l3n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_1p8: ldo4 {
+ regulator-name = "vreg_l4n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_2p8: ldo5 {
+ regulator-name = "vreg_l5n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_2p8: ldo6 {
+ regulator-name = "vreg_l6n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_3p3: ldo7 {
+ regulator-name = "vreg_l7n_3p3";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
};
&dispcc {
status = "okay";
};
+&i2c3 {
+ status = "okay";
+
+ wcd_usbss: typec-mux@e {
+ compatible = "qcom,wcd9395-usbss", "qcom,wcd9390-usbss";
+ reg = <0xe>;
+
+ vdd-supply = <&vreg_l15b_1p8>;
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_HIGH>;
+
+ mode-switch;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ wcd_usbss_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ wcd_usbss_headset_out: endpoint {
+ remote-endpoint = <&wcd_codec_headset_in>;
+ };
+ };
+ };
+ };
+};
+
+&i2c6 {
+ status = "okay";
+
+ typec-mux@1c {
+ compatible = "onnn,nb7vpq904m";
+ reg = <0x1c>;
+
+ vcc-supply = <&vreg_l15b_1p8>;
+
+ retimer-switch;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ redriver_ss_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ redriver_ss_in: endpoint {
+ data-lanes = <3 2 1 0>;
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+ };
+ };
+};
+
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
status = "okay";
};
+&lpass_tlmm {
+ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
&mdss {
status = "okay";
};
status = "okay";
};
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ data-lanes = <0 1>;
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+};
+
&mdss_mdp {
status = "okay";
};
status = "okay";
};
+&qup_i2c3_data_clk {
+ /* Use internal I2C pull-up */
+ bias-pull-up = <2200>;
+};
+
&qupv3_id_0 {
status = "okay";
};
};
};
+&swr0 {
+ status = "okay";
+
+ /* WSA8845, Speaker Left */
+ left_spkr: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&lpass_tlmm 21 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l3c_1p2>;
+ };
+
+ /* WSA8845, Speaker Right */
+ right_spkr: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ pinctrl-0 = <&spkr_2_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l3c_1p2>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ /* WCD9395 RX */
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010e00";
+ reg = <0 4>;
+
+ /*
+ * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R)
+ * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH)
+ * WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R)
+ * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO)
+ * WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R)
+ * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R)
+ */
+ qcom,rx-port-mapping = <1 2 3 4 5 9>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ /* WCD9395 TX */
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010e00";
+ reg = <0 3>;
+
+ /*
+ * WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
+ * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
+ * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7)
+ * WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11)
+ */
+ qcom,tx-port-mapping = <2 2 3 4>;
+ };
+};
+
&tlmm {
/* Reserved I/Os for NFC */
gpio-reserved-ranges = <32 8>, <74 1>;
bias-pull-down;
};
+ spkr_2_sd_n_active: spkr-2-sd-n-active-state {
+ pins = "gpio77";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
ts_irq: ts-irq-state {
pins = "gpio161";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio107";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
};
&uart14 {
};
&usb_1_dwc3_ss {
- remote-endpoint = <&pmic_glink_ss_in>;
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
&usb_1_hsphy {
vdda-phy-supply = <&vreg_l3i_1p2>;
vdda-pll-supply = <&vreg_l3g_0p91>;
+ orientation-switch;
+
status = "okay";
};
+&usb_dp_qmpphy_dp_in {
+ remote-endpoint = <&mdss_dp0_out>;
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&redriver_ss_in>;
+};
+
+&usb_dp_qmpphy_usb_ss_in {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+};
+
&xo_board {
clock-frequency = <76800000>;
};
no-map;
};
+ qlink_logging_mem: qlink-logging@84800000 {
+ reg = <0 0x84800000 0 0x200000>;
+ no-map;
+ };
+
mpss_dsm_mem: mpss-dsm@86b00000 {
reg = <0 0x86b00000 0 0x4900000>;
no-map;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
clock-names = "se";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
<0 0x60100000 0 0x100000>;
reg-names = "parf", "dbi", "elbi", "atu", "config";
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>;
+ msi-map = <0x0 &gic_its 0x1400 0x1>,
+ <0x100 &gic_its 0x1401 0x1>;
+ msi-map-mask = <0xff00>;
+
linux,pci-domain = <0>;
num-lanes = <2>;
bus-range = <0 0xff>;
"atu",
"config";
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>;
+ msi-map = <0x0 &gic_its 0x1480 0x1>,
+ <0x100 &gic_its 0x1481 0x1>;
+ msi-map-mask = <0xff00>;
+
linux,pci-domain = <1>;
num-lanes = <2>;
bus-range = <0 0xff>;
compatible = "qcom,sm8650-qmp-ufs-phy";
reg = <0 0x01d80000 0 0x2000>;
- clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&tcsr TCSR_UFS_CLKREF_EN>;
clock-names = "ref",
- "ref_aux";
+ "ref_aux",
+ "qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
"mss";
memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
- <&mpss_dsm_mem>, <&mpss_dsm_mem_2>;
+ <&mpss_dsm_mem>, <&mpss_dsm_mem_2>,
+ <&qlink_logging_mem>;
qcom,qmp = <&aoss_qmp>;
};
};
- dmic02_default: dmic02-default-state {
+ dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
spmi_bus: spmi@c400000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c400000 0 0x3000>,
- <0 0x0c500000 0 0x4000000>,
+ <0 0x0c500000 0 0x400000>,
<0 0x0c440000 0 0x80000>,
<0 0x0c4c0000 0 0x20000>,
<0 0x0c42d000 0 0x4000>;
iommus = <&apps_smmu 0x1003 0x80>,
<&apps_smmu 0x1043 0x20>;
+ dma-coherent;
};
compute-cb@4 {
iommus = <&apps_smmu 0x1004 0x80>,
<&apps_smmu 0x1044 0x20>;
+ dma-coherent;
};
compute-cb@5 {
iommus = <&apps_smmu 0x1005 0x80>,
<&apps_smmu 0x1045 0x20>;
+ dma-coherent;
};
compute-cb@6 {
iommus = <&apps_smmu 0x1006 0x80>,
<&apps_smmu 0x1046 0x20>;
+ dma-coherent;
};
compute-cb@7 {
iommus = <&apps_smmu 0x1007 0x40>,
<&apps_smmu 0x1067 0x0>,
<&apps_smmu 0x1087 0x0>;
+ dma-coherent;
};
};
iommus = <&apps_smmu 0x1961 0x0>,
<&apps_smmu 0x0c01 0x20>,
<&apps_smmu 0x19c1 0x0>;
+ dma-coherent;
};
compute-cb@2 {
iommus = <&apps_smmu 0x1962 0x0>,
<&apps_smmu 0x0c02 0x20>,
<&apps_smmu 0x19c2 0x0>;
+ dma-coherent;
};
compute-cb@3 {
iommus = <&apps_smmu 0x1963 0x0>,
<&apps_smmu 0x0c03 0x20>,
<&apps_smmu 0x19c3 0x0>;
+ dma-coherent;
};
compute-cb@4 {
iommus = <&apps_smmu 0x1964 0x0>,
<&apps_smmu 0x0c04 0x20>,
<&apps_smmu 0x19c4 0x0>;
+ dma-coherent;
};
compute-cb@5 {
iommus = <&apps_smmu 0x1965 0x0>,
<&apps_smmu 0x0c05 0x20>,
<&apps_smmu 0x19c5 0x0>;
+ dma-coherent;
};
compute-cb@6 {
iommus = <&apps_smmu 0x1966 0x0>,
<&apps_smmu 0x0c06 0x20>,
<&apps_smmu 0x19c6 0x0>;
+ dma-coherent;
};
compute-cb@7 {
iommus = <&apps_smmu 0x1967 0x0>,
<&apps_smmu 0x0c07 0x20>,
<&apps_smmu 0x19c7 0x0>;
+ dma-coherent;
};
compute-cb@8 {
iommus = <&apps_smmu 0x1968 0x0>,
<&apps_smmu 0x0c08 0x20>,
<&apps_smmu 0x19c8 0x0>;
+ dma-coherent;
};
};
};
serial0 = &uart21;
};
+ wcd938x: audio-codec {
+ compatible = "qcom,wcd9385-codec";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcd_default>;
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+
+ vdd-buck-supply = <&vreg_l15b_1p8>;
+ vdd-rxtx-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob1>;
+
+ #sound-dai-cells = <1>;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
+ sound {
+ compatible = "qcom,x1e80100-sndcard";
+ model = "X1E80100-CRD";
+ audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT",
+ "TwitterLeft IN", "WSA WSA_SPK2 OUT",
+ "WooferRight IN", "WSA2 WSA_SPK2 OUT",
+ "TwitterRight IN", "WSA2 WSA_SPK2 OUT",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC2", "MIC BIAS2",
+ "VA DMIC0", "MIC BIAS3",
+ "VA DMIC1", "MIC BIAS3",
+ "VA DMIC2", "MIC BIAS1",
+ "VA DMIC3", "MIC BIAS1",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "TX SWR_INPUT1", "ADC2_OUTPUT";
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&left_woofer>, <&left_tweeter>,
+ <&swr0 0>, <&lpass_wsamacro 0>,
+ <&right_woofer>, <&right_tweeter>,
+ <&swr3 0>, <&lpass_wsa2macro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+ };
+
+ codec {
+ sound-dai = <&lpass_vamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
};
};
+&i2c0 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ touchpad@15 {
+ compatible = "hid-over-i2c";
+ reg = <0x15>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&tpad_default>;
+ pinctrl-names = "default";
+
+ wakeup-source;
+ };
+
+ keyboard@3a {
+ compatible = "hid-over-i2c";
+ reg = <0x3a>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&kybd_default>;
+ pinctrl-names = "default";
+
+ wakeup-source;
+ };
+};
+
+&i2c8 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ touchscreen@10 {
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&ts0_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&lpass_tlmm {
+ spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+ pins = "gpio12";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ spkr_23_sd_n_active: spkr-23-sd-n-active-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&lpass_vamacro {
+ pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+ pinctrl-names = "default";
+
+ vdd-micb-supply = <&vreg_l1b_1p8>;
+ qcom,dmic-sample-rate = <4800000>;
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp3 {
+ compatible = "qcom,x1e80100-dp";
+ /delete-property/ #sound-dai-cells;
+
+ data-lanes = <0 1 2 3>;
+
+ status = "okay";
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ power-supply = <&vreg_edp_3p3>;
+
+ port {
+ edp_panel_in: endpoint {
+ remote-endpoint = <&mdss_dp3_out>;
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+ mdss_dp3_out: endpoint {
+ remote-endpoint = <&edp_panel_in>;
+ };
+ };
+ };
+};
+
+&mdss_dp3_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&pcie4 {
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie6a {
+ status = "okay";
+};
+
+&pcie6a_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&qupv3_0 {
+ status = "okay";
+};
+
+&qupv3_1 {
+ status = "okay";
+};
+
&qupv3_2 {
status = "okay";
};
+&remoteproc_adsp {
+ firmware-name = "qcom/x1e80100/adsp.mbn",
+ "qcom/x1e80100/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/x1e80100/cdsp.mbn",
+ "qcom/x1e80100/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&swr0 {
+ status = "okay";
+
+ /* WSA8845, Left Woofer */
+ left_woofer: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ pinctrl-0 = <&spkr_01_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "WooferLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ };
+
+ /* WSA8845, Left Tweeter */
+ left_tweeter: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ /* pinctrl in left_woofer node because of sharing the GPIO*/
+ powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TwitterLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ /* WCD9385 RX */
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ /* WCD9385 TX */
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <1 1 2 3>;
+ };
+};
+
+&swr3 {
+ status = "okay";
+
+ /* WSA8845, Right Woofer */
+ right_woofer: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ pinctrl-0 = <&spkr_23_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "WooferRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ };
+
+ /* WSA8845, Right Tweeter */
+ right_tweeter: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ /* pinctrl in right_woofer node because of sharing the GPIO*/
+ powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TwitterRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <34 2>, /* Unused */
<44 4>, /* SPI (TPM) */
drive-strength = <16>;
bias-disable;
};
+
+ kybd_default: kybd-default-state {
+ pins = "gpio67";
+ function = "gpio";
+ bias-disable;
+ };
+
+ tpad_default: tpad-default-state {
+ pins = "gpio3";
+ function = "gpio";
+ bias-disable;
+ };
+
+ ts0_default: ts0-default-state {
+ int-n-pins {
+ pins = "gpio51";
+ function = "gpio";
+ bias-disable;
+ };
+
+ reset-n-pins {
+ pins = "gpio48";
+ function = "gpio";
+ output-high;
+ drive-strength = <16>;
+ };
+ };
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio191";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
};
&uart21 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
+
+&usb_1_ss0_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+ status = "okay";
+};
+
+&usb_1_ss0 {
+ status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+ dr_mode = "host";
+ usb-role-switch;
+};
+
+&usb_1_ss1_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+ status = "okay";
+};
+
+&usb_1_ss1 {
+ status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+ dr_mode = "host";
+ usb-role-switch;
+};
+
+&usb_1_ss2_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_ss2_qmpphy {
+ status = "okay";
+};
+
+&usb_1_ss2 {
+ status = "okay";
+};
+
+&usb_1_ss2_dwc3 {
+ dr_mode = "host";
+ usb-role-switch;
+};
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "x1e80100.dtsi"
regulator-always-on;
regulator-boot-on;
};
+
+ vreg_edp_3p3: regulator-edp-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_EDP_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&edp_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&apps_rsc {
qcom,pmic-id = "e";
vdd-l2-supply = <&vreg_s1f_0p7>;
- vdd-l3-supply = <&vph_pwr>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
vreg_l2e_0p8: ldo2 {
regulator-name = "vreg_l2e_0p8";
qcom,pmic-id = "j";
vdd-l1-supply = <&vreg_s1f_0p7>;
- vdd-l2-supply = <&vph_pwr>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
vdd-l3-supply = <&vreg_s1f_0p7>;
vdd-s5-supply = <&vph_pwr>;
};
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp3 {
+ compatible = "qcom,x1e80100-dp";
+ /delete-property/ #sound-dai-cells;
+
+ data-lanes = <0 1 2 3>;
+
+ status = "okay";
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ power-supply = <&vreg_edp_3p3>;
+
+ port {
+ edp_panel_in: endpoint {
+ remote-endpoint = <&mdss_dp3_out>;
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+ mdss_dp3_out: endpoint {
+ remote-endpoint = <&edp_panel_in>;
+ };
+ };
+ };
+};
+
+&mdss_dp3_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&pcie4 {
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie6a {
+ status = "okay";
+};
+
+&pcie6a_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&qupv3_0 {
+ status = "okay";
+};
+
+&qupv3_1 {
+ status = "okay";
+};
+
&qupv3_2 {
status = "okay";
};
+&remoteproc_adsp {
+ firmware-name = "qcom/x1e80100/adsp.mbn",
+ "qcom/x1e80100/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/x1e80100/cdsp.mbn",
+ "qcom/x1e80100/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
&tlmm {
gpio-reserved-ranges = <33 3>, /* Unused */
<44 4>, /* SPI (TPM) */
<238 1>; /* UFS Reset */
+
+ edp_reg_en: edp-reg-en-state {
+ pins = "gpio70";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
};
&uart21 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
+
+&usb_1_ss0_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+ status = "okay";
+};
+
+&usb_1_ss0 {
+ status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+ dr_mode = "host";
+ usb-role-switch;
+};
+
+&usb_1_ss1_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+ status = "okay";
+};
+
+&usb_1_ss1 {
+ status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+ dr_mode = "host";
+ usb-role-switch;
+};
+
+&usb_1_ss2_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_ss2_qmpphy {
+ status = "okay";
+};
+
+&usb_1_ss2 {
+ status = "okay";
+};
+
+&usb_1_ss2_dwc3 {
+ dr_mode = "host";
+ usb-role-switch;
+};
*/
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/ {
interrupt-parent = <&intc>;
domain-idle-states {
CLUSTER_CL4: cluster-sleep-0 {
- compatible = "arm,idle-state";
+ compatible = "domain-idle-state";
idle-state-name = "l2-ret";
arm,psci-suspend-param = <0x01000044>;
entry-latency-us = <350>;
};
CLUSTER_CL5: cluster-sleep-1 {
- compatible = "arm,idle-state";
+ compatible = "domain-idle-state";
idle-state-name = "ret-pll-off";
arm,psci-suspend-param = <0x01000054>;
entry-latency-us = <2200>;
CLUSTER_PD0: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
+ power-domains = <&SYSTEM_PD>;
};
CLUSTER_PD1: power-domain-cpu-cluster1 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
+ power-domains = <&SYSTEM_PD>;
};
CLUSTER_PD2: power-domain-cpu-cluster2 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
+ power-domains = <&SYSTEM_PD>;
+ };
+
+ SYSTEM_PD: power-domain-system {
+ #power-domain-cells = <0>;
+ /* TODO: system-wide idle states */
};
};
};
};
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <443>, <429>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ smp2p_adsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_adsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <94>, <432>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ smp2p_cdsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
<0>,
+ <&pcie4_phy>,
<0>,
+ <&pcie6a_phy>,
<0>,
- <0>,
- <0>,
- <0>,
- <0>,
- <0>;
+ <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
+ ipcc: mailbox@408000 {
+ compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
+ reg = <0 0x00408000 0 0x1000>;
+
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ #mbox-cells = <2>;
+ };
+
gpi_dma2: dma-controller@800000 {
compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00800000 0 0x60000>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
};
};
+ usb_1_ss0_hsphy: phy@fd3000 {
+ compatible = "qcom,x1e80100-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0 0x00fd3000 0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss0_qmpphy: phy@fd5000 {
+ compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
+ reg = <0 0x00fd5000 0 0x4000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss1_hsphy: phy@fd9000 {
+ compatible = "qcom,x1e80100-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0 0x00fd9000 0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss1_qmpphy: phy@fda000 {
+ compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
+ reg = <0 0x00fda000 0 0x4000>;
+
+ clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+ <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss2_hsphy: phy@fde000 {
+ compatible = "qcom,x1e80100-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0 0x00fde000 0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss2_qmpphy: phy@fdf000 {
+ compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
+ reg = <0 0x00fdf000 0 0x4000>;
+
+ clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
+ <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
+ };
+
cnoc_main: interconnect@1500000 {
compatible = "qcom,x1e80100-cnoc-main";
reg = <0 0x1500000 0 0x14400>;
#interconnect-cells = <2>;
};
+ pcie6a: pci@1bf8000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-x1e80100";
+ reg = <0 0x01bf8000 0 0x3000>,
+ <0 0x70000000 0 0xf1d>,
+ <0 0x70000f20 0 0xa8>,
+ <0 0x70001000 0 0x1000>,
+ <0 0x70100000 0 0x100000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>,
+ <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>;
+ bus-range = <0 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <7>;
+ num-lanes = <2>;
+
+ interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_6A_AUX_CLK>,
+ <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_6A_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
+ <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_6A_BCR>,
+ <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ power-domains = <&gcc GCC_PCIE_6A_GDSC>;
+
+ phys = <&pcie6a_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie6a_phy: phy@1bfc000 {
+ compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy";
+ reg = <0 0x01bfc000 0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_6A_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe";
+
+ resets = <&gcc GCC_PCIE_6A_PHY_BCR>,
+ <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
+
+ assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie6a_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie4: pci@1c08000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-x1e80100";
+ reg = <0 0x01c08000 0 0x3000>,
+ <0 0x7c000000 0 0xf1d>,
+ <0 0x7c000f40 0 0xa8>,
+ <0 0x7c001000 0 0x1000>,
+ <0 0x7c100000 0 0x100000>,
+ <0 0x01c0b000 0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>,
+ <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <5>;
+ num-lanes = <2>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
+ <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
+ <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_4_BCR>,
+ <&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ power-domains = <&gcc GCC_PCIE_4_GDSC>;
+
+ phys = <&pcie4_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie4_phy: phy@1c0e000 {
+ compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
+ reg = <0 0x01c0e000 0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
+ <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_4_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe";
+
+ resets = <&gcc GCC_PCIE_4_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie4_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0 0x01f40000 0 0x20000>;
#hwlock-cells = <1>;
};
+ tcsr: clock-controller@1fc0000 {
+ compatible = "qcom,x1e80100-tcsr", "syscon";
+ reg = <0 0x01fc0000 0 0x30000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
gem_noc: interconnect@26400000 {
compatible = "qcom,x1e80100-gem-noc";
reg = <0 0x26400000 0 0x311200>;
#interconnect-cells = <2>;
};
+ lpass_wsa2macro: codec@6aa0000 {
+ compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
+ reg = <0 0x06aa0000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "wsa2-mclk";
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "WSA2";
+ };
+
+ swr3: soundwire@6ab0000 {
+ compatible = "qcom,soundwire-v2.0.0";
+ reg = <0 0x06ab0000 0 0x10000>;
+ clocks = <&lpass_wsa2macro>;
+ clock-names = "iface";
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ label = "WSA2";
+
+ pinctrl-0 = <&wsa2_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <9>;
+
+ qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
+ qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ lpass_rxmacro: codec@6ac0000 {
+ compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
+ reg = <0 0x06ac0000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ swr1: soundwire@6ad0000 {
+ compatible = "qcom,soundwire-v2.0.0";
+ reg = <0 0x06ad0000 0 0x10000>;
+ clocks = <&lpass_rxmacro>;
+ clock-names = "iface";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ label = "RX";
+
+ pinctrl-0 = <&rx_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <1>;
+ qcom,dout-ports = <11>;
+
+ qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ lpass_txmacro: codec@6ae0000 {
+ compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
+ reg = <0 0x06ae0000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ lpass_wsamacro: codec@6b00000 {
+ compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
+ reg = <0 0x06b00000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "WSA";
+ };
+
+ swr0: soundwire@6b10000 {
+ compatible = "qcom,soundwire-v2.0.0";
+ reg = <0 0x06b10000 0 0x10000>;
+ clocks = <&lpass_wsamacro>;
+ clock-names = "iface";
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ label = "WSA";
+
+ pinctrl-0 = <&wsa_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <9>;
+
+ qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
+ qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ swr2: soundwire@6d30000 {
+ compatible = "qcom,soundwire-v2.0.0";
+ reg = <0 0x06d30000 0 0x10000>;
+ clocks = <&lpass_txmacro>;
+ clock-names = "iface";
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "core", "wakeup";
+ label = "TX";
+
+ pinctrl-0 = <&tx_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <1>;
+
+ qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ lpass_vamacro: codec@6d44000 {
+ compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
+ reg = <0 0x06d44000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec";
+
+ #clock-cells = <0>;
+ clock-output-names = "fsgen";
+ #sound-dai-cells = <1>;
+ };
+
+ lpass_tlmm: pinctrl@6e80000 {
+ compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
+ reg = <0 0x06e80000 0 0x20000>,
+ <0 0x07250000 0 0x10000>;
+
+ clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 23>;
+
+ tx_swr_active: tx-swr-active-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio1", "gpio2";
+ function = "swr_tx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_active: rx-swr-active-state {
+ clk-pins {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ dmic01_default: dmic01-default-state {
+ clk-pins {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ dmic23_default: dmic23-default-state {
+ clk-pins {
+ pins = "gpio8";
+ function = "dmic2_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio9";
+ function = "dmic2_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ wsa_swr_active: wsa-swr-active-state {
+ clk-pins {
+ pins = "gpio10";
+ function = "wsa_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio11";
+ function = "wsa_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ wsa2_swr_active: wsa2-swr-active-state {
+ clk-pins {
+ pins = "gpio15";
+ function = "wsa2_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio16";
+ function = "wsa2_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+ };
+
lpass_ag_noc: interconnect@7e40000 {
compatible = "qcom,x1e80100-lpass-ag-noc";
reg = <0 0x7e40000 0 0xE080>;
#interconnect-cells = <2>;
};
+ usb_2_hsphy: phy@88e0000 {
+ compatible = "qcom,x1e80100-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0 0x088e0000 0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss2: usb@a0f8800 {
+ compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
+ reg = <0 0x0a0f8800 0 0x400>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
+ <&gcc GCC_USB30_TERT_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
+ <&gcc GCC_USB30_TERT_SLEEP_CLK>,
+ <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr",
+ "noc_aggr_north",
+ "noc_aggr_south",
+ "noc_sys";
+
+ assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_TERT_MASTER_CLK>;
+ assigned-clock-rates = <19200000>,
+ <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 58 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_TERT_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_TERT_BCR>;
+
+ interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ wakeup-source;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ usb_1_ss2_dwc3: usb@a000000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a000000 0 0xcd00>;
+
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0x14a0 0x0>;
+
+ phys = <&usb_1_ss2_hsphy>,
+ <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,usb3_lpm_capable;
+
+ dma-coherent;
+
+ port {
+ usb_1_ss2_role_switch: endpoint {
+ };
+ };
+ };
+ };
+
+ usb_2: usb@a2f8800 {
+ compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
+ reg = <0 0x0a2f8800 0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_USB20_SLEEP_CLK>,
+ <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr",
+ "noc_aggr_north",
+ "noc_aggr_south",
+ "noc_sys";
+
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 50 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 49 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq";
+
+ power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB20_PRIM_BCR>;
+
+ interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ wakeup-source;
+
+ status = "disabled";
+
+ usb_2_dwc3: usb@a200000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a200000 0 0xcd00>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x14e0 0x0>;
+ phys = <&usb_2_hsphy>;
+ phy-names = "usb2-phy";
+ maximum-speed = "high-speed";
+
+ port {
+ usb_2_role_switch: endpoint {
+ };
+ };
+ };
+ };
+
+ usb_1_ss0: usb@a6f8800 {
+ compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
+ reg = <0 0x0a6f8800 0 0x400>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>,
+ <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr",
+ "noc_aggr_north",
+ "noc_aggr_south",
+ "noc_sys";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>,
+ <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 61 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ wakeup-source;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ usb_1_ss0_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a600000 0 0xcd00>;
+
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0x1420 0x0>;
+
+ phys = <&usb_1_ss0_hsphy>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,usb3_lpm_capable;
+
+ dma-coherent;
+
+ port {
+ usb_1_ss0_role_switch: endpoint {
+ };
+ };
+ };
+ };
+
+ usb_1_ss1: usb@a8f8800 {
+ compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
+ reg = <0 0x0a8f8800 0 0x400>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_USB30_SEC_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_USB30_SEC_SLEEP_CLK>,
+ <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr",
+ "noc_aggr_north",
+ "noc_aggr_south",
+ "noc_sys";
+
+ assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_SEC_MASTER_CLK>;
+ assigned-clock-rates = <19200000>,
+ <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_SEC_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_SEC_BCR>;
+
+ interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ wakeup-source;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ usb_1_ss1_dwc3: usb@a800000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a800000 0 0xcd00>;
+
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0x1460 0x0>;
+
+ phys = <&usb_1_ss1_hsphy>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,usb3_lpm_capable;
+
+ dma-coherent;
+
+ port {
+ usb_1_ss1_role_switch: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss: display-subsystem@ae00000 {
+ compatible = "qcom,x1e80100-mdss";
+ reg = <0 0x0ae00000 0 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ iommus = <&apps_smmu 0x1c00 0x2>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,x1e80100-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb0000 0 0x2008>;
+ reg-names = "mdp",
+ "vbif";
+
+ interrupts-extended = <&mdss 0>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ operating-points-v2 = <&mdp_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp0_in>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ mdss_intf4_out: endpoint {
+ remote-endpoint = <&mdss_dp1_in>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ mdss_intf5_out: endpoint {
+ remote-endpoint = <&mdss_dp3_in>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ mdss_intf6_out: endpoint {
+ remote-endpoint = <&mdss_dp2_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-514000000 {
+ opp-hz = /bits/ 64 <514000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-575000000 {
+ opp-hz = /bits/ 64 <575000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>;
+ };
+ };
+ };
+
+ mdss_dp0: displayport-controller@ae90000 {
+ compatible = "qcom,x1e80100-dp";
+ reg = <0 0xae90000 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0x600>,
+ <0 0xae91000 0 0x400>,
+ <0 0xae91400 0 0x400>;
+
+ interrupts-extended = <&mdss 12>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ operating-points-v2 = <&mdss_dp0_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp0_in: endpoint {
+ remote-endpoint = <&mdss_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp0_out: endpoint {
+ };
+ };
+ };
+
+ mdss_dp0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dp1: displayport-controller@ae98000 {
+ compatible = "qcom,x1e80100-dp";
+ reg = <0 0xae98000 0 0x200>,
+ <0 0xae98200 0 0x200>,
+ <0 0xae98400 0 0x600>,
+ <0 0xae99000 0 0x400>,
+ <0 0xae99400 0 0x400>;
+
+ interrupts-extended = <&mdss 13>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ operating-points-v2 = <&mdss_dp1_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp1_in: endpoint {
+ remote-endpoint = <&mdss_intf4_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp1_out: endpoint {
+ };
+ };
+ };
+
+ mdss_dp1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dp2: displayport-controller@ae9a000 {
+ compatible = "qcom,x1e80100-dp";
+ reg = <0 0xae9a000 0 0x200>,
+ <0 0xae9a200 0 0x200>,
+ <0 0xae9a400 0 0x600>,
+ <0 0xae9b000 0 0x400>,
+ <0 0xae9b400 0 0x400>;
+
+ interrupts-extended = <&mdss 14>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dp2_phy 0>,
+ <&mdss_dp2_phy 1>;
+
+ operating-points-v2 = <&mdss_dp2_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&mdss_dp2_phy>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dp2_in: endpoint {
+ remote-endpoint = <&mdss_intf6_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ mdss_dp2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dp3: displayport-controller@aea0000 {
+ compatible = "qcom,x1e80100-dp";
+ reg = <0 0xaea0000 0 0x200>,
+ <0 0xaea0200 0 0x200>,
+ <0 0xaea0400 0 0x600>,
+ <0 0xaea1000 0 0x400>,
+ <0 0xaea1400 0 0x400>;
+
+ interrupts-extended = <&mdss 15>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dp3_phy 0>,
+ <&mdss_dp3_phy 1>;
+
+ operating-points-v2 = <&mdss_dp3_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&mdss_dp3_phy>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp3_in: endpoint {
+ remote-endpoint = <&mdss_intf5_out>;
+
+ link-frequencies = /bits/ 64 <8100000000>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ mdss_dp3_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ };
+
+ mdss_dp2_phy: phy@aec2a00 {
+ compatible = "qcom,x1e80100-dp-phy";
+ reg = <0 0x0aec2a00 0 0x19c>,
+ <0 0x0aec2200 0 0xec>,
+ <0 0x0aec2600 0 0xec>,
+ <0 0x0aec2000 0 0x1c8>;
+
+ clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux",
+ "cfg_ahb";
+
+ power-domains = <&rpmhpd RPMHPD_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss_dp3_phy: phy@aec5a00 {
+ compatible = "qcom,x1e80100-dp-phy";
+ reg = <0 0x0aec5a00 0 0x19c>,
+ <0 0x0aec5200 0 0xec>,
+ <0 0x0aec5600 0 0xec>,
+ <0 0x0aec5000 0 0x1c8>;
+
+ clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux",
+ "cfg_ahb";
+
+ power-domains = <&rpmhpd RPMHPD_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,x1e80100-dispcc";
+ reg = <0 0x0af00000 0 0x20000>;
+ clocks = <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&sleep_clk>,
+ <0>, /* dsi0 */
+ <0>,
+ <0>, /* dsi1 */
+ <0>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
+ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
+ <&mdss_dp2_phy 0>, /* dp2 */
+ <&mdss_dp2_phy 1>,
+ <&mdss_dp3_phy 0>, /* dp3 */
+ <&mdss_dp3_phy 1>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,x1e80100-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
interrupt-controller;
};
+ aoss_qmp: power-management@c300000 {
+ compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0 0x0c300000 0 0x400>;
+ interrupt-parent = <&ipcc>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ };
+
+
tlmm: pinctrl@f100000 {
compatible = "qcom,x1e80100-tlmm";
reg = <0 0x0f100000 0 0xf00000>;
/* TX, RX */
pins = "gpio86", "gpio87";
function = "qup2_se5";
- drive-strength= <2>;
+ drive-strength = <2>;
bias-disable;
};
};
<0 0x17510000 0 0x10000>,
<0 0x17520000 0 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
- qcom,drv-count = <3>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<WAKE_TCS 2>, <CONTROL_TCS 0>;
label = "apps_rsc";
+ power-domains = <&SYSTEM_PD>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
"llcc_broadcast_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ remoteproc_adsp: remoteproc@30000000 {
+ compatible = "qcom,x1e80100-adsp-pas";
+ reg = <0 0x30000000 0 0x100>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
+ power-domain-names = "lcx",
+ "lmx";
+
+ interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&adspslpi_mem>,
+ <&q6_adsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "lpass";
+ qcom,remote-pid = <2>;
+
+ gpr {
+ compatible = "qcom,gpr";
+ qcom,glink-channels = "adsp_apps";
+ qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+ qcom,intents = <512 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ q6apm: service@1 {
+ compatible = "qcom,q6apm";
+ reg = <GPR_APM_MODULE_IID>;
+ #sound-dai-cells = <0>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6apmbedai: bedais {
+ compatible = "qcom,q6apm-lpass-dais";
+ #sound-dai-cells = <1>;
+ };
+
+ q6apmdai: dais {
+ compatible = "qcom,q6apm-dais";
+ iommus = <&apps_smmu 0x1001 0x80>,
+ <&apps_smmu 0x1061 0x0>;
+ };
+ };
+
+ q6prm: service@2 {
+ compatible = "qcom,q6prm";
+ reg = <GPR_PRM_MODULE_IID>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6prmcc: clock-controller {
+ compatible = "qcom,q6prm-lpass-clocks";
+ #clock-cells = <2>;
+ };
+ };
+ };
+ };
+ };
+
+ remoteproc_cdsp: remoteproc@32300000 {
+ compatible = "qcom,x1e80100-cdsp-pas";
+ reg = <0 0x32300000 0 0x1400000>;
+
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_NSP>;
+ power-domain-names = "cx",
+ "mxc",
+ "nsp";
+
+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&cdsp_mem>,
+ <&q6_cdsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_cdsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "cdsp";
+ qcom,remote-pid = <5>;
+ };
+ };
};
timer {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 713>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 714>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 715>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 716>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 717>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen4";
- reg = <0 0xe6800000 0 0x800>;
+ reg = <0 0xe6800000 0 0x1000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen4";
- reg = <0 0xe6810000 0 0x800>;
+ reg = <0 0xe6810000 0 0x1000>;
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 713>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 714>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 715>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 716>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 717>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the standalone R-Car V4H White Hawk CPU board
+ *
+ * Copyright (C) 2023 Glider bv
+ */
+
+/dts-v1/;
+#include "r8a779g0-white-hawk-cpu.dtsi"
+
+/ {
+ model = "Renesas White Hawk CPU board based on r8a779g0";
+};
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the White Hawk CPU board
+ * Device Tree Source for the R-Car V4H White Hawk CPU board
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include "r8a779g0.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
+#include "white-hawk-cpu-common.dtsi"
/ {
model = "Renesas White Hawk CPU board";
compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
-
- aliases {
- ethernet0 = &avb0;
- serial0 = &hscif0;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:921600n8";
- };
-
- keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&keys_pins>;
- pinctrl-names = "default";
-
- key-1 {
- gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_1>;
- label = "SW47";
- wakeup-source;
- debounce-interval = <20>;
- };
-
- key-2 {
- gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_2>;
- label = "SW48";
- wakeup-source;
- debounce-interval = <20>;
- };
-
- key-3 {
- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_3>;
- label = "SW49";
- wakeup-source;
- debounce-interval = <20>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-1 {
- gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <1>;
- };
-
- led-2 {
- gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <2>;
- };
-
- led-3 {
- gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <3>;
- };
- };
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-
- memory@480000000 {
- device_type = "memory";
- reg = <0x4 0x80000000 0x0 0x80000000>;
- };
-
- memory@600000000 {
- device_type = "memory";
- reg = <0x6 0x00000000 0x1 0x00000000>;
- };
-
- mini-dp-con {
- compatible = "dp-connector";
- label = "CN5";
- type = "mini";
-
- port {
- mini_dp_con_in: endpoint {
- remote-endpoint = <&sn65dsi86_out>;
- };
- };
- };
-
- reg_1p2v: regulator-1p2v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sn65dsi86_refclk: clk-x6 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <38400000>;
- };
-};
-
-&avb0 {
- pinctrl-0 = <&avb0_pins>;
- pinctrl-names = "default";
- phy-handle = <&phy0>;
- tx-internal-delay-ps = <2000>;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0022.1622",
- "ethernet-phy-ieee802.3-c22";
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio7>;
- interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
- };
-};
-
-&dsi0 {
- status = "okay";
-
- ports {
- port@1 {
- dsi0_out: endpoint {
- remote-endpoint = <&sn65dsi86_in>;
- data-lanes = <1 2 3 4>;
- };
- };
- };
-};
-
-&du {
- status = "okay";
-};
-
-&extal_clk {
- clock-frequency = <16666666>;
-};
-
-&extalr_clk {
- clock-frequency = <32768>;
-};
-
-&hscif0 {
- pinctrl-0 = <&hscif0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- io_expander_a: gpio@20 {
- compatible = "onnn,pca9654";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- eeprom@50 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "cpu-board";
- reg = <0x50>;
- pagesize = <8>;
- };
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- clock-frequency = <400000>;
-
- bridge@2c {
- compatible = "ti,sn65dsi86";
- reg = <0x2c>;
-
- clocks = <&sn65dsi86_refclk>;
- clock-names = "refclk";
-
- interrupt-parent = <&intc_ex>;
- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
-
- enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
-
- vccio-supply = <®_1p8v>;
- vpll-supply = <®_1p8v>;
- vcca-supply = <®_1p2v>;
- vcc-supply = <®_1p2v>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- sn65dsi86_in: endpoint {
- remote-endpoint = <&dsi0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- sn65dsi86_out: endpoint {
- remote-endpoint = <&mini_dp_con_in>;
- };
- };
- };
- };
-};
-
-&mmc0 {
- pinctrl-0 = <&mmc_pins>;
- pinctrl-1 = <&mmc_pins>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- bus-width = <8>;
- no-sd;
- no-sdio;
- non-removable;
- full-pwr-cycle-in-suspend;
- status = "okay";
-};
-
-&pfc {
- pinctrl-0 = <&scif_clk_pins>;
- pinctrl-names = "default";
-
- avb0_pins: avb0 {
- mux {
- groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
- "avb0_txcrefclk";
- function = "avb0";
- };
-
- pins_mdio {
- groups = "avb0_mdio";
- drive-strength = <21>;
- };
-
- pins_mii {
- groups = "avb0_rgmii";
- drive-strength = <21>;
- };
-
- };
- hscif0_pins: hscif0 {
- groups = "hscif0_data";
- function = "hscif0";
- };
-
- i2c0_pins: i2c0 {
- groups = "i2c0";
- function = "i2c0";
- };
-
- i2c1_pins: i2c1 {
- groups = "i2c1";
- function = "i2c1";
- };
-
- keys_pins: keys {
- pins = "GP_5_0", "GP_5_1", "GP_5_2";
- bias-pull-up;
- };
-
- mmc_pins: mmc {
- groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
- function = "mmc";
- power-source = <1800>;
- };
-
- qspi0_pins: qspi0 {
- groups = "qspi0_ctrl", "qspi0_data4";
- function = "qspi0";
- };
-
- scif_clk_pins: scif_clk {
- groups = "scif_clk";
- function = "scif_clk";
- };
-};
-
-&rpc {
- pinctrl-0 = <&qspi0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- flash@0 {
- compatible = "spansion,s25fs512s", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
- spi-rx-bus-width = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- boot@0 {
- reg = <0x0 0x1200000>;
- read-only;
- };
- user@1200000 {
- reg = <0x1200000 0x2e00000>;
- };
- };
- };
-};
-
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
-&scif_clk {
- clock-frequency = <24000000>;
};
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the White Hawk CPU and BreakOut boards
+ * Device Tree Source for the R-Car V4H White Hawk CPU and BreakOut boards
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a779g0-white-hawk-cpu.dtsi"
-#include "r8a779g0-white-hawk-csi-dsi.dtsi"
-#include "r8a779g0-white-hawk-ethernet.dtsi"
+#include "white-hawk-common.dtsi"
/ {
model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0";
-
- can_transceiver0: can-phy0 {
- compatible = "nxp,tjr1443";
- #phy-cells = <0>;
- enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- max-bitrate = <5000000>;
- };
-};
-
-&can_clk {
- clock-frequency = <40000000>;
-};
-
-&canfd {
- pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- channel0 {
- status = "okay";
- phys = <&can_transceiver0>;
- };
-
- channel1 {
- status = "okay";
- };
-};
-
-&i2c0 {
- eeprom@51 {
- compatible = "rohm,br24g01", "atmel,24c01";
- label = "breakout-board";
- reg = <0x51>;
- pagesize = <8>;
- };
-};
-
-&pfc {
- can_clk_pins: can-clk {
- groups = "can_clk";
- function = "can_clk";
- };
-
- canfd0_pins: canfd0 {
- groups = "canfd0_data";
- function = "canfd0";
- };
-
- canfd1_pins: canfd1 {
- groups = "canfd1_data";
- function = "canfd1";
- };
};
};
};
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
- /* External SCIF clock - to be overridden by boards that provide it */
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ /* External SCIF clocks - to be overridden by boards that provide them */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
+ scif_clk2: scif2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 713>;
clock-names = "fck";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 714>;
clock-names = "fck";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 715>;
clock-names = "fck";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 716>;
clock-names = "fck";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 717>;
clock-names = "fck";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 516>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
- <&scif_clk>;
+ <&scif_clk2>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x35>, <&dmac0 0x34>,
<&dmac1 0x35>, <&dmac1 0x34>;
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779g0",
"renesas,etheravb-rcar-gen4";
- reg = <0 0xe6800000 0 0x800>;
+ reg = <0 0xe6800000 0 0x1000>;
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779g0",
"renesas,etheravb-rcar-gen4";
- reg = <0 0xe6810000 0 0x800>;
+ reg = <0 0xe6810000 0 0x1000>;
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 705>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
- <&scif_clk>;
+ <&scif_clk2>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>,
<&dmac1 0x59>, <&dmac1 0x58>;
};
};
+ mmc0: mmc@ee140000 {
+ compatible = "renesas,sdhi-r8a779g0",
+ "renesas,rcar-gen4-sdhi";
+ reg = <0 0xee140000 0 0x2000>;
+ interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 706>,
+ <&cpg CPG_CORE R8A779G0_CLK_SD0H>;
+ clock-names = "core", "clkh";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 706>;
+ max-frequency = <200000000>;
+ iommus = <&ipmmu_ds0 32>;
+ status = "disabled";
+ };
+
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a779g0-rpc-if",
+ "renesas,rcar-gen4-rpc-if";
+ reg = <0 0xee200000 0 0x200>,
+ <0 0x08000000 0 0x04000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 629>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 629>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
ipmmu_rt0: iommu@ee480000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
#iommu-cells = <1>;
};
- mmc0: mmc@ee140000 {
- compatible = "renesas,sdhi-r8a779g0",
- "renesas,rcar-gen4-sdhi";
- reg = <0 0xee140000 0 0x2000>;
- interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 706>,
- <&cpg CPG_CORE R8A779G0_CLK_SD0H>;
- clock-names = "core", "clkh";
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 706>;
- max-frequency = <200000000>;
- iommus = <&ipmmu_ds0 32>;
- status = "disabled";
- };
-
- rpc: spi@ee200000 {
- compatible = "renesas,r8a779g0-rpc-if",
- "renesas,rcar-gen4-rpc-if";
- reg = <0 0xee200000 0 0x200>,
- <0 0x08000000 0 0x04000000>,
- <0 0xee208000 0 0x100>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 629>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 629>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car V4H ES2.0 White Hawk Single board
+ *
+ * Copyright (C) 2023 Glider bv
+ */
+
+/dts-v1/;
+#include "r8a779g2.dtsi"
+#include "white-hawk-cpu-common.dtsi"
+#include "white-hawk-common.dtsi"
+
+/ {
+ model = "Renesas White Hawk Single board based on r8a779g2";
+ compatible = "renesas,white-hawk-single", "renesas,r8a779g2",
+ "renesas,r8a779g0";
+};
+
+&hscif0 {
+ uart-has-rtscts;
+};
+
+&hscif0_pins {
+ groups = "hscif0_data", "hscif0_ctrl";
+ function = "hscif0";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car V4H (R8A779G2) SoC
+ *
+ * Copyright (C) 2023 Glider bv
+ */
+
+#include "r8a779g0.dtsi"
+
+/ {
+ compatible = "renesas,r8a779g2", "renesas,r8a779g0";
+};
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the Gray Hawk CPU board
+ * Device Tree Source for the R-Car V4M Gray Hawk Single board
*
* Copyright (C) 2023 Renesas Electronics Corp.
+ * Copyright (C) 2024 Glider bv
*/
+/dts-v1/;
+
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
#include "r8a779h0.dtsi"
/ {
- model = "Renesas Gray Hawk CPU board";
- compatible = "renesas,grayhawk-cpu", "renesas,r8a779h0";
+ model = "Renesas Gray Hawk Single board based on r8a779h0";
+ compatible = "renesas,gray-hawk-single", "renesas,r8a779h0";
aliases {
- ethernet0 = &avb0;
serial0 = &hscif0;
+ ethernet0 = &avb0;
};
chosen {
};
&hscif0 {
+ pinctrl-0 = <&hscif0_pins>;
+ pinctrl-names = "default";
+
uart-has-rtscts;
status = "okay";
};
reg = <0x50>;
pagesize = <8>;
};
+
+ eeprom@51 {
+ compatible = "rohm,br24g01", "atmel,24c01";
+ label = "breakout-board";
+ reg = <0x51>;
+ pagesize = <8>;
+ };
+
+ eeprom@52 {
+ compatible = "rohm,br24g01", "atmel,24c01";
+ label = "csi-dsi-sub-board-id";
+ reg = <0x52>;
+ pagesize = <8>;
+ };
+
+ eeprom@53 {
+ compatible = "rohm,br24g01", "atmel,24c01";
+ label = "ethernet-sub-board-id";
+ reg = <0x53>;
+ pagesize = <8>;
+ };
};
&mmc0 {
power-source = <1800>;
};
- scif_clk_pins: scif_clk {
+ qspi0_pins: qspi0 {
+ groups = "qspi0_ctrl", "qspi0_data4";
+ function = "qspi0";
+ };
+
+ scif_clk_pins: scif-clk {
groups = "scif_clk";
function = "scif_clk";
};
};
+&rpc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fs512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot@0 {
+ reg = <0x0 0x1200000>;
+ read-only;
+ };
+ user@1200000 {
+ reg = <0x1200000 0x2e00000>;
+ };
+ };
+ };
+};
+
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&scif_clk {
clock-frequency = <24000000>;
};
#address-cells = <2>;
#size-cells = <2>;
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <825000>;
+ clock-latency-ns = <500000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <825000>;
+ clock-latency-ns = <500000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&a76_0>;
+ };
+ core1 {
+ cpu = <&a76_1>;
+ };
+ core2 {
+ cpu = <&a76_2>;
+ };
+ core3 {
+ cpu = <&a76_3>;
+ };
+ };
+ };
+
a76_0: cpu@0 {
compatible = "arm,cortex-a76";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
+ next-level-cache = <&L3_CA76>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ a76_1: cpu@100 {
+ compatible = "arm,cortex-a76";
+ reg = <0x100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779H0_PD_A1E0D0C1>;
+ next-level-cache = <&L3_CA76>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ a76_2: cpu@200 {
+ compatible = "arm,cortex-a76";
+ reg = <0x200>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779H0_PD_A1E0D0C2>;
+ next-level-cache = <&L3_CA76>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ a76_3: cpu@300 {
+ compatible = "arm,cortex-a76";
+ reg = <0x300>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779H0_PD_A1E0D0C3>;
+ next-level-cache = <&L3_CA76>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <400>;
+ exit-latency-us = <500>;
+ min-residency-us = <4000>;
+ };
+ };
+
+ L3_CA76: cache-controller {
+ compatible = "cache";
+ power-domains = <&sysc R8A779H0_PD_A2E0D0>;
+ cache-unified;
+ cache-level = <3>;
};
};
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif-clk {
compatible = "fixed-clock";
#size-cells = <2>;
ranges;
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a779h0-wdt",
+ "renesas,rcar-gen4-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ status = "disabled";
+ };
+
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a779h0";
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
clocks = <&cpg CPG_MOD 518>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 518>;
+ dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+ <&dmac2 0x91>, <&dmac2 0x90>;
+ dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cpg CPG_MOD 519>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 519>;
+ dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+ <&dmac2 0x93>, <&dmac2 0x92>;
+ dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cpg CPG_MOD 520>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 520>;
+ dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+ <&dmac2 0x95>, <&dmac2 0x94>;
+ dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cpg CPG_MOD 521>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 521>;
+ dmas = <&dmac1 0x97>, <&dmac1 0x96>,
+ <&dmac2 0x97>, <&dmac2 0x96>;
+ dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 514>;
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
status = "disabled";
};
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779h0",
"renesas,etheravb-rcar-gen4";
- reg = <0 0xe6800000 0 0x800>;
+ reg = <0 0xe6800000 0 0x1000>;
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 211>;
+ clock-names = "fck";
power-domains = <&sysc R8A779H0_PD_C4>;
resets = <&cpg 211>;
phy-mode = "rgmii";
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779h0",
"renesas,etheravb-rcar-gen4";
- reg = <0 0xe6810000 0 0x800>;
+ reg = <0 0xe6810000 0 0x1000>;
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 212>;
+ clock-names = "fck";
power-domains = <&sysc R8A779H0_PD_C4>;
resets = <&cpg 212>;
phy-mode = "rgmii";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
- };
+ };
avb2: ethernet@e6820000 {
compatible = "renesas,etheravb-r8a779h0",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 213>;
+ clock-names = "fck";
power-domains = <&sysc R8A779H0_PD_C4>;
resets = <&cpg 213>;
phy-mode = "rgmii";
status = "disabled";
};
+ dmac1: dma-controller@e7350000 {
+ compatible = "renesas,dmac-r8a779h0",
+ "renesas,rcar-gen4-dmac";
+ reg = <0 0xe7350000 0 0x1000>,
+ <0 0xe7300000 0 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3", "ch4",
+ "ch5", "ch6", "ch7", "ch8", "ch9",
+ "ch10", "ch11", "ch12", "ch13",
+ "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 709>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 709>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ dmac2: dma-controller@e7351000 {
+ compatible = "renesas,dmac-r8a779h0",
+ "renesas,rcar-gen4-dmac";
+ reg = <0 0xe7351000 0 0x1000>,
+ <0 0xe7310000 0 0x10000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3", "ch4",
+ "ch5", "ch6", "ch7";
+ clocks = <&cpg CPG_MOD 710>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 710>;
+ #dma-cells = <1>;
+ dma-channels = <8>;
+ };
+
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a779h0",
"renesas,rcar-gen4-sdhi";
status = "disabled";
};
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a779h0-rpc-if",
+ "renesas,rcar-gen4-rpc-if";
+ reg = <0 0xee200000 0 0x200>,
+ <0 0x08000000 0 0x04000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 629>;
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 629>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
&soc {
interrupt-parent = <&gic>;
+ cru: video@10830000 {
+ compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru";
+ reg = <0 0x10830000 0 0x400>;
+ clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
+ <&cpg CPG_MOD R9A07G043_CRU_PCLK>,
+ <&cpg CPG_MOD R9A07G043_CRU_ACLK>;
+ clock-names = "video", "apb", "axi";
+ interrupts = <SOC_PERIPHERAL_IRQ(167) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(168) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(169) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
+ resets = <&cpg R9A07G043_CRU_PRESETN>,
+ <&cpg R9A07G043_CRU_ARESETN>;
+ reset-names = "presetn", "aresetn";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+ crucsi2: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi2cru>;
+ };
+ };
+ };
+ };
+
+ csi2: csi2@10830400 {
+ compatible = "renesas,r9a07g043-csi2", "renesas,rzg2l-csi2";
+ reg = <0 0x10830400 0 0xfc00>;
+ interrupts = <SOC_PERIPHERAL_IRQ(166) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>,
+ <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
+ <&cpg CPG_MOD R9A07G043_CRU_PCLK>;
+ clock-names = "system", "video", "apb";
+ resets = <&cpg R9A07G043_CRU_PRESETN>,
+ <&cpg R9A07G043_CRU_CMN_RSTB>;
+ reset-names = "presetn", "cmn-rstb";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ csi2cru: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&crucsi2>;
+ };
+ };
+ };
+ };
+
irqc: interrupt-controller@110a0000 {
compatible = "renesas,r9a07g043u-irqc",
"renesas,rzg2l-irqc";
<SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>,
- <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>;
+ <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "nmi",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
- "bus-err";
+ "bus-err", "ec7tie1-0", "ec7tie2-0",
+ "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
+ "ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
<&cpg CPG_MOD R9A07G043_IA55_PCLK>;
clock-names = "clk", "pclk";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree overlay for the RZ/G2UL SMARC EVK with OV5645 camera
+ * connected to CSI and CRU enabled.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+#define OV5645_PARENT_I2C i2c0
+#include "rz-smarc-cru-csi-ov5645.dtsi"
+
+&ov5645 {
+ enable-gpios = <&pinctrl RZG2L_GPIO(4, 4) GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
+};
reset-names = "rst", "arst", "prst";
power-domains = <&cpg>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&du_out_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
};
vspd: vsp@10870000 {
resets = <&cpg R9A07G044_LCDC_RESET_N>;
};
+ du: display@10890000 {
+ compatible = "renesas,r9a07g044-du";
+ reg = <0 0x10890000 0 0x10000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_LCDC_RESET_N>;
+ renesas,vsps = <&vspd 0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_dsi: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g044-cpg";
reg = <0 0x11010000 0 0x10000>;
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31",
+ "bus-err", "ec7tie1-0", "ec7tie2-0",
+ "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
+ "ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
clock-names = "clk", "pclk";
reset-names = "rst", "arst", "prst";
power-domains = <&cpg>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&du_out_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
};
vspd: vsp@10870000 {
resets = <&cpg R9A07G054_LCDC_RESET_N>;
};
+ du: display@10890000 {
+ compatible = "renesas,r9a07g054-du",
+ "renesas,r9a07g044-du";
+ reg = <0 0x10890000 0 0x10000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
+ <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
+ <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_LCDC_RESET_N>;
+ renesas,vsps = <&vspd 0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_dsi: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g054-cpg";
reg = <0 0x11010000 0 0x10000>;
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31",
+ "bus-err", "ec7tie1-0", "ec7tie2-0",
+ "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
+ "ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
<&cpg CPG_MOD R9A07G054_IA55_PCLK>;
clock-names = "clk", "pclk";
clock-frequency = <0>;
};
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "nmi",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
- "bus-err";
+ "bus-err", "ec7tie1-0", "ec7tie2-0",
+ "ec7tiovf-0";
clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
<&cpg CPG_MOD R9A08G045_IA55_PCLK>;
clock-names = "clk", "pclk";
<0x0 0x12440000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+
+ wdt0: watchdog@12800800 {
+ compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt";
+ reg = <0 0x12800800 0 0x400>;
+ clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
+ <&cpg CPG_MOD R9A08G045_WDT0_CLK>;
+ clock-names = "pclk", "oscclk";
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "wdt", "perrout";
+ resets = <&cpg R9A08G045_WDT0_PRESETN>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
timer {
status = "okay";
ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi0_in: endpoint {
- };
- };
-
port@1 {
- reg = <1>;
dsi0_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&adv7535_in>;
};
};
+&du {
+ status = "okay";
+};
+
&i2c1 {
adv7535: hdmi@3d {
compatible = "adi,adv7535";
status = "okay";
ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi0_in: endpoint {
- };
- };
-
port@1 {
- reg = <1>;
dsi0_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&adv7535_in>;
};
};
+&du {
+ status = "okay";
+};
+
&i2c1 {
adv7535: hdmi@3d {
compatible = "adi,adv7535";
#endif
&pinctrl {
+#if SW_CONFIG3 == SW_ON
eth0-phy-irq-hog {
gpio-hog;
gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
input;
line-name = "eth0-phy-irq";
};
+#endif
eth0_pins: eth0 {
txc {
};
};
+#if SW_CONFIG3 == SW_ON
eth1-phy-irq-hog {
gpio-hog;
gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
input;
line-name = "eth1-phy-irq";
};
+#endif
eth1_pins: eth1 {
txc {
};
};
};
+
+&wdt0 {
+ timeout-sec = <60>;
+ status = "okay";
+};
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/ {
mmc1 = &sdhi1;
};
+ keys {
+ compatible = "gpio-keys";
+
+ key-1 {
+ interrupts = <RZG2L_GPIO(18, 0) IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&pinctrl>;
+ linux,code = <KEY_1>;
+ label = "USER_SW1";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+
+ key-2 {
+ interrupts = <RZG2L_GPIO(0, 1) IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&pinctrl>;
+ linux,code = <KEY_2>;
+ label = "USER_SW2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+
+ key-3 {
+ interrupts = <RZG2L_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&pinctrl>;
+ linux,code = <KEY_3>;
+ label = "USER_SW3";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
};
&pinctrl {
+ key-1-gpio-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "key-1-gpio-irq";
+ };
+
+ key-2-gpio-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "key-2-gpio-irq";
+ };
+
+ key-3-gpio-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "key-3-gpio-irq";
+ };
+
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */
<RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
};
};
- accel_3v3: regulator-acc-3v3 {
+ reg_t1p8v: regulator-t1p8v {
compatible = "regulator-fixed";
- regulator-name = "accel-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- hdmi_1v8: regulator-hdmi-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "hdmi-1v8";
+ regulator-name = "T1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
};
- hdmi_3v3: regulator-hdmi-3v3 {
+ pcie_1v5: regulator-pcie-1v5 {
compatible = "regulator-fixed";
- regulator-name = "hdmi-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ regulator-name = "pcie-1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&gpio_exp_77 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
- snd_3p3v: regulator-snd_3p3v {
+ pcie_3v3: regulator-pcie-3v3 {
compatible = "regulator-fixed";
- regulator-name = "snd-3.3v";
+ regulator-name = "pcie-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ gpio = <&gpio_exp_77 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
- snd_vcc5v: regulator-snd_vcc5v {
+ reg_5v: regulator-5v {
compatible = "regulator-fixed";
- regulator-name = "snd-vcc5v";
+ regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
};
wlan_en: regulator-wlan_en {
pd-gpios = <&gpio_exp_75 5 GPIO_ACTIVE_LOW>;
- avdd-supply = <&hdmi_1v8>;
- dvdd-supply = <&hdmi_1v8>;
- pvdd-supply = <&hdmi_1v8>;
- dvdd-3v-supply = <&hdmi_3v3>;
- bgvdd-supply = <&hdmi_1v8>;
+ avdd-supply = <®_t1p8v>;
+ dvdd-supply = <®_t1p8v>;
+ pvdd-supply = <®_t1p8v>;
+ dvdd-3v-supply = <®_3p3v>;
+ bgvdd-supply = <®_t1p8v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
compatible = "st,lsm9ds0-imu";
reg = <0x1d>;
- vdd-supply = <&accel_3v3>;
- vddio-supply = <&accel_3v3>;
+ vdd-supply = <®_3p3v>;
+ vddio-supply = <®_3p3v>;
};
pcm3168a: audio-codec@44 {
clocks = <&clksndsel>;
clock-names = "scki";
- VDD1-supply = <&snd_3p3v>;
- VDD2-supply = <&snd_3p3v>;
- VCCAD1-supply = <&snd_vcc5v>;
- VCCAD2-supply = <&snd_vcc5v>;
- VCCDA1-supply = <&snd_vcc5v>;
- VCCDA2-supply = <&snd_vcc5v>;
+ VDD1-supply = <®_3p3v>;
+ VDD2-supply = <®_3p3v>;
+ VCCAD1-supply = <®_5v>;
+ VCCAD2-supply = <®_5v>;
+ VCCDA1-supply = <®_5v>;
+ VCCDA2-supply = <®_5v>;
};
gyroscope@6b {
compatible = "st,lsm9ds0-gyro";
reg = <0x6b>;
- vdd-supply = <&accel_3v3>;
- vddio-supply = <&accel_3v3>;
+ vdd-supply = <®_3p3v>;
+ vddio-supply = <®_3p3v>;
};
};
};
&pciec1 {
status = "okay";
+
+ vpcie1v5-supply = <&pcie_1v5>;
+ vpcie3v3-supply = <&pcie_3v3>;
};
&pfc {
pinctrl-names = "default";
status = "okay";
+
+ gnss {
+ compatible = "u-blox,neo-m8";
+ reset-gpios = <&gpio_exp_75 6 GPIO_ACTIVE_LOW>;
+ vcc-supply = <®_3p3v>;
+ current-speed = <9600>;
+ };
};
&sdhi3 {
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the White Hawk CPU and BreakOut boards
+ * Device Tree Source for the common parts shared by the White Hawk BreakOut
+ * and White Hawk Single boards
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
-/dts-v1/;
-#include "r8a779g0-white-hawk-cpu.dtsi"
-#include "r8a779g0-white-hawk-csi-dsi.dtsi"
-#include "r8a779g0-white-hawk-ethernet.dtsi"
+#include "white-hawk-csi-dsi.dtsi"
+#include "white-hawk-ethernet.dtsi"
/ {
- model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
- compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0";
-
can_transceiver0: can-phy0 {
compatible = "nxp,tjr1443";
#phy-cells = <0>;
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the White Hawk CPU board
+ * Device Tree Source for the common parts shared by the White Hawk CPU and
+ * White Hawk Single boards
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
-#include "r8a779g0.dtsi"
-
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
- model = "Renesas White Hawk CPU board";
- compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
-
aliases {
ethernet0 = &avb0;
serial0 = &hscif0;
stdout-path = "serial0:921600n8";
};
+ sn65dsi86_refclk: clk-x6 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <38400000>;
+ };
+
keys {
compatible = "gpio-keys";
regulator-boot-on;
regulator-always-on;
};
-
- sn65dsi86_refclk: clk-x6 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <38400000>;
- };
};
&avb0 {
};
&hscif0 {
+ pinctrl-0 = <&hscif0_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
};
};
+
hscif0_pins: hscif0 {
groups = "hscif0_data";
function = "hscif0";
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board
+ * Device Tree Source for the White Hawk CSI/DSI sub-board
*
* Copyright (C) 2022 Glider bv
*/
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1)
+ * Device Tree Source for the White Hawk RAVB/Ethernet(1000Base-T1)
* sub-board
*
* Copyright (C) 2022 Glider bv
&uart5 {
pinctrl-0 = <&uart5_xfer>;
+ rts-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
};
+&pmu_io_domains {
+ pmuio1-supply = <&vcc_3v3>;
+ pmuio2-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
clock_in_out = "input";
- phy-handle = <&rtl8211e>;
+ phy-handle = <&rtl8211>;
phy-mode = "rgmii";
phy-supply = <&vcc_io>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
- rtl8211e: ethernet-phy@1 {
+ rtl8211: ethernet-phy@1 {
reg = <1>;
pinctrl-0 = <ð_phy_int_pin>, <ð_phy_reset_pin>;
pinctrl-names = "default";
status = "disabled";
ports {
- hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
hdmi_in_vop: endpoint {
remote-endpoint = <&vop_out_hdmi>;
};
};
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
};
};
port@1 {
reg = <1>;
- mipi1_in_panel: endpoint@1 {
+ mipi1_in_panel: endpoint {
remote-endpoint = <&mipi1_out_panel>;
};
};
ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
/* PERST# asserted in S3 */
- pcie-reset-suspend = <1>;
vpcie3v3-supply = <&wlan_3v3>;
vpcie1v8-supply = <&pp1800_pcie>;
ethernet0 = &gmac;
mmc0 = &sdmmc;
mmc1 = &sdhci;
- spi1 = &spi1;
- spi2 = &spi2;
- spi5 = &spi5;
};
avdd_0v9_s0: avdd-0v9-s0 {
#size-cells = <0>;
interface@0 { /* interface 0 of configuration 1 */
- compatible = "usbbda,8156.config1.0";
+ compatible = "usbifbda,8156.config1.0";
reg = <0 1>;
};
};
/ {
model = "Orange Pi RK3399 Board";
- compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
+ compatible = "xunlong,rk3399-orangepi", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;
};
&pcie0 {
- bus-scan-delay-ms = <1000>;
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
+ vpcie3v3-supply = <&vcc3v3_baseboard>;
+ vpcie12v-supply = <&dc_12v>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ pinctrl-0 = <&uart0_xfer>;
status = "okay";
};
&uart2 {
+ rts-gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
regulator-max-microvolt = <5000000>;
};
+ vcca_0v9: vcca-0v9-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcca_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcca_1v8: vcca-1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
gpio1830-supply = <&vcc_1v8>;
};
-&pmu_io_domains {
- status = "okay";
- pmu1830-supply = <&vcc_1v8>;
+&pcie0 {
+ /* PCIe PHY supplies */
+ vpcie0v9-supply = <&vcca_0v9>;
+ vpcie1v8-supply = <&vcca_1v8>;
};
-&pwm2 {
- status = "okay";
+&pcie_clkreqn_cpm {
+ rockchip,pins =
+ <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
};
&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&q7_thermal_pin>;
+
+ gpios {
+ q7_thermal_pin: q7-thermal-pin {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
i2c8 {
i2c8_xfer_a: i2c8-xfer {
rockchip,pins =
usb3 {
usb3_id: usb3-id {
rockchip,pins =
- <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
+&pmu_io_domains {
+ status = "okay";
+ pmu1830-supply = <&vcc_1v8>;
+};
+
+&pwm2 {
+ status = "okay";
+};
+
&sdhci {
/*
* Signal integrity isn't great at 200MHz but 100MHz has proven stable
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <10000000>;
+ spi-max-frequency = <108000000>;
};
};
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <10000000>;
+ spi-max-frequency = <108000000>;
};
};
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <10000000>;
+ spi-max-frequency = <108000000>;
};
};
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ spi4 = &spi4;
+ spi5 = &spi5;
};
cpus {
#size-cells = <0>;
cpu-map {
- cluster0 {
+ cluster0 { /* Cortex-A53 */
core0 {
cpu = <&cpu_l0>;
};
};
};
- cluster1 {
+ cluster1 { /* Cortex-A72 */
core0 {
cpu = <&cpu_b0>;
};
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l>;
};
cpu_l1: cpu@1 {
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l>;
};
cpu_l2: cpu@2 {
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l>;
};
cpu_l3: cpu@3 {
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l>;
};
cpu_b0: cpu@100 {
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_b>;
thermal-idle {
#cooling-cells = <2>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_b>;
thermal-idle {
#cooling-cells = <2>;
};
};
+ l2_cache_l: l2-cache-cluster0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+
+ l2_cache_b: l2-cache-cluster1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ };
+
idle-states {
entry-method = "psci";
hdmi: hdmi@ff940000 {
compatible = "rockchip,rk3399-dw-hdmi";
reg = <0x0 0xff940000 0x0 0x20000>;
+ reg-io-width = <4>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_HDMI_CTRL>,
<&cru SCLK_HDMI_SFR>,
<&cru PLL_VPLL>;
clock-names = "iahb", "isfr", "cec", "grf", "ref";
power-domains = <&power RK3399_PD_HDCP>;
- reg-io-width = <4>;
rockchip,grf = <&grf>;
#sound-dai-cells = <0>;
status = "disabled";
ports {
- hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
remote-endpoint = <&vopl_out_hdmi>;
};
};
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
};
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566-anbernic-rg-arc.dtsi"
+
+/ {
+ model = "Anbernic RG ARC-D";
+ compatible = "anbernic,rg-arc-d", "rockchip,rk3566";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ mmc2 = &sdmmc1;
+ mmc3 = &sdmmc2;
+ };
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2m1_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ touchscreen@14 {
+ compatible = "goodix,gt927";
+ reg = <0x14>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <RK_PB1 IRQ_TYPE_EDGE_FALLING>;
+ irq-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&touch_int>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+ touchscreen-inverted-y;
+ touchscreen-size-x = <640>;
+ touchscreen-size-y = <480>;
+ };
+};
+
+&pinctrl {
+ touchscreen {
+ touch_int: touch_int {
+ rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
+ <&emmc_datastrobe>, <&emmc_rstnout>;
+ pinctrl-names = "default";
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566-anbernic-rg-arc.dtsi"
+
+/ {
+ model = "Anbernic RG ARC-S";
+ compatible = "anbernic,rg-arc-s", "rockchip,rk3566";
+
+ aliases {
+ mmc1 = &sdmmc0;
+ mmc2 = &sdmmc1;
+ mmc3 = &sdmmc2;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566-anbernic-rgxx3.dtsi"
+
+/ {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&vcc_sys>;
+ pwms = <&pwm4 0 25000 0>;
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <3472000>;
+ charge-term-current-microamp = <300000>;
+ constant-charge-current-max-microamp = <2000000>;
+ constant-charge-voltage-max-microvolt = <4200000>;
+ factory-internal-resistance-micro-ohms = <117000>;
+ voltage-max-design-microvolt = <4172000>;
+ voltage-min-design-microvolt = <3400000>;
+
+ ocv-capacity-celsius = <20>;
+ ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>,
+ <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>,
+ <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>,
+ <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>,
+ <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>,
+ <3400000 0>;
+ };
+
+ /* Channels reversed for both headphones and speakers. */
+ sound {
+ compatible = "simple-audio-card";
+ pinctrl-0 = <&hp_det>;
+ pinctrl-names = "default";
+ simple-audio-card,name = "rk817_ext";
+ simple-audio-card,aux-devs = <&spk_amp>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Internal Speakers";
+ simple-audio-card,routing =
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Internal Speakers", "Speaker Amp OUTL",
+ "Internal Speakers", "Speaker Amp OUTR",
+ "Speaker Amp INL", "HPOL",
+ "Speaker Amp INR", "HPOR";
+ simple-audio-card,pin-switches = "Internal Speakers";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+ };
+
+ spk_amp: audio-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&spk_amp_enable_h>;
+ pinctrl-names = "default";
+ sound-name-prefix = "Speaker Amp";
+ };
+};
+
+&cru {
+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+ <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+ assigned-clock-rates = <32768>, <1200000000>,
+ <200000000>, <128000000>;
+};
+
+&dsi_dphy0 {
+ status = "okay";
+};
+
+&dsi0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ dsi0_in: port@0 {
+ reg = <0>;
+ dsi0_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_dsi0>;
+ };
+ };
+
+ dsi0_out: port@1 {
+ reg = <1>;
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+
+ panel: panel@0 {
+ compatible = "anbernic,rg-arc-panel", "sitronix,st7701";
+ reg = <0>;
+ backlight = <&backlight>;
+ IOVCC-supply = <&vcc3v3_lcd0_n>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rst>;
+ reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
+ rotation = <90>;
+ VCC-supply = <&vcc3v3_lcd0_n>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+};
+
+/*
+ * Device uses a non-standard six button layout for a gamepad with X,
+ * Y, and Z on the top row of buttons and A, B, and C under the bottom
+ * row.
+ */
+&gpio_keys_control {
+ button-a {
+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>;
+ label = "A";
+ linux,code = <BTN_A>;
+ };
+
+ button-b {
+ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
+ label = "B";
+ linux,code = <BTN_B>;
+ };
+
+ button-c {
+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "C";
+ linux,code = <BTN_C>;
+ };
+
+ button-left {
+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
+ label = "DPAD-LEFT";
+ linux,code = <BTN_DPAD_LEFT>;
+ };
+
+ button-r1 {
+ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
+ label = "TR";
+ linux,code = <BTN_TR>;
+ };
+
+ button-r2 {
+ gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
+ label = "TR2";
+ linux,code = <BTN_TR2>;
+ };
+
+ button-right {
+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "DPAD-RIGHT";
+ linux,code = <BTN_DPAD_RIGHT>;
+ };
+
+ button-x {
+ gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ label = "X";
+ linux,code = <BTN_X>;
+ };
+
+ button-y {
+ gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
+ label = "Y";
+ linux,code = <BTN_Y>;
+ };
+
+ button-z {
+ gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+ label = "Z";
+ linux,code = <BTN_Z>;
+ };
+};
+
+&pinctrl {
+ audio-amplifier {
+ spk_amp_enable_h: spk-amp-enable-h {
+ rockchip,pins =
+ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gpio-lcd {
+ lcd_rst: lcd-rst {
+ rockchip,pins =
+ <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins =
+ <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&rk817 {
+ rk817_charger: charger {
+ monitored-battery = <&battery>;
+ rockchip,resistor-sense-micro-ohms = <10000>;
+ rockchip,sleep-enter-current-microamp = <300000>;
+ rockchip,sleep-filter-current-microamp = <100000>;
+ };
+};
+
+&vp1 {
+ vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
+ reg = <ROCKCHIP_VOP2_EP_MIPI0>;
+ remote-endpoint = <&dsi0_in_vp1>;
+ };
+};
#include "rk3566-anbernic-rgxx3.dtsi"
/ {
+ adc-joystick {
+ compatible = "adc-joystick";
+ io-channels = <&adc_mux 0>,
+ <&adc_mux 1>,
+ <&adc_mux 2>,
+ <&adc_mux 3>;
+ pinctrl-0 = <&joy_mux_en>;
+ pinctrl-names = "default";
+ poll-interval = <60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axis@0 {
+ reg = <0>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <1023 15>;
+ linux,code = <ABS_X>;
+ };
+
+ axis@1 {
+ reg = <1>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <15 1023>;
+ linux,code = <ABS_RX>;
+ };
+
+ axis@2 {
+ reg = <2>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <15 1023>;
+ linux,code = <ABS_Y>;
+ };
+
+ axis@3 {
+ reg = <3>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <1023 15>;
+ linux,code = <ABS_RY>;
+ };
+ };
+
+ adc_mux: adc-mux {
+ compatible = "io-channel-mux";
+ channels = "left_x", "right_x", "left_y", "right_y";
+ #io-channel-cells = <1>;
+ io-channels = <&saradc 3>;
+ io-channel-names = "parent";
+ mux-controls = <&gpio_mux>;
+ settle-time-us = <100>;
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
power-supply = <&vcc_sys>;
pwms = <&pwm4 0 25000 0>;
};
+
+ gpio_mux: mux-controller {
+ compatible = "gpio-mux";
+ mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>,
+ <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+ #mux-control-cells = <0>;
+ };
};
&cru {
linux,code = <BTN_DPAD_RIGHT>;
};
+ button-thumbl {
+ gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+ label = "THUMBL";
+ linux,code = <BTN_THUMBL>;
+ };
+
+ button-thumbr {
+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "THUMBR";
+ linux,code = <BTN_THUMBR>;
+ };
+
button-y {
gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
label = "WEST";
mmc2 = &sdmmc2;
};
+ adc-joystick {
+ compatible = "adc-joystick";
+ io-channels = <&adc_mux 0>,
+ <&adc_mux 1>,
+ <&adc_mux 2>,
+ <&adc_mux 3>;
+ pinctrl-0 = <&joy_mux_en>;
+ pinctrl-names = "default";
+ poll-interval = <60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axis@0 {
+ reg = <0>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <1023 15>;
+ linux,code = <ABS_X>;
+ };
+
+ axis@1 {
+ reg = <1>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <15 1023>;
+ linux,code = <ABS_RX>;
+ };
+
+ axis@2 {
+ reg = <2>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <15 1023>;
+ linux,code = <ABS_Y>;
+ };
+
+ axis@3 {
+ reg = <3>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <1023 15>;
+ linux,code = <ABS_RY>;
+ };
+ };
+
+ adc_mux: adc-mux {
+ compatible = "io-channel-mux";
+ channels = "left_x", "right_x", "left_y", "right_y";
+ #io-channel-cells = <1>;
+ io-channels = <&saradc 3>;
+ io-channel-names = "parent";
+ mux-controls = <&gpio_mux>;
+ settle-time-us = <100>;
+ };
+
battery: battery {
compatible = "simple-battery";
charge-full-design-microamp-hours = <3472000>;
<3400000 0>;
};
+ gpio_mux: mux-controller {
+ compatible = "gpio-mux";
+ mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>,
+ <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+ #mux-control-cells = <0>;
+ };
+
gpio_spi: spi {
compatible = "spi-gpio";
pinctrl-names = "default";
linux,code = <BTN_DPAD_RIGHT>;
};
+ button-thumbl {
+ gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+ label = "THUMBL";
+ linux,code = <BTN_THUMBL>;
+ };
+
+ button-thumbr {
+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "THUMBR";
+ linux,code = <BTN_THUMBR>;
+ };
+
button-y {
gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
label = "WEST";
stdout-path = "serial2:1500000n8";
};
- adc-joystick {
- compatible = "adc-joystick";
- io-channels = <&adc_mux 0>,
- <&adc_mux 1>,
- <&adc_mux 2>,
- <&adc_mux 3>;
- pinctrl-0 = <&joy_mux_en>;
- pinctrl-names = "default";
- poll-interval = <60>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- axis@0 {
- reg = <0>;
- abs-flat = <32>;
- abs-fuzz = <32>;
- abs-range = <1023 15>;
- linux,code = <ABS_X>;
- };
-
- axis@1 {
- reg = <1>;
- abs-flat = <32>;
- abs-fuzz = <32>;
- abs-range = <15 1023>;
- linux,code = <ABS_RX>;
- };
-
- axis@2 {
- reg = <2>;
- abs-flat = <32>;
- abs-fuzz = <32>;
- abs-range = <15 1023>;
- linux,code = <ABS_Y>;
- };
-
- axis@3 {
- reg = <3>;
- abs-flat = <32>;
- abs-fuzz = <32>;
- abs-range = <1023 15>;
- linux,code = <ABS_RY>;
- };
- };
-
adc_keys: adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
};
};
- adc_mux: adc-mux {
- compatible = "io-channel-mux";
- channels = "left_x", "right_x", "left_y", "right_y";
- #io-channel-cells = <1>;
- io-channels = <&saradc 3>;
- io-channel-names = "parent";
- mux-controls = <&gpio_mux>;
- settle-time-us = <100>;
- };
-
gpio_keys_control: gpio-keys-control {
compatible = "gpio-keys";
pinctrl-0 = <&btn_pins_ctrl>;
linux,code = <BTN_START>;
};
- button-thumbl {
- gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
- label = "THUMBL";
- linux,code = <BTN_THUMBL>;
- };
-
- button-thumbr {
- gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
- label = "THUMBR";
- linux,code = <BTN_THUMBR>;
- };
-
button-up {
gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
label = "DPAD-UP";
};
};
- gpio_mux: mux-controller {
- compatible = "gpio-mux";
- mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>,
- <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
- #mux-control-cells = <0>;
- };
-
hdmi-con {
compatible = "hdmi-connector";
ddc-i2c-bus = <&i2c5>;
&pcie2x1 {
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
- disable-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-pinetab2.dtsi"
+
+/ {
+ model = "Pine64 PineTab2 v0.1";
+ compatible = "pine64,pinetab2-v0.1", "pine64,pinetab2", "rockchip,rk3566";
+};
+
+&lcd {
+ reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>;
+};
+
+&pinctrl {
+ lcd0 {
+ lcd0_rst_l: lcd0-rst-l {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc1 {
+ vmmc-supply = <&vcc3v3_sys>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-pinetab2.dtsi"
+
+/ {
+ model = "Pine64 PineTab2 v2.0";
+ compatible = "pine64,pinetab2-v2.0", "pine64,pinetab2", "rockchip,rk3566";
+};
+
+&gpio_keys {
+ pinctrl-0 = <&kb_id_det>, <&hall_int_l>;
+
+ event-hall-sensor {
+ debounce-interval = <20>;
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ label = "Hall Sensor";
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ wakeup-event-action = <EV_ACT_DEASSERTED>;
+ wakeup-source;
+ };
+};
+
+&lcd {
+ reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>;
+};
+
+&pinctrl {
+ lcd0 {
+ lcd0_rst_l: lcd0-rst-l {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hall {
+ hall_int_l: hall-int-l {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc1 {
+ vmmc-supply = <&vcc_sys>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3566.dtsi"
+
+/ {
+ chassis-type = "tablet";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <25>;
+
+ button-vol-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <297500>;
+ };
+
+ button-vol-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <1750>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm4 0 25000 0>;
+ brightness-levels = <20 220>;
+ num-interpolated-steps = <200>;
+ default-brightness-level = <100>;
+ power-supply = <&vcc_sys>;
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <6000000>;
+ charge-term-current-microamp = <300000>;
+ constant-charge-current-max-microamp = <2000000>;
+ constant-charge-voltage-max-microvolt = <4300000>;
+ voltage-max-design-microvolt = <4350000>;
+ voltage-min-design-microvolt = <3400000>;
+
+ ocv-capacity-celsius = <20>;
+ ocv-capacity-table-0 = <4322000 100>, <4250000 95>, <4192000 90>, <4136000 85>,
+ <4080000 80>, <4022000 75>, <3972000 70>, <3928000 65>,
+ <3885000 60>, <3833000 55>, <3798000 50>, <3780000 45>,
+ <3776000 40>, <3773000 35>, <3755000 30>, <3706000 25>,
+ <3640000 20>, <3589000 15>, <3535000 10>, <3492000 5>,
+ <3400000 0>;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&kb_id_det>;
+
+ tablet-mode-switch {
+ debounce-interval = <20>;
+ gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
+ label = "Tablet Mode";
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_TABLET_MODE>;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "d";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ led-0 {
+ compatible = "regulator-led";
+ vled-supply = <&vcc5v0_flashled>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_FLASH;
+ };
+
+ rk817-sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det_l>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "rk817_ext";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Internal Speakers";
+
+ simple-audio-card,routing =
+ "MICR", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Internal Speakers", "Speaker Amplifier OUTL",
+ "Internal Speakers", "Speaker Amplifier OUTR",
+ "Speaker Amplifier INL", "HPOL",
+ "Speaker Amplifier INR", "HPOR";
+ simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
+ simple-audio-card,aux-devs = <&speaker_amp>;
+ simple-audio-card,pin-switches = "Internal Speakers";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+ };
+
+ speaker_amp: speaker-amplifier {
+ compatible = "simple-audio-amplifier";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spk_ctl>;
+ enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+ sound-name-prefix = "Speaker Amplifier";
+ VCC-supply = <&vcc_bat>;
+ };
+
+ vcc_3v3: vcc-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_minipcie: vcc3v3-minipcie-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwren_h>;
+ regulator-name = "vcc3v3_minipcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc3v3_sd: vcc3v3-sd-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwren_l>;
+ regulator-name = "vcc3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc5v0_flashled: vcc5v0-flashled-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_led_en_h>;
+ regulator-name = "vcc5v0_flashled";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v_midu>;
+ };
+
+ vcc5v0_usb_host0: vcc5v0-usb-host0-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_pwren1_h>;
+ regulator-name = "vcc5v0_usb_host0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v_midu>;
+ };
+
+ vcc5v0_usb_host2: vcc5v0-usb-host2-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_pwren2_h>;
+ regulator-name = "vcc5v0_usb_host2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v_midu>;
+ };
+
+ vcc_bat: vcc-bat-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_bat";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_bat>;
+ };
+
+ vdd1v2_dvp: vdd1v2-dvp-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd1v2_dvp";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&vcc_3v3>;
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cru {
+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+ <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+ assigned-clock-rates = <32768>, <1200000000>, <200000000>, <500000000>;
+ assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
+};
+
+&csi_dphy {
+ status = "okay";
+};
+
+&dsi0 {
+ status = "okay";
+ clock-master;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lcd: panel@0 {
+ compatible = "boe,th101mb31ig002-28a";
+ reg = <0>;
+ backlight = <&backlight>;
+ enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ rotation = <90>;
+ power-supply = <&vcc_3v3>;
+
+ port@0 {
+ panel_in_dsi: endpoint@0 {
+ remote-endpoint = <&dsi0_out_con>;
+ };
+ };
+ };
+};
+
+&dsi0_in {
+ dsi0_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_dsi0>;
+ };
+};
+
+&dsi0_out {
+ dsi0_out_con: endpoint {
+ remote-endpoint = <&panel_in_dsi>;
+ };
+};
+
+&dsi_dphy0 {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_npu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda_0v9_p>;
+ avdd-1v8-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk817: pmic@20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+ rockchip,system-power-controller;
+ #sound-dai-cells = <0>;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_sys>;
+ vcc9-supply = <&vcc5v_midu>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_logic";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu_npu: DCDC_REG2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_gpu_npu";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc3v3_sys";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdda_0v9_p: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda_0v9_p";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda0v9_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_acodec";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_dvp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc2v8_dvp: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc2v8_dvp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc5v_midu: BOOST {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "boost";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vbus: OTG_SWITCH {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "otg_switch";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ charger {
+ monitored-battery = <&battery>;
+ rockchip,resistor-sense-micro-ohms = <10000>;
+ rockchip,sleep-enter-current-microamp = <300000>;
+ rockchip,sleep-filter-current-microamp = <100000>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@5d {
+ compatible = "goodix,gt911";
+ reg = <0x5d>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tp_int_l_pmuio2>, <&tp_rst_l_pmuio2>;
+ AVDD28-supply = <&vcc3v3_pmu>;
+ VDDIO-supply = <&vcca1v8_pmu>;
+ irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c2m1_xfer>;
+ status = "okay";
+
+ vcm@c {
+ compatible = "dongwoon,dw9714";
+ reg = <0x0c>;
+ vcc-supply = <&vcc1v8_dvp>;
+ };
+
+ camera@36 {
+ compatible = "ovti,ov5648";
+ reg = <0x36>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camerab_pdn_l &camerab_rst_l>;
+
+ clocks = <&cru CLK_CIF_OUT>;
+ assigned-clocks = <&cru CLK_CIF_OUT>;
+ assigned-clock-rates = <24000000>;
+
+ avdd-supply = <&vcc2v8_dvp>;
+ dvdd-supply = <&vdd1v2_dvp>;
+ dovdd-supply = <&vcc1v8_dvp>;
+ powerdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
+
+ port {
+ endpoint {
+ data-lanes = <1 2>;
+ remote-endpoint = <0>;
+ link-frequencies = /bits/ 64 <210000000 168000000>;
+ };
+ };
+ };
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ accelerometer@18 {
+ compatible = "silan,sc7a20";
+ reg = <0x18>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsensor_int_l>;
+ st,drdy-int-pin = <1>;
+ vdd-supply = <&vcc_1v8>;
+ vddio-supply = <&vcc_1v8>;
+ mount-matrix = "1", "0", "0",
+ "0", "0", "1",
+ "0", "1", "0";
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclktx
+ &i2s1m0_lrcktx
+ &i2s1m0_sdi0
+ &i2s1m0_sdo0>;
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_h>;
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_minipcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ camerab {
+ camerab_pdn_l: camerab-pdn-l {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ camerab_rst_l: camerab-rst-l {
+ rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ cameraf {
+ cameraf_pdn_l: cameraf-pdn-l {
+ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ cameraf_rst_l: cameraf-rst-l {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ flash {
+ flash_led_en_h: flash-led-en-h {
+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ fspi {
+ fspi_dual_io_pins: fspi-dual-io-pins {
+ rockchip,pins =
+ /* fspi_clk */
+ <1 RK_PD0 1 &pcfg_pull_none>,
+ /* fspi_cs0n */
+ <1 RK_PD3 1 &pcfg_pull_none>,
+ /* fspi_d0 */
+ <1 RK_PD1 1 &pcfg_pull_none>,
+ /* fspi_d1 */
+ <1 RK_PD2 1 &pcfg_pull_none>;
+ };
+ };
+
+ gsensor {
+ gsensor_int_l: gsensor-int-l {
+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ kb {
+ kb_id_det: kb-id-det {
+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ lcd {
+ lcd_pwren_h: lcd-pwren-h {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie_pwren_h: pcie-pwren-h {
+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_reset_h: pcie-reset-h {
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_pwren_l: sdmmc-pwren-l {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sound {
+ hp_det_l: hp-det-l {
+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ spk_ctl: spk-ctl {
+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ tp {
+ tp_int_l_pmuio2: tp-int-l-pmuio2 {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ tp_rst_l_pmuio2: tp-rst-l-pmuio2 {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usbcc_int_l: usbcc-int-l {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb_host_pwren1_h: usb-host-pwren1-h {
+ rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb_host_pwren2_h: usb-host-pwren2-h {
+ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ host_wake_wl: host-wake-wl {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_wake_host_h: wifi-wake-host-h {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcca1v8_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_1v8>;
+ vccio6-supply = <&vcc1v8_dvp>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8
+ &emmc_clk
+ &emmc_cmd
+ &emmc_datastrobe
+ &emmc_rstnout>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4
+ &sdmmc0_clk
+ &sdmmc0_cmd
+ &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4
+ &sdmmc1_cmd
+ &sdmmc1_clk>;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vcca1v8_pmu>;
+ status = "okay";
+};
+
+&sfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspi_dual_io_pins>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb_host0>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb_host2>;
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
+
+&vp1 {
+ vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
+ reg = <ROCKCHIP_VOP2_EP_MIPI0>;
+ remote-endpoint = <&dsi0_in_vp1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566-powkiddy-rk2023.dtsi"
+
+/ {
+ model = "Powkiddy RGB10MAX3";
+ compatible = "powkiddy,rgb10max3", "rockchip,rk3566";
+};
+
+&bluetooth {
+ compatible = "realtek,rtl8723ds-bt";
+};
+
+&cru {
+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+ <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+ assigned-clock-rates = <32768>, <1200000000>,
+ <200000000>, <126400000>;
+};
+
+&dsi0 {
+ panel: panel@0 {
+ compatible = "powkiddy,rgb10max3-panel";
+ reg = <0>;
+ backlight = <&backlight>;
+ iovcc-supply = <&vcc3v3_lcd0_n>;
+ pinctrl-0 = <&lcd_rst>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
+ rotation = <270>;
+ vcc-supply = <&vcc3v3_lcd0_n>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+};
+
+&green_led {
+ default-state = "on";
+ function = LED_FUNCTION_POWER;
+};
+
+&i2c0 {
+ vdd_cpu: regulator@40 {
+ compatible = "fcs,fan53555";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-name = "vdd_cpu";
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sys>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&leds {
+ amber_led: led-2 {
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_CHARGING;
+ max-brightness = <255>;
+ pwms = <&pwm0 0 25000 0>;
+ };
+};
+
+&pwm0 {
+ pinctrl-0 = <&pwm0m1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&red_led {
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+};
};
};
};
+
+&i2c0 {
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-name = "vdd_cpu";
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sys>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
};
};
};
+
+&i2c0 {
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-name = "vdd_cpu";
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sys>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
rockchip,sleep-filter-current-microamp = <100000>;
};
};
-
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1390000>;
- regulator-name = "vdd_cpu";
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc_sys>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
};
&i2c5 {
uart-has-rtscts;
status = "okay";
- bluetooth {
+ bluetooth: bluetooth {
compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt";
device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
/ {
model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
+ compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568";
aliases {
ethernet0 = &gmac0;
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ switch@1f {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <0x1f>;
ports {
#address-cells = <1>;
&pcie2x1 {
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
- disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_mini_pcie>;
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2024 Uwe Kleine-König
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Qnap TS-433-4G NAS System 4-Bay";
+ compatible = "qnap,ts433", "rockchip,rk3568";
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ rx_delay = <0x2f>;
+ tx_delay = <0x3c>;
+ status = "okay";
+};
+
+&i2c0 {
+ pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ rtc@51 {
+ compatible = "microcrystal,rv8263";
+ reg = <0x51>;
+ wakeup-source;
+ };
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ };
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x1 {
+ /* The downstream dts has: rockchip,bifurcation, XXX: find out what this is about */
+ reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ status = "okay";
+};
+
+/*
+ * Pins available on CN3 connector at TTL voltage level (3V3).
+ * ,_ _.
+ * |1234| 1=TX 2=VCC
+ * `----' 3=RX 4=GND
+ */
+&uart2 {
+ status = "okay";
+};
compatible = "rockchip,rk3568-vpu";
reg = <0x0 0xfdea0000 0x0 0x800>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vdpu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "hclk";
iommus = <&vdpu_mmu>;
dmas = <&dmac1 4>, <&dmac1 5>;
dma-names = "tx", "rx";
resets = <&cru SRST_M_I2S2_2CH>;
- reset-names = "m";
+ reset-names = "tx-m";
rockchip,grf = <&grf>;
pinctrl-names = "default";
pinctrl-0 = <&i2s2m0_sclktx
pinctrl-0 = <&i2c7m0_xfer>;
status = "okay";
- es8316: audio-codec@11 {
+ es8316: audio-codec@10 {
compatible = "everest,es8316";
- reg = <0x11>;
+ reg = <0x10>;
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
assigned-clock-rates = <12288000>;
clocks = <&cru I2S0_8CH_MCLKOUT>;
* Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
*/
-/ {
- compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588";
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+/ {
aliases {
mmc0 = &sdhci;
};
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led_user: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_user_en>;
+ };
+ };
+
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
};
};
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
cpu-supply = <&vdd_cpu_lit_s0>;
};
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&pinctrl {
+ leds {
+ led_user_en: led_user_en {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
&sdhci {
bus-width = <8>;
no-sdio;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
- regulator-init-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-state-mem {
/dts-v1/;
#include "rk3588.dtsi"
#include "rk3588-edgeble-neu6a.dtsi"
+#include "rk3588-edgeble-neu6a-io.dtsi"
/ {
model = "Edgeble Neu6A IO Board";
compatible = "edgeble,neural-compute-module-6a-io",
"edgeble,neural-compute-module-6a", "rockchip,rk3588";
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc3v3_pcie3x2: vcc3v3-pcie3x2-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3x2_vcc3v3_en>;
+ regulator-name = "vcc3v3_pcie3x2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_pcie3x4: vcc3v3-pcie3x4-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3x4_vcc3v3_en>;
+ regulator-name = "vcc3v3_pcie3x4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+/* ETH */
+&pcie2x1l0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_0_rst>;
+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; /* PCIE20_1_PERST_L */
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+/* B-Key and E-Key */
+&pcie3x2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3x2_rst>;
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */
+ vpcie3v3-supply = <&vcc3v3_pcie3x2>;
+ status = "okay";
+};
+
+/* M-Key */
+&pcie3x4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3x4_rst>;
+ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */
+ vpcie3v3-supply = <&vcc3v3_pcie3x4>;
+ status = "okay";
+};
+
+&pinctrl {
+ pcie2 {
+ pcie2_0_rst: pcie2-0-rst {
+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie3 {
+ pcie3x2_rst: pcie3x2-rst {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie3x2_vcc3v3_en: pcie3x2-vcc3v3-en {
+ rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie3x4_rst: pcie3x4-rst {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie3x4_vcc3v3_en: pcie3x4-vcc3v3-en {
+ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+/* FAN */
+&pwm2 {
+ pinctrl-0 = <&pwm2m1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+/* RS232 */
+&uart6 {
+ pinctrl-0 = <&uart6m0_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* RS485 */
+&uart7 {
+ pinctrl-0 = <&uart7m2_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ /* connected to USB hub, which is powered by vcc5v0_sys */
+ phy-supply = <&vcc5v0_sys>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ *
+ * DT-overlay for Edgeble On-SoM WiFi6/BT M.2 1216 modules,
+ * - AW-XM548NF
+ * - Intel 8260D2W
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+&{/} {
+ vcc3v3_pcie2x1l1: vcc3v3-pcie2x1l1-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; /* WIFI_3V3_EN */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_1_vcc3v3_en>;
+ regulator-name = "vcc3v3_pcie2x1l1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+/* WiFi6 */
+&pcie2x1l1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_1_rst>;
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; /* PCIE20_2_WIFI_PERSTn */
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l1>;
+ status = "okay";
+};
+
+&pinctrl {
+ pcie2 {
+ pcie2_1_rst: pcie2-1-rst {
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie2_1_vcc3v3_en: pcie2-1-vcc-en {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
+#include "rk3588-edgeble-neu6a-common.dtsi"
+
/ {
compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588";
-
- aliases {
- mmc0 = &sdhci;
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
};
/dts-v1/;
#include "rk3588j.dtsi"
#include "rk3588-edgeble-neu6b.dtsi"
+#include "rk3588-edgeble-neu6a-io.dtsi"
/ {
model = "Edgeble Neu6B IO Board";
compatible = "edgeble,neural-compute-module-6a-io",
"edgeble,neural-compute-module-6b", "rockchip,rk3588";
-
- chosen {
- stdout-path = "serial2:1500000n8";
- };
-};
-
-&combphy0_ps {
- status = "okay";
-};
-
-&i2c6 {
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <0>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- wakeup-source;
- };
-};
-
-&pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-/* FAN */
-&pwm2 {
- pinctrl-0 = <&pwm2m1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&sata0 {
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- no-sdio;
- no-mmc;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
-/* RS232 */
-&uart6 {
- pinctrl-0 = <&uart6m0_xfer>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-/* RS485 */
-&uart7 {
- pinctrl-0 = <&uart7m2_xfer>;
- pinctrl-names = "default";
- status = "okay";
};
* Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
*/
+#include "rk3588-edgeble-neu6a-common.dtsi"
+
/ {
compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588";
-
- aliases {
- mmc0 = &sdhci;
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&sdhci {
- bus-width = <8>;
- no-sdio;
- no-sd;
- non-removable;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- status = "okay";
-};
-
-&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
-
- pmic@0 {
- compatible = "rockchip,rk806";
- spi-max-frequency = <1000000>;
- reg = <0x0>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc5v0_sys>;
- vcc6-supply = <&vcc5v0_sys>;
- vcc7-supply = <&vcc5v0_sys>;
- vcc8-supply = <&vcc5v0_sys>;
- vcc9-supply = <&vcc5v0_sys>;
- vcc10-supply = <&vcc5v0_sys>;
- vcc11-supply = <&vcc_2v0_pldo_s3>;
- vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc_1v1_nldo_s3>;
- vcc14-supply = <&vcc_1v1_nldo_s3>;
- vcca-supply = <&vcc5v0_sys>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs2_null: dvs2-null-pins {
- pins = "gpio_pwrctrl2";
- function = "pin_fun0";
- };
-
- rk806_dvs3_null: dvs3-null-pins {
- pins = "gpio_pwrctrl3";
- function = "pin_fun0";
- };
-
- regulators {
- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
- regulator-name = "vdd_gpu_s0";
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
- regulator-enable-ramp-delay = <400>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
- regulator-name = "vdd_cpu_lit_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_log_s0: dcdc-reg3 {
- regulator-name = "vdd_log_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
- regulator-name = "vdd_vdenc_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-init-microvolt = <750000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_ddr_s0: dcdc-reg5 {
- regulator-name = "vdd_ddr_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <900000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- vdd2_ddr_s3: dcdc-reg6 {
- regulator-name = "vdd2_ddr_s3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-name = "vdd_2v0_pldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <2000000>;
- };
- };
-
- vcc_3v3_s3: dcdc-reg8 {
- regulator-name = "vcc_3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vddq_ddr_s0: dcdc-reg9 {
- regulator-name = "vddq_ddr_s0";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s3: dcdc-reg10 {
- regulator-name = "vcc_1v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avcc_1v8_s0: pldo-reg1 {
- regulator-name = "avcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8_s0: pldo-reg2 {
- regulator-name = "vcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- avdd_1v2_s0: pldo-reg3 {
- regulator-name = "avdd_1v2_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3_s0: pldo-reg4 {
- regulator-name = "vcc_3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd_s0: pldo-reg5 {
- regulator-name = "vccio_sd_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- pldo6_s3: pldo-reg6 {
- regulator-name = "pldo6_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_0v75_s3: nldo-reg1 {
- regulator-name = "vdd_0v75_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <750000>;
- };
- };
-
- vdd_ddr_pll_s0: nldo-reg2 {
- regulator-name = "vdd_ddr_pll_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <850000>;
- };
- };
-
- avdd_0v75_s0: nldo-reg3 {
- regulator-name = "avdd_0v75_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v85_s0: nldo-reg4 {
- regulator-name = "vdd_0v85_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_0v75_s0: nldo-reg5 {
- regulator-name = "vdd_0v75_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
};
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
+
+ vcc3v3_sd_s0: vcc3v3-sd-s0-regulator {
+ compatible = "regulator-fixed";
+ enable-active-low;
+ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc3v3_sd_s0";
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vdd_4g_3v3: vdd-4g-3v3-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pin_4g_lte_pwren>;
+ regulator-name = "vdd_4g_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
};
&combphy0_ps {
};
usb {
+ pin_4g_lte_pwren: 4g-lte-pwren {
+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
typec5v_pwren: typec5v-pwren {
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
no-mmc;
no-sdio;
sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
+ vmmc-supply = <&vcc3v3_sd_s0>;
vqmmc-supply = <&vccio_sd_s0>;
status = "okay";
};
};
&u2phy2_host {
+ phy-supply = <&vdd_4g_3v3>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
no-sdio;
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
spi-max-frequency = <1000000>;
+ system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
no-sdio;
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
pinctrl-names = "default";
spi-max-frequency = <1000000>;
+ system-power-controller;
vcc1-supply = <&vcc4v0_sys>;
vcc2-supply = <&vcc4v0_sys>;
#cooling-cells = <2>;
};
+ rfkill {
+ compatible = "rfkill-gpio";
+ label = "rfkill-pcie-wlan";
+ radio-type = "wlan";
+ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
+
vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
compatible = "regulator-fixed";
enable-active-high;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3_s3>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "rk3588-tiger.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3588-Q7 SoM on Haikou devkit";
+ compatible = "tsd,rk3588-tiger-haikou", "tsd,rk3588-tiger", "rockchip,rk3588";
+
+ aliases {
+ ethernet0 = &gmac0;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&haikou_keys_pin>;
+
+ button-batlow-n {
+ label = "BATLOW#";
+ linux,code = <KEY_BATTERY>;
+ gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;
+ };
+
+ button-slp-btn-n {
+ label = "SLP_BTN#";
+ linux,code = <KEY_SLEEP>;
+ gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+ };
+
+ button-wake-n {
+ label = "WAKE#";
+ linux,code = <KEY_WAKEUP>;
+ gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ switch-lid-btn-n {
+ label = "LID_BTN#";
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ i2s3-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Haikou,I2S-codec";
+ simple-audio-card,mclk-fs = <512>;
+ simple-audio-card,frame-master = <&sgtl5000_codec>;
+ simple-audio-card,bitclock-master = <&sgtl5000_codec>;
+
+ sgtl5000_codec: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s3_2ch>;
+ };
+ };
+
+ sgtl5000_clk: sgtl5000-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ vcc3v3_baseboard: vcc3v3-baseboard-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_baseboard";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc3v3_low_noise: vcc3v3-low-noise-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_low_noise";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_baseboard: vcc5v0-baseboard-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_baseboard";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vddd_audio_1v6: vddd-audio-1v6-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vddd_audio_1v6";
+ regulator-boot-on;
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1600000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ eeprom@50 {
+ reg = <0x50>;
+ compatible = "atmel,24c01";
+ pagesize = <8>;
+ size = <128>;
+ vcc-supply = <&vcc3v3_baseboard>;
+ };
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&sgtl5000_clk>;
+ #sound-dai-cells = <0>;
+ VDDA-supply = <&vcc3v3_low_noise>;
+ VDDIO-supply = <&vcc3v3_baseboard>;
+ VDDD-supply = <&vddd_audio_1v6>;
+ };
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2s3_2ch {
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ vpcie3v3-supply = <&vcc3v3_baseboard>;
+ status = "okay";
+};
+
+&pinctrl {
+ haikou {
+ haikou_keys_pin: haikou-keys-pin {
+ rockchip,pins =
+ /* BATLOW# */
+ <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* SLP_BTN# */
+ <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* WAKE# */
+ <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* LID_BTN */
+ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&sdmmc {
+ /* while the same pin, sdmmc_det does not detect card changes */
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_baseboard>;
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m2_xfer>;
+ status = "okay";
+};
+
+&uart5 {
+ rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+/* host0 on Q7_USB_P2, lower usb3 port */
+&usb_host0_ehci {
+ status = "okay";
+};
+
+/* host0 on Q7_USB_P2, lower usb3 port */
+&usb_host0_ohci {
+ status = "okay";
+};
+
+/* host1 on Q7_USB_P3, usb2 port */
+&usb_host1_ehci {
+ status = "okay";
+};
+
+/* host1 on Q7_USB_P3, usb2 port */
+&usb_host1_ohci {
+ status = "okay";
+};
+
+/* host2 on Q7_USB_P2, lower usb3 port */
+&usb_host2_xhci {
+ status = "okay";
+};
* Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
*/
-/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/usb/pd.h>
#include "rk3588.dtsi"
/ {
- model = "Theobroma Systems RK3588-SBC Jaguar";
- compatible = "tsd,rk3588-jaguar", "rockchip,rk3588";
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- /* Can be controlled through SW2 but also GPIO1 on CP2102 on P20 */
- button-bios-disable {
- label = "BIOS_DISABLE";
- linux,code = <KEY_VENDOR>;
- press-threshold-microvolt = <0>;
- };
- };
+ compatible = "tsd,rk3588-tiger", "rockchip,rk3588";
aliases {
- ethernet0 = &gmac0;
mmc0 = &sdhci;
- mmc1 = &sdmmc;
rtc0 = &rtc_twi;
};
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- /* DCIN is 12-24V but standard is 12V */
- dc_12v: dc-12v-regulator {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&led1_pin>;
- status = "okay";
+ pinctrl-0 = <&module_led_pin>;
- /* LED1 on PCB */
+ /* Named LED1 on the board */
led-1 {
- gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_HEARTBEAT;
linux,default-trigger = "heartbeat";
color = <LED_COLOR_ID_AMBER>;
};
};
- pps {
- compatible = "pps-gpio";
- gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ /*
+ * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
+ * clock generator.
+ * The clock output is gated via the OE pin on the clock generator.
+ * This is modeled as a fixed-clock plus a gpio-gate-clock.
+ */
+ pcie_refclk_gen: pcie-refclk-gen-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ };
+
+ pcie_refclk: pcie-refclk-clock {
+ compatible = "gpio-gate-clock";
+ clocks = <&pcie_refclk_gen>;
+ #clock-cells = <0>;
+ enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */
};
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
vin-supply = <&vcc5v0_sys>;
};
- /* Exposed on P14 and P15 */
- vcc_2v8_s3: vcc-2v8-s3-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_2v8_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- vin-supply = <&vcc_3v3_s3>;
- };
-
- vcc_5v0_usb_a: vcc-5v0-usb-a-regulator {
- compatible = "regulator-fixed";
- regulator-name = "usb_a_vcc";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
- gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vcc_5v0_usb_c1: vcc-5v0-usb-c1-regulator {
- compatible = "regulator-fixed";
- regulator-name = "5v_usbc1";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vcc_5v0_usb_c2: vcc-5v0-usb-c2-regulator {
- compatible = "regulator-fixed";
- regulator-name = "5v_usbc2";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vcc3v3_mdot2: vcc3v3-mdot2-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_mdot2";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_12v>;
- };
-
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_usb: vcc5v0-usb-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
+ vin-supply = <&vcc5v0_baseboard>;
};
};
-&combphy1_ps {
- status = "okay";
-};
-
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 100000>;
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1m0_xfer>;
+};
+&i2c1m0_xfer {
+ rockchip,pins =
+ /* i2c1_scl_m0 */
+ <0 RK_PB5 9 &pcfg_pull_none_drv_level_0>,
+ /* i2c1_sda_m0 */
+ <0 RK_PB6 9 &pcfg_pull_none_drv_level_0>;
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2m3_xfer>;
status = "okay";
};
-&gpio1 {
- mdot2e-w-disable1-n-hog {
- gpios = <RK_PB1 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "m.2 E-key W_DISABLE1#";
- gpio-hog;
- };
+&i2c2m3_xfer {
+ rockchip,pins =
+ /* i2c2_scl_m3 */
+ <1 RK_PC5 9 &pcfg_pull_none_drv_level_0>,
+ /* i2c2_sda_m3 */
+ <1 RK_PC4 9 &pcfg_pull_none_drv_level_0>;
};
-&gpio4 {
- mdot2e-w-disable2-n-hog {
- gpios = <RK_PC1 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "m.2 E-key W_DISABLE2#";
- gpio-hog;
- };
+&i2c3 {
+ pinctrl-0 = <&i2c3m0_xfer>;
};
-&i2c0 {
- pinctrl-0 = <&i2c0m2_xfer>;
+&i2c4 {
+ pinctrl-0 = <&i2c4m4_xfer>;
status = "okay";
- fan@18 {
- compatible = "ti,amc6821";
- reg = <0x18>;
- };
-
vdd_npu_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
regulator-off-in-suspend;
};
};
+};
- vdd_cpu_big1_s0: regulator@43 {
- compatible = "rockchip,rk8603", "rockchip,rk8602";
- reg = <0x43>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu_big1_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <1050000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
+&i2c5 {
+ pinctrl-0 = <&i2c5m1_xfer>;
+};
- regulator-state-mem {
- regulator-off-in-suspend;
- };
+&i2c5m1_xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <4 RK_PB6 9 &pcfg_pull_none_drv_level_0>,
+ /* i2c5_sda_m1 */
+ <4 RK_PB7 9 &pcfg_pull_none_drv_level_0>;
+};
+
+&i2c6 {
+ /*
+ * Mule-ATtiny can handle up to Fast mode Plus (1MHz) on I2C bus,
+ * but SOC can handle only up to (400kHz).
+ */
+ clock-frequency = <400000>;
+ status = "okay";
+
+ fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
};
rtc_twi: rtc@6f {
};
};
-&i2c1 {
- pinctrl-0 = <&i2c1m4_xfer>;
-};
-
-&i2c6 {
- pinctrl-0 = <&i2c6m4_xfer>;
+&i2c6m0_xfer {
+ rockchip,pins =
+ /* i2c6_scl_m0 */
+ <0 RK_PD0 9 &pcfg_pull_none_drv_level_0>,
+ /* i2c6_sda_m0 */
+ <0 RK_PC7 9 &pcfg_pull_none_drv_level_0>;
};
&i2c7 {
status = "okay";
- /* SE050 Secure Element at 0x48; GPIO1_A4 for enable pin */
-
- /* Also on 0x55 */
- eeprom@54 {
- compatible = "st,24c04", "atmel,24c04";
- reg = <0x54>;
- pagesize = <16>;
- vcc-supply = <&vcc_3v3_s3>;
- };
-};
-
-&i2c8 {
- pinctrl-0 = <&i2c8m2_xfer>;
- status = "okay";
-
vdd_cpu_big0_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
regulator-off-in-suspend;
};
};
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c7m0_xfer {
+ rockchip,pins =
+ /* i2c7_scl_m0 */
+ <1 RK_PD0 9 &pcfg_pull_none_drv_level_0>,
+ /* i2c7_sda_m0 */
+ <1 RK_PD1 9 &pcfg_pull_none_drv_level_0>;
+};
+
+&i2c8 {
+ pinctrl-0 = <&i2c8m2_xfer>;
};
&mdio0 {
};
};
-&pcie2x1l0 {
- reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; /* WIFI_PERST0# */
- vpcie3v3-supply = <&vcc3v3_mdot2>;
- status = "okay";
+&pcie3x4 {
+ /*
+ * The board has a gpio-controlled "pcie_refclk" generator,
+ * so add it to the list of clocks.
+ */
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
+ <&pcie_refclk>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe",
+ "ref";
+ reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>;
};
&pinctrl {
};
leds {
- led1_pin: led1-pin {
- rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ module_led_pin: module-led-pin {
+ rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
};
&sdmmc {
- broken-cd;
bus-width = <4>;
cap-sd-highspeed;
- disable-wp;
max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-ddr50;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
+};
+
+&spi0 {
+ pinctrl-0 = <&spi0m1_cs0 &spi0m1_cs1 &spi0m3_pins>;
};
&spi2 {
};
vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-name = "vdd_2v0_pldo_s3";
+ regulator-name = "vcc_2v0_pldo_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2000000>;
status = "okay";
};
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy2_host {
- phy-supply = <&vcc_5v0_usb_a>;
- status = "okay";
-};
-
-&u2phy3 {
- status = "okay";
-};
-
-&u2phy3_host {
- status = "okay";
-};
-
-/* Mule-ATtiny debug UART; typically baudrate 9600 */
-&uart0 {
- pinctrl-0 = <&uart0m0_xfer>;
- status = "okay";
-};
-
-/* Main debug interface on P20 micro-USB B port and P21 header */
-&uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
-};
-
-/* RS485 on P19 */
-&uart3 {
- pinctrl-0 = <&uart3m2_xfer &uart3_rtsn>;
- linux,rs485-enabled-at-boot-time;
- status = "okay";
-};
-
-/* Mule-ATtiny UPDI flashing UART */
-&uart7 {
- pinctrl-0 = <&uart7m0_xfer>;
- status = "okay";
-};
-
-/* host0 on P10 USB-A */
-&usb_host0_ehci {
- status = "okay";
-};
-
-/* host0 on P10 USB-A */
-&usb_host0_ohci {
- status = "okay";
-};
-
-/* host1 on M.2 E-key */
-&usb_host1_ehci {
- status = "okay";
-};
-
-/* host1 on M.2 E-key */
-&usb_host1_ohci {
+/* Mule-ATtiny UPDI */
+&uart4 {
+ pinctrl-0 = <&uart4m2_xfer>;
status = "okay";
};
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3588.dtsi"
/ {
- compatible = "coolpi,pi-cm5", "rockchip,rk3588";
+ model = "Rockchip Toybrick TB-RK3588X Board";
+ compatible = "rockchip,rk3588-toybrick-x0", "rockchip,rk3588";
aliases {
mmc0 = &sdhci;
- mmc1 = &sdmmc;
- mmc2 = &sdio;
- };
-
- analog-sound {
- compatible = "audio-graph-card";
- dais = <&i2s0_8ch_p0>;
- label = "rk3588-es8316";
- routing = "MIC2", "Mic Jack",
- "Headphones", "HPOL",
- "Headphones", "HPOR";
- widgets = "Microphone", "Mic Jack",
- "Headphone", "Headphones";
};
chosen {
stdout-path = "serial2:1500000n8";
};
- avdd0v85_pcie20: avdd0v85-pcie20-regulator {
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-vol-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <17000>;
+ };
+
+ button-vol-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <417000>;
+ };
+
+ button-menu {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <890000>;
+ };
+
+ button-escape {
+ label = "Escape";
+ linux,code = <KEY_ESC>;
+ press-threshold-microvolt = <1235000>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&vcc12v_dcin>;
+ pwms = <&pwm2 0 25000 0>;
+ };
+
+ pcie20_avdd0v85: pcie20-avdd0v85-regulator {
compatible = "regulator-fixed";
- regulator-name = "avdd0v85_pcie20";
- regulator-boot-on;
+ regulator-name = "pcie20_avdd0v85";
regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
vin-supply = <&vdd_0v85_s0>;
};
- avdd1v8_pcie20: avdd1v8-pcie20-regulator {
+ pcie20_avdd1v8: pcie20-avdd1v8-regulator {
compatible = "regulator-fixed";
- regulator-name = "avdd1v8_pcie20";
- regulator-boot-on;
+ regulator-name = "pcie20_avdd1v8";
regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&avcc_1v8_s0>;
};
- avdd0v75_pcie30: avdd0v75-pcie30-regulator {
+ pcie30_avdd0v75: pcie30-avdd0v75-regulator {
compatible = "regulator-fixed";
- regulator-name = "avdd0v75_pcie30";
- regulator-boot-on;
+ regulator-name = "pcie30_avdd0v75";
regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
vin-supply = <&avdd_0v75_s0>;
};
- pcie30_avdd1v8: avdd1v8-pcie30-regulator {
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd1v8";
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&avcc_1v8_s0>;
};
-};
-&combphy0_ps {
- status = "okay";
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usbdcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usbdcin>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
};
-&combphy1_ps {
+&combphy0_ps {
status = "okay";
};
};
&i2c0 {
+ pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
status = "okay";
&i2c2 {
status = "okay";
- vdd_npu_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_npu_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <550000>;
- regulator-max-microvolt = <950000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-};
-
-&i2c6 {
- status = "okay";
-
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <0>;
clock-output-names = "hym8563";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
wakeup-source;
};
};
-&i2c7 {
- pinctrl-0 = <&i2c7m0_xfer>;
- status = "okay";
-
- es8316: audio-codec@11 {
- compatible = "everest,es8316";
- reg = <0x11>;
- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
- clocks = <&cru I2S0_8CH_MCLKOUT>;
- clock-names = "mclk";
- #sound-dai-cells = <0>;
-
- port {
- es8316_p0_0: endpoint {
- remote-endpoint = <&i2s0_8ch_p0_0>;
- };
- };
- };
-};
-
-&i2s0_8ch {
- pinctrl-0 = <&i2s0_lrck
- &i2s0_mclk
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdo0>;
- status = "okay";
-
- i2s0_8ch_p0: port {
- i2s0_8ch_p0_0: endpoint {
- dai-format = "i2s";
- mclk-fs = <256>;
- remote-endpoint = <&es8316_p0_0>;
- };
- };
-};
-
&mdio0 {
rgmii_phy: ethernet-phy@1 {
- /* YT8531C/H */
- compatible = "ethernet-phy-ieee802.3-c22";
+ /* RTL8211F */
+ compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
pinctrl-names = "default";
- pinctrl-0 = <&yt8531_rst>;
+ pinctrl-0 = <&rtl8211f_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
};
};
-/* ethernet */
-&pcie2x1l2 {
- reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_sys>;
- pinctrl-names = "default";
- pinctrl-0 = <&yt6801_isolate>;
- status = "okay";
-};
-
&pinctrl {
+ rtl8211f {
+ rtl8211f_rst: rtl8211f-rst {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ };
+
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
- yt6801 {
- yt6801_isolate: yt6801-isolate {
- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+};
- yt8531 {
- yt8531_rst: yt8531-rst {
- rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
+&pwm2 {
+ status = "okay";
};
&saradc {
&sdhci {
bus-width = <8>;
- max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
no-sdio;
status = "okay";
};
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- max-frequency = <150000000>;
- no-sdio;
- no-mmc;
- sd-uhs-sdr104;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
-};
-
&spi2 {
assigned-clocks = <&cru CLK_SPI2>;
assigned-clock-rates = <200000000>;
pmic@0 {
compatible = "rockchip,rk806";
reg = <0x0>;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
spi-max-frequency = <1000000>;
+ system-power-controller;
+
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc_2v0_pldo_s3>;
vcc12-supply = <&vcc5v0_sys>;
- vcc13-supply = <&vcc_2v0_pldo_s3>;
- vcc14-supply = <&vcc_2v0_pldo_s3>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
regulator-boot-on;
+ regulator-enable-ramp-delay = <400>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
- regulator-name = "vdd_gpu_s0";
- regulator-enable-ramp-delay = <400>;
regulator-state-mem {
regulator-off-in-suspend;
};
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
- regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
- regulator-name = "vdd_log_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
+ regulator-init-microvolt = <750000>;
regulator-ramp-delay = <12500>;
- regulator-name = "vdd_vdenc_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <900000>;
regulator-ramp-delay = <12500>;
- regulator-name = "vdd_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
regulator-always-on;
regulator-boot-on;
- regulator-name = "vdd2_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vdd_2v0_pldo_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_3v3_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
regulator-always-on;
regulator-boot-on;
- regulator-name = "vddq_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
avcc_1v8_s0: pldo-reg1 {
+ regulator-name = "avcc_1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "avcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
avdd_1v2_s0: pldo-reg3 {
+ regulator-name = "avdd_1v2_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
- regulator-name = "avdd_1v2_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vcc_3v3_s0: pldo-reg4 {
+ regulator-name = "vcc_3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vcc_3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
- regulator-ramp-delay = <12500>;
- regulator-name = "vccio_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "pldo6_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdd_ddr_pll_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
- regulator-name = "vdd_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
avdd_0v75_s0: nldo-reg3 {
+ regulator-name = "avdd_0v75_s0";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-name = "avdd_0v75_s0";
+ regulator-min-microvolt = <837500>;
+ regulator-max-microvolt = <837500>;
regulator-state-mem {
regulator-off-in-suspend;
};
vdd_0v85_s0: nldo-reg4 {
+ regulator-name = "vdd_0v85_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
- regulator-name = "vdd_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
- regulator-name = "vdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
-&tsadc {
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_host>;
status = "okay";
};
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
status = "okay";
};
+&combphy2_psu {
+ status = "okay";
+};
+
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&usb_host1_ohci {
status = "okay";
};
+
+&usb_host2_xhci {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3588s-nanopi-r6s.dts"
+
+/ {
+ model = "FriendlyElec NanoPi R6C";
+ compatible = "friendlyarm,nanopi-r6c", "rockchip,rk3588s";
+};
+
+&lan2_led {
+ label = "user_led";
+};
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include "rk3588s.dtsi"
/ {
- model = "Radxa ROCK 5 Model A";
- compatible = "radxa,rock-5a", "rockchip,rk3588s";
+ model = "FriendlyElec NanoPi R6S";
+ compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588s";
aliases {
ethernet0 = &gmac1;
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
+ mmc0 = &sdmmc;
+ mmc1 = &sdhci;
};
- analog-sound {
- compatible = "audio-graph-card";
- label = "rk3588-es8316";
-
- widgets = "Microphone", "Mic Jack",
- "Headphone", "Headphones";
-
- routing = "MIC2", "Mic Jack",
- "Headphones", "HPOL",
- "Headphones", "HPOR";
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
- dais = <&i2s0_8ch_p0>;
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-maskrom {
+ label = "Maskrom";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <1800>;
+ };
};
- chosen {
- stdout-path = "serial2:1500000n8";
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key1_pin>;
+
+ button-user {
+ label = "User";
+ linux,code = <BTN_1>;
+ gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
+ debounce-interval = <50>;
+ };
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&io_led>;
- io-led {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+ sys_led: led-0 {
+ label = "sys_led";
+ gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sys_led_pin>;
+ };
+
+ wan_led: led-1 {
+ label = "wan_led";
+ gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wan_led_pin>;
};
- };
- fan: pwm-fan {
- compatible = "pwm-fan";
- cooling-levels = <0 95 145 195 255>;
- fan-supply = <&vcc_5v0>;
- pwms = <&pwm3 0 50000 0>;
- #cooling-cells = <2>;
+ lan1_led: led-2 {
+ label = "lan1_led";
+ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan1_led_pin>;
+ };
+
+ lan2_led: led-3 {
+ label = "lan2_led";
+ gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan2_led_pin>;
+ };
};
- vcc12v_dcin: vcc12v-dcin-regulator {
+ vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
+ regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
};
- vcc5v0_host: vcc5v0-host-regulator {
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_3v3_s0: vcc-3v3-s0-regulator {
+ compatible = "regulator-fixed";
regulator-always-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s0";
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
+ compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- vin-supply = <&vcc5v0_sys>;
+ pinctrl-0 = <&sd_s0_pwr>;
+ regulator-name = "vcc_3v3_sd_s0";
+ regulator-boot-on;
+ regulator-max-microvolt = <3000000>;
+ regulator-min-microvolt = <3000000>;
+ vin-supply = <&vcc_3v3_s3>;
};
- vcc5v0_sys: vcc5v0-sys-regulator {
+ vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
+ regulator-name = "vcc_3v3_pcie20";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
};
- vcc_5v0: vcc-5v0-regulator {
+ vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
- regulator-name = "vcc_5v0";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator {
+ compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&vcc_5v0_en>;
- vin-supply = <&vcc5v0_sys>;
+ pinctrl-0 = <&typec5v_pwren>;
+ regulator-name = "vcc5v0_usb_otg0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
};
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ vcc5v0_host_20: vcc5v0-host-20-regulator {
compatible = "regulator-fixed";
- regulator-name = "vcc_1v1_nldo_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc5v0_sys>;
+ enable-active-high;
+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host20_en>;
+ regulator-name = "vcc5v0_host_20";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
};
};
+&combphy0_ps {
+ status = "okay";
+};
+
&combphy2_psu {
status = "okay";
};
cpu-supply = <&vdd_cpu_lit_s0>;
};
+&gmac1 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-rxid";
+ pinctrl-0 = <&gmac1_miim
+ &gmac1_tx_bus2
+ &gmac1_rx_bus2
+ &gmac1_rgmii_clk
+ &gmac1_rgmii_bus>;
+ pinctrl-names = "default";
+ tx_delay = <0x42>;
+ status = "okay";
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <2300>;
+ regulator-boot-on;
+ regulator-always-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
-
- eeprom: eeprom@50 {
- compatible = "belling,bl24c16a", "atmel,24c16";
- reg = <0x50>;
- pagesize = <16>;
- };
-};
-
-&i2c3 {
- status = "okay";
-};
-
-&i2c5 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5m2_xfer>;
-};
-
-&i2c7 {
- status = "okay";
-
- es8316: audio-codec@11 {
- compatible = "everest,es8316";
- reg = <0x11>;
- clocks = <&cru I2S0_8CH_MCLKOUT>;
- clock-names = "mclk";
- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
- #sound-dai-cells = <0>;
-
- port {
- es8316_p0_0: endpoint {
- remote-endpoint = <&i2s0_8ch_p0_0>;
- };
- };
- };
};
-&i2s0_8ch {
+&i2c6 {
+ clock-frequency = <200000>;
pinctrl-names = "default";
- pinctrl-0 = <&i2s0_lrck
- &i2s0_mclk
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdo0>;
+ pinctrl-0 = <&i2c6m0_xfer>;
status = "okay";
- i2s0_8ch_p0: port {
- i2s0_8ch_p0_0: endpoint {
- dai-format = "i2s";
- mclk-fs = <256>;
- remote-endpoint = <&es8316_p0_0>;
- };
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_int>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
};
};
-&gmac1 {
- clock_in_out = "output";
- phy-handle = <&rgmii_phy1>;
- phy-mode = "rgmii";
- pinctrl-0 = <&gmac1_miim
- &gmac1_tx_bus2
- &gmac1_rx_bus2
- &gmac1_rgmii_clk
- &gmac1_rgmii_bus>;
- pinctrl-names = "default";
- tx_delay = <0x3a>;
- rx_delay = <0x3e>;
- status = "okay";
-};
-
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
- /* RTL8211F */
compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
pinctrl-names = "default";
};
};
+&pcie2x1l1 {
+ reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3_pcie20>;
+ status = "okay";
+};
+
+&pcie2x1l2 {
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3_pcie20>;
+ status = "okay";
+};
+
&pinctrl {
- leds {
- io_led: io-led {
- rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ gpio-key {
+ key1_pin: key1-pin {
+ rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
- power {
- vcc_5v0_en: vcc-5v0-en {
- rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ gpio-leds {
+ sys_led_pin: sys-led-pin {
+ rockchip,pins =
+ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
- };
- rtl8211f {
- rtl8211f_rst: rtl8211f-rst {
- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ wan_led_pin: wan-led-pin {
+ rockchip,pins =
+ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
- };
- usb {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ lan1_led_pin: lan1-led-pin {
+ rockchip,pins =
+ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
- };
- wifibt {
- wl_reset: wl-reset {
- rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ lan2_led_pin: lan2-led-pin {
+ rockchip,pins =
+ <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ };
- wl_dis: wl-dis {
- rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>;
+ hym8563 {
+ rtc_int: rtc-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
+ };
- wl_wake_host: wl-wake-host {
- rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
+ sdmmc {
+ sd_s0_pwr: sd-s0-pwr {
+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
};
+ };
- bt_dis: bt-dis {
- rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>;
+ usb {
+ typec5v_pwren: typec5v-pwren {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
- bt_wake_host: bt-wake-host {
- rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ vcc5v0_host20_en: vcc5v0-host20-en {
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
-};
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3m1_pins>;
- status = "okay";
+ rtl8211f {
+ rtl8211f_rst: rtl8211f-rst {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&saradc {
no-sdio;
no-sd;
non-removable;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
+ mmc-hs200-1_8v;
status = "okay";
};
&sdmmc {
bus-width = <4>;
- cap-mmc-highspeed;
cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
- no-sdio;
no-mmc;
+ no-sdio;
sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s0>;
+ vmmc-supply = <&vcc_3v3_sd_s0>;
vqmmc-supply = <&vccio_sd_s0>;
status = "okay";
};
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
assigned-clock-rates = <200000000>;
- num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ num-cs = <1>;
pmic@0 {
compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
reg = <0x0>;
+
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
pinctrl-names = "default";
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
- spi-max-frequency = <1000000>;
+
+ system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
- regulator-name = "vdd_gpu_s0";
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
regulator-enable-ramp-delay = <400>;
regulator-state-mem {
};
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
- regulator-name = "vdd_cpu_lit_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vdd_log_s0: dcdc-reg3 {
- regulator-name = "vdd_log_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
- regulator-name = "vdd_vdenc_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vdd_ddr_s0: dcdc-reg5 {
- regulator-name = "vdd_ddr_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <900000>;
regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vdd2_ddr_s3: dcdc-reg6 {
- regulator-name = "vdd2_ddr_s3";
regulator-always-on;
regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
vcc_2v0_pldo_s3: dcdc-reg7 {
- regulator-name = "vdd_2v0_pldo_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
vcc_3v3_s3: dcdc-reg8 {
- regulator-name = "vcc_3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
vddq_ddr_s0: dcdc-reg9 {
- regulator-name = "vddq_ddr_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vcc_1v8_s3: dcdc-reg10 {
- regulator-name = "vcc_1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
avcc_1v8_s0: pldo-reg1 {
- regulator-name = "avcc_1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+ regulator-name = "avcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
};
};
vcc_1v8_s0: pldo-reg2 {
- regulator-name = "vcc_1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
avdd_1v2_s0: pldo-reg3 {
- regulator-name = "avdd_1v2_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
+ regulator-name = "avdd_1v2_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
- vcc_3v3_s0: pldo-reg4 {
- regulator-name = "vcc_3v3_s0";
+ avcc_3v3_s0: pldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
+ regulator-name = "avcc_3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vccio_sd_s0: pldo-reg5 {
- regulator-name = "vccio_sd_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
pldo6_s3: pldo-reg6 {
- regulator-name = "pldo6_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
vdd_0v75_s3: nldo-reg1 {
- regulator-name = "vdd_0v75_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
};
- vdd_ddr_pll_s0: nldo-reg2 {
- regulator-name = "vdd_ddr_pll_s0";
+ avdd_ddr_pll_s0: nldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
+ regulator-name = "avdd_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
avdd_0v75_s0: nldo-reg3 {
- regulator-name = "avdd_0v75_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
- vdd_0v85_s0: nldo-reg4 {
- regulator-name = "vdd_0v85_s0";
+ avdd_0v85_s0: nldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
+ regulator-name = "avdd_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
vdd_0v75_s0: nldo-reg5 {
- regulator-name = "vdd_0v75_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
-&u2phy2 {
- status = "okay";
-};
-
-&u2phy2_host {
+&tsadc {
status = "okay";
- phy-supply = <&vcc5v0_host>;
};
-&u2phy3 {
+&u2phy2 {
status = "okay";
};
-&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
+&u2phy2_host {
+ phy-supply = <&vcc5v0_host_20>;
status = "okay";
};
&usb_host0_ehci {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wl_reset &wl_dis &wl_wake_host &bt_dis &bt_wake_host>;
};
&usb_host0_ohci {
status = "okay";
};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usb_host2_xhci {
- status = "okay";
-};
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
no-sdio;
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
+ clocks = <&cru PCLK_VO1GRF>;
};
php_grf: syscon@fd5b0000 {
};
};
+ hdptxphy0_grf: syscon@fd5e0000 {
+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
+ reg = <0x0 0xfd5e0000 0x0 0x100>;
+ };
+
ioc: syscon@fd5f0000 {
compatible = "rockchip,rk3588-ioc", "syscon";
reg = <0x0 0xfd5f0000 0x0 0x10000>;
dmas = <&dmac1 0>, <&dmac1 1>;
dma-names = "tx", "rx";
power-domains = <&power RK3588_PD_AUDIO>;
- rockchip,trcm-sync-tx-only;
pinctrl-names = "default";
pinctrl-0 = <&i2s2m1_lrck
&i2s2m1_sclk
dmas = <&dmac1 2>, <&dmac1 3>;
dma-names = "tx", "rx";
power-domains = <&power RK3588_PD_AUDIO>;
- rockchip,trcm-sync-tx-only;
pinctrl-names = "default";
pinctrl-0 = <&i2s3_lrck
&i2s3_sclk
#dma-cells = <1>;
};
+ hdptxphy_hdmi0: phy@fed60000 {
+ compatible = "rockchip,rk3588-hdptx-phy";
+ reg = <0x0 0xfed60000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
+ clock-names = "ref", "apb";
+ #phy-cells = <0>;
+ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
+ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
+ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
+ <&cru SRST_HDPTX0_LCPLL>;
+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
+ "lcpll";
+ rockchip,grf = <&hdptxphy0_grf>;
+ status = "disabled";
+ };
+
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
+
+ ck_icn_p_vdec: ck-icn-p-vdec {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+
+ ck_icn_p_venc: ck-icn-p-venc {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
};
firmware {
#include "stm32mp253.dtsi"
/ {
+ soc@0 {
+ rifsc: rifsc-bus@42080000 {
+ vdec: vdec@480d0000 {
+ compatible = "st,stm32mp25-vdec";
+ reg = <0x480d0000 0x3c8>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ck_icn_p_vdec>;
+ };
+
+ venc: venc@480e0000 {
+ compatible = "st,stm32mp25-venc";
+ reg = <0x480e0000 0x800>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ck_icn_ls_mcu>;
+ };
+ };
+ };
};
clocks = <&clock_peric PERIC_PCLK_UART0>,
<&clock_peric PERIC_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
+ samsung,uart-fifosize = <64>;
status = "disabled";
};
clocks = <&clock_peric PERIC_PCLK_UART1>,
<&clock_peric PERIC_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
+ samsung,uart-fifosize = <64>;
status = "disabled";
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* AM62x LP SK: https://www.ti.com/tool/SK-AM62-LP
*
- * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family Main Domain peripherals
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
};
};
- main_conf: syscon@100000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x00 0x00100000 0x00 0x20000>;
+ main_conf: bus@100000 {
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x00100000 0x20000>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 57 6>;
assigned-clock-parents = <&k3_clks 57 8>;
+ bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
- ti,trm-icp = <0x2>;
- bus-width = <8>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
clock-names = "clk_ahb", "clk_xin";
- ti,trm-icp = <0x2>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x8>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sd-hs = <0x1>;
ti,itap-del-sel-sdr12 = <0xa>;
ti,itap-del-sel-sdr25 = <0x1>;
- ti,clkbuf-sel = <0x7>;
- bus-width = <4>;
status = "disabled";
};
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
clock-names = "clk_ahb", "clk_xin";
- ti,trm-icp = <0x2>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x8>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sd-hs = <0xa>;
ti,itap-del-sel-sdr12 = <0xa>;
ti,itap-del-sel-sdr25 = <0x1>;
- ti,clkbuf-sel = <0x7>;
status = "disabled";
};
interrupt-names = "host", "peripheral";
maximum-speed = "high-speed";
dr_mode = "otg";
+ snps,usb2-gadget-lpm-disable;
+ snps,usb2-lpm-disable;
};
};
interrupt-names = "host", "peripheral";
maximum-speed = "high-speed";
dr_mode = "otg";
+ snps,usb2-gadget-lpm-disable;
+ snps,usb2-lpm-disable;
};
};
<0x00 0x30207000 0x00 0x1000>, /* ovr1 */
<0x00 0x30208000 0x00 0x1000>, /* ovr2 */
<0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
- <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */
+ <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
+ <0x00 0x30201000 0x00 0x1000>; /* common1 */
reg-names = "common", "vidl1", "vid",
- "ovr1", "ovr2", "vp1", "vp2";
+ "ovr1", "ovr2", "vp1", "vp2", "common1";
power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 186 6>,
<&dss_vp1_clk>,
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family MCU Domain peripherals
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH
+ * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
non-removable;
status = "okay";
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
#include <dt-bindings/thermal/thermal.h>
/* Verdin SD_1 */
&sdhci1 {
- ti,driver-strength-ohm = <33>;
status = "okay";
};
/* Verdin SD_1 */
&sdhci1 {
- ti,driver-strength-ohm = <33>;
status = "okay";
};
<&pinctrl_qspi1_cs2_gpio>;
cs-gpios = <0>, <&main_gpio0 12 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <18500000>;
+ };
};
/* Verdin UART_3 */
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
ti,fails-without-test-cd;
- ti,driver-strength-ohm = <50>;
vmmc-supply = <®_3v3>;
status = "okay";
};
usb1 = &usb1;
};
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_id>;
+ id-gpios = <&main_gpio1 19 GPIO_ACTIVE_HIGH>;
+ label = "USB_1";
+ self-powered;
+ vbus-supply = <®_usb0_vbus>;
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb0_ep>;
+ };
+ };
+ };
+
verdin_gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
vin-supply = <®_sd_3v3_1v8>;
};
+ reg_usb0_vbus: regulator-usb0-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_en>;
+ enable-active-high;
+ /* Verdin USB_1_EN (SODIMM 155) */
+ gpio = <&main_gpio1 50 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "USB_1_EN";
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
>;
};
+ /* Verdin USB_1_EN */
+ pinctrl_usb0_en: main-gpio1-50-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0254, PIN_INPUT, 7) /* (C20) USB0_DRVVBUS.GPIO1_50 */ /* SODIMM 155 */
+ >;
+ };
+
/* On-module I2C - PMIC_I2C */
pinctrl_i2c0: main-i2c0-default-pins {
pinctrl-single,pins = <
>;
};
- /* Verdin USB_1 */
- pinctrl_usb0: main-usb0-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */
- >;
- };
-
/* Verdin USB_2 */
pinctrl_usb1: main-usb1-default-pins {
pinctrl-single,pins = <
"",
"",
"SODIMM_17",
- "", /* 50 */
+ "SODIMM_155", /* 50 */
"",
"",
"",
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <850000>;
- regulator-min-microvolt = <850000>;
+ regulator-min-microvolt = <750000>;
regulator-name = "+VDD_CORE (PMIC BUCK1)";
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0>;
non-removable;
- ti,driver-strength-ohm = <50>;
status = "okay";
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1>;
disable-wp;
- ti,driver-strength-ohm = <50>;
vmmc-supply = <®_sdhc1_vmmc>;
vqmmc-supply = <®_sdhc1_vqmmc>;
status = "disabled";
status = "disabled";
};
-/* TODO: role swich using ID pin */
&usb0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb0_id>;
+ adp-disable;
+ usb-role-switch;
status = "disabled";
+
+ port {
+ usb0_ep: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
+ };
};
/* Verdin USB_2 */
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/bus/ti-sysc.h>
+
&cbass_wakeup {
wkup_conf: syscon@43000000 {
bootph-all;
};
};
- wkup_uart0: serial@2b300000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x2b300000 0x00 0x100>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ target-module@2b300050 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x00 0x2b300050 0x00 0x4>,
+ <0x00 0x2b300054 0x00 0x4>,
+ <0x00 0x2b300058 0x00 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ ti,no-reset-on-init;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
- clock-names = "fclk";
- status = "disabled";
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x2b300000 0x100000>;
+
+ wkup_uart0: serial@0 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
};
wkup_i2c0: i2c@2b200000 {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62 SoC Family
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* ALINX AN5641 & Digilent PCam 5C - OV5640 camera module
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Technexion TEVI-OV5640-*-RPI - OV5640 camera module
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* https://beagleplay.org/
*
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
- * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation
*/
/dts-v1/;
i2c3 = &main_i2c3;
i2c4 = &wkup_i2c0;
i2c5 = &mcu_i2c0;
- mdio-gpio0 = &mdio0;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
mmc2 = &sdhci2;
};
};
- /* Workaround for errata i2329 - just use mdio bitbang */
- mdio0: mdio {
- compatible = "virtual,mdio-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&mdio0_pins_default>;
- gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */
- <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw3g_phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- cpsw3g_phy1: ethernet-phy@1 {
- reg = <1>;
- reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
- reset-assert-us = <25>;
- reset-deassert-us = <60000>; /* T2 */
- };
- };
};
&main_pmx0 {
mdio0_pins_default: mdio0-default-pins {
pinctrl-single,pins = <
- AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */
- AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */
+ AM62X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
+ AM62X_IOPAD(0x015c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
>;
};
};
&usbss0 {
+ bootph-all;
ti,vbus-divider;
status = "okay";
};
&usb0 {
+ bootph-all;
dr_mode = "peripheral";
};
};
&cpsw3g_mdio {
- /* Workaround for errata i2329 - Use mdio bitbang */
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio0_pins_default>;
+
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ cpsw3g_phy1: ethernet-phy@1 {
+ reg = <1>;
+ reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <25>;
+ reset-deassert-us = <60000>; /* T2 */
+ };
};
&main_gpio0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
status = "okay";
};
vmmc-supply = <&vdd_3v3_sd>;
vqmmc-supply = <&vdd_sd_dv>;
- ti,driver-strength-ohm = <50>;
disable-wp;
cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>;
cd-debounce-delay-ms = <100>;
vmmc-supply = <&wlan_en>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>;
- bus-width = <4>;
non-removable;
ti,fails-without-test-cd;
cap-power-off-card;
keep-power-in-suspend;
- ti,driver-strength-ohm = <50>;
assigned-clocks = <&k3_clks 157 158>;
assigned-clock-parents = <&k3_clks 157 160>;
#address-cells = <1>;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH
+ * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
cpsw3g_phy3: ethernet-phy@3 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
reg = <3>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
vqmmc-supply = <&vddshv5_sdio>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
no-1-8-v;
status = "okay";
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* AM625 SK: https://www.ti.com/lit/zip/sprr448
*
- * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC family in Quad core configuration
*
* TRM: https://www.ti.com/lit/pdf/spruiv7
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A SoC Family Main Domain peripherals
*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
};
};
- main_conf: syscon@100000 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00 0x00100000 0x00 0x20000>;
+ main_conf: bus@100000 {
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x20000>;
status = "disabled";
};
+ sdhci0: mmc@fa10000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
+ clock-names = "clk_ahb", "clk_xin";
+ assigned-clocks = <&k3_clks 57 6>;
+ assigned-clock-parents = <&k3_clks 57 8>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-hs200 = <0x6>;
+ status = "disabled";
+ };
+
sdhci1: mmc@fa00000 {
compatible = "ti,am62-sdhci";
reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
clock-names = "clk_ahb", "clk_xin";
- ti,trm-icp = <0x2>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
- ti,clkbuf-sel = <0x7>;
+ no-1-8-v;
+ status = "disabled";
+ };
+
+ sdhci2: mmc@fa20000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
+ clock-names = "clk_ahb", "clk_xin";
bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
no-1-8-v;
status = "disabled";
};
power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
+
+ dss: dss@30200000 {
+ compatible = "ti,am62a7-dss";
+ reg = <0x00 0x30200000 0x00 0x1000>, /* common */
+ <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
+ <0x00 0x30206000 0x00 0x1000>, /* vid */
+ <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
+ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
+ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */
+ <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
+ <0x00 0x30201000 0x00 0x1000>; /* common1 */
+ reg-names = "common", "vidl1", "vid",
+ "ovr1", "ovr2", "vp1", "vp2", "common1";
+ power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 186 6>,
+ <&k3_clks 186 0>,
+ <&k3_clks 186 2>;
+ clock-names = "fck", "vp1", "vp2";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ dss_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family MCU Domain peripherals
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
#include <dt-bindings/thermal/thermal.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_wakeup {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A SoC Family
*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* AM62A SK: https://www.ti.com/lit/zip/sprr459
*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
serial0 = &wkup_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
+ mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
clock-frequency = <12288000>;
};
+ hdmi0: connector-hdmi {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&sii9022_out>;
+ };
+ };
+ };
+
codec_audio: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "AM62Ax-SKEVM";
};
&main_pmx0 {
+ main_dss0_pins_default: main-dss0-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x100, PIN_OUTPUT, 0) /* (V17) VOUT0_VSYNC */
+ AM62AX_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (T18) VOUT0_HSYNC */
+ AM62AX_IOPAD(0x104, PIN_OUTPUT, 0) /* (AA22) VOUT0_PCLK */
+ AM62AX_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (U17) VOUT0_DE */
+ AM62AX_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
+ AM62AX_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (U21) VOUT0_DATA1 */
+ AM62AX_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (U20) VOUT0_DATA2 */
+ AM62AX_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (U19) VOUT0_DATA3 */
+ AM62AX_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (T19) VOUT0_DATA4 */
+ AM62AX_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (U18) VOUT0_DATA5 */
+ AM62AX_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V22) VOUT0_DATA6 */
+ AM62AX_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA7 */
+ AM62AX_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V19) VOUT0_DATA8 */
+ AM62AX_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (V18) VOUT0_DATA9 */
+ AM62AX_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */
+ AM62AX_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA11 */
+ AM62AX_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (W20) VOUT0_DATA12 */
+ AM62AX_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (W19) VOUT0_DATA13 */
+ AM62AX_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y21) VOUT0_DATA14 */
+ AM62AX_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA15 */
+ AM62AX_IOPAD(0x05c, PIN_OUTPUT, 1) /* (P22) GPMC0_AD8.VOUT0_DATA16 */
+ AM62AX_IOPAD(0x060, PIN_OUTPUT, 1) /* (R19) GPMC0_AD9.VOUT0_DATA17 */
+ AM62AX_IOPAD(0x064, PIN_OUTPUT, 1) /* (R20) GPMC0_AD10.VOUT0_DATA18 */
+ AM62AX_IOPAD(0x068, PIN_OUTPUT, 1) /* (R22) GPMC0_AD11.VOUT0_DATA19 */
+ AM62AX_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
+ AM62AX_IOPAD(0x070, PIN_OUTPUT, 1) /* (R21) GPMC0_AD13.VOUT0_DATA21 */
+ AM62AX_IOPAD(0x074, PIN_OUTPUT, 1) /* (T20) GPMC0_AD14.VOUT0_DATA22 */
+ AM62AX_IOPAD(0x078, PIN_OUTPUT, 1) /* (T21) GPMC0_AD15.VOUT0_DATA23 */
+ >;
+ };
+
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
>;
};
+ main_mmc0_pins_default: main-mmc0-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
+ AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */
+ AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
+ AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
+ AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
+ AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
+ AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
+ AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
+ AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
+ AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
+ AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
+ >;
+ };
+
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
"CSI_EN", "AUTO_100M_1000M_CONFIG",
"CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST";
};
+
+ sii9022: bridge-hdmi@3b {
+ compatible = "sil,sii9022";
+ reg = <0x3b>;
+ interrupt-parent = <&exp1>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ #sound-dai-cells = <0>;
+ sil,i2s-data-lanes = < 0 >;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sii9022_in: endpoint {
+ remote-endpoint = <&dpi1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ sii9022_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
};
&main_i2c2 {
clock-frequency = <400000>;
};
+&sdhci0 {
+ /* eMMC */
+ status = "okay";
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc0_pins_default>;
+ disable-wp;
+};
+
&sdhci1 {
/* SD/MMC */
status = "okay";
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
};
tx-num-evt = <32>;
rx-num-evt = <32>;
};
+
+&dss {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_dss0_pins_default>;
+};
+
+&dss_ports {
+ /* VP2: DPI Output */
+ port@1 {
+ reg = <1>;
+
+ dpi1_out: endpoint {
+ remote-endpoint = <&sii9022_in>;
+ };
+ };
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A7 SoC family in Quad core configuration
*
* TRM: https://www.ti.com/lit/zip/spruj16
*
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree file for the AM62P main domain peripherals
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
};
};
+ dmss_csi: bus@4e000000 {
+ compatible = "simple-bus";
+ ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ti,sci-dev-id = <198>;
+
+ inta_main_dmss_csi: interrupt-controller@4e400000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x4e400000 0x00 0x8000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <200>;
+ ti,interrupt-ranges = <0 237 8>;
+ ti,unmapped-event-sources = <&main_bcdma_csi>;
+ };
+
+ main_bcdma_csi: dma-controller@4e230000 {
+ compatible = "ti,am62a-dmss-bcdma-csirx";
+ reg = <0x00 0x4e230000 0x00 0x100>,
+ <0x00 0x4e180000 0x00 0x8000>,
+ <0x00 0x4e100000 0x00 0x10000>;
+ reg-names = "gcfg", "rchanrt", "ringrt";
+ #dma-cells = <3>;
+ msi-parent = <&inta_main_dmss_csi>;
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <199>;
+ ti,sci-rm-range-rchan = <0x21>;
+ };
+ };
+
dmsc: system-controller@44043000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 57 2>;
assigned-clock-parents = <&k3_clks 57 4>;
- ti,otap-del-sel-legacy = <0x0>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ ti,clkbuf-sel = <0x7>;
+ ti,strobe-sel = <0x77>;
+ ti,trm-icp = <0x8>;
+ ti,otap-del-sel-legacy = <0x1>;
+ ti,otap-del-sel-mmc-hs = <0x1>;
+ ti,otap-del-sel-ddr52 = <0x6>;
+ ti,otap-del-sel-hs200 = <0x8>;
+ ti,otap-del-sel-hs400 = <0x5>;
+ ti,itap-del-sel-legacy = <0x10>;
+ ti,itap-del-sel-mmc-hs = <0xa>;
+ ti,itap-del-sel-ddr52 = <0x3>;
status = "disabled";
};
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
clock-names = "clk_ahb", "clk_xin";
- ti,otap-del-sel-legacy = <0x8>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
status = "disabled";
};
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
clock-names = "clk_ahb", "clk_xin";
- ti,otap-del-sel-legacy = <0x8>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
status = "disabled";
};
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
+
+ ti_csi2rx0: ticsi2rx@30102000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ reg = <0x00 0x30102000 0x00 0x1000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dmas = <&main_bcdma_csi 0 0x5000 0>;
+ dma-names = "rx0";
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ cdns_csi2rx0: csi-bridge@30101000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x00 0x30101000 0x00 0x1000>;
+ clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
+ <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi0_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi0_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi0_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi0_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ dphy0: phy@30110000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x00 0x30110000 0x00 0x1100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ vpu: video-codec@30210000 {
+ compatible = "ti,j721s2-wave521c", "cnm,wave521c";
+ reg = <0x00 0x30210000 0x00 0x10000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 204 2>;
+ power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
+ };
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree file for the AM62P MCU domain peripherals
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
ranges = <0x79000000 0x00 0x79000000 0x8000>,
<0x79020000 0x00 0x79020000 0x8000>;
power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
mcu_r5fss0_core0: r5f@79000000 {
compatible = "ti,am62-r5f";
reg = <0x79000000 0x00008000>,
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
#include <dt-bindings/thermal/thermal.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree file for the AM62P wakeup domain peripherals
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_wakeup {
ranges = <0x78000000 0x00 0x78000000 0x8000>,
<0x78100000 0x00 0x78100000 0x8000>;
power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
wkup_r5fss0_core0: r5f@78000000 {
compatible = "ti,am62-r5f";
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62P SoC Family
*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
- <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
+ <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree file for the AM62P5-SK
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*
* Schematics: https://www.ti.com/lit/zip/sprr487
*/
status = "okay";
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};
&sdhci1 {
vqmmc-supply = <&vddshv_sdio>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
- no-1-8-v;
bootph-all;
};
};
&cpsw3g_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mdio1_pins_default>;
+ status = "okay";
+
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree file for the AM62P5 SoC family (quad core)
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*
* TRM: https://www.ti.com/lit/pdf/spruj83
*/
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+#include "k3-pinctrl.h"
+
+&{/} {
+ fan: gpio-fan {
+ compatible = "gpio-fan";
+ gpio-fan,speed-map = <0 0 8600 1>;
+ gpios = <&main_gpio0 40 GPIO_ACTIVE_LOW>;
+ #cooling-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_fan_pins_default>;
+ };
+};
+
+&main_pmx0 {
+ gpio_fan_pins_default: gpio-fan-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0a4, PIN_OUTPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */
+ >;
+ };
+};
+
+&thermal_zones {
+ main0_thermal: main0-thermal {
+ trips {
+ main0_thermal_trip0: main0-thermal-trip {
+ temperature = <65000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&main0_thermal_trip0>;
+ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Common dtsi for AM62x SK and derivatives
*
- * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/leds/common.h>
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
};
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
};
};
&usbss0 {
+ bootph-all;
status = "okay";
ti,vbus-divider;
};
};
&usb0 {
+ bootph-all;
#address-cells = <1>;
#size-cells = <0>;
usb-role-switch;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* IMX219 (RPi v2) Camera Module
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* ALINX AN5641 & Digilent PCam 5C - OV5640 camera module
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Technexion TEVI-OV5640-*-RPI - OV5640 camera module
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* Audio playback via HDMI for AM625-SK and AM62-LP SK.
*
* AM625 SK: https://www.ti.com/tool/SK-AM62
* AM62-LP SK: https://www.ti.com/tool/SK-AM62-LP
*
- * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM642 SoC Family Main Domain peripherals
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/phy/phy-cadence.h>
reg = <0x00000014 0x4>;
};
- serdes_ln_ctrl: mux-controller {
- compatible = "mmio-mux";
+ serdes_ln_ctrl: mux-controller@4080 {
+ compatible = "reg-mux";
+ reg = <0x4080 0x4>;
#mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
+ mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
};
phy_gmii_sel: phy@4044 {
power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
clock-names = "clk_ahb", "clk_xin";
+ bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
+ ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x2>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x6>;
ti,otap-del-sel-hs200 = <0x7>;
+ ti,itap-del-sel-legacy = <0x10>;
+ ti,itap-del-sel-mmc-hs = <0xa>;
+ ti,itap-del-sel-ddr52 = <0x3>;
status = "disabled";
};
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
clock-names = "clk_ahb", "clk_xin";
- ti,trm-icp = <0x2>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x6>;
ti,otap-del-sel-ddr50 = <0x9>;
- ti,clkbuf-sel = <0x7>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
status = "disabled";
};
status = "disabled";
};
- pcie0_ep: pcie-ep@f102000 {
- compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
- reg = <0x00 0x0f102000 0x00 0x1000>,
- <0x00 0x0f100000 0x00 0x400>,
- <0x00 0x0d000000 0x00 0x00800000>,
- <0x00 0x68000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
- max-link-speed = <2>;
- num-lanes = <1>;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 114 0>;
- clock-names = "fck";
- max-functions = /bits/ 8 <1>;
- status = "disabled";
- };
-
epwm0: pwm@23000000 {
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
};
};
+ icssg0_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
+ icssg0_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
};
};
+ icssg1_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
+ icssg1_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM64 SoC Family MCU Domain peripherals
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
+ * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
* Author: Matt McKee <mmckee@phytec.com>
*
- * Copyright (C) 2022 PHYTEC Messtechnik GmbH
+ * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
disable-wp;
keep-power-in-suspend;
};
+
+&tscadc0 {
+ status = "okay";
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
#include <dt-bindings/thermal/thermal.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM642 SoC Family
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT overlay for enabling 2nd ICSSG1 port on AM642 EVM
+ *
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/icssg1-eth/ethernet-ports/port@1";
+ };
+
+ mdio-mux-2 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mdio_mux>;
+ mdio-parent-bus = <&icssg1_mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg1_phy2: ethernet-phy@3 {
+ reg = <3>;
+ tx-internal-delay-ps = <250>;
+ rx-internal-delay-ps = <2000>;
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
+ AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
+ AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
+ AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
+ AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
+ AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+ AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
+ AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
+ AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
+ AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
+ AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
+ AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+ >;
+ };
+};
+
+&cpsw3g {
+ pinctrl-0 = <&rgmii1_pins_default>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
+
+&mdio_mux_1 {
+ status = "disabled";
+};
+
+&icssg1_eth {
+ pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>;
+};
+
+&icssg1_emac1 {
+ status = "okay";
+ phy-handle = <&icssg1_phy2>;
+ phy-mode = "rgmii-id";
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
mmc1 = &sdhci1;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
+ ethernet2 = &icssg1_emac0;
};
memory@80000000 {
mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
};
- mdio-mux-1 {
+ mdio_mux_1: mdio-mux-1 {
compatible = "mdio-mux-multiplexer";
mux-controls = <&mdio_mux>;
mdio-parent-bus = <&cpsw3g_mdio>;
max-bitrate = <5000000>;
standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
};
+
+ icssg1_eth: icssg1-eth {
+ compatible = "ti,am642-icssg-prueth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg1_rgmii1_pins_default>;
+ sram = <&oc_sram>;
+ ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
+ firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
+ "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
+ "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
+ "ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
+ "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
+ "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";
+
+ ti,pruss-gp-mux-sel = <2>, /* MII mode */
+ <2>,
+ <2>,
+ <2>, /* MII mode */
+ <2>,
+ <2>;
+ ti,mii-g-rt = <&icssg1_mii_g_rt>;
+ ti,mii-rt = <&icssg1_mii_rt>;
+ ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
+ interrupt-parent = <&icssg1_intc>;
+ interrupts = <24 0 2>, <25 1 3>;
+ interrupt-names = "tx_ts0", "tx_ts1";
+ dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
+ <&main_pktdma 0xc201 15>, /* egress slice 0 */
+ <&main_pktdma 0xc202 15>, /* egress slice 0 */
+ <&main_pktdma 0xc203 15>, /* egress slice 0 */
+ <&main_pktdma 0xc204 15>, /* egress slice 1 */
+ <&main_pktdma 0xc205 15>, /* egress slice 1 */
+ <&main_pktdma 0xc206 15>, /* egress slice 1 */
+ <&main_pktdma 0xc207 15>, /* egress slice 1 */
+ <&main_pktdma 0x4200 15>, /* ingress slice 0 */
+ <&main_pktdma 0x4201 15>; /* ingress slice 1 */
+ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+ "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+ "rx0", "rx1";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ icssg1_emac0: port@0 {
+ reg = <0>;
+ phy-handle = <&icssg1_phy1>;
+ phy-mode = "rgmii-id";
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ icssg1_emac1: port@1 {
+ reg = <1>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ };
+ };
+ };
};
&main_pmx0 {
AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
>;
};
+
+ icssg1_mdio1_pins_default: icssg1-mdio1-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */
+ AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */
+ >;
+ };
+
+ icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
+ AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
+ AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
+ AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
+ AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
+ AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
+ AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
+ AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
+ AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
+ AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
+ AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
+ AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
+ >;
+ };
};
&main_uart0 {
/* eMMC */
&sdhci0 {
status = "okay";
- bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};
/* SD/MMC */
status = "okay";
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
- bus-width = <4>;
pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
};
};
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
num-lanes = <1>;
};
-&pcie0_ep {
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <1>;
-};
-
&ecap0 {
status = "okay";
/* PWM is available on Pin 1 of header J12 */
pinctrl-0 = <&main_mcan1_pins_default>;
phys = <&transceiver2>;
};
+
+&icssg1_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg1_mdio1_pins_default>;
+
+ icssg1_phy1: ethernet-phy@f {
+ reg = <0xf>;
+ tx-internal-delay-ps = <250>;
+ rx-internal-delay-ps = <2000>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for SolidRun AM642 HummingBoard-T to enable PCI-E.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-serdes.h"
+
+&pcie0_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_pins>;
+ reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+ status = "okay";
+};
+
+&serdes0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ serdes0_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ #phy-cells = <0>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_PCIE0>;
+};
+
+&serdes_mux {
+ idle-state = <1>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for SolidRun AM642 HummingBoard-T to enable USB-3.1.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-serdes.h"
+
+&serdes0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ serdes0_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ #phy-cells = <0>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_USB>;
+};
+
+&serdes_mux {
+ idle-state = <0>;
+};
+
+&usbss0 {
+ /delete-property/ ti,usb2-only;
+};
+
+&usb0 {
+ maximum-speed = "super-speed";
+ phys = <&serdes0_link>;
+ phy-names = "cdns3,usb3-phy";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
+ *
+ * DTS for SolidRun AM642 HummingBoard-T,
+ * running on Cortex A53.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-am642.dtsi"
+#include "k3-am642-sr-som.dtsi"
+
+/ {
+ model = "SolidRun AM642 HummingBoard-T";
+ compatible = "solidrun,am642-hummingboard-t", "solidrun,am642-sr-som", "ti,am642";
+
+ aliases {
+ serial5 = &main_uart3;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_default_pins>;
+
+ /* D24 */
+ led1: led-1 {
+ label = "led1";
+ gpios = <&main_gpio0 29 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ /* D25 */
+ led2: led-2 {
+ label = "led2";
+ gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ /* D26 */
+ led3: led-3 {
+ label = "led3";
+ gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ };
+
+ regulator-m2-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <®ulator_pcie_3v3_default_pins>;
+ regulator-name = "m2-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&main_gpio1 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ regulator-vpp-1v8 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <®ulator_vpp_1v8_default_pins>;
+ regulator-name = "vpp-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&main_gpio1 78 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ serdes_mux: mux-controller {
+ compatible = "gpio-mux";
+ pinctrl-names = "default";
+ pinctrl-0 = <&serdes_mux_default_pins>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux has 2 IOs:
+ * - select: 0 = USB-3 (M2); 1 = PCIE (M1)
+ * - shutdown: 0 = active; 1 = disabled (high impedance)
+ */
+ mux-gpios = <&main_gpio1 40 GPIO_ACTIVE_HIGH>, <&main_gpio1 41 GPIO_ACTIVE_HIGH>;
+ /* default disabled */
+ idle-state = <2>;
+ };
+};
+
+&main_gpio0 {
+ m2-reset-hog {
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_LOW>;
+ output-low; /* deasserted */
+ line-name = "m2-reset";
+ };
+
+ m1-m2-w-disable1-hog {
+ gpio-hog;
+ gpios = <32 GPIO_ACTIVE_LOW>;
+ output-low; /* deasserted */
+ line-name = "m1-m2-pcie-w-disable1";
+ };
+
+ m1-m2-w-disable2-hog {
+ gpio-hog;
+ gpios = <34 GPIO_ACTIVE_LOW>;
+ output-low; /* deasserted */
+ line-name = "m1-m2-pcie-w-disable2";
+ };
+};
+
+&main_gpio1 {
+ m1-pcie-clkreq0-hog {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "m1-pcie-clkreq0";
+ };
+
+ m2-pcie-clkreq-hog {
+ gpio-hog;
+ gpios = <35 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "m2-pcie-clkreq";
+ };
+};
+
+&main_i2c0 {
+ pinctrl-0 = <&main_i2c0_default_pins>, <&main_i2c0_int_default_pins>;
+
+ humidity-sensor@41 {
+ compatible = "ti,hdc2010";
+ reg = <0x41>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <37 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ light-sensor@44 {
+ compatible = "ti,opt3001";
+ reg = <0x44>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <37 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ /* charger@6a */
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_default_pins>;
+ status = "okay";
+
+ rtc@69 {
+ compatible = "abracon,abx80x";
+ reg = <0x69>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_int_default_pins>;
+ abracon,tc-diode = "schottky";
+ abracon,tc-resistor = <3>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <44 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&main_mcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan0_default_pins>;
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <8000000>;
+ };
+};
+
+&main_mcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan1_default_pins>;
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <8000000>;
+ };
+};
+
+&main_pmx0 {
+ leds_default_pins: leds-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0074, PIN_OUTPUT, 7) /* GPMC0_AD14.GPIO0_29 */
+ AM64X_IOPAD(0x0078, PIN_OUTPUT, 7) /* GPMC0_AD15.GPIO0_30 */
+ AM64X_IOPAD(0x0088, PIN_OUTPUT, 7) /* GPMC0_OEn_REn.GPIO0_33 */
+ >;
+ };
+
+ main_i2c0_int_default_pins: main-i2c0-int-default-pins {
+ pinctrl-single,pins = <
+ /* external pull-up on Carrier */
+ AM64X_IOPAD(0x0098, PIN_INPUT, 7) /* GPMC0_WAIT0.GPIO0_37 */
+ >;
+ };
+
+ main_i2c1_default_pins: main-i2c1-default-pins {
+ pinctrl-single,pins = <
+ /* external pull-up on SoM */
+ AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* I2C1_SCL.I2C1_SCL */
+ AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* I2C1_SDA.I2C1_SDA */
+ >;
+ };
+
+ main_mcan0_default_pins: main-mcan0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* MCAN0_RX.MCAN0_RX */
+ AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* MCAN0_TX.MCAN0_TX */
+ >;
+ };
+
+ main_mcan1_default_pins: main-mcan1-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* MCAN1_RX.MCAN1_RX */
+ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* MCAN1_TX.MCAN1_TX */
+ >;
+ };
+
+ main_uart3_default_pins: main-uart3-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x016c, PIN_INPUT, 10) /* PRG0_PRU0_GPO3.UART3_CTSn */
+ AM64X_IOPAD(0x0170, PIN_OUTPUT, 10) /* PRG0_PRU0_GPO4.UART3_TXD */
+ AM64X_IOPAD(0x0174, PIN_OUTPUT, 10) /* PRG0_PRU0_GPO5.UART3_RTSn */
+ AM64X_IOPAD(0x01ac, PIN_INPUT, 10) /* PRG0_PRU0_GPO19.UART3_RXD */
+ >;
+ };
+
+ pcie0_default_pins: pcie0-default-pins {
+ pinctrl-single,pins = <
+ /* connector M2 RESET */
+ AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* OSPI0_CSn1.GPIO0_12 */
+ /* connectors M1 & M2 W_DISABLE1 */
+ AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* GPMC0_ADVN_ALE.GPIO0_32 */
+ /* connectors M1 & M2 W_DISABLE2 */
+ AM64X_IOPAD(0x008c, PIN_OUTPUT, 7) /* GPMC0_WEN.GPIO0_34 */
+ /* connectors M1 & M2 PERST0 (PCI Reset) */
+ AM64X_IOPAD(0x019c, PIN_OUTPUT, 7) /* PRG0_PRU0_GPO15.GPIO1_15 */
+ /* connector M1 CLKREQ0 */
+ AM64X_IOPAD(0x018c, PIN_INPUT, 7) /* PRG0_PRU0_GPO11.GPIO1_11 */
+ /* connector M2 CLKREQ0 */
+ AM64X_IOPAD(0x01ec, PIN_INPUT, 7) /* PRG0_PRU1_GPO15.GPIO1_35 */
+ >;
+ };
+
+ regulator_pcie_3v3_default_pins: regulator-pcie-3v3-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01a4, PIN_OUTPUT, 7) /* PRG0_PRU0_GPO17.GPIO1_17 */
+ >;
+ };
+
+ regulator_vpp_1v8_default_pins: regulator-vpp-1v8-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x029c, PIN_OUTPUT, 7) /* MMC1_SDWP.GPIO1_78 */
+ >;
+ };
+
+ rtc_int_default_pins: rtc-int-default-pins {
+ pinctrl-single,pins = <
+ /* external pull-up on Carrier */
+ AM64X_IOPAD(0x00b4, PIN_INPUT, 7) /* GPMC0_CSn3.GPIO0_44 */
+ >;
+ };
+
+ serdes_mux_default_pins: serdes-mux-default-pins {
+ pinctrl-single,pins = <
+ /* SEL, 10k pull-down on carrier, 2.2k pullup on SoM */
+ AM64X_IOPAD(0x0200, PIN_OUTPUT, 7) /* PRG0_MDIO0_MDIO.GPIO1_40 */
+ /* EN */
+ AM64X_IOPAD(0x0204, PIN_OUTPUT, 7) /* PRG0_MDIO0_MDC.GPIO1_41 */
+ >;
+ };
+};
+
+&main_uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart3_default_pins>;
+ uart-has-rtscts;
+ rs485-rts-active-low;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+&usb0 {
+ dr_mode = "host";
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
+ * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
* Author: Matt McKee <mmckee@phytec.com>
*
- * Copyright (C) 2022 PHYTEC Messtechnik GmbH
+ * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
>;
};
+ main_spi0_pins_default: main-spi0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x020c, PIN_OUTPUT, 7) /* (C13) SPI0_CS1.GPIO1_43 */
+ AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
+ AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
+ AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
+ >;
+ };
+
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
phys = <&can_tc2>;
};
+&main_spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_spi0_pins_default>;
+ cs-gpios = <0>, <&main_gpio1 43 GPIO_ACTIVE_LOW>;
+ ti,pindir-d0-out-d1-in;
+
+ tpm@1 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
bus-width = <4>;
- ti,driver-strength-ohm = <50>;
disable-wp;
no-1-8-v;
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
status = "okay";
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
- bus-width = <4>;
pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
disable-wp;
};
};
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
+ *
+ */
+
+#include <dt-bindings/net/ti-dp83869.h>
+
+/ {
+ model = "SolidRun AM642 SoM";
+ compatible = "solidrun,am642-sr-som", "ti,am642";
+
+ aliases {
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &icssg1_emac0;
+ ethernet2 = &icssg1_emac1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ serial2 = &main_uart0;
+ };
+
+ chosen {
+ /* SoC default UART console */
+ stdout-path = "serial2:115200n8";
+ };
+
+ /* PRU Ethernet Controller */
+ ethernet {
+ compatible = "ti,am642-icssg-prueth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>;
+
+ sram = <&oc_sram>;
+ ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
+ firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
+
+ /* configure internal pinmux for mii mode */
+ ti,pruss-gp-mux-sel = <2>, <2>, <2>, <2>, <2>, <2>;
+
+ ti,mii-g-rt = <&icssg1_mii_g_rt>;
+ ti,mii-rt = <&icssg1_mii_rt>;
+ ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
+
+ /*
+ * Configure icssg interrupt controller to map pru-internal
+ * interrupts 8/9 via channels 0/1 to host interrupts 0/1.
+ *
+ * For details see interrupt controller documentation:
+ * Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml
+ */
+ interrupt-parent = <&icssg1_intc>;
+ interrupts = <24 0 2>, <25 1 3>;
+ interrupt-names = "tx_ts0", "tx_ts1";
+
+ dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
+ <&main_pktdma 0xc201 15>, /* egress slice 0 */
+ <&main_pktdma 0xc202 15>, /* egress slice 0 */
+ <&main_pktdma 0xc203 15>, /* egress slice 0 */
+ <&main_pktdma 0xc204 15>, /* egress slice 1 */
+ <&main_pktdma 0xc205 15>, /* egress slice 1 */
+ <&main_pktdma 0xc206 15>, /* egress slice 1 */
+ <&main_pktdma 0xc207 15>, /* egress slice 1 */
+ <&main_pktdma 0x4200 15>, /* ingress slice 0 */
+ <&main_pktdma 0x4201 15>; /* ingress slice 1 */
+ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+ "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+ "rx0", "rx1";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg1_emac0: port@0 {
+ reg = <0>;
+ ti,syscon-rgmii-delay = <&main_conf 0x4110>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ phy-handle = <ðernet_phy2>;
+ phy-mode = "rgmii-id";
+ };
+
+ icssg1_emac1: port@1 {
+ reg = <1>;
+ ti,syscon-rgmii-delay = <&main_conf 0x4114>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ phy-handle = <ðernet_phy1>;
+ phy-mode = "rgmii-id";
+ };
+ };
+ };
+
+ /* DDR16SS0:
+ * - Bank 1 @ 0x080000000-0x0FFFFFFFF: max. 2GB in 32-bit address space
+ * - Bank 2 @ 0x880000000-0x9FFFFFFFF: max. 6GB in 64-bit address space
+ */
+ memory@80000000 {
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000001 0x80000000>;
+ device_type = "memory";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+ };
+
+ vdd_mmc0: regulator-vdd-mmc0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-mmc0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_default_pins>;
+};
+
+&cpsw3g_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio0_default_pins>;
+ status = "okay";
+
+ ethernet_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id2000.a0f1";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet_phy0_default_pins>;
+ ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
+ ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
+ /*
+ * Disable interrupts because ISR never clears 0x0040
+ *
+ * interrupt-parent = <&main_gpio1>;
+ * interrupts = <70 IRQ_TYPE_LEVEL_LOW>;
+ */
+ /*
+ * Disable HW Reset because clock signal is daisy-chained
+ *
+ * reset-gpios = <&main_gpio0 84 GPIO_ACTIVE_LOW>;
+ * reset-assert-us = <1>;
+ * reset-deassert-us = <30>;
+ */
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy0>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pru1_mdio0_default_pins>;
+ status = "okay";
+
+ ethernet_phy1: ethernet-phy@3 {
+ compatible = "ethernet-phy-id2000.a0f1";
+ reg = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet_phy1_default_pins>;
+ ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
+ ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
+ /*
+ * Disable interrupts because ISR never clears 0x0040
+ *
+ * interrupt-parent = <&main_gpio1>;
+ * interrupts = <70 IRQ_TYPE_LEVEL_LOW>;
+ */
+ /*
+ * Disable HW Reset because clock signal is daisy-chained
+ *
+ * reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>;
+ * reset-assert-us = <1>;
+ * reset-deassert-us = <30>;
+ */
+ };
+
+ ethernet_phy2: ethernet-phy@f {
+ compatible = "ethernet-phy-id2000.a0f1";
+ reg = <0xf>;
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet_phy2_default_pins>;
+ ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
+ /*
+ * Disable interrupts because ISR never clears 0x0040
+ *
+ * interrupt-parent = <&main_gpio1>;
+ * interrupts = <70 IRQ_TYPE_LEVEL_LOW>;
+ */
+ /*
+ * Disable HW Reset because clock signal is daisy-chained
+ *
+ * reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>;
+ * reset-assert-us = <1>;
+ * reset-deassert-us = <30>;
+ */
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "okay";
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 2>;
+ ti,mbox-tx = <1 0 2>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 2>;
+ ti,mbox-tx = <3 0 2>;
+ };
+};
+
+&mailbox0_cluster4 {
+ status = "okay";
+
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 2>;
+ ti,mbox-tx = <1 0 2>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 2>;
+ ti,mbox-tx = <3 0 2>;
+ };
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_default_pins>;
+ status = "okay";
+
+ som_eeprom: eeprom@50 {
+ compatible = "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
+};
+
+&main_pmx0 {
+ /* hog global functions */
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet_phy_default_pins>;
+
+ ethernet_phy_default_pins: ethernet-phy-default-pins {
+ pinctrl-single,pins = <
+ /* interrupt / power-down, external pull-up on SoM */
+ AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* EXTINTn.GPIO1_70 */
+ >;
+ };
+
+ ethernet_phy0_default_pins: ethernet-phy0-default-pins {
+ pinctrl-single,pins = <
+ /* reset */
+ AM64X_IOPAD(0x0154, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO19.GPIO0_84 */
+ /* reference clock */
+ AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* EXT_REFCLK1.CLKOUT0 */
+ >;
+ };
+
+ ethernet_phy1_default_pins: ethernet-phy1-default-pins {
+ pinctrl-single,pins = <
+ /* reset */
+ AM64X_IOPAD(0x0150, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO18.GPIO0_20 */
+ /* led0, external pull-down on SoM */
+ AM64X_IOPAD(0x0128, PIN_INPUT, 7) /* PRG1_PRU1_GPO8.GPIO0_73 */
+ /* led1/rxer */
+ AM64X_IOPAD(0x011c, PIN_INPUT, 7) /* PRG1_PRU1_GPO5.GPIO0_70 */
+ >;
+ };
+
+ ethernet_phy2_default_pins: ethernet-phy2-default-pins {
+ pinctrl-single,pins = <
+ /* reset */
+ AM64X_IOPAD(0x00d4, PIN_OUTPUT, 7) /* PRG1_PRU0_GPO7.GPIO0_52 */
+ /* led0, external pull-down on SoM */
+ AM64X_IOPAD(0x00d8, PIN_INPUT, 7) /* PRG1_PRU0_GPO8.GPIO0_53 */
+ /* led1/rxer */
+ AM64X_IOPAD(0x00cc, PIN_INPUT, 7) /* PRG1_PRU0_GPO5.GPIO0_50 */
+ >;
+ };
+
+ main_i2c0_default_pins: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ /* external pull-up on SoM */
+ AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* I2C0_SCL.I2C0_SCL */
+ AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* I2C0_SDA.I2C0_SDA */
+ >;
+ };
+
+ /*
+ * main_mmc0_default_pins: main-mmc0-default-pins
+ *
+ * MMC0_CMD: no padconfig
+ * MMC0_CLK: no padconfig, external pull-up on SoM
+ * MMC0_DAT0: no padconfig
+ * MMC0_DAT1: no padconfig
+ * MMC0_DAT2: no padconfig
+ * MMC0_DAT3: no padconfig
+ * MMC0_DAT4: no padconfig
+ * MMC0_DAT5: no padconfig
+ * MMC0_DAT6: no padconfig
+ * MMC0_DAT7: no padconfig
+ * MMC0_DS: no padconfig, external pull-down on SoM
+ */
+
+ main_mmc1_default_pins: main-mmc1-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
+ AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* MMC1_CLK.MMC1_CLK */
+ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* MMC1_DAT0.MMC1_DAT0 */
+ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* MMC1_DAT1.MMC1_DAT1 */
+ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* MMC1_DAT2.MMC1_DAT2 */
+ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* MMC1_DAT3.MMC1_DAT3 */
+ /* external pull-down on SoM & Carrier */
+ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* MMC1_SDCD.MMC1_SDCD */
+ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB: clock loopback */
+ >;
+ };
+
+ main_uart0_default_pins: main-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* UART0_RXD.UART0_RXD */
+ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* UART0_TXD.UART0_TXD */
+ >;
+ };
+
+ mdio0_default_pins: mdio0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* PRG0_PRU1_GPO19.MDIO0_MDC */
+ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* PRG0_PRU1_GPO18.MDIO0_MDIO */
+ >;
+ };
+
+ ospi0_default_pins: ospi0-default-pins {
+ pinctrl-single,pins = <
+ /* external pull-down on SoM */
+ AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* OSPI0_CLK.OSPI0_CLK */
+ AM64X_IOPAD(0x0008, PIN_OUTPUT, 0) /* OSPI0_DQS.OSPI0_DQS */
+ /* external pull-up on SoM */
+ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* OSPI0_CSn0.OSPI0_CSn0 */
+ AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* OSPI0_D0.OSPI0_D0 */
+ AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* OSPI0_D1.OSPI0_D1 */
+ AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* OSPI0_D2.OSPI0_D2 */
+ AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* OSPI0_D3.OSPI0_D3 */
+ AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* OSPI0_D4.OSPI0_D4 */
+ AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* OSPI0_D5.OSPI0_D5 */
+ AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* OSPI0_D6.OSPI0_D6 */
+ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* OSPI0_D7.OSPI0_D7 */
+ >;
+ };
+
+ ospi0_flash0_default_pins: ospi0-flash0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0034, PIN_OUTPUT, 7) /* OSPI0_CSn2.GPIO0_13 */
+ AM64X_IOPAD(0x0038, PIN_INPUT, 7) /* OSPI0_CSn3.GPIO0_14 */
+ >;
+ };
+
+ pru1_mdio0_default_pins: pru1-mdio0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* PRG1_MDIO0_MDC.PRG1_MDIO0_MDC */
+ AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* PRG1_MDIO0_MDIO.PRG1_MDIO0_MDIO */
+ >;
+ };
+
+ pru_rgmii1_default_pins: pru-rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
+ AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
+ AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
+ AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
+ AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
+ AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
+ AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
+ AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
+ AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
+ AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
+ AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
+ AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
+ >;
+ };
+
+ pru_rgmii2_default_pins: pru-rgmii2-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* PRG1_PRU1_GPO0.RGMII2_RD0 */
+ AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* PRG1_PRU1_GPO1.RGMII2_RD1 */
+ AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* PRG1_PRU1_GPO2.RGMII2_RD2 */
+ AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* PRG1_PRU1_GPO3.RGMII2_RD3 */
+ AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* PRG1_PRU1_GPO6.RGMII2_RXC */
+ AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+ AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO11.RGMII2_TD0 */
+ AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO12.RGMII2_TD1 */
+ AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO13.RGMII2_TD2 */
+ AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO14.RGMII2_TD3 */
+ AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* PRG1_PRU1_GPO16.RGMII2_TXC */
+ AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+ >;
+ };
+
+ rgmii1_default_pins: rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* PRG0_PRU1_GPO7.RGMII1_RD0 */
+ AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* PRG0_PRU1_GPO9.RGMII1_RD1 */
+ AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* PRG0_PRU1_GPO10.RGMII1_RD2 */
+ AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* PRG0_PRU1_GPO17.RGMII1_RD3 */
+ AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* PRG0_PRU0_GPO10.RGMII1_RXC */
+ AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* PRG0_PRU0_GPO9.RGMII1_RX_CTL */
+ AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO7.RGMII1_TD0 */
+ AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO9.RGMII1_TD1 */
+ AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO10.RGMII1_TD2 */
+ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO17.RGMII1_TD3 */
+ AM64X_IOPAD(0x00e0, PIN_INPUT, 4) /* PRG1_PRU0_GPO10.RGMII1_TXC */
+ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+ >;
+ };
+
+ usb0_default_pins: usb0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */
+ >;
+ };
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+/* SoC default UART console */
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_default_pins>;
+ status = "okay";
+};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ospi0_default_pins>;
+ num-cs = <1>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ospi0_flash0_default_pins>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <200000000>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ cdns,read-delay = <0>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&main_gpio0 13 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&sdhci0 {
+ /* mmc0 pins have no padconfig */
+ bus-width = <8>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ non-removable;
+ cap-mmc-hw-reset;
+ no-sd;
+ /*
+ * MMC controller supports switching between 1.8V and 3.3V signalling.
+ * However MMC0 (unlike MMC1) does not integrate an LDO.
+ * Explicitly link a regulator node for indicating to the driver which
+ * voltages are actually usable.
+ */
+ vqmmc-supply = <&vdd_mmc0>;
+ status = "okay";
+};
+
+/*
+ * microSD is on carrier - however since SoC can boot from it,
+ * configure it just in case.
+ */
+&sdhci1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_default_pins>;
+ bus-width = <4>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ status = "okay";
+};
+
+/*
+ * USB settings are a carrier choice - however since SoC can boot from it,
+ * configure as USB-2.0 OTG here, keeping USB-3 serdes disabled.
+ */
+&usb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_default_pins>;
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+};
+
+&usbss0 {
+ ti,vbus-divider;
+ ti,usb2-only;
+};
cd-gpios = <&main_gpio1 77 GPIO_ACTIVE_LOW>;
disable-wp;
no-mmc;
- ti,driver-strength-ohm = <50>;
ti,fails-without-test-cd;
/* Enabled by overlay */
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM642 SoC family in Dual core configuration
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Siemens AG, 2018-2023
+ *
+ * Authors:
+ * Le Jin <le.jin@siemens.com>
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits for IOT2050 variants with Arduino connector
+ */
+
+&wkup_pmx0 {
+ pinctrl-names =
+ "default",
+ "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown",
+ "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown",
+ "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown",
+ "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown",
+ "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown",
+ "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown",
+ "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown",
+ "d13-spi0-clk", "d13-gpio", "d13-gpio-pullup", "d13-gpio-pulldown",
+ "a0-gpio", "a0-gpio-pullup", "a0-gpio-pulldown",
+ "a1-gpio", "a1-gpio-pullup", "a1-gpio-pulldown",
+ "a2-gpio", "a2-gpio-pullup", "a2-gpio-pulldown",
+ "a3-gpio", "a3-gpio-pullup", "a3-gpio-pulldown",
+ "a4-gpio", "a4-gpio-pullup", "a4-gpio-pulldown",
+ "a5-gpio", "a5-gpio-pullup", "a5-gpio-pulldown";
+
+ pinctrl-0 = <&d0_uart0_rxd>;
+ pinctrl-1 = <&d0_uart0_rxd>;
+ pinctrl-2 = <&d0_gpio>;
+ pinctrl-3 = <&d0_gpio_pullup>;
+ pinctrl-4 = <&d0_gpio_pulldown>;
+ pinctrl-5 = <&d1_uart0_txd>;
+ pinctrl-6 = <&d1_gpio>;
+ pinctrl-7 = <&d1_gpio_pullup>;
+ pinctrl-8 = <&d1_gpio_pulldown>;
+ pinctrl-9 = <&d2_uart0_ctsn>;
+ pinctrl-10 = <&d2_gpio>;
+ pinctrl-11 = <&d2_gpio_pullup>;
+ pinctrl-12 = <&d2_gpio_pulldown>;
+ pinctrl-13 = <&d3_uart0_rtsn>;
+ pinctrl-14 = <&d3_gpio>;
+ pinctrl-15 = <&d3_gpio_pullup>;
+ pinctrl-16 = <&d3_gpio_pulldown>;
+ pinctrl-17 = <&d10_spi0_cs0>;
+ pinctrl-18 = <&d10_gpio>;
+ pinctrl-19 = <&d10_gpio_pullup>;
+ pinctrl-20 = <&d10_gpio_pulldown>;
+ pinctrl-21 = <&d11_spi0_d0>;
+ pinctrl-22 = <&d11_gpio>;
+ pinctrl-23 = <&d11_gpio_pullup>;
+ pinctrl-24 = <&d11_gpio_pulldown>;
+ pinctrl-25 = <&d12_spi0_d1>;
+ pinctrl-26 = <&d12_gpio>;
+ pinctrl-27 = <&d12_gpio_pullup>;
+ pinctrl-28 = <&d12_gpio_pulldown>;
+ pinctrl-29 = <&d13_spi0_clk>;
+ pinctrl-30 = <&d13_gpio>;
+ pinctrl-31 = <&d13_gpio_pullup>;
+ pinctrl-32 = <&d13_gpio_pulldown>;
+ pinctrl-33 = <&a0_gpio>;
+ pinctrl-34 = <&a0_gpio_pullup>;
+ pinctrl-35 = <&a0_gpio_pulldown>;
+ pinctrl-36 = <&a1_gpio>;
+ pinctrl-37 = <&a1_gpio_pullup>;
+ pinctrl-38 = <&a1_gpio_pulldown>;
+ pinctrl-39 = <&a2_gpio>;
+ pinctrl-40 = <&a2_gpio_pullup>;
+ pinctrl-41 = <&a2_gpio_pulldown>;
+ pinctrl-42 = <&a3_gpio>;
+ pinctrl-43 = <&a3_gpio_pullup>;
+ pinctrl-44 = <&a3_gpio_pulldown>;
+ pinctrl-45 = <&a4_gpio>;
+ pinctrl-46 = <&a4_gpio_pullup>;
+ pinctrl-47 = <&a4_gpio_pulldown>;
+ pinctrl-48 = <&a5_gpio>;
+ pinctrl-49 = <&a5_gpio_pullup>;
+ pinctrl-50 = <&a5_gpio_pulldown>;
+
+ d0_uart0_rxd: d0-uart0-rxd-pins {
+ pinctrl-single,pins = <
+ /* (P4) MCU_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
+ >;
+ };
+
+ d0_gpio: d0-gpio-pins {
+ pinctrl-single,pins = <
+ /* (P4) WKUP_GPIO0_29 */
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7)
+ >;
+ };
+
+ d0_gpio_pullup: d0-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (P4) WKUP_GPIO0_29 */
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d0_gpio_pulldown: d0-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (P4) WKUP_GPIO0_29 */
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d1_uart0_txd: d1-uart0-txd-pins {
+ pinctrl-single,pins = <
+ /* (P5) MCU_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
+ >;
+ };
+
+ d1_gpio: d1-gpio-pins {
+ pinctrl-single,pins = <
+ /* (P5) WKUP_GPIO0_30 */
+ AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7)
+ >;
+ };
+
+ d1_gpio_pullup: d1-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (P5) WKUP_GPIO0_30 */
+ AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7)
+ >;
+ };
+
+ d1_gpio_pulldown: d1-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (P5) WKUP_GPIO0_30 */
+ AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d2_uart0_ctsn: d2-uart0-ctsn-pins {
+ pinctrl-single,pins = <
+ /* (P1) MCU_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4)
+ >;
+ };
+
+ d2_gpio: d2-gpio-pins {
+ pinctrl-single,pins = <
+ /* (P5) WKUP_GPIO0_31 */
+ AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
+ >;
+ };
+
+ d2_gpio_pullup: d2-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (P5) WKUP_GPIO0_31 */
+ AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
+ >;
+ };
+
+ d2_gpio_pulldown: d2-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (P5) WKUP_GPIO0_31 */
+ AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d3_uart0_rtsn: d3-uart0-rtsn-pins {
+ pinctrl-single,pins = <
+ /* (N3) MCU_UART0_RTSn */
+ AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4)
+ >;
+ };
+
+ d3_gpio: d3-gpio-pins {
+ pinctrl-single,pins = <
+ /* (N3) WKUP_GPIO0_33 */
+ AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7)
+ >;
+ };
+
+ d3_gpio_pullup: d3-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (N3) WKUP_GPIO0_33 */
+ AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7)
+ >;
+ };
+
+ d3_gpio_pulldown: d3-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (N3) WKUP_GPIO0_33 */
+ AM65X_WKUP_IOPAD(0x0054, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d10_spi0_cs0: d10-spi0-cs0-pins {
+ pinctrl-single,pins = <
+ /* (Y4) MCU_SPI0_CS0 */
+ AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)
+ >;
+ };
+
+ d10_gpio: d10-gpio-pins {
+ pinctrl-single,pins = <
+ /* (Y4) WKUP_GPIO0_51 */
+ AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7)
+ >;
+ };
+
+ d10_gpio_pullup: d10-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (Y4) WKUP_GPIO0_51 */
+ AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7)
+ >;
+ };
+
+ d10_gpio_pulldown: d10-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (Y4) WKUP_GPIO0_51 */
+ AM65X_WKUP_IOPAD(0x009c, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d11_spi0_d0: d11-spi0-d0-pins {
+ pinctrl-single,pins = <
+ /* (Y3) MCU_SPI0_D0 */
+ AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0)
+ >;
+ };
+
+ d11_gpio: d11-gpio-pins {
+ pinctrl-single,pins = <
+ /* (Y3) WKUP_GPIO0_49 */
+ AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7)
+ >;
+ };
+
+ d11_gpio_pullup: d11-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (Y3) WKUP_GPIO0_49 */
+ AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7)
+ >;
+ };
+
+ d11_gpio_pulldown: d11-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (Y3) WKUP_GPIO0_49 */
+ AM65X_WKUP_IOPAD(0x0094, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d12_spi0_d1: d12-spi0-d1-pins {
+ pinctrl-single,pins = <
+ /* (Y2) MCU_SPI0_D1 */
+ AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0)
+ >;
+ };
+
+ d12_gpio: d12-gpio-pins {
+ pinctrl-single,pins = <
+ /* (Y2) WKUP_GPIO0_50 */
+ AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7)
+ >;
+ };
+
+ d12_gpio_pullup: d12-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (Y2) WKUP_GPIO0_50 */
+ AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7)
+ >;
+ };
+
+ d12_gpio_pulldown: d12-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (Y2) WKUP_GPIO0_50 */
+ AM65X_WKUP_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d13_spi0_clk: d13-spi0-clk-pins {
+ pinctrl-single,pins = <
+ /* (Y1) MCU_SPI0_CLK */
+ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
+ >;
+ };
+
+ d13_gpio: d13-gpio-pins {
+ pinctrl-single,pins = <
+ /* (Y1) WKUP_GPIO0_48 */
+ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7)
+ >;
+ };
+
+ d13_gpio_pullup: d13-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (Y1) WKUP_GPIO0_48 */
+ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7)
+ >;
+ };
+
+ d13_gpio_pulldown: d13-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (Y1) WKUP_GPIO0_48 */
+ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ a0_gpio: a0-gpio-pins {
+ pinctrl-single,pins = <
+ /* (L6) WKUP_GPIO0_45 */
+ AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7)
+ >;
+ };
+
+ a0_gpio_pullup: a0-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (L6) WKUP_GPIO0_45 */
+ AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7)
+ >;
+ };
+
+ a0_gpio_pulldown: a0-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (L6) WKUP_GPIO0_45 */
+ AM65X_WKUP_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ a1_gpio: a1-gpio-pins {
+ pinctrl-single,pins = <
+ /* (M6) WKUP_GPIO0_44 */
+ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7)
+ >;
+ };
+
+ a1_gpio_pullup: a1-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (M6) WKUP_GPIO0_44 */
+ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7)
+ >;
+ };
+
+ a1_gpio_pulldown: a1-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (M6) WKUP_GPIO0_44 */
+ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ a2_gpio: a2-gpio-pins {
+ pinctrl-single,pins = <
+ /* (L5) WKUP_GPIO0_43 */
+ AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
+ >;
+ };
+
+ a2_gpio_pullup: a2-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (L5) WKUP_GPIO0_43 */
+ AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
+ >;
+ };
+
+ a2_gpio_pulldown: a2-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (L5) WKUP_GPIO0_43 */
+ AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ a3_gpio: a3-gpio-pins {
+ pinctrl-single,pins = <
+ /* (M5) WKUP_GPIO0_39 */
+ AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
+ >;
+ };
+
+ a3_gpio_pullup: a3-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (M5) WKUP_GPIO0_39 */
+ AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
+ >;
+ };
+
+ a3_gpio_pulldown: a3-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (M5) WKUP_GPIO0_39 */
+ AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ a4_gpio: a4-gpio-pins {
+ pinctrl-single,pins = <
+ /* (L2) WKUP_GPIO0_42 */
+ AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7)
+ >;
+ };
+
+ a4_gpio_pullup: a4-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (L2) WKUP_GPIO0_42 */
+ AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7)
+ >;
+ };
+
+ a4_gpio_pulldown: a4-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (L2) WKUP_GPIO0_42 */
+ AM65X_WKUP_IOPAD(0x0078, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ a5_gpio: a5-gpio-pins {
+ pinctrl-single,pins = <
+ /* (N5) WKUP_GPIO0_35 */
+ AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7)
+ >;
+ };
+
+ a5_gpio_pullup: a5-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (N5) WKUP_GPIO0_35 */
+ AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ a5_gpio_pulldown: a5-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (N5) WKUP_GPIO0_35 */
+ AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ pinctrl-single,pins = <
+ /* (AC7) WKUP_I2C0_SCL */
+ AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0)
+ /* (AD6) WKUP_I2C0_SDA */
+ AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0)
+ >;
+ };
+
+ arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins {
+ pinctrl-single,pins = <
+ /* (R2) WKUP_GPIO0_21 */
+ AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)
+ >;
+ };
+
+ arduino_io_oe_pins_default: arduino-io-oe-default-pins {
+ pinctrl-single,pins = <
+ /* (N4) WKUP_GPIO0_34 */
+ AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)
+ /* (M2) WKUP_GPIO0_36 */
+ AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7)
+ /* (M3) WKUP_GPIO0_37 */
+ AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7)
+ /* (M4) WKUP_GPIO0_38 */
+ AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7)
+ /* (M1) WKUP_GPIO0_41 */
+ AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7)
+ >;
+ };
+};
+
+&main_pmx0 {
+ pinctrl-names =
+ "default",
+ "d4-ehrpwm0-a", "d4-gpio", "d4-gpio-pullup", "d4-gpio-pulldown",
+ "d5-ehrpwm1-a", "d5-gpio", "d5-gpio-pullup", "d5-gpio-pulldown",
+ "d6-ehrpwm2-a", "d6-gpio", "d6-gpio-pullup", "d6-gpio-pulldown",
+ "d7-ehrpwm3-a", "d7-gpio", "d7-gpio-pullup", "d7-gpio-pulldown",
+ "d8-ehrpwm4-a", "d8-gpio", "d8-gpio-pullup", "d8-gpio-pulldown",
+ "d9-ehrpwm5-a", "d9-gpio", "d9-gpio-pullup", "d9-gpio-pulldown";
+
+ pinctrl-0 = <&d4_ehrpwm0_a>;
+ pinctrl-1 = <&d4_ehrpwm0_a>;
+ pinctrl-2 = <&d4_gpio>;
+ pinctrl-3 = <&d4_gpio_pullup>;
+ pinctrl-4 = <&d4_gpio_pulldown>;
+
+ pinctrl-5 = <&d5_ehrpwm1_a>;
+ pinctrl-6 = <&d5_gpio>;
+ pinctrl-7 = <&d5_gpio_pullup>;
+ pinctrl-8 = <&d5_gpio_pulldown>;
+
+ pinctrl-9 = <&d6_ehrpwm2_a>;
+ pinctrl-10 = <&d6_gpio>;
+ pinctrl-11 = <&d6_gpio_pullup>;
+ pinctrl-12 = <&d6_gpio_pulldown>;
+
+ pinctrl-13 = <&d7_ehrpwm3_a>;
+ pinctrl-14 = <&d7_gpio>;
+ pinctrl-15 = <&d7_gpio_pullup>;
+ pinctrl-16 = <&d7_gpio_pulldown>;
+
+ pinctrl-17 = <&d8_ehrpwm4_a>;
+ pinctrl-18 = <&d8_gpio>;
+ pinctrl-19 = <&d8_gpio_pullup>;
+ pinctrl-20 = <&d8_gpio_pulldown>;
+
+ pinctrl-21 = <&d9_ehrpwm5_a>;
+ pinctrl-22 = <&d9_gpio>;
+ pinctrl-23 = <&d9_gpio_pullup>;
+ pinctrl-24 = <&d9_gpio_pulldown>;
+
+ d4_ehrpwm0_a: d4-ehrpwm0-a-pins {
+ pinctrl-single,pins = <
+ /* (AG18) EHRPWM0_A */
+ AM65X_IOPAD(0x0084, PIN_OUTPUT, 5)
+ >;
+ };
+
+ d4_gpio: d4-gpio-pins {
+ pinctrl-single,pins = <
+ /* (AG18) GPIO0_33 */
+ AM65X_IOPAD(0x0084, PIN_INPUT, 7)
+ >;
+ };
+
+ d4_gpio_pullup: d4-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (AG18) GPIO0_33 */
+ AM65X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d4_gpio_pulldown: d4-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (AG18) GPIO0_33 */
+ AM65X_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d5_ehrpwm1_a: d5-ehrpwm1-a-pins {
+ pinctrl-single,pins = <
+ /* (AF17) EHRPWM1_A */
+ AM65X_IOPAD(0x008C, PIN_OUTPUT, 5)
+ >;
+ };
+
+ d5_gpio: d5-gpio-pins {
+ pinctrl-single,pins = <
+ /* (AF17) GPIO0_35 */
+ AM65X_IOPAD(0x008C, PIN_INPUT, 7)
+ >;
+ };
+
+ d5_gpio_pullup: d5-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (AF17) GPIO0_35 */
+ AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d5_gpio_pulldown: d5-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (AF17) GPIO0_35 */
+ AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d6_ehrpwm2_a: d6-ehrpwm2-a-pins {
+ pinctrl-single,pins = <
+ /* (AH16) EHRPWM2_A */
+ AM65X_IOPAD(0x0098, PIN_OUTPUT, 5)
+ >;
+ };
+
+ d6_gpio: d6-gpio-pins {
+ pinctrl-single,pins = <
+ /* (AH16) GPIO0_38 */
+ AM65X_IOPAD(0x0098, PIN_INPUT, 7)
+ >;
+ };
+
+ d6_gpio_pullup: d6-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (AH16) GPIO0_38 */
+ AM65X_IOPAD(0x0098, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d6_gpio_pulldown: d6-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (AH16) GPIO0_38 */
+ AM65X_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d7_ehrpwm3_a: d7-ehrpwm3-a-pins {
+ pinctrl-single,pins = <
+ /* (AH15) EHRPWM3_A */
+ AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5)
+ >;
+ };
+
+ d7_gpio: d7-gpio-pins {
+ pinctrl-single,pins = <
+ /* (AH15) GPIO0_43 */
+ AM65X_IOPAD(0x00AC, PIN_INPUT, 7)
+ >;
+ };
+
+ d7_gpio_pullup: d7-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (AH15) GPIO0_43 */
+ AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d7_gpio_pulldown: d7-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (AH15) GPIO0_43 */
+ AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d8_ehrpwm4_a: d8-ehrpwm4-a-pins {
+ pinctrl-single,pins = <
+ /* (AG15) EHRPWM4_A */
+ AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5)
+ >;
+ };
+
+ d8_gpio: d8-gpio-pins {
+ pinctrl-single,pins = <
+ /* (AG15) GPIO0_48 */
+ AM65X_IOPAD(0x00C0, PIN_INPUT, 7)
+ >;
+ };
+
+ d8_gpio_pullup: d8-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (AG15) GPIO0_48 */
+ AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d8_gpio_pulldown: d8-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (AG15) GPIO0_48 */
+ AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d9_ehrpwm5_a: d9-ehrpwm5-a-pins {
+ pinctrl-single,pins = <
+ /* (AD15) EHRPWM5_A */
+ AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5)
+ >;
+ };
+
+ d9_gpio: d9-gpio-pins {
+ pinctrl-single,pins = <
+ /* (AD15) GPIO0_51 */
+ AM65X_IOPAD(0x00CC, PIN_INPUT, 7)
+ >;
+ };
+
+ d9_gpio_pullup: d9-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (AD15) GPIO0_51 */
+ AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d9_gpio_pulldown: d9-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (AD15) GPIO0_51 */
+ AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+};
+
+&main_gpio0 {
+ gpio-line-names =
+ "main_gpio0-base", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "IO4", "", "IO5", "", "", "IO6", "",
+ "", "", "", "IO7", "", "", "", "", "IO8", "",
+ "", "IO9";
+};
+
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 =
+ <&arduino_i2c_aio_switch_pins_default>,
+ <&arduino_io_oe_pins_default>,
+ <&push_button_pins_default>,
+ <&db9_com_mode_pins_default>;
+ gpio-line-names =
+ /* 0..9 */
+ "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
+ "UART0-enable", "UART0-terminate", "", "WIFI-disable",
+ /* 10..19 */
+ "", "", "", "", "", "", "", "", "", "",
+ /* 20..29 */
+ "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0",
+ /* 30..39 */
+ "IO1", "IO2", "", "IO3", "IO17-direction", "A5",
+ "IO16-direction", "IO15-direction", "IO14-direction", "A3",
+ /* 40..49 */
+ "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13",
+ "IO11",
+ /* 50..51 */
+ "IO12", "IO10";
+};
+
+&wkup_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&mcu_i2c0 {
+ /* D4200 */
+ pcal9535_1: gpio@20 {
+ compatible = "nxp,pcal9535";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names =
+ "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull",
+ "A5-pull", "", "",
+ "IO14-enable", "IO15-enable", "IO16-enable",
+ "IO17-enable", "IO18-enable", "IO19-enable";
+ };
+
+ /* D4201 */
+ pcal9535_2: gpio@21 {
+ compatible = "nxp,pcal9535";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names =
+ "IO0-direction", "IO1-direction", "IO2-direction",
+ "IO3-direction", "IO4-direction", "IO5-direction",
+ "IO6-direction", "IO7-direction",
+ "IO8-direction", "IO9-direction", "IO10-direction",
+ "IO11-direction", "IO12-direction", "IO13-direction",
+ "IO19-direction";
+ };
+
+ /* D4202 */
+ pcal9535_3: gpio@25 {
+ compatible = "nxp,pcal9535";
+ reg = <0x25>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names =
+ "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull",
+ "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull",
+ "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull",
+ "IO12-pull", "IO13-pull";
+ };
+};
+
+&mcu_uart0 {
+ status = "okay";
+};
+
+&tscadc1 {
+ status = "okay";
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5>;
+ };
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Siemens AG, 2021-2023
*
* Common bits of the IOT2050 Basic and Advanced variants, PG1
*/
-&dss {
- assigned-clocks = <&k3_clks 67 2>;
- assigned-clock-parents = <&k3_clks 67 5>;
-};
+#include "k3-am65-iot2050-dp.dtsi"
&serdes0 {
status = "disabled";
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) Siemens AG, 2021
+ * Copyright (c) Siemens AG, 2021-2023
*
* Authors:
* Chao Zeng <chao.zeng@siemens.com>
* Common bits of the IOT2050 Basic and Advanced variants, PG2
*/
+&mcu_r5fss0 {
+ /* lock-step mode not supported on PG2 boards */
+ ti,cluster-mode = <0>;
+};
+
&main_pmx0 {
cp2102n_reset_pin_default: cp2102n-reset-default-pins {
pinctrl-single,pins = <
/* Workaround needed to get DP clock of 154Mhz */
assigned-clocks = <&k3_clks 67 0>;
};
-
-&serdes0 {
- assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
- assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
-};
-
-&dwc3_0 {
- assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
- <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
- phys = <&serdes0 PHY_TYPE_USB3 0>;
- phy-names = "usb3-phy";
-};
-
-&usb0 {
- maximum-speed = "super-speed";
- snps,dis-u1-entry-quirk;
- snps,dis-u2-entry-quirk;
-};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) Siemens AG, 2018-2021
+ * Copyright (c) Siemens AG, 2018-2024
*
* Authors:
* Le Jin <le.jin@siemens.com>
* Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2
*/
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/net/ti-dp83867.h>
alignment = <0x1000>;
no-map;
};
+
+ /* To reserve the power-on(PON) reason for watchdog reset */
+ wdt_reset_memory_region: wdt-memory@a2200000 {
+ reg = <0x00 0xa2200000 0x00 0x1000>;
+ no-map;
+ };
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default>;
- status-led-red {
+ led-0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ label = "status-led-red";
gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
- status-led-green {
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ label = "status-led-green";
gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>;
};
- user-led1-red {
+ led-2 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_INDICATOR;
+ label = "user-led1-red";
gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>;
};
- user-led1-green {
+ led-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ label = "user-led1-green";
gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>;
};
- user-led2-red {
+ led-4 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_INDICATOR;
+ label = "user-led2-red";
gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>;
};
- user-led2-green {
+ led-5 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_INDICATOR;
+ label = "user-led2-green";
gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>;
};
};
};
&wkup_pmx0 {
- pinctrl-names =
- "default",
- "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown",
- "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown",
- "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown",
- "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown",
- "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown",
- "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown",
- "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown",
- "d13-spi0-clk", "d13-gpio", "d13-gpio-pullup", "d13-gpio-pulldown",
- "a0-gpio", "a0-gpio-pullup", "a0-gpio-pulldown",
- "a1-gpio", "a1-gpio-pullup", "a1-gpio-pulldown",
- "a2-gpio", "a2-gpio-pullup", "a2-gpio-pulldown",
- "a3-gpio", "a3-gpio-pullup", "a3-gpio-pulldown",
- "a4-gpio", "a4-gpio-pullup", "a4-gpio-pulldown",
- "a5-gpio", "a5-gpio-pullup", "a5-gpio-pulldown";
-
- pinctrl-0 = <&d0_uart0_rxd>;
- pinctrl-1 = <&d0_uart0_rxd>;
- pinctrl-2 = <&d0_gpio>;
- pinctrl-3 = <&d0_gpio_pullup>;
- pinctrl-4 = <&d0_gpio_pulldown>;
- pinctrl-5 = <&d1_uart0_txd>;
- pinctrl-6 = <&d1_gpio>;
- pinctrl-7 = <&d1_gpio_pullup>;
- pinctrl-8 = <&d1_gpio_pulldown>;
- pinctrl-9 = <&d2_uart0_ctsn>;
- pinctrl-10 = <&d2_gpio>;
- pinctrl-11 = <&d2_gpio_pullup>;
- pinctrl-12 = <&d2_gpio_pulldown>;
- pinctrl-13 = <&d3_uart0_rtsn>;
- pinctrl-14 = <&d3_gpio>;
- pinctrl-15 = <&d3_gpio_pullup>;
- pinctrl-16 = <&d3_gpio_pulldown>;
- pinctrl-17 = <&d10_spi0_cs0>;
- pinctrl-18 = <&d10_gpio>;
- pinctrl-19 = <&d10_gpio_pullup>;
- pinctrl-20 = <&d10_gpio_pulldown>;
- pinctrl-21 = <&d11_spi0_d0>;
- pinctrl-22 = <&d11_gpio>;
- pinctrl-23 = <&d11_gpio_pullup>;
- pinctrl-24 = <&d11_gpio_pulldown>;
- pinctrl-25 = <&d12_spi0_d1>;
- pinctrl-26 = <&d12_gpio>;
- pinctrl-27 = <&d12_gpio_pullup>;
- pinctrl-28 = <&d12_gpio_pulldown>;
- pinctrl-29 = <&d13_spi0_clk>;
- pinctrl-30 = <&d13_gpio>;
- pinctrl-31 = <&d13_gpio_pullup>;
- pinctrl-32 = <&d13_gpio_pulldown>;
- pinctrl-33 = <&a0_gpio>;
- pinctrl-34 = <&a0_gpio_pullup>;
- pinctrl-35 = <&a0_gpio_pulldown>;
- pinctrl-36 = <&a1_gpio>;
- pinctrl-37 = <&a1_gpio_pullup>;
- pinctrl-38 = <&a1_gpio_pulldown>;
- pinctrl-39 = <&a2_gpio>;
- pinctrl-40 = <&a2_gpio_pullup>;
- pinctrl-41 = <&a2_gpio_pulldown>;
- pinctrl-42 = <&a3_gpio>;
- pinctrl-43 = <&a3_gpio_pullup>;
- pinctrl-44 = <&a3_gpio_pulldown>;
- pinctrl-45 = <&a4_gpio>;
- pinctrl-46 = <&a4_gpio_pullup>;
- pinctrl-47 = <&a4_gpio_pulldown>;
- pinctrl-48 = <&a5_gpio>;
- pinctrl-49 = <&a5_gpio_pullup>;
- pinctrl-50 = <&a5_gpio_pulldown>;
-
- d0_uart0_rxd: d0-uart0-rxd-pins {
- pinctrl-single,pins = <
- /* (P4) MCU_UART0_RXD */
- AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
- >;
- };
-
- d0_gpio: d0-gpio-pins {
- pinctrl-single,pins = <
- /* (P4) WKUP_GPIO0_29 */
- AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7)
- >;
- };
-
- d0_gpio_pullup: d0-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (P4) WKUP_GPIO0_29 */
- AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLUP, 7)
- >;
- };
-
- d0_gpio_pulldown: d0-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (P4) WKUP_GPIO0_29 */
- AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- d1_uart0_txd: d1-uart0-txd-pins {
- pinctrl-single,pins = <
- /* (P5) MCU_UART0_TXD */
- AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
- >;
- };
-
- d1_gpio: d1-gpio-pins {
- pinctrl-single,pins = <
- /* (P5) WKUP_GPIO0_30 */
- AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7)
- >;
- };
-
- d1_gpio_pullup: d1-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (P5) WKUP_GPIO0_30 */
- AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7)
- >;
- };
-
- d1_gpio_pulldown: d1-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (P5) WKUP_GPIO0_30 */
- AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- d2_uart0_ctsn: d2-uart0-ctsn-pins {
- pinctrl-single,pins = <
- /* (P1) MCU_UART0_CTSn */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4)
- >;
- };
-
- d2_gpio: d2-gpio-pins {
- pinctrl-single,pins = <
- /* (P5) WKUP_GPIO0_31 */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
- >;
- };
-
- d2_gpio_pullup: d2-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (P5) WKUP_GPIO0_31 */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
- >;
- };
-
- d2_gpio_pulldown: d2-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (P5) WKUP_GPIO0_31 */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- d3_uart0_rtsn: d3-uart0-rtsn-pins {
- pinctrl-single,pins = <
- /* (N3) MCU_UART0_RTSn */
- AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4)
- >;
- };
-
- d3_gpio: d3-gpio-pins {
- pinctrl-single,pins = <
- /* (N3) WKUP_GPIO0_33 */
- AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7)
- >;
- };
-
- d3_gpio_pullup: d3-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (N3) WKUP_GPIO0_33 */
- AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7)
- >;
- };
-
- d3_gpio_pulldown: d3-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (N3) WKUP_GPIO0_33 */
- AM65X_WKUP_IOPAD(0x0054, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- d10_spi0_cs0: d10-spi0-cs0-pins {
- pinctrl-single,pins = <
- /* (Y4) MCU_SPI0_CS0 */
- AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)
- >;
- };
-
- d10_gpio: d10-gpio-pins {
- pinctrl-single,pins = <
- /* (Y4) WKUP_GPIO0_51 */
- AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7)
- >;
- };
-
- d10_gpio_pullup: d10-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (Y4) WKUP_GPIO0_51 */
- AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7)
- >;
- };
-
- d10_gpio_pulldown: d10-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (Y4) WKUP_GPIO0_51 */
- AM65X_WKUP_IOPAD(0x009c, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- d11_spi0_d0: d11-spi0-d0-pins {
- pinctrl-single,pins = <
- /* (Y3) MCU_SPI0_D0 */
- AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0)
- >;
- };
-
- d11_gpio: d11-gpio-pins {
- pinctrl-single,pins = <
- /* (Y3) WKUP_GPIO0_49 */
- AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7)
- >;
- };
-
- d11_gpio_pullup: d11-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (Y3) WKUP_GPIO0_49 */
- AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7)
- >;
- };
-
- d11_gpio_pulldown: d11-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (Y3) WKUP_GPIO0_49 */
- AM65X_WKUP_IOPAD(0x0094, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- d12_spi0_d1: d12-spi0-d1-pins {
- pinctrl-single,pins = <
- /* (Y2) MCU_SPI0_D1 */
- AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0)
- >;
- };
-
- d12_gpio: d12-gpio-pins {
- pinctrl-single,pins = <
- /* (Y2) WKUP_GPIO0_50 */
- AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7)
- >;
- };
-
- d12_gpio_pullup: d12-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (Y2) WKUP_GPIO0_50 */
- AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7)
- >;
- };
-
- d12_gpio_pulldown: d12-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (Y2) WKUP_GPIO0_50 */
- AM65X_WKUP_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- d13_spi0_clk: d13-spi0-clk-pins {
- pinctrl-single,pins = <
- /* (Y1) MCU_SPI0_CLK */
- AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
- >;
- };
-
- d13_gpio: d13-gpio-pins {
- pinctrl-single,pins = <
- /* (Y1) WKUP_GPIO0_48 */
- AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7)
- >;
- };
-
- d13_gpio_pullup: d13-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (Y1) WKUP_GPIO0_48 */
- AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7)
- >;
- };
-
- d13_gpio_pulldown: d13-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (Y1) WKUP_GPIO0_48 */
- AM65X_WKUP_IOPAD(0x0090, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- a0_gpio: a0-gpio-pins {
- pinctrl-single,pins = <
- /* (L6) WKUP_GPIO0_45 */
- AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7)
- >;
- };
-
- a0_gpio_pullup: a0-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (L6) WKUP_GPIO0_45 */
- AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7)
- >;
- };
-
- a0_gpio_pulldown: a0-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (L6) WKUP_GPIO0_45 */
- AM65X_WKUP_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- a1_gpio: a1-gpio-pins {
- pinctrl-single,pins = <
- /* (M6) WKUP_GPIO0_44 */
- AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7)
- >;
- };
-
- a1_gpio_pullup: a1-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (M6) WKUP_GPIO0_44 */
- AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7)
- >;
- };
-
- a1_gpio_pulldown: a1-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (M6) WKUP_GPIO0_44 */
- AM65X_WKUP_IOPAD(0x0080, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- a2_gpio: a2-gpio-pins {
- pinctrl-single,pins = <
- /* (L5) WKUP_GPIO0_43 */
- AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
- >;
- };
-
- a2_gpio_pullup: a2-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (L5) WKUP_GPIO0_43 */
- AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
- >;
- };
-
- a2_gpio_pulldown: a2-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (L5) WKUP_GPIO0_43 */
- AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- a3_gpio: a3-gpio-pins {
- pinctrl-single,pins = <
- /* (M5) WKUP_GPIO0_39 */
- AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
- >;
- };
-
- a3_gpio_pullup: a3-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (M5) WKUP_GPIO0_39 */
- AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
- >;
- };
-
- a3_gpio_pulldown: a3-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (M5) WKUP_GPIO0_39 */
- AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- a4_gpio: a4-gpio-pins {
- pinctrl-single,pins = <
- /* (L2) WKUP_GPIO0_42 */
- AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7)
- >;
- };
-
- a4_gpio_pullup: a4-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (L2) WKUP_GPIO0_42 */
- AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7)
- >;
- };
-
- a4_gpio_pulldown: a4-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (L2) WKUP_GPIO0_42 */
- AM65X_WKUP_IOPAD(0x0078, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- a5_gpio: a5-gpio-pins {
- pinctrl-single,pins = <
- /* (N5) WKUP_GPIO0_35 */
- AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7)
- >;
- };
-
- a5_gpio_pullup: a5-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (N5) WKUP_GPIO0_35 */
- AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7)
- >;
- };
-
- a5_gpio_pulldown: a5-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (N5) WKUP_GPIO0_35 */
- AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- wkup_i2c0_pins_default: wkup-i2c0-default-pins {
- pinctrl-single,pins = <
- /* (AC7) WKUP_I2C0_SCL */
- AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0)
- /* (AD6) WKUP_I2C0_SDA */
- AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0)
- >;
- };
-
mcu_i2c0_pins_default: mcu-i2c0-default-pins {
pinctrl-single,pins = <
/* (AD8) MCU_I2C0_SCL */
>;
};
- arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins {
- pinctrl-single,pins = <
- /* (R2) WKUP_GPIO0_21 */
- AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)
- >;
- };
-
push_button_pins_default: push-button-default-pins {
pinctrl-single,pins = <
/* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
>;
};
-
- arduino_io_oe_pins_default: arduino-io-oe-default-pins {
- pinctrl-single,pins = <
- /* (N4) WKUP_GPIO0_34 */
- AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)
- /* (M2) WKUP_GPIO0_36 */
- AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7)
- /* (M3) WKUP_GPIO0_37 */
- AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7)
- /* (M4) WKUP_GPIO0_38 */
- AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7)
- /* (M1) WKUP_GPIO0_41 */
- AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7)
- >;
- };
-
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
/* (V1) MCU_OSPI0_CLK */
};
&main_pmx0 {
- pinctrl-names =
- "default",
- "d4-ehrpwm0-a", "d4-gpio", "d4-gpio-pullup", "d4-gpio-pulldown",
- "d5-ehrpwm1-a", "d5-gpio", "d5-gpio-pullup", "d5-gpio-pulldown",
- "d6-ehrpwm2-a", "d6-gpio", "d6-gpio-pullup", "d6-gpio-pulldown",
- "d7-ehrpwm3-a", "d7-gpio", "d7-gpio-pullup", "d7-gpio-pulldown",
- "d8-ehrpwm4-a", "d8-gpio", "d8-gpio-pullup", "d8-gpio-pulldown",
- "d9-ehrpwm5-a", "d9-gpio", "d9-gpio-pullup", "d9-gpio-pulldown";
-
- pinctrl-0 = <&d4_ehrpwm0_a>;
- pinctrl-1 = <&d4_ehrpwm0_a>;
- pinctrl-2 = <&d4_gpio>;
- pinctrl-3 = <&d4_gpio_pullup>;
- pinctrl-4 = <&d4_gpio_pulldown>;
-
- pinctrl-5 = <&d5_ehrpwm1_a>;
- pinctrl-6 = <&d5_gpio>;
- pinctrl-7 = <&d5_gpio_pullup>;
- pinctrl-8 = <&d5_gpio_pulldown>;
-
- pinctrl-9 = <&d6_ehrpwm2_a>;
- pinctrl-10 = <&d6_gpio>;
- pinctrl-11 = <&d6_gpio_pullup>;
- pinctrl-12 = <&d6_gpio_pulldown>;
-
- pinctrl-13 = <&d7_ehrpwm3_a>;
- pinctrl-14 = <&d7_gpio>;
- pinctrl-15 = <&d7_gpio_pullup>;
- pinctrl-16 = <&d7_gpio_pulldown>;
-
- pinctrl-17 = <&d8_ehrpwm4_a>;
- pinctrl-18 = <&d8_gpio>;
- pinctrl-19 = <&d8_gpio_pullup>;
- pinctrl-20 = <&d8_gpio_pulldown>;
-
- pinctrl-21 = <&d9_ehrpwm5_a>;
- pinctrl-22 = <&d9_gpio>;
- pinctrl-23 = <&d9_gpio_pullup>;
- pinctrl-24 = <&d9_gpio_pulldown>;
-
- d4_ehrpwm0_a: d4-ehrpwm0-a-pins {
- pinctrl-single,pins = <
- /* (AG18) EHRPWM0_A */
- AM65X_IOPAD(0x0084, PIN_OUTPUT, 5)
- >;
- };
-
- d4_gpio: d4-gpio-pins {
- pinctrl-single,pins = <
- /* (AG18) GPIO0_33 */
- AM65X_IOPAD(0x0084, PIN_INPUT, 7)
- >;
- };
-
- d4_gpio_pullup: d4-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (AG18) GPIO0_33 */
- AM65X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7)
- >;
- };
-
- d4_gpio_pulldown: d4-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (AG18) GPIO0_33 */
- AM65X_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- d5_ehrpwm1_a: d5-ehrpwm1-a-pins {
- pinctrl-single,pins = <
- /* (AF17) EHRPWM1_A */
- AM65X_IOPAD(0x008C, PIN_OUTPUT, 5)
- >;
- };
-
- d5_gpio: d5-gpio-pins {
- pinctrl-single,pins = <
- /* (AF17) GPIO0_35 */
- AM65X_IOPAD(0x008C, PIN_INPUT, 7)
- >;
- };
-
- d5_gpio_pullup: d5-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (AF17) GPIO0_35 */
- AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7)
- >;
- };
-
- d5_gpio_pulldown: d5-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (AF17) GPIO0_35 */
- AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- d6_ehrpwm2_a: d6-ehrpwm2-a-pins {
- pinctrl-single,pins = <
- /* (AH16) EHRPWM2_A */
- AM65X_IOPAD(0x0098, PIN_OUTPUT, 5)
- >;
- };
-
- d6_gpio: d6-gpio-pins {
- pinctrl-single,pins = <
- /* (AH16) GPIO0_38 */
- AM65X_IOPAD(0x0098, PIN_INPUT, 7)
- >;
- };
-
- d6_gpio_pullup: d6-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (AH16) GPIO0_38 */
- AM65X_IOPAD(0x0098, PIN_INPUT_PULLUP, 7)
- >;
- };
-
- d6_gpio_pulldown: d6-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (AH16) GPIO0_38 */
- AM65X_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- d7_ehrpwm3_a: d7-ehrpwm3-a-pins {
- pinctrl-single,pins = <
- /* (AH15) EHRPWM3_A */
- AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5)
- >;
- };
-
- d7_gpio: d7-gpio-pins {
- pinctrl-single,pins = <
- /* (AH15) GPIO0_43 */
- AM65X_IOPAD(0x00AC, PIN_INPUT, 7)
- >;
- };
-
- d7_gpio_pullup: d7-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (AH15) GPIO0_43 */
- AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7)
- >;
- };
-
- d7_gpio_pulldown: d7-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (AH15) GPIO0_43 */
- AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- d8_ehrpwm4_a: d8-ehrpwm4-a-pins {
- pinctrl-single,pins = <
- /* (AG15) EHRPWM4_A */
- AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5)
- >;
- };
-
- d8_gpio: d8-gpio-pins {
- pinctrl-single,pins = <
- /* (AG15) GPIO0_48 */
- AM65X_IOPAD(0x00C0, PIN_INPUT, 7)
- >;
- };
-
- d8_gpio_pullup: d8-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (AG15) GPIO0_48 */
- AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7)
- >;
- };
-
- d8_gpio_pulldown: d8-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (AG15) GPIO0_48 */
- AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
- d9_ehrpwm5_a: d9-ehrpwm5-a-pins {
- pinctrl-single,pins = <
- /* (AD15) EHRPWM5_A */
- AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5)
- >;
- };
-
- d9_gpio: d9-gpio-pins {
- pinctrl-single,pins = <
- /* (AD15) GPIO0_51 */
- AM65X_IOPAD(0x00CC, PIN_INPUT, 7)
- >;
- };
-
- d9_gpio_pullup: d9-gpio-pullup-pins {
- pinctrl-single,pins = <
- /* (AD15) GPIO0_51 */
- AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7)
- >;
- };
-
- d9_gpio_pulldown: d9-gpio-pulldown-pins {
- pinctrl-single,pins = <
- /* (AD15) GPIO0_51 */
- AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7)
- >;
- };
-
main_pcie_enable_pins_default: main-pcie-enable-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
>;
};
- dss_vout1_pins_default: dss-vout1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
- AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */
- AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */
- AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */
- AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */
- AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */
- AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */
- AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */
- AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */
- AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */
- AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */
- AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */
- AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */
- AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */
- AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */
- AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */
- AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */
- AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */
- AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */
- AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */
- AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */
- AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */
- AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */
- AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */
- AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */
- AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */
- AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */
- AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */
- >;
- };
-
- dp_pins_default: dp-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */
- >;
- };
-
main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */
pinctrl-0 = <&main_uart1_pins_default>;
};
-&mcu_uart0 {
- status = "okay";
-};
-
-&main_gpio0 {
- gpio-line-names =
- "main_gpio0-base", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "",
- "", "", "", "IO4", "", "IO5", "", "", "IO6", "",
- "", "", "", "IO7", "", "", "", "", "IO8", "",
- "", "IO9";
-};
-
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&main_pcie_enable_pins_default>;
};
-&wkup_gpio0 {
- pinctrl-names = "default";
- pinctrl-0 =
- <&arduino_i2c_aio_switch_pins_default>,
- <&arduino_io_oe_pins_default>,
- <&push_button_pins_default>,
- <&db9_com_mode_pins_default>;
- gpio-line-names =
- /* 0..9 */
- "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
- "UART0-enable", "UART0-terminate", "", "WIFI-disable",
- /* 10..19 */
- "", "", "", "", "", "", "", "", "", "",
- /* 20..29 */
- "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0",
- /* 30..39 */
- "IO1", "IO2", "", "IO3", "IO17-direction", "A5",
- "IO16-direction", "IO15-direction", "IO14-direction", "A3",
- /* 40..49 */
- "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13",
- "IO11",
- /* 50..51 */
- "IO12", "IO10";
-};
-
-&wkup_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
-};
-
&mcu_i2c0 {
status = "okay";
pinctrl-names = "default";
ti,vsel1-state-high;
ti,enable-vout-discharge;
};
-
- /* D4200 */
- pcal9535_1: gpio@20 {
- compatible = "nxp,pcal9535";
- reg = <0x20>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-line-names =
- "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull",
- "A5-pull", "", "",
- "IO14-enable", "IO15-enable", "IO16-enable",
- "IO17-enable", "IO18-enable", "IO19-enable";
- };
-
- /* D4201 */
- pcal9535_2: gpio@21 {
- compatible = "nxp,pcal9535";
- reg = <0x21>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-line-names =
- "IO0-direction", "IO1-direction", "IO2-direction",
- "IO3-direction", "IO4-direction", "IO5-direction",
- "IO6-direction", "IO7-direction",
- "IO8-direction", "IO9-direction", "IO10-direction",
- "IO11-direction", "IO12-direction", "IO13-direction",
- "IO19-direction";
- };
-
- /* D4202 */
- pcal9535_3: gpio@25 {
- compatible = "nxp,pcal9535";
- reg = <0x25>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-line-names =
- "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull",
- "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull",
- "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull",
- "IO12-pull", "IO13-pull";
- };
};
&main_i2c0 {
#address-cells = <1>;
#size-cells = <0>;
-
- edp-bridge@f {
- compatible = "toshiba,tc358767";
- reg = <0x0f>;
- pinctrl-names = "default";
- pinctrl-0 = <&dp_pins_default>;
- reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
-
- clock-names = "ref";
- clocks = <&dp_refclk>;
-
- toshiba,hpd-pin = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
-
- bridge_in: endpoint {
- remote-endpoint = <&dpi_out>;
- };
- };
- };
- };
};
&mcu_cpsw {
ti,pindir-d0-out-d1-in;
};
-&tscadc1 {
- status = "okay";
- adc {
- ti,adc-channels = <0 1 2 3 4 5>;
- };
-};
-
&ospi0 {
status = "okay";
pinctrl-names = "default";
};
};
-&dss {
- pinctrl-names = "default";
- pinctrl-0 = <&dss_vout1_pins_default>;
-
- assigned-clocks = <&k3_clks 67 2>;
- assigned-clock-parents = <&k3_clks 67 5>;
-};
-
-&dss_ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@1 {
- reg = <1>;
-
- dpi_out: endpoint {
- remote-endpoint = <&bridge_in>;
- };
- };
-};
-
&pcie1_rc {
status = "okay";
pinctrl-names = "default";
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
};
&mcu_r5fss0_core1 {
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
- mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+};
+
+&mcu_rti1 {
+ memory-region = <&wdt_reset_memory_region>;
};
&icssg0_mdio {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Siemens AG, 2024
+ *
+ * Authors:
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits for IOT2050 variants with Display Port
+ */
+
+&main_pmx0 {
+ dss_vout1_pins_default: dss-vout1-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
+ AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */
+ AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */
+ AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */
+ AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */
+ AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */
+ AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */
+ AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */
+ AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */
+ AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */
+ AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */
+ AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */
+ AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */
+ AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */
+ AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */
+ AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */
+ AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */
+ AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */
+ AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */
+ AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */
+ AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */
+ AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */
+ AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */
+ AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */
+ AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */
+ AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */
+ AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */
+ AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */
+ >;
+ };
+
+ dp_pins_default: dp-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */
+ >;
+ };
+};
+
+&main_i2c3 {
+ edp-bridge@f {
+ compatible = "toshiba,tc358767";
+ reg = <0x0f>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp_pins_default>;
+ reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
+
+ clock-names = "ref";
+ clocks = <&dp_refclk>;
+
+ toshiba,hpd-pin = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ bridge_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+ };
+ };
+};
+
+&dss {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_vout1_pins_default>;
+
+ assigned-clocks = <&k3_clks 67 2>;
+ assigned-clock-parents = <&k3_clks 67 5>;
+};
+
+&dss_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@1 {
+ reg = <1>;
+
+ dpi_out: endpoint {
+ remote-endpoint = <&bridge_in>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Siemens AG, 2024
+ *
+ * Authors:
+ * Jan Kiszka <jan.kiszka@siemens.com>
+ *
+ * Common bits for IOT2050 variants with USB3 support
+ */
+
+&serdes0 {
+ assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
+ assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
+};
+
+&dwc3_0 {
+ assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+ <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
+ phys = <&serdes0 PHY_TYPE_USB3 0>;
+ phy-names = "usb3-phy";
+};
+
+&usb0 {
+ maximum-speed = "super-speed";
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM6 SoC Family Main Domain peripherals
*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/phy/phy-am654-serdes.h>
status = "disabled";
};
- pcie0_ep: pcie-ep@5500000 {
- compatible = "ti,am654-pcie-ep";
- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
- reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
- ti,syscon-pcie-mode = <&scm_conf 0x4060>;
- num-ib-windows = <16>;
- num-ob-windows = <16>;
- max-link-speed = <2>;
- dma-coherent;
- interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
pcie1_rc: pcie@5600000 {
compatible = "ti,am654-pcie-rc";
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
status = "disabled";
};
- pcie1_ep: pcie-ep@5600000 {
- compatible = "ti,am654-pcie-ep";
- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
- reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
- ti,syscon-pcie-mode = <&scm_conf 0x4070>;
- num-ib-windows = <16>;
- num-ob-windows = <16>;
- max-link-speed = <2>;
- dma-coherent;
- interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
mcasp0: mcasp@2b00000 {
compatible = "ti,am33xx-mcasp-audio";
reg = <0x0 0x02b00000 0x0 0x2000>,
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
- <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
+ <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */
+ <0x0 0x04a01000 0x0 0x1000>; /* common1 */
reg-names = "common", "vidl1", "vid",
- "ovr1", "ovr2", "vp1", "vp2";
+ "ovr1", "ovr2", "vp1", "vp2", "common1";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
};
};
+ gpu: gpu@7000000 {
+ compatible = "ti,am6548-gpu", "img,powervr-sgx544";
+ reg = <0x0 0x7000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+ };
+
ehrpwm0: pwm@3000000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM6 SoC Family MCU Domain peripherals
*
- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_wakeup {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM6 SoC Family
*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM65 SoC family in Dual core configuration
*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am65.dtsi"
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Siemens AG, 2018-2021
*
#include "k3-am652.dtsi"
#include "k3-am65-iot2050-common.dtsi"
+#include "k3-am65-iot2050-arduino-connector.dtsi"
/ {
memory@80000000 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
-
-&mcu_r5fss0 {
- /* lock-step mode not supported on Basic boards */
- ti,cluster-mode = <0>;
-};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Siemens AG, 2018-2021
*
#include "k3-am6528-iot2050-basic-common.dtsi"
#include "k3-am65-iot2050-common-pg2.dtsi"
+#include "k3-am65-iot2050-dp.dtsi"
+#include "k3-am65-iot2050-usb3.dtsi"
/ {
compatible = "siemens,iot2050-basic-pg2", "ti,am654";
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Siemens AG, 2018-2021
*
compatible = "siemens,iot2050-basic", "ti,am654";
model = "SIMATIC IOT2050 Basic";
};
+
+&mcu_r5fss0 {
+ /* lock-step mode not supported on this board */
+ ti,cluster-mode = <0>;
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* OLDI-LCD1EVM Rocktech integrated panel and touch DT overlay for AM654-EVM.
* Panel Link: https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT
* AM654 LCD EVM: https://www.ti.com/tool/TMDSLCD1EVM
*
- * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
};
&mcu_r5fss0_core1 {
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
- mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
};
&ospi0 {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT overlay for IDK application board on AM654 EVM
*
- * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT overlay for IDK application board on AM654 EVM
*
- * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
#include <dt-bindings/thermal/thermal.h>
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT overlay for SERDES personality card: 2lane PCIe + USB2.0 Host on AM654 EVM
+ *
+ * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-am654-serdes.h>
+#include "k3-pinctrl.h"
+
+&serdes0 {
+ assigned-clocks = <&k3_clks 153 4>,
+ <&serdes0 AM654_SERDES_CMU_REFCLK>,
+ <&serdes0 AM654_SERDES_RO_REFCLK>;
+ assigned-clock-parents = <&k3_clks 153 8>,
+ <&k3_clks 153 4>,
+ <&k3_clks 153 4>;
+ status = "okay";
+};
+
+&serdes1 {
+ assigned-clocks = <&serdes1 AM654_SERDES_CMU_REFCLK>;
+ assigned-clock-parents = <&serdes0 AM654_SERDES_RO_REFCLK>;
+ status = "okay";
+};
+
+&pcie0_rc {
+ num-lanes = <2>;
+ phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>;
+ phy-names = "pcie-phy0", "pcie-phy1";
+ reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&main_pmx0 {
+ usb0_pins_default: usb0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
+ >;
+ };
+};
+
+&dwc3_0 {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins_default>;
+ dr_mode = "host";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM
+ *
+ * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-am654-serdes.h>
+
+#include "k3-pinctrl.h"
+
+&serdes1 {
+ status = "okay";
+};
+
+&pcie1_rc {
+ num-lanes = <1>;
+ phys = <&serdes1 PHY_TYPE_PCIE 0>;
+ phy-names = "pcie-phy0";
+ reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&main_pmx0 {
+ usb0_pins_default: usb0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
+ >;
+ };
+};
+
+&serdes0 {
+ status = "okay";
+ assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
+ assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+ <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
+ phys = <&serdes0 PHY_TYPE_USB3 0>;
+ phy-names = "usb3-phy";
+};
+
+&usb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins_default>;
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+};
+
+&usb0_phy {
+ status = "okay";
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM6 SoC family in Quad core configuration
*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am65.dtsi"
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Siemens AG, 2018-2021
*
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Siemens AG, 2018-2023
*
#include "k3-am6548-iot2050-advanced-common.dtsi"
#include "k3-am65-iot2050-common-pg2.dtsi"
+#include "k3-am65-iot2050-arduino-connector.dtsi"
+#include "k3-am65-iot2050-dp.dtsi"
/ {
compatible = "siemens,iot2050-advanced-m2", "ti,am654";
model = "SIMATIC IOT2050 Advanced M2";
};
-&mcu_r5fss0 {
- /* lock-step mode not supported on this board */
- ti,cluster-mode = <0>;
-};
-
&main_pmx0 {
main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins {
pinctrl-single,pins = <
&pcie1_rc {
status = "disabled";
};
-
-&dwc3_0 {
- assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
- <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
- /delete-property/ phys;
- /delete-property/ phy-names;
-};
-
-&usb0 {
- maximum-speed = "high-speed";
- /delete-property/ snps,dis-u1-entry-quirk;
- /delete-property/ snps,dis-u2-entry-quirk;
-};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) Siemens AG, 2018-2021
+ * Copyright (c) Siemens AG, 2018-2023
*
* Authors:
* Le Jin <le.jin@siemens.com>
#include "k3-am6548-iot2050-advanced-common.dtsi"
#include "k3-am65-iot2050-common-pg2.dtsi"
+#include "k3-am65-iot2050-arduino-connector.dtsi"
+#include "k3-am65-iot2050-dp.dtsi"
+#include "k3-am65-iot2050-usb3.dtsi"
/ {
compatible = "siemens,iot2050-advanced-pg2", "ti,am654";
model = "SIMATIC IOT2050 Advanced PG2";
};
-
-&mcu_r5fss0 {
- /* lock-step mode not supported on this board */
- ti,cluster-mode = <0>;
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Siemens AG, 2023
+ *
+ * Authors:
+ * Baocheng Su <baocheng.su@siemens.com>
+ * Chao Zeng <chao.zeng@siemens.com>
+ * Huaqian Li <huaqian.li@siemens.com>
+ *
+ * AM6548-based (quad-core) IOT2050 SM variant, Product Generation 2
+ * 4 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
+ *
+ * Product homepage:
+ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
+ */
+
+/dts-v1/;
+
+#include "k3-am6548-iot2050-advanced-common.dtsi"
+#include "k3-am65-iot2050-common-pg2.dtsi"
+
+/ {
+ compatible = "siemens,iot2050-advanced-sm", "ti,am654";
+ model = "SIMATIC IOT2050 Advanced SM";
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
+ };
+
+ aliases {
+ spi1 = &main_spi0;
+ };
+
+ leds {
+ pinctrl-0 = <&leds_pins_default>, <&user1_led_pins>;
+
+ led-2 {
+ gpios = <&wkup_gpio0 52 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-3 {
+ gpios = <&wkup_gpio0 53 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&main_pmx0 {
+ main_pcie_enable_pins_default: main-pcie-enable-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01d8, PIN_OUTPUT, 7) /* (AH12) GPIO1_22 */
+ >;
+ };
+
+ main_spi0_pins: main-spi0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
+ AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
+ AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
+ AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
+ >;
+ };
+};
+
+&main_pmx1 {
+ asic_spi_mux_ctrl_pin: asic-spi-mux-ctrl-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0010, PIN_OUTPUT, 7) /* (D21) GPIO1_86 */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ user1_led_pins: user1-led-default-pins {
+ pinctrl-single,pins = <
+ /* (AB1) WKUP_UART0_RXD:WKUP_GPIO0_52, as USER 1 led red */
+ AM65X_WKUP_IOPAD(0x00a0, PIN_OUTPUT, 7)
+ /* (AB5) WKUP_UART0_TXD:WKUP_GPIO0_53, as USER 1 led green */
+ AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 7)
+ >;
+ };
+
+ soc_asic_pins: soc-asic-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7) /* (P4) WKUP_GPIO0_29 */
+ AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) /* (P5) WKUP_GPIO0_30 */
+ AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7) /* (P1) WKUP_GPIO0_31 */
+ >;
+ };
+};
+
+&main_gpio0 {
+ gpio-line-names = "main_gpio0-base";
+};
+
+&main_gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 =
+ <&cp2102n_reset_pin_default>,
+ <&main_pcie_enable_pins_default>,
+ <&asic_spi_mux_ctrl_pin>;
+ gpio-line-names =
+ /* 0..9 */
+ "", "", "", "", "", "", "", "", "", "",
+ /* 10..19 */
+ "", "", "", "", "", "", "", "", "", "",
+ /* 20..29 */
+ "", "", "", "", "CP2102N-RESET", "", "", "", "", "",
+ /* 30..39 */
+ "", "", "", "", "", "", "", "", "", "",
+ /* 40..49 */
+ "", "", "", "", "", "", "", "", "", "",
+ /* 50..59 */
+ "", "", "", "", "", "", "", "", "", "",
+ /* 60..69 */
+ "", "", "", "", "", "", "", "", "", "",
+ /* 70..79 */
+ "", "", "", "", "", "", "", "", "", "",
+ /* 80..86 */
+ "", "", "", "", "", "", "ASIC-spi-mux-ctrl";
+};
+
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 =
+ <&push_button_pins_default>,
+ <&db9_com_mode_pins_default>,
+ <&soc_asic_pins>;
+ gpio-line-names =
+ /* 0..9 */
+ "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
+ "UART0-enable", "UART0-terminate", "", "WIFI-disable",
+ /* 10..19 */
+ "", "", "", "", "", "", "", "", "", "",
+ /* 20..29 */
+ "", "", "", "", "", "USER-button", "", "", "","ASIC-gpio-0",
+ /* 30..31 */
+ "ASIC-gpio-1", "ASIC-gpio-2";
+};
+
+&main_spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_spi0_pins>;
+
+ #address-cells = <1>;
+ #size-cells= <0>;
+};
+
+&mcu_spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_spi0_pins_default>;
+};
+
+&main_i2c3 {
+ accelerometer: lsm6dso@6a {
+ compatible = "st,lsm6dso";
+ reg = <0x6a>;
+ };
+};
+
+&dss {
+ status = "disabled";
+};
+
+&serdes0 {
+ assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
+ assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
+};
+
+&serdes1 {
+ status = "disabled";
+};
+
+&pcie0_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&minipcie_pins_default>;
+
+ num-lanes = <1>;
+ phys = <&serdes0 PHY_TYPE_PCIE 1>;
+ phy-names = "pcie-phy0";
+ reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pcie1_rc {
+ status = "disabled";
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Siemens AG, 2018-2021
*
#include "k3-am6548-iot2050-advanced-common.dtsi"
#include "k3-am65-iot2050-common-pg1.dtsi"
+#include "k3-am65-iot2050-arduino-connector.dtsi"
/ {
compatible = "siemens,iot2050-advanced", "ti,am654";
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*
* Base Board: https://www.ti.com/lit/zip/SPRR463
*/
};
};
};
+
+ csi_mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&exp3 1 GPIO_ACTIVE_HIGH>;
+ idle-state = <0>;
+ };
};
&main_pmx0 {
>;
};
+ main_i2c1_pins_default: main-i2c1-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */
+ J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */
+ >;
+ };
+
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
};
};
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ status = "okay";
+
+ exp3: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn",
+ "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1",
+ "CSI1_B_GPIO1";
+ };
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ cam0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ cam1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ };
+};
+
&main_i2c4 {
status = "okay";
pinctrl-names = "default";
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
};
&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c71_0 {
status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
&c71_1 {
status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
+ mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
memory-region = <&c71_1_dma_memory_region>,
<&c71_1_memory_region>;
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*
* Design Files: https://www.ti.com/lit/zip/SPRR466
* TRM: https://www.ti.com/lit/zip/spruj52
memory@80000000 {
device_type = "memory";
+ bootph-all;
/* 32G RAM */
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x08 0x80000000 0x07 0x80000000>;
};
};
};
+
+ csi_mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
+ idle-state = <0>;
+ };
+
+ transceiver1: can-phy0 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ transceiver2: can-phy1 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ transceiver3: can-phy2 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ transceiver4: can-phy3 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
};
&main_pmx0 {
>;
};
+ main_i2c1_pins_default: main-i2c1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */
+ J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */
+ >;
+ };
+
main_mmc1_pins_default: main-mmc1-default-pins {
bootph-all;
pinctrl-single,pins = <
J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */
>;
};
+
+ main_mcan6_pins_default: main-mcan6-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x098, PIN_INPUT, 0) /* (AH36) MCAN6_RX */
+ J784S4_IOPAD(0x094, PIN_OUTPUT, 0) /* (AG35) MCAN6_TX */
+ >;
+ };
+
+ main_mcan7_pins_default: main-mcan7-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */
+ J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */
+ >;
+ };
+
+};
+
+&wkup_pmx0 {
+ bootph-all;
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */
+ J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */
+ J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */
+ J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */
+ J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */
+ J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */
+ J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */
+ J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */
+ J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */
+ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */
+ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
+ >;
+ };
};
&wkup_pmx2 {
J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */
>;
};
+
+ mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */
+ J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */
+ >;
+ };
+
+ mcu_mcan1_pins_default: mcu-mcan1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */
+ J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0)/* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */
+ >;
+ };
+
};
&wkup_pmx3 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&wkup_gpio0>;
- interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <83 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
ti,primary-pmic;
};
};
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ exp2: gpio@21 {
+ compatible = "ti,tca6408";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz",
+ "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1";
+ };
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ cam0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ cam1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ };
+};
+
&main_sdhci0 {
bootph-all;
/* eMMC */
};
&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&main_r5fss2_core0 {
- mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core0>;
+ mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
memory-region = <&main_r5fss2_core0_dma_memory_region>,
<&main_r5fss2_core0_memory_region>;
};
&main_r5fss2_core1 {
- mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core1>;
+ mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
memory-region = <&main_r5fss2_core1_dma_memory_region>,
<&main_r5fss2_core1_memory_region>;
};
&c71_0 {
status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
&c71_1 {
status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
+ mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
memory-region = <&c71_1_dma_memory_region>,
<&c71_1_memory_region>;
};
&c71_2 {
status = "okay";
- mboxes = <&mailbox0_cluster5>, <&mbox_c71_2>;
+ mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
memory-region = <&c71_2_dma_memory_region>,
<&c71_2_memory_region>;
};
&c71_3 {
status = "okay";
- mboxes = <&mailbox0_cluster5>, <&mbox_c71_3>;
+ mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
memory-region = <&c71_3_dma_memory_region>,
<&c71_3_memory_region>;
};
pinctrl-names = "default";
pinctrl-0 = <&dss_vout0_pins_default>;
assigned-clocks = <&k3_clks 218 2>,
- <&k3_clks 218 5>,
- <&k3_clks 218 14>,
- <&k3_clks 218 18>;
+ <&k3_clks 218 5>;
assigned-clock-parents = <&k3_clks 218 3>,
- <&k3_clks 218 7>,
- <&k3_clks 218 16>,
- <&k3_clks 218 22>;
+ <&k3_clks 218 7>;
};
&serdes_wiz4 {
};
};
};
+
+&mcu_mcan0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_pins_default>;
+ phys = <&transceiver1>;
+};
+
+&mcu_mcan1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan1_pins_default>;
+ phys = <&transceiver2>;
+};
+
+&main_mcan6 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan6_pins_default>;
+ phys = <&transceiver3>;
+};
+
+&main_mcan7 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan7_pins_default>;
+ phys = <&transceiver4>;
+};
+
+&ospi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+
+ partitions {
+ bootph-all;
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x100000>;
+ };
+
+ partition@100000 {
+ label = "ospi.tispl";
+ reg = <0x100000 0x200000>;
+ };
+
+ partition@300000 {
+ label = "ospi.u-boot";
+ reg = <0x300000 0x400000>;
+ };
+
+ partition@700000 {
+ label = "ospi.env";
+ reg = <0x700000 0x40000>;
+ };
+
+ partition@740000 {
+ label = "ospi.env.backup";
+ reg = <0x740000 0x40000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fc0000 {
+ bootph-pre-ram;
+ label = "ospi.phypattern";
+ reg = <0x3fc0000 0x40000>;
+ };
+ };
+ };
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
states = <1800000 0x0>,
<3300000 0x1>;
};
+
+ transceiver1: can-phy1 {
+ compatible = "ti,tcan1043";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
+ standby-gpios = <&wkup_gpio0 58 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver2: can-phy2 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
+ standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver3: can-phy3 {
+ compatible = "ti,tcan1043";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
+ mux-states = <&mux0 1>;
+ };
};
&wkup_pmx0 {
+};
+
+&wkup_pmx2 {
mcu_uart0_pins_default: mcu-uart0-default-pins {
pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
- J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
- J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */
- J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */
+ J721E_WKUP_IOPAD(0x90, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */
+ J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */
+ J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
+ J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
>;
};
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
- J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
+ J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
+ J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
>;
};
-};
-&wkup_pmx2 {
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>;
};
+
+ mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x54, PIN_INPUT, 0) /* (A17) MCU_MCAN0_RX */
+ J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (A16) MCU_MCAN0_TX */
+ >;
+ };
+
+ mcu_mcan1_pins_default: mcu-mcan1-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x6c, PIN_INPUT, 0) /* (B16) WKUP_GPIO0_5.MCU_MCAN1_RX */
+ J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (D13) WKUP_GPIO0_4.MCU_MCAN1_TX */
+ >;
+ };
+
+ mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x58, PIN_INPUT, 7) /* (B18) WKUP_GPIO0_0 */
+ J721E_WKUP_IOPAD(0x40, PIN_INPUT, 7) /* (B17) MCU_SPI0_D1 */
+ >;
+ };
+
+ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x60, PIN_INPUT, 7) /* (D14) WKUP_GPIO0_2 */
+ >;
+ };
};
&main_pmx0 {
J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
>;
};
+
+ main_mcan3_pins_default: main-mcan3-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x3c, PIN_INPUT, 0) /* (W16) MCAN3_RX */
+ J721E_IOPAD(0x38, PIN_OUTPUT, 0) /* (Y21) MCAN3_TX */
+ >;
+ };
};
&main_pmx1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
- clock-frequency = <96000000>;
};
&main_uart0 {
};
&pcie1_rc {
+ status = "okay";
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
};
-&pcie1_ep {
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <2>;
- status = "disabled";
+&mcu_mcan0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_pins_default>;
+ phys = <&transceiver1>;
+};
+
+&mcu_mcan1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan1_pins_default>;
+ phys = <&transceiver2>;
+};
+
+&main_mcan3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan3_pins_default>;
+ phys = <&transceiver3>;
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
* J7200 board.
*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J7200 SoC Family Main Domain peripherals
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
ranges = <0x00 0x00 0x00100000 0x1c000>;
serdes_ln_ctrl: mux-controller@4080 {
- compatible = "mmio-mux";
+ compatible = "reg-mux";
+ reg = <0x4080 0x20>;
#mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
- <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
+ mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
+ <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
};
cpsw0_phy_gmii_sel: phy@4044 {
};
usb_serdes_mux: mux-controller@4000 {
- compatible = "mmio-mux";
+ compatible = "reg-mux";
+ reg = <0x4000 0x4>;
#mux-control-cells = <1>;
- mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
+ mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
};
/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
main_timerio_input: pinctrl@104200 {
- compatible = "pinctrl-single";
+ compatible = "ti,j7200-padconf", "pinctrl-single";
reg = <0x0 0x104200 0x0 0x50>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
main_timerio_output: pinctrl@104280 {
- compatible = "pinctrl-single";
+ compatible = "ti,j7200-padconf", "pinctrl-single";
reg = <0x0 0x104280 0x0 0x20>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
};
main_pmx0: pinctrl@11c000 {
- compatible = "pinctrl-single";
+ compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x11c000 0x00 0x10c>;
#pinctrl-cells = <1>;
};
main_pmx1: pinctrl@11c11c {
- compatible = "pinctrl-single";
+ compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x11c11c 0x00 0xc>;
#pinctrl-cells = <1>;
ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
<0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
- };
-
- pcie1_ep: pcie-ep@2910000 {
- compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
- reg = <0x00 0x02910000 0x00 0x1000>,
- <0x00 0x02917000 0x00 0x400>,
- <0x00 0x0d800000 0x00 0x00800000>,
- <0x00 0x18000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
- max-link-speed = <3>;
- num-lanes = <4>;
- power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 240 6>;
- clock-names = "fck";
- max-functions = /bits/ 8 <6>;
- max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
- dma-coherent;
+ status = "disabled";
};
usbss0: cdns-usb@4104000 {
status = "disabled";
};
+ main_mcan0: can@2701000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02701000 0x00 0x200>,
+ <0x00 0x02708000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 156 0>, <&k3_clks 156 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan1: can@2711000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02711000 0x00 0x200>,
+ <0x00 0x02718000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 158 0>, <&k3_clks 158 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan2: can@2721000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02721000 0x00 0x200>,
+ <0x00 0x02728000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 160 0>, <&k3_clks 160 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan3: can@2731000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02731000 0x00 0x200>,
+ <0x00 0x02738000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 161 0>, <&k3_clks 161 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan4: can@2741000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02741000 0x00 0x200>,
+ <0x00 0x02748000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 162 0>, <&k3_clks 162 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan5: can@2751000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02751000 0x00 0x200>,
+ <0x00 0x02758000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 163 0>, <&k3_clks 163 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan6: can@2761000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02761000 0x00 0x200>,
+ <0x00 0x02768000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 164 0>, <&k3_clks 164 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan7: can@2771000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02771000 0x00 0x200>,
+ <0x00 0x02778000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 165 0>, <&k3_clks 165 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan8: can@2781000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02781000 0x00 0x200>,
+ <0x00 0x02788000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 166 0>, <&k3_clks 166 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan9: can@2791000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02791000 0x00 0x200>,
+ <0x00 0x02798000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 167 0>, <&k3_clks 167 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan10: can@27a1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027a1000 0x00 0x200>,
+ <0x00 0x027a8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 168 0>, <&k3_clks 168 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan11: can@27b1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027b1000 0x00 0x200>,
+ <0x00 0x027b8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 169 0>, <&k3_clks 169 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan12: can@27c1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027c1000 0x00 0x200>,
+ <0x00 0x027c8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 170 0>, <&k3_clks 170 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan13: can@27d1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027d1000 0x00 0x200>,
+ <0x00 0x027d8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 171 0>, <&k3_clks 171 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan14: can@2681000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02681000 0x00 0x200>,
+ <0x00 0x02688000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 150 0>, <&k3_clks 150 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan15: can@2691000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02691000 0x00 0x200>,
+ <0x00 0x02698000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 151 0>, <&k3_clks 151 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan16: can@26a1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x026a1000 0x00 0x200>,
+ <0x00 0x026a8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 152 0>, <&k3_clks 152 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan17: can@26b1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x026b1000 0x00 0x200>,
+ <0x00 0x026b8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 153 0>, <&k3_clks 153 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
main_spi0: spi@2100000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02100000 0x00 0x400>;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu_wakeup {
/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
mcu_timerio_input: pinctrl@40f04200 {
- compatible = "pinctrl-single";
+ compatible = "ti,j7200-padconf", "pinctrl-single";
reg = <0x0 0x40f04200 0x0 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
mcu_timerio_output: pinctrl@40f04280 {
- compatible = "pinctrl-single";
+ compatible = "ti,j7200-padconf", "pinctrl-single";
reg = <0x0 0x40f04280 0x0 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
};
wkup_pmx0: pinctrl@4301c000 {
- compatible = "pinctrl-single";
+ compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c000 0x00 0x34>;
#pinctrl-cells = <1>;
};
wkup_pmx1: pinctrl@4301c038 {
- compatible = "pinctrl-single";
+ compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c038 0x00 0x8>;
#pinctrl-cells = <1>;
};
wkup_pmx2: pinctrl@4301c068 {
- compatible = "pinctrl-single";
+ compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c068 0x00 0xec>;
#pinctrl-cells = <1>;
};
wkup_pmx3: pinctrl@4301c174 {
- compatible = "pinctrl-single";
+ compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c174 0x00 0x20>;
#pinctrl-cells = <1>;
status = "disabled";
};
- fss: syscon@47000000 {
- compatible = "syscon", "simple-mfd";
+ fss: bus@47000000 {
+ compatible = "simple-bus";
reg = <0x00 0x47000000 0x00 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
- hbmc_mux: hbmc-mux {
- compatible = "mmio-mux";
+ hbmc_mux: mux-controller@47000004 {
+ compatible = "reg-mux";
+ reg = <0x00 0x47000004 0x00 0x4>;
#mux-control-cells = <1>;
- mux-reg-masks = <0x4 0x2>; /* HBMC select */
+ mux-reg-masks = <0x0 0x2>; /* HBMC select */
};
hbmc: hyperbus@47034000 {
ti,esm-pins = <95>;
bootph-pre-ram;
};
+
+ mcu_mcan0: can@40528000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x40528000 0x00 0x200>,
+ <0x00 0x40500000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 172 0>, <&k3_clks 172 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcu_mcan1: can@40568000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x40568000 0x00 0x200>,
+ <0x00 0x40540000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 173 0>, <&k3_clks 173 2>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+
#include "k3-j7200.dtsi"
/ {
no-map;
};
};
+
+ mux0: mux-controller {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ mux1: mux-controller {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver0: can-phy0 {
+ /* standby pin has been grounded by default */
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
};
&wkup_pmx0 {
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
>;
};
+
+ main_mcan0_pins_default: main-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x24, PIN_INPUT, 0) /* (V20) MCAN0_RX */
+ J721E_IOPAD(0x20, PIN_OUTPUT, 0) /* (V18) MCAN0_TX */
+ >;
+ };
};
&hbmc {
};
&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
};
};
};
+
+&main_mcan0 {
+ status = "okay";
+ pinctrl-0 = <&main_mcan0_pins_default>;
+ pinctrl-names = "default";
+ phys = <&transceiver0>;
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
#include <dt-bindings/thermal/thermal.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J7200 SoC Family
*
- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/irq.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* https://beagleboard.org/ai-64
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
- * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
- * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Jason Kridner, BeagleBoard.org Foundation
+ * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation
*/
/dts-v1/;
};
&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c66_0 {
status = "okay";
- mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
+ mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
status = "okay";
- mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
+ mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/
*
* Product Link: https://www.ti.com/tool/J721EXCPXEVM
*/
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with
* J721E board.
*
* GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM
*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the
* J7 common processor board.
*
* J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
* J721E board.
*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J721E SoC Family Main Domain peripherals
*
- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-ti.h>
ranges = <0x0 0x0 0x00100000 0x1c000>;
serdes_ln_ctrl: mux-controller@4080 {
- compatible = "mmio-mux";
- reg = <0x00004080 0x50>;
+ compatible = "reg-mux";
+ reg = <0x4080 0x50>;
#mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
- <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
- <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
- <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
- <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
- /* SERDES4 lane0/1/2/3 select */
+ mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
+ <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
+ <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
+ <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */
+ <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
+ <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */
idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
};
usb_serdes_mux: mux-controller@4000 {
- compatible = "mmio-mux";
+ compatible = "reg-mux";
+ reg = <0x4000 0x20>;
#mux-control-cells = <1>;
- mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
- <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
+ mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */
+ <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */
};
ehrpwm_tbclk: clock-controller@4140 {
pinctrl-single,function-mask = <0x0000001f>;
};
+ ti_csi2rx0: ticsi2rx@4500000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ reg = <0x0 0x4500000 0x0 0x1000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dmas = <&main_udmap 0x4940>;
+ dma-names = "rx0";
+ power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ cdns_csi2rx0: csi-bridge@4504000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x0 0x4504000 0x0 0x1000>;
+ clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
+ <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi0_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi0_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi0_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi0_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ ti_csi2rx1: ticsi2rx@4510000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ reg = <0x0 0x4510000 0x0 0x1000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dmas = <&main_udmap 0x4960>;
+ dma-names = "rx0";
+ power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ cdns_csi2rx1: csi-bridge@4514000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x0 0x4514000 0x0 0x1000>;
+ clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
+ <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy1>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi1_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi1_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi1_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi1_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ dphy0: phy@4580000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x0 0x4580000 0x0 0x1100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ dphy1: phy@4590000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x0 0x4590000 0x0 0x1100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
serdes_wiz0: wiz@5000000 {
compatible = "ti,j721e-wiz-16g";
#address-cells = <1>;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
*
- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu_wakeup {
hbmc_mux: mux-controller@47000004 {
compatible = "reg-mux";
- reg = <0x00 0x47000004 0x00 0x2>;
+ reg = <0x00 0x47000004 0x00 0x4>;
#mux-control-cells = <1>;
- mux-reg-masks = <0x4 0x2>; /* HBMC select */
+ mux-reg-masks = <0x0 0x2>; /* HBMC select */
};
hbmc: hyperbus@47034000 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for dual RPi Camera V2.1 (Sony IMX219) interfaced with CSI2
+ * on J721E SK, AM68 SK or AM69-SK board.
+ * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "k3-pinctrl.h"
+
+&{/} {
+ clk_imx219_fixed: imx219-xclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+};
+
+&csi_mux {
+ idle-state = <1>;
+};
+
+/* CAM0 I2C */
+&cam0_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ imx219_0: imx219-0@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+
+ clocks = <&clk_imx219_fixed>;
+ clock-names = "xclk";
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2rx0_in_sensor>;
+ link-frequencies = /bits/ 64 <456000000>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+/* CAM1 I2C */
+&cam1_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ imx219_1: imx219-1@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+
+ clocks = <&clk_imx219_fixed>;
+ clock-names = "xclk";
+
+ port {
+ csi2_cam1: endpoint {
+ remote-endpoint = <&csi2rx1_in_sensor>;
+ link-frequencies = /bits/ 64 <456000000>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2rx0_in_sensor: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+
+ csi0_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi0_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi0_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi0_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&cdns_csi2rx1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2rx1_in_sensor: endpoint {
+ remote-endpoint = <&csi2_cam1>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+
+ csi1_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi1_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi1_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi1_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+};
+
+&dphy1 {
+ status = "okay";
+};
+
+&ti_csi2rx1 {
+ status = "okay";
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*
* J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
*/
};
};
};
+
+ csi_mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>;
+ idle-state = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_csi_mux_sel_pins_default>;
+ };
};
&main_pmx0 {
>;
};
+ main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */
+ >;
+ };
+
dp0_pins_default: dp0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&wkup_gpio0>;
- interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
ti,primary-pmic;
reg = <0x4c>;
system-power-controller;
interrupt-parent = <&wkup_gpio0>;
- interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
buck1234-supply = <&vsys_3v3>;
reg = <0x70>;
/* CSI0 I2C */
- i2c@0 {
+ cam0_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
/* CSI1 I2C */
- i2c@1 {
+ cam1_i2c: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c66_0 {
status = "okay";
- mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
+ mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
status = "okay";
- mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
+ mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/
*
* Product Link: https://www.ti.com/tool/J721EXSOMXEVM
*/
};
&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c66_0 {
status = "okay";
- mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
+ mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
status = "okay";
- mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
+ mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
#include <dt-bindings/thermal/thermal.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J721E SoC Family
*
- * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/irq.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*
* Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM
*/
>;
};
+ main_i2c5_pins_default: main-i2c5-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */
+ J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */
+ >;
+ };
+
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
&wkup_pmx2 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
- J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>;
};
};
+&main_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c5_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ exp5: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0",
+ "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO2",
+ "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2",
+ "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4";
+ };
+};
+
&main_sdhci0 {
/* eMMC */
status = "okay";
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board.
*
* GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM
*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the
* J7 common processor board.
*
* J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J721S2 SoC Family Main Domain peripherals
*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/phy/phy-cadence.h>
ranges = <0x00 0x00 0x00104000 0x18000>;
usb_serdes_mux: mux-controller@0 {
- compatible = "mmio-mux";
+ compatible = "reg-mux";
reg = <0x0 0x4>;
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
serdes_ln_ctrl: mux-controller@80 {
- compatible = "mmio-mux";
+ compatible = "reg-mux";
reg = <0x80 0x10>;
#mux-control-cells = <1>;
- mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
- <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+ mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
+ <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
};
ehrpwm_tbclk: clock-controller@140 {
status = "disabled";
};
+ vpu: video-codec@4210000 {
+ compatible = "ti,j721s2-wave521c", "cnm,wave521c";
+ reg = <0x00 0x4210000 0x00 0x10000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 179 2>;
+ power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+ };
+
main_sdhci0: mmc@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x00 0x04f80000 0x00 0x1000>,
ti,sci-dev-id = <225>;
ti,sci-rm-range-rchan = <0x21>;
ti,sci-rm-range-tchan = <0x22>;
- status = "disabled";
};
cpts@310d0000 {
};
};
+ ti_csi2rx0: ticsi2rx@4500000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ reg = <0x00 0x04500000 0x00 0x1000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dmas = <&main_bcdma_csi 0 0x4940 0>;
+ dma-names = "rx0";
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ cdns_csi2rx0: csi-bridge@4504000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x00 0x04504000 0x00 0x1000>;
+ clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>,
+ <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi0_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi0_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi0_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi0_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ ti_csi2rx1: ticsi2rx@4510000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ reg = <0x00 0x04510000 0x00 0x1000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dmas = <&main_bcdma_csi 0 0x4960 0>;
+ dma-names = "rx0";
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ cdns_csi2rx1: csi-bridge@4514000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x00 0x04514000 0x00 0x1000>;
+ clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>,
+ <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy1>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi1_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi1_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi1_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi1_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ dphy0: phy@4580000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x00 0x04580000 0x00 0x1100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ dphy1: phy@4590000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x00 0x04590000 0x00 0x1100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
serdes_wiz0: wiz@5060000 {
compatible = "ti,j721s2-wiz-10g";
#address-cells = <1>;
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals
*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu_wakeup {
compatible = "ti,j7200-vtm";
reg = <0x00 0x42040000 0x0 0x350>,
<0x00 0x42050000 0x0 0x350>;
- power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
+ power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* SoM: https://www.ti.com/lit/zip/sprr439
*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
};
&mcu_r5fss0_core0 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c71_0 {
status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
&c71_1 {
status = "okay";
- mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
+ mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
memory-region = <&c71_1_dma_memory_region>,
<&c71_1_memory_region>;
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
#include <dt-bindings/thermal/thermal.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J721S2 SoC Family
*
* TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28
*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*
*/
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the J722S EVM
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Schematics: https://www.ti.com/lit/zip/sprr495
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-j722s.dtsi"
+
+/ {
+ compatible = "ti,j722s-evm", "ti,j722s";
+ model = "Texas Instruments J722S EVM";
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial2 = &main_uart0;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
+ chosen {
+ stdout-path = &main_uart0;
+ };
+
+ memory@80000000 {
+ /* 8G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000001 0x80000000>;
+ device_type = "memory";
+ bootph-pre-ram;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_tfa_ddr: tfa@9e780000 {
+ reg = <0x00 0x9e780000 0x00 0x80000>;
+ no-map;
+ };
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ };
+
+ vmain_pd: regulator-0 {
+ /* TPS65988 PD CONTROLLER OUTPUT */
+ compatible = "regulator-fixed";
+ regulator-name = "vmain_pd";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ bootph-all;
+ };
+
+ vsys_5v0: regulator-vsys5v0 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vmain_pd>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: regulator-mmc1 {
+ /* TPS22918DBVR */
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&exp1 15 GPIO_ACTIVE_HIGH>;
+ bootph-all;
+ };
+
+ vdd_sd_dv: regulator-TLV71033 {
+ compatible = "regulator-gpio";
+ regulator-name = "tlv71033";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_pins_default>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_5v0>;
+ gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+
+ vsys_io_1v8: regulator-vsys-io-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_io_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_io_1v2: regulator-vsys-io-1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_io_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&main_pmx0 {
+
+ main_i2c0_pins_default: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */
+ J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */
+ >;
+ bootph-all;
+ };
+
+ main_uart0_pins_default: main-uart0-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */
+ J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */
+ >;
+ bootph-all;
+ };
+
+ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */
+ >;
+ bootph-all;
+ };
+
+ main_mmc1_pins_default: main-mmc1-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */
+ J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */
+ J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */
+ J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */
+ J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */
+ J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */
+ J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */
+ >;
+ bootph-all;
+ };
+
+ mdio_pins_default: mdio-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */
+ J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */
+ >;
+ };
+
+ ospi0_pins_default: ospi0-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */
+ J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */
+ J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */
+ J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */
+ J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */
+ J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */
+ J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (L21) OSPI0_D4 */
+ J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (M26) OSPI0_D5 */
+ J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (N27) OSPI0_D6 */
+ J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (M27) OSPI0_D7 */
+ J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (L22) OSPI0_DQS */
+ >;
+ bootph-all;
+ };
+
+ rgmii1_pins_default: rgmii1-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */
+ J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */
+ J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */
+ J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */
+ J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */
+ J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */
+ J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */
+ J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */
+ J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */
+ J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */
+ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
+ J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
+ >;
+ };
+};
+
+&cpsw3g {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins_default>;
+};
+
+&cpsw3g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins_default>;
+
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
+
+&main_gpio1 {
+ status = "okay";
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ status = "okay";
+ bootph-all;
+};
+
+&mcu_pmx0 {
+
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */
+ J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */
+ J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */
+ J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */
+ >;
+ bootph-all;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */
+ J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */
+ >;
+ bootph-all;
+ };
+};
+
+&wkup_uart0 {
+ /* WKUP UART0 is used by Device Manager firmware */
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "reserved";
+ bootph-all;
+};
+
+&wkup_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+ bootph-all;
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+ bootph-all;
+
+ exp1: gpio@23 {
+ compatible = "ti,tca6424";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL",
+ "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#",
+ "CSI_VIO_SEL", "USB2.0_MUX_SEL",
+ "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2",
+ "LMK1_OE1", "LMK1_OE0",
+ "LMK2_OE0", "LMK2_OE1",
+ "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn",
+ "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN",
+ "USER_LED2", "MCAN0_STB",
+ "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
+ "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
+ "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
+ };
+};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ospi0_pins_default>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ bootph-all;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x00 0x80000>;
+ };
+
+ partition@80000 {
+ label = "ospi.tispl";
+ reg = <0x80000 0x200000>;
+ };
+
+ partition@280000 {
+ label = "ospi.u-boot";
+ reg = <0x280000 0x400000>;
+ };
+
+ partition@680000 {
+ label = "ospi.env";
+ reg = <0x680000 0x40000>;
+ };
+
+ partition@6c0000 {
+ label = "ospi.env.backup";
+ reg = <0x6c0000 0x40000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fc0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fc0000 0x40000>;
+ };
+ };
+ };
+
+};
+
+&sdhci1 {
+ /* SD/MMC */
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ no-1-8-v;
+ status = "okay";
+ bootph-all;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree Source for J722S SoC Family
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-am62p5.dtsi"
+
+/ {
+ model = "Texas Instruments K3 J722S SoC";
+ compatible = "ti,j722s";
+
+ cbass_main: bus@f0000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
+ <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+ <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
+ <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
+ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
+ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */
+ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
+ <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */
+ <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */
+ <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */
+ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
+ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
+ <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */
+ <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */
+ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
+ <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
+ <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */
+ <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */
+ <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */
+ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
+ <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */
+ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
+ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
+ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
+ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
+ <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
+ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+ <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */
+ <0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */
+ <0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */
+ <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */
+ <0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */
+ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+ <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
+
+ /* MCU Domain Range */
+ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
+ <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>,
+ <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>,
+ <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>,
+ <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>,
+
+ /* Wakeup Domain Range */
+ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
+ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
+ <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
+ <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
+ };
+};
+
+/* Main domain overrides */
+
+&inta_main_dmss {
+ ti,interrupt-ranges = <7 71 21>;
+};
+
+&oc_sram {
+ reg = <0x00 0x70000000 0x00 0x40000>;
+ ranges = <0x00 0x00 0x70000000 0x40000>;
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*
* EVM Board Schematics: https://www.ti.com/lit/zip/sprr458
*/
memory@80000000 {
device_type = "memory";
+ bootph-all;
/* 32G RAM */
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x08 0x80000000 0x07 0x80000000>;
>;
};
+ main_i2c5_pins_default: main-i2c5-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */
+ J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */
+ >;
+ };
+
main_mmc1_pins_default: main-mmc1-default-pins {
bootph-all;
pinctrl-single,pins = <
wkup_uart0_pins_default: wkup-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */
- J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
>;
};
};
+&main_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c5_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ exp5: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0",
+ "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3",
+ "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2",
+ "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4";
+ };
+};
+
&main_sdhci0 {
bootph-all;
/* eMMC */
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J784S4 SoC Family Main Domain peripherals
*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/mux/mux.h>
compatible = "reg-mux";
reg = <0x00004080 0x30>;
#mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
- <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
- <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
- <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
- <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
- <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
+ mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
+ <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */
+ <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
+ <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */
+ <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
+ <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */
idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
<J784S4_SERDES0_LANE1_PCIE1_LANE1>,
<J784S4_SERDES0_LANE2_IP3_UNUSED>,
status = "disabled";
};
+ ti_csi2rx0: ticsi2rx@4500000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ reg = <0x00 0x04500000 0x00 0x00001000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dmas = <&main_bcdma_csi 0 0x4940 0>;
+ dma-names = "rx0";
+ power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ cdns_csi2rx0: csi-bridge@4504000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x00 0x04504000 0x00 0x00001000>;
+ clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>,
+ <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi0_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi0_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi0_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi0_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ ti_csi2rx1: ticsi2rx@4510000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ reg = <0x00 0x04510000 0x00 0x1000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dmas = <&main_bcdma_csi 0 0x4960 0>;
+ dma-names = "rx0";
+ power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ cdns_csi2rx1: csi-bridge@4514000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x00 0x04514000 0x00 0x00001000>;
+ clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>,
+ <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy1>;
+ phy-names = "dphy";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi1_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi1_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi1_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi1_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ ti_csi2rx2: ticsi2rx@4520000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ reg = <0x00 0x04520000 0x00 0x00001000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dmas = <&main_bcdma_csi 0 0x4980 0>;
+ dma-names = "rx0";
+ power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ cdns_csi2rx2: csi-bridge@4524000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x00 0x04524000 0x00 0x00001000>;
+ clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>,
+ <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy2>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi2_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi2_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi2_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi2_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi2_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ dphy0: phy@4580000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x00 0x04580000 0x00 0x00001100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ dphy1: phy@4590000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x00 0x04590000 0x00 0x00001100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ dphy2: phy@45a0000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x00 0x045a0000 0x00 0x00001100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ vpu0: video-codec@4210000 {
+ compatible = "ti,j721s2-wave521c", "cnm,wave521c";
+ reg = <0x00 0x4210000 0x00 0x10000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 241 2>;
+ power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ vpu1: video-codec@4220000 {
+ compatible = "ti,j721s2-wave521c", "cnm,wave521c";
+ reg = <0x00 0x4220000 0x00 0x10000>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 242 2>;
+ power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
+ };
+
main_sdhci0: mmc@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x00 0x04f80000 0x00 0x1000>,
ti,sci-dev-id = <281>;
ti,sci-rm-range-rchan = <0x21>;
ti,sci-rm-range-tchan = <0x22>;
- status = "disabled";
};
cpts@310d0000 {
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals
*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu_wakeup {
compatible = "ti,j7200-vtm";
reg = <0x00 0x42040000 0x00 0x350>,
<0x00 0x42050000 0x00 0x350>;
- power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
+ power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
#include <dt-bindings/thermal/thermal.h>
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J784S4 SoC Family
*
* TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52
*
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*
*/
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
+ <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
+ <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
<0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/*
* This header provides constants for pinctrl bindings for TI's K3 SoC
* family.
*
- * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef DTS_ARM64_TI_K3_PINCTRL_H
#define DTS_ARM64_TI_K3_PINCTRL_H
#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J722S_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J722S_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
#define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/*
* This header provides constants for SERDES MUX for TI SoCs
*
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef DTS_ARM64_TI_K3_SERDES_H
&uart0 {
clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
+ assigned-clocks = <&zynqmp_clk UART0_REF>;
};
&uart1 {
clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
+ assigned-clocks = <&zynqmp_clk UART1_REF>;
};
-&dwc3_0 {
+&usb0 {
clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+ assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
-&dwc3_1 {
+&dwc3_0 {
+ clocks = <&zynqmp_clk USB3_DUAL_REF>;
+};
+
+&usb1 {
clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+ assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+};
+
+&dwc3_1 {
+ clocks = <&zynqmp_clk USB3_DUAL_REF>;
};
&watchdog0 {
bus-width = <4>;
};
-&gem3 { /* required by spec */
+&gem3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
};
};
-&pinctrl0 { /* required by spec */
+&pinctrl0 {
status = "okay";
+ pinctrl_gpio0_default: gpio0-default {
+ conf {
+ groups = "gpio0_38_grp";
+ bias-pull-up;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_38_grp";
+ function = "gpio0";
+ };
+
+ conf-tx {
+ pins = "MIO38";
+ bias-disable;
+ output-enable;
+ };
+ };
+
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
conf-tx {
pins = "MIO36";
bias-disable;
+ output-enable;
};
mux {
};
};
- pinctrl_i2c1_gpio: i2c1-gpio {
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
+ output-enable;
low-power-disable;
};
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
+ output-enable;
low-power-enable;
};
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
mux-mdio {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
};
};
+&gpio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default>;
+};
+
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+ assigned-clock-rates = <250000000>, <20000000>;
};
&dwc3_0 {
bus-width = <4>;
};
-&gem3 { /* required by spec */
+&gem3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
};
};
-&pinctrl0 { /* required by spec */
+&pinctrl0 {
status = "okay";
+ pinctrl_gpio0_default: gpio0-default {
+ conf {
+ groups = "gpio0_38_grp";
+ bias-pull-up;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_38_grp";
+ function = "gpio0";
+ };
+
+ conf-tx {
+ pins = "MIO38";
+ bias-disable;
+ output-enable;
+ };
+ };
+
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
conf-tx {
pins = "MIO36";
bias-disable;
+ output-enable;
};
mux {
};
};
- pinctrl_i2c1_gpio: i2c1-gpio {
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
+ output-enable;
low-power-disable;
};
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
+ output-enable;
low-power-enable;
};
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
mux-mdio {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
};
};
+&gpio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default>;
+};
+
&uart1 {
status = "okay";
pinctrl-names = "default";
};
};
- pinctrl_i2c1_gpio: i2c1-gpio {
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_36_grp", "gpio0_37_grp";
function = "gpio0";
};
};
- pinctrl_i2c0_gpio: i2c0-gpio {
+ pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_6_grp", "gpio0_7_grp";
function = "gpio0";
};
};
- pinctrl_i2c0_gpio: i2c0-gpio {
+ pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_74_grp", "gpio0_75_grp";
function = "gpio0";
};
};
- pinctrl_i2c1_gpio: i2c1-gpio {
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_76_grp", "gpio0_77_grp";
function = "gpio0";
};
};
- pinctrl_i2c1_gpio: i2c1-gpio {
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_4_grp", "gpio0_5_grp";
function = "gpio0";
reg = <0x5d>;
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
- clock-frequency = <148500000>;
+ clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
};
};
- pinctrl_i2c0_gpio: i2c0-gpio {
+ pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_14_grp", "gpio0_15_grp";
function = "gpio0";
};
};
- pinctrl_i2c1_gpio: i2c1-gpio {
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
};
};
- pinctrl_i2c1_gpio: i2c1-gpio {
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
};
};
- pinctrl_i2c1_gpio: i2c1-gpio {
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
reg = <0x5d>;
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
- clock-frequency = <148500000>;
+ clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
};
};
- pinctrl_i2c0_gpio: i2c0-gpio {
+ pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_14_grp", "gpio0_15_grp";
function = "gpio0";
};
};
- pinctrl_i2c1_gpio: i2c1-gpio {
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
};
};
- pinctrl_i2c0_gpio: i2c0-gpio {
+ pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_14_grp", "gpio0_15_grp";
function = "gpio0";
};
};
- pinctrl_i2c1_gpio: i2c1-gpio {
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";
// SPDX-License-Identifier: GPL-2.0+
/*
- * dts file for Xilinx ZynqMP ZC1275
+ * dts file for Xilinx ZynqMP ZCU1275
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
#address-cells = <2>;
#size-cells = <2>;
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ bootscr-address = /bits/ 64 <0x20000000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
};
firmware {
+ optee: optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
#power-domain-cells = <1>;
method = "smc";
bootph-all;
- zynqmp_power: zynqmp-power {
+ zynqmp_power: power-management {
bootph-all;
compatible = "xlnx,zynqmp-power";
interrupt-parent = <&gic>;
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>;
power-domains = <&zynqmp_firmware PD_CAN_0>;
};
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>;
power-domains = <&zynqmp_firmware PD_CAN_1>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14e8>;
+ /* iommus = <&smmu 0x14e8>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14e9>;
+ /* iommus = <&smmu 0x14e9>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ea>;
+ /* iommus = <&smmu 0x14ea>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14eb>;
+ /* iommus = <&smmu 0x14eb>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ec>;
+ /* iommus = <&smmu 0x14ec>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ed>;
+ /* iommus = <&smmu 0x14ed>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ee>;
+ /* iommus = <&smmu 0x14ee>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ef>;
+ /* iommus = <&smmu 0x14ef>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x868>;
+ /* iommus = <&smmu 0x868>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x869>;
+ /* iommus = <&smmu 0x869>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86a>;
+ /* iommus = <&smmu 0x86a>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86b>;
+ /* iommus = <&smmu 0x86b>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86c>;
+ /* iommus = <&smmu 0x86c>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86d>;
+ /* iommus = <&smmu 0x86d>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86e>;
+ /* iommus = <&smmu 0x86e>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86f>;
+ /* iommus = <&smmu 0x86f>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- iommus = <&smmu 0x872>;
+ /* iommus = <&smmu 0x872>; */
power-domains = <&zynqmp_firmware PD_NAND>;
};
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- iommus = <&smmu 0x874>;
+ /* iommus = <&smmu 0x874>; */
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
reset-names = "gem0_rst";
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- iommus = <&smmu 0x875>;
+ /* iommus = <&smmu 0x875>; */
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
reset-names = "gem1_rst";
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- iommus = <&smmu 0x876>;
+ /* iommus = <&smmu 0x876>; */
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
reset-names = "gem2_rst";
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- iommus = <&smmu 0x877>;
+ /* iommus = <&smmu 0x877>; */
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
reset-names = "gem3_rst";
msi-parent = <&pcie>;
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
- <0x80 0x00000000 0x0 0x1000000>;
+ <0x80 0x00000000 0x0 0x10000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
- iommus = <&smmu 0x4d0>;
+ /* iommus = <&smmu 0x4d0>; */
power-domains = <&zynqmp_firmware PD_PCIE>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
<0x0 0xc0000000 0x0 0x8000000>;
#address-cells = <1>;
#size-cells = <0>;
- iommus = <&smmu 0x873>;
+ /* iommus = <&smmu 0x873>; */
power-domains = <&zynqmp_firmware PD_QSPI>;
};
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&zynqmp_firmware PD_SATA>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
- iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
- <&smmu 0x4c2>, <&smmu 0x4c3>;
+ /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
};
sdhci0: mmc@ff160000 {
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
- iommus = <&smmu 0x870>;
+ /* iommus = <&smmu 0x870>; */
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
power-domains = <&zynqmp_firmware PD_SD_0>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
- iommus = <&smmu 0x871>;
+ /* iommus = <&smmu 0x871>; */
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
power-domains = <&zynqmp_firmware PD_SD_1>;
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9d0000 0x0 0x100>;
+ clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
dwc3_0: usb@fe200000 {
compatible = "snps,dwc3";
+ status = "disabled";
reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupt-names = "host", "peripheral", "otg";
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "bus_early", "ref";
- iommus = <&smmu 0x860>;
+ clock-names = "ref";
+ /* iommus = <&smmu 0x860>; */
snps,quirk-frame-length-adjustment = <0x20>;
snps,resume-hs-terminations;
/* dma-coherent; */
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9e0000 0x0 0x100>;
+ clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
dwc3_1: usb@fe300000 {
compatible = "snps,dwc3";
+ status = "disabled";
reg = <0x0 0xfe300000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupt-names = "host", "peripheral", "otg";
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "bus_early", "ref";
- iommus = <&smmu 0x861>;
+ clock-names = "ref";
+ /* iommus = <&smmu 0x861>; */
snps,quirk-frame-length-adjustment = <0x20>;
snps,resume-hs-terminations;
/* dma-coherent; */
interrupt-parent = <&gic>;
clock-names = "axi_clk";
power-domains = <&zynqmp_firmware PD_DP>;
+ /* iommus = <&smmu 0xce4>; */
#dma-cells = <1>;
};
reg-names = "dp", "blend", "av_buf", "aud";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
+ /* iommus = <&smmu 0xce3>; */
clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_vtc_pixel_clk_in";
power-domains = <&zynqmp_firmware PD_DP>;
#size-cells = <2>;
dma-coherent;
+ isa@18000000 {
+ compatible = "isa";
+ #size-cells = <1>;
+ #address-cells = <2>;
+ ranges = <1 0x0 0x0 0x18000000 0x4000>;
+ };
+
liointc0: interrupt-controller@1fe01400 {
compatible = "loongson,liointc-2.0";
reg = <0x0 0x1fe01400 0x0 0x40>,
&gmac0 {
status = "okay";
+
+ phy-mode = "gmii";
+ phy-handle = <&phy0>;
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <2>;
+ };
+ };
};
&gmac1 {
status = "okay";
+
+ phy-mode = "gmii";
+ phy-handle = <&phy1>;
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy@1 {
+ reg = <2>;
+ };
+ };
};
&gmac2 {
status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <&phy2>;
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy2: ethernet-phy@2 {
+ reg = <0>;
+ };
+ };
};
#address-cells = <2>;
#size-cells = <2>;
+ isa@18400000 {
+ compatible = "isa";
+ #size-cells = <1>;
+ #address-cells = <2>;
+ ranges = <1 0x0 0x0 0x18400000 0x4000>;
+ };
+
pmc: power-management@100d0000 {
compatible = "loongson,ls2k2000-pmc", "loongson,ls2k0500-pmc", "syscon";
reg = <0x0 0x100d0000 0x0 0x58>;
msi: msi-controller@1fe01140 {
compatible = "loongson,pch-msi-1.0";
reg = <0x0 0x1fe01140 0x0 0x8>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
msi-controller;
loongson,msi-base-vec = <64>;
loongson,msi-num-vecs = <192>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
+ msi-parent = <&msi>;
bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00008000 0x0 0x18400000 0x0 0x00008000>,
+ ranges = <0x01000000 0x0 0x00008000 0x0 0x18408000 0x0 0x00008000>,
<0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>;
gmac0: ethernet@3,0 {
reg = <0x1800 0x0 0x0 0x0 0x0>;
- interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+ <13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&pic>;
status = "disabled";
};
gmac1: ethernet@3,1 {
reg = <0x1900 0x0 0x0 0x0 0x0>;
- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&pic>;
status = "disabled";
};
gmac2: ethernet@3,2 {
reg = <0x1a00 0x0 0x0 0x0 0x0>;
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+ <18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&pic>;
status = "disabled";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2023 Mobileye Vision Technologies Ltd.
+ */
+
+/dts-v1/;
+
+#include "eyeq5.dtsi"
+
+/ {
+ compatible = "mobileye,eyeq5-epm5", "mobileye,eyeq5";
+ model = "Mobile EyeQ5 MP5 Evaluation board";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x02000000>,
+ <0x8 0x02000000 0x0 0x7E000000>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2023 Mobileye Vision Technologies Ltd.
+ */
+
+/ {
+ /* Fixed clock */
+ pll_cpu: pll-cpu {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1500000000>;
+ };
+
+ pll_vdi: pll-vdi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1280000000>;
+ };
+
+ pll_per: pll-per {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2000000000>;
+ };
+
+ pll_ddr0: pll-ddr0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1857210000>;
+ };
+
+ pll_ddr1: pll-ddr1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1857210000>;
+ };
+
+/* PLL_CPU derivatives */
+ occ_cpu: occ-cpu {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_cpu>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_cpu>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ cpc_clk: cpc-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ core0_clk: core0-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ core1_clk: core1-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ core2_clk: core2-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ core3_clk: core3-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ cm_clk: cm-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ mem_clk: mem-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ occ_isram: occ-isram {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_cpu>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+ isram_clk: isram-clk { /* gate ClkRstGen_isram */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_isram>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ occ_dbu: occ-dbu {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_cpu>;
+ #clock-cells = <0>;
+ clock-div = <10>;
+ clock-mult = <1>;
+ };
+ si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_dbu>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+/* PLL_VDI derivatives */
+ occ_vdi: occ-vdi {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_vdi>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+ vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_vdi>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ occ_can_ser: occ-can-ser {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_vdi>;
+ #clock-cells = <0>;
+ clock-div = <16>;
+ clock-mult = <1>;
+ };
+ can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_can_ser>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ i2c_ser_clk: i2c-ser-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_vdi>;
+ #clock-cells = <0>;
+ clock-div = <20>;
+ clock-mult = <1>;
+ };
+/* PLL_PER derivatives */
+ occ_periph: occ-periph {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_per>;
+ #clock-cells = <0>;
+ clock-div = <16>;
+ clock-mult = <1>;
+ };
+ periph_clk: periph-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ can_clk: can-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ spi_clk: spi-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ i2c_clk: i2c-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "i2c_clk";
+ };
+ timer_clk: timer-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "timer_clk";
+ };
+ gpio_clk: gpio-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "gpio_clk";
+ };
+ emmc_sys_clk: emmc-sys-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_per>;
+ #clock-cells = <0>;
+ clock-div = <10>;
+ clock-mult = <1>;
+ clock-output-names = "emmc_sys_clk";
+ };
+ ccf_ctrl_clk: ccf-ctrl-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_per>;
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clock-output-names = "ccf_ctrl_clk";
+ };
+ occ_mjpeg_core: occ-mjpeg-core {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_per>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "occ_mjpeg_core";
+ };
+ hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_mjpeg_core>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "hsm_clk";
+ };
+ mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_mjpeg_core>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "mjpeg_core_clk";
+ };
+ fcmu_a_clk: fcmu-a-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_per>;
+ #clock-cells = <0>;
+ clock-div = <20>;
+ clock-mult = <1>;
+ clock-output-names = "fcmu_a_clk";
+ };
+ occ_pci_sys: occ-pci-sys {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_per>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "occ_pci_sys";
+ };
+ pclk: pclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>; /* 250MHz */
+ };
+ tsu_clk: tsu-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>; /* 125MHz */
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+* Copyright 2023 Mobileye Vision Technologies Ltd.
+*/
+
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
+#include "eyeq5-fixed-clocks.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "img,i6500";
+ reg = <0>;
+ clocks = <&core0_clk>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* These reserved memory regions are also defined in bootmanager
+ * for configuring inbound translation for BARS, don't change
+ * these without syncing with bootmanager
+ */
+ shmem0_reserved: shmem@804000000 {
+ reg = <0x8 0x04000000 0x0 0x1000000>;
+ };
+ shmem1_reserved: shmem@805000000 {
+ reg = <0x8 0x05000000 0x0 0x1000000>;
+ };
+ pci0_msi_reserved: pci0-msi@806000000 {
+ reg = <0x8 0x06000000 0x0 0x100000>;
+ };
+ pci1_msi_reserved: pci1-msi@806100000 {
+ reg = <0x8 0x06100000 0x0 0x100000>;
+ };
+
+ mini_coredump0_reserved: mini-coredump0@806200000 {
+ reg = <0x8 0x06200000 0x0 0x100000>;
+ };
+ mhm_reserved_0: the-mhm-reserved-0@0 {
+ reg = <0x8 0x00000000 0x0 0x0000800>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ cpu_intc: interrupt-controller {
+ compatible = "mti,cpu-interrupt-controller";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ soc: soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "simple-bus";
+
+ uart0: serial@800000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0 0x800000 0x0 0x1000>;
+ reg-io-width = <4>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&occ_periph>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ uart1: serial@900000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0 0x900000 0x0 0x1000>;
+ reg-io-width = <4>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&occ_periph>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ uart2: serial@a00000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0 0xa00000 0x0 0x1000>;
+ reg-io-width = <4>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&occ_periph>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ gic: interrupt-controller@140000 {
+ compatible = "mti,gic";
+ reg = <0x0 0x140000 0x0 0x20000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ /*
+ * Declare the interrupt-parent even though the mti,gic
+ * binding doesn't require it, such that the kernel can
+ * figure out that cpu_intc is the root interrupt
+ * controller & should be probed first.
+ */
+ interrupt-parent = <&cpu_intc>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clocks = <&core0_clk>;
+ };
+ };
+ };
+};
compatible = "ns16550a";
reg = <0xc00 0x100>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
clocks = <&sysc MT7621_CLK_UART1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ };
+
+ serial1: serial@d00 {
+ compatible = "ns16550a";
+ reg = <0xd00 0x100>;
+
+ reg-io-width = <4>;
reg-shift = <2>;
+
+ clocks = <&sysc MT7621_CLK_UART2>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
+
+ no-loopback-test;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+
+ status = "disabled";
+ };
+
+ serial2: serial@e00 {
+ compatible = "ns16550a";
+ reg = <0xe00 0x100>;
+
reg-io-width = <4>;
+ reg-shift = <2>;
+
+ clocks = <&sysc MT7621_CLK_UART3>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
+
no-loopback-test;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+
+ status = "disabled";
};
spi0: spi@b00 {
0x1e1d0700 0x0100>;
reg-names = "mac", "ippc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
clocks = <&sysc MT7621_CLK_XTAL>;
clock-names = "sys_ck";
interrupts = <93 2>;
};
- EHCI0: ehci@30010000000 {
+ EHCI0: usb@30010000000 {
compatible = "ibm,476gtr-ehci", "generic-ehci";
reg = <0x300 0x10000000 0x0 0x10000>;
interrupt-parent = <&MPIC>;
interrupt-parent = <&MPIC>;
};
- OHCI0: ohci@30010010000 {
+ OHCI0: usb@30010010000 {
compatible = "ibm,476gtr-ohci", "generic-ohci";
reg = <0x300 0x10010000 0x0 0x10000>;
interrupt-parent = <&MPIC>;
interrupts = <89 1>;
};
- OHCI1: ohci@30010020000 {
+ OHCI1: usb@30010020000 {
compatible = "ibm,476gtr-ohci", "generic-ohci";
reg = <0x300 0x10020000 0x0 0x10000>;
interrupt-parent = <&MPIC>;
};
pdma: dma-controller@3000000 {
- compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
+ compatible = "microchip,mpfs-pdma", "sifive,pdma0";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
can0: can@2010c000 {
compatible = "microchip,mpfs-can";
reg = <0x0 0x2010c000 0x0 0x1000>;
- clocks = <&clkcfg CLK_CAN0>;
+ clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;
interrupt-parent = <&plic>;
interrupts = <56>;
status = "disabled";
can1: can@2010d000 {
compatible = "microchip,mpfs-can";
reg = <0x0 0x2010d000 0x0 0x1000>;
- clocks = <&clkcfg CLK_CAN1>;
+ clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;
interrupt-parent = <&plic>;
interrupts = <57>;
status = "disabled";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xandespmu";
mmu-type = "riscv,sv39";
i-cache-size = <0x8000>;
i-cache-line-size = <0x40>;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
+ compatible = "andestech,cpu-intc", "riscv,cpu-intc";
interrupt-controller;
};
};
};
};
+&pinctrl {
+ gpio-ranges = <&pinctrl 0 0 232>;
+};
+
&soc {
dma-noncoherent;
interrupt-parent = <&plic>;
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/sophgo,sg2042-reset.h>
+
#include "sg2042-cpus.dtsi"
/ {
riscv,ndev = <224>;
};
+ rstgen: reset-controller@7030013000 {
+ compatible = "sophgo,sg2042-reset";
+ reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
+ #reset-cells = <1>;
+ };
+
uart0: serial@7040000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
clock-frequency = <500000000>;
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rstgen RST_UART0>;
status = "disabled";
};
};
model = "BeagleV Starlight Beta";
compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
};
+
+&gmac {
+ phy-handle = <&phy>;
+};
+
+&mdio {
+ phy: ethernet-phy@7 {
+ reg = <7>;
+ reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
+ };
+};
};
};
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+};
+
&gpio {
+ gmac_pins: gmac-0 {
+ gtxclk-pins {
+ pins = <PAD_FUNC_SHARE(115)>;
+ bias-pull-up;
+ drive-strength = <35>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ miitxclk-pins {
+ pins = <PAD_FUNC_SHARE(116)>;
+ bias-pull-up;
+ drive-strength = <14>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ tx-pins {
+ pins = <PAD_FUNC_SHARE(117)>,
+ <PAD_FUNC_SHARE(119)>,
+ <PAD_FUNC_SHARE(120)>,
+ <PAD_FUNC_SHARE(121)>,
+ <PAD_FUNC_SHARE(122)>,
+ <PAD_FUNC_SHARE(123)>,
+ <PAD_FUNC_SHARE(124)>,
+ <PAD_FUNC_SHARE(125)>,
+ <PAD_FUNC_SHARE(126)>;
+ bias-pull-up;
+ drive-strength = <35>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ rxclk-pins {
+ pins = <PAD_FUNC_SHARE(127)>;
+ bias-pull-up;
+ drive-strength = <14>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <6>;
+ };
+ rxer-pins {
+ pins = <PAD_FUNC_SHARE(129)>;
+ bias-pull-up;
+ drive-strength = <14>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ rx-pins {
+ pins = <PAD_FUNC_SHARE(128)>,
+ <PAD_FUNC_SHARE(130)>,
+ <PAD_FUNC_SHARE(131)>,
+ <PAD_FUNC_SHARE(132)>,
+ <PAD_FUNC_SHARE(133)>,
+ <PAD_FUNC_SHARE(134)>,
+ <PAD_FUNC_SHARE(135)>,
+ <PAD_FUNC_SHARE(136)>,
+ <PAD_FUNC_SHARE(137)>,
+ <PAD_FUNC_SHARE(138)>,
+ <PAD_FUNC_SHARE(139)>,
+ <PAD_FUNC_SHARE(140)>,
+ <PAD_FUNC_SHARE(141)>;
+ bias-pull-up;
+ drive-strength = <14>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+
i2c0_pins: i2c0-0 {
i2c-pins {
pinmux = <GPIOMUX(62, GPO_LOW,
};
};
+ pwm_pins: pwm-0 {
+ pwm-pins {
+ pinmux = <GPIOMUX(7,
+ GPO_PWM_PAD_OUT_BIT0,
+ GPO_PWM_PAD_OE_N_BIT0,
+ GPI_NONE)>,
+ <GPIOMUX(5,
+ GPO_PWM_PAD_OUT_BIT1,
+ GPO_PWM_PAD_OE_N_BIT1,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <35>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
sdio0_pins: sdio0-0 {
clk-pins {
pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
clock-frequency = <27000000>;
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
&sdio0 {
broken-cd;
bus-width = <4>;
/dts-v1/;
#include "jh7100-common.dtsi"
-#include <dt-bindings/gpio/gpio.h>
/ {
model = "StarFive VisionFive V1";
priority = <224>;
};
};
+
+&gmac {
+ phy-handle = <&phy>;
+};
+
+/*
+ * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
+ * manual adjustment of the RX internal delay to work properly. The default
+ * RX delay provided by the driver (1.95ns) is too high, but applying a 50%
+ * reduction seems to mitigate the issue.
+ *
+ * It is worth noting the adjustment is not necessary on BeagleV Starlight SBC,
+ * which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
+ * responsible for the misbehaviour, not the GMAC.
+ */
+&mdio {
+ phy: ethernet-phy@0 {
+ reg = <0>;
+ rx-internal-delay-ps = <900>;
+ };
+};
osc_sys: osc-sys {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-output-names = "osc_sys";
/* This value must be overridden by the board */
clock-frequency = <0>;
};
osc_aud: osc-aud {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-output-names = "osc_aud";
/* This value must be overridden by the board */
clock-frequency = <0>;
};
gmac_rmii_ref: gmac-rmii-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-output-names = "gmac_rmii_ref";
/* Should be overridden by the board when needed */
clock-frequency = <0>;
};
gmac_gr_mii_rxclk: gmac-gr-mii-rxclk {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-output-names = "gmac_gr_mii_rxclk";
/* Should be overridden by the board when needed */
clock-frequency = <0>;
};
status = "disabled";
};
+ gmac: ethernet@10020000 {
+ compatible = "starfive,jh7100-dwmac", "snps,dwmac";
+ reg = <0x0 0x10020000 0x0 0x10000>;
+ clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
+ <&clkgen JH7100_CLK_GMAC_AHB>,
+ <&clkgen JH7100_CLK_GMAC_PTP_REF>,
+ <&clkgen JH7100_CLK_GMAC_TX_INV>,
+ <&clkgen JH7100_CLK_GMAC_GTX>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
+ resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
+ reset-names = "ahb";
+ interrupts = <6>, <7>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ max-frame-size = <9000>;
+ snps,multicast-filter-bins = <32>;
+ snps,perfect-filter-entries = <128>;
+ starfive,syscon = <&sysmain 0x70 0>;
+ rx-fifo-depth = <32768>;
+ tx-fifo-depth = <16384>;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,fixed-burst;
+ snps,force_thresh_dma_mode;
+ status = "disabled";
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <16>;
+ snps,rd_osr_lmt = <16>;
+ snps,blen = <256 128 64 32 0 0 0>;
+ };
+ };
+
clkgen: clock-controller@11800000 {
compatible = "starfive,jh7100-clkgen";
reg = <0x0 0x11800000 0x0 0x10000>;
#reset-cells = <1>;
};
+ sysmain: syscon@11850000 {
+ compatible = "starfive,jh7100-sysmain", "syscon";
+ reg = <0x0 0x11850000 0x0 0x10000>;
+ };
+
i2c0: i2c@118b0000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x118b0000 0x0 0x10000>;
<&rstgen JH7100_RSTN_WDT>;
};
+ pwm: pwm@12490000 {
+ compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
+ reg = <0x0 0x12490000 0x0 0x10000>;
+ clocks = <&clkgen JH7100_CLK_PWM_APB>;
+ resets = <&rstgen JH7100_RSTN_PWM_APB>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
sfctemp: temperature-sensor@124a0000 {
compatible = "starfive,jh7100-temp";
reg = <0x0 0x124a0000 0x0 0x10000>;
clock-frequency = <49152000>;
};
+&camss {
+ assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
+ <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
+ assigned-clock-rates = <49500000>, <198000000>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ camss_from_csi2rx: endpoint {
+ remote-endpoint = <&csi2rx_to_camss>;
+ };
+ };
+ };
+};
+
+&csi2rx {
+ assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
+ assigned-clock-rates = <297000000>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ /* remote MIPI sensor endpoint */
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csi2rx_to_camss: endpoint {
+ remote-endpoint = <&camss_from_csi2rx>;
+ };
+ };
+ };
+};
+
&gmac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
};
};
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
};
};
+ pwm_pins: pwm-0 {
+ pwm-pins {
+ pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
+ GPOEN_SYS_PWM0_CHANNEL0,
+ GPI_NONE)>,
+ <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
+ GPOEN_SYS_PWM0_CHANNEL1,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
spi0_pins: spi0-0 {
mosi-pins {
pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
status = "disabled";
};
+ pwm: pwm@120d0000 {
+ compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
+ reg = <0x0 0x120d0000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
+ resets = <&syscrg JH7110_SYSRST_PWM_APB>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
sfctemp: temperature-sensor@120e0000 {
compatible = "starfive,jh7110-temp";
reg = <0x0 0x120e0000 0x0 0x10000>;
#power-domain-cells = <1>;
};
+ csi2rx: csi@19800000 {
+ compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
+ reg = <0x0 0x19800000 0x0 0x10000>;
+ clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>,
+ <&ispcrg JH7110_ISPCLK_VIN_APB>,
+ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>,
+ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>,
+ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>,
+ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>;
+ clock-names = "sys_clk", "p_clk",
+ "pixel_if0_clk", "pixel_if1_clk",
+ "pixel_if2_clk", "pixel_if3_clk";
+ resets = <&ispcrg JH7110_ISPRST_VIN_SYS>,
+ <&ispcrg JH7110_ISPRST_VIN_APB>,
+ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>,
+ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>,
+ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>,
+ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>;
+ reset-names = "sys", "reg_bank",
+ "pixel_if0", "pixel_if1",
+ "pixel_if2", "pixel_if3";
+ phys = <&csi_phy>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
ispcrg: clock-controller@19810000 {
compatible = "starfive,jh7110-ispcrg";
reg = <0x0 0x19810000 0x0 0x10000>;
power-domains = <&pwrc JH7110_PD_ISP>;
};
+ csi_phy: phy@19820000 {
+ compatible = "starfive,jh7110-dphy-rx";
+ reg = <0x0 0x19820000 0x0 0x10000>;
+ clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>,
+ <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>,
+ <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>;
+ clock-names = "cfg", "ref", "tx";
+ resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>,
+ <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>;
+ power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>;
+ #phy-cells = <0>;
+ };
+
+ camss: isp@19840000 {
+ compatible = "starfive,jh7110-camss";
+ reg = <0x0 0x19840000 0x0 0x10000>,
+ <0x0 0x19870000 0x0 0x30000>;
+ reg-names = "syscon", "isp";
+ clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
+ <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>,
+ <&ispcrg JH7110_ISPCLK_DVP_INV>,
+ <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>,
+ <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>,
+ <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
+ <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>;
+ clock-names = "apb_func", "wrapper_clk_c", "dvp_inv",
+ "axiwr", "mipi_rx0_pxl", "ispcore_2x",
+ "isp_axi";
+ resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>,
+ <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>,
+ <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>,
+ <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>,
+ <&syscrg JH7110_SYSRST_ISP_TOP>,
+ <&syscrg JH7110_SYSRST_ISP_TOP_AXI>;
+ reset-names = "wrapper_p", "wrapper_c", "axird",
+ "axiwr", "isp_top_n", "isp_top_axi";
+ power-domains = <&pwrc JH7110_PD_ISP>;
+ interrupts = <92>, <87>, <90>, <88>;
+ status = "disabled";
+ };
+
voutcrg: clock-controller@295c0000 {
compatible = "starfive,jh7110-voutcrg";
reg = <0x0 0x295c0000 0x0 0x10000>;
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_FSL_ESDHC_ADDR 0
-#define CFG_FEC_MXC_PHYADDR 0
+#define CFG_FEC_MXC_PHYADDR -1 /* Auto search of PHY on MII */
/* USB Configs */
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#include <configs/verdin-imx8mm.h>
+/* PHY needs a longer autoneg timeout */
+#define PHY_ANEG_TIMEOUT 20000
+
/* Custom initial environment variables */
#undef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
#define __CONFIG_J721S2_EVM_H
#include <linux/sizes.h>
-#include <config_distro_bootcmd.h>
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_J721S2_A72_EVM)
"addargs=run addcons addmisc addmtd\0" \
"mmcload=" \
"mmc rescan || reset ; load mmc ${mmcdev}:${mmcpart} " \
- "${kernel_addr_r} ${bootfile} || reset\0" \
+ "${kernel_addr_r} boot/${bootfile} || reset\0" \
"miscargs=nohlt panic=1\0" \
"mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \
"rootwait\0" \
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Collabora Ltd.
+ */
+
+#ifndef __NOVA_RK3588S_H
+#define __NOVA_RK3588S_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __NOVA_RK3588S_H */
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
-#define PHYS_SDRAM_SIZE 0x80000000
+#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */
#endif /* __PHYCORE_IMX8MP_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __POWKIDDY_X55_RK3566_H
+#define __POWKIDDY_X55_RK3566_H
+
+#include <configs/rk3568_common.h>
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#endif
#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
-#define PHYS_SDRAM 0x40000000
-#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE (long)(SZ_2G + SZ_1G)
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE (long)(SZ_1G)
/* USB Configs */
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (C) 2021 Linaro Ltd.
- * Author: Sam Protsenko <semen.protsenko@linaro.org>
- *
- * Device Tree binding constants for Exynos850 clock controller.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H
-#define _DT_BINDINGS_CLOCK_EXYNOS_850_H
-
-/* CMU_TOP */
-#define CLK_FOUT_SHARED0_PLL 1
-#define CLK_FOUT_SHARED1_PLL 2
-#define CLK_FOUT_MMC_PLL 3
-#define CLK_MOUT_SHARED0_PLL 4
-#define CLK_MOUT_SHARED1_PLL 5
-#define CLK_MOUT_MMC_PLL 6
-#define CLK_MOUT_CORE_BUS 7
-#define CLK_MOUT_CORE_CCI 8
-#define CLK_MOUT_CORE_MMC_EMBD 9
-#define CLK_MOUT_CORE_SSS 10
-#define CLK_MOUT_DPU 11
-#define CLK_MOUT_HSI_BUS 12
-#define CLK_MOUT_HSI_MMC_CARD 13
-#define CLK_MOUT_HSI_USB20DRD 14
-#define CLK_MOUT_PERI_BUS 15
-#define CLK_MOUT_PERI_UART 16
-#define CLK_MOUT_PERI_IP 17
-#define CLK_DOUT_SHARED0_DIV3 18
-#define CLK_DOUT_SHARED0_DIV2 19
-#define CLK_DOUT_SHARED1_DIV3 20
-#define CLK_DOUT_SHARED1_DIV2 21
-#define CLK_DOUT_SHARED0_DIV4 22
-#define CLK_DOUT_SHARED1_DIV4 23
-#define CLK_DOUT_CORE_BUS 24
-#define CLK_DOUT_CORE_CCI 25
-#define CLK_DOUT_CORE_MMC_EMBD 26
-#define CLK_DOUT_CORE_SSS 27
-#define CLK_DOUT_DPU 28
-#define CLK_DOUT_HSI_BUS 29
-#define CLK_DOUT_HSI_MMC_CARD 30
-#define CLK_DOUT_HSI_USB20DRD 31
-#define CLK_DOUT_PERI_BUS 32
-#define CLK_DOUT_PERI_UART 33
-#define CLK_DOUT_PERI_IP 34
-#define CLK_GOUT_CORE_BUS 35
-#define CLK_GOUT_CORE_CCI 36
-#define CLK_GOUT_CORE_MMC_EMBD 37
-#define CLK_GOUT_CORE_SSS 38
-#define CLK_GOUT_DPU 39
-#define CLK_GOUT_HSI_BUS 40
-#define CLK_GOUT_HSI_MMC_CARD 41
-#define CLK_GOUT_HSI_USB20DRD 42
-#define CLK_GOUT_PERI_BUS 43
-#define CLK_GOUT_PERI_UART 44
-#define CLK_GOUT_PERI_IP 45
-#define CLK_MOUT_CLKCMU_APM_BUS 46
-#define CLK_DOUT_CLKCMU_APM_BUS 47
-#define CLK_GOUT_CLKCMU_APM_BUS 48
-#define CLK_MOUT_AUD 49
-#define CLK_GOUT_AUD 50
-#define CLK_DOUT_AUD 51
-#define CLK_MOUT_IS_BUS 52
-#define CLK_MOUT_IS_ITP 53
-#define CLK_MOUT_IS_VRA 54
-#define CLK_MOUT_IS_GDC 55
-#define CLK_GOUT_IS_BUS 56
-#define CLK_GOUT_IS_ITP 57
-#define CLK_GOUT_IS_VRA 58
-#define CLK_GOUT_IS_GDC 59
-#define CLK_DOUT_IS_BUS 60
-#define CLK_DOUT_IS_ITP 61
-#define CLK_DOUT_IS_VRA 62
-#define CLK_DOUT_IS_GDC 63
-#define CLK_MOUT_MFCMSCL_MFC 64
-#define CLK_MOUT_MFCMSCL_M2M 65
-#define CLK_MOUT_MFCMSCL_MCSC 66
-#define CLK_MOUT_MFCMSCL_JPEG 67
-#define CLK_GOUT_MFCMSCL_MFC 68
-#define CLK_GOUT_MFCMSCL_M2M 69
-#define CLK_GOUT_MFCMSCL_MCSC 70
-#define CLK_GOUT_MFCMSCL_JPEG 71
-#define CLK_DOUT_MFCMSCL_MFC 72
-#define CLK_DOUT_MFCMSCL_M2M 73
-#define CLK_DOUT_MFCMSCL_MCSC 74
-#define CLK_DOUT_MFCMSCL_JPEG 75
-#define CLK_MOUT_G3D_SWITCH 76
-#define CLK_GOUT_G3D_SWITCH 77
-#define CLK_DOUT_G3D_SWITCH 78
-
-/* CMU_APM */
-#define CLK_RCO_I3C_PMIC 1
-#define OSCCLK_RCO_APM 2
-#define CLK_RCO_APM__ALV 3
-#define CLK_DLL_DCO 4
-#define CLK_MOUT_APM_BUS_USER 5
-#define CLK_MOUT_RCO_APM_I3C_USER 6
-#define CLK_MOUT_RCO_APM_USER 7
-#define CLK_MOUT_DLL_USER 8
-#define CLK_MOUT_CLKCMU_CHUB_BUS 9
-#define CLK_MOUT_APM_BUS 10
-#define CLK_MOUT_APM_I3C 11
-#define CLK_DOUT_CLKCMU_CHUB_BUS 12
-#define CLK_DOUT_APM_BUS 13
-#define CLK_DOUT_APM_I3C 14
-#define CLK_GOUT_CLKCMU_CMGP_BUS 15
-#define CLK_GOUT_CLKCMU_CHUB_BUS 16
-#define CLK_GOUT_RTC_PCLK 17
-#define CLK_GOUT_TOP_RTC_PCLK 18
-#define CLK_GOUT_I3C_PCLK 19
-#define CLK_GOUT_I3C_SCLK 20
-#define CLK_GOUT_SPEEDY_PCLK 21
-#define CLK_GOUT_GPIO_ALIVE_PCLK 22
-#define CLK_GOUT_PMU_ALIVE_PCLK 23
-#define CLK_GOUT_SYSREG_APM_PCLK 24
-
-/* CMU_AUD */
-#define CLK_DOUT_AUD_AUDIF 1
-#define CLK_DOUT_AUD_BUSD 2
-#define CLK_DOUT_AUD_BUSP 3
-#define CLK_DOUT_AUD_CNT 4
-#define CLK_DOUT_AUD_CPU 5
-#define CLK_DOUT_AUD_CPU_ACLK 6
-#define CLK_DOUT_AUD_CPU_PCLKDBG 7
-#define CLK_DOUT_AUD_FM 8
-#define CLK_DOUT_AUD_FM_SPDY 9
-#define CLK_DOUT_AUD_MCLK 10
-#define CLK_DOUT_AUD_UAIF0 11
-#define CLK_DOUT_AUD_UAIF1 12
-#define CLK_DOUT_AUD_UAIF2 13
-#define CLK_DOUT_AUD_UAIF3 14
-#define CLK_DOUT_AUD_UAIF4 15
-#define CLK_DOUT_AUD_UAIF5 16
-#define CLK_DOUT_AUD_UAIF6 17
-#define CLK_FOUT_AUD_PLL 18
-#define CLK_GOUT_AUD_ABOX_ACLK 19
-#define CLK_GOUT_AUD_ASB_CCLK 20
-#define CLK_GOUT_AUD_CA32_CCLK 21
-#define CLK_GOUT_AUD_CNT_BCLK 22
-#define CLK_GOUT_AUD_CODEC_MCLK 23
-#define CLK_GOUT_AUD_DAP_CCLK 24
-#define CLK_GOUT_AUD_GPIO_PCLK 25
-#define CLK_GOUT_AUD_PPMU_ACLK 26
-#define CLK_GOUT_AUD_PPMU_PCLK 27
-#define CLK_GOUT_AUD_SPDY_BCLK 28
-#define CLK_GOUT_AUD_SYSMMU_CLK 29
-#define CLK_GOUT_AUD_SYSREG_PCLK 30
-#define CLK_GOUT_AUD_TZPC_PCLK 31
-#define CLK_GOUT_AUD_UAIF0_BCLK 32
-#define CLK_GOUT_AUD_UAIF1_BCLK 33
-#define CLK_GOUT_AUD_UAIF2_BCLK 34
-#define CLK_GOUT_AUD_UAIF3_BCLK 35
-#define CLK_GOUT_AUD_UAIF4_BCLK 36
-#define CLK_GOUT_AUD_UAIF5_BCLK 37
-#define CLK_GOUT_AUD_UAIF6_BCLK 38
-#define CLK_GOUT_AUD_WDT_PCLK 39
-#define CLK_MOUT_AUD_CPU 40
-#define CLK_MOUT_AUD_CPU_HCH 41
-#define CLK_MOUT_AUD_CPU_USER 42
-#define CLK_MOUT_AUD_FM 43
-#define CLK_MOUT_AUD_PLL 44
-#define CLK_MOUT_AUD_TICK_USB_USER 45
-#define CLK_MOUT_AUD_UAIF0 46
-#define CLK_MOUT_AUD_UAIF1 47
-#define CLK_MOUT_AUD_UAIF2 48
-#define CLK_MOUT_AUD_UAIF3 49
-#define CLK_MOUT_AUD_UAIF4 50
-#define CLK_MOUT_AUD_UAIF5 51
-#define CLK_MOUT_AUD_UAIF6 52
-#define IOCLK_AUDIOCDCLK0 53
-#define IOCLK_AUDIOCDCLK1 54
-#define IOCLK_AUDIOCDCLK2 55
-#define IOCLK_AUDIOCDCLK3 56
-#define IOCLK_AUDIOCDCLK4 57
-#define IOCLK_AUDIOCDCLK5 58
-#define IOCLK_AUDIOCDCLK6 59
-#define TICK_USB 60
-#define CLK_GOUT_AUD_CMU_AUD_PCLK 61
-
-/* CMU_CMGP */
-#define CLK_RCO_CMGP 1
-#define CLK_MOUT_CMGP_ADC 2
-#define CLK_MOUT_CMGP_USI0 3
-#define CLK_MOUT_CMGP_USI1 4
-#define CLK_DOUT_CMGP_ADC 5
-#define CLK_DOUT_CMGP_USI0 6
-#define CLK_DOUT_CMGP_USI1 7
-#define CLK_GOUT_CMGP_ADC_S0_PCLK 8
-#define CLK_GOUT_CMGP_ADC_S1_PCLK 9
-#define CLK_GOUT_CMGP_GPIO_PCLK 10
-#define CLK_GOUT_CMGP_USI0_IPCLK 11
-#define CLK_GOUT_CMGP_USI0_PCLK 12
-#define CLK_GOUT_CMGP_USI1_IPCLK 13
-#define CLK_GOUT_CMGP_USI1_PCLK 14
-#define CLK_GOUT_SYSREG_CMGP_PCLK 15
-
-/* CMU_G3D */
-#define CLK_FOUT_G3D_PLL 1
-#define CLK_MOUT_G3D_PLL 2
-#define CLK_MOUT_G3D_SWITCH_USER 3
-#define CLK_MOUT_G3D_BUSD 4
-#define CLK_DOUT_G3D_BUSP 5
-#define CLK_GOUT_G3D_CMU_G3D_PCLK 6
-#define CLK_GOUT_G3D_GPU_CLK 7
-#define CLK_GOUT_G3D_TZPC_PCLK 8
-#define CLK_GOUT_G3D_GRAY2BIN_CLK 9
-#define CLK_GOUT_G3D_BUSD_CLK 10
-#define CLK_GOUT_G3D_BUSP_CLK 11
-#define CLK_GOUT_G3D_SYSREG_PCLK 12
-
-/* CMU_HSI */
-#define CLK_MOUT_HSI_BUS_USER 1
-#define CLK_MOUT_HSI_MMC_CARD_USER 2
-#define CLK_MOUT_HSI_USB20DRD_USER 3
-#define CLK_MOUT_HSI_RTC 4
-#define CLK_GOUT_USB_RTC_CLK 5
-#define CLK_GOUT_USB_REF_CLK 6
-#define CLK_GOUT_USB_PHY_REF_CLK 7
-#define CLK_GOUT_USB_PHY_ACLK 8
-#define CLK_GOUT_USB_BUS_EARLY_CLK 9
-#define CLK_GOUT_GPIO_HSI_PCLK 10
-#define CLK_GOUT_MMC_CARD_ACLK 11
-#define CLK_GOUT_MMC_CARD_SDCLKIN 12
-#define CLK_GOUT_SYSREG_HSI_PCLK 13
-#define CLK_GOUT_HSI_PPMU_ACLK 14
-#define CLK_GOUT_HSI_PPMU_PCLK 15
-#define CLK_GOUT_HSI_CMU_HSI_PCLK 16
-
-/* CMU_IS */
-#define CLK_MOUT_IS_BUS_USER 1
-#define CLK_MOUT_IS_ITP_USER 2
-#define CLK_MOUT_IS_VRA_USER 3
-#define CLK_MOUT_IS_GDC_USER 4
-#define CLK_DOUT_IS_BUSP 5
-#define CLK_GOUT_IS_CMU_IS_PCLK 6
-#define CLK_GOUT_IS_CSIS0_ACLK 7
-#define CLK_GOUT_IS_CSIS1_ACLK 8
-#define CLK_GOUT_IS_CSIS2_ACLK 9
-#define CLK_GOUT_IS_TZPC_PCLK 10
-#define CLK_GOUT_IS_CSIS_DMA_CLK 11
-#define CLK_GOUT_IS_GDC_CLK 12
-#define CLK_GOUT_IS_IPP_CLK 13
-#define CLK_GOUT_IS_ITP_CLK 14
-#define CLK_GOUT_IS_MCSC_CLK 15
-#define CLK_GOUT_IS_VRA_CLK 16
-#define CLK_GOUT_IS_PPMU_IS0_ACLK 17
-#define CLK_GOUT_IS_PPMU_IS0_PCLK 18
-#define CLK_GOUT_IS_PPMU_IS1_ACLK 19
-#define CLK_GOUT_IS_PPMU_IS1_PCLK 20
-#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
-#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
-#define CLK_GOUT_IS_SYSREG_PCLK 23
-
-/* CMU_MFCMSCL */
-#define CLK_MOUT_MFCMSCL_MFC_USER 1
-#define CLK_MOUT_MFCMSCL_M2M_USER 2
-#define CLK_MOUT_MFCMSCL_MCSC_USER 3
-#define CLK_MOUT_MFCMSCL_JPEG_USER 4
-#define CLK_DOUT_MFCMSCL_BUSP 5
-#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6
-#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7
-#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8
-#define CLK_GOUT_MFCMSCL_M2M_ACLK 9
-#define CLK_GOUT_MFCMSCL_MCSC_CLK 10
-#define CLK_GOUT_MFCMSCL_MFC_ACLK 11
-#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12
-#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13
-#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14
-#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15
-
-/* CMU_PERI */
-#define CLK_MOUT_PERI_BUS_USER 1
-#define CLK_MOUT_PERI_UART_USER 2
-#define CLK_MOUT_PERI_HSI2C_USER 3
-#define CLK_MOUT_PERI_SPI_USER 4
-#define CLK_DOUT_PERI_HSI2C0 5
-#define CLK_DOUT_PERI_HSI2C1 6
-#define CLK_DOUT_PERI_HSI2C2 7
-#define CLK_DOUT_PERI_SPI0 8
-#define CLK_GOUT_PERI_HSI2C0 9
-#define CLK_GOUT_PERI_HSI2C1 10
-#define CLK_GOUT_PERI_HSI2C2 11
-#define CLK_GOUT_GPIO_PERI_PCLK 12
-#define CLK_GOUT_HSI2C0_IPCLK 13
-#define CLK_GOUT_HSI2C0_PCLK 14
-#define CLK_GOUT_HSI2C1_IPCLK 15
-#define CLK_GOUT_HSI2C1_PCLK 16
-#define CLK_GOUT_HSI2C2_IPCLK 17
-#define CLK_GOUT_HSI2C2_PCLK 18
-#define CLK_GOUT_I2C0_PCLK 19
-#define CLK_GOUT_I2C1_PCLK 20
-#define CLK_GOUT_I2C2_PCLK 21
-#define CLK_GOUT_I2C3_PCLK 22
-#define CLK_GOUT_I2C4_PCLK 23
-#define CLK_GOUT_I2C5_PCLK 24
-#define CLK_GOUT_I2C6_PCLK 25
-#define CLK_GOUT_MCT_PCLK 26
-#define CLK_GOUT_PWM_MOTOR_PCLK 27
-#define CLK_GOUT_SPI0_IPCLK 28
-#define CLK_GOUT_SPI0_PCLK 29
-#define CLK_GOUT_SYSREG_PERI_PCLK 30
-#define CLK_GOUT_UART_IPCLK 31
-#define CLK_GOUT_UART_PCLK 32
-#define CLK_GOUT_WDT0_PCLK 33
-#define CLK_GOUT_WDT1_PCLK 34
-
-/* CMU_CORE */
-#define CLK_MOUT_CORE_BUS_USER 1
-#define CLK_MOUT_CORE_CCI_USER 2
-#define CLK_MOUT_CORE_MMC_EMBD_USER 3
-#define CLK_MOUT_CORE_SSS_USER 4
-#define CLK_MOUT_CORE_GIC 5
-#define CLK_DOUT_CORE_BUSP 6
-#define CLK_GOUT_CCI_ACLK 7
-#define CLK_GOUT_GIC_CLK 8
-#define CLK_GOUT_MMC_EMBD_ACLK 9
-#define CLK_GOUT_MMC_EMBD_SDCLKIN 10
-#define CLK_GOUT_SSS_ACLK 11
-#define CLK_GOUT_SSS_PCLK 12
-#define CLK_GOUT_GPIO_CORE_PCLK 13
-#define CLK_GOUT_SYSREG_CORE_PCLK 14
-
-/* CMU_DPU */
-#define CLK_MOUT_DPU_USER 1
-#define CLK_DOUT_DPU_BUSP 2
-#define CLK_GOUT_DPU_CMU_DPU_PCLK 3
-#define CLK_GOUT_DPU_DECON0_ACLK 4
-#define CLK_GOUT_DPU_DMA_ACLK 5
-#define CLK_GOUT_DPU_DPP_ACLK 6
-#define CLK_GOUT_DPU_PPMU_ACLK 7
-#define CLK_GOUT_DPU_PPMU_PCLK 8
-#define CLK_GOUT_DPU_SMMU_CLK 9
-#define CLK_GOUT_DPU_SYSREG_PCLK 10
-#define DPU_NR_CLK 11
-
-#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
- * Author: Finley Xiao <finley.xiao@rock-chips.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
-
-/* core clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_VPLL0 3
-#define PLL_VPLL1 4
-#define ARMCLK 5
-
-/* sclk (special clocks) */
-#define USB480M 14
-#define SCLK_RTC32K 15
-#define SCLK_PVTM_CORE 16
-#define SCLK_UART0 17
-#define SCLK_UART1 18
-#define SCLK_UART2 19
-#define SCLK_UART3 20
-#define SCLK_UART4 21
-#define SCLK_I2C0 22
-#define SCLK_I2C1 23
-#define SCLK_I2C2 24
-#define SCLK_I2C3 25
-#define SCLK_PWM0 26
-#define SCLK_SPI0 27
-#define SCLK_SPI1 28
-#define SCLK_SPI2 29
-#define SCLK_TIMER0 30
-#define SCLK_TIMER1 31
-#define SCLK_TIMER2 32
-#define SCLK_TIMER3 33
-#define SCLK_TIMER4 34
-#define SCLK_TIMER5 35
-#define SCLK_TSADC 36
-#define SCLK_SARADC 37
-#define SCLK_OTP 38
-#define SCLK_OTP_USR 39
-#define SCLK_CPU_BOOST 40
-#define SCLK_CRYPTO 41
-#define SCLK_CRYPTO_APK 42
-#define SCLK_NANDC_DIV 43
-#define SCLK_NANDC_DIV50 44
-#define SCLK_NANDC 45
-#define SCLK_SDMMC_DIV 46
-#define SCLK_SDMMC_DIV50 47
-#define SCLK_SDMMC 48
-#define SCLK_SDMMC_DRV 49
-#define SCLK_SDMMC_SAMPLE 50
-#define SCLK_SDIO_DIV 51
-#define SCLK_SDIO_DIV50 52
-#define SCLK_SDIO 53
-#define SCLK_SDIO_DRV 54
-#define SCLK_SDIO_SAMPLE 55
-#define SCLK_EMMC_DIV 56
-#define SCLK_EMMC_DIV50 57
-#define SCLK_EMMC 58
-#define SCLK_EMMC_DRV 59
-#define SCLK_EMMC_SAMPLE 60
-#define SCLK_SFC 61
-#define SCLK_OTG_ADP 62
-#define SCLK_MAC_SRC 63
-#define SCLK_MAC 64
-#define SCLK_MAC_REF 65
-#define SCLK_MAC_RX_TX 66
-#define SCLK_MAC_RMII 67
-#define SCLK_DDR_MON_TIMER 68
-#define SCLK_DDR_MON 69
-#define SCLK_DDRCLK 70
-#define SCLK_PMU 71
-#define SCLK_USBPHY_REF 72
-#define SCLK_WIFI 73
-#define SCLK_PVTM_PMU 74
-#define SCLK_PDM 75
-#define SCLK_I2S0_8CH_TX 76
-#define SCLK_I2S0_8CH_TX_OUT 77
-#define SCLK_I2S0_8CH_RX 78
-#define SCLK_I2S0_8CH_RX_OUT 79
-#define SCLK_I2S1_8CH_TX 80
-#define SCLK_I2S1_8CH_TX_OUT 81
-#define SCLK_I2S1_8CH_RX 82
-#define SCLK_I2S1_8CH_RX_OUT 83
-#define SCLK_I2S2_8CH_TX 84
-#define SCLK_I2S2_8CH_TX_OUT 85
-#define SCLK_I2S2_8CH_RX 86
-#define SCLK_I2S2_8CH_RX_OUT 87
-#define SCLK_I2S3_8CH_TX 88
-#define SCLK_I2S3_8CH_TX_OUT 89
-#define SCLK_I2S3_8CH_RX 90
-#define SCLK_I2S3_8CH_RX_OUT 91
-#define SCLK_I2S0_2CH 92
-#define SCLK_I2S0_2CH_OUT 93
-#define SCLK_I2S1_2CH 94
-#define SCLK_I2S1_2CH_OUT 95
-#define SCLK_SPDIF_TX_DIV 96
-#define SCLK_SPDIF_TX_DIV50 97
-#define SCLK_SPDIF_TX 98
-#define SCLK_SPDIF_RX_DIV 99
-#define SCLK_SPDIF_RX_DIV50 100
-#define SCLK_SPDIF_RX 101
-#define SCLK_I2S0_8CH_TX_MUX 102
-#define SCLK_I2S0_8CH_RX_MUX 103
-#define SCLK_I2S1_8CH_TX_MUX 104
-#define SCLK_I2S1_8CH_RX_MUX 105
-#define SCLK_I2S2_8CH_TX_MUX 106
-#define SCLK_I2S2_8CH_RX_MUX 107
-#define SCLK_I2S3_8CH_TX_MUX 108
-#define SCLK_I2S3_8CH_RX_MUX 109
-#define SCLK_I2S0_8CH_TX_SRC 110
-#define SCLK_I2S0_8CH_RX_SRC 111
-#define SCLK_I2S1_8CH_TX_SRC 112
-#define SCLK_I2S1_8CH_RX_SRC 113
-#define SCLK_I2S2_8CH_TX_SRC 114
-#define SCLK_I2S2_8CH_RX_SRC 115
-#define SCLK_I2S3_8CH_TX_SRC 116
-#define SCLK_I2S3_8CH_RX_SRC 117
-#define SCLK_I2S0_2CH_SRC 118
-#define SCLK_I2S1_2CH_SRC 119
-#define SCLK_PWM1 120
-#define SCLK_PWM2 121
-#define SCLK_OWIRE 122
-
-/* dclk */
-#define DCLK_VOP 125
-
-/* aclk */
-#define ACLK_BUS_SRC 130
-#define ACLK_BUS 131
-#define ACLK_PERI_SRC 132
-#define ACLK_PERI 133
-#define ACLK_MAC 134
-#define ACLK_CRYPTO 135
-#define ACLK_VOP 136
-#define ACLK_GIC 137
-#define ACLK_DMAC0 138
-#define ACLK_DMAC1 139
-
-/* hclk */
-#define HCLK_BUS 150
-#define HCLK_PERI 151
-#define HCLK_AUDIO 152
-#define HCLK_NANDC 153
-#define HCLK_SDMMC 154
-#define HCLK_SDIO 155
-#define HCLK_EMMC 156
-#define HCLK_SFC 157
-#define HCLK_OTG 158
-#define HCLK_HOST 159
-#define HCLK_HOST_ARB 160
-#define HCLK_PDM 161
-#define HCLK_SPDIFTX 162
-#define HCLK_SPDIFRX 163
-#define HCLK_I2S0_8CH 164
-#define HCLK_I2S1_8CH 165
-#define HCLK_I2S2_8CH 166
-#define HCLK_I2S3_8CH 167
-#define HCLK_I2S0_2CH 168
-#define HCLK_I2S1_2CH 169
-#define HCLK_VAD 170
-#define HCLK_CRYPTO 171
-#define HCLK_VOP 172
-
-/* pclk */
-#define PCLK_BUS 190
-#define PCLK_DDR 191
-#define PCLK_PERI 192
-#define PCLK_PMU 193
-#define PCLK_AUDIO 194
-#define PCLK_MAC 195
-#define PCLK_ACODEC 196
-#define PCLK_UART0 197
-#define PCLK_UART1 198
-#define PCLK_UART2 199
-#define PCLK_UART3 200
-#define PCLK_UART4 201
-#define PCLK_I2C0 202
-#define PCLK_I2C1 203
-#define PCLK_I2C2 204
-#define PCLK_I2C3 205
-#define PCLK_PWM0 206
-#define PCLK_SPI0 207
-#define PCLK_SPI1 208
-#define PCLK_SPI2 209
-#define PCLK_SARADC 210
-#define PCLK_TSADC 211
-#define PCLK_TIMER 212
-#define PCLK_OTP_NS 213
-#define PCLK_WDT 214
-#define PCLK_GPIO0 215
-#define PCLK_GPIO1 216
-#define PCLK_GPIO2 217
-#define PCLK_GPIO3 218
-#define PCLK_GPIO4 219
-#define PCLK_SGRF 220
-#define PCLK_GRF 221
-#define PCLK_USBSD_DET 222
-#define PCLK_DDR_UPCTL 223
-#define PCLK_DDR_MON 224
-#define PCLK_DDRPHY 225
-#define PCLK_DDR_STDBY 226
-#define PCLK_USB_GRF 227
-#define PCLK_CRU 228
-#define PCLK_OTP_PHY 229
-#define PCLK_CPU_BOOST 230
-#define PCLK_PWM1 231
-#define PCLK_PWM2 232
-#define PCLK_CAN 233
-#define PCLK_OWIRE 234
-
-#define CLK_NR_CLKS (PCLK_OWIRE + 1)
-
-/* soft-reset indices */
-
-/* cru_softrst_con0 */
-#define SRST_CORE0_PO 0
-#define SRST_CORE1_PO 1
-#define SRST_CORE2_PO 2
-#define SRST_CORE3_PO 3
-#define SRST_CORE0 4
-#define SRST_CORE1 5
-#define SRST_CORE2 6
-#define SRST_CORE3 7
-#define SRST_CORE0_DBG 8
-#define SRST_CORE1_DBG 9
-#define SRST_CORE2_DBG 10
-#define SRST_CORE3_DBG 11
-#define SRST_TOPDBG 12
-#define SRST_CORE_NOC 13
-#define SRST_STRC_A 14
-#define SRST_L2C 15
-
-/* cru_softrst_con1 */
-#define SRST_DAP 16
-#define SRST_CORE_PVTM 17
-#define SRST_CORE_PRF 18
-#define SRST_CORE_GRF 19
-#define SRST_DDRUPCTL 20
-#define SRST_DDRUPCTL_P 22
-#define SRST_MSCH 23
-#define SRST_DDRMON_P 25
-#define SRST_DDRSTDBY_P 26
-#define SRST_DDRSTDBY 27
-#define SRST_DDRPHY 28
-#define SRST_DDRPHY_DIV 29
-#define SRST_DDRPHY_P 30
-
-/* cru_softrst_con2 */
-#define SRST_BUS_NIU_H 32
-#define SRST_USB_NIU_P 33
-#define SRST_CRYPTO_A 34
-#define SRST_CRYPTO_H 35
-#define SRST_CRYPTO 36
-#define SRST_CRYPTO_APK 37
-#define SRST_VOP_A 38
-#define SRST_VOP_H 39
-#define SRST_VOP_D 40
-#define SRST_INTMEM_A 41
-#define SRST_ROM_H 42
-#define SRST_GIC_A 43
-#define SRST_UART0_P 44
-#define SRST_UART0 45
-#define SRST_UART1_P 46
-#define SRST_UART1 47
-
-/* cru_softrst_con3 */
-#define SRST_UART2_P 48
-#define SRST_UART2 49
-#define SRST_UART3_P 50
-#define SRST_UART3 51
-#define SRST_UART4_P 52
-#define SRST_UART4 53
-#define SRST_I2C0_P 54
-#define SRST_I2C0 55
-#define SRST_I2C1_P 56
-#define SRST_I2C1 57
-#define SRST_I2C2_P 58
-#define SRST_I2C2 59
-#define SRST_I2C3_P 60
-#define SRST_I2C3 61
-#define SRST_PWM0_P 62
-#define SRST_PWM0 63
-
-/* cru_softrst_con4 */
-#define SRST_SPI0_P 64
-#define SRST_SPI0 65
-#define SRST_SPI1_P 66
-#define SRST_SPI1 67
-#define SRST_SPI2_P 68
-#define SRST_SPI2 69
-#define SRST_SARADC_P 70
-#define SRST_TSADC_P 71
-#define SRST_TSADC 72
-#define SRST_TIMER0_P 73
-#define SRST_TIMER0 74
-#define SRST_TIMER1 75
-#define SRST_TIMER2 76
-#define SRST_TIMER3 77
-#define SRST_TIMER4 78
-#define SRST_TIMER5 79
-
-/* cru_softrst_con5 */
-#define SRST_OTP_NS_P 80
-#define SRST_OTP_NS_SBPI 81
-#define SRST_OTP_NS_USR 82
-#define SRST_OTP_PHY_P 83
-#define SRST_OTP_PHY 84
-#define SRST_GPIO0_P 86
-#define SRST_GPIO1_P 87
-#define SRST_GPIO2_P 88
-#define SRST_GPIO3_P 89
-#define SRST_GPIO4_P 90
-#define SRST_GRF_P 91
-#define SRST_USBSD_DET_P 92
-#define SRST_PMU 93
-#define SRST_PMU_PVTM 94
-#define SRST_USB_GRF_P 95
-
-/* cru_softrst_con6 */
-#define SRST_CPU_BOOST 96
-#define SRST_CPU_BOOST_P 97
-#define SRST_PWM1_P 98
-#define SRST_PWM1 99
-#define SRST_PWM2_P 100
-#define SRST_PWM2 101
-#define SRST_PERI_NIU_A 104
-#define SRST_PERI_NIU_H 105
-#define SRST_PERI_NIU_p 106
-#define SRST_USB2OTG_H 107
-#define SRST_USB2OTG 108
-#define SRST_USB2OTG_ADP 109
-#define SRST_USB2HOST_H 110
-#define SRST_USB2HOST_ARB_H 111
-
-/* cru_softrst_con7 */
-#define SRST_USB2HOST_AUX_H 112
-#define SRST_USB2HOST_EHCI 113
-#define SRST_USB2HOST 114
-#define SRST_USBPHYPOR 115
-#define SRST_UTMI0 116
-#define SRST_UTMI1 117
-#define SRST_SDIO_H 118
-#define SRST_EMMC_H 119
-#define SRST_SFC_H 120
-#define SRST_SFC 121
-#define SRST_SD_H 122
-#define SRST_NANDC_H 123
-#define SRST_NANDC_N 124
-#define SRST_MAC_A 125
-#define SRST_CAN_P 126
-#define SRST_OWIRE_P 127
-
-/* cru_softrst_con8 */
-#define SRST_AUDIO_NIU_H 128
-#define SRST_AUDIO_NIU_P 129
-#define SRST_PDM_H 130
-#define SRST_PDM_M 131
-#define SRST_SPDIFTX_H 132
-#define SRST_SPDIFTX_M 133
-#define SRST_SPDIFRX_H 134
-#define SRST_SPDIFRX_M 135
-#define SRST_I2S0_8CH_H 136
-#define SRST_I2S0_8CH_TX_M 137
-#define SRST_I2S0_8CH_RX_M 138
-#define SRST_I2S1_8CH_H 139
-#define SRST_I2S1_8CH_TX_M 140
-#define SRST_I2S1_8CH_RX_M 141
-#define SRST_I2S2_8CH_H 142
-#define SRST_I2S2_8CH_TX_M 143
-
-/* cru_softrst_con9 */
-#define SRST_I2S2_8CH_RX_M 144
-#define SRST_I2S3_8CH_H 145
-#define SRST_I2S3_8CH_TX_M 146
-#define SRST_I2S3_8CH_RX_M 147
-#define SRST_I2S0_2CH_H 148
-#define SRST_I2S0_2CH_M 149
-#define SRST_I2S1_2CH_H 150
-#define SRST_I2S1_2CH_M 151
-#define SRST_VAD_H 152
-#define SRST_ACODEC_P 153
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
- * Author: Elaine <zhangqing@rock-chips.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
-
-/* core clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_CPLL 3
-#define PLL_GPLL 4
-#define PLL_NPLL 5
-#define ARMCLK 6
-
-/* sclk gates (special clocks) */
-#define SCLK_RTC32K 30
-#define SCLK_SDMMC_EXT 31
-#define SCLK_SPI 32
-#define SCLK_SDMMC 33
-#define SCLK_SDIO 34
-#define SCLK_EMMC 35
-#define SCLK_TSADC 36
-#define SCLK_SARADC 37
-#define SCLK_UART0 38
-#define SCLK_UART1 39
-#define SCLK_UART2 40
-#define SCLK_I2S0 41
-#define SCLK_I2S1 42
-#define SCLK_I2S2 43
-#define SCLK_I2S1_OUT 44
-#define SCLK_I2S2_OUT 45
-#define SCLK_SPDIF 46
-#define SCLK_TIMER0 47
-#define SCLK_TIMER1 48
-#define SCLK_TIMER2 49
-#define SCLK_TIMER3 50
-#define SCLK_TIMER4 51
-#define SCLK_TIMER5 52
-#define SCLK_WIFI 53
-#define SCLK_CIF_OUT 54
-#define SCLK_I2C0 55
-#define SCLK_I2C1 56
-#define SCLK_I2C2 57
-#define SCLK_I2C3 58
-#define SCLK_CRYPTO 59
-#define SCLK_PWM 60
-#define SCLK_PDM 61
-#define SCLK_EFUSE 62
-#define SCLK_OTP 63
-#define SCLK_DDRCLK 64
-#define SCLK_VDEC_CABAC 65
-#define SCLK_VDEC_CORE 66
-#define SCLK_VENC_DSP 67
-#define SCLK_VENC_CORE 68
-#define SCLK_RGA 69
-#define SCLK_HDMI_SFC 70
-#define SCLK_HDMI_CEC 71
-#define SCLK_USB3_REF 72
-#define SCLK_USB3_SUSPEND 73
-#define SCLK_SDMMC_DRV 74
-#define SCLK_SDIO_DRV 75
-#define SCLK_EMMC_DRV 76
-#define SCLK_SDMMC_EXT_DRV 77
-#define SCLK_SDMMC_SAMPLE 78
-#define SCLK_SDIO_SAMPLE 79
-#define SCLK_EMMC_SAMPLE 80
-#define SCLK_SDMMC_EXT_SAMPLE 81
-#define SCLK_VOP 82
-#define SCLK_MAC2PHY_RXTX 83
-#define SCLK_MAC2PHY_SRC 84
-#define SCLK_MAC2PHY_REF 85
-#define SCLK_MAC2PHY_OUT 86
-#define SCLK_MAC2IO_RX 87
-#define SCLK_MAC2IO_TX 88
-#define SCLK_MAC2IO_REFOUT 89
-#define SCLK_MAC2IO_REF 90
-#define SCLK_MAC2IO_OUT 91
-#define SCLK_TSP 92
-#define SCLK_HSADC_TSP 93
-#define SCLK_USB3PHY_REF 94
-#define SCLK_REF_USB3OTG 95
-#define SCLK_USB3OTG_REF 96
-#define SCLK_USB3OTG_SUSPEND 97
-#define SCLK_REF_USB3OTG_SRC 98
-#define SCLK_MAC2IO_SRC 99
-#define SCLK_MAC2IO 100
-#define SCLK_MAC2PHY 101
-#define SCLK_MAC2IO_EXT 102
-
-/* dclk gates */
-#define DCLK_LCDC 120
-#define DCLK_HDMIPHY 121
-#define HDMIPHY 122
-#define USB480M 123
-#define DCLK_LCDC_SRC 124
-
-/* aclk gates */
-#define ACLK_AXISRAM 130
-#define ACLK_VOP_PRE 131
-#define ACLK_USB3OTG 132
-#define ACLK_RGA_PRE 133
-#define ACLK_DMAC 134
-#define ACLK_GPU 135
-#define ACLK_BUS_PRE 136
-#define ACLK_PERI_PRE 137
-#define ACLK_RKVDEC_PRE 138
-#define ACLK_RKVDEC 139
-#define ACLK_RKVENC 140
-#define ACLK_VPU_PRE 141
-#define ACLK_VIO_PRE 142
-#define ACLK_VPU 143
-#define ACLK_VIO 144
-#define ACLK_VOP 145
-#define ACLK_GMAC 146
-#define ACLK_H265 147
-#define ACLK_H264 148
-#define ACLK_MAC2PHY 149
-#define ACLK_MAC2IO 150
-#define ACLK_DCF 151
-#define ACLK_TSP 152
-#define ACLK_PERI 153
-#define ACLK_RGA 154
-#define ACLK_IEP 155
-#define ACLK_CIF 156
-#define ACLK_HDCP 157
-
-/* pclk gates */
-#define PCLK_GPIO0 200
-#define PCLK_GPIO1 201
-#define PCLK_GPIO2 202
-#define PCLK_GPIO3 203
-#define PCLK_GRF 204
-#define PCLK_I2C0 205
-#define PCLK_I2C1 206
-#define PCLK_I2C2 207
-#define PCLK_I2C3 208
-#define PCLK_SPI 209
-#define PCLK_UART0 210
-#define PCLK_UART1 211
-#define PCLK_UART2 212
-#define PCLK_TSADC 213
-#define PCLK_PWM 214
-#define PCLK_TIMER 215
-#define PCLK_BUS_PRE 216
-#define PCLK_PERI_PRE 217
-#define PCLK_HDMI_CTRL 218
-#define PCLK_HDMI_PHY 219
-#define PCLK_GMAC 220
-#define PCLK_H265 221
-#define PCLK_MAC2PHY 222
-#define PCLK_MAC2IO 223
-#define PCLK_USB3PHY_OTG 224
-#define PCLK_USB3PHY_PIPE 225
-#define PCLK_USB3_GRF 226
-#define PCLK_USB2_GRF 227
-#define PCLK_HDMIPHY 228
-#define PCLK_DDR 229
-#define PCLK_PERI 230
-#define PCLK_HDMI 231
-#define PCLK_HDCP 232
-#define PCLK_DCF 233
-#define PCLK_SARADC 234
-#define PCLK_ACODECPHY 235
-#define PCLK_WDT 236
-
-/* hclk gates */
-#define HCLK_PERI 308
-#define HCLK_TSP 309
-#define HCLK_GMAC 310
-#define HCLK_I2S0_8CH 311
-#define HCLK_I2S1_8CH 312
-#define HCLK_I2S2_2CH 313
-#define HCLK_SPDIF_8CH 314
-#define HCLK_VOP 315
-#define HCLK_NANDC 316
-#define HCLK_SDMMC 317
-#define HCLK_SDIO 318
-#define HCLK_EMMC 319
-#define HCLK_SDMMC_EXT 320
-#define HCLK_RKVDEC_PRE 321
-#define HCLK_RKVDEC 322
-#define HCLK_RKVENC 323
-#define HCLK_VPU_PRE 324
-#define HCLK_VIO_PRE 325
-#define HCLK_VPU 326
-#define HCLK_BUS_PRE 328
-#define HCLK_PERI_PRE 329
-#define HCLK_H264 330
-#define HCLK_CIF 331
-#define HCLK_OTG_PMU 332
-#define HCLK_OTG 333
-#define HCLK_HOST0 334
-#define HCLK_HOST0_ARB 335
-#define HCLK_CRYPTO_MST 336
-#define HCLK_CRYPTO_SLV 337
-#define HCLK_PDM 338
-#define HCLK_IEP 339
-#define HCLK_RGA 340
-#define HCLK_HDCP 341
-
-#define CLK_NR_CLKS (HCLK_HDCP + 1)
-
-/* soft-reset indices */
-#define SRST_CORE0_PO 0
-#define SRST_CORE1_PO 1
-#define SRST_CORE2_PO 2
-#define SRST_CORE3_PO 3
-#define SRST_CORE0 4
-#define SRST_CORE1 5
-#define SRST_CORE2 6
-#define SRST_CORE3 7
-#define SRST_CORE0_DBG 8
-#define SRST_CORE1_DBG 9
-#define SRST_CORE2_DBG 10
-#define SRST_CORE3_DBG 11
-#define SRST_TOPDBG 12
-#define SRST_CORE_NIU 13
-#define SRST_STRC_A 14
-#define SRST_L2C 15
-
-#define SRST_A53_GIC 18
-#define SRST_DAP 19
-#define SRST_PMU_P 21
-#define SRST_EFUSE 22
-#define SRST_BUSSYS_H 23
-#define SRST_BUSSYS_P 24
-#define SRST_SPDIF 25
-#define SRST_INTMEM 26
-#define SRST_ROM 27
-#define SRST_GPIO0 28
-#define SRST_GPIO1 29
-#define SRST_GPIO2 30
-#define SRST_GPIO3 31
-
-#define SRST_I2S0 32
-#define SRST_I2S1 33
-#define SRST_I2S2 34
-#define SRST_I2S0_H 35
-#define SRST_I2S1_H 36
-#define SRST_I2S2_H 37
-#define SRST_UART0 38
-#define SRST_UART1 39
-#define SRST_UART2 40
-#define SRST_UART0_P 41
-#define SRST_UART1_P 42
-#define SRST_UART2_P 43
-#define SRST_I2C0 44
-#define SRST_I2C1 45
-#define SRST_I2C2 46
-#define SRST_I2C3 47
-
-#define SRST_I2C0_P 48
-#define SRST_I2C1_P 49
-#define SRST_I2C2_P 50
-#define SRST_I2C3_P 51
-#define SRST_EFUSE_SE_P 52
-#define SRST_EFUSE_NS_P 53
-#define SRST_PWM0 54
-#define SRST_PWM0_P 55
-#define SRST_DMA 56
-#define SRST_TSP_A 57
-#define SRST_TSP_H 58
-#define SRST_TSP 59
-#define SRST_TSP_HSADC 60
-#define SRST_DCF_A 61
-#define SRST_DCF_P 62
-
-#define SRST_SCR 64
-#define SRST_SPI 65
-#define SRST_TSADC 66
-#define SRST_TSADC_P 67
-#define SRST_CRYPTO 68
-#define SRST_SGRF 69
-#define SRST_GRF 70
-#define SRST_USB_GRF 71
-#define SRST_TIMER_6CH_P 72
-#define SRST_TIMER0 73
-#define SRST_TIMER1 74
-#define SRST_TIMER2 75
-#define SRST_TIMER3 76
-#define SRST_TIMER4 77
-#define SRST_TIMER5 78
-#define SRST_USB3GRF 79
-
-#define SRST_PHYNIU 80
-#define SRST_HDMIPHY 81
-#define SRST_VDAC 82
-#define SRST_ACODEC_p 83
-#define SRST_SARADC 85
-#define SRST_SARADC_P 86
-#define SRST_GRF_DDR 87
-#define SRST_DFIMON 88
-#define SRST_MSCH 89
-#define SRST_DDRMSCH 91
-#define SRST_DDRCTRL 92
-#define SRST_DDRCTRL_P 93
-#define SRST_DDRPHY 94
-#define SRST_DDRPHY_P 95
-
-#define SRST_GMAC_NIU_A 96
-#define SRST_GMAC_NIU_P 97
-#define SRST_GMAC2PHY_A 98
-#define SRST_GMAC2IO_A 99
-#define SRST_MACPHY 100
-#define SRST_OTP_PHY 101
-#define SRST_GPU_A 102
-#define SRST_GPU_NIU_A 103
-#define SRST_SDMMCEXT 104
-#define SRST_PERIPH_NIU_A 105
-#define SRST_PERIHP_NIU_H 106
-#define SRST_PERIHP_P 107
-#define SRST_PERIPHSYS_H 108
-#define SRST_MMC0 109
-#define SRST_SDIO 110
-#define SRST_EMMC 111
-
-#define SRST_USB2OTG_H 112
-#define SRST_USB2OTG 113
-#define SRST_USB2OTG_ADP 114
-#define SRST_USB2HOST_H 115
-#define SRST_USB2HOST_ARB 116
-#define SRST_USB2HOST_AUX 117
-#define SRST_USB2HOST_EHCIPHY 118
-#define SRST_USB2HOST_UTMI 119
-#define SRST_USB3OTG 120
-#define SRST_USBPOR 121
-#define SRST_USB2OTG_UTMI 122
-#define SRST_USB2HOST_PHY_UTMI 123
-#define SRST_USB3OTG_UTMI 124
-#define SRST_USB3PHY_U2 125
-#define SRST_USB3PHY_U3 126
-#define SRST_USB3PHY_PIPE 127
-
-#define SRST_VIO_A 128
-#define SRST_VIO_BUS_H 129
-#define SRST_VIO_H2P_H 130
-#define SRST_VIO_ARBI_H 131
-#define SRST_VOP_NIU_A 132
-#define SRST_VOP_A 133
-#define SRST_VOP_H 134
-#define SRST_VOP_D 135
-#define SRST_RGA 136
-#define SRST_RGA_NIU_A 137
-#define SRST_RGA_A 138
-#define SRST_RGA_H 139
-#define SRST_IEP_A 140
-#define SRST_IEP_H 141
-#define SRST_HDMI 142
-#define SRST_HDMI_P 143
-
-#define SRST_HDCP_A 144
-#define SRST_HDCP 145
-#define SRST_HDCP_H 146
-#define SRST_CIF_A 147
-#define SRST_CIF_H 148
-#define SRST_CIF_P 149
-#define SRST_OTP_P 150
-#define SRST_OTP_SBPI 151
-#define SRST_OTP_USER 152
-#define SRST_DDRCTRL_A 153
-#define SRST_DDRSTDY_P 154
-#define SRST_DDRSTDY 155
-#define SRST_PDM_H 156
-#define SRST_PDM 157
-#define SRST_USB3PHY_OTG_P 158
-#define SRST_USB3PHY_PIPE_P 159
-
-#define SRST_VCODEC_A 160
-#define SRST_VCODEC_NIU_A 161
-#define SRST_VCODEC_H 162
-#define SRST_VCODEC_NIU_H 163
-#define SRST_VDEC_A 164
-#define SRST_VDEC_NIU_A 165
-#define SRST_VDEC_H 166
-#define SRST_VDEC_NIU_H 167
-#define SRST_VDEC_CORE 168
-#define SRST_VDEC_CABAC 169
-#define SRST_DDRPHYDIV 175
-
-#define SRST_RKVENC_NIU_A 176
-#define SRST_RKVENC_NIU_H 177
-#define SRST_RKVENC_H265_A 178
-#define SRST_RKVENC_H265_P 179
-#define SRST_RKVENC_H265_CORE 180
-#define SRST_RKVENC_H265_DSP 181
-#define SRST_RKVENC_H264_A 182
-#define SRST_RKVENC_H264_H 183
-#define SRST_RKVENC_INTMEM 184
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
-
-/* core clocks */
-#define PLL_APLLL 1
-#define PLL_APLLB 2
-#define PLL_DPLL 3
-#define PLL_CPLL 4
-#define PLL_GPLL 5
-#define PLL_NPLL 6
-#define PLL_VPLL 7
-#define ARMCLKL 8
-#define ARMCLKB 9
-
-/* sclk gates (special clocks) */
-#define SCLK_I2C1 65
-#define SCLK_I2C2 66
-#define SCLK_I2C3 67
-#define SCLK_I2C5 68
-#define SCLK_I2C6 69
-#define SCLK_I2C7 70
-#define SCLK_SPI0 71
-#define SCLK_SPI1 72
-#define SCLK_SPI2 73
-#define SCLK_SPI4 74
-#define SCLK_SPI5 75
-#define SCLK_SDMMC 76
-#define SCLK_SDIO 77
-#define SCLK_EMMC 78
-#define SCLK_TSADC 79
-#define SCLK_SARADC 80
-#define SCLK_UART0 81
-#define SCLK_UART1 82
-#define SCLK_UART2 83
-#define SCLK_UART3 84
-#define SCLK_SPDIF_8CH 85
-#define SCLK_I2S0_8CH 86
-#define SCLK_I2S1_8CH 87
-#define SCLK_I2S2_8CH 88
-#define SCLK_I2S_8CH_OUT 89
-#define SCLK_TIMER00 90
-#define SCLK_TIMER01 91
-#define SCLK_TIMER02 92
-#define SCLK_TIMER03 93
-#define SCLK_TIMER04 94
-#define SCLK_TIMER05 95
-#define SCLK_TIMER06 96
-#define SCLK_TIMER07 97
-#define SCLK_TIMER08 98
-#define SCLK_TIMER09 99
-#define SCLK_TIMER10 100
-#define SCLK_TIMER11 101
-#define SCLK_MACREF 102
-#define SCLK_MAC_RX 103
-#define SCLK_MAC_TX 104
-#define SCLK_MAC 105
-#define SCLK_MACREF_OUT 106
-#define SCLK_VOP0_PWM 107
-#define SCLK_VOP1_PWM 108
-#define SCLK_RGA_CORE 109
-#define SCLK_ISP0 110
-#define SCLK_ISP1 111
-#define SCLK_HDMI_CEC 112
-#define SCLK_HDMI_SFR 113
-#define SCLK_DP_CORE 114
-#define SCLK_PVTM_CORE_L 115
-#define SCLK_PVTM_CORE_B 116
-#define SCLK_PVTM_GPU 117
-#define SCLK_PVTM_DDR 118
-#define SCLK_MIPIDPHY_REF 119
-#define SCLK_MIPIDPHY_CFG 120
-#define SCLK_HSICPHY 121
-#define SCLK_USBPHY480M 122
-#define SCLK_USB2PHY0_REF 123
-#define SCLK_USB2PHY1_REF 124
-#define SCLK_UPHY0_TCPDPHY_REF 125
-#define SCLK_UPHY0_TCPDCORE 126
-#define SCLK_UPHY1_TCPDPHY_REF 127
-#define SCLK_UPHY1_TCPDCORE 128
-#define SCLK_USB3OTG0_REF 129
-#define SCLK_USB3OTG1_REF 130
-#define SCLK_USB3OTG0_SUSPEND 131
-#define SCLK_USB3OTG1_SUSPEND 132
-#define SCLK_CRYPTO0 133
-#define SCLK_CRYPTO1 134
-#define SCLK_CCI_TRACE 135
-#define SCLK_CS 136
-#define SCLK_CIF_OUT 137
-#define SCLK_PCIEPHY_REF 138
-#define SCLK_PCIE_CORE 139
-#define SCLK_M0_PERILP 140
-#define SCLK_M0_PERILP_DEC 141
-#define SCLK_CM0S 142
-#define SCLK_DBG_NOC 143
-#define SCLK_DBG_PD_CORE_B 144
-#define SCLK_DBG_PD_CORE_L 145
-#define SCLK_DFIMON0_TIMER 146
-#define SCLK_DFIMON1_TIMER 147
-#define SCLK_INTMEM0 148
-#define SCLK_INTMEM1 149
-#define SCLK_INTMEM2 150
-#define SCLK_INTMEM3 151
-#define SCLK_INTMEM4 152
-#define SCLK_INTMEM5 153
-#define SCLK_SDMMC_DRV 154
-#define SCLK_SDMMC_SAMPLE 155
-#define SCLK_SDIO_DRV 156
-#define SCLK_SDIO_SAMPLE 157
-#define SCLK_VDU_CORE 158
-#define SCLK_VDU_CA 159
-#define SCLK_PCIE_PM 160
-#define SCLK_SPDIF_REC_DPTX 161
-#define SCLK_DPHY_PLL 162
-#define SCLK_DPHY_TX0_CFG 163
-#define SCLK_DPHY_TX1RX1_CFG 164
-#define SCLK_DPHY_RX0_CFG 165
-#define SCLK_RMII_SRC 166
-#define SCLK_PCIEPHY_REF100M 167
-#define SCLK_USBPHY0_480M_SRC 168
-#define SCLK_USBPHY1_480M_SRC 169
-#define SCLK_DDRCLK 170
-#define SCLK_TESTOUT2 171
-
-#define DCLK_VOP0 180
-#define DCLK_VOP1 181
-#define DCLK_VOP0_DIV 182
-#define DCLK_VOP1_DIV 183
-#define DCLK_M0_PERILP 184
-
-#define FCLK_CM0S 190
-
-/* aclk gates */
-#define ACLK_PERIHP 192
-#define ACLK_PERIHP_NOC 193
-#define ACLK_PERILP0 194
-#define ACLK_PERILP0_NOC 195
-#define ACLK_PERF_PCIE 196
-#define ACLK_PCIE 197
-#define ACLK_INTMEM 198
-#define ACLK_TZMA 199
-#define ACLK_DCF 200
-#define ACLK_CCI 201
-#define ACLK_CCI_NOC0 202
-#define ACLK_CCI_NOC1 203
-#define ACLK_CCI_GRF 204
-#define ACLK_CENTER 205
-#define ACLK_CENTER_MAIN_NOC 206
-#define ACLK_CENTER_PERI_NOC 207
-#define ACLK_GPU 208
-#define ACLK_PERF_GPU 209
-#define ACLK_GPU_GRF 210
-#define ACLK_DMAC0_PERILP 211
-#define ACLK_DMAC1_PERILP 212
-#define ACLK_GMAC 213
-#define ACLK_GMAC_NOC 214
-#define ACLK_PERF_GMAC 215
-#define ACLK_VOP0_NOC 216
-#define ACLK_VOP0 217
-#define ACLK_VOP1_NOC 218
-#define ACLK_VOP1 219
-#define ACLK_RGA 220
-#define ACLK_RGA_NOC 221
-#define ACLK_HDCP 222
-#define ACLK_HDCP_NOC 223
-#define ACLK_HDCP22 224
-#define ACLK_IEP 225
-#define ACLK_IEP_NOC 226
-#define ACLK_VIO 227
-#define ACLK_VIO_NOC 228
-#define ACLK_ISP0 229
-#define ACLK_ISP1 230
-#define ACLK_ISP0_NOC 231
-#define ACLK_ISP1_NOC 232
-#define ACLK_ISP0_WRAPPER 233
-#define ACLK_ISP1_WRAPPER 234
-#define ACLK_VCODEC 235
-#define ACLK_VCODEC_NOC 236
-#define ACLK_VDU 237
-#define ACLK_VDU_NOC 238
-#define ACLK_PERI 239
-#define ACLK_EMMC 240
-#define ACLK_EMMC_CORE 241
-#define ACLK_EMMC_NOC 242
-#define ACLK_EMMC_GRF 243
-#define ACLK_USB3 244
-#define ACLK_USB3_NOC 245
-#define ACLK_USB3OTG0 246
-#define ACLK_USB3OTG1 247
-#define ACLK_USB3_RKSOC_AXI_PERF 248
-#define ACLK_USB3_GRF 249
-#define ACLK_GIC 250
-#define ACLK_GIC_NOC 251
-#define ACLK_GIC_ADB400_CORE_L_2_GIC 252
-#define ACLK_GIC_ADB400_CORE_B_2_GIC 253
-#define ACLK_GIC_ADB400_GIC_2_CORE_L 254
-#define ACLK_GIC_ADB400_GIC_2_CORE_B 255
-#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
-#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
-#define ACLK_ADB400M_PD_CORE_L 258
-#define ACLK_ADB400M_PD_CORE_B 259
-#define ACLK_PERF_CORE_L 260
-#define ACLK_PERF_CORE_B 261
-#define ACLK_GIC_PRE 262
-#define ACLK_VOP0_PRE 263
-#define ACLK_VOP1_PRE 264
-
-/* pclk gates */
-#define PCLK_PERIHP 320
-#define PCLK_PERIHP_NOC 321
-#define PCLK_PERILP0 322
-#define PCLK_PERILP1 323
-#define PCLK_PERILP1_NOC 324
-#define PCLK_PERILP_SGRF 325
-#define PCLK_PERIHP_GRF 326
-#define PCLK_PCIE 327
-#define PCLK_SGRF 328
-#define PCLK_INTR_ARB 329
-#define PCLK_CENTER_MAIN_NOC 330
-#define PCLK_CIC 331
-#define PCLK_COREDBG_B 332
-#define PCLK_COREDBG_L 333
-#define PCLK_DBG_CXCS_PD_CORE_B 334
-#define PCLK_DCF 335
-#define PCLK_GPIO2 336
-#define PCLK_GPIO3 337
-#define PCLK_GPIO4 338
-#define PCLK_GRF 339
-#define PCLK_HSICPHY 340
-#define PCLK_I2C1 341
-#define PCLK_I2C2 342
-#define PCLK_I2C3 343
-#define PCLK_I2C5 344
-#define PCLK_I2C6 345
-#define PCLK_I2C7 346
-#define PCLK_SPI0 347
-#define PCLK_SPI1 348
-#define PCLK_SPI2 349
-#define PCLK_SPI4 350
-#define PCLK_SPI5 351
-#define PCLK_UART0 352
-#define PCLK_UART1 353
-#define PCLK_UART2 354
-#define PCLK_UART3 355
-#define PCLK_TSADC 356
-#define PCLK_SARADC 357
-#define PCLK_GMAC 358
-#define PCLK_GMAC_NOC 359
-#define PCLK_TIMER0 360
-#define PCLK_TIMER1 361
-#define PCLK_EDP 362
-#define PCLK_EDP_NOC 363
-#define PCLK_EDP_CTRL 364
-#define PCLK_VIO 365
-#define PCLK_VIO_NOC 366
-#define PCLK_VIO_GRF 367
-#define PCLK_MIPI_DSI0 368
-#define PCLK_MIPI_DSI1 369
-#define PCLK_HDCP 370
-#define PCLK_HDCP_NOC 371
-#define PCLK_HDMI_CTRL 372
-#define PCLK_DP_CTRL 373
-#define PCLK_HDCP22 374
-#define PCLK_GASKET 375
-#define PCLK_DDR 376
-#define PCLK_DDR_MON 377
-#define PCLK_DDR_SGRF 378
-#define PCLK_ISP1_WRAPPER 379
-#define PCLK_WDT 380
-#define PCLK_EFUSE1024NS 381
-#define PCLK_EFUSE1024S 382
-#define PCLK_PMU_INTR_ARB 383
-#define PCLK_MAILBOX0 384
-#define PCLK_USBPHY_MUX_G 385
-#define PCLK_UPHY0_TCPHY_G 386
-#define PCLK_UPHY0_TCPD_G 387
-#define PCLK_UPHY1_TCPHY_G 388
-#define PCLK_UPHY1_TCPD_G 389
-#define PCLK_ALIVE 390
-
-/* hclk gates */
-#define HCLK_PERIHP 448
-#define HCLK_PERILP0 449
-#define HCLK_PERILP1 450
-#define HCLK_PERILP0_NOC 451
-#define HCLK_PERILP1_NOC 452
-#define HCLK_M0_PERILP 453
-#define HCLK_M0_PERILP_NOC 454
-#define HCLK_AHB1TOM 455
-#define HCLK_HOST0 456
-#define HCLK_HOST0_ARB 457
-#define HCLK_HOST1 458
-#define HCLK_HOST1_ARB 459
-#define HCLK_HSIC 460
-#define HCLK_SD 461
-#define HCLK_SDMMC 462
-#define HCLK_SDMMC_NOC 463
-#define HCLK_M_CRYPTO0 464
-#define HCLK_M_CRYPTO1 465
-#define HCLK_S_CRYPTO0 466
-#define HCLK_S_CRYPTO1 467
-#define HCLK_I2S0_8CH 468
-#define HCLK_I2S1_8CH 469
-#define HCLK_I2S2_8CH 470
-#define HCLK_SPDIF 471
-#define HCLK_VOP0_NOC 472
-#define HCLK_VOP0 473
-#define HCLK_VOP1_NOC 474
-#define HCLK_VOP1 475
-#define HCLK_ROM 476
-#define HCLK_IEP 477
-#define HCLK_IEP_NOC 478
-#define HCLK_ISP0 479
-#define HCLK_ISP1 480
-#define HCLK_ISP0_NOC 481
-#define HCLK_ISP1_NOC 482
-#define HCLK_ISP0_WRAPPER 483
-#define HCLK_ISP1_WRAPPER 484
-#define HCLK_RGA 485
-#define HCLK_RGA_NOC 486
-#define HCLK_HDCP 487
-#define HCLK_HDCP_NOC 488
-#define HCLK_HDCP22 489
-#define HCLK_VCODEC 490
-#define HCLK_VCODEC_NOC 491
-#define HCLK_VDU 492
-#define HCLK_VDU_NOC 493
-#define HCLK_SDIO 494
-#define HCLK_SDIO_NOC 495
-#define HCLK_SDIOAUDIO_NOC 496
-
-#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
-
-/* pmu-clocks indices */
-
-#define PLL_PPLL 1
-
-#define SCLK_32K_SUSPEND_PMU 2
-#define SCLK_SPI3_PMU 3
-#define SCLK_TIMER12_PMU 4
-#define SCLK_TIMER13_PMU 5
-#define SCLK_UART4_PMU 6
-#define SCLK_PVTM_PMU 7
-#define SCLK_WIFI_PMU 8
-#define SCLK_I2C0_PMU 9
-#define SCLK_I2C4_PMU 10
-#define SCLK_I2C8_PMU 11
-
-#define PCLK_SRC_PMU 19
-#define PCLK_PMU 20
-#define PCLK_PMUGRF_PMU 21
-#define PCLK_INTMEM1_PMU 22
-#define PCLK_GPIO0_PMU 23
-#define PCLK_GPIO1_PMU 24
-#define PCLK_SGRF_PMU 25
-#define PCLK_NOC_PMU 26
-#define PCLK_I2C0_PMU 27
-#define PCLK_I2C4_PMU 28
-#define PCLK_I2C8_PMU 29
-#define PCLK_RKPWM_PMU 30
-#define PCLK_SPI3_PMU 31
-#define PCLK_TIMER_PMU 32
-#define PCLK_MAILBOX_PMU 33
-#define PCLK_UART4_PMU 34
-#define PCLK_WDT_M0_PMU 35
-
-#define FCLK_CM0S_SRC_PMU 44
-#define FCLK_CM0S_PMU 45
-#define SCLK_CM0S_PMU 46
-#define HCLK_CM0S_PMU 47
-#define DCLK_CM0S_PMU 48
-#define PCLK_INTR_ARB_PMU 49
-#define HCLK_NOC_PMU 50
-
-#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
-
-/* soft-reset indices */
-
-/* cru_softrst_con0 */
-#define SRST_CORE_L0 0
-#define SRST_CORE_B0 1
-#define SRST_CORE_PO_L0 2
-#define SRST_CORE_PO_B0 3
-#define SRST_L2_L 4
-#define SRST_L2_B 5
-#define SRST_ADB_L 6
-#define SRST_ADB_B 7
-#define SRST_A_CCI 8
-#define SRST_A_CCIM0_NOC 9
-#define SRST_A_CCIM1_NOC 10
-#define SRST_DBG_NOC 11
-
-/* cru_softrst_con1 */
-#define SRST_CORE_L0_T 16
-#define SRST_CORE_L1 17
-#define SRST_CORE_L2 18
-#define SRST_CORE_L3 19
-#define SRST_CORE_PO_L0_T 20
-#define SRST_CORE_PO_L1 21
-#define SRST_CORE_PO_L2 22
-#define SRST_CORE_PO_L3 23
-#define SRST_A_ADB400_GIC2COREL 24
-#define SRST_A_ADB400_COREL2GIC 25
-#define SRST_P_DBG_L 26
-#define SRST_L2_L_T 28
-#define SRST_ADB_L_T 29
-#define SRST_A_RKPERF_L 30
-#define SRST_PVTM_CORE_L 31
-
-/* cru_softrst_con2 */
-#define SRST_CORE_B0_T 32
-#define SRST_CORE_B1 33
-#define SRST_CORE_PO_B0_T 36
-#define SRST_CORE_PO_B1 37
-#define SRST_A_ADB400_GIC2COREB 40
-#define SRST_A_ADB400_COREB2GIC 41
-#define SRST_P_DBG_B 42
-#define SRST_L2_B_T 43
-#define SRST_ADB_B_T 45
-#define SRST_A_RKPERF_B 46
-#define SRST_PVTM_CORE_B 47
-
-/* cru_softrst_con3 */
-#define SRST_A_CCI_T 50
-#define SRST_A_CCIM0_NOC_T 51
-#define SRST_A_CCIM1_NOC_T 52
-#define SRST_A_ADB400M_PD_CORE_B_T 53
-#define SRST_A_ADB400M_PD_CORE_L_T 54
-#define SRST_DBG_NOC_T 55
-#define SRST_DBG_CXCS 56
-#define SRST_CCI_TRACE 57
-#define SRST_P_CCI_GRF 58
-
-/* cru_softrst_con4 */
-#define SRST_A_CENTER_MAIN_NOC 64
-#define SRST_A_CENTER_PERI_NOC 65
-#define SRST_P_CENTER_MAIN 66
-#define SRST_P_DDRMON 67
-#define SRST_P_CIC 68
-#define SRST_P_CENTER_SGRF 69
-#define SRST_DDR0_MSCH 70
-#define SRST_DDRCFG0_MSCH 71
-#define SRST_DDR0 72
-#define SRST_DDRPHY0 73
-#define SRST_DDR1_MSCH 74
-#define SRST_DDRCFG1_MSCH 75
-#define SRST_DDR1 76
-#define SRST_DDRPHY1 77
-#define SRST_DDR_CIC 78
-#define SRST_PVTM_DDR 79
-
-/* cru_softrst_con5 */
-#define SRST_A_VCODEC_NOC 80
-#define SRST_A_VCODEC 81
-#define SRST_H_VCODEC_NOC 82
-#define SRST_H_VCODEC 83
-#define SRST_A_VDU_NOC 88
-#define SRST_A_VDU 89
-#define SRST_H_VDU_NOC 90
-#define SRST_H_VDU 91
-#define SRST_VDU_CORE 92
-#define SRST_VDU_CA 93
-
-/* cru_softrst_con6 */
-#define SRST_A_IEP_NOC 96
-#define SRST_A_VOP_IEP 97
-#define SRST_A_IEP 98
-#define SRST_H_IEP_NOC 99
-#define SRST_H_IEP 100
-#define SRST_A_RGA_NOC 102
-#define SRST_A_RGA 103
-#define SRST_H_RGA_NOC 104
-#define SRST_H_RGA 105
-#define SRST_RGA_CORE 106
-#define SRST_EMMC_NOC 108
-#define SRST_EMMC 109
-#define SRST_EMMC_GRF 110
-
-/* cru_softrst_con7 */
-#define SRST_A_PERIHP_NOC 112
-#define SRST_P_PERIHP_GRF 113
-#define SRST_H_PERIHP_NOC 114
-#define SRST_USBHOST0 115
-#define SRST_HOSTC0_AUX 116
-#define SRST_HOST0_ARB 117
-#define SRST_USBHOST1 118
-#define SRST_HOSTC1_AUX 119
-#define SRST_HOST1_ARB 120
-#define SRST_SDIO0 121
-#define SRST_SDMMC 122
-#define SRST_HSIC 123
-#define SRST_HSIC_AUX 124
-#define SRST_AHB1TOM 125
-#define SRST_P_PERIHP_NOC 126
-#define SRST_HSICPHY 127
-
-/* cru_softrst_con8 */
-#define SRST_A_PCIE 128
-#define SRST_P_PCIE 129
-#define SRST_PCIE_CORE 130
-#define SRST_PCIE_MGMT 131
-#define SRST_PCIE_MGMT_STICKY 132
-#define SRST_PCIE_PIPE 133
-#define SRST_PCIE_PM 134
-#define SRST_PCIEPHY 135
-#define SRST_A_GMAC_NOC 136
-#define SRST_A_GMAC 137
-#define SRST_P_GMAC_NOC 138
-#define SRST_P_GMAC_GRF 140
-#define SRST_HSICPHY_POR 142
-#define SRST_HSICPHY_UTMI 143
-
-/* cru_softrst_con9 */
-#define SRST_USB2PHY0_POR 144
-#define SRST_USB2PHY0_UTMI_PORT0 145
-#define SRST_USB2PHY0_UTMI_PORT1 146
-#define SRST_USB2PHY0_EHCIPHY 147
-#define SRST_UPHY0_PIPE_L00 148
-#define SRST_UPHY0 149
-#define SRST_UPHY0_TCPDPWRUP 150
-#define SRST_USB2PHY1_POR 152
-#define SRST_USB2PHY1_UTMI_PORT0 153
-#define SRST_USB2PHY1_UTMI_PORT1 154
-#define SRST_USB2PHY1_EHCIPHY 155
-#define SRST_UPHY1_PIPE_L00 156
-#define SRST_UPHY1 157
-#define SRST_UPHY1_TCPDPWRUP 158
-
-/* cru_softrst_con10 */
-#define SRST_A_PERILP0_NOC 160
-#define SRST_A_DCF 161
-#define SRST_GIC500 162
-#define SRST_DMAC0_PERILP0 163
-#define SRST_DMAC1_PERILP0 164
-#define SRST_TZMA 165
-#define SRST_INTMEM 166
-#define SRST_ADB400_MST0 167
-#define SRST_ADB400_MST1 168
-#define SRST_ADB400_SLV0 169
-#define SRST_ADB400_SLV1 170
-#define SRST_H_PERILP0 171
-#define SRST_H_PERILP0_NOC 172
-#define SRST_ROM 173
-#define SRST_CRYPTO_S 174
-#define SRST_CRYPTO_M 175
-
-/* cru_softrst_con11 */
-#define SRST_P_DCF 176
-#define SRST_CM0S_NOC 177
-#define SRST_CM0S 178
-#define SRST_CM0S_DBG 179
-#define SRST_CM0S_PO 180
-#define SRST_CRYPTO 181
-#define SRST_P_PERILP1_SGRF 182
-#define SRST_P_PERILP1_GRF 183
-#define SRST_CRYPTO1_S 184
-#define SRST_CRYPTO1_M 185
-#define SRST_CRYPTO1 186
-#define SRST_GIC_NOC 188
-#define SRST_SD_NOC 189
-#define SRST_SDIOAUDIO_BRG 190
-
-/* cru_softrst_con12 */
-#define SRST_H_PERILP1 192
-#define SRST_H_PERILP1_NOC 193
-#define SRST_H_I2S0_8CH 194
-#define SRST_H_I2S1_8CH 195
-#define SRST_H_I2S2_8CH 196
-#define SRST_H_SPDIF_8CH 197
-#define SRST_P_PERILP1_NOC 198
-#define SRST_P_EFUSE_1024 199
-#define SRST_P_EFUSE_1024S 200
-#define SRST_P_I2C0 201
-#define SRST_P_I2C1 202
-#define SRST_P_I2C2 203
-#define SRST_P_I2C3 204
-#define SRST_P_I2C4 205
-#define SRST_P_I2C5 206
-#define SRST_P_MAILBOX0 207
-
-/* cru_softrst_con13 */
-#define SRST_P_UART0 208
-#define SRST_P_UART1 209
-#define SRST_P_UART2 210
-#define SRST_P_UART3 211
-#define SRST_P_SARADC 212
-#define SRST_P_TSADC 213
-#define SRST_P_SPI0 214
-#define SRST_P_SPI1 215
-#define SRST_P_SPI2 216
-#define SRST_P_SPI4 217
-#define SRST_P_SPI5 218
-#define SRST_SPI0 219
-#define SRST_SPI1 220
-#define SRST_SPI2 221
-#define SRST_SPI4 222
-#define SRST_SPI5 223
-
-/* cru_softrst_con14 */
-#define SRST_I2S0_8CH 224
-#define SRST_I2S1_8CH 225
-#define SRST_I2S2_8CH 226
-#define SRST_SPDIF_8CH 227
-#define SRST_UART0 228
-#define SRST_UART1 229
-#define SRST_UART2 230
-#define SRST_UART3 231
-#define SRST_TSADC 232
-#define SRST_I2C0 233
-#define SRST_I2C1 234
-#define SRST_I2C2 235
-#define SRST_I2C3 236
-#define SRST_I2C4 237
-#define SRST_I2C5 238
-#define SRST_SDIOAUDIO_NOC 239
-
-/* cru_softrst_con15 */
-#define SRST_A_VIO_NOC 240
-#define SRST_A_HDCP_NOC 241
-#define SRST_A_HDCP 242
-#define SRST_H_HDCP_NOC 243
-#define SRST_H_HDCP 244
-#define SRST_P_HDCP_NOC 245
-#define SRST_P_HDCP 246
-#define SRST_P_HDMI_CTRL 247
-#define SRST_P_DP_CTRL 248
-#define SRST_S_DP_CTRL 249
-#define SRST_C_DP_CTRL 250
-#define SRST_P_MIPI_DSI0 251
-#define SRST_P_MIPI_DSI1 252
-#define SRST_DP_CORE 253
-#define SRST_DP_I2S 254
-
-/* cru_softrst_con16 */
-#define SRST_GASKET 256
-#define SRST_VIO_GRF 258
-#define SRST_DPTX_SPDIF_REC 259
-#define SRST_HDMI_CTRL 260
-#define SRST_HDCP_CTRL 261
-#define SRST_A_ISP0_NOC 262
-#define SRST_A_ISP1_NOC 263
-#define SRST_H_ISP0_NOC 266
-#define SRST_H_ISP1_NOC 267
-#define SRST_H_ISP0 268
-#define SRST_H_ISP1 269
-#define SRST_ISP0 270
-#define SRST_ISP1 271
-
-/* cru_softrst_con17 */
-#define SRST_A_VOP0_NOC 272
-#define SRST_A_VOP1_NOC 273
-#define SRST_A_VOP0 274
-#define SRST_A_VOP1 275
-#define SRST_H_VOP0_NOC 276
-#define SRST_H_VOP1_NOC 277
-#define SRST_H_VOP0 278
-#define SRST_H_VOP1 279
-#define SRST_D_VOP0 280
-#define SRST_D_VOP1 281
-#define SRST_VOP0_PWM 282
-#define SRST_VOP1_PWM 283
-#define SRST_P_EDP_NOC 284
-#define SRST_P_EDP_CTRL 285
-
-/* cru_softrst_con18 */
-#define SRST_A_GPU 288
-#define SRST_A_GPU_NOC 289
-#define SRST_A_GPU_GRF 290
-#define SRST_PVTM_GPU 291
-#define SRST_A_USB3_NOC 292
-#define SRST_A_USB3_OTG0 293
-#define SRST_A_USB3_OTG1 294
-#define SRST_A_USB3_GRF 295
-#define SRST_PMU 296
-
-/* cru_softrst_con19 */
-#define SRST_P_TIMER0_5 304
-#define SRST_TIMER0 305
-#define SRST_TIMER1 306
-#define SRST_TIMER2 307
-#define SRST_TIMER3 308
-#define SRST_TIMER4 309
-#define SRST_TIMER5 310
-#define SRST_P_TIMER6_11 311
-#define SRST_TIMER6 312
-#define SRST_TIMER7 313
-#define SRST_TIMER8 314
-#define SRST_TIMER9 315
-#define SRST_TIMER10 316
-#define SRST_TIMER11 317
-#define SRST_P_INTR_ARB_PMU 318
-#define SRST_P_ALIVE_SGRF 319
-
-/* cru_softrst_con20 */
-#define SRST_P_GPIO2 320
-#define SRST_P_GPIO3 321
-#define SRST_P_GPIO4 322
-#define SRST_P_GRF 323
-#define SRST_P_ALIVE_NOC 324
-#define SRST_P_WDT0 325
-#define SRST_P_WDT1 326
-#define SRST_P_INTR_ARB 327
-#define SRST_P_UPHY0_DPTX 328
-#define SRST_P_UPHY0_APB 330
-#define SRST_P_UPHY0_TCPHY 332
-#define SRST_P_UPHY1_TCPHY 333
-#define SRST_P_UPHY0_TCPDCTRL 334
-#define SRST_P_UPHY1_TCPDCTRL 335
-
-/* pmu soft-reset indices */
-
-/* pmu_cru_softrst_con0 */
-#define SRST_P_NOC 0
-#define SRST_P_INTMEM 1
-#define SRST_H_CM0S 2
-#define SRST_H_CM0S_NOC 3
-#define SRST_DBG_CM0S 4
-#define SRST_PO_CM0S 5
-#define SRST_P_SPI3 6
-#define SRST_SPI3 7
-#define SRST_P_TIMER_0_1 8
-#define SRST_P_TIMER_0 9
-#define SRST_P_TIMER_1 10
-#define SRST_P_UART4 11
-#define SRST_UART4 12
-#define SRST_P_WDT 13
-
-/* pmu_cru_softrst_con1 */
-#define SRST_P_I2C6 16
-#define SRST_P_I2C7 17
-#define SRST_P_I2C8 18
-#define SRST_P_MAILBOX 19
-#define SRST_P_RKPWM 20
-#define SRST_P_PMUGRF 21
-#define SRST_P_SGRF 22
-#define SRST_P_GPIO0 23
-#define SRST_P_GPIO1 24
-#define SRST_P_CRU 25
-#define SRST_P_INTR 26
-#define SRST_PVTM 27
-#define SRST_I2C6 28
-#define SRST_I2C7 29
-#define SRST_I2C8 30
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
- * Author: Elaine Zhang <zhangqing@rock-chips.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
-
-/* pmucru-clocks indices */
-
-/* pmucru plls */
-#define PLL_PPLL 1
-#define PLL_HPLL 2
-
-/* pmucru clocks */
-#define XIN_OSC0_DIV 4
-#define CLK_RTC_32K 5
-#define CLK_PMU 6
-#define CLK_I2C0 7
-#define CLK_RTC32K_FRAC 8
-#define CLK_UART0_DIV 9
-#define CLK_UART0_FRAC 10
-#define SCLK_UART0 11
-#define DBCLK_GPIO0 12
-#define CLK_PWM0 13
-#define CLK_CAPTURE_PWM0_NDFT 14
-#define CLK_PMUPVTM 15
-#define CLK_CORE_PMUPVTM 16
-#define CLK_REF24M 17
-#define XIN_OSC0_USBPHY0_G 18
-#define CLK_USBPHY0_REF 19
-#define XIN_OSC0_USBPHY1_G 20
-#define CLK_USBPHY1_REF 21
-#define XIN_OSC0_MIPIDSIPHY0_G 22
-#define CLK_MIPIDSIPHY0_REF 23
-#define XIN_OSC0_MIPIDSIPHY1_G 24
-#define CLK_MIPIDSIPHY1_REF 25
-#define CLK_WIFI_DIV 26
-#define CLK_WIFI_OSC0 27
-#define CLK_WIFI 28
-#define CLK_PCIEPHY0_DIV 29
-#define CLK_PCIEPHY0_OSC0 30
-#define CLK_PCIEPHY0_REF 31
-#define CLK_PCIEPHY1_DIV 32
-#define CLK_PCIEPHY1_OSC0 33
-#define CLK_PCIEPHY1_REF 34
-#define CLK_PCIEPHY2_DIV 35
-#define CLK_PCIEPHY2_OSC0 36
-#define CLK_PCIEPHY2_REF 37
-#define CLK_PCIE30PHY_REF_M 38
-#define CLK_PCIE30PHY_REF_N 39
-#define CLK_HDMI_REF 40
-#define XIN_OSC0_EDPPHY_G 41
-#define PCLK_PDPMU 42
-#define PCLK_PMU 43
-#define PCLK_UART0 44
-#define PCLK_I2C0 45
-#define PCLK_GPIO0 46
-#define PCLK_PMUPVTM 47
-#define PCLK_PWM0 48
-#define CLK_PDPMU 49
-#define SCLK_32K_IOE 50
-
-#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1)
-
-/* cru-clocks indices */
-
-/* cru plls */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_CPLL 3
-#define PLL_GPLL 4
-#define PLL_VPLL 5
-#define PLL_NPLL 6
-
-/* cru clocks */
-#define CPLL_333M 9
-#define ARMCLK 10
-#define USB480M 11
-#define ACLK_CORE_NIU2BUS 18
-#define CLK_CORE_PVTM 19
-#define CLK_CORE_PVTM_CORE 20
-#define CLK_CORE_PVTPLL 21
-#define CLK_GPU_SRC 22
-#define CLK_GPU_PRE_NDFT 23
-#define CLK_GPU_PRE_MUX 24
-#define ACLK_GPU_PRE 25
-#define PCLK_GPU_PRE 26
-#define CLK_GPU 27
-#define CLK_GPU_NP5 28
-#define PCLK_GPU_PVTM 29
-#define CLK_GPU_PVTM 30
-#define CLK_GPU_PVTM_CORE 31
-#define CLK_GPU_PVTPLL 32
-#define CLK_NPU_SRC 33
-#define CLK_NPU_PRE_NDFT 34
-#define CLK_NPU 35
-#define CLK_NPU_NP5 36
-#define HCLK_NPU_PRE 37
-#define PCLK_NPU_PRE 38
-#define ACLK_NPU_PRE 39
-#define ACLK_NPU 40
-#define HCLK_NPU 41
-#define PCLK_NPU_PVTM 42
-#define CLK_NPU_PVTM 43
-#define CLK_NPU_PVTM_CORE 44
-#define CLK_NPU_PVTPLL 45
-#define CLK_DDRPHY1X_SRC 46
-#define CLK_DDRPHY1X_HWFFC_SRC 47
-#define CLK_DDR1X 48
-#define CLK_MSCH 49
-#define CLK24_DDRMON 50
-#define ACLK_GIC_AUDIO 51
-#define HCLK_GIC_AUDIO 52
-#define HCLK_SDMMC_BUFFER 53
-#define DCLK_SDMMC_BUFFER 54
-#define ACLK_GIC600 55
-#define ACLK_SPINLOCK 56
-#define HCLK_I2S0_8CH 57
-#define HCLK_I2S1_8CH 58
-#define HCLK_I2S2_2CH 59
-#define HCLK_I2S3_2CH 60
-#define CLK_I2S0_8CH_TX_SRC 61
-#define CLK_I2S0_8CH_TX_FRAC 62
-#define MCLK_I2S0_8CH_TX 63
-#define I2S0_MCLKOUT_TX 64
-#define CLK_I2S0_8CH_RX_SRC 65
-#define CLK_I2S0_8CH_RX_FRAC 66
-#define MCLK_I2S0_8CH_RX 67
-#define I2S0_MCLKOUT_RX 68
-#define CLK_I2S1_8CH_TX_SRC 69
-#define CLK_I2S1_8CH_TX_FRAC 70
-#define MCLK_I2S1_8CH_TX 71
-#define I2S1_MCLKOUT_TX 72
-#define CLK_I2S1_8CH_RX_SRC 73
-#define CLK_I2S1_8CH_RX_FRAC 74
-#define MCLK_I2S1_8CH_RX 75
-#define I2S1_MCLKOUT_RX 76
-#define CLK_I2S2_2CH_SRC 77
-#define CLK_I2S2_2CH_FRAC 78
-#define MCLK_I2S2_2CH 79
-#define I2S2_MCLKOUT 80
-#define CLK_I2S3_2CH_TX_SRC 81
-#define CLK_I2S3_2CH_TX_FRAC 82
-#define MCLK_I2S3_2CH_TX 83
-#define I2S3_MCLKOUT_TX 84
-#define CLK_I2S3_2CH_RX_SRC 85
-#define CLK_I2S3_2CH_RX_FRAC 86
-#define MCLK_I2S3_2CH_RX 87
-#define I2S3_MCLKOUT_RX 88
-#define HCLK_PDM 89
-#define MCLK_PDM 90
-#define HCLK_VAD 91
-#define HCLK_SPDIF_8CH 92
-#define MCLK_SPDIF_8CH_SRC 93
-#define MCLK_SPDIF_8CH_FRAC 94
-#define MCLK_SPDIF_8CH 95
-#define HCLK_AUDPWM 96
-#define SCLK_AUDPWM_SRC 97
-#define SCLK_AUDPWM_FRAC 98
-#define SCLK_AUDPWM 99
-#define HCLK_ACDCDIG 100
-#define CLK_ACDCDIG_I2C 101
-#define CLK_ACDCDIG_DAC 102
-#define CLK_ACDCDIG_ADC 103
-#define ACLK_SECURE_FLASH 104
-#define HCLK_SECURE_FLASH 105
-#define ACLK_CRYPTO_NS 106
-#define HCLK_CRYPTO_NS 107
-#define CLK_CRYPTO_NS_CORE 108
-#define CLK_CRYPTO_NS_PKA 109
-#define CLK_CRYPTO_NS_RNG 110
-#define HCLK_TRNG_NS 111
-#define CLK_TRNG_NS 112
-#define PCLK_OTPC_NS 113
-#define CLK_OTPC_NS_SBPI 114
-#define CLK_OTPC_NS_USR 115
-#define HCLK_NANDC 116
-#define NCLK_NANDC 117
-#define HCLK_SFC 118
-#define HCLK_SFC_XIP 119
-#define SCLK_SFC 120
-#define ACLK_EMMC 121
-#define HCLK_EMMC 122
-#define BCLK_EMMC 123
-#define CCLK_EMMC 124
-#define TCLK_EMMC 125
-#define ACLK_PIPE 126
-#define PCLK_PIPE 127
-#define PCLK_PIPE_GRF 128
-#define ACLK_PCIE20_MST 129
-#define ACLK_PCIE20_SLV 130
-#define ACLK_PCIE20_DBI 131
-#define PCLK_PCIE20 132
-#define CLK_PCIE20_AUX_NDFT 133
-#define CLK_PCIE20_AUX_DFT 134
-#define CLK_PCIE20_PIPE_DFT 135
-#define ACLK_PCIE30X1_MST 136
-#define ACLK_PCIE30X1_SLV 137
-#define ACLK_PCIE30X1_DBI 138
-#define PCLK_PCIE30X1 139
-#define CLK_PCIE30X1_AUX_NDFT 140
-#define CLK_PCIE30X1_AUX_DFT 141
-#define CLK_PCIE30X1_PIPE_DFT 142
-#define ACLK_PCIE30X2_MST 143
-#define ACLK_PCIE30X2_SLV 144
-#define ACLK_PCIE30X2_DBI 145
-#define PCLK_PCIE30X2 146
-#define CLK_PCIE30X2_AUX_NDFT 147
-#define CLK_PCIE30X2_AUX_DFT 148
-#define CLK_PCIE30X2_PIPE_DFT 149
-#define ACLK_SATA0 150
-#define CLK_SATA0_PMALIVE 151
-#define CLK_SATA0_RXOOB 152
-#define CLK_SATA0_PIPE_NDFT 153
-#define CLK_SATA0_PIPE_DFT 154
-#define ACLK_SATA1 155
-#define CLK_SATA1_PMALIVE 156
-#define CLK_SATA1_RXOOB 157
-#define CLK_SATA1_PIPE_NDFT 158
-#define CLK_SATA1_PIPE_DFT 159
-#define ACLK_SATA2 160
-#define CLK_SATA2_PMALIVE 161
-#define CLK_SATA2_RXOOB 162
-#define CLK_SATA2_PIPE_NDFT 163
-#define CLK_SATA2_PIPE_DFT 164
-#define ACLK_USB3OTG0 165
-#define CLK_USB3OTG0_REF 166
-#define CLK_USB3OTG0_SUSPEND 167
-#define ACLK_USB3OTG1 168
-#define CLK_USB3OTG1_REF 169
-#define CLK_USB3OTG1_SUSPEND 170
-#define CLK_XPCS_EEE 171
-#define PCLK_XPCS 172
-#define ACLK_PHP 173
-#define HCLK_PHP 174
-#define PCLK_PHP 175
-#define HCLK_SDMMC0 176
-#define CLK_SDMMC0 177
-#define HCLK_SDMMC1 178
-#define CLK_SDMMC1 179
-#define ACLK_GMAC0 180
-#define PCLK_GMAC0 181
-#define CLK_MAC0_2TOP 182
-#define CLK_MAC0_OUT 183
-#define CLK_MAC0_REFOUT 184
-#define CLK_GMAC0_PTP_REF 185
-#define ACLK_USB 186
-#define HCLK_USB 187
-#define PCLK_USB 188
-#define HCLK_USB2HOST0 189
-#define HCLK_USB2HOST0_ARB 190
-#define HCLK_USB2HOST1 191
-#define HCLK_USB2HOST1_ARB 192
-#define HCLK_SDMMC2 193
-#define CLK_SDMMC2 194
-#define ACLK_GMAC1 195
-#define PCLK_GMAC1 196
-#define CLK_MAC1_2TOP 197
-#define CLK_MAC1_OUT 198
-#define CLK_MAC1_REFOUT 199
-#define CLK_GMAC1_PTP_REF 200
-#define ACLK_PERIMID 201
-#define HCLK_PERIMID 202
-#define ACLK_VI 203
-#define HCLK_VI 204
-#define PCLK_VI 205
-#define ACLK_VICAP 206
-#define HCLK_VICAP 207
-#define DCLK_VICAP 208
-#define ICLK_VICAP_G 209
-#define ACLK_ISP 210
-#define HCLK_ISP 211
-#define CLK_ISP 212
-#define PCLK_CSI2HOST1 213
-#define CLK_CIF_OUT 214
-#define CLK_CAM0_OUT 215
-#define CLK_CAM1_OUT 216
-#define ACLK_VO 217
-#define HCLK_VO 218
-#define PCLK_VO 219
-#define ACLK_VOP_PRE 220
-#define ACLK_VOP 221
-#define HCLK_VOP 222
-#define DCLK_VOP0 223
-#define DCLK_VOP1 224
-#define DCLK_VOP2 225
-#define CLK_VOP_PWM 226
-#define ACLK_HDCP 227
-#define HCLK_HDCP 228
-#define PCLK_HDCP 229
-#define PCLK_HDMI_HOST 230
-#define CLK_HDMI_SFR 231
-#define PCLK_DSITX_0 232
-#define PCLK_DSITX_1 233
-#define PCLK_EDP_CTRL 234
-#define CLK_EDP_200M 235
-#define ACLK_VPU_PRE 236
-#define HCLK_VPU_PRE 237
-#define ACLK_VPU 238
-#define HCLK_VPU 239
-#define ACLK_RGA_PRE 240
-#define HCLK_RGA_PRE 241
-#define PCLK_RGA_PRE 242
-#define ACLK_RGA 243
-#define HCLK_RGA 244
-#define CLK_RGA_CORE 245
-#define ACLK_IEP 246
-#define HCLK_IEP 247
-#define CLK_IEP_CORE 248
-#define HCLK_EBC 249
-#define DCLK_EBC 250
-#define ACLK_JDEC 251
-#define HCLK_JDEC 252
-#define ACLK_JENC 253
-#define HCLK_JENC 254
-#define PCLK_EINK 255
-#define HCLK_EINK 256
-#define ACLK_RKVENC_PRE 257
-#define HCLK_RKVENC_PRE 258
-#define ACLK_RKVENC 259
-#define HCLK_RKVENC 260
-#define CLK_RKVENC_CORE 261
-#define ACLK_RKVDEC_PRE 262
-#define HCLK_RKVDEC_PRE 263
-#define ACLK_RKVDEC 264
-#define HCLK_RKVDEC 265
-#define CLK_RKVDEC_CA 266
-#define CLK_RKVDEC_CORE 267
-#define CLK_RKVDEC_HEVC_CA 268
-#define ACLK_BUS 269
-#define PCLK_BUS 270
-#define PCLK_TSADC 271
-#define CLK_TSADC_TSEN 272
-#define CLK_TSADC 273
-#define PCLK_SARADC 274
-#define CLK_SARADC 275
-#define PCLK_SCR 276
-#define PCLK_WDT_NS 277
-#define TCLK_WDT_NS 278
-#define ACLK_DMAC0 279
-#define ACLK_DMAC1 280
-#define ACLK_MCU 281
-#define PCLK_INTMUX 282
-#define PCLK_MAILBOX 283
-#define PCLK_UART1 284
-#define CLK_UART1_SRC 285
-#define CLK_UART1_FRAC 286
-#define SCLK_UART1 287
-#define PCLK_UART2 288
-#define CLK_UART2_SRC 289
-#define CLK_UART2_FRAC 290
-#define SCLK_UART2 291
-#define PCLK_UART3 292
-#define CLK_UART3_SRC 293
-#define CLK_UART3_FRAC 294
-#define SCLK_UART3 295
-#define PCLK_UART4 296
-#define CLK_UART4_SRC 297
-#define CLK_UART4_FRAC 298
-#define SCLK_UART4 299
-#define PCLK_UART5 300
-#define CLK_UART5_SRC 301
-#define CLK_UART5_FRAC 302
-#define SCLK_UART5 303
-#define PCLK_UART6 304
-#define CLK_UART6_SRC 305
-#define CLK_UART6_FRAC 306
-#define SCLK_UART6 307
-#define PCLK_UART7 308
-#define CLK_UART7_SRC 309
-#define CLK_UART7_FRAC 310
-#define SCLK_UART7 311
-#define PCLK_UART8 312
-#define CLK_UART8_SRC 313
-#define CLK_UART8_FRAC 314
-#define SCLK_UART8 315
-#define PCLK_UART9 316
-#define CLK_UART9_SRC 317
-#define CLK_UART9_FRAC 318
-#define SCLK_UART9 319
-#define PCLK_CAN0 320
-#define CLK_CAN0 321
-#define PCLK_CAN1 322
-#define CLK_CAN1 323
-#define PCLK_CAN2 324
-#define CLK_CAN2 325
-#define CLK_I2C 326
-#define PCLK_I2C1 327
-#define CLK_I2C1 328
-#define PCLK_I2C2 329
-#define CLK_I2C2 330
-#define PCLK_I2C3 331
-#define CLK_I2C3 332
-#define PCLK_I2C4 333
-#define CLK_I2C4 334
-#define PCLK_I2C5 335
-#define CLK_I2C5 336
-#define PCLK_SPI0 337
-#define CLK_SPI0 338
-#define PCLK_SPI1 339
-#define CLK_SPI1 340
-#define PCLK_SPI2 341
-#define CLK_SPI2 342
-#define PCLK_SPI3 343
-#define CLK_SPI3 344
-#define PCLK_PWM1 345
-#define CLK_PWM1 346
-#define CLK_PWM1_CAPTURE 347
-#define PCLK_PWM2 348
-#define CLK_PWM2 349
-#define CLK_PWM2_CAPTURE 350
-#define PCLK_PWM3 351
-#define CLK_PWM3 352
-#define CLK_PWM3_CAPTURE 353
-#define DBCLK_GPIO 354
-#define PCLK_GPIO1 355
-#define DBCLK_GPIO1 356
-#define PCLK_GPIO2 357
-#define DBCLK_GPIO2 358
-#define PCLK_GPIO3 359
-#define DBCLK_GPIO3 360
-#define PCLK_GPIO4 361
-#define DBCLK_GPIO4 362
-#define OCC_SCAN_CLK_GPIO 363
-#define PCLK_TIMER 364
-#define CLK_TIMER0 365
-#define CLK_TIMER1 366
-#define CLK_TIMER2 367
-#define CLK_TIMER3 368
-#define CLK_TIMER4 369
-#define CLK_TIMER5 370
-#define ACLK_TOP_HIGH 371
-#define ACLK_TOP_LOW 372
-#define HCLK_TOP 373
-#define PCLK_TOP 374
-#define PCLK_PCIE30PHY 375
-#define CLK_OPTC_ARB 376
-#define PCLK_MIPICSIPHY 377
-#define PCLK_MIPIDSIPHY0 378
-#define PCLK_MIPIDSIPHY1 379
-#define PCLK_PIPEPHY0 380
-#define PCLK_PIPEPHY1 381
-#define PCLK_PIPEPHY2 382
-#define PCLK_CPU_BOOST 383
-#define CLK_CPU_BOOST 384
-#define PCLK_OTPPHY 385
-#define SCLK_GMAC0 386
-#define SCLK_GMAC0_RGMII_SPEED 387
-#define SCLK_GMAC0_RMII_SPEED 388
-#define SCLK_GMAC0_RX_TX 389
-#define SCLK_GMAC1 390
-#define SCLK_GMAC1_RGMII_SPEED 391
-#define SCLK_GMAC1_RMII_SPEED 392
-#define SCLK_GMAC1_RX_TX 393
-#define SCLK_SDMMC0_DRV 394
-#define SCLK_SDMMC0_SAMPLE 395
-#define SCLK_SDMMC1_DRV 396
-#define SCLK_SDMMC1_SAMPLE 397
-#define SCLK_SDMMC2_DRV 398
-#define SCLK_SDMMC2_SAMPLE 399
-#define SCLK_EMMC_DRV 400
-#define SCLK_EMMC_SAMPLE 401
-#define PCLK_EDPPHY_GRF 402
-#define CLK_HDMI_CEC 403
-#define CLK_I2S0_8CH_TX 404
-#define CLK_I2S0_8CH_RX 405
-#define CLK_I2S1_8CH_TX 406
-#define CLK_I2S1_8CH_RX 407
-#define CLK_I2S2_2CH 408
-#define CLK_I2S3_2CH_TX 409
-#define CLK_I2S3_2CH_RX 410
-#define CPLL_500M 411
-#define CPLL_250M 412
-#define CPLL_125M 413
-#define CPLL_62P5M 414
-#define CPLL_50M 415
-#define CPLL_25M 416
-#define CPLL_100M 417
-#define SCLK_DDRCLK 418
-
-#define PCLK_CORE_PVTM 450
-
-#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)
-
-/* pmu soft-reset indices */
-/* pmucru_softrst_con0 */
-#define SRST_P_PDPMU_NIU 0
-#define SRST_P_PMUCRU 1
-#define SRST_P_PMUGRF 2
-#define SRST_P_I2C0 3
-#define SRST_I2C0 4
-#define SRST_P_UART0 5
-#define SRST_S_UART0 6
-#define SRST_P_PWM0 7
-#define SRST_PWM0 8
-#define SRST_P_GPIO0 9
-#define SRST_GPIO0 10
-#define SRST_P_PMUPVTM 11
-#define SRST_PMUPVTM 12
-
-/* soft-reset indices */
-
-/* cru_softrst_con0 */
-#define SRST_NCORERESET0 0
-#define SRST_NCORERESET1 1
-#define SRST_NCORERESET2 2
-#define SRST_NCORERESET3 3
-#define SRST_NCPUPORESET0 4
-#define SRST_NCPUPORESET1 5
-#define SRST_NCPUPORESET2 6
-#define SRST_NCPUPORESET3 7
-#define SRST_NSRESET 8
-#define SRST_NSPORESET 9
-#define SRST_NATRESET 10
-#define SRST_NGICRESET 11
-#define SRST_NPRESET 12
-#define SRST_NPERIPHRESET 13
-
-/* cru_softrst_con1 */
-#define SRST_A_CORE_NIU2DDR 16
-#define SRST_A_CORE_NIU2BUS 17
-#define SRST_P_DBG_NIU 18
-#define SRST_P_DBG 19
-#define SRST_P_DBG_DAPLITE 20
-#define SRST_DAP 21
-#define SRST_A_ADB400_CORE2GIC 22
-#define SRST_A_ADB400_GIC2CORE 23
-#define SRST_P_CORE_GRF 24
-#define SRST_P_CORE_PVTM 25
-#define SRST_CORE_PVTM 26
-#define SRST_CORE_PVTPLL 27
-
-/* cru_softrst_con2 */
-#define SRST_GPU 32
-#define SRST_A_GPU_NIU 33
-#define SRST_P_GPU_NIU 34
-#define SRST_P_GPU_PVTM 35
-#define SRST_GPU_PVTM 36
-#define SRST_GPU_PVTPLL 37
-#define SRST_A_NPU_NIU 40
-#define SRST_H_NPU_NIU 41
-#define SRST_P_NPU_NIU 42
-#define SRST_A_NPU 43
-#define SRST_H_NPU 44
-#define SRST_P_NPU_PVTM 45
-#define SRST_NPU_PVTM 46
-#define SRST_NPU_PVTPLL 47
-
-/* cru_softrst_con3 */
-#define SRST_A_MSCH 51
-#define SRST_HWFFC_CTRL 52
-#define SRST_DDR_ALWAYSON 53
-#define SRST_A_DDRSPLIT 54
-#define SRST_DDRDFI_CTL 55
-#define SRST_A_DMA2DDR 57
-
-/* cru_softrst_con4 */
-#define SRST_A_PERIMID_NIU 64
-#define SRST_H_PERIMID_NIU 65
-#define SRST_A_GIC_AUDIO_NIU 66
-#define SRST_H_GIC_AUDIO_NIU 67
-#define SRST_A_GIC600 68
-#define SRST_A_GIC600_DEBUG 69
-#define SRST_A_GICADB_CORE2GIC 70
-#define SRST_A_GICADB_GIC2CORE 71
-#define SRST_A_SPINLOCK 72
-#define SRST_H_SDMMC_BUFFER 73
-#define SRST_D_SDMMC_BUFFER 74
-#define SRST_H_I2S0_8CH 75
-#define SRST_H_I2S1_8CH 76
-#define SRST_H_I2S2_2CH 77
-#define SRST_H_I2S3_2CH 78
-
-/* cru_softrst_con5 */
-#define SRST_M_I2S0_8CH_TX 80
-#define SRST_M_I2S0_8CH_RX 81
-#define SRST_M_I2S1_8CH_TX 82
-#define SRST_M_I2S1_8CH_RX 83
-#define SRST_M_I2S2_2CH 84
-#define SRST_M_I2S3_2CH_TX 85
-#define SRST_M_I2S3_2CH_RX 86
-#define SRST_H_PDM 87
-#define SRST_M_PDM 88
-#define SRST_H_VAD 89
-#define SRST_H_SPDIF_8CH 90
-#define SRST_M_SPDIF_8CH 91
-#define SRST_H_AUDPWM 92
-#define SRST_S_AUDPWM 93
-#define SRST_H_ACDCDIG 94
-#define SRST_ACDCDIG 95
-
-/* cru_softrst_con6 */
-#define SRST_A_SECURE_FLASH_NIU 96
-#define SRST_H_SECURE_FLASH_NIU 97
-#define SRST_A_CRYPTO_NS 103
-#define SRST_H_CRYPTO_NS 104
-#define SRST_CRYPTO_NS_CORE 105
-#define SRST_CRYPTO_NS_PKA 106
-#define SRST_CRYPTO_NS_RNG 107
-#define SRST_H_TRNG_NS 108
-#define SRST_TRNG_NS 109
-
-/* cru_softrst_con7 */
-#define SRST_H_NANDC 112
-#define SRST_N_NANDC 113
-#define SRST_H_SFC 114
-#define SRST_H_SFC_XIP 115
-#define SRST_S_SFC 116
-#define SRST_A_EMMC 117
-#define SRST_H_EMMC 118
-#define SRST_B_EMMC 119
-#define SRST_C_EMMC 120
-#define SRST_T_EMMC 121
-
-/* cru_softrst_con8 */
-#define SRST_A_PIPE_NIU 128
-#define SRST_P_PIPE_NIU 130
-#define SRST_P_PIPE_GRF 133
-#define SRST_A_SATA0 134
-#define SRST_SATA0_PIPE 135
-#define SRST_SATA0_PMALIVE 136
-#define SRST_SATA0_RXOOB 137
-#define SRST_A_SATA1 138
-#define SRST_SATA1_PIPE 139
-#define SRST_SATA1_PMALIVE 140
-#define SRST_SATA1_RXOOB 141
-
-/* cru_softrst_con9 */
-#define SRST_A_SATA2 144
-#define SRST_SATA2_PIPE 145
-#define SRST_SATA2_PMALIVE 146
-#define SRST_SATA2_RXOOB 147
-#define SRST_USB3OTG0 148
-#define SRST_USB3OTG1 149
-#define SRST_XPCS 150
-#define SRST_XPCS_TX_DIV10 151
-#define SRST_XPCS_RX_DIV10 152
-#define SRST_XPCS_XGXS_RX 153
-
-/* cru_softrst_con10 */
-#define SRST_P_PCIE20 160
-#define SRST_PCIE20_POWERUP 161
-#define SRST_MSTR_ARESET_PCIE20 162
-#define SRST_SLV_ARESET_PCIE20 163
-#define SRST_DBI_ARESET_PCIE20 164
-#define SRST_BRESET_PCIE20 165
-#define SRST_PERST_PCIE20 166
-#define SRST_CORE_RST_PCIE20 167
-#define SRST_NSTICKY_RST_PCIE20 168
-#define SRST_STICKY_RST_PCIE20 169
-#define SRST_PWR_RST_PCIE20 170
-
-/* cru_softrst_con11 */
-#define SRST_P_PCIE30X1 176
-#define SRST_PCIE30X1_POWERUP 177
-#define SRST_M_ARESET_PCIE30X1 178
-#define SRST_S_ARESET_PCIE30X1 179
-#define SRST_D_ARESET_PCIE30X1 180
-#define SRST_BRESET_PCIE30X1 181
-#define SRST_PERST_PCIE30X1 182
-#define SRST_CORE_RST_PCIE30X1 183
-#define SRST_NSTC_RST_PCIE30X1 184
-#define SRST_STC_RST_PCIE30X1 185
-#define SRST_PWR_RST_PCIE30X1 186
-
-/* cru_softrst_con12 */
-#define SRST_P_PCIE30X2 192
-#define SRST_PCIE30X2_POWERUP 193
-#define SRST_M_ARESET_PCIE30X2 194
-#define SRST_S_ARESET_PCIE30X2 195
-#define SRST_D_ARESET_PCIE30X2 196
-#define SRST_BRESET_PCIE30X2 197
-#define SRST_PERST_PCIE30X2 198
-#define SRST_CORE_RST_PCIE30X2 199
-#define SRST_NSTC_RST_PCIE30X2 200
-#define SRST_STC_RST_PCIE30X2 201
-#define SRST_PWR_RST_PCIE30X2 202
-
-/* cru_softrst_con13 */
-#define SRST_A_PHP_NIU 208
-#define SRST_H_PHP_NIU 209
-#define SRST_P_PHP_NIU 210
-#define SRST_H_SDMMC0 211
-#define SRST_SDMMC0 212
-#define SRST_H_SDMMC1 213
-#define SRST_SDMMC1 214
-#define SRST_A_GMAC0 215
-#define SRST_GMAC0_TIMESTAMP 216
-
-/* cru_softrst_con14 */
-#define SRST_A_USB_NIU 224
-#define SRST_H_USB_NIU 225
-#define SRST_P_USB_NIU 226
-#define SRST_P_USB_GRF 227
-#define SRST_H_USB2HOST0 228
-#define SRST_H_USB2HOST0_ARB 229
-#define SRST_USB2HOST0_UTMI 230
-#define SRST_H_USB2HOST1 231
-#define SRST_H_USB2HOST1_ARB 232
-#define SRST_USB2HOST1_UTMI 233
-#define SRST_H_SDMMC2 234
-#define SRST_SDMMC2 235
-#define SRST_A_GMAC1 236
-#define SRST_GMAC1_TIMESTAMP 237
-
-/* cru_softrst_con15 */
-#define SRST_A_VI_NIU 240
-#define SRST_H_VI_NIU 241
-#define SRST_P_VI_NIU 242
-#define SRST_A_VICAP 247
-#define SRST_H_VICAP 248
-#define SRST_D_VICAP 249
-#define SRST_I_VICAP 250
-#define SRST_P_VICAP 251
-#define SRST_H_ISP 252
-#define SRST_ISP 253
-#define SRST_P_CSI2HOST1 255
-
-/* cru_softrst_con16 */
-#define SRST_A_VO_NIU 256
-#define SRST_H_VO_NIU 257
-#define SRST_P_VO_NIU 258
-#define SRST_A_VOP_NIU 259
-#define SRST_A_VOP 260
-#define SRST_H_VOP 261
-#define SRST_VOP0 262
-#define SRST_VOP1 263
-#define SRST_VOP2 264
-#define SRST_VOP_PWM 265
-#define SRST_A_HDCP 266
-#define SRST_H_HDCP 267
-#define SRST_P_HDCP 268
-#define SRST_P_HDMI_HOST 270
-#define SRST_HDMI_HOST 271
-
-/* cru_softrst_con17 */
-#define SRST_P_DSITX_0 272
-#define SRST_P_DSITX_1 273
-#define SRST_P_EDP_CTRL 274
-#define SRST_EDP_24M 275
-#define SRST_A_VPU_NIU 280
-#define SRST_H_VPU_NIU 281
-#define SRST_A_VPU 282
-#define SRST_H_VPU 283
-#define SRST_H_EINK 286
-#define SRST_P_EINK 287
-
-/* cru_softrst_con18 */
-#define SRST_A_RGA_NIU 288
-#define SRST_H_RGA_NIU 289
-#define SRST_P_RGA_NIU 290
-#define SRST_A_RGA 292
-#define SRST_H_RGA 293
-#define SRST_RGA_CORE 294
-#define SRST_A_IEP 295
-#define SRST_H_IEP 296
-#define SRST_IEP_CORE 297
-#define SRST_H_EBC 298
-#define SRST_D_EBC 299
-#define SRST_A_JDEC 300
-#define SRST_H_JDEC 301
-#define SRST_A_JENC 302
-#define SRST_H_JENC 303
-
-/* cru_softrst_con19 */
-#define SRST_A_VENC_NIU 304
-#define SRST_H_VENC_NIU 305
-#define SRST_A_RKVENC 307
-#define SRST_H_RKVENC 308
-#define SRST_RKVENC_CORE 309
-
-/* cru_softrst_con20 */
-#define SRST_A_RKVDEC_NIU 320
-#define SRST_H_RKVDEC_NIU 321
-#define SRST_A_RKVDEC 322
-#define SRST_H_RKVDEC 323
-#define SRST_RKVDEC_CA 324
-#define SRST_RKVDEC_CORE 325
-#define SRST_RKVDEC_HEVC_CA 326
-
-/* cru_softrst_con21 */
-#define SRST_A_BUS_NIU 336
-#define SRST_P_BUS_NIU 338
-#define SRST_P_CAN0 340
-#define SRST_CAN0 341
-#define SRST_P_CAN1 342
-#define SRST_CAN1 343
-#define SRST_P_CAN2 344
-#define SRST_CAN2 345
-#define SRST_P_GPIO1 346
-#define SRST_GPIO1 347
-#define SRST_P_GPIO2 348
-#define SRST_GPIO2 349
-#define SRST_P_GPIO3 350
-#define SRST_GPIO3 351
-
-/* cru_softrst_con22 */
-#define SRST_P_GPIO4 352
-#define SRST_GPIO4 353
-#define SRST_P_I2C1 354
-#define SRST_I2C1 355
-#define SRST_P_I2C2 356
-#define SRST_I2C2 357
-#define SRST_P_I2C3 358
-#define SRST_I2C3 359
-#define SRST_P_I2C4 360
-#define SRST_I2C4 361
-#define SRST_P_I2C5 362
-#define SRST_I2C5 363
-#define SRST_P_OTPC_NS 364
-#define SRST_OTPC_NS_SBPI 365
-#define SRST_OTPC_NS_USR 366
-
-/* cru_softrst_con23 */
-#define SRST_P_PWM1 368
-#define SRST_PWM1 369
-#define SRST_P_PWM2 370
-#define SRST_PWM2 371
-#define SRST_P_PWM3 372
-#define SRST_PWM3 373
-#define SRST_P_SPI0 374
-#define SRST_SPI0 375
-#define SRST_P_SPI1 376
-#define SRST_SPI1 377
-#define SRST_P_SPI2 378
-#define SRST_SPI2 379
-#define SRST_P_SPI3 380
-#define SRST_SPI3 381
-
-/* cru_softrst_con24 */
-#define SRST_P_SARADC 384
-#define SRST_P_TSADC 385
-#define SRST_TSADC 386
-#define SRST_P_TIMER 387
-#define SRST_TIMER0 388
-#define SRST_TIMER1 389
-#define SRST_TIMER2 390
-#define SRST_TIMER3 391
-#define SRST_TIMER4 392
-#define SRST_TIMER5 393
-#define SRST_P_UART1 394
-#define SRST_S_UART1 395
-
-/* cru_softrst_con25 */
-#define SRST_P_UART2 400
-#define SRST_S_UART2 401
-#define SRST_P_UART3 402
-#define SRST_S_UART3 403
-#define SRST_P_UART4 404
-#define SRST_S_UART4 405
-#define SRST_P_UART5 406
-#define SRST_S_UART5 407
-#define SRST_P_UART6 408
-#define SRST_S_UART6 409
-#define SRST_P_UART7 410
-#define SRST_S_UART7 411
-#define SRST_P_UART8 412
-#define SRST_S_UART8 413
-#define SRST_P_UART9 414
-#define SRST_S_UART9 415
-
-/* cru_softrst_con26 */
-#define SRST_P_GRF 416
-#define SRST_P_GRF_VCCIO12 417
-#define SRST_P_GRF_VCCIO34 418
-#define SRST_P_GRF_VCCIO567 419
-#define SRST_P_SCR 420
-#define SRST_P_WDT_NS 421
-#define SRST_T_WDT_NS 422
-#define SRST_P_DFT2APB 423
-#define SRST_A_MCU 426
-#define SRST_P_INTMUX 427
-#define SRST_P_MAILBOX 428
-
-/* cru_softrst_con27 */
-#define SRST_A_TOP_HIGH_NIU 432
-#define SRST_A_TOP_LOW_NIU 433
-#define SRST_H_TOP_NIU 434
-#define SRST_P_TOP_NIU 435
-#define SRST_P_TOP_CRU 438
-#define SRST_P_DDRPHY 439
-#define SRST_DDRPHY 440
-#define SRST_P_MIPICSIPHY 442
-#define SRST_P_MIPIDSIPHY0 443
-#define SRST_P_MIPIDSIPHY1 444
-#define SRST_P_PCIE30PHY 445
-#define SRST_PCIE30PHY 446
-#define SRST_P_PCIE30PHY_GRF 447
-
-/* cru_softrst_con28 */
-#define SRST_P_APB2ASB_LEFT 448
-#define SRST_P_APB2ASB_BOTTOM 449
-#define SRST_P_ASB2APB_LEFT 450
-#define SRST_P_ASB2APB_BOTTOM 451
-#define SRST_P_PIPEPHY0 452
-#define SRST_PIPEPHY0 453
-#define SRST_P_PIPEPHY1 454
-#define SRST_PIPEPHY1 455
-#define SRST_P_PIPEPHY2 456
-#define SRST_PIPEPHY2 457
-#define SRST_P_USB2PHY0_GRF 458
-#define SRST_P_USB2PHY1_GRF 459
-#define SRST_P_CPU_BOOST 460
-#define SRST_CPU_BOOST 461
-#define SRST_P_OTPPHY 462
-#define SRST_OTPPHY 463
-
-/* cru_softrst_con29 */
-#define SRST_USB2PHY0_POR 464
-#define SRST_USB2PHY0_USB3OTG0 465
-#define SRST_USB2PHY0_USB3OTG1 466
-#define SRST_USB2PHY1_POR 467
-#define SRST_USB2PHY1_USB2HOST0 468
-#define SRST_USB2PHY1_USB2HOST1 469
-#define SRST_P_EDPPHY_GRF 470
-#define SRST_TSADCPHY 471
-#define SRST_GMAC0_DELAYLINE 472
-#define SRST_GMAC1_DELAYLINE 473
-#define SRST_OTPC_ARB 474
-#define SRST_P_PIPEPHY0_GRF 475
-#define SRST_P_PIPEPHY1_GRF 476
-#define SRST_P_PIPEPHY2_GRF 477
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
-/*
- * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
- * Copyright (c) 2022 Collabora Ltd.
- *
- * Author: Elaine Zhang <zhangqing@rock-chips.com>
- * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
-
-/* cru-clocks indices */
-
-#define PLL_B0PLL 0
-#define PLL_B1PLL 1
-#define PLL_LPLL 2
-#define PLL_V0PLL 3
-#define PLL_AUPLL 4
-#define PLL_CPLL 5
-#define PLL_GPLL 6
-#define PLL_NPLL 7
-#define PLL_PPLL 8
-#define ARMCLK_L 9
-#define ARMCLK_B01 10
-#define ARMCLK_B23 11
-#define PCLK_BIGCORE0_ROOT 12
-#define PCLK_BIGCORE0_PVTM 13
-#define PCLK_BIGCORE1_ROOT 14
-#define PCLK_BIGCORE1_PVTM 15
-#define PCLK_DSU_S_ROOT 16
-#define PCLK_DSU_ROOT 17
-#define PCLK_DSU_NS_ROOT 18
-#define PCLK_LITCORE_PVTM 19
-#define PCLK_DBG 20
-#define PCLK_DSU 21
-#define PCLK_S_DAPLITE 22
-#define PCLK_M_DAPLITE 23
-#define MBIST_MCLK_PDM1 24
-#define MBIST_CLK_ACDCDIG 25
-#define HCLK_I2S2_2CH 26
-#define HCLK_I2S3_2CH 27
-#define CLK_I2S2_2CH_SRC 28
-#define CLK_I2S2_2CH_FRAC 29
-#define CLK_I2S2_2CH 30
-#define MCLK_I2S2_2CH 31
-#define I2S2_2CH_MCLKOUT 32
-#define CLK_DAC_ACDCDIG 33
-#define CLK_I2S3_2CH_SRC 34
-#define CLK_I2S3_2CH_FRAC 35
-#define CLK_I2S3_2CH 36
-#define MCLK_I2S3_2CH 37
-#define I2S3_2CH_MCLKOUT 38
-#define PCLK_ACDCDIG 39
-#define HCLK_I2S0_8CH 40
-#define CLK_I2S0_8CH_TX_SRC 41
-#define CLK_I2S0_8CH_TX_FRAC 42
-#define MCLK_I2S0_8CH_TX 43
-#define CLK_I2S0_8CH_TX 44
-#define CLK_I2S0_8CH_RX_SRC 45
-#define CLK_I2S0_8CH_RX_FRAC 46
-#define MCLK_I2S0_8CH_RX 47
-#define CLK_I2S0_8CH_RX 48
-#define I2S0_8CH_MCLKOUT 49
-#define HCLK_PDM1 50
-#define MCLK_PDM1 51
-#define HCLK_AUDIO_ROOT 52
-#define PCLK_AUDIO_ROOT 53
-#define HCLK_SPDIF0 54
-#define CLK_SPDIF0_SRC 55
-#define CLK_SPDIF0_FRAC 56
-#define MCLK_SPDIF0 57
-#define CLK_SPDIF0 58
-#define CLK_SPDIF1 59
-#define HCLK_SPDIF1 60
-#define CLK_SPDIF1_SRC 61
-#define CLK_SPDIF1_FRAC 62
-#define MCLK_SPDIF1 63
-#define ACLK_AV1_ROOT 64
-#define ACLK_AV1 65
-#define PCLK_AV1_ROOT 66
-#define PCLK_AV1 67
-#define PCLK_MAILBOX0 68
-#define PCLK_MAILBOX1 69
-#define PCLK_MAILBOX2 70
-#define PCLK_PMU2 71
-#define PCLK_PMUCM0_INTMUX 72
-#define PCLK_DDRCM0_INTMUX 73
-#define PCLK_TOP 74
-#define PCLK_PWM1 75
-#define CLK_PWM1 76
-#define CLK_PWM1_CAPTURE 77
-#define PCLK_PWM2 78
-#define CLK_PWM2 79
-#define CLK_PWM2_CAPTURE 80
-#define PCLK_PWM3 81
-#define CLK_PWM3 82
-#define CLK_PWM3_CAPTURE 83
-#define PCLK_BUSTIMER0 84
-#define PCLK_BUSTIMER1 85
-#define CLK_BUS_TIMER_ROOT 86
-#define CLK_BUSTIMER0 87
-#define CLK_BUSTIMER1 88
-#define CLK_BUSTIMER2 89
-#define CLK_BUSTIMER3 90
-#define CLK_BUSTIMER4 91
-#define CLK_BUSTIMER5 92
-#define CLK_BUSTIMER6 93
-#define CLK_BUSTIMER7 94
-#define CLK_BUSTIMER8 95
-#define CLK_BUSTIMER9 96
-#define CLK_BUSTIMER10 97
-#define CLK_BUSTIMER11 98
-#define PCLK_WDT0 99
-#define TCLK_WDT0 100
-#define PCLK_CAN0 101
-#define CLK_CAN0 102
-#define PCLK_CAN1 103
-#define CLK_CAN1 104
-#define PCLK_CAN2 105
-#define CLK_CAN2 106
-#define ACLK_DECOM 107
-#define PCLK_DECOM 108
-#define DCLK_DECOM 109
-#define ACLK_DMAC0 110
-#define ACLK_DMAC1 111
-#define ACLK_DMAC2 112
-#define ACLK_BUS_ROOT 113
-#define ACLK_GIC 114
-#define PCLK_GPIO1 115
-#define DBCLK_GPIO1 116
-#define PCLK_GPIO2 117
-#define DBCLK_GPIO2 118
-#define PCLK_GPIO3 119
-#define DBCLK_GPIO3 120
-#define PCLK_GPIO4 121
-#define DBCLK_GPIO4 122
-#define PCLK_I2C1 123
-#define PCLK_I2C2 124
-#define PCLK_I2C3 125
-#define PCLK_I2C4 126
-#define PCLK_I2C5 127
-#define PCLK_I2C6 128
-#define PCLK_I2C7 129
-#define PCLK_I2C8 130
-#define CLK_I2C1 131
-#define CLK_I2C2 132
-#define CLK_I2C3 133
-#define CLK_I2C4 134
-#define CLK_I2C5 135
-#define CLK_I2C6 136
-#define CLK_I2C7 137
-#define CLK_I2C8 138
-#define PCLK_OTPC_NS 139
-#define CLK_OTPC_NS 140
-#define CLK_OTPC_ARB 141
-#define CLK_OTPC_AUTO_RD_G 142
-#define CLK_OTP_PHY_G 143
-#define PCLK_SARADC 144
-#define CLK_SARADC 145
-#define PCLK_SPI0 146
-#define PCLK_SPI1 147
-#define PCLK_SPI2 148
-#define PCLK_SPI3 149
-#define PCLK_SPI4 150
-#define CLK_SPI0 151
-#define CLK_SPI1 152
-#define CLK_SPI2 153
-#define CLK_SPI3 154
-#define CLK_SPI4 155
-#define ACLK_SPINLOCK 156
-#define PCLK_TSADC 157
-#define CLK_TSADC 158
-#define PCLK_UART1 159
-#define PCLK_UART2 160
-#define PCLK_UART3 161
-#define PCLK_UART4 162
-#define PCLK_UART5 163
-#define PCLK_UART6 164
-#define PCLK_UART7 165
-#define PCLK_UART8 166
-#define PCLK_UART9 167
-#define CLK_UART1_SRC 168
-#define CLK_UART1_FRAC 169
-#define CLK_UART1 170
-#define SCLK_UART1 171
-#define CLK_UART2_SRC 172
-#define CLK_UART2_FRAC 173
-#define CLK_UART2 174
-#define SCLK_UART2 175
-#define CLK_UART3_SRC 176
-#define CLK_UART3_FRAC 177
-#define CLK_UART3 178
-#define SCLK_UART3 179
-#define CLK_UART4_SRC 180
-#define CLK_UART4_FRAC 181
-#define CLK_UART4 182
-#define SCLK_UART4 183
-#define CLK_UART5_SRC 184
-#define CLK_UART5_FRAC 185
-#define CLK_UART5 186
-#define SCLK_UART5 187
-#define CLK_UART6_SRC 188
-#define CLK_UART6_FRAC 189
-#define CLK_UART6 190
-#define SCLK_UART6 191
-#define CLK_UART7_SRC 192
-#define CLK_UART7_FRAC 193
-#define CLK_UART7 194
-#define SCLK_UART7 195
-#define CLK_UART8_SRC 196
-#define CLK_UART8_FRAC 197
-#define CLK_UART8 198
-#define SCLK_UART8 199
-#define CLK_UART9_SRC 200
-#define CLK_UART9_FRAC 201
-#define CLK_UART9 202
-#define SCLK_UART9 203
-#define ACLK_CENTER_ROOT 204
-#define ACLK_CENTER_LOW_ROOT 205
-#define HCLK_CENTER_ROOT 206
-#define PCLK_CENTER_ROOT 207
-#define ACLK_DMA2DDR 208
-#define ACLK_DDR_SHAREMEM 209
-#define ACLK_CENTER_S200_ROOT 210
-#define ACLK_CENTER_S400_ROOT 211
-#define FCLK_DDR_CM0_CORE 212
-#define CLK_DDR_TIMER_ROOT 213
-#define CLK_DDR_TIMER0 214
-#define CLK_DDR_TIMER1 215
-#define TCLK_WDT_DDR 216
-#define CLK_DDR_CM0_RTC 217
-#define PCLK_WDT 218
-#define PCLK_TIMER 219
-#define PCLK_DMA2DDR 220
-#define PCLK_SHAREMEM 221
-#define CLK_50M_SRC 222
-#define CLK_100M_SRC 223
-#define CLK_150M_SRC 224
-#define CLK_200M_SRC 225
-#define CLK_250M_SRC 226
-#define CLK_300M_SRC 227
-#define CLK_350M_SRC 228
-#define CLK_400M_SRC 229
-#define CLK_450M_SRC 230
-#define CLK_500M_SRC 231
-#define CLK_600M_SRC 232
-#define CLK_650M_SRC 233
-#define CLK_700M_SRC 234
-#define CLK_800M_SRC 235
-#define CLK_1000M_SRC 236
-#define CLK_1200M_SRC 237
-#define ACLK_TOP_M300_ROOT 238
-#define ACLK_TOP_M500_ROOT 239
-#define ACLK_TOP_M400_ROOT 240
-#define ACLK_TOP_S200_ROOT 241
-#define ACLK_TOP_S400_ROOT 242
-#define CLK_MIPI_CAMARAOUT_M0 243
-#define CLK_MIPI_CAMARAOUT_M1 244
-#define CLK_MIPI_CAMARAOUT_M2 245
-#define CLK_MIPI_CAMARAOUT_M3 246
-#define CLK_MIPI_CAMARAOUT_M4 247
-#define MCLK_GMAC0_OUT 248
-#define REFCLKO25M_ETH0_OUT 249
-#define REFCLKO25M_ETH1_OUT 250
-#define CLK_CIFOUT_OUT 251
-#define PCLK_MIPI_DCPHY0 252
-#define PCLK_MIPI_DCPHY1 253
-#define PCLK_CSIPHY0 254
-#define PCLK_CSIPHY1 255
-#define ACLK_TOP_ROOT 256
-#define PCLK_TOP_ROOT 257
-#define ACLK_LOW_TOP_ROOT 258
-#define PCLK_CRU 259
-#define PCLK_GPU_ROOT 260
-#define CLK_GPU_SRC 261
-#define CLK_GPU 262
-#define CLK_GPU_COREGROUP 263
-#define CLK_GPU_STACKS 264
-#define PCLK_GPU_PVTM 265
-#define CLK_GPU_PVTM 266
-#define CLK_CORE_GPU_PVTM 267
-#define PCLK_GPU_GRF 268
-#define ACLK_ISP1_ROOT 269
-#define HCLK_ISP1_ROOT 270
-#define CLK_ISP1_CORE 271
-#define CLK_ISP1_CORE_MARVIN 272
-#define CLK_ISP1_CORE_VICAP 273
-#define ACLK_ISP1 274
-#define HCLK_ISP1 275
-#define ACLK_NPU1 276
-#define HCLK_NPU1 277
-#define ACLK_NPU2 278
-#define HCLK_NPU2 279
-#define HCLK_NPU_CM0_ROOT 280
-#define FCLK_NPU_CM0_CORE 281
-#define CLK_NPU_CM0_RTC 282
-#define PCLK_NPU_PVTM 283
-#define PCLK_NPU_GRF 284
-#define CLK_NPU_PVTM 285
-#define CLK_CORE_NPU_PVTM 286
-#define ACLK_NPU0 287
-#define HCLK_NPU0 288
-#define HCLK_NPU_ROOT 289
-#define CLK_NPU_DSU0 290
-#define PCLK_NPU_ROOT 291
-#define PCLK_NPU_TIMER 292
-#define CLK_NPUTIMER_ROOT 293
-#define CLK_NPUTIMER0 294
-#define CLK_NPUTIMER1 295
-#define PCLK_NPU_WDT 296
-#define TCLK_NPU_WDT 297
-#define HCLK_EMMC 298
-#define ACLK_EMMC 299
-#define CCLK_EMMC 300
-#define BCLK_EMMC 301
-#define TMCLK_EMMC 302
-#define SCLK_SFC 303
-#define HCLK_SFC 304
-#define HCLK_SFC_XIP 305
-#define HCLK_NVM_ROOT 306
-#define ACLK_NVM_ROOT 307
-#define CLK_GMAC0_PTP_REF 308
-#define CLK_GMAC1_PTP_REF 309
-#define CLK_GMAC_125M 310
-#define CLK_GMAC_50M 311
-#define ACLK_PHP_GIC_ITS 312
-#define ACLK_MMU_PCIE 313
-#define ACLK_MMU_PHP 314
-#define ACLK_PCIE_4L_DBI 315
-#define ACLK_PCIE_2L_DBI 316
-#define ACLK_PCIE_1L0_DBI 317
-#define ACLK_PCIE_1L1_DBI 318
-#define ACLK_PCIE_1L2_DBI 319
-#define ACLK_PCIE_4L_MSTR 320
-#define ACLK_PCIE_2L_MSTR 321
-#define ACLK_PCIE_1L0_MSTR 322
-#define ACLK_PCIE_1L1_MSTR 323
-#define ACLK_PCIE_1L2_MSTR 324
-#define ACLK_PCIE_4L_SLV 325
-#define ACLK_PCIE_2L_SLV 326
-#define ACLK_PCIE_1L0_SLV 327
-#define ACLK_PCIE_1L1_SLV 328
-#define ACLK_PCIE_1L2_SLV 329
-#define PCLK_PCIE_4L 330
-#define PCLK_PCIE_2L 331
-#define PCLK_PCIE_1L0 332
-#define PCLK_PCIE_1L1 333
-#define PCLK_PCIE_1L2 334
-#define CLK_PCIE_AUX0 335
-#define CLK_PCIE_AUX1 336
-#define CLK_PCIE_AUX2 337
-#define CLK_PCIE_AUX3 338
-#define CLK_PCIE_AUX4 339
-#define CLK_PIPEPHY0_REF 340
-#define CLK_PIPEPHY1_REF 341
-#define CLK_PIPEPHY2_REF 342
-#define PCLK_PHP_ROOT 343
-#define PCLK_GMAC0 344
-#define PCLK_GMAC1 345
-#define ACLK_PCIE_ROOT 346
-#define ACLK_PHP_ROOT 347
-#define ACLK_PCIE_BRIDGE 348
-#define ACLK_GMAC0 349
-#define ACLK_GMAC1 350
-#define CLK_PMALIVE0 351
-#define CLK_PMALIVE1 352
-#define CLK_PMALIVE2 353
-#define ACLK_SATA0 354
-#define ACLK_SATA1 355
-#define ACLK_SATA2 356
-#define CLK_RXOOB0 357
-#define CLK_RXOOB1 358
-#define CLK_RXOOB2 359
-#define ACLK_USB3OTG2 360
-#define SUSPEND_CLK_USB3OTG2 361
-#define REF_CLK_USB3OTG2 362
-#define CLK_UTMI_OTG2 363
-#define CLK_PIPEPHY0_PIPE_G 364
-#define CLK_PIPEPHY1_PIPE_G 365
-#define CLK_PIPEPHY2_PIPE_G 366
-#define CLK_PIPEPHY0_PIPE_ASIC_G 367
-#define CLK_PIPEPHY1_PIPE_ASIC_G 368
-#define CLK_PIPEPHY2_PIPE_ASIC_G 369
-#define CLK_PIPEPHY2_PIPE_U3_G 370
-#define CLK_PCIE1L2_PIPE 371
-#define CLK_PCIE4L_PIPE 372
-#define CLK_PCIE2L_PIPE 373
-#define PCLK_PCIE_COMBO_PIPE_PHY0 374
-#define PCLK_PCIE_COMBO_PIPE_PHY1 375
-#define PCLK_PCIE_COMBO_PIPE_PHY2 376
-#define PCLK_PCIE_COMBO_PIPE_PHY 377
-#define HCLK_RGA3_1 378
-#define ACLK_RGA3_1 379
-#define CLK_RGA3_1_CORE 380
-#define ACLK_RGA3_ROOT 381
-#define HCLK_RGA3_ROOT 382
-#define ACLK_RKVDEC_CCU 383
-#define HCLK_RKVDEC0 384
-#define ACLK_RKVDEC0 385
-#define CLK_RKVDEC0_CA 386
-#define CLK_RKVDEC0_HEVC_CA 387
-#define CLK_RKVDEC0_CORE 388
-#define HCLK_RKVDEC1 389
-#define ACLK_RKVDEC1 390
-#define CLK_RKVDEC1_CA 391
-#define CLK_RKVDEC1_HEVC_CA 392
-#define CLK_RKVDEC1_CORE 393
-#define HCLK_SDIO 394
-#define CCLK_SRC_SDIO 395
-#define ACLK_USB_ROOT 396
-#define HCLK_USB_ROOT 397
-#define HCLK_HOST0 398
-#define HCLK_HOST_ARB0 399
-#define HCLK_HOST1 400
-#define HCLK_HOST_ARB1 401
-#define ACLK_USB3OTG0 402
-#define SUSPEND_CLK_USB3OTG0 403
-#define REF_CLK_USB3OTG0 404
-#define ACLK_USB3OTG1 405
-#define SUSPEND_CLK_USB3OTG1 406
-#define REF_CLK_USB3OTG1 407
-#define UTMI_OHCI_CLK48_HOST0 408
-#define UTMI_OHCI_CLK48_HOST1 409
-#define HCLK_IEP2P0 410
-#define ACLK_IEP2P0 411
-#define CLK_IEP2P0_CORE 412
-#define ACLK_JPEG_ENCODER0 413
-#define HCLK_JPEG_ENCODER0 414
-#define ACLK_JPEG_ENCODER1 415
-#define HCLK_JPEG_ENCODER1 416
-#define ACLK_JPEG_ENCODER2 417
-#define HCLK_JPEG_ENCODER2 418
-#define ACLK_JPEG_ENCODER3 419
-#define HCLK_JPEG_ENCODER3 420
-#define ACLK_JPEG_DECODER 421
-#define HCLK_JPEG_DECODER 422
-#define HCLK_RGA2 423
-#define ACLK_RGA2 424
-#define CLK_RGA2_CORE 425
-#define HCLK_RGA3_0 426
-#define ACLK_RGA3_0 427
-#define CLK_RGA3_0_CORE 428
-#define ACLK_VDPU_ROOT 429
-#define ACLK_VDPU_LOW_ROOT 430
-#define HCLK_VDPU_ROOT 431
-#define ACLK_JPEG_DECODER_ROOT 432
-#define ACLK_VPU 433
-#define HCLK_VPU 434
-#define HCLK_RKVENC0_ROOT 435
-#define ACLK_RKVENC0_ROOT 436
-#define HCLK_RKVENC0 437
-#define ACLK_RKVENC0 438
-#define CLK_RKVENC0_CORE 439
-#define HCLK_RKVENC1_ROOT 440
-#define ACLK_RKVENC1_ROOT 441
-#define HCLK_RKVENC1 442
-#define ACLK_RKVENC1 443
-#define CLK_RKVENC1_CORE 444
-#define ICLK_CSIHOST01 445
-#define ICLK_CSIHOST0 446
-#define ICLK_CSIHOST1 447
-#define PCLK_CSI_HOST_0 448
-#define PCLK_CSI_HOST_1 449
-#define PCLK_CSI_HOST_2 450
-#define PCLK_CSI_HOST_3 451
-#define PCLK_CSI_HOST_4 452
-#define PCLK_CSI_HOST_5 453
-#define ACLK_FISHEYE0 454
-#define HCLK_FISHEYE0 455
-#define CLK_FISHEYE0_CORE 456
-#define ACLK_FISHEYE1 457
-#define HCLK_FISHEYE1 458
-#define CLK_FISHEYE1_CORE 459
-#define CLK_ISP0_CORE 460
-#define CLK_ISP0_CORE_MARVIN 461
-#define CLK_ISP0_CORE_VICAP 462
-#define ACLK_ISP0 463
-#define HCLK_ISP0 464
-#define ACLK_VI_ROOT 465
-#define HCLK_VI_ROOT 466
-#define PCLK_VI_ROOT 467
-#define DCLK_VICAP 468
-#define ACLK_VICAP 469
-#define HCLK_VICAP 470
-#define PCLK_DP0 471
-#define PCLK_DP1 472
-#define PCLK_S_DP0 473
-#define PCLK_S_DP1 474
-#define CLK_DP0 475
-#define CLK_DP1 476
-#define HCLK_HDCP_KEY0 477
-#define ACLK_HDCP0 478
-#define HCLK_HDCP0 479
-#define PCLK_HDCP0 480
-#define HCLK_I2S4_8CH 481
-#define ACLK_TRNG0 482
-#define PCLK_TRNG0 483
-#define ACLK_VO0_ROOT 484
-#define HCLK_VO0_ROOT 485
-#define HCLK_VO0_S_ROOT 486
-#define PCLK_VO0_ROOT 487
-#define PCLK_VO0_S_ROOT 488
-#define PCLK_VO0GRF 489
-#define CLK_I2S4_8CH_TX_SRC 490
-#define CLK_I2S4_8CH_TX_FRAC 491
-#define MCLK_I2S4_8CH_TX 492
-#define CLK_I2S4_8CH_TX 493
-#define HCLK_I2S8_8CH 494
-#define CLK_I2S8_8CH_TX_SRC 495
-#define CLK_I2S8_8CH_TX_FRAC 496
-#define MCLK_I2S8_8CH_TX 497
-#define CLK_I2S8_8CH_TX 498
-#define HCLK_SPDIF2_DP0 499
-#define CLK_SPDIF2_DP0_SRC 500
-#define CLK_SPDIF2_DP0_FRAC 501
-#define MCLK_SPDIF2_DP0 502
-#define CLK_SPDIF2_DP0 503
-#define MCLK_SPDIF2 504
-#define HCLK_SPDIF5_DP1 505
-#define CLK_SPDIF5_DP1_SRC 506
-#define CLK_SPDIF5_DP1_FRAC 507
-#define MCLK_SPDIF5_DP1 508
-#define CLK_SPDIF5_DP1 509
-#define MCLK_SPDIF5 510
-#define PCLK_EDP0 511
-#define CLK_EDP0_24M 512
-#define CLK_EDP0_200M 513
-#define PCLK_EDP1 514
-#define CLK_EDP1_24M 515
-#define CLK_EDP1_200M 516
-#define HCLK_HDCP_KEY1 517
-#define ACLK_HDCP1 518
-#define HCLK_HDCP1 519
-#define PCLK_HDCP1 520
-#define ACLK_HDMIRX 521
-#define PCLK_HDMIRX 522
-#define CLK_HDMIRX_REF 523
-#define CLK_HDMIRX_AUD_SRC 524
-#define CLK_HDMIRX_AUD_FRAC 525
-#define CLK_HDMIRX_AUD 526
-#define CLK_HDMIRX_AUD_P_MUX 527
-#define PCLK_HDMITX0 528
-#define CLK_HDMITX0_EARC 529
-#define CLK_HDMITX0_REF 530
-#define PCLK_HDMITX1 531
-#define CLK_HDMITX1_EARC 532
-#define CLK_HDMITX1_REF 533
-#define CLK_HDMITRX_REFSRC 534
-#define ACLK_TRNG1 535
-#define PCLK_TRNG1 536
-#define ACLK_HDCP1_ROOT 537
-#define ACLK_HDMIRX_ROOT 538
-#define HCLK_VO1_ROOT 539
-#define HCLK_VO1_S_ROOT 540
-#define PCLK_VO1_ROOT 541
-#define PCLK_VO1_S_ROOT 542
-#define PCLK_S_EDP0 543
-#define PCLK_S_EDP1 544
-#define PCLK_S_HDMIRX 545
-#define HCLK_I2S10_8CH 546
-#define CLK_I2S10_8CH_RX_SRC 547
-#define CLK_I2S10_8CH_RX_FRAC 548
-#define CLK_I2S10_8CH_RX 549
-#define MCLK_I2S10_8CH_RX 550
-#define HCLK_I2S7_8CH 551
-#define CLK_I2S7_8CH_RX_SRC 552
-#define CLK_I2S7_8CH_RX_FRAC 553
-#define CLK_I2S7_8CH_RX 554
-#define MCLK_I2S7_8CH_RX 555
-#define HCLK_I2S9_8CH 556
-#define CLK_I2S9_8CH_RX_SRC 557
-#define CLK_I2S9_8CH_RX_FRAC 558
-#define CLK_I2S9_8CH_RX 559
-#define MCLK_I2S9_8CH_RX 560
-#define CLK_I2S5_8CH_TX_SRC 561
-#define CLK_I2S5_8CH_TX_FRAC 562
-#define CLK_I2S5_8CH_TX 563
-#define MCLK_I2S5_8CH_TX 564
-#define HCLK_I2S5_8CH 565
-#define CLK_I2S6_8CH_TX_SRC 566
-#define CLK_I2S6_8CH_TX_FRAC 567
-#define CLK_I2S6_8CH_TX 568
-#define MCLK_I2S6_8CH_TX 569
-#define CLK_I2S6_8CH_RX_SRC 570
-#define CLK_I2S6_8CH_RX_FRAC 571
-#define CLK_I2S6_8CH_RX 572
-#define MCLK_I2S6_8CH_RX 573
-#define I2S6_8CH_MCLKOUT 574
-#define HCLK_I2S6_8CH 575
-#define HCLK_SPDIF3 576
-#define CLK_SPDIF3_SRC 577
-#define CLK_SPDIF3_FRAC 578
-#define CLK_SPDIF3 579
-#define MCLK_SPDIF3 580
-#define HCLK_SPDIF4 581
-#define CLK_SPDIF4_SRC 582
-#define CLK_SPDIF4_FRAC 583
-#define CLK_SPDIF4 584
-#define MCLK_SPDIF4 585
-#define HCLK_SPDIFRX0 586
-#define MCLK_SPDIFRX0 587
-#define HCLK_SPDIFRX1 588
-#define MCLK_SPDIFRX1 589
-#define HCLK_SPDIFRX2 590
-#define MCLK_SPDIFRX2 591
-#define ACLK_VO1USB_TOP_ROOT 592
-#define HCLK_VO1USB_TOP_ROOT 593
-#define CLK_HDMIHDP0 594
-#define CLK_HDMIHDP1 595
-#define PCLK_HDPTX0 596
-#define PCLK_HDPTX1 597
-#define PCLK_USBDPPHY0 598
-#define PCLK_USBDPPHY1 599
-#define ACLK_VOP_ROOT 600
-#define ACLK_VOP_LOW_ROOT 601
-#define HCLK_VOP_ROOT 602
-#define PCLK_VOP_ROOT 603
-#define HCLK_VOP 604
-#define ACLK_VOP 605
-#define DCLK_VOP0_SRC 606
-#define DCLK_VOP1_SRC 607
-#define DCLK_VOP2_SRC 608
-#define DCLK_VOP0 609
-#define DCLK_VOP1 610
-#define DCLK_VOP2 611
-#define DCLK_VOP3 612
-#define PCLK_DSIHOST0 613
-#define PCLK_DSIHOST1 614
-#define CLK_DSIHOST0 615
-#define CLK_DSIHOST1 616
-#define CLK_VOP_PMU 617
-#define ACLK_VOP_DOBY 618
-#define ACLK_VOP_SUB_SRC 619
-#define CLK_USBDP_PHY0_IMMORTAL 620
-#define CLK_USBDP_PHY1_IMMORTAL 621
-#define CLK_PMU0 622
-#define PCLK_PMU0 623
-#define PCLK_PMU0IOC 624
-#define PCLK_GPIO0 625
-#define DBCLK_GPIO0 626
-#define PCLK_I2C0 627
-#define CLK_I2C0 628
-#define HCLK_I2S1_8CH 629
-#define CLK_I2S1_8CH_TX_SRC 630
-#define CLK_I2S1_8CH_TX_FRAC 631
-#define CLK_I2S1_8CH_TX 632
-#define MCLK_I2S1_8CH_TX 633
-#define CLK_I2S1_8CH_RX_SRC 634
-#define CLK_I2S1_8CH_RX_FRAC 635
-#define CLK_I2S1_8CH_RX 636
-#define MCLK_I2S1_8CH_RX 637
-#define I2S1_8CH_MCLKOUT 638
-#define CLK_PMU1_50M_SRC 639
-#define CLK_PMU1_100M_SRC 640
-#define CLK_PMU1_200M_SRC 641
-#define CLK_PMU1_300M_SRC 642
-#define CLK_PMU1_400M_SRC 643
-#define HCLK_PMU1_ROOT 644
-#define PCLK_PMU1_ROOT 645
-#define PCLK_PMU0_ROOT 646
-#define HCLK_PMU_CM0_ROOT 647
-#define PCLK_PMU1 648
-#define CLK_DDR_FAIL_SAFE 649
-#define CLK_PMU1 650
-#define HCLK_PDM0 651
-#define MCLK_PDM0 652
-#define HCLK_VAD 653
-#define FCLK_PMU_CM0_CORE 654
-#define CLK_PMU_CM0_RTC 655
-#define PCLK_PMU1_IOC 656
-#define PCLK_PMU1PWM 657
-#define CLK_PMU1PWM 658
-#define CLK_PMU1PWM_CAPTURE 659
-#define PCLK_PMU1TIMER 660
-#define CLK_PMU1TIMER_ROOT 661
-#define CLK_PMU1TIMER0 662
-#define CLK_PMU1TIMER1 663
-#define CLK_UART0_SRC 664
-#define CLK_UART0_FRAC 665
-#define CLK_UART0 666
-#define SCLK_UART0 667
-#define PCLK_UART0 668
-#define PCLK_PMU1WDT 669
-#define TCLK_PMU1WDT 670
-#define CLK_CR_PARA 671
-#define CLK_USB2PHY_HDPTXRXPHY_REF 672
-#define CLK_USBDPPHY_MIPIDCPPHY_REF 673
-#define CLK_REF_PIPE_PHY0_OSC_SRC 674
-#define CLK_REF_PIPE_PHY1_OSC_SRC 675
-#define CLK_REF_PIPE_PHY2_OSC_SRC 676
-#define CLK_REF_PIPE_PHY0_PLL_SRC 677
-#define CLK_REF_PIPE_PHY1_PLL_SRC 678
-#define CLK_REF_PIPE_PHY2_PLL_SRC 679
-#define CLK_REF_PIPE_PHY0 680
-#define CLK_REF_PIPE_PHY1 681
-#define CLK_REF_PIPE_PHY2 682
-#define SCLK_SDIO_DRV 683
-#define SCLK_SDIO_SAMPLE 684
-#define SCLK_SDMMC_DRV 685
-#define SCLK_SDMMC_SAMPLE 686
-#define CLK_PCIE1L0_PIPE 687
-#define CLK_PCIE1L1_PIPE 688
-#define CLK_BIGCORE0_PVTM 689
-#define CLK_CORE_BIGCORE0_PVTM 690
-#define CLK_BIGCORE1_PVTM 691
-#define CLK_CORE_BIGCORE1_PVTM 692
-#define CLK_LITCORE_PVTM 693
-#define CLK_CORE_LITCORE_PVTM 694
-#define CLK_AUX16M_0 695
-#define CLK_AUX16M_1 696
-#define CLK_PHY0_REF_ALT_P 697
-#define CLK_PHY0_REF_ALT_M 698
-#define CLK_PHY1_REF_ALT_P 699
-#define CLK_PHY1_REF_ALT_M 700
-#define ACLK_ISP1_PRE 701
-#define HCLK_ISP1_PRE 702
-#define HCLK_NVM 703
-#define ACLK_USB 704
-#define HCLK_USB 705
-#define ACLK_JPEG_DECODER_PRE 706
-#define ACLK_VDPU_LOW_PRE 707
-#define ACLK_RKVENC1_PRE 708
-#define HCLK_RKVENC1_PRE 709
-#define HCLK_RKVDEC0_PRE 710
-#define ACLK_RKVDEC0_PRE 711
-#define HCLK_RKVDEC1_PRE 712
-#define ACLK_RKVDEC1_PRE 713
-#define ACLK_HDCP0_PRE 714
-#define HCLK_VO0 715
-#define ACLK_HDCP1_PRE 716
-#define HCLK_VO1 717
-#define ACLK_AV1_PRE 718
-#define PCLK_AV1_PRE 719
-#define HCLK_SDIO_PRE 720
-
-#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1)
-
-/* scmi-clocks indices */
-
-#define SCMI_CLK_CPUL 0
-#define SCMI_CLK_DSU 1
-#define SCMI_CLK_CPUB01 2
-#define SCMI_CLK_CPUB23 3
-#define SCMI_CLK_DDR 4
-#define SCMI_CLK_GPU 5
-#define SCMI_CLK_NPU 6
-#define SCMI_CLK_SBUS 7
-#define SCMI_PCLK_SBUS 8
-#define SCMI_CCLK_SD 9
-#define SCMI_DCLK_SD 10
-#define SCMI_ACLK_SECURE_NS 11
-#define SCMI_HCLK_SECURE_NS 12
-#define SCMI_TCLK_WDT 13
-#define SCMI_KEYLADDER_CORE 14
-#define SCMI_KEYLADDER_RNG 15
-#define SCMI_ACLK_SECURE_S 16
-#define SCMI_HCLK_SECURE_S 17
-#define SCMI_PCLK_SECURE_S 18
-#define SCMI_CRYPTO_RNG 19
-#define SCMI_CRYPTO_CORE 20
-#define SCMI_CRYPTO_PKA 21
-#define SCMI_SPLL 22
-#define SCMI_HCLK_SD 23
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
- * Author: Finley Xiao <finley.xiao@rock-chips.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
-
-/* pmucru-clocks indices */
-
-/* pll clocks */
-#define PLL_GPLL 1
-
-/* sclk (special clocks) */
-#define CLK_OSC0_DIV32K 2
-#define CLK_RTC32K 3
-#define CLK_WIFI_DIV 4
-#define CLK_WIFI_OSC0 5
-#define CLK_WIFI 6
-#define CLK_PMU 7
-#define SCLK_UART1_DIV 8
-#define SCLK_UART1_FRACDIV 9
-#define SCLK_UART1_MUX 10
-#define SCLK_UART1 11
-#define CLK_I2C0 12
-#define CLK_I2C2 13
-#define CLK_CAPTURE_PWM0 14
-#define CLK_PWM0 15
-#define CLK_CAPTURE_PWM1 16
-#define CLK_PWM1 17
-#define CLK_SPI0 18
-#define DBCLK_GPIO0 19
-#define CLK_PMUPVTM 20
-#define CLK_CORE_PMUPVTM 21
-#define CLK_REF12M 22
-#define CLK_USBPHY_OTG_REF 23
-#define CLK_USBPHY_HOST_REF 24
-#define CLK_REF24M 25
-#define CLK_MIPIDSIPHY_REF 26
-
-/* pclk */
-#define PCLK_PDPMU 30
-#define PCLK_PMU 31
-#define PCLK_UART1 32
-#define PCLK_I2C0 33
-#define PCLK_I2C2 34
-#define PCLK_PWM0 35
-#define PCLK_PWM1 36
-#define PCLK_SPI0 37
-#define PCLK_GPIO0 38
-#define PCLK_PMUSGRF 39
-#define PCLK_PMUGRF 40
-#define PCLK_PMUCRU 41
-#define PCLK_CHIPVEROTP 42
-#define PCLK_PDPMU_NIU 43
-#define PCLK_PMUPVTM 44
-#define PCLK_SCRKEYGEN 45
-
-#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)
-
-/* cru-clocks indices */
-
-/* pll clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_CPLL 3
-#define PLL_HPLL 4
-
-/* sclk (special clocks) */
-#define ARMCLK 5
-#define USB480M 6
-#define CLK_CORE_CPUPVTM 7
-#define CLK_CPUPVTM 8
-#define CLK_SCR1 9
-#define CLK_SCR1_CORE 10
-#define CLK_SCR1_RTC 11
-#define CLK_SCR1_JTAG 12
-#define SCLK_UART0_DIV 13
-#define SCLK_UART0_FRAC 14
-#define SCLK_UART0_MUX 15
-#define SCLK_UART0 16
-#define SCLK_UART2_DIV 17
-#define SCLK_UART2_FRAC 18
-#define SCLK_UART2_MUX 19
-#define SCLK_UART2 20
-#define SCLK_UART3_DIV 21
-#define SCLK_UART3_FRAC 22
-#define SCLK_UART3_MUX 23
-#define SCLK_UART3 24
-#define SCLK_UART4_DIV 25
-#define SCLK_UART4_FRAC 26
-#define SCLK_UART4_MUX 27
-#define SCLK_UART4 28
-#define SCLK_UART5_DIV 29
-#define SCLK_UART5_FRAC 30
-#define SCLK_UART5_MUX 31
-#define SCLK_UART5 32
-#define CLK_I2C1 33
-#define CLK_I2C3 34
-#define CLK_I2C4 35
-#define CLK_I2C5 36
-#define CLK_SPI1 37
-#define CLK_CAPTURE_PWM2 38
-#define CLK_PWM2 39
-#define DBCLK_GPIO1 40
-#define DBCLK_GPIO2 41
-#define DBCLK_GPIO3 42
-#define DBCLK_GPIO4 43
-#define CLK_SARADC 44
-#define CLK_TIMER0 45
-#define CLK_TIMER1 46
-#define CLK_TIMER2 47
-#define CLK_TIMER3 48
-#define CLK_TIMER4 49
-#define CLK_TIMER5 50
-#define CLK_CAN 51
-#define CLK_NPU_TSADC 52
-#define CLK_NPU_TSADCPHY 53
-#define CLK_CPU_TSADC 54
-#define CLK_CPU_TSADCPHY 55
-#define CLK_CRYPTO_CORE 56
-#define CLK_CRYPTO_PKA 57
-#define MCLK_I2S0_TX_DIV 58
-#define MCLK_I2S0_TX_FRACDIV 59
-#define MCLK_I2S0_TX_MUX 60
-#define MCLK_I2S0_TX 61
-#define MCLK_I2S0_RX_DIV 62
-#define MCLK_I2S0_RX_FRACDIV 63
-#define MCLK_I2S0_RX_MUX 64
-#define MCLK_I2S0_RX 65
-#define MCLK_I2S0_TX_OUT2IO 66
-#define MCLK_I2S0_RX_OUT2IO 67
-#define MCLK_I2S1_DIV 68
-#define MCLK_I2S1_FRACDIV 69
-#define MCLK_I2S1_MUX 70
-#define MCLK_I2S1 71
-#define MCLK_I2S1_OUT2IO 72
-#define MCLK_I2S2_DIV 73
-#define MCLK_I2S2_FRACDIV 74
-#define MCLK_I2S2_MUX 75
-#define MCLK_I2S2 76
-#define MCLK_I2S2_OUT2IO 77
-#define MCLK_PDM 78
-#define SCLK_ADUPWM_DIV 79
-#define SCLK_AUDPWM_FRACDIV 80
-#define SCLK_AUDPWM_MUX 81
-#define SCLK_AUDPWM 82
-#define CLK_ACDCDIG_ADC 83
-#define CLK_ACDCDIG_DAC 84
-#define CLK_ACDCDIG_I2C 85
-#define CLK_VENC_CORE 86
-#define CLK_VDEC_CORE 87
-#define CLK_VDEC_CA 88
-#define CLK_VDEC_HEVC_CA 89
-#define CLK_RGA_CORE 90
-#define CLK_IEP_CORE 91
-#define CLK_ISP_DIV 92
-#define CLK_ISP_NP5 93
-#define CLK_ISP_NUX 94
-#define CLK_ISP 95
-#define CLK_CIF_OUT_DIV 96
-#define CLK_CIF_OUT_FRACDIV 97
-#define CLK_CIF_OUT_MUX 98
-#define CLK_CIF_OUT 99
-#define CLK_MIPICSI_OUT_DIV 100
-#define CLK_MIPICSI_OUT_FRACDIV 101
-#define CLK_MIPICSI_OUT_MUX 102
-#define CLK_MIPICSI_OUT 103
-#define CLK_ISPP_DIV 104
-#define CLK_ISPP_NP5 105
-#define CLK_ISPP_NUX 106
-#define CLK_ISPP 107
-#define CLK_SDMMC 108
-#define SCLK_SDMMC_DRV 109
-#define SCLK_SDMMC_SAMPLE 110
-#define CLK_SDIO 111
-#define SCLK_SDIO_DRV 112
-#define SCLK_SDIO_SAMPLE 113
-#define CLK_EMMC 114
-#define SCLK_EMMC_DRV 115
-#define SCLK_EMMC_SAMPLE 116
-#define CLK_NANDC 117
-#define SCLK_SFC 118
-#define CLK_USBHOST_UTMI_OHCI 119
-#define CLK_USBOTG_REF 120
-#define CLK_GMAC_DIV 121
-#define CLK_GMAC_RGMII_M0 122
-#define CLK_GMAC_SRC_M0 123
-#define CLK_GMAC_RGMII_M1 124
-#define CLK_GMAC_SRC_M1 125
-#define CLK_GMAC_SRC 126
-#define CLK_GMAC_REF 127
-#define CLK_GMAC_TX_SRC 128
-#define CLK_GMAC_TX_DIV5 129
-#define CLK_GMAC_TX_DIV50 130
-#define RGMII_MODE_CLK 131
-#define CLK_GMAC_RX_SRC 132
-#define CLK_GMAC_RX_DIV2 133
-#define CLK_GMAC_RX_DIV20 134
-#define RMII_MODE_CLK 135
-#define CLK_GMAC_TX_RX 136
-#define CLK_GMAC_PTPREF 137
-#define CLK_GMAC_ETHERNET_OUT 138
-#define CLK_DDRPHY 139
-#define CLK_DDR_MON 140
-#define TMCLK_DDR_MON 141
-#define CLK_NPU_DIV 142
-#define CLK_NPU_NP5 143
-#define CLK_CORE_NPU 144
-#define CLK_CORE_NPUPVTM 145
-#define CLK_NPUPVTM 146
-#define SCLK_DDRCLK 147
-#define CLK_OTP 148
-
-/* dclk */
-#define DCLK_DECOM 150
-#define DCLK_VOP_DIV 151
-#define DCLK_VOP_FRACDIV 152
-#define DCLK_VOP_MUX 153
-#define DCLK_VOP 154
-#define DCLK_CIF 155
-#define DCLK_CIFLITE 156
-
-/* aclk */
-#define ACLK_PDBUS 160
-#define ACLK_DMAC 161
-#define ACLK_DCF 162
-#define ACLK_SPINLOCK 163
-#define ACLK_DECOM 164
-#define ACLK_PDCRYPTO 165
-#define ACLK_CRYPTO 166
-#define ACLK_PDVEPU 167
-#define ACLK_VENC 168
-#define ACLK_PDVDEC 169
-#define ACLK_PDJPEG 170
-#define ACLK_VDEC 171
-#define ACLK_JPEG 172
-#define ACLK_PDVO 173
-#define ACLK_RGA 174
-#define ACLK_VOP 175
-#define ACLK_IEP 176
-#define ACLK_PDVI_DIV 177
-#define ACLK_PDVI_NP5 178
-#define ACLK_PDVI 179
-#define ACLK_ISP 180
-#define ACLK_CIF 181
-#define ACLK_CIFLITE 182
-#define ACLK_PDISPP_DIV 183
-#define ACLK_PDISPP_NP5 184
-#define ACLK_PDISPP 185
-#define ACLK_ISPP 186
-#define ACLK_PDPHP 187
-#define ACLK_PDUSB 188
-#define ACLK_USBOTG 189
-#define ACLK_PDGMAC 190
-#define ACLK_GMAC 191
-#define ACLK_PDNPU_DIV 192
-#define ACLK_PDNPU_NP5 193
-#define ACLK_PDNPU 194
-#define ACLK_NPU 195
-
-/* hclk */
-#define HCLK_PDCORE_NIU 200
-#define HCLK_PDUSB 201
-#define HCLK_PDCRYPTO 202
-#define HCLK_CRYPTO 203
-#define HCLK_PDAUDIO 204
-#define HCLK_I2S0 205
-#define HCLK_I2S1 206
-#define HCLK_I2S2 207
-#define HCLK_PDM 208
-#define HCLK_AUDPWM 209
-#define HCLK_PDVEPU 210
-#define HCLK_VENC 211
-#define HCLK_PDVDEC 212
-#define HCLK_PDJPEG 213
-#define HCLK_VDEC 214
-#define HCLK_JPEG 215
-#define HCLK_PDVO 216
-#define HCLK_RGA 217
-#define HCLK_VOP 218
-#define HCLK_IEP 219
-#define HCLK_PDVI 220
-#define HCLK_ISP 221
-#define HCLK_CIF 222
-#define HCLK_CIFLITE 223
-#define HCLK_PDISPP 224
-#define HCLK_ISPP 225
-#define HCLK_PDPHP 226
-#define HCLK_PDSDMMC 227
-#define HCLK_SDMMC 228
-#define HCLK_PDSDIO 229
-#define HCLK_SDIO 230
-#define HCLK_PDNVM 231
-#define HCLK_EMMC 232
-#define HCLK_NANDC 233
-#define HCLK_SFC 234
-#define HCLK_SFCXIP 235
-#define HCLK_PDBUS 236
-#define HCLK_USBHOST 237
-#define HCLK_USBHOST_ARB 238
-#define HCLK_PDNPU 239
-#define HCLK_NPU 240
-
-/* pclk */
-#define PCLK_CPUPVTM 245
-#define PCLK_PDBUS 246
-#define PCLK_DCF 247
-#define PCLK_WDT 248
-#define PCLK_MAILBOX 249
-#define PCLK_UART0 250
-#define PCLK_UART2 251
-#define PCLK_UART3 252
-#define PCLK_UART4 253
-#define PCLK_UART5 254
-#define PCLK_I2C1 255
-#define PCLK_I2C3 256
-#define PCLK_I2C4 257
-#define PCLK_I2C5 258
-#define PCLK_SPI1 259
-#define PCLK_PWM2 261
-#define PCLK_GPIO1 262
-#define PCLK_GPIO2 263
-#define PCLK_GPIO3 264
-#define PCLK_GPIO4 265
-#define PCLK_SARADC 266
-#define PCLK_TIMER 267
-#define PCLK_DECOM 268
-#define PCLK_CAN 269
-#define PCLK_NPU_TSADC 270
-#define PCLK_CPU_TSADC 271
-#define PCLK_ACDCDIG 272
-#define PCLK_PDVO 273
-#define PCLK_DSIHOST 274
-#define PCLK_PDVI 275
-#define PCLK_CSIHOST 276
-#define PCLK_PDGMAC 277
-#define PCLK_GMAC 278
-#define PCLK_PDDDR 279
-#define PCLK_DDR_MON 280
-#define PCLK_PDNPU 281
-#define PCLK_NPUPVTM 282
-#define PCLK_PDTOP 283
-#define PCLK_TOPCRU 284
-#define PCLK_TOPGRF 285
-#define PCLK_CPUEMADET 286
-#define PCLK_DDRPHY 287
-#define PCLK_DSIPHY 289
-#define PCLK_CSIPHY0 290
-#define PCLK_CSIPHY1 291
-#define PCLK_USBPHY_HOST 292
-#define PCLK_USBPHY_OTG 293
-#define PCLK_OTP 294
-
-#define CLK_NR_CLKS (PCLK_OTP + 1)
-
-/* pmu soft-reset indices */
-
-/* pmu_cru_softrst_con0 */
-#define SRST_PDPMU_NIU_P 0
-#define SRST_PMU_SGRF_P 1
-#define SRST_PMU_SGRF_REMAP_P 2
-#define SRST_I2C0_P 3
-#define SRST_I2C0 4
-#define SRST_I2C2_P 7
-#define SRST_I2C2 8
-#define SRST_UART1_P 9
-#define SRST_UART1 10
-#define SRST_PWM0_P 11
-#define SRST_PWM0 12
-#define SRST_PWM1_P 13
-#define SRST_PWM1 14
-#define SRST_DDR_FAIL_SAFE 15
-
-/* pmu_cru_softrst_con1 */
-#define SRST_GPIO0_P 17
-#define SRST_GPIO0_DB 18
-#define SRST_SPI0_P 19
-#define SRST_SPI0 20
-#define SRST_PMUGRF_P 21
-#define SRST_CHIPVEROTP_P 22
-#define SRST_PMUPVTM 24
-#define SRST_PMUPVTM_P 25
-#define SRST_PMUCRU_P 30
-
-/* soft-reset indices */
-
-/* cru_softrst_con0 */
-#define SRST_CORE0_PO 0
-#define SRST_CORE1_PO 1
-#define SRST_CORE2_PO 2
-#define SRST_CORE3_PO 3
-#define SRST_CORE0 4
-#define SRST_CORE1 5
-#define SRST_CORE2 6
-#define SRST_CORE3 7
-#define SRST_CORE0_DBG 8
-#define SRST_CORE1_DBG 9
-#define SRST_CORE2_DBG 10
-#define SRST_CORE3_DBG 11
-#define SRST_NL2 12
-#define SRST_CORE_NIU_A 13
-#define SRST_DBG_DAPLITE_P 14
-#define SRST_DAPLITE_P 15
-
-/* cru_softrst_con1 */
-#define SRST_PDBUS_NIU1_A 16
-#define SRST_PDBUS_NIU1_H 17
-#define SRST_PDBUS_NIU1_P 18
-#define SRST_PDBUS_NIU2_A 19
-#define SRST_PDBUS_NIU2_H 20
-#define SRST_PDBUS_NIU3_A 21
-#define SRST_PDBUS_NIU3_H 22
-#define SRST_PDBUS_HOLD_NIU1_A 23
-#define SRST_DBG_NIU_P 24
-#define SRST_PDCORE_NIIU_H 25
-#define SRST_MUC_NIU 26
-#define SRST_DCF_A 29
-#define SRST_DCF_P 30
-#define SRST_SYSTEM_SRAM_A 31
-
-/* cru_softrst_con2 */
-#define SRST_I2C1_P 32
-#define SRST_I2C1 33
-#define SRST_I2C3_P 34
-#define SRST_I2C3 35
-#define SRST_I2C4_P 36
-#define SRST_I2C4 37
-#define SRST_I2C5_P 38
-#define SRST_I2C5 39
-#define SRST_SPI1_P 40
-#define SRST_SPI1 41
-#define SRST_MCU_CORE 42
-#define SRST_PWM2_P 44
-#define SRST_PWM2 45
-#define SRST_SPINLOCK_A 46
-
-/* cru_softrst_con3 */
-#define SRST_UART0_P 48
-#define SRST_UART0 49
-#define SRST_UART2_P 50
-#define SRST_UART2 51
-#define SRST_UART3_P 52
-#define SRST_UART3 53
-#define SRST_UART4_P 54
-#define SRST_UART4 55
-#define SRST_UART5_P 56
-#define SRST_UART5 57
-#define SRST_WDT_P 58
-#define SRST_SARADC_P 59
-#define SRST_GRF_P 61
-#define SRST_TIMER_P 62
-#define SRST_MAILBOX_P 63
-
-/* cru_softrst_con4 */
-#define SRST_TIMER0 64
-#define SRST_TIMER1 65
-#define SRST_TIMER2 66
-#define SRST_TIMER3 67
-#define SRST_TIMER4 68
-#define SRST_TIMER5 69
-#define SRST_INTMUX_P 70
-#define SRST_GPIO1_P 72
-#define SRST_GPIO1_DB 73
-#define SRST_GPIO2_P 74
-#define SRST_GPIO2_DB 75
-#define SRST_GPIO3_P 76
-#define SRST_GPIO3_DB 77
-#define SRST_GPIO4_P 78
-#define SRST_GPIO4_DB 79
-
-/* cru_softrst_con5 */
-#define SRST_CAN_P 80
-#define SRST_CAN 81
-#define SRST_DECOM_A 85
-#define SRST_DECOM_P 86
-#define SRST_DECOM_D 87
-#define SRST_PDCRYPTO_NIU_A 88
-#define SRST_PDCRYPTO_NIU_H 89
-#define SRST_CRYPTO_A 90
-#define SRST_CRYPTO_H 91
-#define SRST_CRYPTO_CORE 92
-#define SRST_CRYPTO_PKA 93
-#define SRST_SGRF_P 95
-
-/* cru_softrst_con6 */
-#define SRST_PDAUDIO_NIU_H 96
-#define SRST_PDAUDIO_NIU_P 97
-#define SRST_I2S0_H 98
-#define SRST_I2S0_TX_M 99
-#define SRST_I2S0_RX_M 100
-#define SRST_I2S1_H 101
-#define SRST_I2S1_M 102
-#define SRST_I2S2_H 103
-#define SRST_I2S2_M 104
-#define SRST_PDM_H 105
-#define SRST_PDM_M 106
-#define SRST_AUDPWM_H 107
-#define SRST_AUDPWM 108
-#define SRST_ACDCDIG_P 109
-#define SRST_ACDCDIG 110
-
-/* cru_softrst_con7 */
-#define SRST_PDVEPU_NIU_A 112
-#define SRST_PDVEPU_NIU_H 113
-#define SRST_VENC_A 114
-#define SRST_VENC_H 115
-#define SRST_VENC_CORE 116
-#define SRST_PDVDEC_NIU_A 117
-#define SRST_PDVDEC_NIU_H 118
-#define SRST_VDEC_A 119
-#define SRST_VDEC_H 120
-#define SRST_VDEC_CORE 121
-#define SRST_VDEC_CA 122
-#define SRST_VDEC_HEVC_CA 123
-#define SRST_PDJPEG_NIU_A 124
-#define SRST_PDJPEG_NIU_H 125
-#define SRST_JPEG_A 126
-#define SRST_JPEG_H 127
-
-/* cru_softrst_con8 */
-#define SRST_PDVO_NIU_A 128
-#define SRST_PDVO_NIU_H 129
-#define SRST_PDVO_NIU_P 130
-#define SRST_RGA_A 131
-#define SRST_RGA_H 132
-#define SRST_RGA_CORE 133
-#define SRST_VOP_A 134
-#define SRST_VOP_H 135
-#define SRST_VOP_D 136
-#define SRST_TXBYTEHS_DSIHOST 137
-#define SRST_DSIHOST_P 138
-#define SRST_IEP_A 139
-#define SRST_IEP_H 140
-#define SRST_IEP_CORE 141
-#define SRST_ISP_RX_P 142
-
-/* cru_softrst_con9 */
-#define SRST_PDVI_NIU_A 144
-#define SRST_PDVI_NIU_H 145
-#define SRST_PDVI_NIU_P 146
-#define SRST_ISP 147
-#define SRST_CIF_A 148
-#define SRST_CIF_H 149
-#define SRST_CIF_D 150
-#define SRST_CIF_P 151
-#define SRST_CIF_I 152
-#define SRST_CIF_RX_P 153
-#define SRST_PDISPP_NIU_A 154
-#define SRST_PDISPP_NIU_H 155
-#define SRST_ISPP_A 156
-#define SRST_ISPP_H 157
-#define SRST_ISPP 158
-#define SRST_CSIHOST_P 159
-
-/* cru_softrst_con10 */
-#define SRST_PDPHPMID_NIU_A 160
-#define SRST_PDPHPMID_NIU_H 161
-#define SRST_PDNVM_NIU_H 163
-#define SRST_SDMMC_H 164
-#define SRST_SDIO_H 165
-#define SRST_EMMC_H 166
-#define SRST_SFC_H 167
-#define SRST_SFCXIP_H 168
-#define SRST_SFC 169
-#define SRST_NANDC_H 170
-#define SRST_NANDC 171
-#define SRST_PDSDMMC_H 173
-#define SRST_PDSDIO_H 174
-
-/* cru_softrst_con11 */
-#define SRST_PDUSB_NIU_A 176
-#define SRST_PDUSB_NIU_H 177
-#define SRST_USBHOST_H 178
-#define SRST_USBHOST_ARB_H 179
-#define SRST_USBHOST_UTMI 180
-#define SRST_USBOTG_A 181
-#define SRST_USBPHY_OTG_P 182
-#define SRST_USBPHY_HOST_P 183
-#define SRST_USBPHYPOR_OTG 184
-#define SRST_USBPHYPOR_HOST 185
-#define SRST_PDGMAC_NIU_A 188
-#define SRST_PDGMAC_NIU_P 189
-#define SRST_GMAC_A 190
-
-/* cru_softrst_con12 */
-#define SRST_DDR_DFICTL_P 193
-#define SRST_DDR_MON_P 194
-#define SRST_DDR_STANDBY_P 195
-#define SRST_DDR_GRF_P 196
-#define SRST_DDR_MSCH_P 197
-#define SRST_DDR_SPLIT_A 198
-#define SRST_DDR_MSCH 199
-#define SRST_DDR_DFICTL 202
-#define SRST_DDR_STANDBY 203
-#define SRST_NPUMCU_NIU 205
-#define SRST_DDRPHY_P 206
-#define SRST_DDRPHY 207
-
-/* cru_softrst_con13 */
-#define SRST_PDNPU_NIU_A 208
-#define SRST_PDNPU_NIU_H 209
-#define SRST_PDNPU_NIU_P 210
-#define SRST_NPU_A 211
-#define SRST_NPU_H 212
-#define SRST_NPU 213
-#define SRST_NPUPVTM_P 214
-#define SRST_NPUPVTM 215
-#define SRST_NPU_TSADC_P 216
-#define SRST_NPU_TSADC 217
-#define SRST_NPU_TSADCPHY 218
-#define SRST_CIFLITE_A 220
-#define SRST_CIFLITE_H 221
-#define SRST_CIFLITE_D 222
-#define SRST_CIFLITE_RX_P 223
-
-/* cru_softrst_con14 */
-#define SRST_TOPNIU_P 224
-#define SRST_TOPCRU_P 225
-#define SRST_TOPGRF_P 226
-#define SRST_CPUEMADET_P 227
-#define SRST_CSIPHY0_P 228
-#define SRST_CSIPHY1_P 229
-#define SRST_DSIPHY_P 230
-#define SRST_CPU_TSADC_P 232
-#define SRST_CPU_TSADC 233
-#define SRST_CPU_TSADCPHY 234
-#define SRST_CPUPVTM_P 235
-#define SRST_CPUPVTM 236
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
- * Author: Shawn Lin <shawn.lin@rock-chips.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
-
-/* pll id */
-#define PLL_APLL 0
-#define PLL_DPLL 1
-#define PLL_GPLL 2
-#define ARMCLK 3
-
-/* sclk gates (special clocks) */
-#define SCLK_SPI0 65
-#define SCLK_NANDC 67
-#define SCLK_SDMMC 68
-#define SCLK_SDIO 69
-#define SCLK_EMMC 71
-#define SCLK_UART0 72
-#define SCLK_UART1 73
-#define SCLK_UART2 74
-#define SCLK_I2S0 75
-#define SCLK_I2S1 76
-#define SCLK_I2S2 77
-#define SCLK_TIMER0 78
-#define SCLK_TIMER1 79
-#define SCLK_SFC 80
-#define SCLK_SDMMC_DRV 81
-#define SCLK_SDIO_DRV 82
-#define SCLK_EMMC_DRV 83
-#define SCLK_SDMMC_SAMPLE 84
-#define SCLK_SDIO_SAMPLE 85
-#define SCLK_EMMC_SAMPLE 86
-#define SCLK_VENC_CORE 87
-#define SCLK_HEVC_CORE 88
-#define SCLK_HEVC_CABAC 89
-#define SCLK_PWM0_PMU 90
-#define SCLK_I2C0_PMU 91
-#define SCLK_WIFI 92
-#define SCLK_CIFOUT 93
-#define SCLK_MIPI_CSI_OUT 94
-#define SCLK_CIF0 95
-#define SCLK_CIF1 96
-#define SCLK_CIF2 97
-#define SCLK_CIF3 98
-#define SCLK_DSP 99
-#define SCLK_DSP_IOP 100
-#define SCLK_DSP_EPP 101
-#define SCLK_DSP_EDP 102
-#define SCLK_DSP_EDAP 103
-#define SCLK_CVBS_HOST 104
-#define SCLK_HDMI_SFR 105
-#define SCLK_HDMI_CEC 106
-#define SCLK_CRYPTO 107
-#define SCLK_SPI 108
-#define SCLK_SARADC 109
-#define SCLK_TSADC 110
-#define SCLK_MAC_PRE 111
-#define SCLK_MAC 112
-#define SCLK_MAC_RX 113
-#define SCLK_MAC_REF 114
-#define SCLK_MAC_REFOUT 115
-#define SCLK_DSP_PFM 116
-#define SCLK_RGA 117
-#define SCLK_I2C1 118
-#define SCLK_I2C2 119
-#define SCLK_I2C3 120
-#define SCLK_PWM 121
-#define SCLK_ISP 122
-#define SCLK_USBPHY 123
-#define SCLK_I2S0_SRC 124
-#define SCLK_I2S1_SRC 125
-#define SCLK_I2S2_SRC 126
-#define SCLK_UART0_SRC 127
-#define SCLK_UART1_SRC 128
-#define SCLK_UART2_SRC 129
-#define SCLK_MAC_TX 130
-#define SCLK_MACREF 131
-#define SCLK_MACREF_OUT 132
-
-#define DCLK_VOP_SRC 185
-#define DCLK_HDMIPHY 186
-#define DCLK_VOP 187
-
-/* aclk gates */
-#define ACLK_DMAC 192
-#define ACLK_PRE 193
-#define ACLK_CORE 194
-#define ACLK_ENMCORE 195
-#define ACLK_RKVENC 196
-#define ACLK_RKVDEC 197
-#define ACLK_VPU 198
-#define ACLK_CIF0 199
-#define ACLK_VIO0 200
-#define ACLK_VIO1 201
-#define ACLK_VOP 202
-#define ACLK_IEP 203
-#define ACLK_RGA 204
-#define ACLK_ISP 205
-#define ACLK_CIF1 206
-#define ACLK_CIF2 207
-#define ACLK_CIF3 208
-#define ACLK_PERI 209
-#define ACLK_GMAC 210
-
-/* pclk gates */
-#define PCLK_GPIO1 256
-#define PCLK_GPIO2 257
-#define PCLK_GPIO3 258
-#define PCLK_GRF 259
-#define PCLK_I2C1 260
-#define PCLK_I2C2 261
-#define PCLK_I2C3 262
-#define PCLK_SPI 263
-#define PCLK_SFC 264
-#define PCLK_UART0 265
-#define PCLK_UART1 266
-#define PCLK_UART2 267
-#define PCLK_TSADC 268
-#define PCLK_PWM 269
-#define PCLK_TIMER 270
-#define PCLK_PERI 271
-#define PCLK_GPIO0_PMU 272
-#define PCLK_I2C0_PMU 273
-#define PCLK_PWM0_PMU 274
-#define PCLK_ISP 275
-#define PCLK_VIO 276
-#define PCLK_MIPI_DSI 277
-#define PCLK_HDMI_CTRL 278
-#define PCLK_SARADC 279
-#define PCLK_DSP_CFG 280
-#define PCLK_BUS 281
-#define PCLK_EFUSE0 282
-#define PCLK_EFUSE1 283
-#define PCLK_WDT 284
-#define PCLK_GMAC 285
-
-/* hclk gates */
-#define HCLK_I2S0_8CH 320
-#define HCLK_I2S1_2CH 321
-#define HCLK_I2S2_2CH 322
-#define HCLK_NANDC 323
-#define HCLK_SDMMC 324
-#define HCLK_SDIO 325
-#define HCLK_EMMC 326
-#define HCLK_PERI 327
-#define HCLK_SFC 328
-#define HCLK_RKVENC 329
-#define HCLK_RKVDEC 330
-#define HCLK_CIF0 331
-#define HCLK_VIO 332
-#define HCLK_VOP 333
-#define HCLK_IEP 334
-#define HCLK_RGA 335
-#define HCLK_ISP 336
-#define HCLK_CRYPTO_MST 337
-#define HCLK_CRYPTO_SLV 338
-#define HCLK_HOST0 339
-#define HCLK_OTG 340
-#define HCLK_CIF1 341
-#define HCLK_CIF2 342
-#define HCLK_CIF3 343
-#define HCLK_BUS 344
-#define HCLK_VPU 345
-
-#define CLK_NR_CLKS (HCLK_VPU + 1)
-
-/* reset id */
-#define SRST_CORE_PO_AD 0
-#define SRST_CORE_AD 1
-#define SRST_L2_AD 2
-#define SRST_CPU_NIU_AD 3
-#define SRST_CORE_PO 4
-#define SRST_CORE 5
-#define SRST_L2 6
-#define SRST_CORE_DBG 8
-#define PRST_DBG 9
-#define RST_DAP 10
-#define PRST_DBG_NIU 11
-#define ARST_STRC_SYS_AD 15
-
-#define SRST_DDRPHY_CLKDIV 16
-#define SRST_DDRPHY 17
-#define PRST_DDRPHY 18
-#define PRST_HDMIPHY 19
-#define PRST_VDACPHY 20
-#define PRST_VADCPHY 21
-#define PRST_MIPI_CSI_PHY 22
-#define PRST_MIPI_DSI_PHY 23
-#define PRST_ACODEC 24
-#define ARST_BUS_NIU 25
-#define PRST_TOP_NIU 26
-#define ARST_INTMEM 27
-#define HRST_ROM 28
-#define ARST_DMAC 29
-#define SRST_MSCH_NIU 30
-#define PRST_MSCH_NIU 31
-
-#define PRST_DDRUPCTL 32
-#define NRST_DDRUPCTL 33
-#define PRST_DDRMON 34
-#define HRST_I2S0_8CH 35
-#define MRST_I2S0_8CH 36
-#define HRST_I2S1_2CH 37
-#define MRST_IS21_2CH 38
-#define HRST_I2S2_2CH 39
-#define MRST_I2S2_2CH 40
-#define HRST_CRYPTO 41
-#define SRST_CRYPTO 42
-#define PRST_SPI 43
-#define SRST_SPI 44
-#define PRST_UART0 45
-#define PRST_UART1 46
-#define PRST_UART2 47
-
-#define SRST_UART0 48
-#define SRST_UART1 49
-#define SRST_UART2 50
-#define PRST_I2C1 51
-#define PRST_I2C2 52
-#define PRST_I2C3 53
-#define SRST_I2C1 54
-#define SRST_I2C2 55
-#define SRST_I2C3 56
-#define PRST_PWM1 58
-#define SRST_PWM1 60
-#define PRST_WDT 61
-#define PRST_GPIO1 62
-#define PRST_GPIO2 63
-
-#define PRST_GPIO3 64
-#define PRST_GRF 65
-#define PRST_EFUSE 66
-#define PRST_EFUSE512 67
-#define PRST_TIMER0 68
-#define SRST_TIMER0 69
-#define SRST_TIMER1 70
-#define PRST_TSADC 71
-#define SRST_TSADC 72
-#define PRST_SARADC 73
-#define SRST_SARADC 74
-#define HRST_SYSBUS 75
-#define PRST_USBGRF 76
-
-#define ARST_PERIPH_NIU 80
-#define HRST_PERIPH_NIU 81
-#define PRST_PERIPH_NIU 82
-#define HRST_PERIPH 83
-#define HRST_SDMMC 84
-#define HRST_SDIO 85
-#define HRST_EMMC 86
-#define HRST_NANDC 87
-#define NRST_NANDC 88
-#define HRST_SFC 89
-#define SRST_SFC 90
-#define ARST_GMAC 91
-#define HRST_OTG 92
-#define SRST_OTG 93
-#define SRST_OTG_ADP 94
-#define HRST_HOST0 95
-
-#define HRST_HOST0_AUX 96
-#define HRST_HOST0_ARB 97
-#define SRST_HOST0_EHCIPHY 98
-#define SRST_HOST0_UTMI 99
-#define SRST_USBPOR 100
-#define SRST_UTMI0 101
-#define SRST_UTMI1 102
-
-#define ARST_VIO0_NIU 102
-#define ARST_VIO1_NIU 103
-#define HRST_VIO_NIU 104
-#define PRST_VIO_NIU 105
-#define ARST_VOP 106
-#define HRST_VOP 107
-#define DRST_VOP 108
-#define ARST_IEP 109
-#define HRST_IEP 110
-#define ARST_RGA 111
-#define HRST_RGA 112
-#define SRST_RGA 113
-#define PRST_CVBS 114
-#define PRST_HDMI 115
-#define SRST_HDMI 116
-#define PRST_MIPI_DSI 117
-
-#define ARST_ISP_NIU 118
-#define HRST_ISP_NIU 119
-#define HRST_ISP 120
-#define SRST_ISP 121
-#define ARST_VIP0 122
-#define HRST_VIP0 123
-#define PRST_VIP0 124
-#define ARST_VIP1 125
-#define HRST_VIP1 126
-#define PRST_VIP1 127
-#define ARST_VIP2 128
-#define HRST_VIP2 129
-#define PRST_VIP2 120
-#define ARST_VIP3 121
-#define HRST_VIP3 122
-#define PRST_VIP4 123
-
-#define PRST_CIF1TO4 124
-#define SRST_CVBS_CLK 125
-#define HRST_CVBS 126
-
-#define ARST_VPU_NIU 140
-#define HRST_VPU_NIU 141
-#define ARST_VPU 142
-#define HRST_VPU 143
-#define ARST_RKVDEC_NIU 144
-#define HRST_RKVDEC_NIU 145
-#define ARST_RKVDEC 146
-#define HRST_RKVDEC 147
-#define SRST_RKVDEC_CABAC 148
-#define SRST_RKVDEC_CORE 149
-#define ARST_RKVENC_NIU 150
-#define HRST_RKVENC_NIU 151
-#define ARST_RKVENC 152
-#define HRST_RKVENC 153
-#define SRST_RKVENC_CORE 154
-
-#define SRST_DSP_CORE 156
-#define SRST_DSP_SYS 157
-#define SRST_DSP_GLOBAL 158
-#define SRST_DSP_OECM 159
-#define PRST_DSP_IOP_NIU 160
-#define ARST_DSP_EPP_NIU 161
-#define ARST_DSP_EDP_NIU 162
-#define PRST_DSP_DBG_NIU 163
-#define PRST_DSP_CFG_NIU 164
-#define PRST_DSP_GRF 165
-#define PRST_DSP_MAILBOX 166
-#define PRST_DSP_INTC 167
-#define PRST_DSP_PFM_MON 169
-#define SRST_DSP_PFM_MON 170
-#define ARST_DSP_EDAP_NIU 171
-
-#define SRST_PMU 172
-#define SRST_PMU_I2C0 173
-#define PRST_PMU_I2C0 174
-#define PRST_PMU_GPIO0 175
-#define PRST_PMU_INTMEM 176
-#define PRST_PMU_PWM0 177
-#define SRST_PMU_PWM0 178
-#define PRST_PMU_GRF 179
-#define SRST_PMU_NIU 180
-#define SRST_PMU_PVTM 181
-#define ARST_DSP_EDP_PERF 184
-#define ARST_DSP_EPP_PERF 185
-
-#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__
-#define __DT_BINDINGS_POWER_RK3328_POWER_H__
-
-/**
- * RK3328 idle id Summary.
- */
-#define RK3328_PD_CORE 0
-#define RK3328_PD_GPU 1
-#define RK3328_PD_BUS 2
-#define RK3328_PD_MSCH 3
-#define RK3328_PD_PERI 4
-#define RK3328_PD_VIDEO 5
-#define RK3328_PD_HEVC 6
-#define RK3328_PD_SYS 7
-#define RK3328_PD_VPU 8
-#define RK3328_PD_VIO 9
-
-#endif
+++ /dev/null
-#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__
-#define __DT_BINDINGS_POWER_RK3399_POWER_H__
-
-/* VD_CORE_L */
-#define RK3399_PD_A53_L0 0
-#define RK3399_PD_A53_L1 1
-#define RK3399_PD_A53_L2 2
-#define RK3399_PD_A53_L3 3
-#define RK3399_PD_SCU_L 4
-
-/* VD_CORE_B */
-#define RK3399_PD_A72_B0 5
-#define RK3399_PD_A72_B1 6
-#define RK3399_PD_SCU_B 7
-
-/* VD_LOGIC */
-#define RK3399_PD_TCPD0 8
-#define RK3399_PD_TCPD1 9
-#define RK3399_PD_CCI 10
-#define RK3399_PD_CCI0 11
-#define RK3399_PD_CCI1 12
-#define RK3399_PD_PERILP 13
-#define RK3399_PD_PERIHP 14
-#define RK3399_PD_VIO 15
-#define RK3399_PD_VO 16
-#define RK3399_PD_VOPB 17
-#define RK3399_PD_VOPL 18
-#define RK3399_PD_ISP0 19
-#define RK3399_PD_ISP1 20
-#define RK3399_PD_HDCP 21
-#define RK3399_PD_GMAC 22
-#define RK3399_PD_EMMC 23
-#define RK3399_PD_USB3 24
-#define RK3399_PD_EDP 25
-#define RK3399_PD_GIC 26
-#define RK3399_PD_SD 27
-#define RK3399_PD_SDIOAUDIO 28
-#define RK3399_PD_ALIVE 29
-
-/* VD_CENTER */
-#define RK3399_PD_CENTER 30
-#define RK3399_PD_VCODEC 31
-#define RK3399_PD_VDU 32
-#define RK3399_PD_RGA 33
-#define RK3399_PD_IEP 34
-
-/* VD_GPU */
-#define RK3399_PD_GPU 35
-
-/* VD_PMU */
-#define RK3399_PD_PMU 36
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__
-#define __DT_BINDINGS_POWER_RK3568_POWER_H__
-
-/* VD_CORE */
-#define RK3568_PD_CPU_0 0
-#define RK3568_PD_CPU_1 1
-#define RK3568_PD_CPU_2 2
-#define RK3568_PD_CPU_3 3
-#define RK3568_PD_CORE_ALIVE 4
-
-/* VD_PMU */
-#define RK3568_PD_PMU 5
-
-/* VD_NPU */
-#define RK3568_PD_NPU 6
-
-/* VD_GPU */
-#define RK3568_PD_GPU 7
-
-/* VD_LOGIC */
-#define RK3568_PD_VI 8
-#define RK3568_PD_VO 9
-#define RK3568_PD_RGA 10
-#define RK3568_PD_VPU 11
-#define RK3568_PD_CENTER 12
-#define RK3568_PD_RKVDEC 13
-#define RK3568_PD_RKVENC 14
-#define RK3568_PD_PIPE 15
-#define RK3568_PD_LOGIC_ALIVE 16
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
-#ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__
-#define __DT_BINDINGS_POWER_RK3588_POWER_H__
-
-/* VD_LITDSU */
-#define RK3588_PD_CPU_0 0
-#define RK3588_PD_CPU_1 1
-#define RK3588_PD_CPU_2 2
-#define RK3588_PD_CPU_3 3
-
-/* VD_BIGCORE0 */
-#define RK3588_PD_CPU_4 4
-#define RK3588_PD_CPU_5 5
-
-/* VD_BIGCORE1 */
-#define RK3588_PD_CPU_6 6
-#define RK3588_PD_CPU_7 7
-
-/* VD_NPU */
-#define RK3588_PD_NPU 8
-#define RK3588_PD_NPUTOP 9
-#define RK3588_PD_NPU1 10
-#define RK3588_PD_NPU2 11
-
-/* VD_GPU */
-#define RK3588_PD_GPU 12
-
-/* VD_VCODEC */
-#define RK3588_PD_VCODEC 13
-#define RK3588_PD_RKVDEC0 14
-#define RK3588_PD_RKVDEC1 15
-#define RK3588_PD_VENC0 16
-#define RK3588_PD_VENC1 17
-
-/* VD_DD01 */
-#define RK3588_PD_DDR01 18
-
-/* VD_DD23 */
-#define RK3588_PD_DDR23 19
-
-/* VD_LOGIC */
-#define RK3588_PD_CENTER 20
-#define RK3588_PD_VDPU 21
-#define RK3588_PD_RGA30 22
-#define RK3588_PD_AV1 23
-#define RK3588_PD_VOP 24
-#define RK3588_PD_VO0 25
-#define RK3588_PD_VO1 26
-#define RK3588_PD_VI 27
-#define RK3588_PD_ISP1 28
-#define RK3588_PD_FEC 29
-#define RK3588_PD_RGA31 30
-#define RK3588_PD_USB 31
-#define RK3588_PD_PHP 32
-#define RK3588_PD_GMAC 33
-#define RK3588_PD_PCIE 34
-#define RK3588_PD_NVM 35
-#define RK3588_PD_NVM0 36
-#define RK3588_PD_SDIO 37
-#define RK3588_PD_AUDIO 38
-#define RK3588_PD_SECURE 39
-#define RK3588_PD_SDMMC 40
-#define RK3588_PD_CRYPTO 41
-#define RK3588_PD_BUS 42
-
-/* VD_PMU */
-#define RK3588_PD_PMU1 43
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
-#define __DT_BINDINGS_POWER_RV1126_POWER_H__
-
-/* VD_CORE */
-#define RV1126_PD_CPU_0 0
-#define RV1126_PD_CPU_1 1
-#define RV1126_PD_CPU_2 2
-#define RV1126_PD_CPU_3 3
-#define RV1126_PD_CORE_ALIVE 4
-
-/* VD_PMU */
-#define RV1126_PD_PMU 5
-#define RV1126_PD_PMU_ALIVE 6
-
-/* VD_NPU */
-#define RV1126_PD_NPU 7
-
-/* VD_VEPU */
-#define RV1126_PD_VEPU 8
-
-/* VD_LOGIC */
-#define RV1126_PD_VI 9
-#define RV1126_PD_VO 10
-#define RV1126_PD_ISPP 11
-#define RV1126_PD_VDPU 12
-#define RV1126_PD_CRYPTO 13
-#define RV1126_PD_DDR 14
-#define RV1126_PD_NVM 15
-#define RV1126_PD_SDIO 16
-#define RV1126_PD_USB 17
-#define RV1126_PD_LOGIC_ALIVE 18
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
-/*
- * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
- * Copyright (c) 2022 Collabora Ltd.
- *
- * Author: Elaine Zhang <zhangqing@rock-chips.com>
- * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
- */
-
-#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
-#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
-
-#define SRST_A_TOP_BIU 0
-#define SRST_P_TOP_BIU 1
-#define SRST_P_CSIPHY0 2
-#define SRST_CSIPHY0 3
-#define SRST_P_CSIPHY1 4
-#define SRST_CSIPHY1 5
-#define SRST_A_TOP_M500_BIU 6
-
-#define SRST_A_TOP_M400_BIU 7
-#define SRST_A_TOP_S200_BIU 8
-#define SRST_A_TOP_S400_BIU 9
-#define SRST_A_TOP_M300_BIU 10
-#define SRST_USBDP_COMBO_PHY0_INIT 11
-#define SRST_USBDP_COMBO_PHY0_CMN 12
-#define SRST_USBDP_COMBO_PHY0_LANE 13
-#define SRST_USBDP_COMBO_PHY0_PCS 14
-#define SRST_USBDP_COMBO_PHY1_INIT 15
-
-#define SRST_USBDP_COMBO_PHY1_CMN 16
-#define SRST_USBDP_COMBO_PHY1_LANE 17
-#define SRST_USBDP_COMBO_PHY1_PCS 18
-#define SRST_DCPHY0 19
-#define SRST_P_MIPI_DCPHY0 20
-#define SRST_P_MIPI_DCPHY0_GRF 21
-
-#define SRST_DCPHY1 22
-#define SRST_P_MIPI_DCPHY1 23
-#define SRST_P_MIPI_DCPHY1_GRF 24
-#define SRST_P_APB2ASB_SLV_CDPHY 25
-#define SRST_P_APB2ASB_SLV_CSIPHY 26
-#define SRST_P_APB2ASB_SLV_VCCIO3_5 27
-#define SRST_P_APB2ASB_SLV_VCCIO6 28
-#define SRST_P_APB2ASB_SLV_EMMCIO 29
-#define SRST_P_APB2ASB_SLV_IOC_TOP 30
-#define SRST_P_APB2ASB_SLV_IOC_RIGHT 31
-
-#define SRST_P_CRU 32
-#define SRST_A_CHANNEL_SECURE2VO1USB 33
-#define SRST_A_CHANNEL_SECURE2CENTER 34
-#define SRST_H_CHANNEL_SECURE2VO1USB 35
-#define SRST_H_CHANNEL_SECURE2CENTER 36
-
-#define SRST_P_CHANNEL_SECURE2VO1USB 37
-#define SRST_P_CHANNEL_SECURE2CENTER 38
-
-#define SRST_H_AUDIO_BIU 39
-#define SRST_P_AUDIO_BIU 40
-#define SRST_H_I2S0_8CH 41
-#define SRST_M_I2S0_8CH_TX 42
-#define SRST_M_I2S0_8CH_RX 43
-#define SRST_P_ACDCDIG 44
-#define SRST_H_I2S2_2CH 45
-#define SRST_H_I2S3_2CH 46
-
-#define SRST_M_I2S2_2CH 47
-#define SRST_M_I2S3_2CH 48
-#define SRST_DAC_ACDCDIG 49
-#define SRST_H_SPDIF0 50
-
-#define SRST_M_SPDIF0 51
-#define SRST_H_SPDIF1 52
-#define SRST_M_SPDIF1 53
-#define SRST_H_PDM1 54
-#define SRST_PDM1 55
-
-#define SRST_A_BUS_BIU 56
-#define SRST_P_BUS_BIU 57
-#define SRST_A_GIC 58
-#define SRST_A_GIC_DBG 59
-#define SRST_A_DMAC0 60
-#define SRST_A_DMAC1 61
-#define SRST_A_DMAC2 62
-#define SRST_P_I2C1 63
-#define SRST_P_I2C2 64
-#define SRST_P_I2C3 65
-#define SRST_P_I2C4 66
-#define SRST_P_I2C5 67
-#define SRST_P_I2C6 68
-#define SRST_P_I2C7 69
-#define SRST_P_I2C8 70
-
-#define SRST_I2C1 71
-#define SRST_I2C2 72
-#define SRST_I2C3 73
-#define SRST_I2C4 74
-#define SRST_I2C5 75
-#define SRST_I2C6 76
-#define SRST_I2C7 77
-#define SRST_I2C8 78
-#define SRST_P_CAN0 79
-#define SRST_CAN0 80
-#define SRST_P_CAN1 81
-#define SRST_CAN1 82
-#define SRST_P_CAN2 83
-#define SRST_CAN2 84
-#define SRST_P_SARADC 85
-
-#define SRST_P_TSADC 86
-#define SRST_TSADC 87
-#define SRST_P_UART1 88
-#define SRST_P_UART2 89
-#define SRST_P_UART3 90
-#define SRST_P_UART4 91
-#define SRST_P_UART5 92
-#define SRST_P_UART6 93
-#define SRST_P_UART7 94
-#define SRST_P_UART8 95
-#define SRST_P_UART9 96
-#define SRST_S_UART1 97
-
-#define SRST_S_UART2 98
-#define SRST_S_UART3 99
-#define SRST_S_UART4 100
-#define SRST_S_UART5 101
-#define SRST_S_UART6 102
-#define SRST_S_UART7 103
-
-#define SRST_S_UART8 104
-#define SRST_S_UART9 105
-#define SRST_P_SPI0 106
-#define SRST_P_SPI1 107
-#define SRST_P_SPI2 108
-#define SRST_P_SPI3 109
-#define SRST_P_SPI4 110
-#define SRST_SPI0 111
-#define SRST_SPI1 112
-#define SRST_SPI2 113
-#define SRST_SPI3 114
-#define SRST_SPI4 115
-
-#define SRST_P_WDT0 116
-#define SRST_T_WDT0 117
-#define SRST_P_SYS_GRF 118
-#define SRST_P_PWM1 119
-#define SRST_PWM1 120
-#define SRST_P_PWM2 121
-#define SRST_PWM2 122
-#define SRST_P_PWM3 123
-#define SRST_PWM3 124
-#define SRST_P_BUSTIMER0 125
-#define SRST_P_BUSTIMER1 126
-#define SRST_BUSTIMER0 127
-
-#define SRST_BUSTIMER1 128
-#define SRST_BUSTIMER2 129
-#define SRST_BUSTIMER3 130
-#define SRST_BUSTIMER4 131
-#define SRST_BUSTIMER5 132
-#define SRST_BUSTIMER6 133
-#define SRST_BUSTIMER7 134
-#define SRST_BUSTIMER8 135
-#define SRST_BUSTIMER9 136
-#define SRST_BUSTIMER10 137
-#define SRST_BUSTIMER11 138
-#define SRST_P_MAILBOX0 139
-#define SRST_P_MAILBOX1 140
-#define SRST_P_MAILBOX2 141
-#define SRST_P_GPIO1 142
-#define SRST_GPIO1 143
-
-#define SRST_P_GPIO2 144
-#define SRST_GPIO2 145
-#define SRST_P_GPIO3 146
-#define SRST_GPIO3 147
-#define SRST_P_GPIO4 148
-#define SRST_GPIO4 149
-#define SRST_A_DECOM 150
-#define SRST_P_DECOM 151
-#define SRST_D_DECOM 152
-#define SRST_P_TOP 153
-#define SRST_A_GICADB_GIC2CORE_BUS 154
-#define SRST_P_DFT2APB 155
-#define SRST_P_APB2ASB_MST_TOP 156
-#define SRST_P_APB2ASB_MST_CDPHY 157
-#define SRST_P_APB2ASB_MST_BOT_RIGHT 158
-
-#define SRST_P_APB2ASB_MST_IOC_TOP 159
-#define SRST_P_APB2ASB_MST_IOC_RIGHT 160
-#define SRST_P_APB2ASB_MST_CSIPHY 161
-#define SRST_P_APB2ASB_MST_VCCIO3_5 162
-#define SRST_P_APB2ASB_MST_VCCIO6 163
-#define SRST_P_APB2ASB_MST_EMMCIO 164
-#define SRST_A_SPINLOCK 165
-#define SRST_P_OTPC_NS 166
-#define SRST_OTPC_NS 167
-#define SRST_OTPC_ARB 168
-
-#define SRST_P_BUSIOC 169
-#define SRST_P_PMUCM0_INTMUX 170
-#define SRST_P_DDRCM0_INTMUX 171
-
-#define SRST_P_DDR_DFICTL_CH0 172
-#define SRST_P_DDR_MON_CH0 173
-#define SRST_P_DDR_STANDBY_CH0 174
-#define SRST_P_DDR_UPCTL_CH0 175
-#define SRST_TM_DDR_MON_CH0 176
-#define SRST_P_DDR_GRF_CH01 177
-#define SRST_DFI_CH0 178
-#define SRST_SBR_CH0 179
-#define SRST_DDR_UPCTL_CH0 180
-#define SRST_DDR_DFICTL_CH0 181
-#define SRST_DDR_MON_CH0 182
-#define SRST_DDR_STANDBY_CH0 183
-#define SRST_A_DDR_UPCTL_CH0 184
-#define SRST_P_DDR_DFICTL_CH1 185
-#define SRST_P_DDR_MON_CH1 186
-#define SRST_P_DDR_STANDBY_CH1 187
-
-#define SRST_P_DDR_UPCTL_CH1 188
-#define SRST_TM_DDR_MON_CH1 189
-#define SRST_DFI_CH1 190
-#define SRST_SBR_CH1 191
-#define SRST_DDR_UPCTL_CH1 192
-#define SRST_DDR_DFICTL_CH1 193
-#define SRST_DDR_MON_CH1 194
-#define SRST_DDR_STANDBY_CH1 195
-#define SRST_A_DDR_UPCTL_CH1 196
-#define SRST_A_DDR01_MSCH0 197
-#define SRST_A_DDR01_RS_MSCH0 198
-#define SRST_A_DDR01_FRS_MSCH0 199
-
-#define SRST_A_DDR01_SCRAMBLE0 200
-#define SRST_A_DDR01_FRS_SCRAMBLE0 201
-#define SRST_A_DDR01_MSCH1 202
-#define SRST_A_DDR01_RS_MSCH1 203
-#define SRST_A_DDR01_FRS_MSCH1 204
-#define SRST_A_DDR01_SCRAMBLE1 205
-#define SRST_A_DDR01_FRS_SCRAMBLE1 206
-#define SRST_P_DDR01_MSCH0 207
-#define SRST_P_DDR01_MSCH1 208
-
-#define SRST_P_DDR_DFICTL_CH2 209
-#define SRST_P_DDR_MON_CH2 210
-#define SRST_P_DDR_STANDBY_CH2 211
-#define SRST_P_DDR_UPCTL_CH2 212
-#define SRST_TM_DDR_MON_CH2 213
-#define SRST_P_DDR_GRF_CH23 214
-#define SRST_DFI_CH2 215
-#define SRST_SBR_CH2 216
-#define SRST_DDR_UPCTL_CH2 217
-#define SRST_DDR_DFICTL_CH2 218
-#define SRST_DDR_MON_CH2 219
-#define SRST_DDR_STANDBY_CH2 220
-#define SRST_A_DDR_UPCTL_CH2 221
-#define SRST_P_DDR_DFICTL_CH3 222
-#define SRST_P_DDR_MON_CH3 223
-#define SRST_P_DDR_STANDBY_CH3 224
-
-#define SRST_P_DDR_UPCTL_CH3 225
-#define SRST_TM_DDR_MON_CH3 226
-#define SRST_DFI_CH3 227
-#define SRST_SBR_CH3 228
-#define SRST_DDR_UPCTL_CH3 229
-#define SRST_DDR_DFICTL_CH3 230
-#define SRST_DDR_MON_CH3 231
-#define SRST_DDR_STANDBY_CH3 232
-#define SRST_A_DDR_UPCTL_CH3 233
-#define SRST_A_DDR23_MSCH2 234
-#define SRST_A_DDR23_RS_MSCH2 235
-#define SRST_A_DDR23_FRS_MSCH2 236
-
-#define SRST_A_DDR23_SCRAMBLE2 237
-#define SRST_A_DDR23_FRS_SCRAMBLE2 238
-#define SRST_A_DDR23_MSCH3 239
-#define SRST_A_DDR23_RS_MSCH3 240
-#define SRST_A_DDR23_FRS_MSCH3 241
-#define SRST_A_DDR23_SCRAMBLE3 242
-#define SRST_A_DDR23_FRS_SCRAMBLE3 243
-#define SRST_P_DDR23_MSCH2 244
-#define SRST_P_DDR23_MSCH3 245
-
-#define SRST_ISP1 246
-#define SRST_ISP1_VICAP 247
-#define SRST_A_ISP1_BIU 248
-#define SRST_H_ISP1_BIU 249
-
-#define SRST_A_RKNN1 250
-#define SRST_A_RKNN1_BIU 251
-#define SRST_H_RKNN1 252
-#define SRST_H_RKNN1_BIU 253
-
-#define SRST_A_RKNN2 254
-#define SRST_A_RKNN2_BIU 255
-#define SRST_H_RKNN2 256
-#define SRST_H_RKNN2_BIU 257
-
-#define SRST_A_RKNN_DSU0 258
-#define SRST_P_NPUTOP_BIU 259
-#define SRST_P_NPU_TIMER 260
-#define SRST_NPUTIMER0 261
-#define SRST_NPUTIMER1 262
-#define SRST_P_NPU_WDT 263
-#define SRST_T_NPU_WDT 264
-#define SRST_P_NPU_PVTM 265
-#define SRST_P_NPU_GRF 266
-#define SRST_NPU_PVTM 267
-
-#define SRST_NPU_PVTPLL 268
-#define SRST_H_NPU_CM0_BIU 269
-#define SRST_F_NPU_CM0_CORE 270
-#define SRST_T_NPU_CM0_JTAG 271
-#define SRST_A_RKNN0 272
-#define SRST_A_RKNN0_BIU 273
-#define SRST_H_RKNN0 274
-#define SRST_H_RKNN0_BIU 275
-
-#define SRST_H_NVM_BIU 276
-#define SRST_A_NVM_BIU 277
-#define SRST_H_EMMC 278
-#define SRST_A_EMMC 279
-#define SRST_C_EMMC 280
-#define SRST_B_EMMC 281
-#define SRST_T_EMMC 282
-#define SRST_S_SFC 283
-#define SRST_H_SFC 284
-#define SRST_H_SFC_XIP 285
-
-#define SRST_P_GRF 286
-#define SRST_P_DEC_BIU 287
-#define SRST_P_PHP_BIU 288
-#define SRST_A_PCIE_GRIDGE 289
-#define SRST_A_PHP_BIU 290
-#define SRST_A_GMAC0 291
-#define SRST_A_GMAC1 292
-#define SRST_A_PCIE_BIU 293
-#define SRST_PCIE0_POWER_UP 294
-#define SRST_PCIE1_POWER_UP 295
-#define SRST_PCIE2_POWER_UP 296
-
-#define SRST_PCIE3_POWER_UP 297
-#define SRST_PCIE4_POWER_UP 298
-#define SRST_P_PCIE0 299
-#define SRST_P_PCIE1 300
-#define SRST_P_PCIE2 301
-#define SRST_P_PCIE3 302
-
-#define SRST_P_PCIE4 303
-#define SRST_A_PHP_GIC_ITS 304
-#define SRST_A_MMU_PCIE 305
-#define SRST_A_MMU_PHP 306
-#define SRST_A_MMU_BIU 307
-
-#define SRST_A_USB3OTG2 308
-
-#define SRST_PMALIVE0 309
-#define SRST_PMALIVE1 310
-#define SRST_PMALIVE2 311
-#define SRST_A_SATA0 312
-#define SRST_A_SATA1 313
-#define SRST_A_SATA2 314
-#define SRST_RXOOB0 315
-#define SRST_RXOOB1 316
-#define SRST_RXOOB2 317
-#define SRST_ASIC0 318
-#define SRST_ASIC1 319
-#define SRST_ASIC2 320
-
-#define SRST_A_RKVDEC_CCU 321
-#define SRST_H_RKVDEC0 322
-#define SRST_A_RKVDEC0 323
-#define SRST_H_RKVDEC0_BIU 324
-#define SRST_A_RKVDEC0_BIU 325
-#define SRST_RKVDEC0_CA 326
-#define SRST_RKVDEC0_HEVC_CA 327
-#define SRST_RKVDEC0_CORE 328
-
-#define SRST_H_RKVDEC1 329
-#define SRST_A_RKVDEC1 330
-#define SRST_H_RKVDEC1_BIU 331
-#define SRST_A_RKVDEC1_BIU 332
-#define SRST_RKVDEC1_CA 333
-#define SRST_RKVDEC1_HEVC_CA 334
-#define SRST_RKVDEC1_CORE 335
-
-#define SRST_A_USB_BIU 336
-#define SRST_H_USB_BIU 337
-#define SRST_A_USB3OTG0 338
-#define SRST_A_USB3OTG1 339
-#define SRST_H_HOST0 340
-#define SRST_H_HOST_ARB0 341
-#define SRST_H_HOST1 342
-#define SRST_H_HOST_ARB1 343
-#define SRST_A_USB_GRF 344
-#define SRST_C_USB2P0_HOST0 345
-
-#define SRST_C_USB2P0_HOST1 346
-#define SRST_HOST_UTMI0 347
-#define SRST_HOST_UTMI1 348
-
-#define SRST_A_VDPU_BIU 349
-#define SRST_A_VDPU_LOW_BIU 350
-#define SRST_H_VDPU_BIU 351
-#define SRST_A_JPEG_DECODER_BIU 352
-#define SRST_A_VPU 353
-#define SRST_H_VPU 354
-#define SRST_A_JPEG_ENCODER0 355
-#define SRST_H_JPEG_ENCODER0 356
-#define SRST_A_JPEG_ENCODER1 357
-#define SRST_H_JPEG_ENCODER1 358
-#define SRST_A_JPEG_ENCODER2 359
-#define SRST_H_JPEG_ENCODER2 360
-
-#define SRST_A_JPEG_ENCODER3 361
-#define SRST_H_JPEG_ENCODER3 362
-#define SRST_A_JPEG_DECODER 363
-#define SRST_H_JPEG_DECODER 364
-#define SRST_H_IEP2P0 365
-#define SRST_A_IEP2P0 366
-#define SRST_IEP2P0_CORE 367
-#define SRST_H_RGA2 368
-#define SRST_A_RGA2 369
-#define SRST_RGA2_CORE 370
-#define SRST_H_RGA3_0 371
-#define SRST_A_RGA3_0 372
-#define SRST_RGA3_0_CORE 373
-
-#define SRST_H_RKVENC0_BIU 374
-#define SRST_A_RKVENC0_BIU 375
-#define SRST_H_RKVENC0 376
-#define SRST_A_RKVENC0 377
-#define SRST_RKVENC0_CORE 378
-
-#define SRST_H_RKVENC1_BIU 379
-#define SRST_A_RKVENC1_BIU 380
-#define SRST_H_RKVENC1 381
-#define SRST_A_RKVENC1 382
-#define SRST_RKVENC1_CORE 383
-
-#define SRST_A_VI_BIU 384
-#define SRST_H_VI_BIU 385
-#define SRST_P_VI_BIU 386
-#define SRST_D_VICAP 387
-#define SRST_A_VICAP 388
-#define SRST_H_VICAP 389
-#define SRST_ISP0 390
-#define SRST_ISP0_VICAP 391
-
-#define SRST_FISHEYE0 392
-#define SRST_FISHEYE1 393
-#define SRST_P_CSI_HOST_0 394
-#define SRST_P_CSI_HOST_1 395
-#define SRST_P_CSI_HOST_2 396
-#define SRST_P_CSI_HOST_3 397
-#define SRST_P_CSI_HOST_4 398
-#define SRST_P_CSI_HOST_5 399
-
-#define SRST_CSIHOST0_VICAP 400
-#define SRST_CSIHOST1_VICAP 401
-#define SRST_CSIHOST2_VICAP 402
-#define SRST_CSIHOST3_VICAP 403
-#define SRST_CSIHOST4_VICAP 404
-#define SRST_CSIHOST5_VICAP 405
-#define SRST_CIFIN 406
-
-#define SRST_A_VOP_BIU 407
-#define SRST_A_VOP_LOW_BIU 408
-#define SRST_H_VOP_BIU 409
-#define SRST_P_VOP_BIU 410
-#define SRST_H_VOP 411
-#define SRST_A_VOP 412
-#define SRST_D_VOP0 413
-#define SRST_D_VOP2HDMI_BRIDGE0 414
-#define SRST_D_VOP2HDMI_BRIDGE1 415
-
-#define SRST_D_VOP1 416
-#define SRST_D_VOP2 417
-#define SRST_D_VOP3 418
-#define SRST_P_VOPGRF 419
-#define SRST_P_DSIHOST0 420
-#define SRST_P_DSIHOST1 421
-#define SRST_DSIHOST0 422
-#define SRST_DSIHOST1 423
-#define SRST_VOP_PMU 424
-#define SRST_P_VOP_CHANNEL_BIU 425
-
-#define SRST_H_VO0_BIU 426
-#define SRST_H_VO0_S_BIU 427
-#define SRST_P_VO0_BIU 428
-#define SRST_P_VO0_S_BIU 429
-#define SRST_A_HDCP0_BIU 430
-#define SRST_P_VO0GRF 431
-#define SRST_H_HDCP_KEY0 432
-#define SRST_A_HDCP0 433
-#define SRST_H_HDCP0 434
-#define SRST_HDCP0 435
-
-#define SRST_P_TRNG0 436
-#define SRST_DP0 437
-#define SRST_DP1 438
-#define SRST_H_I2S4_8CH 439
-#define SRST_M_I2S4_8CH_TX 440
-#define SRST_H_I2S8_8CH 441
-
-#define SRST_M_I2S8_8CH_TX 442
-#define SRST_H_SPDIF2_DP0 443
-#define SRST_M_SPDIF2_DP0 444
-#define SRST_H_SPDIF5_DP1 445
-#define SRST_M_SPDIF5_DP1 446
-
-#define SRST_A_HDCP1_BIU 447
-#define SRST_A_VO1_BIU 448
-#define SRST_H_VOP1_BIU 449
-#define SRST_H_VOP1_S_BIU 450
-#define SRST_P_VOP1_BIU 451
-#define SRST_P_VO1GRF 452
-#define SRST_P_VO1_S_BIU 453
-
-#define SRST_H_I2S7_8CH 454
-#define SRST_M_I2S7_8CH_RX 455
-#define SRST_H_HDCP_KEY1 456
-#define SRST_A_HDCP1 457
-#define SRST_H_HDCP1 458
-#define SRST_HDCP1 459
-#define SRST_P_TRNG1 460
-#define SRST_P_HDMITX0 461
-
-#define SRST_HDMITX0_REF 462
-#define SRST_P_HDMITX1 463
-#define SRST_HDMITX1_REF 464
-#define SRST_A_HDMIRX 465
-#define SRST_P_HDMIRX 466
-#define SRST_HDMIRX_REF 467
-
-#define SRST_P_EDP0 468
-#define SRST_EDP0_24M 469
-#define SRST_P_EDP1 470
-#define SRST_EDP1_24M 471
-#define SRST_M_I2S5_8CH_TX 472
-#define SRST_H_I2S5_8CH 473
-#define SRST_M_I2S6_8CH_TX 474
-
-#define SRST_M_I2S6_8CH_RX 475
-#define SRST_H_I2S6_8CH 476
-#define SRST_H_SPDIF3 477
-#define SRST_M_SPDIF3 478
-#define SRST_H_SPDIF4 479
-#define SRST_M_SPDIF4 480
-#define SRST_H_SPDIFRX0 481
-#define SRST_M_SPDIFRX0 482
-#define SRST_H_SPDIFRX1 483
-#define SRST_M_SPDIFRX1 484
-
-#define SRST_H_SPDIFRX2 485
-#define SRST_M_SPDIFRX2 486
-#define SRST_LINKSYM_HDMITXPHY0 487
-#define SRST_LINKSYM_HDMITXPHY1 488
-#define SRST_VO1_BRIDGE0 489
-#define SRST_VO1_BRIDGE1 490
-
-#define SRST_H_I2S9_8CH 491
-#define SRST_M_I2S9_8CH_RX 492
-#define SRST_H_I2S10_8CH 493
-#define SRST_M_I2S10_8CH_RX 494
-#define SRST_P_S_HDMIRX 495
-
-#define SRST_GPU 496
-#define SRST_SYS_GPU 497
-#define SRST_A_S_GPU_BIU 498
-#define SRST_A_M0_GPU_BIU 499
-#define SRST_A_M1_GPU_BIU 500
-#define SRST_A_M2_GPU_BIU 501
-#define SRST_A_M3_GPU_BIU 502
-#define SRST_P_GPU_BIU 503
-#define SRST_P_GPU_PVTM 504
-
-#define SRST_GPU_PVTM 505
-#define SRST_P_GPU_GRF 506
-#define SRST_GPU_PVTPLL 507
-#define SRST_GPU_JTAG 508
-
-#define SRST_A_AV1_BIU 509
-#define SRST_A_AV1 510
-#define SRST_P_AV1_BIU 511
-#define SRST_P_AV1 512
-
-#define SRST_A_DDR_BIU 513
-#define SRST_A_DMA2DDR 514
-#define SRST_A_DDR_SHAREMEM 515
-#define SRST_A_DDR_SHAREMEM_BIU 516
-#define SRST_A_CENTER_S200_BIU 517
-#define SRST_A_CENTER_S400_BIU 518
-#define SRST_H_AHB2APB 519
-#define SRST_H_CENTER_BIU 520
-#define SRST_F_DDR_CM0_CORE 521
-
-#define SRST_DDR_TIMER0 522
-#define SRST_DDR_TIMER1 523
-#define SRST_T_WDT_DDR 524
-#define SRST_T_DDR_CM0_JTAG 525
-#define SRST_P_CENTER_GRF 526
-#define SRST_P_AHB2APB 527
-#define SRST_P_WDT 528
-#define SRST_P_TIMER 529
-#define SRST_P_DMA2DDR 530
-#define SRST_P_SHAREMEM 531
-#define SRST_P_CENTER_BIU 532
-#define SRST_P_CENTER_CHANNEL_BIU 533
-
-#define SRST_P_USBDPGRF0 534
-#define SRST_P_USBDPPHY0 535
-#define SRST_P_USBDPGRF1 536
-#define SRST_P_USBDPPHY1 537
-#define SRST_P_HDPTX0 538
-#define SRST_P_HDPTX1 539
-#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540
-#define SRST_P_USB2PHY_U3_0_GRF0 541
-#define SRST_P_USB2PHY_U3_1_GRF0 542
-#define SRST_P_USB2PHY_U2_0_GRF0 543
-#define SRST_P_USB2PHY_U2_1_GRF0 544
-#define SRST_HDPTX0_ROPLL 545
-#define SRST_HDPTX0_LCPLL 546
-#define SRST_HDPTX0 547
-#define SRST_HDPTX1_ROPLL 548
-
-#define SRST_HDPTX1_LCPLL 549
-#define SRST_HDPTX1 550
-#define SRST_HDPTX0_HDMIRXPHY_SET 551
-#define SRST_USBDP_COMBO_PHY0 552
-#define SRST_USBDP_COMBO_PHY0_LCPLL 553
-#define SRST_USBDP_COMBO_PHY0_ROPLL 554
-#define SRST_USBDP_COMBO_PHY0_PCS_HS 555
-#define SRST_USBDP_COMBO_PHY1 556
-#define SRST_USBDP_COMBO_PHY1_LCPLL 557
-#define SRST_USBDP_COMBO_PHY1_ROPLL 558
-#define SRST_USBDP_COMBO_PHY1_PCS_HS 559
-#define SRST_HDMIHDP0 560
-#define SRST_HDMIHDP1 561
-
-#define SRST_A_VO1USB_TOP_BIU 562
-#define SRST_H_VO1USB_TOP_BIU 563
-
-#define SRST_H_SDIO_BIU 564
-#define SRST_H_SDIO 565
-#define SRST_SDIO 566
-
-#define SRST_H_RGA3_BIU 567
-#define SRST_A_RGA3_BIU 568
-#define SRST_H_RGA3_1 569
-#define SRST_A_RGA3_1 570
-#define SRST_RGA3_1_CORE 571
-
-#define SRST_REF_PIPE_PHY0 572
-#define SRST_REF_PIPE_PHY1 573
-#define SRST_REF_PIPE_PHY2 574
-
-#define SRST_P_PHPTOP_CRU 575
-#define SRST_P_PCIE2_GRF0 576
-#define SRST_P_PCIE2_GRF1 577
-#define SRST_P_PCIE2_GRF2 578
-#define SRST_P_PCIE2_PHY0 579
-#define SRST_P_PCIE2_PHY1 580
-#define SRST_P_PCIE2_PHY2 581
-#define SRST_P_PCIE3_PHY 582
-#define SRST_P_APB2ASB_SLV_CHIP_TOP 583
-#define SRST_PCIE30_PHY 584
-
-#define SRST_H_PMU1_BIU 585
-#define SRST_P_PMU1_BIU 586
-#define SRST_H_PMU_CM0_BIU 587
-#define SRST_F_PMU_CM0_CORE 588
-#define SRST_T_PMU1_CM0_JTAG 589
-
-#define SRST_DDR_FAIL_SAFE 590
-#define SRST_P_CRU_PMU1 591
-#define SRST_P_PMU1_GRF 592
-#define SRST_P_PMU1_IOC 593
-#define SRST_P_PMU1WDT 594
-#define SRST_T_PMU1WDT 595
-#define SRST_P_PMU1TIMER 596
-#define SRST_PMU1TIMER0 597
-#define SRST_PMU1TIMER1 598
-#define SRST_P_PMU1PWM 599
-#define SRST_PMU1PWM 600
-
-#define SRST_P_I2C0 601
-#define SRST_I2C0 602
-#define SRST_S_UART0 603
-#define SRST_P_UART0 604
-#define SRST_H_I2S1_8CH 605
-#define SRST_M_I2S1_8CH_TX 606
-#define SRST_M_I2S1_8CH_RX 607
-#define SRST_H_PDM0 608
-#define SRST_PDM0 609
-
-#define SRST_H_VAD 610
-#define SRST_HDPTX0_INIT 611
-#define SRST_HDPTX0_CMN 612
-#define SRST_HDPTX0_LANE 613
-#define SRST_HDPTX1_INIT 614
-
-#define SRST_HDPTX1_CMN 615
-#define SRST_HDPTX1_LANE 616
-#define SRST_M_MIPI_DCPHY0 617
-#define SRST_S_MIPI_DCPHY0 618
-#define SRST_M_MIPI_DCPHY1 619
-#define SRST_S_MIPI_DCPHY1 620
-#define SRST_OTGPHY_U3_0 621
-#define SRST_OTGPHY_U3_1 622
-#define SRST_OTGPHY_U2_0 623
-#define SRST_OTGPHY_U2_1 624
-
-#define SRST_P_PMU0GRF 625
-#define SRST_P_PMU0IOC 626
-#define SRST_P_GPIO0 627
-#define SRST_GPIO0 628
-
-#define SRST_A_SECURE_NS_BIU 629
-#define SRST_H_SECURE_NS_BIU 630
-#define SRST_A_SECURE_S_BIU 631
-#define SRST_H_SECURE_S_BIU 632
-#define SRST_P_SECURE_S_BIU 633
-#define SRST_CRYPTO_CORE 634
-
-#define SRST_CRYPTO_PKA 635
-#define SRST_CRYPTO_RNG 636
-#define SRST_A_CRYPTO 637
-#define SRST_H_CRYPTO 638
-#define SRST_KEYLADDER_CORE 639
-#define SRST_KEYLADDER_RNG 640
-#define SRST_A_KEYLADDER 641
-#define SRST_H_KEYLADDER 642
-#define SRST_P_OTPC_S 643
-#define SRST_OTPC_S 644
-#define SRST_WDT_S 645
-
-#define SRST_T_WDT_S 646
-#define SRST_H_BOOTROM 647
-#define SRST_A_DCF 648
-#define SRST_P_DCF 649
-#define SRST_H_BOOTROM_NS 650
-#define SRST_P_KEYLADDER 651
-#define SRST_H_TRNG_S 652
-
-#define SRST_H_TRNG_NS 653
-#define SRST_D_SDMMC_BUFFER 654
-#define SRST_H_SDMMC 655
-#define SRST_H_SDMMC_BUFFER 656
-#define SRST_SDMMC 657
-#define SRST_P_TRNG_CHK 658
-#define SRST_TRNG_S 659
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2021 Linaro Ltd.
- * Author: Sam Protsenko <semen.protsenko@linaro.org>
- *
- * Device Tree bindings for Samsung Exynos USI (Universal Serial Interface).
- */
-
-#ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
-#define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
-
-#define USI_V2_NONE 0
-#define USI_V2_UART 1
-#define USI_V2_SPI 2
-#define USI_V2_I2C 3
-
-#endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */
#include <blk.h>
#include <efi.h>
+#include <fwu_mdata.h>
#include <mtd.h>
#include <uuid.h>
char uuidbuf[UUID_STR_LEN + 1];
};
+struct fwu_mdata_mtd_priv {
+ struct mtd_info *mtd;
+ char pri_label[50];
+ char sec_label[50];
+ u32 pri_offset;
+ u32 sec_offset;
+ struct fwu_mtd_image_info *fwu_mtd_images;
+};
+
+struct fwu_data {
+ uint32_t crc32;
+ uint32_t version;
+ uint32_t active_index;
+ uint32_t previous_active_index;
+ uint32_t metadata_size;
+ uint32_t boot_index;
+ uint32_t num_banks;
+ uint32_t num_images;
+ uint8_t bank_state[4];
+ bool trial_state;
+
+ struct fwu_mdata *fwu_mdata;
+
+ struct fwu_image_entry fwu_images[CONFIG_FWU_NUM_IMAGES_PER_BANK];
+};
+
struct fwu_mdata_ops {
/**
* read_mdata() - Populate the asked FWU metadata copy
* @dev: FWU metadata device
* @mdata: Output FWU mdata read
* @primary: If primary or secondary copy of metadata is to be read
+ * @size: Size in bytes of the metadata to be read
*
* Return: 0 if OK, -ve on error
*/
- int (*read_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
+ int (*read_mdata)(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary, uint32_t size);
/**
* write_mdata() - Write the given FWU metadata copy
* @dev: FWU metadata device
* @mdata: Copy of the FWU metadata to write
* @primary: If primary or secondary copy of metadata is to be written
+ * @size: Size in bytes of the metadata to be written
*
* Return: 0 if OK, -ve on error
*/
- int (*write_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
+ int (*write_mdata)(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary, uint32_t size);
};
-#define FWU_MDATA_VERSION 0x1
#define FWU_IMAGE_ACCEPTED 0x1
+#define FWU_BANK_INVALID (uint8_t)0xFF
+#define FWU_BANK_VALID (uint8_t)0xFE
+#define FWU_BANK_ACCEPTED (uint8_t)0xFC
+
+enum {
+ PRIMARY_PART = 1,
+ SECONDARY_PART,
+ BOTH_PARTS,
+};
+
/*
* GUID value defined in the FWU specification for identification
* of the FWU metadata partition.
/**
* fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata()
*/
-int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
+int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary, uint32_t size);
/**
* fwu_write_mdata() - Wrapper around fwu_mdata_ops.write_mdata()
*/
-int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary);
+int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata,
+ bool primary, uint32_t size);
/**
* fwu_get_mdata() - Read, verify and return the FWU metadata
*/
int fwu_mtd_get_alt_num(efi_guid_t *image_guid, u8 *alt_num, const char *mtd_dev);
+/**
+ * fwu_mdata_copies_allocate() - Allocate memory for metadata
+ * @mdata_size: Size of the metadata structure
+ *
+ * Allocate memory for storing both the copies of the FWU metadata. The
+ * copies are then used as a cache for storing FWU metadata contents.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_mdata_copies_allocate(u32 mdata_size);
+
+/**
+ * fwu_get_dev() - Return the FWU metadata device
+ *
+ * Return the pointer to the FWU metadata device.
+ *
+ * Return: Pointer to the FWU metadata dev
+ */
+struct udevice *fwu_get_dev(void);
+
+/**
+ * fwu_get_data() - Return the version agnostic FWU structure
+ *
+ * Return the pointer to the version agnostic FWU structure.
+ *
+ * Return: Pointer to the FWU data structure
+ */
+struct fwu_data *fwu_get_data(void);
+
+/**
+ * fwu_sync_mdata() - Update given meta-data partition(s) with the copy provided
+ * @data: FWU Data structure
+ * @part: Bitmask of FWU metadata partitions to be written to
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_sync_mdata(struct fwu_mdata *mdata, int part);
+
+/**
+ * fwu_populate_mdata_image_info() - Populate the image information
+ * of the metadata
+ * @data: Version agnostic FWU metadata information
+ *
+ * Populate the image information in the FWU metadata by copying it
+ * from the version agnostic structure. This is done before the
+ * metadata gets written to the storage media.
+ *
+ * Return: None
+ */
+void fwu_populate_mdata_image_info(struct fwu_data *data);
+
+/**
+ * fwu_get_mdata_size() - Get the FWU metadata size
+ * @mdata_size: Size of the metadata structure
+ *
+ * Get the size of the FWU metadata from the structure. This is later used
+ * to allocate memory for the structure.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_get_mdata_size(uint32_t *mdata_size);
+
+/**
+ * fwu_state_machine_updates() - Update FWU state of the platform
+ * @trial_state: Is platform transitioning into Trial State
+ * @update_index: Bank number to which images have been updated
+ *
+ * On successful completion of updates, transition the platform to
+ * either Trial State or Regular State.
+ *
+ * To transition the platform to Trial State, start the
+ * TrialStateCtr counter, followed by setting the value of bank_state
+ * field of the metadata to Valid state(applicable only in version 2
+ * of metadata).
+ *
+ * In case, the platform is to transition directly to Regular State,
+ * update the bank_state field of the metadata to Accepted
+ * state(applicable only in version 2 of metadata).
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_state_machine_updates(bool trial_state, uint32_t update_index);
+
+/**
+ * fwu_init() - FWU specific initialisations
+ *
+ * Carry out some FWU specific initialisations including allocation
+ * of memory for the metadata copies, and reading the FWU metadata
+ * copies into the allocated memory. The metadata fields are then
+ * copied into a version agnostic structure.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_init(void);
+
#endif /* _FWU_H_ */
/**
* struct fwu_image_bank_info - firmware image information
- * @image_uuid: Guid value of the image in this bank
+ * @image_guid: Guid value of the image in this bank
* @accepted: Acceptance status of the image
* @reserved: Reserved
*
* acceptance status
*/
struct fwu_image_bank_info {
- efi_guid_t image_uuid;
+ efi_guid_t image_guid;
uint32_t accepted;
uint32_t reserved;
} __packed;
/**
* struct fwu_image_entry - information for a particular type of image
- * @image_type_uuid: Guid value for identifying the image type
- * @location_uuid: Guid of the storage volume where the image is located
+ * @image_type_guid: Guid value for identifying the image type
+ * @location_guid: Guid of the storage volume where the image is located
* @img_bank_info: Array containing properties of images
*
* This structure contains information on various types of updatable
* information per bank.
*/
struct fwu_image_entry {
- efi_guid_t image_type_uuid;
- efi_guid_t location_uuid;
+ efi_guid_t image_type_guid;
+ efi_guid_t location_guid;
struct fwu_image_bank_info img_bank_info[CONFIG_FWU_NUM_BANKS];
} __packed;
+/**
+ * struct fwu_fw_store_desc - FWU updatable image information
+ * @num_banks: Number of firmware banks
+ * @num_images: Number of images per bank
+ * @img_entry_size: The size of the img_entry array
+ * @bank_info_entry_size: The size of the img_bank_info array
+ * @img_entry: Array of image entries each giving information on a image
+ *
+ * This image descriptor structure contains information on the number of
+ * updatable banks and images per bank. It also gives the total sizes of
+ * the fwu_image_entry and fwu_image_bank_info arrays. This structure is
+ * only present in version 2 of the metadata structure.
+ */
+struct fwu_fw_store_desc {
+ uint8_t num_banks;
+ uint8_t reserved;
+ uint16_t num_images;
+ uint16_t img_entry_size;
+ uint16_t bank_info_entry_size;
+
+ struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK];
+} __packed;
+
+#if defined(CONFIG_FWU_MDATA_V1)
/**
* struct fwu_mdata - FWU metadata structure for multi-bank updates
* @crc32: crc32 value for the FWU metadata
struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK];
} __packed;
+#else /* CONFIG_FWU_MDATA_V1 */
+/**
+ * struct fwu_mdata - FWU metadata structure for multi-bank updates
+ * @crc32: crc32 value for the FWU metadata
+ * @version: FWU metadata version
+ * @active_index: Index of the bank currently used for booting images
+ * @previous_active_inde: Index of the bank used before the current bank
+ * being used for booting
+ * @metadata_size: Size of the entire metadata structure, including the
+ * image descriptors
+ * @desc_offset: The offset from the start of this structure where the
+ * image descriptor structure starts. 0 if absent
+ * @bank_state: State of each bank, valid, invalid or accepted
+ * @fw_desc: The structure describing the FWU updatable images
+ *
+ * This is the top level structure used to store all information for performing
+ * multi bank updates on the platform. This contains info on the bank being
+ * used to boot along with the information on state of individual banks.
+ */
+struct fwu_mdata {
+ uint32_t crc32;
+ uint32_t version;
+ uint32_t active_index;
+ uint32_t previous_active_index;
+ uint32_t metadata_size;
+ uint16_t desc_offset;
+ uint16_t reserved1;
+ uint8_t bank_state[4];
+ uint32_t reserved2;
+
+ // struct fwu_fw_store_desc fw_desc;
+} __packed;
+
+#endif /* CONFIG_FWU_MDATA_V1 */
+
#endif /* _FWU_MDATA_H_ */
}
#endif
+/**
+ * Format a string and place it in a buffer
+ *
+ * @buf: The buffer to place the result into
+ * @size: The size of the buffer, including the trailing null space
+ * @fmt: The format string to use
+ * @...: Arguments for the format string
+ * Return: the number of characters which would be
+ * generated for the given input, excluding the trailing null,
+ * as per ISO C99. If the return is greater than or equal to
+ * @size, the resulting string is truncated.
+ *
+ * See the vsprintf() documentation for format string extensions over C99.
+ */
+int snprintf(char *buf, size_t size, const char *fmt, ...)
+ __attribute__ ((format (__printf__, 3, 4)));
+
/*
* FILE based functions (can only be used AFTER relocation!)
*/
TPM2_ALG_SM3_256 = 0x12,
};
-extern const enum tpm2_algorithms tpm2_supported_algorithms[4];
+/**
+ * struct digest_info - details of supported digests
+ *
+ * @hash_name: hash name
+ * @hash_alg: hash algorithm id
+ * @hash_mask: hash registry mask
+ * @hash_len: hash digest length
+ */
+struct digest_info {
+ const char *hash_name;
+ u16 hash_alg;
+ u32 hash_mask;
+ u16 hash_len;
+};
+
+/* Algorithm Registry */
+#define TCG2_BOOT_HASH_ALG_SHA1 0x00000001
+#define TCG2_BOOT_HASH_ALG_SHA256 0x00000002
+#define TCG2_BOOT_HASH_ALG_SHA384 0x00000004
+#define TCG2_BOOT_HASH_ALG_SHA512 0x00000008
+#define TCG2_BOOT_HASH_ALG_SM3_256 0x00000010
+
+static const struct digest_info hash_algo_list[] = {
+ {
+ "sha1",
+ TPM2_ALG_SHA1,
+ TCG2_BOOT_HASH_ALG_SHA1,
+ TPM2_SHA1_DIGEST_SIZE,
+ },
+ {
+ "sha256",
+ TPM2_ALG_SHA256,
+ TCG2_BOOT_HASH_ALG_SHA256,
+ TPM2_SHA256_DIGEST_SIZE,
+ },
+ {
+ "sha384",
+ TPM2_ALG_SHA384,
+ TCG2_BOOT_HASH_ALG_SHA384,
+ TPM2_SHA384_DIGEST_SIZE,
+ },
+ {
+ "sha512",
+ TPM2_ALG_SHA512,
+ TCG2_BOOT_HASH_ALG_SHA512,
+ TPM2_SHA512_DIGEST_SIZE,
+ },
+};
static inline u16 tpm2_algorithm_to_len(enum tpm2_algorithms a)
{
}
}
-#define tpm2_algorithm_to_mask(a) (1 << (a))
-
/* NV index attributes */
enum tpm_index_attrs {
TPMA_NV_PPWRITE = 1UL << 0,
*/
u32 tpm2_auto_start(struct udevice *dev);
+/**
+ * tpm2_name_to_algorithm() - Return an algorithm id given a supported
+ * algorithm name
+ *
+ * @name: algorithm name
+ * Return: enum tpm2_algorithms or -EINVAL
+ */
+enum tpm2_algorithms tpm2_name_to_algorithm(const char *name);
+
+/**
+ * tpm2_algorithm_name() - Return an algorithm name string for a
+ * supported algorithm id
+ *
+ * @algorithm_id: algorithm defined in enum tpm2_algorithms
+ * Return: algorithm name string or ""
+ */
+const char *tpm2_algorithm_name(enum tpm2_algorithms);
+
+/**
+ * tpm2_algorithm_to_mask() - Get a TCG hash mask for algorithm
+ *
+ * @hash_alg: TCG defined algorithm
+ * Return: TCG hashing algorithm bitmaps (or 0 if algo not supported)
+ */
+u32 tpm2_algorithm_to_mask(enum tpm2_algorithms);
+
#endif /* __TPM_V2_H */
#define MD5_SUM_LEN 16
-struct MD5Context {
+typedef struct MD5Context {
__u32 buf[4];
__u32 bits[2];
union {
unsigned char in[64];
__u32 in32[16];
};
-};
+} MD5Context;
-void MD5Init(struct MD5Context *ctx);
-void MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len);
-void MD5Final(unsigned char digest[16], struct MD5Context *ctx);
+void MD5Init(MD5Context *ctx);
+void MD5Update(MD5Context *ctx, unsigned char const *buf, unsigned int len);
+void MD5Final(unsigned char digest[16], MD5Context *ctx);
/*
* Calculate and store in 'output' the MD5 digest of 'len' bytes at
*/
char *simple_xtoa(ulong num);
-/**
- * Format a string and place it in a buffer
- *
- * @buf: The buffer to place the result into
- * @size: The size of the buffer, including the trailing null space
- * @fmt: The format string to use
- * @...: Arguments for the format string
- * Return: the number of characters which would be
- * generated for the given input, excluding the trailing null,
- * as per ISO C99. If the return is greater than or equal to
- * @size, the resulting string is truncated.
- *
- * See the vsprintf() documentation for format string extensions over C99.
- */
-int snprintf(char *buf, size_t size, const char *fmt, ...)
- __attribute__ ((format (__printf__, 3, 4)));
-
/**
* Format a string and place it in a buffer
*
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <asm/io.h>
+#include <stdio.h>
#include <vsprintf.h>
char *display_options_get_banner_priv(bool newlines, const char *build_tag,
if (ret != EFI_SUCCESS)
log_err("Unable to set the Accept bit for the image %pUs\n",
image_guid);
+
+ status = fwu_state_machine_updates(0, active_idx);
+ if (status < 0)
+ ret = EFI_DEVICE_ERROR;
+
}
return ret;
log_err("Failed to update FWU metadata index values\n");
} else {
log_debug("Successfully updated the active_index\n");
- if (fw_accept_os) {
- status = fwu_trial_state_ctr_start();
- if (status < 0)
- ret = EFI_DEVICE_ERROR;
- }
+ status = fwu_state_machine_updates(fw_accept_os ? 1 : 0,
+ update_index);
+ if (status < 0)
+ ret = EFI_DEVICE_ERROR;
}
return ret;
#include <linux/oid_registry.h>
#include <u-boot/hash-checksum.h>
#include <u-boot/rsa.h>
-#include <u-boot/sha256.h>
const efi_guid_t efi_guid_sha256 = EFI_CERT_SHA256_GUID;
const efi_guid_t efi_guid_cert_rsa2048 = EFI_CERT_RSA2048_GUID;
#include <tpm-v2.h>
#include <tpm_api.h>
#include <u-boot/hash-checksum.h>
-#include <u-boot/sha1.h>
-#include <u-boot/sha256.h>
-#include <u-boot/sha512.h>
#include <linux/unaligned/be_byteshift.h>
#include <linux/unaligned/le_byteshift.h>
#include <linux/unaligned/generic.h>
}
digest_list->count = 0;
- for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); i++) {
- u16 hash_alg = tpm2_supported_algorithms[i];
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); i++) {
+ u16 hash_alg = hash_algo_list[i].hash_alg;
- if (!(active & tpm2_algorithm_to_mask(hash_alg)))
+ if (!(active & hash_algo_list[i].hash_mask))
continue;
switch (hash_alg) {
case TPM2_ALG_SHA1:
the platform is allowed to boot in Trial State after an
update.
+config FWU_MDATA_V1
+ bool "Enable support FWU Metadata version 1"
+ help
+ The FWU specification supports two versions of the
+ metadata structure. This option enables support for FWU
+ Metadata version 1 access.
+
+config FWU_MDATA_V2
+ bool "Enable support FWU Metadata version 2"
+ help
+ The FWU specification supports two versions of the
+ metadata structure. This option enables support for FWU
+ Metadata version 2 access.
+
endif
obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += fwu.o
obj-$(CONFIG_FWU_MDATA_GPT_BLK) += fwu_gpt.o
obj-$(CONFIG_FWU_MDATA_MTD) += fwu_mtd.o
+obj-$(CONFIG_FWU_MDATA_V1) += fwu_v1.o
+obj-$(CONFIG_FWU_MDATA_V2) += fwu_v2.o
#include <event.h>
#include <fwu.h>
#include <fwu_mdata.h>
+#include <log.h>
#include <malloc.h>
#include <linux/errno.h>
#include <u-boot/crc.h>
-static struct fwu_mdata g_mdata; /* = {0} makes uninit crc32 always invalid */
+struct fwu_data g_fwu_data;
static struct udevice *g_dev;
static u8 in_trial;
static u8 boottime_check;
IMAGE_ACCEPT_CLEAR,
};
-enum {
- PRIMARY_PART = 1,
- SECONDARY_PART,
- BOTH_PARTS,
-};
-
static int trial_counter_update(u16 *trial_state_ctr)
{
bool delete;
return ret;
}
-static int in_trial_state(struct fwu_mdata *mdata)
+static u32 in_trial_state(void)
{
- u32 i, active_bank;
- struct fwu_image_entry *img_entry;
- struct fwu_image_bank_info *img_bank_info;
-
- active_bank = mdata->active_index;
- img_entry = &mdata->img_entry[0];
- for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
- img_bank_info = &img_entry[i].img_bank_info[active_bank];
- if (!img_bank_info->accepted) {
- log_info("System booting in Trial State\n");
- return 1;
- }
- }
-
- return 0;
+ return g_fwu_data.trial_state;
}
static int fwu_get_image_type_id(u8 image_index, efi_guid_t *image_type_id)
return -ENOENT;
}
+static int mdata_crc_check(struct fwu_mdata *mdata)
+{
+ int ret;
+ u32 calc_crc32;
+ uint32_t mdata_size;
+ void *buf = &mdata->version;
+
+ ret = fwu_get_mdata_size(&mdata_size);
+ if (ret)
+ return ret;
+
+ calc_crc32 = crc32(0, buf, mdata_size - sizeof(u32));
+ return calc_crc32 == mdata->crc32 ? 0 : -EINVAL;
+}
+
+static void fwu_data_crc_update(uint32_t crc32)
+{
+ g_fwu_data.crc32 = crc32;
+}
+
+/**
+ * fwu_get_data() - Return the version agnostic FWU structure
+ *
+ * Return the pointer to the version agnostic FWU structure.
+ *
+ * Return: Pointer to the FWU data structure
+ */
+struct fwu_data *fwu_get_data(void)
+{
+ return &g_fwu_data;
+}
+
+static void fwu_populate_mdata_bank_index(struct fwu_data *fwu_data)
+{
+ struct fwu_mdata *mdata = fwu_data->fwu_mdata;
+
+ mdata->active_index = fwu_data->active_index;
+ mdata->previous_active_index = fwu_data->previous_active_index;
+}
+
+/**
+ * fwu_get_dev() - Return the FWU metadata device
+ *
+ * Return the pointer to the FWU metadata device.
+ *
+ * Return: Pointer to the FWU metadata dev
+ */
+struct udevice *fwu_get_dev(void)
+{
+ return g_dev;
+}
+
/**
* fwu_sync_mdata() - Update given meta-data partition(s) with the copy provided
- * @mdata: FWU metadata structure
+ * @data: FWU Data structure
* @part: Bitmask of FWU metadata partitions to be written to
*
* Return: 0 if OK, -ve on error
*/
-static int fwu_sync_mdata(struct fwu_mdata *mdata, int part)
+int fwu_sync_mdata(struct fwu_mdata *mdata, int part)
{
- void *buf = &mdata->version;
int err;
+ uint mdata_size;
+ void *buf = &mdata->version;
if (part == BOTH_PARTS) {
err = fwu_sync_mdata(mdata, SECONDARY_PART);
part = PRIMARY_PART;
}
+ err = fwu_get_mdata_size(&mdata_size);
+ if (err)
+ return err;
+
/*
* Calculate the crc32 for the updated FWU metadata
* and put the updated value in the FWU metadata crc32
* field
*/
- mdata->crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32));
+ mdata->crc32 = crc32(0, buf, mdata_size - sizeof(u32));
+ fwu_data_crc_update(mdata->crc32);
- err = fwu_write_mdata(g_dev, mdata, part == PRIMARY_PART);
+ err = fwu_write_mdata(g_dev, mdata, part == PRIMARY_PART, mdata_size);
if (err) {
log_err("Unable to write %s mdata\n",
part == PRIMARY_PART ? "primary" : "secondary");
return err;
}
- /* update the cached copy of meta-data */
- memcpy(&g_mdata, mdata, sizeof(struct fwu_mdata));
-
return 0;
}
-static inline int mdata_crc_check(struct fwu_mdata *mdata)
+/**
+ * fwu_mdata_copies_allocate() - Allocate memory for metadata
+ * @mdata_size: Size of the metadata structure
+ *
+ * Allocate memory for storing both the copies of the FWU metadata. The
+ * copies are then used as a cache for storing FWU metadata contents.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_mdata_copies_allocate(u32 mdata_size)
{
- void *buf = &mdata->version;
- u32 calc_crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32));
+ if (g_fwu_data.fwu_mdata)
+ return 0;
- return calc_crc32 == mdata->crc32 ? 0 : -EINVAL;
+ /*
+ * Allocate the total memory that would be needed for both
+ * the copies.
+ */
+ g_fwu_data.fwu_mdata = calloc(2, mdata_size);
+ if (!g_fwu_data.fwu_mdata) {
+ log_err("Unable to allocate space for FWU metadata\n");
+ return -ENOMEM;
+ }
+
+ return 0;
}
/**
int fwu_get_mdata(struct fwu_mdata *mdata)
{
int err;
+ uint32_t mdata_size;
bool parts_ok[2] = { false };
- struct fwu_mdata s, *parts_mdata[2];
+ struct fwu_mdata *parts_mdata[2];
- parts_mdata[0] = &g_mdata;
- parts_mdata[1] = &s;
+ err = fwu_get_mdata_size(&mdata_size);
+ if (err)
+ return err;
+
+ parts_mdata[0] = g_fwu_data.fwu_mdata;
+ if (!parts_mdata[0]) {
+ log_err("Memory not allocated for the FWU Metadata copies\n");
+ return -ENOMEM;
+ }
+
+ parts_mdata[1] = (struct fwu_mdata *)((char *)parts_mdata[0] +
+ mdata_size);
/* if mdata already read and ready */
err = mdata_crc_check(parts_mdata[0]);
if (!err)
goto ret_mdata;
- /* else read, verify and, if needed, fix mdata */
+
+ /* else read, verify and, if needed, fix mdata */
for (int i = 0; i < 2; i++) {
parts_ok[i] = false;
- err = fwu_read_mdata(g_dev, parts_mdata[i], !i);
+ err = fwu_read_mdata(g_dev, parts_mdata[i], !i, mdata_size);
if (!err) {
err = mdata_crc_check(parts_mdata[i]);
if (!err)
* Before returning, check that both the
* FWU metadata copies are the same.
*/
- err = memcmp(parts_mdata[0], parts_mdata[1], sizeof(struct fwu_mdata));
+ err = memcmp(parts_mdata[0], parts_mdata[1], mdata_size);
if (!err)
goto ret_mdata;
if (parts_ok[i])
continue;
- memcpy(parts_mdata[i], parts_mdata[1 - i], sizeof(struct fwu_mdata));
+ memcpy(parts_mdata[i], parts_mdata[1 - i], mdata_size);
err = fwu_sync_mdata(parts_mdata[i], i ? SECONDARY_PART : PRIMARY_PART);
if (err) {
log_debug("mdata : %s write failed\n", i ? "secondary" : "primary");
ret_mdata:
if (!err && mdata)
- memcpy(mdata, parts_mdata[0], sizeof(struct fwu_mdata));
+ memcpy(mdata, parts_mdata[0], mdata_size);
return err;
}
int fwu_get_active_index(uint *active_idx)
{
int ret = 0;
- struct fwu_mdata *mdata = &g_mdata;
+ struct fwu_data *data = &g_fwu_data;
/*
* Found the FWU metadata partition, now read the active_index
* value
*/
- *active_idx = mdata->active_index;
+ *active_idx = data->active_index;
if (*active_idx >= CONFIG_FWU_NUM_BANKS) {
log_debug("Active index value read is incorrect\n");
ret = -EINVAL;
int fwu_set_active_index(uint active_idx)
{
int ret;
- struct fwu_mdata *mdata = &g_mdata;
+ struct fwu_data *data = &g_fwu_data;
if (active_idx >= CONFIG_FWU_NUM_BANKS) {
log_debug("Invalid active index value\n");
* Update the active index and previous_active_index fields
* in the FWU metadata
*/
- mdata->previous_active_index = mdata->active_index;
- mdata->active_index = active_idx;
+ data->previous_active_index = data->active_index;
+ data->active_index = active_idx;
+
+ fwu_populate_mdata_bank_index(data);
/*
* Now write this updated FWU metadata to both the
* FWU metadata partitions
*/
- ret = fwu_sync_mdata(mdata, BOTH_PARTS);
+ ret = fwu_sync_mdata(data->fwu_mdata, BOTH_PARTS);
if (ret) {
log_debug("Failed to update FWU metadata partitions\n");
ret = -EIO;
int ret, i;
uint update_bank;
efi_guid_t *image_guid, image_type_id;
- struct fwu_mdata *mdata = &g_mdata;
+ struct fwu_data *data = &g_fwu_data;
struct fwu_image_entry *img_entry;
struct fwu_image_bank_info *img_bank_info;
ret = -EINVAL;
/*
- * The FWU metadata has been read. Now get the image_uuid for the
+ * The FWU metadata has been read. Now get the image_guid for the
* image with the update_bank.
*/
for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
if (!guidcmp(&image_type_id,
- &mdata->img_entry[i].image_type_uuid)) {
- img_entry = &mdata->img_entry[i];
+ &data->fwu_images[i].image_type_guid)) {
+ img_entry = &data->fwu_images[i];
img_bank_info = &img_entry->img_bank_info[update_bank];
- image_guid = &img_bank_info->image_uuid;
+ image_guid = &img_bank_info->image_guid;
ret = fwu_plat_get_alt_num(g_dev, image_guid, alt_num);
if (ret)
log_debug("alt_num not found for partition with GUID %pUs\n",
{
int ret;
u32 cur_active_index;
- struct fwu_mdata *mdata = &g_mdata;
+ struct fwu_data *data = &g_fwu_data;
/*
* Swap the active index and previous_active_index fields
* in the FWU metadata
*/
- cur_active_index = mdata->active_index;
- mdata->active_index = mdata->previous_active_index;
- mdata->previous_active_index = cur_active_index;
+ cur_active_index = data->active_index;
+ data->active_index = data->previous_active_index;
+ data->previous_active_index = cur_active_index;
+
+ fwu_populate_mdata_bank_index(data);
/*
* Now write this updated FWU metadata to both the
* FWU metadata partitions
*/
- ret = fwu_sync_mdata(mdata, BOTH_PARTS);
+ ret = fwu_sync_mdata(data->fwu_mdata, BOTH_PARTS);
if (ret) {
log_debug("Failed to update FWU metadata partitions\n");
ret = -EIO;
static int fwu_clrset_image_accept(efi_guid_t *img_type_id, u32 bank, u8 action)
{
int ret, i;
- struct fwu_mdata *mdata = &g_mdata;
+ struct fwu_data *data = &g_fwu_data;
struct fwu_image_entry *img_entry;
struct fwu_image_bank_info *img_bank_info;
- img_entry = &mdata->img_entry[0];
+ img_entry = &data->fwu_images[0];
for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
- if (!guidcmp(&img_entry[i].image_type_uuid, img_type_id)) {
+ if (!guidcmp(&img_entry[i].image_type_guid, img_type_id)) {
img_bank_info = &img_entry[i].img_bank_info[bank];
if (action == IMAGE_ACCEPT_SET)
img_bank_info->accepted |= FWU_IMAGE_ACCEPTED;
else
img_bank_info->accepted = 0;
- ret = fwu_sync_mdata(mdata, BOTH_PARTS);
+ fwu_populate_mdata_image_info(data);
+ ret = fwu_sync_mdata(data->fwu_mdata, BOTH_PARTS);
goto out;
}
}
return 0;
}
- ret = fwu_get_mdata(NULL);
+ ret = fwu_init();
if (ret) {
- log_debug("Unable to read meta-data\n");
+ log_debug("fwu_init() failed\n");
return ret;
}
if (efi_init_obj_list() != EFI_SUCCESS)
return 0;
- in_trial = in_trial_state(&g_mdata);
+ in_trial = in_trial_state();
if (!in_trial || (ret = fwu_trial_count_update()) > 0)
ret = trial_counter_update(NULL);
#include <malloc.h>
#include <mtd.h>
#include <uuid.h>
-#include <vsprintf.h>
+#include <stdio.h>
#include <dm/ofnode.h>
-struct fwu_mtd_image_info
-fwu_mtd_images[CONFIG_FWU_NUM_BANKS * CONFIG_FWU_NUM_IMAGES_PER_BANK];
-
static struct fwu_mtd_image_info *mtd_img_by_uuid(const char *uuidbuf)
{
- int num_images = ARRAY_SIZE(fwu_mtd_images);
+ int num_images;
+ struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(fwu_get_dev());
+ struct fwu_mtd_image_info *image_info = mtd_priv->fwu_mtd_images;
+
+ if (!image_info)
+ return NULL;
+
+ num_images = CONFIG_FWU_NUM_BANKS *
+ CONFIG_FWU_NUM_IMAGES_PER_BANK;
for (int i = 0; i < num_images; i++)
- if (!strcmp(uuidbuf, fwu_mtd_images[i].uuidbuf))
- return &fwu_mtd_images[i];
+ if (!strcmp(uuidbuf, image_info[i].uuidbuf))
+ return &image_info[i];
return NULL;
}
return fwu_mtd_get_alt_num(image_id, alt_num, "nor1");
}
-static int gen_image_alt_info(char *buf, size_t len, int sidx,
+static int gen_image_alt_info(char *buf, size_t len,
struct fwu_image_entry *img, struct mtd_info *mtd)
{
char *p = buf, *end = buf + len;
/* Query a partition by image UUID */
bank = &img->img_bank_info[i];
- uuid_bin_to_str(bank->image_uuid.b, uuidbuf, UUID_STR_FORMAT_STD);
+ uuid_bin_to_str(bank->image_guid.b, uuidbuf, UUID_STR_FORMAT_STD);
mtd_img_info = mtd_img_by_uuid(uuidbuf);
if (!mtd_img_info) {
int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd)
{
- struct fwu_mdata mdata;
int i, l, ret;
-
- ret = fwu_get_mdata(&mdata);
- if (ret < 0) {
- log_err("Failed to get the FWU mdata.\n");
- return ret;
- }
+ struct fwu_data *data = fwu_get_data();
+ struct fwu_image_entry *img_entry;
for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
- ret = gen_image_alt_info(buf, len, i * CONFIG_FWU_NUM_BANKS,
- &mdata.img_entry[i], mtd);
+ img_entry = &data->fwu_images[i];
+ ret = gen_image_alt_info(buf, len, img_entry, mtd);
if (ret)
break;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#include <fwu.h>
+#include <fwu_mdata.h>
+
+#include <linux/types.h>
+
+#define FWU_MDATA_VERSION 0x1U
+
+static uint32_t fwu_check_trial_state(struct fwu_mdata *mdata, uint32_t bank)
+{
+ u32 i;
+ struct fwu_image_entry *img_entry;
+ struct fwu_image_bank_info *img_bank_info;
+
+ img_entry = &mdata->img_entry[0];
+ for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
+ img_bank_info = &img_entry[i].img_bank_info[bank];
+ if (!img_bank_info->accepted) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static void fwu_data_init(void)
+{
+ size_t image_info_size;
+ void *dst_img_info, *src_img_info;
+ struct fwu_data *data = fwu_get_data();
+ struct fwu_mdata *mdata = data->fwu_mdata;
+
+ data->crc32 = mdata->crc32;
+ data->version = mdata->version;
+ data->active_index = mdata->active_index;
+ data->previous_active_index = mdata->previous_active_index;
+
+ data->metadata_size = sizeof(struct fwu_mdata);
+ data->num_banks = CONFIG_FWU_NUM_BANKS;
+ data->num_images = CONFIG_FWU_NUM_IMAGES_PER_BANK;
+ fwu_plat_get_bootidx(&data->boot_index);
+ data->trial_state = fwu_check_trial_state(mdata, data->boot_index);
+
+ src_img_info = &mdata->img_entry[0];
+ dst_img_info = &data->fwu_images[0];
+ image_info_size = sizeof(data->fwu_images);
+
+ memcpy(dst_img_info, src_img_info, image_info_size);
+}
+
+static int fwu_trial_state_update(bool trial_state)
+{
+ int ret;
+ struct fwu_data *data = fwu_get_data();
+
+ if (trial_state) {
+ ret = fwu_trial_state_ctr_start();
+ if (ret)
+ return ret;
+ }
+
+ data->trial_state = trial_state;
+
+ return 0;
+}
+
+/**
+ * fwu_populate_mdata_image_info() - Populate the image information
+ * of the metadata
+ * @data: Version agnostic FWU metadata information
+ *
+ * Populate the image information in the FWU metadata by copying it
+ * from the version agnostic structure. This is done before the
+ * metadata gets written to the storage media.
+ *
+ * Return: None
+ */
+void fwu_populate_mdata_image_info(struct fwu_data *data)
+{
+ size_t image_info_size;
+ void *dst_img_info, *src_img_info;
+ struct fwu_mdata *mdata = data->fwu_mdata;
+
+ image_info_size = sizeof(data->fwu_images);
+ dst_img_info = &mdata->img_entry[0];
+ src_img_info = &data->fwu_images[0];
+
+ memcpy(dst_img_info, src_img_info, image_info_size);
+}
+
+/**
+ * fwu_state_machine_updates() - Update FWU state of the platform
+ * @trial_state: Is platform transitioning into Trial State
+ * @update_index: Bank number to which images have been updated
+ *
+ * On successful completion of updates, transition the platform to
+ * either Trial State or Regular State.
+ *
+ * To transition the platform to Trial State, start the
+ * TrialStateCtr counter, followed by setting the value of bank_state
+ * field of the metadata to Valid state(applicable only in version 2
+ * of metadata).
+ *
+ * In case, the platform is to transition directly to Regular State,
+ * update the bank_state field of the metadata to Accepted
+ * state(applicable only in version 2 of metadata).
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_state_machine_updates(bool trial_state,
+ __maybe_unused uint32_t update_index)
+{
+ return fwu_trial_state_update(trial_state);
+}
+
+/**
+ * fwu_get_mdata_size() - Get the FWU metadata size
+ * @mdata_size: Size of the metadata structure
+ *
+ * Get the size of the FWU metadata.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_get_mdata_size(uint32_t *mdata_size)
+{
+ *mdata_size = sizeof(struct fwu_mdata);
+
+ return 0;
+}
+
+/**
+ * fwu_init() - FWU specific initialisations
+ *
+ * Carry out some FWU specific initialisations including allocation
+ * of memory for the metadata copies, and reading the FWU metadata
+ * copies into the allocated memory. The metadata fields are then
+ * copied into a version agnostic structure.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_init(void)
+{
+ int ret;
+ uint32_t mdata_size;
+
+ fwu_get_mdata_size(&mdata_size);
+
+ ret = fwu_mdata_copies_allocate(mdata_size);
+ if (ret)
+ return ret;
+
+ /*
+ * Now read the entire structure, both copies, and
+ * validate that the copies.
+ */
+ ret = fwu_get_mdata(NULL);
+ if (ret)
+ return ret;
+
+ fwu_data_init();
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#include <fwu.h>
+#include <fwu_mdata.h>
+#include <log.h>
+
+#include <linux/types.h>
+
+#define FWU_MDATA_VERSION 0x2U
+
+static inline struct fwu_fw_store_desc *fwu_get_fw_desc(struct fwu_mdata *mdata)
+{
+ return (struct fwu_fw_store_desc *)((u8 *)mdata + sizeof(*mdata));
+}
+
+static uint32_t fwu_check_trial_state(struct fwu_mdata *mdata, uint32_t bank)
+{
+ return mdata->bank_state[bank] == FWU_BANK_VALID ? 1 : 0;
+}
+
+static void fwu_data_init(void)
+{
+ int i;
+ size_t image_info_size;
+ void *dst_img_info, *src_img_info;
+ struct fwu_data *data = fwu_get_data();
+ struct fwu_mdata *mdata = data->fwu_mdata;
+
+ data->crc32 = mdata->crc32;
+ data->version = mdata->version;
+ data->active_index = mdata->active_index;
+ data->previous_active_index = mdata->previous_active_index;
+ data->metadata_size = mdata->metadata_size;
+ fwu_plat_get_bootidx(&data->boot_index);
+ data->trial_state = fwu_check_trial_state(mdata, data->boot_index);
+
+ data->num_banks = fwu_get_fw_desc(mdata)->num_banks;
+ data->num_images = fwu_get_fw_desc(mdata)->num_images;
+
+ for (i = 0; i < 4; i++) {
+ data->bank_state[i] = mdata->bank_state[i];
+ }
+
+ image_info_size = sizeof(data->fwu_images);
+ src_img_info = &fwu_get_fw_desc(mdata)->img_entry[0];
+ dst_img_info = &data->fwu_images[0];
+
+ memcpy(dst_img_info, src_img_info, image_info_size);
+}
+
+static int fwu_mdata_sanity_checks(void)
+{
+ uint8_t num_banks;
+ uint16_t num_images;
+ struct fwu_data *data = fwu_get_data();
+ struct fwu_mdata *mdata = data->fwu_mdata;
+
+ if (mdata->version != FWU_MDATA_VERSION) {
+ log_err("FWU metadata version %u. Expected value of %u\n",
+ mdata->version, FWU_MDATA_VERSION);
+ return -EINVAL;
+ }
+
+ if (!mdata->desc_offset) {
+ log_err("No image information provided with the Metadata. ");
+ log_err("Image information expected in the metadata\n");
+ return -EINVAL;
+ }
+
+ if (mdata->desc_offset != 0x20) {
+ log_err("Descriptor Offset(0x%x) in the FWU Metadata not equal to 0x20\n",
+ mdata->desc_offset);
+ return -EINVAL;
+ }
+
+ num_banks = fwu_get_fw_desc(mdata)->num_banks;
+ num_images = fwu_get_fw_desc(mdata)->num_images;
+
+ if (num_banks != CONFIG_FWU_NUM_BANKS) {
+ log_err("Number of Banks(%u) in FWU Metadata different from the configured value(%d)",
+ num_banks, CONFIG_FWU_NUM_BANKS);
+ return -EINVAL;
+ }
+
+ if (num_images != CONFIG_FWU_NUM_IMAGES_PER_BANK) {
+ log_err("Number of Images(%u) in FWU Metadata different from the configured value(%d)",
+ num_images, CONFIG_FWU_NUM_IMAGES_PER_BANK);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int fwu_bank_state_update(bool trial_state, uint32_t bank)
+{
+ int ret;
+ struct fwu_data *data = fwu_get_data();
+ struct fwu_mdata *mdata = data->fwu_mdata;
+
+ mdata->bank_state[bank] = data->bank_state[bank] = trial_state ?
+ FWU_BANK_VALID : FWU_BANK_ACCEPTED;
+
+ ret = fwu_sync_mdata(mdata, BOTH_PARTS);
+ if (ret)
+ log_err("Unable to set bank_state for bank %u\n", bank);
+ else
+ data->trial_state = trial_state;
+
+ return ret;
+}
+
+static int fwu_trial_state_start(uint update_index)
+{
+ int ret;
+
+ ret = fwu_trial_state_ctr_start();
+ if (ret)
+ return ret;
+
+ ret = fwu_bank_state_update(1, update_index);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/**
+ * fwu_populate_mdata_image_info() - Populate the image information
+ * of the metadata
+ * @data: Version agnostic FWU metadata information
+ *
+ * Populate the image information in the FWU metadata by copying it
+ * from the version agnostic structure. This is done before the
+ * metadata gets written to the storage media.
+ *
+ * Return: None
+ */
+void fwu_populate_mdata_image_info(struct fwu_data *data)
+{
+ size_t image_info_size;
+ struct fwu_mdata *mdata = data->fwu_mdata;
+ void *dst_img_info, *src_img_info;
+
+ image_info_size = sizeof(data->fwu_images);
+ dst_img_info = &fwu_get_fw_desc(mdata)->img_entry[0];
+ src_img_info = &data->fwu_images[0];
+
+ memcpy(dst_img_info, src_img_info, image_info_size);
+}
+
+/**
+ * fwu_state_machine_updates() - Update FWU state of the platform
+ * @trial_state: Is platform transitioning into Trial State
+ * @update_index: Bank number to which images have been updated
+ *
+ * On successful completion of updates, transition the platform to
+ * either Trial State or Regular State.
+ *
+ * To transition the platform to Trial State, start the
+ * TrialStateCtr counter, followed by setting the value of bank_state
+ * field of the metadata to Valid state(applicable only in version 2
+ * of metadata).
+ *
+ * In case, the platform is to transition directly to Regular State,
+ * update the bank_state field of the metadata to Accepted
+ * state(applicable only in version 2 of metadata).
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_state_machine_updates(bool trial_state, uint32_t update_index)
+{
+ return trial_state ? fwu_trial_state_start(update_index) :
+ fwu_bank_state_update(0, update_index);
+}
+
+/**
+ * fwu_get_mdata_size() - Get the FWU metadata size
+ * @mdata_size: Size of the metadata structure
+ *
+ * Get the size of the FWU metadata from the structure. This is later used
+ * to allocate memory for the structure.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_get_mdata_size(uint32_t *mdata_size)
+{
+ int ret = 0;
+ struct fwu_mdata mdata = { 0 };
+ struct fwu_data *data = fwu_get_data();
+ struct udevice *fwu_dev = fwu_get_dev();
+
+ if (data->metadata_size) {
+ *mdata_size = data->metadata_size;
+ return 0;
+ }
+
+ ret = fwu_read_mdata(fwu_dev, &mdata, 1,
+ sizeof(struct fwu_mdata));
+ if (ret) {
+ log_err("FWU metadata read failed\n");
+ return ret;
+ }
+
+ *mdata_size = mdata.metadata_size;
+ if (!*mdata_size)
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * fwu_init() - FWU specific initialisations
+ *
+ * Carry out some FWU specific initialisations including allocation
+ * of memory for the metadata copies, and reading the FWU metadata
+ * copies into the allocated memory. The metadata fields are then
+ * copied into a version agnostic structure.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int fwu_init(void)
+{
+ int ret;
+ struct fwu_mdata mdata = { 0 };
+ struct udevice *fwu_dev = fwu_get_dev();
+
+ /*
+ * First we read only the top level structure
+ * and get the size of the complete structure.
+ */
+ ret = fwu_read_mdata(fwu_dev, &mdata, 1,
+ sizeof(struct fwu_mdata));
+ if (ret) {
+ log_err("FWU metadata read failed\n");
+ return ret;
+ }
+
+ ret = fwu_mdata_copies_allocate(mdata.metadata_size);
+ if (ret)
+ return ret;
+
+ /*
+ * Now read the entire structure, both copies, and
+ * validate that the copies.
+ */
+ ret = fwu_get_mdata(NULL);
+ if (ret)
+ return ret;
+
+ ret = fwu_mdata_sanity_checks();
+ if (ret)
+ return ret;
+
+ fwu_data_init();
+
+ return 0;
+}
#include <hexdump.h>
#include <mapmem.h>
-#include <vsprintf.h>
+#include <stdio.h>
#include <linux/ctype.h>
#include <linux/compat.h>
#include <linux/log2.h>
* initialization constants.
*/
void
-MD5Init(struct MD5Context *ctx)
+MD5Init(MD5Context *ctx)
{
ctx->buf[0] = 0x67452301;
ctx->buf[1] = 0xefcdab89;
* of bytes.
*/
void
-MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len)
+MD5Update(MD5Context *ctx, unsigned char const *buf, unsigned int len)
{
register __u32 t;
* 1 0* (64-bit count of bits processed, MSB-first)
*/
void
-MD5Final(unsigned char digest[16], struct MD5Context *ctx)
+MD5Final(unsigned char digest[16], MD5Context *ctx)
{
unsigned int count;
unsigned char *p;
void
md5 (unsigned char *input, int len, unsigned char output[16])
{
- struct MD5Context context;
+ MD5Context context;
MD5Init(&context);
MD5Update(&context, input, len);
md5_wd(const unsigned char *input, unsigned int len, unsigned char output[16],
unsigned int chunk_sz)
{
- struct MD5Context context;
+ MD5Context context;
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
const unsigned char *end, *curr;
int chunk;
#include "tpm-utils.h"
-const enum tpm2_algorithms tpm2_supported_algorithms[4] = {
- TPM2_ALG_SHA1,
- TPM2_ALG_SHA256,
- TPM2_ALG_SHA384,
- TPM2_ALG_SHA512,
-};
-
int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks)
{
u32 supported = 0;
return rc;
digest_list->count = 0;
- for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) {
- u32 mask =
- tpm2_algorithm_to_mask(tpm2_supported_algorithms[i]);
-
- if (!(active & mask))
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) {
+ if (!(active & hash_algo_list[i].hash_mask))
continue;
- switch (tpm2_supported_algorithms[i]) {
+ switch (hash_algo_list[i].hash_alg) {
case TPM2_ALG_SHA1:
sha1_starts(&ctx);
sha1_update(&ctx, input, length);
break;
default:
printf("%s: unsupported algorithm %x\n", __func__,
- tpm2_supported_algorithms[i]);
+ hash_algo_list[i].hash_alg);
continue;
}
digest_list->digests[digest_list->count].hash_alg =
- tpm2_supported_algorithms[i];
+ hash_algo_list[i].hash_alg;
memcpy(&digest_list->digests[digest_list->count].digest, final,
len);
digest_list->count++;
u32 count = 0;
u32 log_size;
u32 active;
- u32 mask;
size_t i;
u16 len;
int rc;
return rc;
event_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes);
- for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) {
- mask = tpm2_algorithm_to_mask(tpm2_supported_algorithms[i]);
-
- if (!(active & mask))
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) {
+ if (!(active & hash_algo_list[i].hash_mask))
continue;
- switch (tpm2_supported_algorithms[i]) {
+ switch (hash_algo_list[i].hash_alg) {
case TPM2_ALG_SHA1:
case TPM2_ALG_SHA256:
case TPM2_ALG_SHA384:
put_unaligned_le32(count, &ev->number_of_algorithms);
count = 0;
- for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) {
- mask = tpm2_algorithm_to_mask(tpm2_supported_algorithms[i]);
-
- if (!(active & mask))
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) {
+ if (!(active & hash_algo_list[i].hash_mask))
continue;
- len = tpm2_algorithm_to_len(tpm2_supported_algorithms[i]);
+ len = hash_algo_list[i].hash_len;
if (!len)
continue;
- put_unaligned_le16(tpm2_supported_algorithms[i],
+ put_unaligned_le16(hash_algo_list[i].hash_alg,
&ev->digest_sizes[count].algorithm_id);
put_unaligned_le16(len, &ev->digest_sizes[count].digest_size);
count++;
pos = offsetof(struct tcg_pcr_event2, digests) +
offsetof(struct tpml_digest_values, count);
count = get_unaligned_le32(log + pos);
- if (count > ARRAY_SIZE(tpm2_supported_algorithms) ||
+ if (count > ARRAY_SIZE(hash_algo_list) ||
(digest_list->count && digest_list->count != count))
return 0;
return 0;
count = get_unaligned_le32(&event->number_of_algorithms);
- if (count > ARRAY_SIZE(tpm2_supported_algorithms))
+ if (count > ARRAY_SIZE(hash_algo_list))
return 0;
calc_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes) +
* We only support 5 algorithms for now so check against that
* instead of TPM2_NUM_PCR_BANKS
*/
- if (pcrs.count > ARRAY_SIZE(tpm2_supported_algorithms) ||
+ if (pcrs.count > ARRAY_SIZE(hash_algo_list) ||
pcrs.count < 1) {
printf("%s: too many pcrs: %u\n", __func__, pcrs.count);
return -EMSGSIZE;
return 0;
}
+
+enum tpm2_algorithms tpm2_name_to_algorithm(const char *name)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) {
+ if (!strcasecmp(name, hash_algo_list[i].hash_name))
+ return hash_algo_list[i].hash_alg;
+ }
+ printf("%s: unsupported algorithm %s\n", __func__, name);
+
+ return -EINVAL;
+}
+
+const char *tpm2_algorithm_name(enum tpm2_algorithms algo)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); ++i) {
+ if (hash_algo_list[i].hash_alg == algo)
+ return hash_algo_list[i].hash_name;
+ }
+
+ return "";
+}
+
+u32 tpm2_algorithm_to_mask(enum tpm2_algorithms algo)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(hash_algo_list); i++) {
+ if (hash_algo_list[i].hash_alg == algo)
+ return hash_algo_list[i].hash_mask;
+ }
+
+ return 0;
+}
#include <hexdump.h>
#include <stdarg.h>
#include <uuid.h>
+#include <stdio.h>
#include <vsprintf.h>
#include <linux/ctype.h>
#include <linux/err.h>
# SPDX-License-Identifier: GPL-2.0
#
# This scripts adds local version information from the version
-# control systems git, mercurial (hg) and subversion (svn).
+# control system git.
#
# If something goes wrong, send a mail the kernel build mailinglist
# (see MAINTAINERS) and CC Nico Schottelius
#
usage() {
- echo "Usage: $0 [--save-scmversion] [srctree]" >&2
+ echo "Usage: $0 [--no-local] [srctree]" >&2
exit 1
}
-scm_only=false
-srctree=.
-if test "$1" = "--save-scmversion"; then
- scm_only=true
+no_local=false
+if test "$1" = "--no-local"; then
+ no_local=true
shift
fi
+
+srctree=.
if test $# -gt 0; then
srctree=$1
shift
scm_version()
{
- local short
- short=false
+ local short=false
+ local no_dirty=false
+ local tag
+
+ while [ $# -gt 0 ];
+ do
+ case "$1" in
+ --short)
+ short=true;;
+ --no-dirty)
+ no_dirty=true;;
+ esac
+ shift
+ done
cd "$srctree"
- if test -e .scmversion; then
- cat .scmversion
+
+ if test -n "$(git rev-parse --show-cdup 2>/dev/null)"; then
return
fi
- if test "$1" = "--short"; then
- short=true
- fi
- # Check for git and a git repo.
- if test -z "$(git rev-parse --show-cdup 2>/dev/null)" &&
- head=$(git rev-parse --verify --short HEAD 2>/dev/null); then
-
- # If we are at a tagged commit (like "v2.6.30-rc6"), we ignore
- # it, because this version is defined in the top level Makefile.
- if [ -z "$(git describe --exact-match 2>/dev/null)" ]; then
-
- # If only the short version is requested, don't bother
- # running further git commands
- if $short; then
- echo "+"
- return
- fi
- # If we are past a tagged commit (like
- # "v2.6.30-rc5-302-g72357d5"), we pretty print it.
- if atag="$(git describe 2>/dev/null)"; then
- echo "$atag" | awk -F- '{printf("-%05d-%s", $(NF-1),$(NF))}'
-
- # If we don't have a tag at all we print -g{commitish}.
- else
- printf '%s%s' -g $head
- fi
- fi
+ if ! head=$(git rev-parse --verify HEAD 2>/dev/null); then
+ return
+ fi
- # Is this git on svn?
- if git config --get svn-remote.svn.url >/dev/null; then
- printf -- '-svn%s' "$(git svn find-rev $head)"
- fi
+ # mainline kernel: 6.2.0-rc5 -> v6.2-rc5
+ # stable kernel: 6.1.7 -> v6.1.7
+ version_tag=v$(echo "${KERNELVERSION}" | sed -E 's/^([0-9]+\.[0-9]+)\.0(.*)$/\1\2/')
+
+ # If a localversion* file exists, and the corresponding
+ # annotated tag exists and is an ancestor of HEAD, use
+ # it. This is the case in linux-next.
+ tag=${file_localversion#-}
+ desc=
+ if [ -n "${tag}" ]; then
+ desc=$(git describe --match=$tag 2>/dev/null)
+ fi
- # Check for uncommitted changes.
- # First, with git-status, but --no-optional-locks is only
- # supported in git >= 2.14, so fall back to git-diff-index if
- # it fails. Note that git-diff-index does not refresh the
- # index, so it may give misleading results. See
- # git-update-index(1), git-diff-index(1), and git-status(1).
- if {
- git --no-optional-locks status -uno --porcelain 2>/dev/null ||
- git diff-index --name-only HEAD
- } | grep -qvE '^(.. )?scripts/package'; then
- printf '%s' -dirty
- fi
+ # Otherwise, if a localversion* file exists, and the tag
+ # obtained by appending it to the tag derived from
+ # KERNELVERSION exists and is an ancestor of HEAD, use
+ # it. This is e.g. the case in linux-rt.
+ if [ -z "${desc}" ] && [ -n "${file_localversion}" ]; then
+ tag="${version_tag}${file_localversion}"
+ desc=$(git describe --match=$tag 2>/dev/null)
+ fi
- # All done with git
- return
+ # Otherwise, default to the annotated tag derived from KERNELVERSION.
+ if [ -z "${desc}" ]; then
+ tag="${version_tag}"
+ desc=$(git describe --match=$tag 2>/dev/null)
fi
- # Check for mercurial and a mercurial repo.
- if test -d .hg && hgid=$(hg id 2>/dev/null); then
- # Do we have an tagged version? If so, latesttagdistance == 1
- if [ "$(hg log -r . --template '{latesttagdistance}')" = "1" ]; then
- id=$(hg log -r . --template '{latesttag}')
- printf '%s%s' -hg "$id"
- else
- tag=$(printf '%s' "$hgid" | cut -d' ' -f2)
- if [ -z "$tag" -o "$tag" = tip ]; then
- id=$(printf '%s' "$hgid" | sed 's/[+ ].*//')
- printf '%s%s' -hg "$id"
- fi
+ # If we are at the tagged commit, we ignore it because the version is
+ # well-defined.
+ if [ "${tag}" != "${desc}" ]; then
+
+ # If only the short version is requested, don't bother
+ # running further git commands
+ if $short; then
+ echo "+"
+ return
+ fi
+ # If we are past the tagged commit, we pretty print it.
+ # (like 6.1.0-14595-g292a089d78d3)
+ if [ -n "${desc}" ]; then
+ echo "${desc}" | awk -F- '{printf("-%05d", $(NF-1))}'
fi
- # Are there uncommitted changes?
- # These are represented by + after the changeset id.
- case "$hgid" in
- *+|*+\ *) printf '%s' -dirty ;;
- esac
+ # Add -g and exactly 12 hex chars.
+ printf '%s%s' -g "$(echo $head | cut -c1-12)"
+ fi
- # All done with mercurial
+ if ${no_dirty}; then
return
fi
- # Check for svn and a svn repo.
- if rev=$(LANG= LC_ALL= LC_MESSAGES=C svn info 2>/dev/null | grep '^Last Changed Rev'); then
- rev=$(echo $rev | awk '{print $NF}')
- printf -- '-svn%s' "$rev"
-
- # All done with svn
- return
+ # Check for uncommitted changes.
+ # This script must avoid any write attempt to the source tree, which
+ # might be read-only.
+ # You cannot use 'git describe --dirty' because it tries to create
+ # .git/index.lock .
+ # First, with git-status, but --no-optional-locks is only supported in
+ # git >= 2.14, so fall back to git-diff-index if it fails. Note that
+ # git-diff-index does not refresh the index, so it may give misleading
+ # results.
+ # See git-update-index(1), git-diff-index(1), and git-status(1).
+ if {
+ git --no-optional-locks status -uno --porcelain 2>/dev/null ||
+ git diff-index --name-only HEAD
+ } | read dummy; then
+ printf '%s' -dirty
fi
}
echo "$res"
}
-if $scm_only; then
- if test ! -e .scmversion; then
- res=$(scm_version)
- echo "$res" >.scmversion
- fi
- exit
-fi
-
-if test -e include/config/auto.conf; then
- # We are interested only in CONFIG_LOCALVERSION and
- # CONFIG_LOCALVERSION_AUTO, so extract these in a safe
- # way (i.e. w/o sourcing auto.conf)
- # xargs echo removes quotes
- CONFIG_LOCALVERSION=`cat include/config/auto.conf | awk -F '=' '/^CONFIG_LOCALVERSION=/ {print $2}' | xargs echo`
- CONFIG_LOCALVERSION_AUTO=`cat include/config/auto.conf | awk -F '=' '/^CONFIG_LOCALVERSION_AUTO=/ {print $2}' | xargs echo`
-else
- echo "Error: kernelrelease not valid - run 'make prepare' to update it" >&2
+if [ -z "${KERNELVERSION}" ]; then
+ echo "KERNELVERSION is not set" >&2
exit 1
fi
# localversion* files in the build and source directory
-res="$(collect_files localversion*)"
+file_localversion="$(collect_files localversion*)"
if test ! "$srctree" -ef .; then
- res="$res$(collect_files "$srctree"/localversion*)"
+ file_localversion="${file_localversion}$(collect_files "$srctree"/localversion*)"
+fi
+
+if ${no_local}; then
+ echo "${KERNELVERSION}$(scm_version --no-dirty)"
+ exit 0
+fi
+
+if ! test -e include/config/auto.conf; then
+ echo "Error: kernelrelease not valid - run 'make prepare' to update it" >&2
+ exit 1
fi
-# CONFIG_LOCALVERSION and LOCALVERSION (if set)
-res="${res}${CONFIG_LOCALVERSION}${LOCALVERSION}"
+# version string from CONFIG_LOCALVERSION
+config_localversion=$(sed -n 's/^CONFIG_LOCALVERSION=\(.*\)$/\1/p' include/config/auto.conf | tr -d '"')
-# scm version string if not at a tagged commit
-if test "$CONFIG_LOCALVERSION_AUTO" = "y"; then
+# scm version string if not at the kernel version tag or at the file_localversion
+if grep -q "^CONFIG_LOCALVERSION_AUTO=y$" include/config/auto.conf; then
# full scm version string
- res="$res$(scm_version)"
-else
- # append a plus sign if the repository is not in a clean
- # annotated or signed tagged state (as git describe only
- # looks at signed or annotated tags - git tag -a/-s) and
- # LOCALVERSION= is not specified
- if test "${LOCALVERSION+set}" != "set"; then
- scm=$(scm_version --short)
- res="$res${scm:++}"
- fi
+ scm_version="$(scm_version)"
+elif [ "${LOCALVERSION+set}" != "set" ]; then
+ # If the variable LOCALVERSION is not set, append a plus
+ # sign if the repository is not in a clean annotated or
+ # signed tagged state (as git describe only looks at signed
+ # or annotated tags - git tag -a/-s).
+ #
+ # If the variable LOCALVERSION is set (including being set
+ # to an empty string), we don't want to append a plus sign.
+ scm_version="$(scm_version --short)"
fi
-echo "$res"
+echo "${KERNELVERSION}${file_localversion}${config_localversion}${LOCALVERSION}${scm_version}"
struct udevice *dev;
struct fwu_mdata mdata = { 0 };
+ ut_assertok(setup_blk_device(uts));
+ ut_assertok(populate_mmc_disk_image(uts));
+ ut_assertok(write_mmc_blk_device(uts));
+
/*
* Trigger lib/fwu_updates/fwu.c fwu_boottime_checks()
* to populate g_dev global pointer in that library.
event_notify_null(EVT_MAIN_LOOP);
ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev));
- ut_assertok(setup_blk_device(uts));
- ut_assertok(populate_mmc_disk_image(uts));
- ut_assertok(write_mmc_blk_device(uts));
+ ut_assertok(fwu_init());
ut_assertok(fwu_get_mdata(&mdata));
struct udevice *dev;
struct fwu_mdata mdata = { 0 };
+ ut_assertok(setup_blk_device(uts));
+ ut_assertok(populate_mmc_disk_image(uts));
+ ut_assertok(write_mmc_blk_device(uts));
+
/*
* Trigger lib/fwu_updates/fwu.c fwu_boottime_checks()
* to populate g_dev global pointer in that library.
*/
event_notify_null(EVT_MAIN_LOOP);
- ut_assertok(setup_blk_device(uts));
- ut_assertok(populate_mmc_disk_image(uts));
- ut_assertok(write_mmc_blk_device(uts));
ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev));
+ ut_assertok(fwu_init());
ut_assertok(fwu_get_mdata(&mdata));
active_idx = (mdata.active_index + 1) % CONFIG_FWU_NUM_BANKS;
#include <scmi_agent.h>
#include <scmi_agent-uclass.h>
#include <scmi_protocols.h>
-#include <vsprintf.h>
+#include <stdio.h>
#include <asm/scmi_test.h>
#include <dm/device-internal.h>
#include <dm/test.h>
#include <log.h>
#include <mapmem.h>
#include <version_string.h>
+#include <stdio.h>
#include <vsprintf.h>
#include <test/suites.h>
#include <test/test.h>
updates = int(re.findall(r'\d+', str)[0])
# Check the output value
- assert 'PCR #10 content' in read_pcr
+ assert 'PCR #10 sha256 32 byte content' in read_pcr
assert '00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00' in read_pcr
@pytest.mark.buildconfigspec('cmd_tpm_v2')
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2024 Marek Vasut <marex@denx.de>
+#
+"""Bintool implementation for cst"""
+
+import re
+
+from binman import bintool
+
+class Bintoolcst(bintool.Bintool):
+ """Image generation for U-Boot
+
+ This bintool supports running `cst` with some basic parameters as
+ needed by binman.
+ """
+ def __init__(self, name):
+ super().__init__(name, 'Sign NXP i.MX image')
+
+ # pylint: disable=R0913
+ def run(self, output_fname=None):
+ """Run cst
+
+ Args:
+ output_fname: Output filename to write to
+ """
+ args = []
+ if output_fname:
+ args += ['-o', output_fname]
+ return self.run_cmd(*args)
+
+ def fetch(self, method):
+ """Fetch handler for cst
+
+ This installs cst using the apt utility.
+
+ Args:
+ method (FETCH_...): Method to use
+
+ Returns:
+ True if the file was fetched and now installed, None if a method
+ other than FETCH_BIN was requested
+
+ Raises:
+ Valuerror: Fetching could not be completed
+ """
+ if method != bintool.FETCH_BIN:
+ return None
+ return self.apt_install('imx-code-signing-tool')
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2023-2024 Marek Vasut <marex@denx.de>
+# Written with much help from Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for generating the i.MX8M code signing tool
+# input configuration file and invocation of cst on generated
+# input configuration file and input data to be signed.
+#
+
+import configparser
+import os
+import struct
+
+from collections import OrderedDict
+
+from binman.entry import Entry
+from binman.etype.mkimage import Entry_mkimage
+from binman.etype.section import Entry_section
+from binman import elf
+from dtoc import fdt_util
+from u_boot_pylib import tools
+
+MAGIC_NXP_IMX_IVT = 0x412000d1
+MAGIC_FITIMAGE = 0xedfe0dd0
+
+csf_config_template = """
+[Header]
+ Version = 4.3
+ Hash Algorithm = sha256
+ Engine = CAAM
+ Engine Configuration = 0
+ Certificate Format = X509
+ Signature Format = CMS
+
+[Install SRK]
+ File = "SRK_1_2_3_4_table.bin"
+ Source index = 0
+
+[Install CSFK]
+ File = "CSF1_1_sha256_4096_65537_v3_usr_crt.pem"
+
+[Authenticate CSF]
+
+[Unlock]
+ Engine = CAAM
+ Features = MID
+
+[Install Key]
+ Verification index = 0
+ Target Index = 2
+ File = "IMG1_1_sha256_4096_65537_v3_usr_crt.pem"
+
+[Authenticate Data]
+ Verification index = 2
+ Blocks = 0x1234 0x78 0xabcd "data.bin"
+"""
+
+class Entry_nxp_imx8mcst(Entry_mkimage):
+ """NXP i.MX8M CST .cfg file generator and cst invoker
+
+ Properties / Entry arguments:
+ - nxp,loader-address - loader address (SPL text base)
+ """
+
+ def __init__(self, section, etype, node):
+ super().__init__(section, etype, node)
+ self.required_props = ['nxp,loader-address']
+
+ def ReadNode(self):
+ super().ReadNode()
+ self.loader_address = fdt_util.GetInt(self._node, 'nxp,loader-address')
+ self.srk_table = os.getenv('SRK_TABLE', fdt_util.GetString(self._node, 'nxp,srk-table', 'SRK_1_2_3_4_table.bin'))
+ self.csf_crt = os.getenv('CSF_KEY', fdt_util.GetString(self._node, 'nxp,csf-crt', 'CSF1_1_sha256_4096_65537_v3_usr_crt.pem'))
+ self.img_crt = os.getenv('IMG_KEY', fdt_util.GetString(self._node, 'nxp,img-crt', 'IMG1_1_sha256_4096_65537_v3_usr_crt.pem'))
+ self.unlock = fdt_util.GetBool(self._node, 'nxp,unlock')
+ self.ReadEntries()
+
+ def BuildSectionData(self, required):
+ data, input_fname, uniq = self.collect_contents_to_file(
+ self._entries.values(), 'input')
+
+ # Parse the input data and figure out what it is that is being signed.
+ # - If it is mkimage'd imx8mimage, then extract to be signed data size
+ # from imx8mimage header, and calculate CSF blob offset right past
+ # the SPL from this information.
+ # - If it is fitImage, then pad the image to 4k, add generated IVT and
+ # sign the whole payload, then append CSF blob at the end right past
+ # the IVT.
+ signtype = struct.unpack('<I', data[:4])[0]
+ signbase = self.loader_address
+ signsize = 0
+ if signtype == MAGIC_NXP_IMX_IVT: # SPL/imx8mimage
+ # Sign the payload including imx8mimage header
+ # (extra 0x40 bytes before the payload)
+ signbase -= 0x40
+ signsize = struct.unpack('<I', data[24:28])[0] - signbase
+ # Remove mkimage generated padding from the end of data
+ data = data[:signsize]
+ elif signtype == MAGIC_FITIMAGE: # fitImage
+ # Align fitImage to 4k
+ signsize = tools.align(len(data), 0x1000)
+ data += tools.get_bytes(0, signsize - len(data))
+ # Add generated IVT
+ data += struct.pack('<I', MAGIC_NXP_IMX_IVT)
+ data += struct.pack('<I', signbase + signsize) # IVT base
+ data += struct.pack('<I', 0)
+ data += struct.pack('<I', 0)
+ data += struct.pack('<I', 0)
+ data += struct.pack('<I', signbase + signsize) # IVT base
+ data += struct.pack('<I', signbase + signsize + 0x20) # CSF base
+ data += struct.pack('<I', 0)
+ else:
+ # Unknown section type, pass input data through.
+ return data
+
+ # Write out customized data to be signed
+ output_dname = tools.get_output_filename(f'nxp.cst-input-data.{uniq}')
+ tools.write_file(output_dname, data)
+
+ # Generate CST configuration file used to sign payload
+ cfg_fname = tools.get_output_filename('nxp.csf-config-txt.%s' % uniq)
+ config = configparser.ConfigParser()
+ # Do not make key names lowercase
+ config.optionxform = str
+ # Load configuration template and modify keys of interest
+ config.read_string(csf_config_template)
+ config['Install SRK']['File'] = '"' + self.srk_table + '"'
+ config['Install CSFK']['File'] = '"' + self.csf_crt + '"'
+ config['Install Key']['File'] = '"' + self.img_crt + '"'
+ config['Authenticate Data']['Blocks'] = hex(signbase) + ' 0 ' + hex(len(data)) + ' "' + str(output_dname) + '"'
+ if not self.unlock:
+ config.remove_section('Unlock')
+ with open(cfg_fname, 'w') as cfgf:
+ config.write(cfgf)
+
+ output_fname = tools.get_output_filename(f'nxp.csf-output-blob.{uniq}')
+ args = ['-i', cfg_fname, '-o', output_fname]
+ if self.cst.run_cmd(*args) is not None:
+ outdata = tools.read_file(output_fname)
+ return data + outdata
+ else:
+ # Bintool is missing; just use the input data as the output
+ self.record_missing_bintool(self.cst)
+ return data
+
+ def SetImagePos(self, image_pos):
+ # Customized SoC specific SetImagePos which skips the mkimage etype
+ # implementation and removes the 0x48 offset introduced there. That
+ # offset is only used for uImage/fitImage, which is not the case in
+ # here.
+ upto = 0x00
+ for entry in super().GetEntries().values():
+ entry.SetOffsetSize(upto, None)
+
+ # Give up if any entries lack a size
+ if entry.size is None:
+ return
+ upto += entry.size
+
+ Entry_section.SetImagePos(self, image_pos)
+
+ def AddBintools(self, btools):
+ super().AddBintools(btools)
+ self.cst = self.AddBintool(btools, 'cst')
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
-#include <u-boot/crc.h>
#include <unistd.h>
+#include <generated/autoconf.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <u-boot/crc.h>
#include <uuid/uuid.h>
-/* This will dynamically allocate the fwu_mdata */
-#define CONFIG_FWU_NUM_BANKS 0
-#define CONFIG_FWU_NUM_IMAGES_PER_BANK 0
-
-/* Since we can not include fwu.h, redefine version here. */
-#define FWU_MDATA_VERSION 1
-
typedef uint8_t u8;
typedef int16_t s16;
typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
-#include <fwu_mdata.h>
+#undef CONFIG_FWU_NUM_BANKS
+#undef CONFIG_FWU_NUM_IMAGES_PER_BANK
-/* TODO: Endianness conversion may be required for some arch. */
+/* This will dynamically allocate the fwu_mdata */
+#define CONFIG_FWU_NUM_BANKS 0
+#define CONFIG_FWU_NUM_IMAGES_PER_BANK 0
+
+/* version 2 supports maximum of 4 banks */
+#define MAX_BANKS_V2 4
+
+#define BANK_INVALID (u8)0xFF
+#define BANK_ACCEPTED (u8)0xFC
-static const char *opts_short = "b:i:a:p:gh";
+#include <fwu_mdata.h>
+
+static const char *opts_short = "b:i:a:p:v:V:gh";
static struct option options[] = {
{"banks", required_argument, NULL, 'b'},
{"guid", required_argument, NULL, 'g'},
{"active-bank", required_argument, NULL, 'a'},
{"previous-bank", required_argument, NULL, 'p'},
+ {"version", required_argument, NULL, 'v'},
+ {"vendor-file", required_argument, NULL, 'V'},
{"help", no_argument, NULL, 'h'},
{NULL, 0, NULL, 0},
};
fprintf(stderr, "Options:\n"
"\t-i, --images <num> Number of images (mandatory)\n"
"\t-b, --banks <num> Number of banks (mandatory)\n"
+ "\t-v, --version Metadata version (mandatory)\n"
"\t-a, --active-bank <num> Active bank (default=0)\n"
"\t-p, --previous-bank <num> Previous active bank (default=active_bank - 1)\n"
"\t-g, --guid Use GUID instead of UUID\n"
+ "\t-V, --vendor-file Vendor data file to append to the metadata\n"
"\t-h, --help print a help message\n"
);
fprintf(stderr, " UUIDs list syntax:\n"
size_t images;
size_t banks;
size_t size;
+ u8 version;
+ size_t vsize;
+ void *vbuf;
struct fwu_mdata *mdata;
};
static int previous_bank, active_bank;
static bool __use_guid;
-static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks)
+static bool supported_mdata_version(unsigned long version)
+{
+ switch (version) {
+ case 1:
+ case 2:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks,
+ u8 version, size_t vendor_size)
{
struct fwu_mdata_object *mobj;
if (!mobj)
return NULL;
- mobj->size = sizeof(struct fwu_mdata) +
- (sizeof(struct fwu_image_entry) +
- sizeof(struct fwu_image_bank_info) * banks) * images;
+ if (version == 1) {
+ mobj->size = sizeof(struct fwu_mdata) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * banks) * images;
+ } else {
+ mobj->size = sizeof(struct fwu_mdata) +
+ sizeof(struct fwu_fw_store_desc) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * banks) * images;
+
+ mobj->size += vendor_size;
+ mobj->vsize = vendor_size;
+ }
+
mobj->images = images;
mobj->banks = banks;
+ mobj->version = version;
mobj->mdata = calloc(1, mobj->size);
- if (!mobj->mdata) {
- free(mobj);
- return NULL;
+ if (!mobj->mdata)
+ goto alloc_err;
+
+ if (vendor_size) {
+ mobj->vbuf = calloc(1, mobj->vsize);
+ if (!mobj->vbuf)
+ goto alloc_err;
}
return mobj;
+
+alloc_err:
+ free(mobj->mdata);
+ free(mobj);
+ return NULL;
}
static struct fwu_image_entry *
{
size_t offset;
- offset = sizeof(struct fwu_mdata) +
- (sizeof(struct fwu_image_entry) +
- sizeof(struct fwu_image_bank_info) * mobj->banks) * idx;
+ if (mobj->version == 1) {
+ offset = sizeof(struct fwu_mdata) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * mobj->banks) *
+ idx;
+ } else {
+ offset = sizeof(struct fwu_mdata) +
+ sizeof(struct fwu_fw_store_desc) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * mobj->banks) *
+ idx;
+ }
return (struct fwu_image_entry *)((char *)mobj->mdata + offset);
}
{
size_t offset;
- offset = sizeof(struct fwu_mdata) +
- (sizeof(struct fwu_image_entry) +
- sizeof(struct fwu_image_bank_info) * mobj->banks) * img_idx +
- sizeof(struct fwu_image_entry) +
- sizeof(struct fwu_image_bank_info) * bnk_idx;
+ if (mobj->version == 1) {
+ offset = sizeof(struct fwu_mdata) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * mobj->banks) *
+ img_idx + sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * bnk_idx;
+ } else {
+ offset = sizeof(struct fwu_mdata) +
+ sizeof(struct fwu_fw_store_desc) +
+ (sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * mobj->banks) *
+ img_idx + sizeof(struct fwu_image_entry) +
+ sizeof(struct fwu_image_bank_info) * bnk_idx;
+ }
return (struct fwu_image_bank_info *)((char *)mobj->mdata + offset);
}
return -EINVAL;
if (strcmp(uuid, "0") &&
- uuid_guid_parse(uuid, (unsigned char *)&image->location_uuid) < 0)
+ uuid_guid_parse(uuid, (unsigned char *)&image->location_guid) < 0)
return -EINVAL;
/* Image type UUID */
if (!uuid)
return -EINVAL;
- if (uuid_guid_parse(uuid, (unsigned char *)&image->image_type_uuid) < 0)
+ if (uuid_guid_parse(uuid, (unsigned char *)&image->image_type_guid) < 0)
return -EINVAL;
/* Fill bank image-UUID */
return -EINVAL;
if (strcmp(uuid, "0") &&
- uuid_guid_parse(uuid, (unsigned char *)&bank->image_uuid) < 0)
+ uuid_guid_parse(uuid, (unsigned char *)&bank->image_guid) < 0)
return -EINVAL;
}
return 0;
}
+#if defined(CONFIG_FWU_MDATA_V1)
+static void fwu_fill_version_specific_mdata(struct fwu_mdata_object *mobj)
+{
+}
+#else
+static void fwu_fill_version_specific_mdata(struct fwu_mdata_object *mobj)
+{
+ int i;
+ struct fwu_fw_store_desc *fw_desc;
+ struct fwu_mdata *mdata = mobj->mdata;
+
+ mdata->metadata_size = mobj->size;
+ mdata->desc_offset = sizeof(struct fwu_mdata);
+
+ for (i = 0; i < MAX_BANKS_V2; i++)
+ mdata->bank_state[i] = i < mobj->banks ?
+ BANK_ACCEPTED : BANK_INVALID;
+
+ fw_desc = (struct fwu_fw_store_desc *)((u8 *)mdata + sizeof(*mdata));
+ fw_desc->num_banks = mobj->banks;
+ fw_desc->num_images = mobj->images;
+ fw_desc->img_entry_size = sizeof(struct fwu_image_entry) +
+ (sizeof(struct fwu_image_bank_info) * mobj->banks);
+ fw_desc->bank_info_entry_size =
+ sizeof(struct fwu_image_bank_info);
+}
+#endif /* CONFIG_FWU_MDATA_V1 */
+
/* Caller must ensure that @uuids[] has @mobj->images entries. */
static int fwu_parse_fill_uuids(struct fwu_mdata_object *mobj, char *uuids[])
{
struct fwu_mdata *mdata = mobj->mdata;
+ char *vdata;
int i, ret;
- mdata->version = FWU_MDATA_VERSION;
+ mdata->version = mobj->version;
mdata->active_index = active_bank;
mdata->previous_active_index = previous_bank;
+ fwu_fill_version_specific_mdata(mobj);
+
for (i = 0; i < mobj->images; i++) {
ret = fwu_parse_fill_image_uuid(mobj, i, uuids[i]);
if (ret < 0)
return ret;
}
+ if (mobj->vsize) {
+ vdata = (char *)mobj->mdata + (mobj->size - mobj->vsize);
+ memcpy(vdata, mobj->vbuf, mobj->vsize);
+ }
+
mdata->crc32 = crc32(0, (const unsigned char *)&mdata->version,
mobj->size - sizeof(uint32_t));
return 0;
}
-static int
-fwu_make_mdata(size_t images, size_t banks, char *uuids[], char *output)
+static int fwu_read_vendor_data(struct fwu_mdata_object *mobj,
+ const char *vendor_file)
+{
+ int ret = 0;
+ FILE *vfile = NULL;
+
+ vfile = fopen(vendor_file, "r");
+ if (!vfile) {
+ ret = -1;
+ goto out;
+ }
+
+ if (fread(mobj->vbuf, 1, mobj->vsize, vfile) != mobj->vsize)
+ ret = -1;
+
+out:
+ fclose(vfile);
+ return ret;
+}
+
+static int fwu_make_mdata(size_t images, size_t banks, u8 version,
+ const char *vendor_file, char *uuids[],
+ char *output)
{
- struct fwu_mdata_object *mobj;
- FILE *file;
int ret;
+ FILE *file;
+ struct stat sbuf;
+ size_t vendor_size = 0;
+ struct fwu_mdata_object *mobj;
+
+ if (vendor_file) {
+ ret = stat(vendor_file, &sbuf);
+ if (ret)
+ return -errno;
- mobj = fwu_alloc_mdata(images, banks);
+ vendor_size = sbuf.st_size;
+ }
+
+ mobj = fwu_alloc_mdata(images, banks, version, vendor_size);
if (!mobj)
return -ENOMEM;
+ if (vendor_file) {
+ ret = fwu_read_vendor_data(mobj, vendor_file);
+ if (ret)
+ goto done_make;
+ }
+
ret = fwu_parse_fill_uuids(mobj, uuids);
if (ret < 0)
goto done_make;
goto done_make;
}
- ret = fwrite(mobj->mdata, mobj->size, 1, file);
+ ret = fwrite(mobj->mdata, 1, mobj->size, file);
if (ret != mobj->size)
ret = -errno;
else
done_make:
free(mobj->mdata);
+ free(mobj->vbuf);
free(mobj);
return ret;
int main(int argc, char *argv[])
{
- unsigned long banks = 0, images = 0;
+ unsigned long banks = 0, images = 0, version = 0;
int c, ret;
+ const char *vendor_file;
/* Explicitly initialize defaults */
active_bank = 0;
__use_guid = false;
previous_bank = INT_MAX;
+ vendor_file = NULL;
do {
c = getopt_long(argc, argv, opts_short, options, NULL);
case 'a':
active_bank = strtoul(optarg, NULL, 0);
break;
+ case 'v':
+ version = strtoul(optarg, NULL, 0);
+ break;
+ case 'V':
+ vendor_file = optarg;
+ break;
}
} while (c != -1);
return -EINVAL;
}
+ if (!version || !supported_mdata_version(version)) {
+ fprintf(stderr, "Error: Version value can only be either 1 or 2, not %ld.\n",
+ version);
+ return -EINVAL;
+ }
+
+ if (version == 1 && vendor_file) {
+ fprintf(stderr, "Error: Vendor Data can only be appended in version 2 of FWU Metadata.\n");
+ return -EINVAL;
+ }
+
/* This command takes UUIDs * images and output file. */
if (optind + images + 1 != argc) {
fprintf(stderr, "Error: UUID list or output file is not specified or too much.\n");
previous_bank = active_bank > 0 ? active_bank - 1 : banks - 1;
}
- ret = fwu_make_mdata(images, banks, argv + optind, argv[argc - 1]);
+ ret = fwu_make_mdata(images, banks, (u8)version, vendor_file,
+ argv + optind, argv[argc - 1]);
if (ret < 0)
fprintf(stderr, "Error: Failed to parse and write image: %s\n",
strerror(-ret));
projects / thirdparty / u-boot.git / commitdiff
