static void rtl930x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
{
h->cpu_tag[0] = 0x8000; /* CPU tag marker */
- h->cpu_tag[1] = 0x0200; /* Set FWD_TYPE to LOGICAL (2) */
+
+ h->cpu_tag[1] = FIELD_PREP(RTL93XX_CPU_TAG1_FWD_MASK,
+ RTL93XX_CPU_TAG1_FWD_LOGICAL);
+ h->cpu_tag[1] |= FIELD_PREP(RTL93XX_CPU_TAG1_IGNORE_STP_MASK, 1);
h->cpu_tag[2] = 0;
h->cpu_tag[3] = 0;
h->cpu_tag[4] = 0;
static void rtl931x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio)
{
h->cpu_tag[0] = 0x8000; /* CPU tag marker */
- h->cpu_tag[1] = 0x0200; /* Set FWD_TYPE to LOGICAL (2) */
+
+ h->cpu_tag[1] = FIELD_PREP(RTL93XX_CPU_TAG1_FWD_MASK,
+ RTL93XX_CPU_TAG1_FWD_LOGICAL);
+ h->cpu_tag[1] |= FIELD_PREP(RTL93XX_CPU_TAG1_IGNORE_STP_MASK, 1);
h->cpu_tag[2] = 0;
h->cpu_tag[3] = 0;
h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0;
/* Registers of the internal Serdes of the 8380 */
#define RTL838X_SDS4_FIB_REG0 (0xF800)
+/* shared CPU tag definitions for RTL930X/RTL931X */
+#define RTL93XX_CPU_TAG1_FWD_MASK GENMASK(11, 8)
+
+#define RTL93XX_CPU_TAG1_FWD_ALE 0
+#define RTL93XX_CPU_TAG1_FWD_PHYSICAL 1
+#define RTL93XX_CPU_TAG1_FWD_LOGICAL 2
+#define RTL93XX_CPU_TAG1_FWD_TRUNK 3
+#define RTL93XX_CPU_TAG1_FWD_ONE_HOP 4
+#define RTL93XX_CPU_TAG1_FWD_LOGICAL_ONE_HOP 5
+#define RTL93XX_CPU_TAG1_FWD_UCST_CPU_MIN_PORT 6
+#define RTL93XX_CPU_TAG1_FWD_UCST_CPU 7
+#define RTL93XX_CPU_TAG1_FWD_BCST_CPU 8
+
+#define RTL93XX_CPU_TAG1_IGNORE_STP_MASK GENMASK(2, 2)
+
/* Default MTU with jumbo frames support */
#define DEFAULT_MTU 9000