--- /dev/null
+From 1c687c0da9efb7c627793483a8927554764e7a55 Mon Sep 17 00:00:00 2001
+From: Shaoyun Liu <shaoyun.liu@amd.com>
+Date: Wed, 5 Feb 2025 13:16:45 -0500
+Subject: drm/amd/include : MES v11 and v12 API header update
+
+From: Shaoyun Liu <shaoyun.liu@amd.com>
+
+commit 1c687c0da9efb7c627793483a8927554764e7a55 upstream.
+
+MES requires driver set cleaner_shader_fence_mc_addr
+for cleaner shader support.
+
+Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/include/mes_v11_api_def.h | 3 ++-
+ drivers/gpu/drm/amd/include/mes_v12_api_def.h | 2 ++
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h
++++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
+@@ -266,7 +266,8 @@ union MESAPI_SET_HW_RESOURCES_1 {
+ };
+ uint64_t mes_info_ctx_mc_addr;
+ uint32_t mes_info_ctx_size;
+- uint32_t mes_kiq_unmap_timeout; // unit is 100ms
++ uint64_t reserved1;
++ uint64_t cleaner_shader_fence_mc_addr;
+ };
+
+ uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+--- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
++++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
+@@ -278,6 +278,8 @@ union MESAPI_SET_HW_RESOURCES_1 {
+ uint32_t mes_debug_ctx_size;
+ /* unit is 100ms */
+ uint32_t mes_kiq_unmap_timeout;
++ uint64_t reserved1;
++ uint64_t cleaner_shader_fence_mc_addr;
+ };
+
+ uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
--- /dev/null
+From 15d8c92f107c17c2e585cb4888c67873538f9722 Mon Sep 17 00:00:00 2001
+From: Shaoyun Liu <shaoyun.liu@amd.com>
+Date: Wed, 5 Feb 2025 12:33:11 -0500
+Subject: drm/amd/include : Update MES v12 API for fence update
+
+From: Shaoyun Liu <shaoyun.liu@amd.com>
+
+commit 15d8c92f107c17c2e585cb4888c67873538f9722 upstream.
+
+MES fence_value will be updated in fence_addr if API success,
+otherwise upper 32 bit will be used to indicate error code.
+In any case, MES will trigger an EOP interrupt with 0xb1 as
+context id in the interrupt cookie
+
+Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/include/mes_v12_api_def.h | 40 +++++++++++++++++++++++++-
+ 1 file changed, 39 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
++++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
+@@ -105,6 +105,43 @@ struct MES_API_STATUS {
+ uint64_t api_completion_fence_value;
+ };
+
++/*
++ * MES will set api_completion_fence_value in api_completion_fence_addr
++ * when it can successflly process the API. MES will also trigger
++ * following interrupt when it finish process the API no matter success
++ * or failed.
++ * Interrupt source id 181 (EOP) with context ID (DW 6 in the int
++ * cookie) set to 0xb1 and context type set to 8. Driver side need
++ * to enable TIME_STAMP_INT_ENABLE in CPC_INT_CNTL for MES pipe to
++ * catch this interrupt.
++ * Driver side also need to set enable_mes_fence_int = 1 in
++ * set_HW_resource package to enable this fence interrupt.
++ * when the API process failed.
++ * lowre 32 bits set to 0.
++ * higher 32 bits set as follows (bit shift within high 32)
++ * bit 0 - 7 API specific error code.
++ * bit 8 - 15 API OPCODE.
++ * bit 16 - 23 MISC OPCODE if any
++ * bit 24 - 30 ERROR category (API_ERROR_XXX)
++ * bit 31 Set to 1 to indicate error status
++ *
++ */
++enum { MES_SCH_ERROR_CODE_HEADER_SHIFT_12 = 8 };
++enum { MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 = 16 };
++enum { MES_ERROR_CATEGORY_SHIFT_12 = 24 };
++enum { MES_API_STATUS_ERROR_SHIFT_12 = 31 };
++
++enum MES_ERROR_CATEGORY_CODE_12 {
++ MES_ERROR_API = 1,
++ MES_ERROR_SCHEDULING = 2,
++ MES_ERROR_UNKNOWN = 3,
++};
++
++#define MES_ERR_CODE(api_err, opcode, misc_op, category) \
++ ((uint64) (api_err | opcode << MES_SCH_ERROR_CODE_HEADER_SHIFT_12 | \
++ misc_op << MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 | \
++ category << MES_ERROR_CATEGORY_SHIFT_12 | \
++ 1 << MES_API_STATUS_ERROR_SHIFT_12) << 32)
+
+ enum { MAX_COMPUTE_PIPES = 8 };
+ enum { MAX_GFX_PIPES = 2 };
+@@ -248,7 +285,8 @@ union MESAPI_SET_HW_RESOURCES {
+ uint32_t enable_mes_sch_stb_log : 1;
+ uint32_t limit_single_process : 1;
+ uint32_t unmapped_doorbell_handling: 2;
+- uint32_t reserved : 11;
++ uint32_t enable_mes_fence_int: 1;
++ uint32_t reserved : 10;
+ };
+ uint32_t uint32_all;
+ };
--- /dev/null
+From ce4971388c79d36b3f50f607c3278dbfae6c789b Mon Sep 17 00:00:00 2001
+From: Shaoyun Liu <shaoyun.liu@amd.com>
+Date: Fri, 18 Oct 2024 15:56:25 -0400
+Subject: drm/amd : Update MES API header file for v11 & v12
+
+From: Shaoyun Liu <shaoyun.liu@amd.com>
+
+commit ce4971388c79d36b3f50f607c3278dbfae6c789b upstream.
+
+New features require the new fields defines
+
+Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/include/mes_v11_api_def.h | 43 +++++++++++++++++++++++++-
+ drivers/gpu/drm/amd/include/mes_v12_api_def.h | 31 ++++++++++++++++++
+ 2 files changed, 72 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h
++++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
+@@ -230,13 +230,23 @@ union MESAPI_SET_HW_RESOURCES {
+ uint32_t disable_add_queue_wptr_mc_addr : 1;
+ uint32_t enable_mes_event_int_logging : 1;
+ uint32_t enable_reg_active_poll : 1;
+- uint32_t reserved : 21;
++ uint32_t use_disable_queue_in_legacy_uq_preemption : 1;
++ uint32_t send_write_data : 1;
++ uint32_t os_tdr_timeout_override : 1;
++ uint32_t use_rs64mem_for_proc_gang_ctx : 1;
++ uint32_t use_add_queue_unmap_flag_addr : 1;
++ uint32_t enable_mes_sch_stb_log : 1;
++ uint32_t limit_single_process : 1;
++ uint32_t is_strix_tmz_wa_enabled :1;
++ uint32_t reserved : 13;
+ };
+ uint32_t uint32_t_all;
+ };
+ uint32_t oversubscription_timer;
+ uint64_t doorbell_info;
+ uint64_t event_intr_history_gpu_mc_ptr;
++ uint64_t timestamp;
++ uint32_t os_tdr_timeout_in_sec;
+ };
+
+ uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+@@ -563,6 +573,11 @@ enum MESAPI_MISC_OPCODE {
+ MESAPI_MISC__READ_REG,
+ MESAPI_MISC__WAIT_REG_MEM,
+ MESAPI_MISC__SET_SHADER_DEBUGGER,
++ MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
++ MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
++ MESAPI_MISC__CHANGE_CONFIG,
++ MESAPI_MISC__LAUNCH_CLEANER_SHADER,
++
+ MESAPI_MISC__MAX,
+ };
+
+@@ -617,6 +632,31 @@ struct SET_SHADER_DEBUGGER {
+ uint32_t trap_en;
+ };
+
++enum MESAPI_MISC__CHANGE_CONFIG_OPTION {
++ MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0,
++ MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1,
++ MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG = 2,
++
++ MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F
++};
++
++struct CHANGE_CONFIG {
++ enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode;
++ union {
++ struct {
++ uint32_t limit_single_process : 1;
++ uint32_t enable_hws_logging_buffer : 1;
++ uint32_t reserved : 31;
++ } bits;
++ uint32_t all;
++ } option;
++
++ struct {
++ uint32_t tdr_level;
++ uint32_t tdr_delay;
++ } tdr_config;
++};
++
+ union MESAPI__MISC {
+ struct {
+ union MES_API_HEADER header;
+@@ -631,6 +671,7 @@ union MESAPI__MISC {
+ struct WAIT_REG_MEM wait_reg_mem;
+ struct SET_SHADER_DEBUGGER set_shader_debugger;
+ enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
++ struct CHANGE_CONFIG change_config;
+
+ uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
+ };
+--- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
++++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
+@@ -643,6 +643,10 @@ enum MESAPI_MISC_OPCODE {
+ MESAPI_MISC__SET_SHADER_DEBUGGER,
+ MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
+ MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
++ MESAPI_MISC__QUERY_HUNG_ENGINE_ID,
++ MESAPI_MISC__CHANGE_CONFIG,
++ MESAPI_MISC__LAUNCH_CLEANER_SHADER,
++ MESAPI_MISC__SETUP_MES_DBGEXT,
+
+ MESAPI_MISC__MAX,
+ };
+@@ -713,6 +717,31 @@ struct SET_GANG_SUBMIT {
+ uint32_t slave_gang_context_array_index;
+ };
+
++enum MESAPI_MISC__CHANGE_CONFIG_OPTION {
++ MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0,
++ MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1,
++ MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG = 2,
++
++ MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F
++};
++
++struct CHANGE_CONFIG {
++ enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode;
++ union {
++ struct {
++ uint32_t limit_single_process : 1;
++ uint32_t enable_hws_logging_buffer : 1;
++ uint32_t reserved : 30;
++ } bits;
++ uint32_t all;
++ } option;
++
++ struct {
++ uint32_t tdr_level;
++ uint32_t tdr_delay;
++ } tdr_config;
++};
++
+ union MESAPI__MISC {
+ struct {
+ union MES_API_HEADER header;
+@@ -726,7 +755,7 @@ union MESAPI__MISC {
+ struct WAIT_REG_MEM wait_reg_mem;
+ struct SET_SHADER_DEBUGGER set_shader_debugger;
+ enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
+-
++ struct CHANGE_CONFIG change_config;
+ uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
+ };
+ uint64_t timestamp;
--- /dev/null
+From 1fb710793ce2619223adffaf981b1ff13cd48f17 Mon Sep 17 00:00:00 2001
+From: Mario Limonciello <mario.limonciello@amd.com>
+Date: Thu, 18 Sep 2025 19:48:00 -0500
+Subject: drm/amdgpu: Enable MES lr_compute_wa by default
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+commit 1fb710793ce2619223adffaf981b1ff13cd48f17 upstream.
+
+The MES set resources packet has an optional bit 'lr_compute_wa'
+which can be used for preventing MES hangs on long compute jobs.
+
+Set this bit by default.
+
+Co-developed-by: Yifan Zhang <yifan1.zhang@amd.com>
+Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 6 ++++++
+ drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 5 +++++
+ drivers/gpu/drm/amd/include/mes_v11_api_def.h | 3 ++-
+ drivers/gpu/drm/amd/include/mes_v12_api_def.h | 3 ++-
+ 4 files changed, 15 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+@@ -677,6 +677,12 @@ static int mes_v11_0_set_hw_resources(st
+ mes_set_hw_res_pkt.enable_reg_active_poll = 1;
+ mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
+ mes_set_hw_res_pkt.oversubscription_timer = 50;
++ if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x7f)
++ mes_set_hw_res_pkt.enable_lr_compute_wa = 1;
++ else
++ dev_info_once(mes->adev->dev,
++ "MES FW version must be >= 0x7f to enable LR compute workaround.\n");
++
+ if (amdgpu_mes_log_enable) {
+ mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
+ mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr =
+--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+@@ -610,6 +610,11 @@ static int mes_v12_0_set_hw_resources(st
+ mes_set_hw_res_pkt.use_different_vmid_compute = 1;
+ mes_set_hw_res_pkt.enable_reg_active_poll = 1;
+ mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
++ if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x82)
++ mes_set_hw_res_pkt.enable_lr_compute_wa = 1;
++ else
++ dev_info_once(adev->dev,
++ "MES FW version must be >= 0x82 to enable LR compute workaround.\n");
+
+ /*
+ * Keep oversubscribe timer for sdma . When we have unmapped doorbell
+--- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h
++++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
+@@ -238,7 +238,8 @@ union MESAPI_SET_HW_RESOURCES {
+ uint32_t enable_mes_sch_stb_log : 1;
+ uint32_t limit_single_process : 1;
+ uint32_t is_strix_tmz_wa_enabled :1;
+- uint32_t reserved : 13;
++ uint32_t enable_lr_compute_wa : 1;
++ uint32_t reserved : 12;
+ };
+ uint32_t uint32_t_all;
+ };
+--- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
++++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
+@@ -286,7 +286,8 @@ union MESAPI_SET_HW_RESOURCES {
+ uint32_t limit_single_process : 1;
+ uint32_t unmapped_doorbell_handling: 2;
+ uint32_t enable_mes_fence_int: 1;
+- uint32_t reserved : 10;
++ uint32_t enable_lr_compute_wa : 1;
++ uint32_t reserved : 9;
+ };
+ uint32_t uint32_all;
+ };
can-hi311x-fix-null-pointer-dereference-when-resumin.patch
can-rcar_canfd-fix-controller-mode-setting.patch
platform-x86-amd-pmc-add-stellaris-slim-gen6-amd-to-.patch
+drm-amd-update-mes-api-header-file-for-v11-v12.patch
+drm-amd-include-mes-v11-and-v12-api-header-update.patch
+drm-amd-include-update-mes-v12-api-for-fence-update.patch
+drm-amdgpu-enable-mes-lr_compute_wa-by-default.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
