From: Greg Kroah-Hartman Date: Mon, 5 Jun 2023 20:39:22 +0000 (+0200) Subject: drop iommu-amd-pgtbl_v2-fix-domain-max-address.patch X-Git-Tag: v4.14.317~44 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=01b1c7d5c9c10d9e487c97ba907769143543cd6b;p=thirdparty%2Fkernel%2Fstable-queue.git drop iommu-amd-pgtbl_v2-fix-domain-max-address.patch --- diff --git a/queue-6.1/iommu-amd-pgtbl_v2-fix-domain-max-address.patch b/queue-6.1/iommu-amd-pgtbl_v2-fix-domain-max-address.patch deleted file mode 100644 index 9a2310977ac..00000000000 --- a/queue-6.1/iommu-amd-pgtbl_v2-fix-domain-max-address.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 11c439a19466e7feaccdbce148a75372fddaf4e9 Mon Sep 17 00:00:00 2001 -From: Vasant Hegde -Date: Thu, 18 May 2023 05:43:51 +0000 -Subject: iommu/amd/pgtbl_v2: Fix domain max address - -From: Vasant Hegde - -commit 11c439a19466e7feaccdbce148a75372fddaf4e9 upstream. - -IOMMU v2 page table supports 4 level (47 bit) or 5 level (56 bit) virtual -address space. Current code assumes it can support 64bit IOVA address -space. If IOVA allocator allocates virtual address > 47/56 bit (depending -on page table level) then it will do wrong mapping and cause invalid -translation. - -Hence adjust aperture size to use max address supported by the page table. - -Reported-by: Jerry Snitselaar -Fixes: aaac38f61487 ("iommu/amd: Initial support for AMD IOMMU v2 page table") -Cc: # v6.0+ -Cc: Suravee Suthikulpanit -Signed-off-by: Vasant Hegde -Reviewed-by: Jerry Snitselaar -Link: https://lore.kernel.org/r/20230518054351.9626-1-vasant.hegde@amd.com -Signed-off-by: Joerg Roedel -Signed-off-by: Greg Kroah-Hartman ---- - drivers/iommu/amd/iommu.c | 11 ++++++++++- - 1 file changed, 10 insertions(+), 1 deletion(-) - ---- a/drivers/iommu/amd/iommu.c -+++ b/drivers/iommu/amd/iommu.c -@@ -2101,6 +2101,15 @@ out_err: - return NULL; - } - -+static inline u64 dma_max_address(void) -+{ -+ if (amd_iommu_pgtable == AMD_IOMMU_V1) -+ return ~0ULL; -+ -+ /* V2 with 4/5 level page table */ -+ return ((1ULL << PM_LEVEL_SHIFT(amd_iommu_gpt_level)) - 1); -+} -+ - static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) - { - struct protection_domain *domain; -@@ -2117,7 +2126,7 @@ static struct iommu_domain *amd_iommu_do - return NULL; - - domain->domain.geometry.aperture_start = 0; -- domain->domain.geometry.aperture_end = ~0ULL; -+ domain->domain.geometry.aperture_end = dma_max_address(); - domain->domain.geometry.force_aperture = true; - - return &domain->domain; diff --git a/queue-6.1/series b/queue-6.1/series index 5ff7c25fd50..03106f33a2b 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -187,5 +187,4 @@ phy-qcom-qmp-pcie-msm8996-fix-init-count-imbalance.patch block-fix-revalidate-performance-regression.patch powerpc-iommu-limit-number-of-tces-to-512-for-h_stuff_tce-hcall.patch iommu-amd-fix-domain-flush-size-when-syncing-iotlb.patch -iommu-amd-pgtbl_v2-fix-domain-max-address.patch tpm-tpm_tis-correct-tpm_tis_flags-enumeration-values.patch diff --git a/queue-6.3/iommu-amd-pgtbl_v2-fix-domain-max-address.patch b/queue-6.3/iommu-amd-pgtbl_v2-fix-domain-max-address.patch deleted file mode 100644 index 124aae9ec55..00000000000 --- a/queue-6.3/iommu-amd-pgtbl_v2-fix-domain-max-address.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 11c439a19466e7feaccdbce148a75372fddaf4e9 Mon Sep 17 00:00:00 2001 -From: Vasant Hegde -Date: Thu, 18 May 2023 05:43:51 +0000 -Subject: iommu/amd/pgtbl_v2: Fix domain max address - -From: Vasant Hegde - -commit 11c439a19466e7feaccdbce148a75372fddaf4e9 upstream. - -IOMMU v2 page table supports 4 level (47 bit) or 5 level (56 bit) virtual -address space. Current code assumes it can support 64bit IOVA address -space. If IOVA allocator allocates virtual address > 47/56 bit (depending -on page table level) then it will do wrong mapping and cause invalid -translation. - -Hence adjust aperture size to use max address supported by the page table. - -Reported-by: Jerry Snitselaar -Fixes: aaac38f61487 ("iommu/amd: Initial support for AMD IOMMU v2 page table") -Cc: # v6.0+ -Cc: Suravee Suthikulpanit -Signed-off-by: Vasant Hegde -Reviewed-by: Jerry Snitselaar -Link: https://lore.kernel.org/r/20230518054351.9626-1-vasant.hegde@amd.com -Signed-off-by: Joerg Roedel -Signed-off-by: Greg Kroah-Hartman ---- - drivers/iommu/amd/iommu.c | 11 ++++++++++- - 1 file changed, 10 insertions(+), 1 deletion(-) - ---- a/drivers/iommu/amd/iommu.c -+++ b/drivers/iommu/amd/iommu.c -@@ -2118,6 +2118,15 @@ out_err: - return NULL; - } - -+static inline u64 dma_max_address(void) -+{ -+ if (amd_iommu_pgtable == AMD_IOMMU_V1) -+ return ~0ULL; -+ -+ /* V2 with 4/5 level page table */ -+ return ((1ULL << PM_LEVEL_SHIFT(amd_iommu_gpt_level)) - 1); -+} -+ - static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) - { - struct protection_domain *domain; -@@ -2134,7 +2143,7 @@ static struct iommu_domain *amd_iommu_do - return NULL; - - domain->domain.geometry.aperture_start = 0; -- domain->domain.geometry.aperture_end = ~0ULL; -+ domain->domain.geometry.aperture_end = dma_max_address(); - domain->domain.geometry.force_aperture = true; - - return &domain->domain; diff --git a/queue-6.3/series b/queue-6.3/series index a2641ceec2e..2cb9c8b33fa 100644 --- a/queue-6.3/series +++ b/queue-6.3/series @@ -231,6 +231,5 @@ phy-qcom-qmp-pcie-msm8996-fix-init-count-imbalance.patch block-fix-revalidate-performance-regression.patch powerpc-iommu-limit-number-of-tces-to-512-for-h_stuff_tce-hcall.patch iommu-amd-fix-domain-flush-size-when-syncing-iotlb.patch -iommu-amd-pgtbl_v2-fix-domain-max-address.patch tpm-tpm_tis-correct-tpm_tis_flags-enumeration-values.patch module-decompress-fix-error-checking-on-zstd-decompression.patch