From: Greg Kroah-Hartman Date: Fri, 23 Apr 2010 23:39:30 +0000 (-0700) Subject: delete the mips patches from .32 and .33 for now. X-Git-Tag: v2.6.32.12~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=0265d223ffb07facc648801730f44dc7101e7583;p=thirdparty%2Fkernel%2Fstable-queue.git delete the mips patches from .32 and .33 for now. Will come back in a later release --- diff --git a/review-2.6.32/mips-sibyte-fix-m3-tlb-exception-handler-workaround.patch b/review-2.6.32/mips-sibyte-fix-m3-tlb-exception-handler-workaround.patch deleted file mode 100644 index 464f8e2ade7..00000000000 --- a/review-2.6.32/mips-sibyte-fix-m3-tlb-exception-handler-workaround.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 3d45285dd1ff4d4a1361b95e2d6508579a4402b5 Mon Sep 17 00:00:00 2001 -From: Ralf Baechle -Date: Tue, 23 Mar 2010 17:56:38 +0100 -Subject: MIPS: Sibyte: Fix M3 TLB exception handler workaround. - -From: Ralf Baechle - -commit 3d45285dd1ff4d4a1361b95e2d6508579a4402b5 upstream. - -The M3 workaround needs to cmpare the region and VPN2 fields only. - -Signed-off-by: Ralf Baechle -Cc: Sebastian Andrzej Siewior -Signed-off-by: Greg Kroah-Hartman - ---- - arch/mips/mm/tlbex.c | 22 ++++++++++++++++------ - 1 file changed, 16 insertions(+), 6 deletions(-) - ---- a/arch/mips/mm/tlbex.c -+++ b/arch/mips/mm/tlbex.c -@@ -725,10 +725,15 @@ static void __cpuinit build_r4000_tlb_re - * create the plain linear handler - */ - if (bcm1250_m3_war()) { -- UASM_i_MFC0(&p, K0, C0_BADVADDR); -- UASM_i_MFC0(&p, K1, C0_ENTRYHI); -+ unsigned int segbits = 44; -+ -+ uasm_i_dmfc0(&p, K0, C0_BADVADDR); -+ uasm_i_dmfc0(&p, K1, C0_ENTRYHI); - uasm_i_xor(&p, K0, K0, K1); -- UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); -+ uasm_i_dsrl32(&p, K1, K0, 62 - 32); -+ uasm_i_dsrl(&p, K0, K0, 12 + 1); -+ uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32); -+ uasm_i_or(&p, K0, K0, K1); - uasm_il_bnez(&p, &r, K0, label_leave); - /* No need for uasm_i_nop */ - } -@@ -1242,10 +1247,15 @@ static void __cpuinit build_r4000_tlb_lo - memset(relocs, 0, sizeof(relocs)); - - if (bcm1250_m3_war()) { -- UASM_i_MFC0(&p, K0, C0_BADVADDR); -- UASM_i_MFC0(&p, K1, C0_ENTRYHI); -+ unsigned int segbits = 44; -+ -+ uasm_i_dmfc0(&p, K0, C0_BADVADDR); -+ uasm_i_dmfc0(&p, K1, C0_ENTRYHI); - uasm_i_xor(&p, K0, K0, K1); -- UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); -+ uasm_i_dsrl32(&p, K1, K0, 62 - 32); -+ uasm_i_dsrl(&p, K0, K0, 12 + 1); -+ uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32); -+ uasm_i_or(&p, K0, K0, K1); - uasm_il_bnez(&p, &r, K0, label_leave); - /* No need for uasm_i_nop */ - } diff --git a/review-2.6.32/mips-uasm-add-or-instruction.patch b/review-2.6.32/mips-uasm-add-or-instruction.patch deleted file mode 100644 index 910d64807ea..00000000000 --- a/review-2.6.32/mips-uasm-add-or-instruction.patch +++ /dev/null @@ -1,61 +0,0 @@ -From sebastian@breakpoint.cc Thu Apr 22 09:39:49 2010 -From: Ralf Baechle -Date: Sun, 18 Apr 2010 21:59:25 +0200 -Subject: MIPS: uasm: Add OR instruction. -To: stable@kernel.org -Message-ID: <20100418195925.GA2729@Chamillionaire.breakpoint.cc> -Content-Disposition: inline - -From: Ralf Baechle - -This is the manual fixup of cherry picking from 5808184 ("MIPS: uasm: Add -OR instruction.") - -This is needed for the fix of the M3 workaround. - -Signed-off-by: Ralf Baechle -Signed-off-by: Sebastian Andrzej Siewior -Signed-off-by: Greg Kroah-Hartman - ---- - arch/mips/mm/uasm.c | 4 +++- - arch/mips/mm/uasm.h | 1 + - 2 files changed, 4 insertions(+), 1 deletion(-) - ---- a/arch/mips/mm/uasm.c -+++ b/arch/mips/mm/uasm.c -@@ -62,7 +62,7 @@ enum opcode { - insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, - insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, - insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, -- insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, -+ insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, - insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, - insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori - }; -@@ -116,6 +116,7 @@ static struct insn insn_table[] __cpuini - { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, - { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, -+ { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, - { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, - { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, - { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, -@@ -362,6 +363,7 @@ I_u2s3u1(_lw) - I_u1u2u3(_mfc0) - I_u1u2u3(_mtc0) - I_u2u1u3(_ori) -+I_u3u1u2(_or) - I_u2s3u1(_pref) - I_0(_rfe) - I_u2s3u1(_sc) ---- a/arch/mips/mm/uasm.h -+++ b/arch/mips/mm/uasm.h -@@ -78,6 +78,7 @@ Ip_u2s3u1(_lw); - Ip_u1u2u3(_mfc0); - Ip_u1u2u3(_mtc0); - Ip_u2u1u3(_ori); -+Ip_u3u1u2(_or); - Ip_u2s3u1(_pref); - Ip_0(_rfe); - Ip_u2s3u1(_sc); diff --git a/review-2.6.32/series b/review-2.6.32/series index 9790cbffba2..cf7e58152dd 100644 --- a/review-2.6.32/series +++ b/review-2.6.32/series @@ -192,6 +192,4 @@ sched-use-proper-type-in-sched_getaffinity.patch 0008-KVM-Increase-NR_IOBUS_DEVS-limit-to-200.patch 0009-KVM-x86-Fix-TSS-size-check-for-16-bit-tasks.patch x86-gart-disable-gart-explicitly-before-initialization.patch -mips-uasm-add-or-instruction.patch -mips-sibyte-fix-m3-tlb-exception-handler-workaround.patch r8169-clean-up-my-printk-uglyness.patch diff --git a/review-2.6.33/mips-sibyte-fix-m3-tlb-exception-handler-workaround.patch b/review-2.6.33/mips-sibyte-fix-m3-tlb-exception-handler-workaround.patch deleted file mode 100644 index d98faefc565..00000000000 --- a/review-2.6.33/mips-sibyte-fix-m3-tlb-exception-handler-workaround.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 3d45285dd1ff4d4a1361b95e2d6508579a4402b5 Mon Sep 17 00:00:00 2001 -From: Ralf Baechle -Date: Tue, 23 Mar 2010 17:56:38 +0100 -Subject: MIPS: Sibyte: Fix M3 TLB exception handler workaround. - -From: Ralf Baechle - -commit 3d45285dd1ff4d4a1361b95e2d6508579a4402b5 upstream. - -The M3 workaround needs to cmpare the region and VPN2 fields only. - -Signed-off-by: Ralf Baechle -Cc: Sebastian Andrzej Siewior -Signed-off-by: Greg Kroah-Hartman - ---- - arch/mips/mm/tlbex.c | 22 ++++++++++++++++------ - 1 file changed, 16 insertions(+), 6 deletions(-) - ---- a/arch/mips/mm/tlbex.c -+++ b/arch/mips/mm/tlbex.c -@@ -741,10 +741,15 @@ static void __cpuinit build_r4000_tlb_re - * create the plain linear handler - */ - if (bcm1250_m3_war()) { -- UASM_i_MFC0(&p, K0, C0_BADVADDR); -- UASM_i_MFC0(&p, K1, C0_ENTRYHI); -+ unsigned int segbits = 44; -+ -+ uasm_i_dmfc0(&p, K0, C0_BADVADDR); -+ uasm_i_dmfc0(&p, K1, C0_ENTRYHI); - uasm_i_xor(&p, K0, K0, K1); -- UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); -+ uasm_i_dsrl32(&p, K1, K0, 62 - 32); -+ uasm_i_dsrl(&p, K0, K0, 12 + 1); -+ uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32); -+ uasm_i_or(&p, K0, K0, K1); - uasm_il_bnez(&p, &r, K0, label_leave); - /* No need for uasm_i_nop */ - } -@@ -1260,10 +1265,15 @@ static void __cpuinit build_r4000_tlb_lo - memset(relocs, 0, sizeof(relocs)); - - if (bcm1250_m3_war()) { -- UASM_i_MFC0(&p, K0, C0_BADVADDR); -- UASM_i_MFC0(&p, K1, C0_ENTRYHI); -+ unsigned int segbits = 44; -+ -+ uasm_i_dmfc0(&p, K0, C0_BADVADDR); -+ uasm_i_dmfc0(&p, K1, C0_ENTRYHI); - uasm_i_xor(&p, K0, K0, K1); -- UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); -+ uasm_i_dsrl32(&p, K1, K0, 62 - 32); -+ uasm_i_dsrl(&p, K0, K0, 12 + 1); -+ uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32); -+ uasm_i_or(&p, K0, K0, K1); - uasm_il_bnez(&p, &r, K0, label_leave); - /* No need for uasm_i_nop */ - } diff --git a/review-2.6.33/series b/review-2.6.33/series index 3bf13c4bfe4..ee538e56978 100644 --- a/review-2.6.33/series +++ b/review-2.6.33/series @@ -135,5 +135,4 @@ sched-use-proper-type-in-sched_getaffinity.patch 0008-KVM-Increase-NR_IOBUS_DEVS-limit-to-200.patch 0009-KVM-x86-Fix-TSS-size-check-for-16-bit-tasks.patch x86-gart-disable-gart-explicitly-before-initialization.patch -mips-sibyte-fix-m3-tlb-exception-handler-workaround.patch r8169-clean-up-my-printk-uglyness.patch