From: Greg Kroah-Hartman Date: Thu, 18 Aug 2016 12:08:16 +0000 (+0200) Subject: 4.4-stable patches X-Git-Tag: v3.14.77~14 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=030f5afd8c19bfc73df3e944134dc35c33f6c134;p=thirdparty%2Fkernel%2Fstable-queue.git 4.4-stable patches added patches: drm-i915-dp-revert-drm-i915-dp-fall-back-to-18-bpp-when-sink-capability-is-unknown.patch drm-i915-never-fully-mask-the-the-ei-up-rps-interrupt-on-snb-ivb.patch --- diff --git a/queue-4.4/drm-i915-dp-revert-drm-i915-dp-fall-back-to-18-bpp-when-sink-capability-is-unknown.patch b/queue-4.4/drm-i915-dp-revert-drm-i915-dp-fall-back-to-18-bpp-when-sink-capability-is-unknown.patch new file mode 100644 index 00000000000..8274a15107e --- /dev/null +++ b/queue-4.4/drm-i915-dp-revert-drm-i915-dp-fall-back-to-18-bpp-when-sink-capability-is-unknown.patch @@ -0,0 +1,80 @@ +From 196f954e250943df414efd3d632254c29be38e59 Mon Sep 17 00:00:00 2001 +From: Mario Kleiner +Date: Wed, 6 Jul 2016 12:05:45 +0200 +Subject: drm/i915/dp: Revert "drm/i915/dp: fall back to 18 bpp when sink capability is unknown" +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Mario Kleiner + +commit 196f954e250943df414efd3d632254c29be38e59 upstream. + +This reverts commit 013dd9e03872 +("drm/i915/dp: fall back to 18 bpp when sink capability is unknown") + +This commit introduced a regression into stable kernels, +as it reduces output color depth to 6 bpc for any video +sink connected to a Displayport connector if that sink +doesn't report a specific color depth via EDID, or if +our EDID parser doesn't actually recognize the proper +bpc from EDID. + +Affected are active DisplayPort->VGA converters and +active DisplayPort->DVI converters. Both should be +able to handle 8 bpc, but are degraded to 6 bpc with +this patch. + +The reverted commit was meant to fix +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=105331 + +A followup patch implements a fix for that specific bug, +which is caused by a faulty EDID of the affected DP panel +by adding a new EDID quirk for that panel. + +DP 18 bpp fallback handling and other improvements to +DP sink bpc detection will be handled for future +kernels in a separate series of patches. + +Please backport to stable. + +Signed-off-by: Mario Kleiner +Acked-by: Jani Nikula +Cc: Ville Syrjälä +Cc: Daniel Vetter +Signed-off-by: Dave Airlie +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_display.c | 20 +++++--------------- + 1 file changed, 5 insertions(+), 15 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -11952,21 +11952,11 @@ connected_sink_compute_bpp(struct intel_ + pipe_config->pipe_bpp = connector->base.display_info.bpc*3; + } + +- /* Clamp bpp to default limit on screens without EDID 1.4 */ +- if (connector->base.display_info.bpc == 0) { +- int type = connector->base.connector_type; +- int clamp_bpp = 24; +- +- /* Fall back to 18 bpp when DP sink capability is unknown. */ +- if (type == DRM_MODE_CONNECTOR_DisplayPort || +- type == DRM_MODE_CONNECTOR_eDP) +- clamp_bpp = 18; +- +- if (bpp > clamp_bpp) { +- DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", +- bpp, clamp_bpp); +- pipe_config->pipe_bpp = clamp_bpp; +- } ++ /* Clamp bpp to 8 on screens without EDID 1.4 */ ++ if (connector->base.display_info.bpc == 0 && bpp > 24) { ++ DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", ++ bpp); ++ pipe_config->pipe_bpp = 24; + } + } + diff --git a/queue-4.4/drm-i915-never-fully-mask-the-the-ei-up-rps-interrupt-on-snb-ivb.patch b/queue-4.4/drm-i915-never-fully-mask-the-the-ei-up-rps-interrupt-on-snb-ivb.patch new file mode 100644 index 00000000000..689d4d18fcc --- /dev/null +++ b/queue-4.4/drm-i915-never-fully-mask-the-the-ei-up-rps-interrupt-on-snb-ivb.patch @@ -0,0 +1,46 @@ +From a7b4667a00025ac28300737c868bd4818b6d8c4d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Mon, 23 May 2016 17:42:48 +0300 +Subject: drm/i915: Never fully mask the the EI up rps interrupt on SNB/IVB +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit a7b4667a00025ac28300737c868bd4818b6d8c4d upstream. + +SNB (and IVB too I suppose) starts to misbehave if the GPU gets stuck +in an infinite batch buffer loop. The GPU apparently hogs something +critical and CPUs start to lose interrupts and whatnot. We can keep +the system limping along by unmasking some interrupts in +GEN6_PMINTRMSK. The EI up interrupt has been previously chosen for +that task, so let's never mask it. + +v2: s/gen6_rps_pm_mask/gen6_sanitize_rps_pm_mask/ (Chris) + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93122 +Signed-off-by: Ville Syrjälä +Reviewed-by: Chris Wilson +Signed-off-by: Chris Wilson +Link: http://patchwork.freedesktop.org/patch/msgid/1464014568-4529-1-git-send-email-ville.syrjala@linux.intel.com +(cherry picked from commit 12c100bfa5d9103b6c4d43636fee09c31e75605a) +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_pm.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -4526,7 +4526,8 @@ void gen6_rps_idle(struct drm_i915_priva + else + gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); + dev_priv->rps.last_adj = 0; +- I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); ++ I915_WRITE(GEN6_PMINTRMSK, ++ gen6_sanitize_rps_pm_mask(dev_priv, ~0)); + } + mutex_unlock(&dev_priv->rps.hw_lock); + diff --git a/queue-4.4/series b/queue-4.4/series index 8be3dacbf20..a2cb4dfc372 100644 --- a/queue-4.4/series +++ b/queue-4.4/series @@ -87,3 +87,5 @@ drm-nouveau-gr-nv3x-fix-instobj-write-offsets-in-gr-setup.patch drm-nouveau-fbcon-fix-font-width-not-divisible-by-8.patch drm-restore-double-clflush-on-the-last-partial-cacheline.patch drm-edid-add-6-bpc-quirk-for-display-aeo-model-0.patch +drm-i915-never-fully-mask-the-the-ei-up-rps-interrupt-on-snb-ivb.patch +drm-i915-dp-revert-drm-i915-dp-fall-back-to-18-bpp-when-sink-capability-is-unknown.patch