From: Stephen Boyd <sboyd@kernel.org>
Date: Wed, 15 Aug 2018 05:58:53 +0000 (-0700)
Subject: Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter', 'clk... 
X-Git-Tag: v4.19-rc1~130^2~1
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=032405a754fb338812732eac449cd10173f13a1a;p=thirdparty%2Flinux.git

Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next

* clk-imx6-ocram:
  :  - i.MX6SX ocram_s clk support
  clk: imx: add ocram_s clock for i.mx6sx

* clk-missing-put:
  :  - Add missing of_node_put()s in some i.MX clk drivers
  clk: imx6sll: fix missing of_node_put()
  clk: imx6ul: fix missing of_node_put()

* clk-tegra-sdmmc-jitter:
  :  - Tegra SDMMC clk jitter improvements with high speed signaling modes
  clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks
  clk: tegra: Add sdmmc mux divider clock
  clk: tegra: Refactor fractional divider calculation
  clk: tegra: Fix includes required by fence_udelay()

* clk-allwinner:
  clk: sunxi-ng: add A64 compatible string
  dt-bindings: add compatible string for the A64 DE2 CCU
  clk: sunxi-ng: r40: Export video PLLs
  clk: sunxi-ng: r40: Allow setting parent rate to display related clocks
  clk: sunxi-ng: r40: Add minimal rate for video PLLs

* clk-uniphier:
  :  - Uniphier NAND, USB3 PHY, and SPI clk support
  clk: uniphier: add clock frequency support for SPI
  clk: uniphier: add more USB3 PHY clocks
  clk: uniphier: add NAND 200MHz clock
---

032405a754fb338812732eac449cd10173f13a1a
diff --cc drivers/clk/tegra/clk-divider.c
index 58874c1bbf5e6,16e0aee14773b,16e0aee14773b,8f175ff62f73e,16e0aee14773b,16e0aee14773b..205fe8ff63f03
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@@@@@@ -32,35 -32,35 -32,35 -32,15 -32,35 -32,35 +32,15 @@@@@@@
      static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
      		   unsigned long parent_rate)
      {
--- --	u64 divider_ux1 = parent_rate;
--- --	u8 flags = divider->flags;
--- --	int mul;
 -- --
 -- --	if (!rate)
 -- --		return 0;
 -- --
 -- --	mul = get_mul(divider);
 -- --
 -- --	if (!(flags & TEGRA_DIVIDER_INT))
 -- --		divider_ux1 *= mul;
 -- --
 -- --	if (flags & TEGRA_DIVIDER_ROUND_UP)
 -- --		divider_ux1 += rate - 1;
 -- --
 -- --	do_div(divider_ux1, rate);
 -- --
 -- --	if (flags & TEGRA_DIVIDER_INT)
 -- --		divider_ux1 *= mul;
+++ ++	int div;
      
-     	if (!rate)
-     		return 0;
-     
-     	mul = get_mul(divider);
-     
-     	if (!(flags & TEGRA_DIVIDER_INT))
-     		divider_ux1 *= mul;
-     
-     	if (flags & TEGRA_DIVIDER_ROUND_UP)
-     		divider_ux1 += rate - 1;
 -- --	divider_ux1 -= mul;
+++ ++	div = div_frac_get(rate, parent_rate, divider->width,
+++ ++			   divider->frac_width, divider->flags);
      
-     	do_div(divider_ux1, rate);
-     
-     	if (flags & TEGRA_DIVIDER_INT)
-     		divider_ux1 *= mul;
-     
-     	divider_ux1 -= mul;
-     
--- --	if ((s64)divider_ux1 < 0)
+++ ++	if (div < 0)
      		return 0;
      
--- --	if (divider_ux1 > get_max_div(divider))
--- --		return get_max_div(divider);
--- --
--- --	return divider_ux1;
+++ ++	return div;
      }
      
      static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,