From: Dnyaneshwar Bhadane Date: Sun, 25 Aug 2024 12:11:56 +0000 (+0530) Subject: drm/i915/gt: Whitelist COMMON_SLICE_CHICKEN1 for UMD access. X-Git-Tag: v6.12-rc1~126^2~7^2~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=037f93434ce9aea3dc19ba2d97e888a12e538f7b;p=thirdparty%2Fkernel%2Flinux.git drm/i915/gt: Whitelist COMMON_SLICE_CHICKEN1 for UMD access. As part of the recommended tuning setting, whitelist COMMON_SLICE_CHICKEN1 for MTL/ARL and DG2. The UMD will selectively enable or disable specific bits of the register based on the type of workload and its requirements. v2: Remove the KMD par of enabling specific bits(Matt R) Bspec: 68331 Signed-off-by: Dnyaneshwar Bhadane Reviewed-by: Matt Roper Signed-off-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20240825121156.2498810-1-dnyaneshwar.bhadane@intel.com --- diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index baa609bdf7cb4..e539a656cfc3a 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2071,7 +2071,7 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine) case RENDER_CLASS: /* Required by recommended tuning setting (not a workaround) */ whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); - + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); break; default: break; @@ -2086,7 +2086,7 @@ static void xelpg_whitelist_build(struct intel_engine_cs *engine) case RENDER_CLASS: /* Required by recommended tuning setting (not a workaround) */ whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); - + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); break; default: break;