From: Nicholas Piggin Date: Tue, 12 Mar 2024 20:14:58 +0000 (+0100) Subject: physmem: Fix migration dirty bitmap coherency with TCG memory access X-Git-Tag: v9.0.0-rc0~7^2~5 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=03bfc2188f061;p=thirdparty%2Fqemu.git physmem: Fix migration dirty bitmap coherency with TCG memory access The fastpath in cpu_physical_memory_sync_dirty_bitmap() to test large aligned ranges forgot to bring the TCG TLB up to date after clearing some of the dirty memory bitmap bits. This can result in stores though the TCG TLB not setting the dirty memory bitmap and ultimately causes memory corruption / lost updates during migration from a TCG host. Fix this by calling cpu_physical_memory_dirty_bits_cleared() when dirty bits have been cleared. Fixes: aa8dc044772 ("migration: synchronize memory bitmap 64bits at a time") Signed-off-by: Nicholas Piggin Tested-by: Thomas Huth Message-ID: <20240219061731.232570-1-npiggin@gmail.com> [PMD: Split patch in 2: part 2/2, slightly adapt description] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Link: https://lore.kernel.org/r/20240312201458.79532-4-philmd@linaro.org Signed-off-by: Peter Xu --- diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index b060ea91760..de45ba7bc96 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -513,6 +513,9 @@ uint64_t cpu_physical_memory_sync_dirty_bitmap(RAMBlock *rb, idx++; } } + if (num_dirty) { + cpu_physical_memory_dirty_bits_cleared(start, length); + } if (rb->clear_bmap) { /*