From: Johan Jonker Date: Tue, 29 Mar 2022 15:07:37 +0000 (+0200) Subject: dt-bindings: clock: fix some conversion style issues for rockchip,rk3399-cru.yaml X-Git-Tag: v5.19-rc1~117^2~1^2^2~13 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=04d3e427148f8ed7322f70e324731c81460671df;p=thirdparty%2Fkernel%2Flinux.git dt-bindings: clock: fix some conversion style issues for rockchip,rk3399-cru.yaml With the conversion of rockchip,rk3399-cru.txt a table with external clocks was copied. Make it a bit cleaner by aligning the columns. Also fix a description. Phrases start with a capital. Signed-off-by: Johan Jonker Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220329150742.22093-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml index 72b286a1beba2..76dd24d49a37a 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml @@ -22,11 +22,11 @@ description: | There are several clocks that are generated outside the SoC. It is expected that they are defined using standard clock bindings with following clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "clkin_gmac" - external GMAC clock - optional, - - "clkin_i2s" - external I2S clock - optional, - - "pclkin_cif" - external ISP clock - optional, + - "xin24m" - crystal input - required, + - "xin32k" - rtc clock - optional, + - "clkin_gmac" - external GMAC clock - optional, + - "clkin_i2s" - external I2S clock - optional, + - "pclkin_cif" - external ISP clock - optional, - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 @@ -62,8 +62,8 @@ properties: rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle - description: > - phandle to the syscon managing the "general register files". It is used + description: + Phandle to the syscon managing the "general register files". It is used for GRF muxes, if missing any muxes present in the GRF will not be available.