From: Jürgen Urban <JuergenUrban@gmx.de>
Date: Mon, 22 Jul 2013 18:48:32 +0000 (+0000)
Subject: config.gcc (mips*-*-*): Add --with-fpu support.
X-Git-Tag: releases/gcc-4.9.0~4900
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=04dfc6df2e1cc1b2534f8160a58d8c9e2c3f18f6;p=thirdparty%2Fgcc.git

config.gcc (mips*-*-*): Add --with-fpu support.

gcc/
2013-07-26  Jürgen Urban  <JuergenUrban@gmx.de>

	* config.gcc (mips*-*-*): Add --with-fpu support.  Make single the
	default for R5900 targets.
	* config/mips/mips.h (OPTION_DEFAULT_SPECS): Handle --with-fpu.
	(ISA_HAS_LDC1_SDC1): Set to false for TARGET_MIPS5900.
	* config/mips/mips.c (mips_option_override): Report an error for
	-march=r5900 -mhard-float -mdouble-float.  Use spu_single_format
	for -march=r5900 -mhard-float.

From-SVN: r201143
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4bb747fdec96..efc9ac7e51de 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2013-07-22  Jürgen Urban  <JuergenUrban@gmx.de>
+
+	* config.gcc (mips*-*-*): Add --with-fpu support.  Make single the
+	default for R5900 targets.
+	* config/mips/mips.h (OPTION_DEFAULT_SPECS): Handle --with-fpu.
+	(ISA_HAS_LDC1_SDC1): Set to false for TARGET_MIPS5900.
+	* config/mips/mips.c (mips_option_override): Report an error for
+	-march=r5900 -mhard-float -mdouble-float.  Use spu_single_format
+	for -march=r5900 -mhard-float.
+
 2013-07-22  Chang  <pchang9@cs.wisc.edu>
 
 	* df-problems.c (can_move_insns_across): Exit loop once we
diff --git a/gcc/config.gcc b/gcc/config.gcc
index e1b688fd4348..1a398a7232fc 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3091,6 +3091,16 @@ if test x$with_float = x; then
   esac
 fi
 
+# Infer a default setting for --with-fpu.
+if test x$with_fpu = x; then
+  case ${target} in
+    mips64r5900-*-* | mips64r5900el-*-* | mipsr5900-*-* | mipsr5900el-*-*)
+      # The R5900 FPU only supports single precision.
+      with_fpu=single
+      ;;
+  esac
+fi
+
 # Support --with-fpmath.
 if test x$with_fpmath != x; then
   case ${target} in
@@ -3469,7 +3479,7 @@ case "${target}" in
 		;;
 
 	mips*-*-*)
-		supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64 divide llsc mips-plt synci"
+		supported_defaults="abi arch arch_32 arch_64 float fpu tune tune_32 tune_64 divide llsc mips-plt synci"
 
 		case ${with_float} in
 		"" | soft | hard)
@@ -3481,6 +3491,16 @@ case "${target}" in
 			;;
 		esac
 
+		case ${with_fpu} in
+		"" | single | double)
+			# OK
+			;;
+		*)
+			echo "Unknown fpu type used in --with-fpu=$with_fpu" 1>&2
+			exit 1
+			;;
+		esac
+
 		case ${with_abi} in
 		"" | 32 | o64 | n32 | 64 | eabi)
 			# OK
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index e95bdd88d4a0..a3735dc598d4 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -16832,6 +16832,11 @@ mips_option_override (void)
 
   /* End of code shared with GAS.  */
 
+  /* The R5900 FPU only supports single precision.  */
+  if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
+    error ("unsupported combination: %s",
+	   "-march=r5900 -mhard-float -mdouble-float");
+
   /* If a -mlong* option was given, check that it matches the ABI,
      otherwise infer the -mlong* setting from the other options.  */
   if ((target_flags_explicit & MASK_LONG64) != 0)
@@ -17139,6 +17144,9 @@ mips_option_override (void)
      filling.  Registering the pass must be done at start up.  It's
      convenient to do it here.  */
   register_pass (&insert_pass_mips_machine_reorg2);
+
+  if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
+    REAL_MODE_FORMAT (SFmode) = &spu_single_format;
 }
 
 /* Swap the register information for registers I and I + 1, which
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 007f598c658f..2dcccd48b8fd 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -754,6 +754,7 @@ struct mips_cpu_info {
   {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
   {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
+  {"fpu", "%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}" }, \
   {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
   {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
   {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
@@ -859,7 +860,9 @@ struct mips_cpu_info {
 				 || TARGET_LOONGSON_2EF)
 
 /* ISA has LDC1 and SDC1.  */
-#define ISA_HAS_LDC1_SDC1	(!ISA_MIPS1 && !TARGET_MIPS16)
+#define ISA_HAS_LDC1_SDC1	(!ISA_MIPS1				\
+				 && !TARGET_MIPS5900			\
+				 && !TARGET_MIPS16)
 
 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
    branch on CC, and move (both FP and non-FP) on CC.  */