From: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: Mon, 31 Mar 2025 14:46:13 +0000 (+0200)
Subject: hw/pci-host/designware: Fix ATU_UPPER_TARGET register access
X-Git-Tag: v10.0.0-rc2~2^2~6
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=04e99f9eb7920b0f0fcce65686c3bedf5e32a1f9;p=thirdparty%2Fqemu.git

hw/pci-host/designware: Fix ATU_UPPER_TARGET register access

Fix copy/paste error writing to the ATU_UPPER_TARGET
register, we want to update the upper 32 bits.

Cc: qemu-stable@nongnu.org
Reported-by: Joey <jeundery@gmail.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2861
Fixes: d64e5eabc4c ("pci: Add support for Designware IP block")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-Id: <20250331152041.74533-2-philmd@linaro.org>
---

diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index c07740bfaa..5598d18f47 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -371,7 +371,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
 
     case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
         viewport->target &= 0x00000000FFFFFFFFULL;
-        viewport->target |= val;
+        viewport->target |= (uint64_t)val << 32;
         break;
 
     case DESIGNWARE_PCIE_ATU_LIMIT: