From: Greg Kroah-Hartman Date: Wed, 24 Jul 2013 17:40:43 +0000 (-0700) Subject: 3.0-stable patches X-Git-Tag: v3.10.3~5 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=050a293f3d59481824c3c7890d2a23d940e73918;p=thirdparty%2Fkernel%2Fstable-queue.git 3.0-stable patches added patches: sparc32-vm_area_struct-access-for-old-sun-sparcs.patch sparc64-address-congruence-property.patch sparc-tsb-must-be-flushed-before-tlb.patch --- diff --git a/queue-3.0/series b/queue-3.0/series index 44cbc279463..fc290f14d33 100644 --- a/queue-3.0/series +++ b/queue-3.0/series @@ -7,3 +7,6 @@ tracing-use-current_uid-for-critical-time-tracing.patch perf-clone-child-context-from-parent-context-pmu.patch perf-remove-warn_on_once-check-in-__perf_event_enable-for-valid-scenario.patch perf-fix-perf_lock_task_context-vs-rcu.patch +sparc32-vm_area_struct-access-for-old-sun-sparcs.patch +sparc64-address-congruence-property.patch +sparc-tsb-must-be-flushed-before-tlb.patch diff --git a/queue-3.0/sparc-tsb-must-be-flushed-before-tlb.patch b/queue-3.0/sparc-tsb-must-be-flushed-before-tlb.patch new file mode 100644 index 00000000000..2f7918d06da --- /dev/null +++ b/queue-3.0/sparc-tsb-must-be-flushed-before-tlb.patch @@ -0,0 +1,35 @@ +From 175bc3b75a63151eba7cab828d34ce86fe854b69 Mon Sep 17 00:00:00 2001 +From: Dave Kleikamp +Date: Tue, 18 Jun 2013 09:05:36 -0500 +Subject: sparc: tsb must be flushed before tlb + +From: Dave Kleikamp + +This fixes a race where a cpu may re-load a tlb from a stale tsb right +after it has been flushed by a remote function call. + +I still see some instability when stressing the system with parallel +kernel builds while creating memory pressure by writing to +/proc/sys/vm/nr_hugepages, but this patch improves the stability +significantly. + +Signed-off-by: Dave Kleikamp +Acked-by: Bob Picco +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman +--- + arch/sparc/mm/tlb.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/sparc/mm/tlb.c ++++ b/arch/sparc/mm/tlb.c +@@ -115,8 +115,8 @@ no_cache_flush: + } + + if (!tb->active) { +- global_flush_tlb_page(mm, vaddr); + flush_tsb_user_page(mm, vaddr); ++ global_flush_tlb_page(mm, vaddr); + goto out; + } + diff --git a/queue-3.0/sparc32-vm_area_struct-access-for-old-sun-sparcs.patch b/queue-3.0/sparc32-vm_area_struct-access-for-old-sun-sparcs.patch new file mode 100644 index 00000000000..2e83d7eda46 --- /dev/null +++ b/queue-3.0/sparc32-vm_area_struct-access-for-old-sun-sparcs.patch @@ -0,0 +1,188 @@ +From e204b082d78904ee2d5e751a130bd6273d87eeac Mon Sep 17 00:00:00 2001 +From: Olivier DANET +Date: Wed, 10 Jul 2013 13:56:10 -0700 +Subject: sparc32: vm_area_struct access for old Sun SPARCs. + +From: Olivier DANET + +Commit e4c6bfd2d79d063017ab19a18915f0bc759f32d9 ("mm: rearrange +vm_area_struct for fewer cache misses") changed the layout of the +vm_area_struct structure, it broke several SPARC32 assembly routines +which used numerical constants for accessing the vm_mm field. + +This patch defines the VMA_VM_MM constant to replace the immediate values. + +Signed-off-by: Olivier DANET +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman +--- + arch/sparc/kernel/asm-offsets.c | 2 ++ + arch/sparc/mm/hypersparc.S | 8 ++++---- + arch/sparc/mm/swift.S | 8 ++++---- + arch/sparc/mm/tsunami.S | 6 +++--- + arch/sparc/mm/viking.S | 10 +++++----- + 5 files changed, 18 insertions(+), 16 deletions(-) + +--- a/arch/sparc/kernel/asm-offsets.c ++++ b/arch/sparc/kernel/asm-offsets.c +@@ -34,6 +34,8 @@ int foo(void) + DEFINE(AOFF_task_thread, offsetof(struct task_struct, thread)); + BLANK(); + DEFINE(AOFF_mm_context, offsetof(struct mm_struct, context)); ++ BLANK(); ++ DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm)); + + /* DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28); */ + return 0; +--- a/arch/sparc/mm/hypersparc.S ++++ b/arch/sparc/mm/hypersparc.S +@@ -74,7 +74,7 @@ hypersparc_flush_cache_mm_out: + + /* The things we do for performance... */ + hypersparc_flush_cache_range: +- ld [%o0 + 0x0], %o0 /* XXX vma->vm_mm, GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + #ifndef CONFIG_SMP + ld [%o0 + AOFF_mm_context], %g1 + cmp %g1, -1 +@@ -163,7 +163,7 @@ hypersparc_flush_cache_range_out: + */ + /* Verified, my ass... */ + hypersparc_flush_cache_page: +- ld [%o0 + 0x0], %o0 /* XXX vma->vm_mm, GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + ld [%o0 + AOFF_mm_context], %g2 + #ifndef CONFIG_SMP + cmp %g2, -1 +@@ -284,7 +284,7 @@ hypersparc_flush_tlb_mm_out: + sta %g5, [%g1] ASI_M_MMUREGS + + hypersparc_flush_tlb_range: +- ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + mov SRMMU_CTX_REG, %g1 + ld [%o0 + AOFF_mm_context], %o3 + lda [%g1] ASI_M_MMUREGS, %g5 +@@ -307,7 +307,7 @@ hypersparc_flush_tlb_range_out: + sta %g5, [%g1] ASI_M_MMUREGS + + hypersparc_flush_tlb_page: +- ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + mov SRMMU_CTX_REG, %g1 + ld [%o0 + AOFF_mm_context], %o3 + andn %o1, (PAGE_SIZE - 1), %o1 +--- a/arch/sparc/mm/swift.S ++++ b/arch/sparc/mm/swift.S +@@ -105,7 +105,7 @@ swift_flush_cache_mm_out: + + .globl swift_flush_cache_range + swift_flush_cache_range: +- ld [%o0 + 0x0], %o0 /* XXX vma->vm_mm, GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + sub %o2, %o1, %o2 + sethi %hi(4096), %o3 + cmp %o2, %o3 +@@ -116,7 +116,7 @@ swift_flush_cache_range: + + .globl swift_flush_cache_page + swift_flush_cache_page: +- ld [%o0 + 0x0], %o0 /* XXX vma->vm_mm, GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + 70: + ld [%o0 + AOFF_mm_context], %g2 + cmp %g2, -1 +@@ -219,7 +219,7 @@ swift_flush_sig_insns: + .globl swift_flush_tlb_range + .globl swift_flush_tlb_all + swift_flush_tlb_range: +- ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + swift_flush_tlb_mm: + ld [%o0 + AOFF_mm_context], %g2 + cmp %g2, -1 +@@ -233,7 +233,7 @@ swift_flush_tlb_all_out: + + .globl swift_flush_tlb_page + swift_flush_tlb_page: +- ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + mov SRMMU_CTX_REG, %g1 + ld [%o0 + AOFF_mm_context], %o3 + andn %o1, (PAGE_SIZE - 1), %o1 +--- a/arch/sparc/mm/tsunami.S ++++ b/arch/sparc/mm/tsunami.S +@@ -24,7 +24,7 @@ + /* Sliiick... */ + tsunami_flush_cache_page: + tsunami_flush_cache_range: +- ld [%o0 + 0x0], %o0 /* XXX vma->vm_mm, GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + tsunami_flush_cache_mm: + ld [%o0 + AOFF_mm_context], %g2 + cmp %g2, -1 +@@ -46,7 +46,7 @@ tsunami_flush_sig_insns: + + /* More slick stuff... */ + tsunami_flush_tlb_range: +- ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + tsunami_flush_tlb_mm: + ld [%o0 + AOFF_mm_context], %g2 + cmp %g2, -1 +@@ -65,7 +65,7 @@ tsunami_flush_tlb_out: + + /* This one can be done in a fine grained manner... */ + tsunami_flush_tlb_page: +- ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + mov SRMMU_CTX_REG, %g1 + ld [%o0 + AOFF_mm_context], %o3 + andn %o1, (PAGE_SIZE - 1), %o1 +--- a/arch/sparc/mm/viking.S ++++ b/arch/sparc/mm/viking.S +@@ -109,7 +109,7 @@ viking_mxcc_flush_page: + viking_flush_cache_page: + viking_flush_cache_range: + #ifndef CONFIG_SMP +- ld [%o0 + 0x0], %o0 /* XXX vma->vm_mm, GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + #endif + viking_flush_cache_mm: + #ifndef CONFIG_SMP +@@ -149,7 +149,7 @@ viking_flush_tlb_mm: + #endif + + viking_flush_tlb_range: +- ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + mov SRMMU_CTX_REG, %g1 + ld [%o0 + AOFF_mm_context], %o3 + lda [%g1] ASI_M_MMUREGS, %g5 +@@ -174,7 +174,7 @@ viking_flush_tlb_range: + #endif + + viking_flush_tlb_page: +- ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + mov SRMMU_CTX_REG, %g1 + ld [%o0 + AOFF_mm_context], %o3 + lda [%g1] ASI_M_MMUREGS, %g5 +@@ -240,7 +240,7 @@ sun4dsmp_flush_tlb_range: + tst %g5 + bne 3f + mov SRMMU_CTX_REG, %g1 +- ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + ld [%o0 + AOFF_mm_context], %o3 + lda [%g1] ASI_M_MMUREGS, %g5 + sethi %hi(~((1 << SRMMU_PGDIR_SHIFT) - 1)), %o4 +@@ -266,7 +266,7 @@ sun4dsmp_flush_tlb_page: + tst %g5 + bne 2f + mov SRMMU_CTX_REG, %g1 +- ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */ ++ ld [%o0 + VMA_VM_MM], %o0 + ld [%o0 + AOFF_mm_context], %o3 + lda [%g1] ASI_M_MMUREGS, %g5 + and %o1, PAGE_MASK, %o1 diff --git a/queue-3.0/sparc64-address-congruence-property.patch b/queue-3.0/sparc64-address-congruence-property.patch new file mode 100644 index 00000000000..aea38efdab1 --- /dev/null +++ b/queue-3.0/sparc64-address-congruence-property.patch @@ -0,0 +1,37 @@ +From 0dc836a588dda1250a451716270d5dd5ff07041c Mon Sep 17 00:00:00 2001 +From: bob picco +Date: Tue, 11 Jun 2013 14:54:51 -0400 +Subject: sparc64 address-congruence property + +From: bob picco + +The Machine Description (MD) property "address-congruence-offset" is +optional. According to the MD specification the value is assumed 0UL when +not present. This caused early boot failure on T5. + +Signed-off-by: Bob Picco +CC: sparclinux@vger.kernel.org +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman +--- + arch/sparc/mm/init_64.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/arch/sparc/mm/init_64.c ++++ b/arch/sparc/mm/init_64.c +@@ -1071,7 +1071,14 @@ static int __init grab_mblocks(struct md + m->size = *val; + val = mdesc_get_property(md, node, + "address-congruence-offset", NULL); +- m->offset = *val; ++ ++ /* The address-congruence-offset property is optional. ++ * Explicity zero it be identifty this. ++ */ ++ if (val) ++ m->offset = *val; ++ else ++ m->offset = 0UL; + + numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", + count - 1, m->base, m->size, m->offset);