From: Andrew Pinski <pinskia@physics.uc.edu>
Date: Mon, 31 Jan 2005 22:29:27 +0000 (+0000)
Subject: rs6000.md (copysignsf3): New expand.
X-Git-Tag: releases/gcc-4.0.0~1158
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=0530bc70fbab2126ca2510ca18b61d01f949f38d;p=thirdparty%2Fgcc.git

rs6000.md (copysignsf3): New expand.

2005-01-31  Andrew Pinski  <pinskia@physics.uc.edu>

        * config/rs6000/rs6000.md (copysignsf3): New expand.
        (copysigndf3): Likewise.

From-SVN: r94497
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 76e28d1ef4af..8d618f5a9437 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2005-01-31  Andrew Pinski  <pinskia@physics.uc.edu>
+
+	* config/rs6000/rs6000.md (copysignsf3): New expand.
+	(copysigndf3): Likewise.
+
 2005-01-31  Steven Bosscher  <stevenb@suse.de>
 
 	* recog.c (constrain_operands): Only look for earlyclobber operand
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 988dc4b8a978..7ccdab8b5a8e 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4705,6 +4705,42 @@
   "fsqrt %0,%1"
   [(set_attr "type" "dsqrt")])
 
+(define_expand "copysignsf3"
+  [(set (match_dup 3)
+        (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
+   (set (match_dup 4)
+	(neg:SF (abs:SF (match_dup 1))))
+   (set (match_operand:SF 0 "gpc_reg_operand" "")
+        (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
+	                     (match_dup 5))
+			 (match_dup 3)
+			 (match_dup 4)))]
+  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
+   && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)" 
+  {
+     operands[3] = gen_reg_rtx (SFmode);
+     operands[4] = gen_reg_rtx (SFmode);
+     operands[5] = CONST0_RTX (SFmode);
+  })
+
+(define_expand "copysigndf3"
+  [(set (match_dup 3)
+        (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
+   (set (match_dup 4)
+	(neg:DF (abs:DF (match_dup 1))))
+   (set (match_operand:DF 0 "gpc_reg_operand" "")
+        (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
+	                     (match_dup 5))
+			 (match_dup 3)
+			 (match_dup 4)))]
+  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
+   && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
+  {
+     operands[3] = gen_reg_rtx (DFmode);
+     operands[4] = gen_reg_rtx (DFmode);
+     operands[5] = CONST0_RTX (DFmode);
+  })
+
 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
 ;; fsel instruction and some auxiliary computations.  Then we just have a
 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by