From: Bastian Koppelmann Date: Fri, 22 May 2015 10:15:56 +0000 (+0200) Subject: target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result X-Git-Tag: v2.4.0-rc0~109^2~2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=05b6ca9bbcaede74120050aa8e6684300c09257c;p=thirdparty%2Fqemu.git target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result If the argument r1 was the same as the extended result register r3+1, we would overwrite r1 and then use it. Signed-off-by: Bastian Koppelmann Message-Id: <1432289758-6250-2-git-send-email-kbastian@mail.uni-paderborn.de> --- diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 5f8eff04fa2..6c148434385 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6451,8 +6451,8 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) /* sv */ tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); /* write result */ - tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); + tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); tcg_temp_free(temp); tcg_temp_free(temp2); tcg_temp_free(temp3);