From: Mike Frysinger <vapier@gentoo.org>
Date: Thu, 21 Dec 2023 06:35:41 +0000 (-0500)
Subject: sim: riscv: fix -Wimplicit-fallthrough warnings
X-Git-Tag: binutils-2_42~447
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=05b9feffffb7af6986469f1be427d0c7d7fa2683;p=thirdparty%2Fbinutils-gdb.git

sim: riscv: fix -Wimplicit-fallthrough warnings
---

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index afdfcf50656..4d205345395 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -126,6 +126,7 @@ store_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg,
     case CSR_INSTRETH:
     case CSR_TIMEH:
       RISCV_ASSERT_RV32 (cpu, "CSR: %s", name);
+      ATTRIBUTE_FALLTHROUGH;
 
     /* All the rest are immutable.  */
     default: