From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: Sat, 22 May 2021 18:16:15 +0000 (+0200)
Subject: target/mips: Do not abort on invalid instruction
X-Git-Tag: v6.1.0-rc0~55^2~10
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=05d9d0359e6da7dc8255712d745d079a04fa5ae5;p=thirdparty%2Fqemu.git

target/mips: Do not abort on invalid instruction

On real hardware an invalid instruction doesn't halt the world,
but usually triggers a RESERVED INSTRUCTION exception.
TCG guest code shouldn't abort QEMU anyway.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210617174323.2900831-2-f4bug@amsat.org>
---

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 3fd0c48d772..4b7229a868a 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -12151,8 +12151,8 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
             tcg_gen_lookup_and_goto_ptr();
             break;
         default:
-            fprintf(stderr, "unknown branch 0x%x\n", proc_hflags);
-            abort();
+            LOG_DISAS("unknown branch 0x%x\n", proc_hflags);
+            gen_reserved_instruction(ctx);
         }
     }
 }