From: Sylwester Nawrocki Date: Wed, 7 Mar 2018 16:46:55 +0000 (+0100) Subject: clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk X-Git-Tag: v4.17-rc1~18^2~7^4~1^2~3 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=06255a92793925474ea806d0c46ed8a82c49bcc7;p=thirdparty%2Fkernel%2Flinux.git clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk This allows changing the EPLL output frequency through the audio subsystem clock tree leaf clocks. This change is needed to support audio on the HDMI interface on Peach-Pi(t) Chromebook. Signed-off-by: Sylwester Nawrocki Acked-by: Chanwoo Choi Signed-off-by: Sylwester Nawrocki --- diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index c7b0f55dfbb64..1bb6e103509f4 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -621,7 +621,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", mout_group5_5800_p, SRC_TOP7, 16, 2), - MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2), + MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2, + CLK_SET_RATE_PARENT, 0), MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), };