From: nobody <> Date: Fri, 24 Aug 2012 08:14:41 +0000 (+0000) Subject: This commit was manufactured by cvs2svn to create branch 'binutils- X-Git-Tag: binutils-2_23~96 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=068992f7eeae49ae604d7e6fa1cd2e132a2adbd1;p=thirdparty%2Fbinutils-gdb.git This commit was manufactured by cvs2svn to create branch 'binutils- 2_23-branch'. Cherrypick from master 2012-08-24 08:14:40 UTC Matthew Gretton-Dann ' * gas/config/tc-arm.c (ARM_ENC_TAB): Add sha1h and sha2op entries.': gas/testsuite/gas/arm/armv8-a+crypto.d gas/testsuite/gas/arm/armv8-a+crypto.s gas/testsuite/gas/arm/armv8-a+fp.d gas/testsuite/gas/arm/armv8-a+fp.s gas/testsuite/gas/arm/armv8-a+simd.d gas/testsuite/gas/arm/armv8-a+simd.s gas/testsuite/gas/arm/armv8-a-bad.d gas/testsuite/gas/arm/armv8-a-bad.l gas/testsuite/gas/arm/armv8-a-bad.s gas/testsuite/gas/arm/armv8-a-barrier-arm.d gas/testsuite/gas/arm/armv8-a-barrier-thumb.d gas/testsuite/gas/arm/armv8-a-barrier.s gas/testsuite/gas/arm/armv8-a-it-bad.d gas/testsuite/gas/arm/armv8-a-it-bad.l gas/testsuite/gas/arm/armv8-a-it-bad.s gas/testsuite/gas/arm/armv8-a.d gas/testsuite/gas/arm/armv8-a.s gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d gas/testsuite/gas/arm/attr-march-armv8-a+fp.d gas/testsuite/gas/arm/attr-march-armv8-a+simd.d gas/testsuite/gas/arm/attr-march-armv8-a.d gas/testsuite/gas/i386/arch-10-btver1.d gas/testsuite/gas/i386/arch-10-btver2.d gas/testsuite/gas/i386/nops-1-btver1.d gas/testsuite/gas/i386/nops-1-btver2.d gas/testsuite/gas/i386/x86-64-arch-2-btver1.d gas/testsuite/gas/i386/x86-64-arch-2-btver2.d gas/testsuite/gas/i386/x86-64-nops-1-btver1.d gas/testsuite/gas/i386/x86-64-nops-1-btver2.d ld/testsuite/ld-arm/attr-merge-vfp-7.d ld/testsuite/ld-arm/attr-merge-vfp-7r.d ld/testsuite/ld-arm/attr-merge-vfp-armv8-hard.s ld/testsuite/ld-arm/attr-merge-vfp-armv8.s --- diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.d b/gas/testsuite/gas/arm/armv8-a+crypto.d new file mode 100644 index 00000000000..d5b2b4b358e --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a+crypto.d @@ -0,0 +1,122 @@ +#name: Valid v8-a+cryptov1 +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f2a00e00 vmull.p64 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2efeeaf vmull.p64 q15, d31, d31 +0[0-9a-f]+ <[^>]+> f3b00300 aese.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b0e30e aese.8 q7, q7 +0[0-9a-f]+ <[^>]+> f3f00320 aese.8 q8, q8 +0[0-9a-f]+ <[^>]+> f3f0e32e aese.8 q15, q15 +0[0-9a-f]+ <[^>]+> f3b00340 aesd.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b0e34e aesd.8 q7, q7 +0[0-9a-f]+ <[^>]+> f3f00360 aesd.8 q8, q8 +0[0-9a-f]+ <[^>]+> f3f0e36e aesd.8 q15, q15 +0[0-9a-f]+ <[^>]+> f3b00380 aesmc.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b0e38e aesmc.8 q7, q7 +0[0-9a-f]+ <[^>]+> f3f003a0 aesmc.8 q8, q8 +0[0-9a-f]+ <[^>]+> f3f0e3ae aesmc.8 q15, q15 +0[0-9a-f]+ <[^>]+> f3b003c0 aesimc.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b0e3ce aesimc.8 q7, q7 +0[0-9a-f]+ <[^>]+> f3f003e0 aesimc.8 q8, q8 +0[0-9a-f]+ <[^>]+> f3f0e3ee aesimc.8 q15, q15 +0[0-9a-f]+ <[^>]+> f2000c40 sha1c.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f20eec4e sha1c.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f2400ce0 sha1c.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f24eecee sha1c.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f2100c40 sha1p.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f21eec4e sha1p.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f2500ce0 sha1p.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f25eecee sha1p.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f2200c40 sha1m.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f22eec4e sha1m.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f2600ce0 sha1m.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f26eecee sha1m.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f2300c40 sha1su0.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f23eec4e sha1su0.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f2700ce0 sha1su0.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f27eecee sha1su0.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f3000c40 sha256h.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f30eec4e sha256h.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f3400ce0 sha256h.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f34eecee sha256h.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f3100c40 sha256h2.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f31eec4e sha256h2.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f3500ce0 sha256h2.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f35eecee sha256h2.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f3200c40 sha256su1.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f32eec4e sha256su1.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f3600ce0 sha256su1.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f36eecee sha256su1.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f3b902c0 sha1h.32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b9e2ce sha1h.32 q7, q7 +0[0-9a-f]+ <[^>]+> f3f902e0 sha1h.32 q8, q8 +0[0-9a-f]+ <[^>]+> f3f9e2ee sha1h.32 q15, q15 +0[0-9a-f]+ <[^>]+> f3ba0380 sha1su1.32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bae38e sha1su1.32 q7, q7 +0[0-9a-f]+ <[^>]+> f3fa03a0 sha1su1.32 q8, q8 +0[0-9a-f]+ <[^>]+> f3fae3ae sha1su1.32 q15, q15 +0[0-9a-f]+ <[^>]+> f3ba03c0 sha256su0.32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bae3ce sha256su0.32 q7, q7 +0[0-9a-f]+ <[^>]+> f3fa03e0 sha256su0.32 q8, q8 +0[0-9a-f]+ <[^>]+> f3fae3ee sha256su0.32 q15, q15 +0[0-9a-f]+ <[^>]+> efa0 0e00 vmull.p64 q0, d0, d0 +0[0-9a-f]+ <[^>]+> efef eeaf vmull.p64 q15, d31, d31 +0[0-9a-f]+ <[^>]+> ffb0 0300 aese.8 q0, q0 +0[0-9a-f]+ <[^>]+> ffb0 e30e aese.8 q7, q7 +0[0-9a-f]+ <[^>]+> fff0 0320 aese.8 q8, q8 +0[0-9a-f]+ <[^>]+> fff0 e32e aese.8 q15, q15 +0[0-9a-f]+ <[^>]+> ffb0 0340 aesd.8 q0, q0 +0[0-9a-f]+ <[^>]+> ffb0 e34e aesd.8 q7, q7 +0[0-9a-f]+ <[^>]+> fff0 0360 aesd.8 q8, q8 +0[0-9a-f]+ <[^>]+> fff0 e36e aesd.8 q15, q15 +0[0-9a-f]+ <[^>]+> ffb0 0380 aesmc.8 q0, q0 +0[0-9a-f]+ <[^>]+> ffb0 e38e aesmc.8 q7, q7 +0[0-9a-f]+ <[^>]+> fff0 03a0 aesmc.8 q8, q8 +0[0-9a-f]+ <[^>]+> fff0 e3ae aesmc.8 q15, q15 +0[0-9a-f]+ <[^>]+> ffb0 03c0 aesimc.8 q0, q0 +0[0-9a-f]+ <[^>]+> ffb0 e3ce aesimc.8 q7, q7 +0[0-9a-f]+ <[^>]+> fff0 03e0 aesimc.8 q8, q8 +0[0-9a-f]+ <[^>]+> fff0 e3ee aesimc.8 q15, q15 +0[0-9a-f]+ <[^>]+> ef00 0c40 sha1c.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ef0e ec4e sha1c.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ef40 0ce0 sha1c.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ef4e ecee sha1c.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ef10 0c40 sha1p.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ef1e ec4e sha1p.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ef50 0ce0 sha1p.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ef5e ecee sha1p.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ef20 0c40 sha1m.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ef2e ec4e sha1m.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ef60 0ce0 sha1m.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ef6e ecee sha1m.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ef30 0c40 sha1su0.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ef3e ec4e sha1su0.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ef70 0ce0 sha1su0.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ef7e ecee sha1su0.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ff00 0c40 sha256h.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ff0e ec4e sha256h.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ff40 0ce0 sha256h.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ff4e ecee sha256h.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ff10 0c40 sha256h2.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ff1e ec4e sha256h2.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ff50 0ce0 sha256h2.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ff5e ecee sha256h2.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ff20 0c40 sha256su1.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ff2e ec4e sha256su1.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ff60 0ce0 sha256su1.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ff6e ecee sha256su1.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ffb9 02c0 sha1h.32 q0, q0 +0[0-9a-f]+ <[^>]+> ffb9 e2ce sha1h.32 q7, q7 +0[0-9a-f]+ <[^>]+> fff9 02e0 sha1h.32 q8, q8 +0[0-9a-f]+ <[^>]+> fff9 e2ee sha1h.32 q15, q15 +0[0-9a-f]+ <[^>]+> ffba 0380 sha1su1.32 q0, q0 +0[0-9a-f]+ <[^>]+> ffba e38e sha1su1.32 q7, q7 +0[0-9a-f]+ <[^>]+> fffa 03a0 sha1su1.32 q8, q8 +0[0-9a-f]+ <[^>]+> fffa e3ae sha1su1.32 q15, q15 +0[0-9a-f]+ <[^>]+> ffba 03c0 sha256su0.32 q0, q0 +0[0-9a-f]+ <[^>]+> ffba e3ce sha256su0.32 q7, q7 +0[0-9a-f]+ <[^>]+> fffa 03e0 sha256su0.32 q8, q8 +0[0-9a-f]+ <[^>]+> fffa e3ee sha256su0.32 q15, q15 diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.s b/gas/testsuite/gas/arm/armv8-a+crypto.s new file mode 100644 index 00000000000..679f6045bad --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a+crypto.s @@ -0,0 +1,123 @@ + .syntax unified + .arch armv8-a + .arch_extension crypto + + .arm + vmull.p64 q0, d0, d0 + vmull.p64 q15, d31, d31 + aese.8 q0, q0 + aese.8 q7, q7 + aese.8 q8, q8 + aese.8 q15, q15 + aesd.8 q0, q0 + aesd.8 q7, q7 + aesd.8 q8, q8 + aesd.8 q15, q15 + aesmc.8 q0, q0 + aesmc.8 q7, q7 + aesmc.8 q8, q8 + aesmc.8 q15, q15 + aesimc.8 q0, q0 + aesimc.8 q7, q7 + aesimc.8 q8, q8 + aesimc.8 q15, q15 + sha1c.32 q0, q0, q0 + sha1c.32 q7, q7, q7 + sha1c.32 q8, q8, q8 + sha1c.32 q15, q15, q15 + sha1p.32 q0, q0, q0 + sha1p.32 q7, q7, q7 + sha1p.32 q8, q8, q8 + sha1p.32 q15, q15, q15 + sha1m.32 q0, q0, q0 + sha1m.32 q7, q7, q7 + sha1m.32 q8, q8, q8 + sha1m.32 q15, q15, q15 + sha1su0.32 q0, q0, q0 + sha1su0.32 q7, q7, q7 + sha1su0.32 q8, q8, q8 + sha1su0.32 q15, q15, q15 + sha256h.32 q0, q0, q0 + sha256h.32 q7, q7, q7 + sha256h.32 q8, q8, q8 + sha256h.32 q15, q15, q15 + sha256h2.32 q0, q0, q0 + sha256h2.32 q7, q7, q7 + sha256h2.32 q8, q8, q8 + sha256h2.32 q15, q15, q15 + sha256su1.32 q0, q0, q0 + sha256su1.32 q7, q7, q7 + sha256su1.32 q8, q8, q8 + sha256su1.32 q15, q15, q15 + sha1h.32 q0, q0 + sha1h.32 q7, q7 + sha1h.32 q8, q8 + sha1h.32 q15, q15 + sha1su1.32 q0, q0 + sha1su1.32 q7, q7 + sha1su1.32 q8, q8 + sha1su1.32 q15, q15 + sha256su0.32 q0, q0 + sha256su0.32 q7, q7 + sha256su0.32 q8, q8 + sha256su0.32 q15, q15 + + .thumb + vmull.p64 q0, d0, d0 + vmull.p64 q15, d31, d31 + aese.8 q0, q0 + aese.8 q7, q7 + aese.8 q8, q8 + aese.8 q15, q15 + aesd.8 q0, q0 + aesd.8 q7, q7 + aesd.8 q8, q8 + aesd.8 q15, q15 + aesmc.8 q0, q0 + aesmc.8 q7, q7 + aesmc.8 q8, q8 + aesmc.8 q15, q15 + aesimc.8 q0, q0 + aesimc.8 q7, q7 + aesimc.8 q8, q8 + aesimc.8 q15, q15 + sha1c.32 q0, q0, q0 + sha1c.32 q7, q7, q7 + sha1c.32 q8, q8, q8 + sha1c.32 q15, q15, q15 + sha1p.32 q0, q0, q0 + sha1p.32 q7, q7, q7 + sha1p.32 q8, q8, q8 + sha1p.32 q15, q15, q15 + sha1m.32 q0, q0, q0 + sha1m.32 q7, q7, q7 + sha1m.32 q8, q8, q8 + sha1m.32 q15, q15, q15 + sha1su0.32 q0, q0, q0 + sha1su0.32 q7, q7, q7 + sha1su0.32 q8, q8, q8 + sha1su0.32 q15, q15, q15 + sha256h.32 q0, q0, q0 + sha256h.32 q7, q7, q7 + sha256h.32 q8, q8, q8 + sha256h.32 q15, q15, q15 + sha256h2.32 q0, q0, q0 + sha256h2.32 q7, q7, q7 + sha256h2.32 q8, q8, q8 + sha256h2.32 q15, q15, q15 + sha256su1.32 q0, q0, q0 + sha256su1.32 q7, q7, q7 + sha256su1.32 q8, q8, q8 + sha256su1.32 q15, q15, q15 + sha1h.32 q0, q0 + sha1h.32 q7, q7 + sha1h.32 q8, q8 + sha1h.32 q15, q15 + sha1su1.32 q0, q0 + sha1su1.32 q7, q7 + sha1su1.32 q8, q8 + sha1su1.32 q15, q15 + sha256su0.32 q0, q0 + sha256su0.32 q7, q7 + sha256su0.32 q8, q8 + sha256su0.32 q15, q15 diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d new file mode 100644 index 00000000000..bb52e0a401e --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a+fp.d @@ -0,0 +1,114 @@ +#name: Valid v8-a+fp +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> fe000a00 vseleq.f32 s0, s0, s0 +0[0-9a-f]+ <[^>]+> fe500aa0 vselvs.f32 s1, s1, s1 +0[0-9a-f]+ <[^>]+> fe2ffa0f vselge.f32 s30, s30, s30 +0[0-9a-f]+ <[^>]+> fe7ffaaf vselgt.f32 s31, s31, s31 +0[0-9a-f]+ <[^>]+> fe000b00 vseleq.f64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> fe500ba0 vselvs.f64 d16, d16, d16 +0[0-9a-f]+ <[^>]+> fe2ffb0f vselge.f64 d15, d15, d15 +0[0-9a-f]+ <[^>]+> fe7ffbaf vselgt.f64 d31, d31, d31 +0[0-9a-f]+ <[^>]+> fe800a00 vmaxnm.f32 s0, s0, s0 +0[0-9a-f]+ <[^>]+> fec00aa0 vmaxnm.f32 s1, s1, s1 +0[0-9a-f]+ <[^>]+> fe8ffa0f vmaxnm.f32 s30, s30, s30 +0[0-9a-f]+ <[^>]+> fecffaaf vmaxnm.f32 s31, s31, s31 +0[0-9a-f]+ <[^>]+> fe800b00 vmaxnm.f64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> fec00ba0 vmaxnm.f64 d16, d16, d16 +0[0-9a-f]+ <[^>]+> fe8ffb0f vmaxnm.f64 d15, d15, d15 +0[0-9a-f]+ <[^>]+> fecffbaf vmaxnm.f64 d31, d31, d31 +0[0-9a-f]+ <[^>]+> fe800a40 vminnm.f32 s0, s0, s0 +0[0-9a-f]+ <[^>]+> fec00ae0 vminnm.f32 s1, s1, s1 +0[0-9a-f]+ <[^>]+> fe8ffa4f vminnm.f32 s30, s30, s30 +0[0-9a-f]+ <[^>]+> fecffaef vminnm.f32 s31, s31, s31 +0[0-9a-f]+ <[^>]+> fe800b40 vminnm.f64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> fec00be0 vminnm.f64 d16, d16, d16 +0[0-9a-f]+ <[^>]+> fe8ffb4f vminnm.f64 d15, d15, d15 +0[0-9a-f]+ <[^>]+> fecffbef vminnm.f64 d31, d31, d31 +0[0-9a-f]+ <[^>]+> febc0ac0 vcvta.s32.f32 s0, s0 +0[0-9a-f]+ <[^>]+> fefd0ae0 vcvtn.s32.f32 s1, s1 +0[0-9a-f]+ <[^>]+> febefa4f vcvtp.u32.f32 s30, s30 +0[0-9a-f]+ <[^>]+> fefffa6f vcvtm.u32.f32 s31, s31 +0[0-9a-f]+ <[^>]+> febc0b40 vcvta.u32.f64 s0, d0 +0[0-9a-f]+ <[^>]+> fefd0b60 vcvtn.u32.f64 s1, d16 +0[0-9a-f]+ <[^>]+> febefb4f vcvtp.u32.f64 s30, d15 +0[0-9a-f]+ <[^>]+> fefffb6f vcvtm.u32.f64 s31, d31 +0[0-9a-f]+ <[^>]+> eeb60ac0 vrintz.f32.f32 s0, s0 +0[0-9a-f]+ <[^>]+> eef70a60 vrintx.f32.f32 s1, s1 +0[0-9a-f]+ <[^>]+> 0eb6fa4f vrintreq.f32.f32 s30, s30 +0[0-9a-f]+ <[^>]+> feb80a40 vrinta.f32.f32 s0, s0 +0[0-9a-f]+ <[^>]+> fef90a60 vrintn.f32.f32 s1, s1 +0[0-9a-f]+ <[^>]+> febafa4f vrintp.f32.f32 s30, s30 +0[0-9a-f]+ <[^>]+> fefbfa6f vrintm.f32.f32 s31, s31 +0[0-9a-f]+ <[^>]+> eeb60bc0 vrintz.f64.f64 d0, d0 +0[0-9a-f]+ <[^>]+> eeb71b41 vrintx.f64.f64 d1, d1 +0[0-9a-f]+ <[^>]+> 0ef6eb6e vrintreq.f64.f64 d30, d30 +0[0-9a-f]+ <[^>]+> feb80b40 vrinta.f64.f64 d0, d0 +0[0-9a-f]+ <[^>]+> feb91b41 vrintn.f64.f64 d1, d1 +0[0-9a-f]+ <[^>]+> fefaeb6e vrintp.f64.f64 d30, d30 +0[0-9a-f]+ <[^>]+> fefbfb6f vrintm.f64.f64 d31, d31 +0[0-9a-f]+ <[^>]+> eeb30bc0 vcvtt.f16.f64 s0, d0 +0[0-9a-f]+ <[^>]+> eef30b60 vcvtb.f16.f64 s1, d16 +0[0-9a-f]+ <[^>]+> eeb3fbcf vcvtt.f16.f64 s30, d15 +0[0-9a-f]+ <[^>]+> eef3fb6f vcvtb.f16.f64 s31, d31 +0[0-9a-f]+ <[^>]+> eeb20bc0 vcvtt.f64.f16 d0, s0 +0[0-9a-f]+ <[^>]+> eef20b60 vcvtb.f64.f16 d16, s1 +0[0-9a-f]+ <[^>]+> eeb2fbcf vcvtt.f64.f16 d15, s30 +0[0-9a-f]+ <[^>]+> eef2fb6f vcvtb.f64.f16 d31, s31 +0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0 +0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1 +0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30 +0[0-9a-f]+ <[^>]+> fe7f faaf vselgt.f32 s31, s31, s31 +0[0-9a-f]+ <[^>]+> fe00 0b00 vseleq.f64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> fe50 0ba0 vselvs.f64 d16, d16, d16 +0[0-9a-f]+ <[^>]+> fe2f fb0f vselge.f64 d15, d15, d15 +0[0-9a-f]+ <[^>]+> fe7f fbaf vselgt.f64 d31, d31, d31 +0[0-9a-f]+ <[^>]+> fe80 0a00 vmaxnm.f32 s0, s0, s0 +0[0-9a-f]+ <[^>]+> fec0 0aa0 vmaxnm.f32 s1, s1, s1 +0[0-9a-f]+ <[^>]+> fe8f fa0f vmaxnm.f32 s30, s30, s30 +0[0-9a-f]+ <[^>]+> fecf faaf vmaxnm.f32 s31, s31, s31 +0[0-9a-f]+ <[^>]+> fe80 0b00 vmaxnm.f64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> fec0 0ba0 vmaxnm.f64 d16, d16, d16 +0[0-9a-f]+ <[^>]+> fe8f fb0f vmaxnm.f64 d15, d15, d15 +0[0-9a-f]+ <[^>]+> fecf fbaf vmaxnm.f64 d31, d31, d31 +0[0-9a-f]+ <[^>]+> fe80 0a40 vminnm.f32 s0, s0, s0 +0[0-9a-f]+ <[^>]+> fec0 0ae0 vminnm.f32 s1, s1, s1 +0[0-9a-f]+ <[^>]+> fe8f fa4f vminnm.f32 s30, s30, s30 +0[0-9a-f]+ <[^>]+> fecf faef vminnm.f32 s31, s31, s31 +0[0-9a-f]+ <[^>]+> fe80 0b40 vminnm.f64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> fec0 0be0 vminnm.f64 d16, d16, d16 +0[0-9a-f]+ <[^>]+> fe8f fb4f vminnm.f64 d15, d15, d15 +0[0-9a-f]+ <[^>]+> fecf fbef vminnm.f64 d31, d31, d31 +0[0-9a-f]+ <[^>]+> febc 0ac0 vcvta.s32.f32 s0, s0 +0[0-9a-f]+ <[^>]+> fefd 0ae0 vcvtn.s32.f32 s1, s1 +0[0-9a-f]+ <[^>]+> febe fa4f vcvtp.u32.f32 s30, s30 +0[0-9a-f]+ <[^>]+> feff fa6f vcvtm.u32.f32 s31, s31 +0[0-9a-f]+ <[^>]+> febc 0b40 vcvta.u32.f64 s0, d0 +0[0-9a-f]+ <[^>]+> fefd 0b60 vcvtn.u32.f64 s1, d16 +0[0-9a-f]+ <[^>]+> febe fb4f vcvtp.u32.f64 s30, d15 +0[0-9a-f]+ <[^>]+> feff fb6f vcvtm.u32.f64 s31, d31 +0[0-9a-f]+ <[^>]+> eeb6 0ac0 vrintz.f32.f32 s0, s0 +0[0-9a-f]+ <[^>]+> eef7 0a60 vrintx.f32.f32 s1, s1 +0[0-9a-f]+ <[^>]+> eeb6 fa4f vrintr.f32.f32 s30, s30 +0[0-9a-f]+ <[^>]+> feb8 0a40 vrinta.f32.f32 s0, s0 +0[0-9a-f]+ <[^>]+> fef9 0a60 vrintn.f32.f32 s1, s1 +0[0-9a-f]+ <[^>]+> feba fa4f vrintp.f32.f32 s30, s30 +0[0-9a-f]+ <[^>]+> fefb fa6f vrintm.f32.f32 s31, s31 +0[0-9a-f]+ <[^>]+> eeb6 0bc0 vrintz.f64.f64 d0, d0 +0[0-9a-f]+ <[^>]+> eeb7 1b41 vrintx.f64.f64 d1, d1 +0[0-9a-f]+ <[^>]+> eef6 eb6e vrintr.f64.f64 d30, d30 +0[0-9a-f]+ <[^>]+> feb8 0b40 vrinta.f64.f64 d0, d0 +0[0-9a-f]+ <[^>]+> feb9 1b41 vrintn.f64.f64 d1, d1 +0[0-9a-f]+ <[^>]+> fefa eb6e vrintp.f64.f64 d30, d30 +0[0-9a-f]+ <[^>]+> fefb fb6f vrintm.f64.f64 d31, d31 +0[0-9a-f]+ <[^>]+> eeb3 0bc0 vcvtt.f16.f64 s0, d0 +0[0-9a-f]+ <[^>]+> eef3 0b60 vcvtb.f16.f64 s1, d16 +0[0-9a-f]+ <[^>]+> eeb3 fbcf vcvtt.f16.f64 s30, d15 +0[0-9a-f]+ <[^>]+> eef3 fb6f vcvtb.f16.f64 s31, d31 +0[0-9a-f]+ <[^>]+> eeb2 0bc0 vcvtt.f64.f16 d0, s0 +0[0-9a-f]+ <[^>]+> eef2 0b60 vcvtb.f64.f16 d16, s1 +0[0-9a-f]+ <[^>]+> eeb2 fbcf vcvtt.f64.f16 d15, s30 +0[0-9a-f]+ <[^>]+> eef2 fb6f vcvtb.f64.f16 d31, s31 diff --git a/gas/testsuite/gas/arm/armv8-a+fp.s b/gas/testsuite/gas/arm/armv8-a+fp.s new file mode 100644 index 00000000000..f99302f263e --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a+fp.s @@ -0,0 +1,116 @@ + .syntax unified + .text + .arch armv8-a + .arch_extension fp + + .arm + vseleq.f32 s0, s0, s0 + vselvs.f32 s1, s1, s1 + vselge.f32 s30, s30, s30 + vselgt.f32 s31, s31, s31 + vseleq.f64 d0, d0, d0 + vselvs.f64 d16, d16, d16 + vselge.f64 d15, d15, d15 + vselgt.f64 d31, d31, d31 + vmaxnm.f32 s0, s0, s0 + vmaxnm.f32 s1, s1, s1 + vmaxnm.f32 s30, s30, s30 + vmaxnm.f32 s31, s31, s31 + vmaxnm.f64 d0, d0, d0 + vmaxnm.f64 d16, d16, d16 + vmaxnm.f64 d15, d15, d15 + vmaxnm.f64 d31, d31, d31 + vminnm.f32 s0, s0, s0 + vminnm.f32 s1, s1, s1 + vminnm.f32 s30, s30, s30 + vminnm.f32 s31, s31, s31 + vminnm.f64 d0, d0, d0 + vminnm.f64 d16, d16, d16 + vminnm.f64 d15, d15, d15 + vminnm.f64 d31, d31, d31 + vcvta.s32.f32 s0, s0 + vcvtn.s32.f32 s1, s1 + vcvtp.u32.f32 s30, s30 + vcvtm.u32.f32 s31, s31 + vcvta.s32.f64 s0, d0 + vcvtn.s32.f64 s1, d16 + vcvtp.u32.f64 s30, d15 + vcvtm.u32.f64 s31, d31 + vrintz.f32.f32 s0, s0 + vrintx.f32.f32 s1, s1 + vrintreq.f32.f32 s30, s30 + vrinta.f32.f32 s0, s0 + vrintn.f32.f32 s1, s1 + vrintp.f32.f32 s30, s30 + vrintm.f32.f32 s31, s31 + vrintz.f64.f64 d0, d0 + vrintx.f64.f64 d1, d1 + vrintreq.f64.f64 d30, d30 + vrinta.f64.f64 d0, d0 + vrintn.f64.f64 d1, d1 + vrintp.f64.f64 d30, d30 + vrintm.f64.f64 d31, d31 + vcvtt.f16.f64 s0, d0 + vcvtb.f16.f64 s1, d16 + vcvtt.f16.f64 s30, d15 + vcvtb.f16.f64 s31, d31 + vcvtt.f64.f16 d0, s0 + vcvtb.f64.f16 d16, s1 + vcvtt.f64.f16 d15, s30 + vcvtb.f64.f16 d31, s31 + + .thumb + vseleq.f32 s0, s0, s0 + vselvs.f32 s1, s1, s1 + vselge.f32 s30, s30, s30 + vselgt.f32 s31, s31, s31 + vseleq.f64 d0, d0, d0 + vselvs.f64 d16, d16, d16 + vselge.f64 d15, d15, d15 + vselgt.f64 d31, d31, d31 + vmaxnm.f32 s0, s0, s0 + vmaxnm.f32 s1, s1, s1 + vmaxnm.f32 s30, s30, s30 + vmaxnm.f32 s31, s31, s31 + vmaxnm.f64 d0, d0, d0 + vmaxnm.f64 d16, d16, d16 + vmaxnm.f64 d15, d15, d15 + vmaxnm.f64 d31, d31, d31 + vminnm.f32 s0, s0, s0 + vminnm.f32 s1, s1, s1 + vminnm.f32 s30, s30, s30 + vminnm.f32 s31, s31, s31 + vminnm.f64 d0, d0, d0 + vminnm.f64 d16, d16, d16 + vminnm.f64 d15, d15, d15 + vminnm.f64 d31, d31, d31 + vcvta.s32.f32 s0, s0 + vcvtn.s32.f32 s1, s1 + vcvtp.u32.f32 s30, s30 + vcvtm.u32.f32 s31, s31 + vcvta.s32.f64 s0, d0 + vcvtn.s32.f64 s1, d16 + vcvtp.u32.f64 s30, d15 + vcvtm.u32.f64 s31, d31 + vrintz.f32.f32 s0, s0 + vrintx.f32.f32 s1, s1 + vrintr.f32.f32 s30, s30 + vrinta.f32.f32 s0, s0 + vrintn.f32.f32 s1, s1 + vrintp.f32.f32 s30, s30 + vrintm.f32.f32 s31, s31 + vrintz.f64.f64 d0, d0 + vrintx.f64.f64 d1, d1 + vrintr.f64.f64 d30, d30 + vrinta.f64.f64 d0, d0 + vrintn.f64.f64 d1, d1 + vrintp.f64.f64 d30, d30 + vrintm.f64.f64 d31, d31 + vcvtt.f16.f64 s0, d0 + vcvtb.f16.f64 s1, d16 + vcvtt.f16.f64 s30, d15 + vcvtb.f16.f64 s31, d31 + vcvtt.f64.f16 d0, s0 + vcvtb.f64.f16 d16, s1 + vcvtt.f64.f16 d15, s30 + vcvtb.f64.f16 d31, s31 diff --git a/gas/testsuite/gas/arm/armv8-a+simd.d b/gas/testsuite/gas/arm/armv8-a+simd.d new file mode 100644 index 00000000000..c6a4a5eb5b6 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a+simd.d @@ -0,0 +1,78 @@ +#name: Valid v8-a+simdv3 +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f3000f10 vmaxnm.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3400fb0 vmaxnm.f32 d16, d16, d16 +0[0-9a-f]+ <[^>]+> f30fff1f vmaxnm.f32 d15, d15, d15 +0[0-9a-f]+ <[^>]+> f34fffbf vmaxnm.f32 d31, d31, d31 +0[0-9a-f]+ <[^>]+> f3000f50 vmaxnm.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3400ff0 vmaxnm.f32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f30eef5e vmaxnm.f32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f34eeffe vmaxnm.f32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f3200f10 vminnm.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3600fb0 vminnm.f32 d16, d16, d16 +0[0-9a-f]+ <[^>]+> f32fff1f vminnm.f32 d15, d15, d15 +0[0-9a-f]+ <[^>]+> f36fffbf vminnm.f32 d31, d31, d31 +0[0-9a-f]+ <[^>]+> f3200f50 vminnm.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3600ff0 vminnm.f32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f32eef5e vminnm.f32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f36eeffe vminnm.f32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f3bb0000 vcvta.s32.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3fb0120 vcvtn.s32.f32 d16, d16 +0[0-9a-f]+ <[^>]+> f3bbf28f vcvtp.u32.f32 d15, d15 +0[0-9a-f]+ <[^>]+> f3fbf3af vcvtm.u32.f32 d31, d31 +0[0-9a-f]+ <[^>]+> f3bb0040 vcvta.s32.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3fb0160 vcvtn.s32.f32 q8, q8 +0[0-9a-f]+ <[^>]+> f3bbe2ce vcvtp.u32.f32 q7, q7 +0[0-9a-f]+ <[^>]+> f3fbe3ee vcvtm.u32.f32 q15, q15 +0[0-9a-f]+ <[^>]+> f3ba0500 vrinta.f32.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3fa0420 vrintn.f32.f32 d16, d16 +0[0-9a-f]+ <[^>]+> f3baf68f vrintm.f32.f32 d15, d15 +0[0-9a-f]+ <[^>]+> f3faf7af vrintp.f32.f32 d31, d31 +0[0-9a-f]+ <[^>]+> f3ba04af vrintx.f32.f32 d0, d31 +0[0-9a-f]+ <[^>]+> f3fa058f vrintz.f32.f32 d16, d15 +0[0-9a-f]+ <[^>]+> f3ba0540 vrinta.f32.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3fa0460 vrintn.f32.f32 q8, q8 +0[0-9a-f]+ <[^>]+> f3bae6ce vrintm.f32.f32 q7, q7 +0[0-9a-f]+ <[^>]+> f3fae7ee vrintp.f32.f32 q15, q15 +0[0-9a-f]+ <[^>]+> f3ba04ee vrintx.f32.f32 q0, q15 +0[0-9a-f]+ <[^>]+> f3fa05ce vrintz.f32.f32 q8, q7 +0[0-9a-f]+ <[^>]+> ff00 0f10 vmaxnm.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> ff40 0fb0 vmaxnm.f32 d16, d16, d16 +0[0-9a-f]+ <[^>]+> ff0f ff1f vmaxnm.f32 d15, d15, d15 +0[0-9a-f]+ <[^>]+> ff4f ffbf vmaxnm.f32 d31, d31, d31 +0[0-9a-f]+ <[^>]+> ff00 0f50 vmaxnm.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ff40 0ff0 vmaxnm.f32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ff0e ef5e vmaxnm.f32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ff4e effe vmaxnm.f32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ff20 0f10 vminnm.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> ff60 0fb0 vminnm.f32 d16, d16, d16 +0[0-9a-f]+ <[^>]+> ff2f ff1f vminnm.f32 d15, d15, d15 +0[0-9a-f]+ <[^>]+> ff6f ffbf vminnm.f32 d31, d31, d31 +0[0-9a-f]+ <[^>]+> ff20 0f50 vminnm.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ff60 0ff0 vminnm.f32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ff2e ef5e vminnm.f32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ff6e effe vminnm.f32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ffbb 0000 vcvta.s32.f32 d0, d0 +0[0-9a-f]+ <[^>]+> fffb 0120 vcvtn.s32.f32 d16, d16 +0[0-9a-f]+ <[^>]+> ffbb f28f vcvtp.u32.f32 d15, d15 +0[0-9a-f]+ <[^>]+> fffb f3af vcvtm.u32.f32 d31, d31 +0[0-9a-f]+ <[^>]+> ffbb 0040 vcvta.s32.f32 q0, q0 +0[0-9a-f]+ <[^>]+> fffb 0160 vcvtn.s32.f32 q8, q8 +0[0-9a-f]+ <[^>]+> ffbb e2ce vcvtp.u32.f32 q7, q7 +0[0-9a-f]+ <[^>]+> fffb e3ee vcvtm.u32.f32 q15, q15 +0[0-9a-f]+ <[^>]+> ffba 0500 vrinta.f32.f32 d0, d0 +0[0-9a-f]+ <[^>]+> fffa 0420 vrintn.f32.f32 d16, d16 +0[0-9a-f]+ <[^>]+> ffba f68f vrintm.f32.f32 d15, d15 +0[0-9a-f]+ <[^>]+> fffa f7af vrintp.f32.f32 d31, d31 +0[0-9a-f]+ <[^>]+> ffba 04af vrintx.f32.f32 d0, d31 +0[0-9a-f]+ <[^>]+> fffa 058f vrintz.f32.f32 d16, d15 +0[0-9a-f]+ <[^>]+> ffba 0540 vrinta.f32.f32 q0, q0 +0[0-9a-f]+ <[^>]+> fffa 0460 vrintn.f32.f32 q8, q8 +0[0-9a-f]+ <[^>]+> ffba e6ce vrintm.f32.f32 q7, q7 +0[0-9a-f]+ <[^>]+> fffa e7ee vrintp.f32.f32 q15, q15 +0[0-9a-f]+ <[^>]+> ffba 04ee vrintx.f32.f32 q0, q15 +0[0-9a-f]+ <[^>]+> fffa 05ce vrintz.f32.f32 q8, q7 diff --git a/gas/testsuite/gas/arm/armv8-a+simd.s b/gas/testsuite/gas/arm/armv8-a+simd.s new file mode 100644 index 00000000000..9a08a07cbe4 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a+simd.s @@ -0,0 +1,79 @@ + .syntax unified + .arch armv8-a + .arch_extension simd + + .arm + vmaxnm.f32 d0, d0, d0 + vmaxnm.f32 d16, d16, d16 + vmaxnm.f32 d15, d15, d15 + vmaxnm.f32 d31, d31, d31 + vmaxnm.f32 q0, q0, q0 + vmaxnm.f32 q8, q8, q8 + vmaxnm.f32 q7, q7, q7 + vmaxnm.f32 q15, q15, q15 + vminnm.f32 d0, d0, d0 + vminnm.f32 d16, d16, d16 + vminnm.f32 d15, d15, d15 + vminnm.f32 d31, d31, d31 + vminnm.f32 q0, q0, q0 + vminnm.f32 q8, q8, q8 + vminnm.f32 q7, q7, q7 + vminnm.f32 q15, q15, q15 + vcvta.s32.f32 d0, d0 + vcvtn.s32.f32 d16, d16 + vcvtp.u32.f32 d15, d15 + vcvtm.u32.f32 d31, d31 + vcvta.s32.f32 q0, q0 + vcvtn.s32.f32 q8, q8 + vcvtp.u32.f32 q7, q7 + vcvtm.u32.f32 q15, q15 + vrinta.f32.f32 d0, d0 + vrintn.f32.f32 d16, d16 + vrintm.f32.f32 d15, d15 + vrintp.f32.f32 d31, d31 + vrintx.f32.f32 d0, d31 + vrintz.f32.f32 d16, d15 + vrinta.f32.f32 q0, q0 + vrintn.f32.f32 q8, q8 + vrintm.f32.f32 q7, q7 + vrintp.f32.f32 q15, q15 + vrintx.f32.f32 q0, q15 + vrintz.f32.f32 q8, q7 + + .thumb + vmaxnm.f32 d0, d0, d0 + vmaxnm.f32 d16, d16, d16 + vmaxnm.f32 d15, d15, d15 + vmaxnm.f32 d31, d31, d31 + vmaxnm.f32 q0, q0, q0 + vmaxnm.f32 q8, q8, q8 + vmaxnm.f32 q7, q7, q7 + vmaxnm.f32 q15, q15, q15 + vminnm.f32 d0, d0, d0 + vminnm.f32 d16, d16, d16 + vminnm.f32 d15, d15, d15 + vminnm.f32 d31, d31, d31 + vminnm.f32 q0, q0, q0 + vminnm.f32 q8, q8, q8 + vminnm.f32 q7, q7, q7 + vminnm.f32 q15, q15, q15 + vcvta.s32.f32 d0, d0 + vcvtn.s32.f32 d16, d16 + vcvtp.u32.f32 d15, d15 + vcvtm.u32.f32 d31, d31 + vcvta.s32.f32 q0, q0 + vcvtn.s32.f32 q8, q8 + vcvtp.u32.f32 q7, q7 + vcvtm.u32.f32 q15, q15 + vrinta.f32.f32 d0, d0 + vrintn.f32.f32 d16, d16 + vrintm.f32.f32 d15, d15 + vrintp.f32.f32 d31, d31 + vrintx.f32.f32 d0, d31 + vrintz.f32.f32 d16, d15 + vrinta.f32.f32 q0, q0 + vrintn.f32.f32 q8, q8 + vrintm.f32.f32 q7, q7 + vrintp.f32.f32 q15, q15 + vrintx.f32.f32 q0, q15 + vrintz.f32.f32 q8, q7 diff --git a/gas/testsuite/gas/arm/armv8-a-bad.d b/gas/testsuite/gas/arm/armv8-a-bad.d new file mode 100644 index 00000000000..94e130c6d3d --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a-bad.d @@ -0,0 +1,2 @@ +#name: Invalid v8-a +#error-output: armv8-a-bad.l diff --git a/gas/testsuite/gas/arm/armv8-a-bad.l b/gas/testsuite/gas/arm/armv8-a-bad.l new file mode 100644 index 00000000000..7950f0a16f3 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a-bad.l @@ -0,0 +1,96 @@ +.*: Assembler messages: +.*:7: Error: swp{b} use is obsoleted for ARMv8 and later +.*:10: Warning: This coprocessor register access is deprecated in ARMv8 +.*:11: Warning: This coprocessor register access is deprecated in ARMv8 +.*:12: Warning: This coprocessor register access is deprecated in ARMv8 +.*:13: Warning: This coprocessor register access is deprecated in ARMv8 +.*:14: Warning: This coprocessor register access is deprecated in ARMv8 +.*:17: Warning: setend use is deprecated for ARMv8 +.*:20: Warning: setend use is deprecated for ARMv8 +.*:24: Error: immediate value out of range -- `hlt 0x10000' +.*:25: Error: instruction cannot be conditional -- `hltne 0x1' +.*:29: Error: immediate value out of range -- `hlt 64' +.*:31: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions +.*:31: Error: instruction is always unconditional -- `hltne 0' +.*:35: Error: r15 not allowed here -- `strlb pc,\[r0\]' +.*:36: Error: r15 not allowed here -- `strlb r0,\[pc\]' +.*:37: Error: r15 not allowed here -- `strlh pc,\[r0\]' +.*:38: Error: r15 not allowed here -- `strlh r0,\[pc\]' +.*:39: Error: r15 not allowed here -- `strl pc,\[r0\]' +.*:40: Error: r15 not allowed here -- `strl r0,\[pc\]' +.*:41: Error: r15 not allowed here -- `strlexb r1,pc,\[r0\]' +.*:42: Error: r15 not allowed here -- `strlexb r1,r0,\[pc\]' +.*:43: Error: r15 not allowed here -- `strlexb pc,r0,\[r1\]' +.*:44: Error: registers may not be the same -- `strlexb r0,r0,\[r1\]' +.*:45: Error: registers may not be the same -- `strlexb r0,r1,\[r0\]' +.*:46: Error: r15 not allowed here -- `strlexh r1,pc,\[r0\]' +.*:47: Error: r15 not allowed here -- `strlexh r1,r0,\[pc\]' +.*:48: Error: r15 not allowed here -- `strlexh pc,r0,\[r1\]' +.*:49: Error: registers may not be the same -- `strlexh r0,r0,\[r1\]' +.*:50: Error: registers may not be the same -- `strlexh r0,r1,\[r0\]' +.*:51: Error: r15 not allowed here -- `strlex r1,pc,\[r0\]' +.*:52: Error: r15 not allowed here -- `strlex r1,r0,\[pc\]' +.*:53: Error: r15 not allowed here -- `strlex pc,r0,\[r1\]' +.*:54: Error: registers may not be the same -- `strlex r0,r0,\[r1\]' +.*:55: Error: registers may not be the same -- `strlex r0,r1,\[r0\]' +.*:56: Error: r14 not allowed here -- `strlexd r1,lr,\[r0\]' +.*:57: Error: r15 not allowed here -- `strlexd r1,r0,\[pc\]' +.*:58: Error: r15 not allowed here -- `strlexd pc,r0,\[r1\]' +.*:59: Error: registers may not be the same -- `strlexd r0,r0,\[r1\]' +.*:60: Error: registers may not be the same -- `strlexd r0,r2,\[r0\]' +.*:61: Error: even register required -- `strlexd r0,r1,\[r2\]' +.*:65: Error: r15 not allowed here -- `strlb pc,\[r0\]' +.*:66: Error: r15 not allowed here -- `strlb r0,\[pc\]' +.*:67: Error: r15 not allowed here -- `strlh pc,\[r0\]' +.*:68: Error: r15 not allowed here -- `strlh r0,\[pc\]' +.*:69: Error: r15 not allowed here -- `strl pc,\[r0\]' +.*:70: Error: r15 not allowed here -- `strl r0,\[pc\]' +.*:71: Error: r15 not allowed here -- `strlexb r1,pc,\[r0\]' +.*:72: Error: r15 not allowed here -- `strlexb r1,r0,\[pc\]' +.*:73: Error: r15 not allowed here -- `strlexb pc,r0,\[r1\]' +.*:74: Error: registers may not be the same -- `strlexb r0,r0,\[r1\]' +.*:75: Error: registers may not be the same -- `strlexb r0,r1,\[r0\]' +.*:76: Error: r15 not allowed here -- `strlexh r1,pc,\[r0\]' +.*:77: Error: r15 not allowed here -- `strlexh r1,r0,\[pc\]' +.*:78: Error: r15 not allowed here -- `strlexh pc,r0,\[r1\]' +.*:79: Error: registers may not be the same -- `strlexh r0,r0,\[r1\]' +.*:80: Error: registers may not be the same -- `strlexh r0,r1,\[r0\]' +.*:81: Error: r15 not allowed here -- `strlex r1,pc,\[r0\]' +.*:82: Error: r15 not allowed here -- `strlex r1,r0,\[pc\]' +.*:83: Error: r15 not allowed here -- `strlex pc,r0,\[r1\]' +.*:84: Error: registers may not be the same -- `strlex r0,r0,\[r1\]' +.*:85: Error: registers may not be the same -- `strlex r0,r1,\[r0\]' +.*:87: Error: r15 not allowed here -- `strlexd r1,r0,\[pc\]' +.*:88: Error: r15 not allowed here -- `strlexd pc,r0,\[r1\]' +.*:89: Error: registers may not be the same -- `strlexd r0,r0,\[r1\]' +.*:90: Error: registers may not be the same -- `strlexd r0,r2,\[r0\]' +.*:95: Error: r15 not allowed here -- `ldrab pc,\[r0\]' +.*:96: Error: r15 not allowed here -- `ldrab r0,\[pc\]' +.*:97: Error: r15 not allowed here -- `ldrah pc,\[r0\]' +.*:98: Error: r15 not allowed here -- `ldrah r0,\[pc\]' +.*:99: Error: r15 not allowed here -- `ldra pc,\[r0\]' +.*:100: Error: r15 not allowed here -- `ldra r0,\[pc\]' +.*:101: Error: r15 not allowed here -- `ldraexb pc,\[r0\]' +.*:102: Error: r15 not allowed here -- `ldraexb r0,\[pc\]' +.*:103: Error: r15 not allowed here -- `ldraexh pc,\[r0\]' +.*:104: Error: r15 not allowed here -- `ldraexh r0,\[pc\]' +.*:105: Error: r15 not allowed here -- `ldraex pc,\[r0\]' +.*:106: Error: r15 not allowed here -- `ldraex r0,\[pc\]' +.*:107: Error: r14 not allowed here -- `ldraexd lr,\[r0\]' +.*:108: Error: r15 not allowed here -- `ldraexd r0,\[pc\]' +.*:109: Error: even register required -- `ldraexd r1,\[r2\]' +.*:113: Error: r15 not allowed here -- `ldrab pc,\[r0\]' +.*:114: Error: r15 not allowed here -- `ldrab r0,\[pc\]' +.*:115: Error: r15 not allowed here -- `ldrah pc,\[r0\]' +.*:116: Error: r15 not allowed here -- `ldrah r0,\[pc\]' +.*:117: Error: r15 not allowed here -- `ldra pc,\[r0\]' +.*:118: Error: r15 not allowed here -- `ldra r0,\[pc\]' +.*:119: Error: r15 not allowed here -- `ldraexb pc,\[r0\]' +.*:120: Error: r15 not allowed here -- `ldraexb r0,\[pc\]' +.*:121: Error: r15 not allowed here -- `ldraexh pc,\[r0\]' +.*:122: Error: r15 not allowed here -- `ldraexh r0,\[pc\]' +.*:123: Error: r15 not allowed here -- `ldraex pc,\[r0\]' +.*:124: Error: r15 not allowed here -- `ldraex r0,\[pc\]' +.*:125: Error: r15 not allowed here -- `ldraexd r0,pc,\[r0\]' +.*:126: Error: r15 not allowed here -- `ldraexd pc,r0,\[r0\]' +.*:127: Error: r15 not allowed here -- `ldraexd r1,r0,\[pc\]' diff --git a/gas/testsuite/gas/arm/armv8-a-bad.s b/gas/testsuite/gas/arm/armv8-a-bad.s new file mode 100644 index 00000000000..2431dc22e60 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a-bad.s @@ -0,0 +1,127 @@ + .syntax unified + .text + .arch armv8-a + + // SWP + .arm + swp r0, r1, [r2] + + // deprecated MCRs + mcr p15, 0, r0, c7, c5, 4 + mcr p15, 0, r1, c7, c10, 4 + mcr p15, 0, r2, c7, c10, 5 + mrc p14, 6, r1, c0, c0, 0 + mrc p14, 6, r0, c1, c0, 0 + + // deprecated SETEND + setend be + + .thumb + setend le + + // HLT A32 + .arm + hlt 0x10000 + hltne 0x1 + + // HLT T32 + .thumb + hlt 64 + it ne + hltne 0 + + // STRL A32 + .arm + strlb pc, [r0] + strlb r0, [pc] + strlh pc, [r0] + strlh r0, [pc] + strl pc, [r0] + strl r0, [pc] + strlexb r1, pc, [r0] + strlexb r1, r0, [pc] + strlexb pc, r0, [r1] + strlexb r0, r0, [r1] + strlexb r0, r1, [r0] + strlexh r1, pc, [r0] + strlexh r1, r0, [pc] + strlexh pc, r0, [r1] + strlexh r0, r0, [r1] + strlexh r0, r1, [r0] + strlex r1, pc, [r0] + strlex r1, r0, [pc] + strlex pc, r0, [r1] + strlex r0, r0, [r1] + strlex r0, r1, [r0] + strlexd r1, lr, [r0] + strlexd r1, r0, [pc] + strlexd pc, r0, [r1] + strlexd r0, r0, [r1] + strlexd r0, r2, [r0] + strlexd r0, r1, [r2] + + // STRL T32 + .thumb + strlb pc, [r0] + strlb r0, [pc] + strlh pc, [r0] + strlh r0, [pc] + strl pc, [r0] + strl r0, [pc] + strlexb r1, pc, [r0] + strlexb r1, r0, [pc] + strlexb pc, r0, [r1] + strlexb r0, r0, [r1] + strlexb r0, r1, [r0] + strlexh r1, pc, [r0] + strlexh r1, r0, [pc] + strlexh pc, r0, [r1] + strlexh r0, r0, [r1] + strlexh r0, r1, [r0] + strlex r1, pc, [r0] + strlex r1, r0, [pc] + strlex pc, r0, [r1] + strlex r0, r0, [r1] + strlex r0, r1, [r0] + strlexd r1, lr, [r0] + strlexd r1, r0, [pc] + strlexd pc, r0, [r1] + strlexd r0, r0, [r1] + strlexd r0, r2, [r0] + strlexd r0, r1, [r2] + + // LDRA A32 + .arm + ldrab pc, [r0] + ldrab r0, [pc] + ldrah pc, [r0] + ldrah r0, [pc] + ldra pc, [r0] + ldra r0, [pc] + ldraexb pc, [r0] + ldraexb r0, [pc] + ldraexh pc, [r0] + ldraexh r0, [pc] + ldraex pc, [r0] + ldraex r0, [pc] + ldraexd lr, [r0] + ldraexd r0, [pc] + ldraexd r1, [r2] + + // LDRA T32 + .thumb + ldrab pc, [r0] + ldrab r0, [pc] + ldrah pc, [r0] + ldrah r0, [pc] + ldra pc, [r0] + ldra r0, [pc] + ldraexb pc, [r0] + ldraexb r0, [pc] + ldraexh pc, [r0] + ldraexh r0, [pc] + ldraex pc, [r0] + ldraex r0, [pc] + ldraexd r0, pc, [r0] + ldraexd pc, r0, [r0] + ldraexd r1, r0, [pc] diff --git a/gas/testsuite/gas/arm/armv8-a-barrier-arm.d b/gas/testsuite/gas/arm/armv8-a-barrier-arm.d new file mode 100644 index 00000000000..1a245fa92dc --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a-barrier-arm.d @@ -0,0 +1,24 @@ +#name: Valid v8-A barrier (ARM) +#as: -march=armv8-a +#source: armv8-a-barrier.s +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f57ff04d dsb ld +0[0-9a-f]+ <[^>]+> f57ff049 dsb ishld +0[0-9a-f]+ <[^>]+> f57ff045 dsb nshld +0[0-9a-f]+ <[^>]+> f57ff041 dsb oshld +0[0-9a-f]+ <[^>]+> f57ff05d dmb ld +0[0-9a-f]+ <[^>]+> f57ff059 dmb ishld +0[0-9a-f]+ <[^>]+> f57ff055 dmb nshld +0[0-9a-f]+ <[^>]+> f57ff051 dmb oshld +0[0-9a-f]+ <[^>]+> f57ff04d dsb ld +0[0-9a-f]+ <[^>]+> f57ff049 dsb ishld +0[0-9a-f]+ <[^>]+> f57ff045 dsb nshld +0[0-9a-f]+ <[^>]+> f57ff041 dsb oshld +0[0-9a-f]+ <[^>]+> f57ff05d dmb ld +0[0-9a-f]+ <[^>]+> f57ff059 dmb ishld +0[0-9a-f]+ <[^>]+> f57ff055 dmb nshld +0[0-9a-f]+ <[^>]+> f57ff051 dmb oshld diff --git a/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d b/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d new file mode 100644 index 00000000000..42dae156861 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d @@ -0,0 +1,24 @@ +#name: Valid v8-A barrier (Thumb) +#as: -march=armv8-a -mthumb +#source: armv8-a-barrier.s +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f3bf 8f4d dsb ld +0[0-9a-f]+ <[^>]+> f3bf 8f49 dsb ishld +0[0-9a-f]+ <[^>]+> f3bf 8f45 dsb nshld +0[0-9a-f]+ <[^>]+> f3bf 8f41 dsb oshld +0[0-9a-f]+ <[^>]+> f3bf 8f5d dmb ld +0[0-9a-f]+ <[^>]+> f3bf 8f59 dmb ishld +0[0-9a-f]+ <[^>]+> f3bf 8f55 dmb nshld +0[0-9a-f]+ <[^>]+> f3bf 8f51 dmb oshld +0[0-9a-f]+ <[^>]+> f3bf 8f4d dsb ld +0[0-9a-f]+ <[^>]+> f3bf 8f49 dsb ishld +0[0-9a-f]+ <[^>]+> f3bf 8f45 dsb nshld +0[0-9a-f]+ <[^>]+> f3bf 8f41 dsb oshld +0[0-9a-f]+ <[^>]+> f3bf 8f5d dmb ld +0[0-9a-f]+ <[^>]+> f3bf 8f59 dmb ishld +0[0-9a-f]+ <[^>]+> f3bf 8f55 dmb nshld +0[0-9a-f]+ <[^>]+> f3bf 8f51 dmb oshld diff --git a/gas/testsuite/gas/arm/armv8-a-barrier.s b/gas/testsuite/gas/arm/armv8-a-barrier.s new file mode 100644 index 00000000000..f7b71c0cc43 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a-barrier.s @@ -0,0 +1,18 @@ + .syntax unified + .text + dsb ld + dsb ishld + dsb nshld + dsb oshld + dmb ld + dmb ishld + dmb nshld + dmb oshld + dsb LD + dsb ISHLD + dsb NSHLD + dsb OSHLD + dmb LD + dmb ISHLD + dmb NSHLD + dmb OSHLD diff --git a/gas/testsuite/gas/arm/armv8-a-it-bad.d b/gas/testsuite/gas/arm/armv8-a-it-bad.d new file mode 100644 index 00000000000..4789484238a --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a-it-bad.d @@ -0,0 +1,3 @@ +#name: Deprecated IT blocks (ARM v8) +#error-output: armv8-a-it-bad.l +#as: -mimplicit-it=always diff --git a/gas/testsuite/gas/arm/armv8-a-it-bad.l b/gas/testsuite/gas/arm/armv8-a-it-bad.l new file mode 100644 index 00000000000..aa1b53b8b28 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a-it-bad.l @@ -0,0 +1,14 @@ +.*: Assembler messages: +.*:7: Warning: it blocks containing wide Thumb instructions are deprecated in ARMv8 +.*:15: Warning: it blocks of more than one conditional instruction are deprecated in ARMv8 +.*:20: Warning: it blocks of more than one conditional instruction are deprecated in ARMv8 +.*:30: Warning: it blocks containing wide Thumb instructions are deprecated in ARMv8 +.*:36: Warning: it blocks of more than one conditional instruction are deprecated in ARMv8 +.*:40: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM +.*:43: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions +.*:49: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Literal loads +.*:52: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Hi-register ADD, MOV, CMP, BX, BLX using pc +.*:55: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM +.*:55: Error: r15 not allowed here -- `addeq r0,pc,pc' +.*:58: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM +.*:58: Error: r15 not allowed here -- `addeq pc,r0,r0' diff --git a/gas/testsuite/gas/arm/armv8-a-it-bad.s b/gas/testsuite/gas/arm/armv8-a-it-bad.s new file mode 100644 index 00000000000..42f2b86b190 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a-it-bad.s @@ -0,0 +1,58 @@ +.syntax unified +.arch armv8-a + +.thumb +@ Wide instruction in IT block is deprecated. +it eq +ldrdeq r0, [r1] + +@ This IT block is not deprecated. +it eq +moveq r2, r3 + +@ IT block of more than one instruction is deprecated. +itt eq +moveq r0, r1 +moveq r2, r3 + +@ Even for auto IT blocks +moveq r2, r3 +movne r2, r3 + +adds r0, r1 + +@ This automatic IT block is valid +moveq r2,r3 + +add r0, r1, r2 + +@ This one is too wide. +ldrdeq r0, [r1] + +add r0, r1, r2 + +@ Test automatic IT block generation at end of a file. +movne r0, r1 +moveq r1, r0 + +@ Test the various classes of 16-bit instructions that are deprecated. +it eq +svceq 0 + +it eq +uxtheq r0, r1 + +it eq +addeq r0, pc, #0 + +it eq +ldreq r0, [pc, #4] + +it eq +bxeq pc + +it eq +addeq r0, pc, pc + +it eq +addeq pc, r0, r0 diff --git a/gas/testsuite/gas/arm/armv8-a.d b/gas/testsuite/gas/arm/armv8-a.d new file mode 100644 index 00000000000..03219cafa67 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a.d @@ -0,0 +1,102 @@ +#name: Valid v8-a +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e320f005 sevl +0[0-9a-f]+ <[^>]+> e1000070 hlt 0x0000 +0[0-9a-f]+ <[^>]+> e100007f hlt 0x000f +0[0-9a-f]+ <[^>]+> e10fff70 hlt 0xfff0 +0[0-9a-f]+ <[^>]+> e1c0fc90 strlb r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1c1fc91 strlb r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1cefc9e strlb lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1e0fc90 strlh r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1e1fc91 strlh r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1eefc9e strlh lr, \[lr\] +0[0-9a-f]+ <[^>]+> e180fc90 strl r0, \[r0\] +0[0-9a-f]+ <[^>]+> e181fc91 strl r1, \[r1\] +0[0-9a-f]+ <[^>]+> e18efc9e strl lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1ce0e91 strlexb r0, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e1c01e9e strlexb r1, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e1c1ee90 strlexb lr, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e1ee0e91 strlexh r0, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e1e01e9e strlexh r1, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e1e1ee90 strlexh lr, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e18e0e91 strlex r0, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e1801e9e strlex r1, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e181ee90 strlex lr, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e1ae0e92 strlexd r0, r2, r3, \[lr\] +0[0-9a-f]+ <[^>]+> e1a01e9c strlexd r1, ip, sp, \[r0\] +0[0-9a-f]+ <[^>]+> e1a1ee90 strlexd lr, r0, r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1d00c9f ldrab r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1d11c9f ldrab r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1deec9f ldrab lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1f00c9f ldraexh r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1f11c9f ldraexh r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1feec9f ldraexh lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1900c9f ldra r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1911c9f ldra r1, \[r1\] +0[0-9a-f]+ <[^>]+> e19eec9f ldra lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1d00e9f ldraexb r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1d11e9f ldraexb r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1deee9f ldraexb lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1f00e9f ldraexh r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1f11e9f ldraexh r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1feee9f ldraexh lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1900e9f ldraex r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1911e9f ldraex r1, \[r1\] +0[0-9a-f]+ <[^>]+> e19eee9f ldraex lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1b00e9f ldraexd r0, r1, \[r0\] +0[0-9a-f]+ <[^>]+> e1b12e9f ldraexd r2, r3, \[r1\] +0[0-9a-f]+ <[^>]+> e1bece9f ldraexd ip, sp, \[lr\] +0[0-9a-f]+ <[^>]+> bf50 sevl +0[0-9a-f]+ <[^>]+> bf50 sevl +0[0-9a-f]+ <[^>]+> f3af 8005 sevl.w +0[0-9a-f]+ <[^>]+> f78f 8001 dcps1 +0[0-9a-f]+ <[^>]+> f78f 8002 dcps2 +0[0-9a-f]+ <[^>]+> f78f 8003 dcps3 +0[0-9a-f]+ <[^>]+> ba80 hlt 0x0000 +0[0-9a-f]+ <[^>]+> babf hlt 0x003f +0[0-9a-f]+ <[^>]+> e8c0 0f8f strlb r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 1f8f strlb r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8ce ef8f strlb lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8c0 0f9f strlh r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 1f9f strlh r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8ce ef9f strlh lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8c0 0faf strl r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 1faf strl r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8ce efaf strl lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8ce 1fc0 strlexb r0, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e8c0 efc1 strlexb r1, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 0fce strlexb lr, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e8ce 1fd0 strlexh r0, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e8c0 efd1 strlexh r1, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 0fde strlexh lr, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e8ce 1fe0 strlex r0, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e8c0 efe1 strlex r1, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 0fee strlex lr, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e8ce 11f0 strlexd r0, r1, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e8c0 eef1 strlexd r1, lr, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 00fe strlexd lr, r0, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e8d0 0f8f ldrab r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1f8f ldrab r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8de ef8f ldrab lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8d0 0f9f ldrah r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1f9f ldrah r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8de ef9f ldrah lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8d0 0faf ldra r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1faf ldra r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8de efaf ldra lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8d0 0fcf ldraexb r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1fcf ldraexb r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8de efcf ldraexb lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8d0 0fdf ldraexh r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1fdf ldraexh r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8de efdf ldraexh lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8d0 0fef ldraex r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1fef ldraex r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8de efef ldraex lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8d0 01ff ldraexd r0, r1, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1eff ldraexd r1, lr, \[r1\] +0[0-9a-f]+ <[^>]+> e8de e0ff ldraexd lr, r0, \[lr\] diff --git a/gas/testsuite/gas/arm/armv8-a.s b/gas/testsuite/gas/arm/armv8-a.s new file mode 100644 index 00000000000..f35d00030ab --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a.s @@ -0,0 +1,106 @@ + .syntax unified + .text + .arch armv8-a + + .arm +foo: + sevl + hlt 0x0 + hlt 0xf + hlt 0xfff0 + strlb r0, [r0] + strlb r1, [r1] + strlb r14, [r14] + strlh r0, [r0] + strlh r1, [r1] + strlh r14, [r14] + strl r0, [r0] + strl r1, [r1] + strl r14, [r14] + strlexb r0, r1, [r14] + strlexb r1, r14, [r0] + strlexb r14, r0, [r1] + strlexh r0, r1, [r14] + strlexh r1, r14, [r0] + strlexh r14, r0, [r1] + strlex r0, r1, [r14] + strlex r1, r14, [r0] + strlex r14, r0, [r1] + strlexd r0, r2, r3, [r14] + strlexd r1, r12, r13, [r0] + strlexd r14, r0, r1, [r1] + ldrab r0, [r0] + ldrab r1, [r1] + ldrab r14, [r14] + ldrah r0, [r0] + ldrah r1, [r1] + ldrah r14, [r14] + ldra r0, [r0] + ldra r1, [r1] + ldra r14, [r14] + ldraexb r0, [r0] + ldraexb r1, [r1] + ldraexb r14, [r14] + ldraexh r0, [r0] + ldraexh r1, [r1] + ldraexh r14, [r14] + ldraex r0, [r0] + ldraex r1, [r1] + ldraex r14, [r14] + ldraexd r0, r1, [r0] + ldraexd r2, r3, [r1] + ldraexd r12, r13, [r14] + + .thumb + .thumb_func +bar: + sevl + sevl.n + sevl.w + dcps1 + dcps2 + dcps3 + hlt 0 + hlt 63 + strlb r0, [r0] + strlb r1, [r1] + strlb r14, [r14] + strlh r0, [r0] + strlh r1, [r1] + strlh r14, [r14] + strl r0, [r0] + strl r1, [r1] + strl r14, [r14] + strlexb r0, r1, [r14] + strlexb r1, r14, [r0] + strlexb r14, r0, [r1] + strlexh r0, r1, [r14] + strlexh r1, r14, [r0] + strlexh r14, r0, [r1] + strlex r0, r1, [r14] + strlex r1, r14, [r0] + strlex r14, r0, [r1] + strlexd r0, r1, r1, [r14] + strlexd r1, r14, r14, [r0] + strlexd r14, r0, r0, [r1] + ldrab r0, [r0] + ldrab r1, [r1] + ldrab r14, [r14] + ldrah r0, [r0] + ldrah r1, [r1] + ldrah r14, [r14] + ldra r0, [r0] + ldra r1, [r1] + ldra r14, [r14] + ldraexb r0, [r0] + ldraexb r1, [r1] + ldraexb r14, [r14] + ldraexh r0, [r0] + ldraexh r1, [r1] + ldraexh r14, [r14] + ldraex r0, [r0] + ldraex r1, [r1] + ldraex r14, [r14] + ldraexd r0, r1, [r0] + ldraexd r1, r14, [r1] + ldraexd r14, r0, [r14] diff --git a/gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d b/gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d new file mode 100644 index 00000000000..f1d9cf43d8e --- /dev/null +++ b/gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d @@ -0,0 +1,18 @@ +# name: attributes for -march=armv8-a+crypto +# source: blank.s +# as: -march=armv8-a+crypto +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_FP_arch: FP for ARMv8 + Tag_Advanced_SIMD_arch: NEON for ARMv8 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/gas/testsuite/gas/arm/attr-march-armv8-a+fp.d b/gas/testsuite/gas/arm/attr-march-armv8-a+fp.d new file mode 100644 index 00000000000..54d472f3f81 --- /dev/null +++ b/gas/testsuite/gas/arm/attr-march-armv8-a+fp.d @@ -0,0 +1,17 @@ +# name: attributes for -march=armv8-a+fp +# source: blank.s +# as: -march=armv8-a+fp +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_FP_arch: FP for ARMv8 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/gas/testsuite/gas/arm/attr-march-armv8-a+simd.d b/gas/testsuite/gas/arm/attr-march-armv8-a+simd.d new file mode 100644 index 00000000000..e8e6af999bc --- /dev/null +++ b/gas/testsuite/gas/arm/attr-march-armv8-a+simd.d @@ -0,0 +1,18 @@ +# name: attributes for -march=armv8-a+simd +# source: blank.s +# as: -march=armv8-a+simd +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_FP_arch: FP for ARMv8 + Tag_Advanced_SIMD_arch: NEON for ARMv8 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/gas/testsuite/gas/arm/attr-march-armv8-a.d b/gas/testsuite/gas/arm/attr-march-armv8-a.d new file mode 100644 index 00000000000..d02bc65193c --- /dev/null +++ b/gas/testsuite/gas/arm/attr-march-armv8-a.d @@ -0,0 +1,16 @@ +# name: attributes for -march=armv8-a +# source: blank.s +# as: -march=armv8-a +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/gas/testsuite/gas/i386/arch-10-btver1.d b/gas/testsuite/gas/i386/arch-10-btver1.d new file mode 100644 index 00000000000..92a415186a6 --- /dev/null +++ b/gas/testsuite/gas/i386/arch-10-btver1.d @@ -0,0 +1,42 @@ +#source: arch-10.s +#as: -march=btver1+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+movbe+ept+clflush+svme+padlock+fma+bmi+tbm +#objdump: -dw +#name: i386 arch 10 (btver1) + +.*: file format .* + +Disassembly of section .text: + +0+ <.text>: +[ ]*[a-f0-9]+: 0f 44 d8 cmove %eax,%ebx +[ ]*[a-f0-9]+: 0f ae 38 clflush \(%eax\) +[ ]*[a-f0-9]+: 0f 05 syscall +[ ]*[a-f0-9]+: 0f fc dc paddb %mm4,%mm3 +[ ]*[a-f0-9]+: f3 0f 58 dc addss %xmm4,%xmm3 +[ ]*[a-f0-9]+: f2 0f 58 dc addsd %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f d0 dc addsubpd %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3 +[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx +[ ]*[a-f0-9]+: c5 fc 77 vzeroall +[ ]*[a-f0-9]+: 0f 01 c4 vmxoff +[ ]*[a-f0-9]+: 0f 37 getsec +[ ]*[a-f0-9]+: 0f 01 d0 xgetbv +[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \(%ecx\) +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0 +[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%ecx\),%xmm0,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 44 d4 08 vpclmulqdq \$0x8,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx +[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx +[ ]*[a-f0-9]+: 0f 01 f9 rdtscp +[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%esi,2\) +[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1 +[ ]*[a-f0-9]+: 0f 01 da vmload +[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx +[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng +[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\) +[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx +[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx +#pass diff --git a/gas/testsuite/gas/i386/arch-10-btver2.d b/gas/testsuite/gas/i386/arch-10-btver2.d new file mode 100644 index 00000000000..c6a8d662d31 --- /dev/null +++ b/gas/testsuite/gas/i386/arch-10-btver2.d @@ -0,0 +1,42 @@ +#source: arch-10.s +#as: -march=btver2+smx+vmx+ept+clflush+svme+padlock+fma+tbm +#objdump: -dw +#name: i386 arch 10 (btver2) + +.*: file format .* + +Disassembly of section .text: + +0+ <.text>: +[ ]*[a-f0-9]+: 0f 44 d8 cmove %eax,%ebx +[ ]*[a-f0-9]+: 0f ae 38 clflush \(%eax\) +[ ]*[a-f0-9]+: 0f 05 syscall +[ ]*[a-f0-9]+: 0f fc dc paddb %mm4,%mm3 +[ ]*[a-f0-9]+: f3 0f 58 dc addss %xmm4,%xmm3 +[ ]*[a-f0-9]+: f2 0f 58 dc addsd %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f d0 dc addsubpd %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3 +[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx +[ ]*[a-f0-9]+: c5 fc 77 vzeroall +[ ]*[a-f0-9]+: 0f 01 c4 vmxoff +[ ]*[a-f0-9]+: 0f 37 getsec +[ ]*[a-f0-9]+: 0f 01 d0 xgetbv +[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \(%ecx\) +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0 +[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%ecx\),%xmm0,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 44 d4 08 vpclmulqdq \$0x8,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx +[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx +[ ]*[a-f0-9]+: 0f 01 f9 rdtscp +[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%esi,2\) +[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1 +[ ]*[a-f0-9]+: 0f 01 da vmload +[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx +[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng +[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\) +[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx +[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx +#pass diff --git a/gas/testsuite/gas/i386/nops-1-btver1.d b/gas/testsuite/gas/i386/nops-1-btver1.d new file mode 100644 index 00000000000..4bc5fc51cb7 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-1-btver1.d @@ -0,0 +1,162 @@ +#as: -mtune=btver1 +#source: nops-1.s +#objdump: -drw +#name: i386 -mtune=btver1 nops 1 + +.*: +file format .* + + +Disassembly of section .text: + +0+ : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\) +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%eax,%eax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\) +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\) +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\) +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%eax,%eax,1\) +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\) + +0+60 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 84 00 00 00 00 00 nopw 0x0\(%eax,%eax,1\) + +0+70 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%eax,%eax,1\) + +0+80 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\) + +0+90 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\) + +0+a0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%eax,%eax,1\) + +0+b0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 40 00 nopl 0x0\(%eax\) + +0+c0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\) + +0+d0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/nops-1-btver2.d b/gas/testsuite/gas/i386/nops-1-btver2.d new file mode 100644 index 00000000000..7e88b612cc0 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-1-btver2.d @@ -0,0 +1,162 @@ +#as: -mtune=btver2 +#source: nops-1.s +#objdump: -drw +#name: i386 -mtune=btver2 nops 1 + +.*: +file format .* + + +Disassembly of section .text: + +0+ : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\) +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%eax,%eax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\) +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\) +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\) +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%eax,%eax,1\) +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\) + +0+60 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 84 00 00 00 00 00 nopw 0x0\(%eax,%eax,1\) + +0+70 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%eax,%eax,1\) + +0+80 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\) + +0+90 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\) + +0+a0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%eax,%eax,1\) + +0+b0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 40 00 nopl 0x0\(%eax\) + +0+c0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\) + +0+d0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/x86-64-arch-2-btver1.d b/gas/testsuite/gas/i386/x86-64-arch-2-btver1.d new file mode 100644 index 00000000000..8cfa78003ee --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-arch-2-btver1.d @@ -0,0 +1,41 @@ +#source: x86-64-arch-2.s +#as: -march=btver1+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+movbe+ept+clflush+svme+padlock+fma+bmi+tbm +#objdump: -dw +#name: x86-64 arch 2 (btver1) + +.*: file format .* + +Disassembly of section .text: + +0+ <.text>: +[ ]*[a-f0-9]+: 0f 44 d8 cmove %eax,%ebx +[ ]*[a-f0-9]+: 0f ae 38 clflush \(%rax\) +[ ]*[a-f0-9]+: 0f 05 syscall +[ ]*[a-f0-9]+: 0f fc dc paddb %mm4,%mm3 +[ ]*[a-f0-9]+: f3 0f 58 dc addss %xmm4,%xmm3 +[ ]*[a-f0-9]+: f2 0f 58 dc addsd %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f d0 dc addsubpd %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3 +[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx +[ ]*[a-f0-9]+: c5 fc 77 vzeroall +[ ]*[a-f0-9]+: 0f 01 c4 vmxoff +[ ]*[a-f0-9]+: 0f 37 getsec +[ ]*[a-f0-9]+: 0f 01 d0 xgetbv +[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \(%rcx\) +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0 +[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%rcx\),%xmm0,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 44 d4 08 vpclmulqdq \$0x8,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx +[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx +[ ]*[a-f0-9]+: 0f 01 f9 rdtscp +[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%rsi,2\) +[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1 +[ ]*[a-f0-9]+: 0f 01 da vmload +[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx +[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng +[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx +[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx +#pass diff --git a/gas/testsuite/gas/i386/x86-64-arch-2-btver2.d b/gas/testsuite/gas/i386/x86-64-arch-2-btver2.d new file mode 100644 index 00000000000..61e8fae016e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-arch-2-btver2.d @@ -0,0 +1,41 @@ +#source: x86-64-arch-2.s +#as: -march=btver2+smx+vmx+ept+clflush+svme+padlock+fma+tbm +#objdump: -dw +#name: x86-64 arch 2 (btver2) + +.*: file format .* + +Disassembly of section .text: + +0+ <.text>: +[ ]*[a-f0-9]+: 0f 44 d8 cmove %eax,%ebx +[ ]*[a-f0-9]+: 0f ae 38 clflush \(%rax\) +[ ]*[a-f0-9]+: 0f 05 syscall +[ ]*[a-f0-9]+: 0f fc dc paddb %mm4,%mm3 +[ ]*[a-f0-9]+: f3 0f 58 dc addss %xmm4,%xmm3 +[ ]*[a-f0-9]+: f2 0f 58 dc addsd %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f d0 dc addsubpd %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3 +[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx +[ ]*[a-f0-9]+: c5 fc 77 vzeroall +[ ]*[a-f0-9]+: 0f 01 c4 vmxoff +[ ]*[a-f0-9]+: 0f 37 getsec +[ ]*[a-f0-9]+: 0f 01 d0 xgetbv +[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \(%rcx\) +[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0 +[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0 +[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%rcx\),%xmm0,%xmm2 +[ ]*[a-f0-9]+: c4 e3 49 44 d4 08 vpclmulqdq \$0x8,%xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2 +[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx +[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx +[ ]*[a-f0-9]+: 0f 01 f9 rdtscp +[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%rsi,2\) +[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1 +[ ]*[a-f0-9]+: 0f 01 da vmload +[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx +[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng +[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx +[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-1-btver1.d b/gas/testsuite/gas/i386/x86-64-nops-1-btver1.d new file mode 100644 index 00000000000..a8f0295b19a --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-1-btver1.d @@ -0,0 +1,162 @@ +#as: -mtune=btver1 +#source: nops-1.s +#objdump: -drw +#name: x86-64 -mtune=btver1 nops 1 + +.*: +file format .* + + +Disassembly of section .text: + +0+ : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%rax,%rax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\) + +0+60 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 84 00 00 00 00 00 nopw 0x0\(%rax,%rax,1\) + +0+70 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%rax,%rax,1\) + +0+80 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) + +0+90 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) + +0+a0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) + +0+b0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 40 00 nopl 0x0\(%rax\) + +0+c0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\) + +0+d0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-1-btver2.d b/gas/testsuite/gas/i386/x86-64-nops-1-btver2.d new file mode 100644 index 00000000000..8474dcaeb15 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-1-btver2.d @@ -0,0 +1,162 @@ +#as: -mtune=btver2 +#source: nops-1.s +#objdump: -drw +#name: x86-64 -mtune=btver2 nops 1 + +.*: +file format .* + + +Disassembly of section .text: + +0+ : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%rax,%rax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\) + +0+60 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 84 00 00 00 00 00 nopw 0x0\(%rax,%rax,1\) + +0+70 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%rax,%rax,1\) + +0+80 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) + +0+90 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) + +0+a0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) + +0+b0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 40 00 nopl 0x0\(%rax\) + +0+c0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\) + +0+d0 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax +#pass diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-7.d b/ld/testsuite/ld-arm/attr-merge-vfp-7.d new file mode 100644 index 00000000000..6b1f9c9bc3f --- /dev/null +++ b/ld/testsuite/ld-arm/attr-merge-vfp-7.d @@ -0,0 +1,14 @@ +#source: attr-merge-vfp-armv8.s +#source: attr-merge-vfp-armv8-hard.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: FP for ARMv8 + Tag_ABI_HardFP_use: SP and DP diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-7r.d b/ld/testsuite/ld-arm/attr-merge-vfp-7r.d new file mode 100644 index 00000000000..6b1f9c9bc3f --- /dev/null +++ b/ld/testsuite/ld-arm/attr-merge-vfp-7r.d @@ -0,0 +1,14 @@ +#source: attr-merge-vfp-armv8.s +#source: attr-merge-vfp-armv8-hard.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: FP for ARMv8 + Tag_ABI_HardFP_use: SP and DP diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-armv8-hard.s b/ld/testsuite/ld-arm/attr-merge-vfp-armv8-hard.s new file mode 100644 index 00000000000..6457974c488 --- /dev/null +++ b/ld/testsuite/ld-arm/attr-merge-vfp-armv8-hard.s @@ -0,0 +1,2 @@ +.fpu fp-armv8 +.eabi_attribute Tag_ABI_HardFP_use, 3 diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-armv8.s b/ld/testsuite/ld-arm/attr-merge-vfp-armv8.s new file mode 100644 index 00000000000..a7679cd5787 --- /dev/null +++ b/ld/testsuite/ld-arm/attr-merge-vfp-armv8.s @@ -0,0 +1,2 @@ +.fpu fp-armv8 +