From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sat, 6 Dec 2025 00:26:57 +0000 (-0800)
Subject: Merge tag 'riscv-for-linus-6.19-mw1' of git://git.kernel.org/pub/scm/linux/kernel... 
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=07025b51c1149951d64804c73014499bb3564dca;p=thirdparty%2Fkernel%2Flinux.git

Merge tag 'riscv-for-linus-6.19-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Paul Walmsley:

 - Enable parallel hotplug for RISC-V

 - Optimize vector regset allocation for ptrace()

 - Add a kernel selftest for the vector ptrace interface

 - Enable the userspace RAID6 test to build and run using RISC-V vectors

 - Add initial support for the Zalasr RISC-V ratified ISA extension

 - For the Zicbop RISC-V ratified ISA extension to userspace, expose
   hardware and kernel support to userspace and add a kselftest for
   Zicbop

 - Convert open-coded instances of 'asm goto's that are controlled by
   runtime ALTERNATIVEs to use riscv_has_extension_{un,}likely(),
   following arm64's alternative_has_cap_{un,}likely()

 - Remove an unnecessary mask in the GFP flags used in some calls to
   pagetable_alloc()

* tag 'riscv-for-linus-6.19-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  selftests/riscv: Add Zicbop prefetch test
  riscv: hwprobe: Expose Zicbop extension and its block size
  riscv: Introduce Zalasr instructions
  riscv: hwprobe: Export Zalasr extension
  dt-bindings: riscv: Add Zalasr ISA extension description
  riscv: Add ISA extension parsing for Zalasr
  selftests: riscv: Add test for the Vector ptrace interface
  riscv: ptrace: Optimize the allocation of vector regset
  raid6: test: Add support for RISC-V
  raid6: riscv: Allow code to be compiled in userspace
  raid6: riscv: Prevent compiler from breaking inline vector assembly code
  riscv: cmpxchg: Use riscv_has_extension_likely
  riscv: bitops: Use riscv_has_extension_likely
  riscv: hweight: Use riscv_has_extension_likely
  riscv: checksum: Use riscv_has_extension_likely
  riscv: pgtable: Use riscv_has_extension_unlikely
  riscv: Remove __GFP_HIGHMEM masking
  RISC-V: Enable HOTPLUG_PARALLEL for secondary CPUs
---

07025b51c1149951d64804c73014499bb3564dca
diff --cc arch/riscv/include/asm/hwcap.h
index f98fcb5c17d56,ae3852c4f2ca2..dfe57b215e6c9
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@@ -106,7 -106,7 +106,8 @@@
  #define RISCV_ISA_EXT_ZAAMO		97
  #define RISCV_ISA_EXT_ZALRSC		98
  #define RISCV_ISA_EXT_ZICBOP		99
 -#define RISCV_ISA_EXT_ZALASR		100
 +#define RISCV_ISA_EXT_SVRSW60T59B	100
++#define RISCV_ISA_EXT_ZALASR		101
  
  #define RISCV_ISA_EXT_XLINUXENVCFG	127