From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Fri, 10 Nov 2023 03:33:16 +0000 (+0800)
Subject: RISC-V: Robustify vec_init pattern[NFC]
X-Git-Tag: basepoints/gcc-15~4826
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=072a409803a270fd3e8f8aa1b4f9bb8e83789b85;p=thirdparty%2Fgcc.git

RISC-V: Robustify vec_init pattern[NFC]

Although current GCC didn't cause ICE when I create FP16 vec_init case
with -march=rv64gcv (no ZVFH), current vec_init pattern looks wrong.

Since V_VLS FP16 predicate is TARGET_VECTOR_ELEN_FP_16, wheras vec_init
needs vfslide1down/vfslide1up.

It makes more sense to robustify the vec_init patterns which split them
into 2 patterns (one is integer, the other is float) like other autovectorization patterns.

gcc/ChangeLog:

	* config/riscv/autovec.md (vec_init<mode><vel>): Split patterns.
---

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 33722ea1139e..868b47c8af70 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -373,7 +373,19 @@
 ;; -------------------------------------------------------------------------
 
 (define_expand "vec_init<mode><vel>"
-  [(match_operand:V_VLS 0 "register_operand")
+  [(match_operand:V_VLSI 0 "register_operand")
+   (match_operand 1 "")]
+  "TARGET_VECTOR"
+  {
+    riscv_vector::expand_vec_init (operands[0], operands[1]);
+    DONE;
+  }
+)
+
+;; We split RVV floating-point because we are going to
+;; use vfslide1down/vfslide1up for FP16 which need TARGET_ZVFH.
+(define_expand "vec_init<mode><vel>"
+  [(match_operand:V_VLSF 0 "register_operand")
    (match_operand 1 "")]
   "TARGET_VECTOR"
   {