From: Alice Carlotti Date: Tue, 7 Oct 2025 22:38:01 +0000 (+0100) Subject: aarch64: Add support for FEAT_SME_TMOP X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=0787e01a25d2a3497af2a6eabf7f67cc7b4bad6f;p=thirdparty%2Fbinutils-gdb.git aarch64: Add support for FEAT_SME_TMOP --- diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 8d7d750e046..4a66642cc04 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6937,6 +6937,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: case AARCH64_OPND_SVE_Zn_5_INDEX: + case AARCH64_OPND_SME_Zk_INDEX: case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: case AARCH64_OPND_SME_Zm_INDEX2_3: @@ -10893,6 +10894,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"sve2p2", AARCH64_FEATURE (SVE2p2), AARCH64_FEATURE (SVE2p1)}, {"sme2p2", AARCH64_FEATURE (SME2p2), AARCH64_FEATURE (SME2p1)}, {"gcie", AARCH64_FEATURE (GCIE), AARCH64_NO_FEATURES}, + {"sme-tmop", AARCH64_FEATURE (SME_TMOP), AARCH64_FEATURE (SME2)}, {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 1cbd97795fa..5176757c235 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -309,6 +309,8 @@ automatically cause those extensions to be disabled. @tab Enable SME I16I64 Extension. @item @code{sme-lutv2} @tab @tab Enable SME Lookup Table v2 (LUTv2) extension. +@item @code{sme-tmop} @tab @code{sme2} + @tab Enable SME structured sparsity outer product instructions. @item @code{sme2} @tab @code{sme} @tab Enable SME2. @item @code{sme2p1} @tab @code{sme2} diff --git a/gas/testsuite/gas/aarch64/sme-tmop-b16b16.d b/gas/testsuite/gas/aarch64/sme-tmop-b16b16.d new file mode 100644 index 00000000000..665efd80741 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop-b16b16.d @@ -0,0 +1,17 @@ +#as: -march=armv8-a+sme-tmop+sme-b16b16 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 81600008 bftmopa za0\.h, {z0\.h-z1\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 81600009 bftmopa za1\.h, {z0\.h-z1\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 816003c8 bftmopa za0\.h, {z30\.h-z31\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 817f0008 bftmopa za0\.h, {z0\.h-z1\.h}, z31\.h, z20\[0\] + *[0-9a-f]+: 81600c08 bftmopa za0\.h, {z0\.h-z1\.h}, z0\.h, z23\[0\] + *[0-9a-f]+: 81601008 bftmopa za0\.h, {z0\.h-z1\.h}, z0\.h, z28\[0\] + *[0-9a-f]+: 81601c08 bftmopa za0\.h, {z0\.h-z1\.h}, z0\.h, z31\[0\] + *[0-9a-f]+: 81600038 bftmopa za0\.h, {z0\.h-z1\.h}, z0\.h, z20\[3\] diff --git a/gas/testsuite/gas/aarch64/sme-tmop-b16b16.s b/gas/testsuite/gas/aarch64/sme-tmop-b16b16.s new file mode 100644 index 00000000000..b66ab7b0dbc --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop-b16b16.s @@ -0,0 +1,8 @@ + bftmopa za0.h, { z0.h-z1.h }, z0.h, z20[0] + bftmopa za1.h, { z0.h-z1.h }, z0.h, z20[0] + bftmopa za0.h, { z30.h-z31.h }, z0.h, z20[0] + bftmopa za0.h, { z0.h-z1.h }, z31.h, z20[0] + bftmopa za0.h, { z0.h-z1.h }, z0.h, z23[0] + bftmopa za0.h, { z0.h-z1.h }, z0.h, z28[0] + bftmopa za0.h, { z0.h-z1.h }, z0.h, z31[0] + bftmopa za0.h, { z0.h-z1.h }, z0.h, z20[3] diff --git a/gas/testsuite/gas/aarch64/sme-tmop-f16f16.d b/gas/testsuite/gas/aarch64/sme-tmop-f16f16.d new file mode 100644 index 00000000000..1ba801d1e86 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop-f16f16.d @@ -0,0 +1,17 @@ +#as: -march=armv8-a+sme-tmop+sme-f16f16 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 81400008 ftmopa za0\.h, {z0\.h-z1\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 81400009 ftmopa za1\.h, {z0\.h-z1\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 814003c8 ftmopa za0\.h, {z30\.h-z31\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 815f0008 ftmopa za0\.h, {z0\.h-z1\.h}, z31\.h, z20\[0\] + *[0-9a-f]+: 81400c08 ftmopa za0\.h, {z0\.h-z1\.h}, z0\.h, z23\[0\] + *[0-9a-f]+: 81401008 ftmopa za0\.h, {z0\.h-z1\.h}, z0\.h, z28\[0\] + *[0-9a-f]+: 81401c08 ftmopa za0\.h, {z0\.h-z1\.h}, z0\.h, z31\[0\] + *[0-9a-f]+: 81400038 ftmopa za0\.h, {z0\.h-z1\.h}, z0\.h, z20\[3\] diff --git a/gas/testsuite/gas/aarch64/sme-tmop-f16f16.s b/gas/testsuite/gas/aarch64/sme-tmop-f16f16.s new file mode 100644 index 00000000000..6e85c6e7dd4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop-f16f16.s @@ -0,0 +1,8 @@ + ftmopa za0.h, { z0.h-z1.h }, z0.h, z20[0] + ftmopa za1.h, { z0.h-z1.h }, z0.h, z20[0] + ftmopa za0.h, { z30.h-z31.h }, z0.h, z20[0] + ftmopa za0.h, { z0.h-z1.h }, z31.h, z20[0] + ftmopa za0.h, { z0.h-z1.h }, z0.h, z23[0] + ftmopa za0.h, { z0.h-z1.h }, z0.h, z28[0] + ftmopa za0.h, { z0.h-z1.h }, z0.h, z31[0] + ftmopa za0.h, { z0.h-z1.h }, z0.h, z20[3] diff --git a/gas/testsuite/gas/aarch64/sme-tmop-f8f16.d b/gas/testsuite/gas/aarch64/sme-tmop-f8f16.d new file mode 100644 index 00000000000..c9d47df3afa --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop-f8f16.d @@ -0,0 +1,17 @@ +#as: -march=armv8-a+sme-tmop+sme-f8f16 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 80600008 ftmopa za0\.h, {z0\.b-z1\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 80600009 ftmopa za1\.h, {z0\.b-z1\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 806003c8 ftmopa za0\.h, {z30\.b-z31\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 807f0008 ftmopa za0\.h, {z0\.b-z1\.b}, z31\.b, z20\[0\] + *[0-9a-f]+: 80600c08 ftmopa za0\.h, {z0\.b-z1\.b}, z0\.b, z23\[0\] + *[0-9a-f]+: 80601008 ftmopa za0\.h, {z0\.b-z1\.b}, z0\.b, z28\[0\] + *[0-9a-f]+: 80601c08 ftmopa za0\.h, {z0\.b-z1\.b}, z0\.b, z31\[0\] + *[0-9a-f]+: 80600038 ftmopa za0\.h, {z0\.b-z1\.b}, z0\.b, z20\[3\] diff --git a/gas/testsuite/gas/aarch64/sme-tmop-f8f16.s b/gas/testsuite/gas/aarch64/sme-tmop-f8f16.s new file mode 100644 index 00000000000..85ab95ef135 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop-f8f16.s @@ -0,0 +1,8 @@ + ftmopa za0.h, { z0.b-z1.b }, z0.b, z20[0] + ftmopa za1.h, { z0.b-z1.b }, z0.b, z20[0] + ftmopa za0.h, { z30.b-z31.b }, z0.b, z20[0] + ftmopa za0.h, { z0.b-z1.b }, z31.b, z20[0] + ftmopa za0.h, { z0.b-z1.b }, z0.b, z23[0] + ftmopa za0.h, { z0.b-z1.b }, z0.b, z28[0] + ftmopa za0.h, { z0.b-z1.b }, z0.b, z31[0] + ftmopa za0.h, { z0.b-z1.b }, z0.b, z20[3] diff --git a/gas/testsuite/gas/aarch64/sme-tmop-f8f32.d b/gas/testsuite/gas/aarch64/sme-tmop-f8f32.d new file mode 100644 index 00000000000..47a3effe3df --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop-f8f32.d @@ -0,0 +1,17 @@ +#as: -march=armv8-a+sme-tmop+sme-f8f32 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 80600000 ftmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 80600003 ftmopa za3\.s, {z0\.b-z1\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 806003c0 ftmopa za0\.s, {z30\.b-z31\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 807f0000 ftmopa za0\.s, {z0\.b-z1\.b}, z31\.b, z20\[0\] + *[0-9a-f]+: 80600c00 ftmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z23\[0\] + *[0-9a-f]+: 80601000 ftmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z28\[0\] + *[0-9a-f]+: 80601c00 ftmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z31\[0\] + *[0-9a-f]+: 80600030 ftmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z20\[3\] diff --git a/gas/testsuite/gas/aarch64/sme-tmop-f8f32.s b/gas/testsuite/gas/aarch64/sme-tmop-f8f32.s new file mode 100644 index 00000000000..000b52c3f96 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop-f8f32.s @@ -0,0 +1,8 @@ + ftmopa za0.s, { z0.b-z1.b }, z0.b, z20[0] + ftmopa za3.s, { z0.b-z1.b }, z0.b, z20[0] + ftmopa za0.s, { z30.b-z31.b }, z0.b, z20[0] + ftmopa za0.s, { z0.b-z1.b }, z31.b, z20[0] + ftmopa za0.s, { z0.b-z1.b }, z0.b, z23[0] + ftmopa za0.s, { z0.b-z1.b }, z0.b, z28[0] + ftmopa za0.s, { z0.b-z1.b }, z0.b, z31[0] + ftmopa za0.s, { z0.b-z1.b }, z0.b, z20[3] diff --git a/gas/testsuite/gas/aarch64/sme-tmop-invalid.d b/gas/testsuite/gas/aarch64/sme-tmop-invalid.d new file mode 100644 index 00000000000..4429a9bf5a3 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop-invalid.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+sme-tmop +#error_output: sme-tmop-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme-tmop-invalid.l b/gas/testsuite/gas/aarch64/sme-tmop-invalid.l new file mode 100644 index 00000000000..6bf589f2453 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop-invalid.l @@ -0,0 +1,6 @@ +[^:]*: Assembler messages: +[^:]*:\d+: Error: register out of range at operand 4 -- `ftmopa za0\.s,{z0\.s-z1\.s},z0\.s,z0\[0\]' +[^:]*:\d+: Error: register out of range at operand 4 -- `stmopa za0\.s,{z0\.h-z1\.h},z0\.h,z7\[0\]' +[^:]*:\d+: Error: register out of range at operand 4 -- `utmopa za0\.s,{z0\.b-z1\.b},z0\.b,z19\[0\]' +[^:]*:\d+: Error: register out of range at operand 4 -- `bftmopa za0\.s,{z0\.h-z1\.h},z0\.h,z27\[0\]' +[^:]*:\d+: Error: register element index out of range 0 to 3 at operand 4 -- `ftmopa za0\.s,{z0\.s-z1\.s},z0\.s,z20\[4\]' diff --git a/gas/testsuite/gas/aarch64/sme-tmop-invalid.s b/gas/testsuite/gas/aarch64/sme-tmop-invalid.s new file mode 100644 index 00000000000..f26a79d9125 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop-invalid.s @@ -0,0 +1,5 @@ + ftmopa za0.s, { z0.s-z1.s }, z0.s, z0[0] + stmopa za0.s, { z0.h-z1.h }, z0.h, z7[0] + utmopa za0.s, { z0.b-z1.b }, z0.b, z19[0] + bftmopa za0.s, { z0.h-z1.h }, z0.h, z27[0] + ftmopa za0.s, { z0.s-z1.s }, z0.s, z20[4] diff --git a/gas/testsuite/gas/aarch64/sme-tmop.d b/gas/testsuite/gas/aarch64/sme-tmop.d new file mode 100644 index 00000000000..552ff43c9f4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop.d @@ -0,0 +1,81 @@ +#as: -march=armv8-a+sme-tmop +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 81400000 bftmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 81400003 bftmopa za3\.s, {z0\.h-z1\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 814003c0 bftmopa za0\.s, {z30\.h-z31\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 815f0000 bftmopa za0\.s, {z0\.h-z1\.h}, z31\.h, z20\[0\] + *[0-9a-f]+: 81400c00 bftmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z23\[0\] + *[0-9a-f]+: 81401000 bftmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z28\[0\] + *[0-9a-f]+: 81401c00 bftmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z31\[0\] + *[0-9a-f]+: 81400030 bftmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z20\[3\] + *[0-9a-f]+: 80400000 ftmopa za0\.s, {z0\.s-z1\.s}, z0\.s, z20\[0\] + *[0-9a-f]+: 80400003 ftmopa za3\.s, {z0\.s-z1\.s}, z0\.s, z20\[0\] + *[0-9a-f]+: 804003c0 ftmopa za0\.s, {z30\.s-z31\.s}, z0\.s, z20\[0\] + *[0-9a-f]+: 805f0000 ftmopa za0\.s, {z0\.s-z1\.s}, z31\.s, z20\[0\] + *[0-9a-f]+: 80400c00 ftmopa za0\.s, {z0\.s-z1\.s}, z0\.s, z23\[0\] + *[0-9a-f]+: 80401000 ftmopa za0\.s, {z0\.s-z1\.s}, z0\.s, z28\[0\] + *[0-9a-f]+: 80401c00 ftmopa za0\.s, {z0\.s-z1\.s}, z0\.s, z31\[0\] + *[0-9a-f]+: 80400030 ftmopa za0\.s, {z0\.s-z1\.s}, z0\.s, z20\[3\] + *[0-9a-f]+: 81600000 ftmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 81600003 ftmopa za3\.s, {z0\.h-z1\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 816003c0 ftmopa za0\.s, {z30\.h-z31\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 817f0000 ftmopa za0\.s, {z0\.h-z1\.h}, z31\.h, z20\[0\] + *[0-9a-f]+: 81600c00 ftmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z23\[0\] + *[0-9a-f]+: 81601000 ftmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z28\[0\] + *[0-9a-f]+: 81601c00 ftmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z31\[0\] + *[0-9a-f]+: 81600030 ftmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z20\[3\] + *[0-9a-f]+: 80408008 stmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 8040800b stmopa za3\.s, {z0\.h-z1\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 804083c8 stmopa za0\.s, {z30\.h-z31\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 805f8008 stmopa za0\.s, {z0\.h-z1\.h}, z31\.h, z20\[0\] + *[0-9a-f]+: 80408c08 stmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z23\[0\] + *[0-9a-f]+: 80409008 stmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z28\[0\] + *[0-9a-f]+: 80409c08 stmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z31\[0\] + *[0-9a-f]+: 80408038 stmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z20\[3\] + *[0-9a-f]+: 80408000 stmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 80408003 stmopa za3\.s, {z0\.b-z1\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 804083c0 stmopa za0\.s, {z30\.b-z31\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 805f8000 stmopa za0\.s, {z0\.b-z1\.b}, z31\.b, z20\[0\] + *[0-9a-f]+: 80408c00 stmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z23\[0\] + *[0-9a-f]+: 80409000 stmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z28\[0\] + *[0-9a-f]+: 80409c00 stmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z31\[0\] + *[0-9a-f]+: 80408030 stmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z20\[3\] + *[0-9a-f]+: 80608000 sutmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 80608003 sutmopa za3\.s, {z0\.b-z1\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 806083c0 sutmopa za0\.s, {z30\.b-z31\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 807f8000 sutmopa za0\.s, {z0\.b-z1\.b}, z31\.b, z20\[0\] + *[0-9a-f]+: 80608c00 sutmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z23\[0\] + *[0-9a-f]+: 80609000 sutmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z28\[0\] + *[0-9a-f]+: 80609c00 sutmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z31\[0\] + *[0-9a-f]+: 80608030 sutmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z20\[3\] + *[0-9a-f]+: 81408000 ustmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 81408003 ustmopa za3\.s, {z0\.b-z1\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 814083c0 ustmopa za0\.s, {z30\.b-z31\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 815f8000 ustmopa za0\.s, {z0\.b-z1\.b}, z31\.b, z20\[0\] + *[0-9a-f]+: 81408c00 ustmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z23\[0\] + *[0-9a-f]+: 81409000 ustmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z28\[0\] + *[0-9a-f]+: 81409c00 ustmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z31\[0\] + *[0-9a-f]+: 81408030 ustmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z20\[3\] + *[0-9a-f]+: 81408008 utmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 8140800b utmopa za3\.s, {z0\.h-z1\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 814083c8 utmopa za0\.s, {z30\.h-z31\.h}, z0\.h, z20\[0\] + *[0-9a-f]+: 815f8008 utmopa za0\.s, {z0\.h-z1\.h}, z31\.h, z20\[0\] + *[0-9a-f]+: 81408c08 utmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z23\[0\] + *[0-9a-f]+: 81409008 utmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z28\[0\] + *[0-9a-f]+: 81409c08 utmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z31\[0\] + *[0-9a-f]+: 81408038 utmopa za0\.s, {z0\.h-z1\.h}, z0\.h, z20\[3\] + *[0-9a-f]+: 81608000 utmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 81608003 utmopa za3\.s, {z0\.b-z1\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 816083c0 utmopa za0\.s, {z30\.b-z31\.b}, z0\.b, z20\[0\] + *[0-9a-f]+: 817f8000 utmopa za0\.s, {z0\.b-z1\.b}, z31\.b, z20\[0\] + *[0-9a-f]+: 81608c00 utmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z23\[0\] + *[0-9a-f]+: 81609000 utmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z28\[0\] + *[0-9a-f]+: 81609c00 utmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z31\[0\] + *[0-9a-f]+: 81608030 utmopa za0\.s, {z0\.b-z1\.b}, z0\.b, z20\[3\] diff --git a/gas/testsuite/gas/aarch64/sme-tmop.s b/gas/testsuite/gas/aarch64/sme-tmop.s new file mode 100644 index 00000000000..037a6d63c06 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme-tmop.s @@ -0,0 +1,80 @@ + bftmopa za0.s, { z0.h-z1.h }, z0.h, z20[0] + bftmopa za3.s, { z0.h-z1.h }, z0.h, z20[0] + bftmopa za0.s, { z30.h-z31.h }, z0.h, z20[0] + bftmopa za0.s, { z0.h-z1.h }, z31.h, z20[0] + bftmopa za0.s, { z0.h-z1.h }, z0.h, z23[0] + bftmopa za0.s, { z0.h-z1.h }, z0.h, z28[0] + bftmopa za0.s, { z0.h-z1.h }, z0.h, z31[0] + bftmopa za0.s, { z0.h-z1.h }, z0.h, z20[3] + + ftmopa za0.s, { z0.s-z1.s }, z0.s, z20[0] + ftmopa za3.s, { z0.s-z1.s }, z0.s, z20[0] + ftmopa za0.s, { z30.s-z31.s }, z0.s, z20[0] + ftmopa za0.s, { z0.s-z1.s }, z31.s, z20[0] + ftmopa za0.s, { z0.s-z1.s }, z0.s, z23[0] + ftmopa za0.s, { z0.s-z1.s }, z0.s, z28[0] + ftmopa za0.s, { z0.s-z1.s }, z0.s, z31[0] + ftmopa za0.s, { z0.s-z1.s }, z0.s, z20[3] + + ftmopa za0.s, { z0.h-z1.h }, z0.h, z20[0] + ftmopa za3.s, { z0.h-z1.h }, z0.h, z20[0] + ftmopa za0.s, { z30.h-z31.h }, z0.h, z20[0] + ftmopa za0.s, { z0.h-z1.h }, z31.h, z20[0] + ftmopa za0.s, { z0.h-z1.h }, z0.h, z23[0] + ftmopa za0.s, { z0.h-z1.h }, z0.h, z28[0] + ftmopa za0.s, { z0.h-z1.h }, z0.h, z31[0] + ftmopa za0.s, { z0.h-z1.h }, z0.h, z20[3] + + stmopa za0.s, { z0.h-z1.h }, z0.h, z20[0] + stmopa za3.s, { z0.h-z1.h }, z0.h, z20[0] + stmopa za0.s, { z30.h-z31.h }, z0.h, z20[0] + stmopa za0.s, { z0.h-z1.h }, z31.h, z20[0] + stmopa za0.s, { z0.h-z1.h }, z0.h, z23[0] + stmopa za0.s, { z0.h-z1.h }, z0.h, z28[0] + stmopa za0.s, { z0.h-z1.h }, z0.h, z31[0] + stmopa za0.s, { z0.h-z1.h }, z0.h, z20[3] + + stmopa za0.s, { z0.b-z1.b }, z0.b, z20[0] + stmopa za3.s, { z0.b-z1.b }, z0.b, z20[0] + stmopa za0.s, { z30.b-z31.b }, z0.b, z20[0] + stmopa za0.s, { z0.b-z1.b }, z31.b, z20[0] + stmopa za0.s, { z0.b-z1.b }, z0.b, z23[0] + stmopa za0.s, { z0.b-z1.b }, z0.b, z28[0] + stmopa za0.s, { z0.b-z1.b }, z0.b, z31[0] + stmopa za0.s, { z0.b-z1.b }, z0.b, z20[3] + + sutmopa za0.s, { z0.b-z1.b }, z0.b, z20[0] + sutmopa za3.s, { z0.b-z1.b }, z0.b, z20[0] + sutmopa za0.s, { z30.b-z31.b }, z0.b, z20[0] + sutmopa za0.s, { z0.b-z1.b }, z31.b, z20[0] + sutmopa za0.s, { z0.b-z1.b }, z0.b, z23[0] + sutmopa za0.s, { z0.b-z1.b }, z0.b, z28[0] + sutmopa za0.s, { z0.b-z1.b }, z0.b, z31[0] + sutmopa za0.s, { z0.b-z1.b }, z0.b, z20[3] + + ustmopa za0.s, { z0.b-z1.b }, z0.b, z20[0] + ustmopa za3.s, { z0.b-z1.b }, z0.b, z20[0] + ustmopa za0.s, { z30.b-z31.b }, z0.b, z20[0] + ustmopa za0.s, { z0.b-z1.b }, z31.b, z20[0] + ustmopa za0.s, { z0.b-z1.b }, z0.b, z23[0] + ustmopa za0.s, { z0.b-z1.b }, z0.b, z28[0] + ustmopa za0.s, { z0.b-z1.b }, z0.b, z31[0] + ustmopa za0.s, { z0.b-z1.b }, z0.b, z20[3] + + utmopa za0.s, { z0.h-z1.h }, z0.h, z20[0] + utmopa za3.s, { z0.h-z1.h }, z0.h, z20[0] + utmopa za0.s, { z30.h-z31.h }, z0.h, z20[0] + utmopa za0.s, { z0.h-z1.h }, z31.h, z20[0] + utmopa za0.s, { z0.h-z1.h }, z0.h, z23[0] + utmopa za0.s, { z0.h-z1.h }, z0.h, z28[0] + utmopa za0.s, { z0.h-z1.h }, z0.h, z31[0] + utmopa za0.s, { z0.h-z1.h }, z0.h, z20[3] + + utmopa za0.s, { z0.b-z1.b }, z0.b, z20[0] + utmopa za3.s, { z0.b-z1.b }, z0.b, z20[0] + utmopa za0.s, { z30.b-z31.b }, z0.b, z20[0] + utmopa za0.s, { z0.b-z1.b }, z31.b, z20[0] + utmopa za0.s, { z0.b-z1.b }, z0.b, z23[0] + utmopa za0.s, { z0.b-z1.b }, z0.b, z28[0] + utmopa za0.s, { z0.b-z1.b }, z0.b, z31[0] + utmopa za0.s, { z0.b-z1.b }, z0.b, z20[3] diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ad3f419f914..099fb2366df 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -253,6 +253,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_PoPS, /* GICv5 (Generic Interrupt Controller) CPU Interface Extension. */ AARCH64_FEATURE_GCIE, + /* SME TMOP instructions. */ + AARCH64_FEATURE_SME_TMOP, /* Virtual features. These are used to gate instructions that are enabled by either of two (or more) sets of command line flags. */ @@ -899,6 +901,7 @@ enum aarch64_opnd AARCH64_OPND_SME_PnT_Wm_imm, /* SME .[, #]. */ AARCH64_OPND_SME_SHRIMM4, /* 4-bit right shift, bits [19:16]. */ AARCH64_OPND_SME_SHRIMM5, /* size + 5-bit right shift, bits [23:22,20:16]. */ + AARCH64_OPND_SME_Zk_INDEX, /* Zk[index], bits [12:10,5:4]. */ AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */ AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */ AARCH64_OPND_SME_Zm_INDEX2_3, /* Zn.T[index], bits [19:16,10,3]. */ diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index ac0bf7a70be..a5dbabbb3cd 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -556,7 +556,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode) case A64_OPID_d503323f_dsb_BARRIER_DSB_NXS: value = A64_OPID_d503323f_dsb_BARRIER_DSB_NXS; break; - case A64_OPID_d5080000_gsb_GSB: + case A64_OPID_d508001f_gsb_GSB: case A64_OPID_d5080000_gicr_Rd_GICR: case A64_OPID_d5080000_gic_GIC_Rd: case A64_OPID_d50b72e0_trcit_Rt: @@ -870,6 +870,7 @@ aarch64_insert_operand (const aarch64_operand *self, case AARCH64_OPND_SVE_Zm3_12_INDEX: case AARCH64_OPND_SME_PNn3_INDEX1: case AARCH64_OPND_SME_PNn3_INDEX2: + case AARCH64_OPND_SME_Zk_INDEX: case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: case AARCH64_OPND_SME_Zm_INDEX2_3: diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 275d295d7f9..87e0f2a54ba 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -92,19 +92,49 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 4) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0000000x10xxxxxxxxxxxxxxxx0xxxx. */ - return A64_OPID_80c00000_fmopa_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16; + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000000010xxxxx0xxxxxxxxxxx0xxx. */ + return A64_OPID_80400000_ftmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000000010xxxxx1xxxxxxxxxxx0xxx. */ + return A64_OPID_80408000_stmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; + } + } + else + { + if (((word >> 4) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000000110xxxxxxxxxxxxxxxx00xxx. */ + return A64_OPID_80c00000_fmopa_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000000110xxxxxxxxxxxxxxxx10xxx. */ + return A64_OPID_80c00010_fmops_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16; + } + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x0000000x10xxxxxxxxxxxxxxxx1xxxx. */ - return A64_OPID_80c00010_fmops_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16; + x0000000x10xxxxxxxxxxxxxxxxx1xxx. */ + return A64_OPID_80408008_stmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; } } } @@ -1287,169 +1317,199 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 23) & 0x1) == 0) { - if (((word >> 30) & 0x1) == 0) + if (((word >> 29) & 0x1) == 0) { - if (((word >> 0) & 0x1) == 0) + if (((word >> 3) & 0x1) == 0) { - if (((word >> 13) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { - if (((word >> 14) & 0x1) == 0) - { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx000xxxxxxxxxxxx0. */ - return A64_OPID_a0600000_st1b_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx100xxxxxxxxxxxx0. */ - return A64_OPID_a0608000_st1b_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; - } - } - else - { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx010xxxxxxxxxxxx0. */ - return A64_OPID_a0604000_st1w_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx110xxxxxxxxxxxx0. */ - return A64_OPID_a060c000_st1w_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; - } - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000000011xxxxx0xxxxxxxxxxx0xxx. */ + return A64_OPID_80600000_ftmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; } else { - if (((word >> 14) & 0x1) == 0) - { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx001xxxxxxxxxxxx0. */ - return A64_OPID_a0602000_st1h_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx101xxxxxxxxxxxx0. */ - return A64_OPID_a060a000_st1h_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; - } - } - else - { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx011xxxxxxxxxxxx0. */ - return A64_OPID_a0606000_st1d_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx111xxxxxxxxxxxx0. */ - return A64_OPID_a060e000_st1d_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; - } - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000000011xxxxx1xxxxxxxxxxx0xxx. */ + return A64_OPID_80608000_sutmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; } } else { - if (((word >> 13) & 0x1) == 0) + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000000011xxxxxxxxxxxxxxxxx1xxx. */ + return A64_OPID_80600008_ftmopa_SME_ZAda_1b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + if (((word >> 0) & 0x1) == 0) { - if (((word >> 14) & 0x1) == 0) + if (((word >> 13) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx000xxxxxxxxxxxx1. */ - return A64_OPID_a0600001_stnt1b_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx000xxxxxxxxxxxx0. */ + return A64_OPID_a0600000_st1b_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx100xxxxxxxxxxxx0. */ + return A64_OPID_a0608000_st1b_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx100xxxxxxxxxxxx1. */ - return A64_OPID_a0608001_stnt1b_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx010xxxxxxxxxxxx0. */ + return A64_OPID_a0604000_st1w_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx110xxxxxxxxxxxx0. */ + return A64_OPID_a060c000_st1w_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + } } } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx010xxxxxxxxxxxx1. */ - return A64_OPID_a0604001_stnt1w_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx001xxxxxxxxxxxx0. */ + return A64_OPID_a0602000_st1h_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx101xxxxxxxxxxxx0. */ + return A64_OPID_a060a000_st1h_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx110xxxxxxxxxxxx1. */ - return A64_OPID_a060c001_stnt1w_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx011xxxxxxxxxxxx0. */ + return A64_OPID_a0606000_st1d_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx111xxxxxxxxxxxx0. */ + return A64_OPID_a060e000_st1d_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + } } } } else { - if (((word >> 14) & 0x1) == 0) + if (((word >> 13) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx001xxxxxxxxxxxx1. */ - return A64_OPID_a0602001_stnt1h_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx000xxxxxxxxxxxx1. */ + return A64_OPID_a0600001_stnt1b_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx100xxxxxxxxxxxx1. */ + return A64_OPID_a0608001_stnt1b_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx101xxxxxxxxxxxx1. */ - return A64_OPID_a060a001_stnt1h_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx010xxxxxxxxxxxx1. */ + return A64_OPID_a0604001_stnt1w_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx110xxxxxxxxxxxx1. */ + return A64_OPID_a060c001_stnt1w_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + } } } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx011xxxxxxxxxxxx1. */ - return A64_OPID_a0606001_stnt1d_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx001xxxxxxxxxxxx1. */ + return A64_OPID_a0602001_stnt1h_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx101xxxxxxxxxxxx1. */ + return A64_OPID_a060a001_stnt1h_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00000011xxxxx111xxxxxxxxxxxx1. */ - return A64_OPID_a060e001_stnt1d_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx011xxxxxxxxxxxx1. */ + return A64_OPID_a0606001_stnt1d_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100000011xxxxx111xxxxxxxxxxxx1. */ + return A64_OPID_a060e001_stnt1d_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + } } } } } - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1x00000011xxxxxxxxxxxxxxxxxxxxx. */ - return A64_OPID_e0600000_st1h_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1; + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1100000011xxxxxxxxxxxxxxxxxxxxx. */ + return A64_OPID_e0600000_st1h_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1; + } } } else @@ -2319,88 +2379,188 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 3) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 29) & 0x1) == 0) { - if (((word >> 29) & 0x1) == 0) + if (((word >> 30) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx0000010100xxxxxxxxxxxxxxxx0xxx. */ - return A64_OPID_c1400000_fmlall_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001010xxxxx0xxxxxxxxxxx0xxx. */ + return A64_OPID_81400000_bftmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001010xxxxx1xxxxxxxxxxx0xxx. */ + return A64_OPID_81408000_ustmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; + } } else { - if (((word >> 13) & 0x1) == 0) + if (((word >> 4) & 0x1) == 0) { - if (((word >> 14) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx1000010100xxxx000xxxxxxxxx0xxx. */ - return A64_OPID_a1400000_ld1b_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx1000010100xxxx100xxxxxxxxx0xxx. */ - return A64_OPID_a1408000_ld1b_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010100xxxxxxxxxxxxxxx00xxx. */ + return A64_OPID_c1400000_fmlall_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10; } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx1000010100xxxx010xxxxxxxxx0xxx. */ - return A64_OPID_a1404000_ld1w_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010101xxxx0xx0xxxxxx000xxx. */ + return A64_OPID_c1500000_fmla_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010101xxxx1xx0xxxxxx000xxx. */ + return A64_OPID_c1508000_fmla_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010101xxxx0xx1xxxxxx000xxx. */ + return A64_OPID_c1501000_sdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010101xxxx1xx1xxxxxx000xxx. */ + return A64_OPID_c1509000_sdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx1000010100xxxx110xxxxxxxxx0xxx. */ - return A64_OPID_a140c000_ld1w_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010101xxxx0xx0xxxxxx100xxx. */ + return A64_OPID_c1500020_svdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010101xxxx1xx0xxxxxx100xxx. */ + return A64_OPID_c1508020_svdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010101xxxx0xx1xxxxxx100xxx. */ + return A64_OPID_c1501020_sdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010101xxxx1xx1xxxxxx100xxx. */ + return A64_OPID_c1509020_sdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } + } } } } else { - if (((word >> 14) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx1000010100xxxx001xxxxxxxxx0xxx. */ - return A64_OPID_a1402000_ld1h_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx0xx0xxxxxx010xxx. */ + return A64_OPID_c1500010_fmls_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx1xx0xxxxxx010xxx. */ + return A64_OPID_c1508010_fmls_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx1000010100xxxx101xxxxxxxxx0xxx. */ - return A64_OPID_a140a000_ld1h_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx0xx1xxxxxx010xxx. */ + return A64_OPID_c1501010_udot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx1xx1xxxxxx010xxx. */ + return A64_OPID_c1509010_udot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } } } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx1000010100xxxx011xxxxxxxxx0xxx. */ - return A64_OPID_a1406000_ld1d_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx0xx0xxxxxx110xxx. */ + return A64_OPID_c1500030_uvdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx1xx0xxxxxx110xxx. */ + return A64_OPID_c1508030_uvdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx1000010100xxxx111xxxxxxxxx0xxx. */ - return A64_OPID_a140e000_ld1d_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx0xx1xxxxxx110xxx. */ + return A64_OPID_c1501030_udot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx1xx1xxxxxx110xxx. */ + return A64_OPID_c1509030_udot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } } } } @@ -2408,167 +2568,164 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 4) & 0x1) == 0) + if (((word >> 13) & 0x1) == 0) { - if (((word >> 5) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx0xxxxxx000xxx. */ - return A64_OPID_c1500000_fmla_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx0xxxxxx000xxx. */ - return A64_OPID_c1508000_fmla_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001010xxxxx000xxxxxxxxx0xxx. */ + return A64_OPID_a1400000_ld1b_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL; } else { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx1xxxxxx000xxx. */ - return A64_OPID_c1501000_sdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx1xxxxxx000xxx. */ - return A64_OPID_c1509000_sdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001010xxxxx100xxxxxxxxx0xxx. */ + return A64_OPID_a1408000_ld1b_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL; } } else { - if (((word >> 12) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx0xxxxxx100xxx. */ - return A64_OPID_c1500020_svdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx0xxxxxx100xxx. */ - return A64_OPID_c1508020_svdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001010xxxxx010xxxxxxxxx0xxx. */ + return A64_OPID_a1404000_ld1w_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL; } else { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx1xxxxxx100xxx. */ - return A64_OPID_c1501020_sdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx1xxxxxx100xxx. */ - return A64_OPID_c1509020_sdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001010xxxxx110xxxxxxxxx0xxx. */ + return A64_OPID_a140c000_ld1w_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL; } } } else { - if (((word >> 5) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx0xxxxxx010xxx. */ - return A64_OPID_c1500010_fmls_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx0xxxxxx010xxx. */ - return A64_OPID_c1508010_fmls_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001010xxxxx001xxxxxxxxx0xxx. */ + return A64_OPID_a1402000_ld1h_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL; } else { - if (((word >> 15) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx1xxxxxx010xxx. */ - return A64_OPID_c1501010_udot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx1xxxxxx010xxx. */ - return A64_OPID_c1509010_udot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001010xxxxx101xxxxxxxxx0xxx. */ + return A64_OPID_a140a000_ld1h_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL; } } else { - if (((word >> 12) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001010xxxxx011xxxxxxxxx0xxx. */ + return A64_OPID_a1406000_ld1d_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001010xxxxx111xxxxxxxxx0xxx. */ + return A64_OPID_a140e000_ld1d_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL; + } + } + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 29) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001010xxxxx0xxxxxxxxxxx1xxx. */ + return A64_OPID_81400008_ftmopa_SME_ZAda_1b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; + } + else + { + if (((word >> 4) & 0x1) == 0) + { + if (((word >> 5) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx0xxxxxx110xxx. */ - return A64_OPID_c1500030_uvdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx0xx0xxxxxx001xxx. */ + return A64_OPID_c1500008_fvdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx0xx1xxxxxx001xxx. */ + return A64_OPID_c1501008_fdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx1xx0xxxxxx110xxx. */ - return A64_OPID_c1508030_uvdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + x1000001010xxxxx0xxxxxxxxx101xxx. */ + return A64_OPID_c1501028_usdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; } } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx1xxxxxx110xxx. */ - return A64_OPID_c1501030_udot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx0xx0xxxxxx011xxx. */ + return A64_OPID_c1500018_bfvdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx0xx1xxxxxx011xxx. */ + return A64_OPID_c1501018_bfdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx1xxxxxx110xxx. */ - return A64_OPID_c1509030_udot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx0xx0xxxxxx111xxx. */ + return A64_OPID_c1500038_fdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx0xx1xxxxxx111xxx. */ + return A64_OPID_c1501038_sudot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + } } } } } - } - } - else - { - if (((word >> 15) & 0x1) == 0) - { - if (((word >> 20) & 0x1) == 0) + else { if (((word >> 13) & 0x1) == 0) { @@ -2576,14 +2733,14 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010100xxxx000xxxxxxxxx1xxx. */ + xx100001010xxxxx000xxxxxxxxx1xxx. */ return A64_OPID_a1400008_ldnt1b_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010100xxxx010xxxxxxxxx1xxx. */ + xx100001010xxxxx010xxxxxxxxx1xxx. */ return A64_OPID_a1404008_ldnt1w_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL; } } @@ -2593,89 +2750,99 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010100xxxx001xxxxxxxxx1xxx. */ + xx100001010xxxxx001xxxxxxxxx1xxx. */ return A64_OPID_a1402008_ldnt1h_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010100xxxx011xxxxxxxxx1xxx. */ + xx100001010xxxxx011xxxxxxxxx1xxx. */ return A64_OPID_a1406008_ldnt1d_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL; } } } - else + } + else + { + if (((word >> 29) & 0x1) == 0) { - if (((word >> 4) & 0x1) == 0) + if (((word >> 30) & 0x1) == 0) { - if (((word >> 5) & 0x1) == 0) - { - if (((word >> 12) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx0xxxxxx001xxx. */ - return A64_OPID_c1500008_fvdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx1xxxxxx001xxx. */ - return A64_OPID_c1501008_fdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; - } - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xxxxxxxxx101xxx. */ - return A64_OPID_c1501028_usdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001010xxxxx1xxxxxxxxxxx1xxx. */ + return A64_OPID_81408008_utmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; } else { - if (((word >> 5) & 0x1) == 0) + if (((word >> 4) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx0xxxxxx011xxx. */ - return A64_OPID_c1500018_bfvdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx1xx0xxxxxx001xxx. */ + return A64_OPID_c1508008_fdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx1xx1xxxxxx001xxx. */ + return A64_OPID_c1509008_fdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx1xxxxxx011xxx. */ - return A64_OPID_c1501018_bfdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx1xx0xxxxxx101xxx. */ + return A64_OPID_c1508028_usvdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx1xx1xxxxxx101xxx. */ + return A64_OPID_c1509028_usdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } } } else { - if (((word >> 12) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010101xxxx0xx0xxxxxx111xxx. */ - return A64_OPID_c1500038_fdot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + x1000001010xxxxx1xxxxxxxxx011xxx. */ + return A64_OPID_c1509018_bfdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx0xx1xxxxxx111xxx. */ - return A64_OPID_c1501038_sudot_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx1xx0xxxxxx111xxx. */ + return A64_OPID_c1508038_suvdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001010xxxxx1xx1xxxxxx111xxx. */ + return A64_OPID_c1509038_sudot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; + } } } } } - } - else - { - if (((word >> 20) & 0x1) == 0) + else { if (((word >> 13) & 0x1) == 0) { @@ -2683,14 +2850,14 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010100xxxx100xxxxxxxxx1xxx. */ + xx100001010xxxxx100xxxxxxxxx1xxx. */ return A64_OPID_a1408008_ldnt1b_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010100xxxx110xxxxxxxxx1xxx. */ + xx100001010xxxxx110xxxxxxxxx1xxx. */ return A64_OPID_a140c008_ldnt1w_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL; } } @@ -2700,85 +2867,18 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010100xxxx101xxxxxxxxx1xxx. */ + xx100001010xxxxx101xxxxxxxxx1xxx. */ return A64_OPID_a140a008_ldnt1h_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx000010100xxxx111xxxxxxxxx1xxx. */ + xx100001010xxxxx111xxxxxxxxx1xxx. */ return A64_OPID_a140e008_ldnt1d_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL; } } } - else - { - if (((word >> 4) & 0x1) == 0) - { - if (((word >> 5) & 0x1) == 0) - { - if (((word >> 12) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx0xxxxxx001xxx. */ - return A64_OPID_c1508008_fdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx1xxxxxx001xxx. */ - return A64_OPID_c1509008_fdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } - } - else - { - if (((word >> 12) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx0xxxxxx101xxx. */ - return A64_OPID_c1508028_usvdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx1xxxxxx101xxx. */ - return A64_OPID_c1509028_usdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } - } - } - else - { - if (((word >> 5) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xxxxxxxxx011xxx. */ - return A64_OPID_c1509018_bfdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } - else - { - if (((word >> 12) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx0xxxxxx111xxx. */ - return A64_OPID_c1508038_suvdot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx000010101xxxx1xx1xxxxxx111xxx. */ - return A64_OPID_c1509038_sudot_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2; - } - } - } - } } } } @@ -3089,36 +3189,66 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 3) & 0x1) == 0) { - if (((word >> 4) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0000001xx1xxxxxxxxxxxxxxxx00xxx. */ - return A64_OPID_81a00000_fmopa_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16; + if (((word >> 4) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001x01xxxxxxxxxxxxxxxx00xxx. */ + return A64_OPID_81a00000_fmopa_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001x01xxxxxxxxxxxxxxxx10xxx. */ + return A64_OPID_81a00010_fmops_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0000001xx1xxxxxxxxxxxxxxxx10xxx. */ - return A64_OPID_81a00010_fmops_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001x11xxxxx0xxxxxxxxxxx0xxx. */ + return A64_OPID_81600000_ftmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001x11xxxxx1xxxxxxxxxxx0xxx. */ + return A64_OPID_81608000_utmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; + } } } else { - if (((word >> 4) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0000001xx1xxxxxxxxxxxxxxxx01xxx. */ - return A64_OPID_81a00008_bfmopa_SME_ZAda_1b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16; + if (((word >> 4) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001x01xxxxxxxxxxxxxxxx01xxx. */ + return A64_OPID_81a00008_bfmopa_SME_ZAda_1b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0000001x01xxxxxxxxxxxxxxxx11xxx. */ + return A64_OPID_81a00018_bfmops_SME_ZAda_1b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x0000001xx1xxxxxxxxxxxxxxxx11xxx. */ - return A64_OPID_81a00018_bfmops_SME_ZAda_1b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16; + x0000001x11xxxxxxxxxxxxxxxxx1xxx. */ + return A64_OPID_81600008_bftmopa_SME_ZAda_1b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX; } } } @@ -34859,7 +34989,7 @@ aarch64_find_alias_opcode (const aarch64_opcode *opcode) value = A64_OPID_d503323f_dsb_BARRIER_DSB_NXS; break; case A64_OPID_d5080000_sys_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt: - value = A64_OPID_d5080000_gsb_GSB; + value = A64_OPID_d508001f_gsb_GSB; break; case A64_OPID_d5480000_sysp_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR: value = A64_OPID_d5480000_tlbip_SYSREG_TLBIP_Rt_SYS_PAIRREG_OR_XZR; @@ -35508,7 +35638,7 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode) case A64_OPID_d5033c9f_dfb: value = A64_OPID_d503309f_dsb_BARRIER; break; - case A64_OPID_d5080000_gsb_GSB: + case A64_OPID_d508001f_gsb_GSB: value = A64_OPID_d5080000_gicr_Rd_GICR; break; case A64_OPID_d5080000_gicr_Rd_GICR: @@ -35807,6 +35937,7 @@ aarch64_extract_operand (const aarch64_operand *self, case AARCH64_OPND_SVE_Zm3_12_INDEX: case AARCH64_OPND_SME_PNn3_INDEX1: case AARCH64_OPND_SME_PNn3_INDEX2: + case AARCH64_OPND_SME_Zk_INDEX: case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: case AARCH64_OPND_SME_Zm_INDEX2_3: diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 2ce7b00724c..dc8aab5a588 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -320,6 +320,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm4}, "a shift-right immediate operand"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM5", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5b}, "a shift-right immediate operand"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zk_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_4, FLD_CONST_1, FLD_SVE_i3l2, FLD_CONST_1, FLD_imm2_10}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_10, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_10, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 1050f8ffea6..07aba80a088 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -362,6 +362,7 @@ const aarch64_field aarch64_fields[] = AARCH64_FIELD ( 0, 2), /* imm2_0: general immediate in bits [1:0]. */ AARCH64_FIELD ( 1, 2), /* imm2_1: general immediate in bits [2:1]. */ AARCH64_FIELD ( 2, 2), /* imm2_2: general immediate in bits [3:2]. */ + AARCH64_FIELD ( 4, 2), /* imm2_4: general immediate in bits [5:4]. */ AARCH64_FIELD ( 8, 2), /* imm2_8: general immediate in bits [9:8]. */ AARCH64_FIELD (10, 2), /* imm2_10: 2-bit immediate, bits [11:10] */ AARCH64_FIELD (12, 2), /* imm2_12: 2-bit immediate, bits [13:12] */ @@ -1966,6 +1967,17 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return false; break; + case AARCH64_OPND_SME_Zk_INDEX: + if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 3)) + return false; + if ((opnd->reglane.regno & 20) != 20) + { + set_other_error (mismatch_detail, idx, + _("register out of range")); + return false; + } + break; + case AARCH64_OPND_SME_Zm: case AARCH64_OPND_SME_Zm_17: if (opnd->reg.regno > 15) @@ -4387,6 +4399,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: + case AARCH64_OPND_SME_Zk_INDEX: case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: case AARCH64_OPND_SME_Zm_INDEX2_3: diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 2e5d2c30850..cd639fde6de 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -166,6 +166,7 @@ enum aarch64_field_kind FLD_imm2_0, FLD_imm2_1, FLD_imm2_2, + FLD_imm2_4, FLD_imm2_8, FLD_imm2_10, FLD_imm2_12, diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h index 01a984dd849..3d06d5c7ae3 100644 --- a/opcodes/aarch64-tbl-2.h +++ b/opcodes/aarch64-tbl-2.h @@ -3845,6 +3845,19 @@ enum aarch64_opcode_idx A64_OPID_c121e400_fmul_SME_Zdnx4_SME_Znx4_SME_Zmx4, A64_OPID_d5080000_gic_GIC_Rd, A64_OPID_d5080000_gicr_Rd_GICR, - A64_OPID_d5080000_gsb_GSB, + A64_OPID_d508001f_gsb_GSB, + A64_OPID_81600008_bftmopa_SME_ZAda_1b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, + A64_OPID_81400000_bftmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, + A64_OPID_81400008_ftmopa_SME_ZAda_1b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, + A64_OPID_80400000_ftmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, + A64_OPID_81600000_ftmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, + A64_OPID_80600008_ftmopa_SME_ZAda_1b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, + A64_OPID_80600000_ftmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, + A64_OPID_80408008_stmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, + A64_OPID_80408000_stmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, + A64_OPID_80608000_sutmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, + A64_OPID_81408000_ustmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, + A64_OPID_81408008_utmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, + A64_OPID_81608000_utmopa_SME_ZAda_2b_SME_Znx2_SVE_Zm_16_SME_Zk_INDEX, A64_OPID_MAX, }; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 86969201b45..f836c66f4bf 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1768,6 +1768,10 @@ { \ QLF2(S_B,S_S), \ } +#define OP_SVE_HBBU \ +{ \ + QLF4(S_H,S_B,S_B,NIL), \ +} #define OP_SVE_HHH \ { \ QLF3(S_H,S_H,S_H), \ @@ -1871,6 +1875,14 @@ QLF3(W,NIL,S_S), \ QLF3(X,NIL,S_D), \ } +#define OP_SVE_SBBU \ +{ \ + QLF4(S_S,S_B,S_B,NIL), \ +} +#define OP_SVE_SHHU \ +{ \ + QLF4(S_S,S_H,S_H,NIL), \ +} #define OP_SVE_SMD \ { \ QLF3(S_S,P_M,S_D), \ @@ -1919,6 +1931,10 @@ { \ QLF2(S_S,S_S), \ } +#define OP_SVE_SSSU \ +{ \ + QLF4(S_S,S_S,S_S,NIL), \ +} #define OP_SVE_SU \ { \ QLF2(S_S,NIL), \ @@ -3011,6 +3027,16 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = AARCH64_FEATURE (SVE2p2_SME2p2); static const aarch64_feature_set aarch64_feature_gcie = AARCH64_FEATURE (GCIE); +static const aarch64_feature_set aarch64_feature_sme_tmop = + AARCH64_FEATURE (SME_TMOP); +static const aarch64_feature_set aarch64_feature_sme_tmop_b16b16 = + AARCH64_FEATURES (2, SME_TMOP, SME_B16B16); +static const aarch64_feature_set aarch64_feature_sme_tmop_f16f16 = + AARCH64_FEATURES (2, SME_TMOP, SME_F16F16); +static const aarch64_feature_set aarch64_feature_sme_tmop_f8f16 = + AARCH64_FEATURES (2, SME_TMOP, SME_F8F16); +static const aarch64_feature_set aarch64_feature_sme_tmop_f8f32 = + AARCH64_FEATURES (2, SME_TMOP, SME_F8F32); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -3122,6 +3148,11 @@ static const aarch64_feature_set aarch64_feature_gcie = #define SVE_SME2p2 &aarch64_feature_sve_sme2p2 #define SVE2p2_SME2p2 &aarch64_feature_sve2p2_sme2p2 #define GCIE &aarch64_feature_gcie +#define SME_TMOP &aarch64_feature_sme_tmop +#define SME_TMOP_B16B16 &aarch64_feature_sme_tmop_b16b16 +#define SME_TMOP_F16F16 &aarch64_feature_sme_tmop_f16f16 +#define SME_TMOP_F8F16 &aarch64_feature_sme_tmop_f8f16 +#define SME_TMOP_F8F32 &aarch64_feature_sme_tmop_f8f32 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } @@ -3412,6 +3443,21 @@ static const aarch64_feature_set aarch64_feature_gcie = F_STRICT | FLAGS, 0, TIED, NULL } #define GCIE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, GCIE, OPS, QUALS, FLAGS, 0, 0, NULL } +#define SME_TMOP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, SME_TMOP, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } +#define SME_TMOP_B16B16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, SME_TMOP_B16B16, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } +#define SME_TMOP_F16F16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, SME_TMOP_F16F16, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } +#define SME_TMOP_F8F16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, SME_TMOP_F8F16, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } +#define SME_TMOP_F8F32_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, SME_TMOP_F8F32, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -7487,6 +7533,21 @@ const struct aarch64_opcode aarch64_opcode_table[] = GCIE_INSN ("gicr", 0xd5080000, 0xfff80000, OP2 (Rd, GICR), QL_DST_X, F_ALIAS), GCIE_INSN ("gsb", 0xd508001f, 0xfff8001f, OP1 (GSB), QL_IMM_NIL, F_ALIAS), + /* SME TMOP instructions. */ + SME_TMOP_B16B16_INSN ("bftmopa", 0x81600008, 0xffe0e00e, sme_misc, OP4 (SME_ZAda_1b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_HHHU, 0, 0), + SME_TMOP_INSN ("bftmopa", 0x81400000, 0xffe0e00c, sme_misc, OP4 (SME_ZAda_2b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_SHHU, 0, 0), + SME_TMOP_F16F16_INSN ("ftmopa", 0x81400008, 0xffe0e00e, sme_misc, OP4 (SME_ZAda_1b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_HHHU, 0, 0), + SME_TMOP_INSN ("ftmopa", 0x80400000, 0xffe0e00c, sme_misc, OP4 (SME_ZAda_2b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_SSSU, 0, 0), + SME_TMOP_INSN ("ftmopa", 0x81600000, 0xffe0e00c, sme_misc, OP4 (SME_ZAda_2b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_SHHU, 0, 0), + SME_TMOP_F8F16_INSN ("ftmopa", 0x80600008, 0xffe0e00e, sme_misc, OP4 (SME_ZAda_1b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_HBBU, 0, 0), + SME_TMOP_F8F32_INSN ("ftmopa", 0x80600000, 0xffe0e00c, sme_misc, OP4 (SME_ZAda_2b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_SBBU, 0, 0), + SME_TMOP_INSN ("stmopa", 0x80408008, 0xffe0e00c, sme_misc, OP4 (SME_ZAda_2b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_SHHU, 0, 0), + SME_TMOP_INSN ("stmopa", 0x80408000, 0xffe0e00c, sme_misc, OP4 (SME_ZAda_2b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_SBBU, 0, 0), + SME_TMOP_INSN ("sutmopa", 0x80608000, 0xffe0e00c, sme_misc, OP4 (SME_ZAda_2b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_SBBU, 0, 0), + SME_TMOP_INSN ("ustmopa", 0x81408000, 0xffe0e00c, sme_misc, OP4 (SME_ZAda_2b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_SBBU, 0, 0), + SME_TMOP_INSN ("utmopa", 0x81408008, 0xffe0e00c, sme_misc, OP4 (SME_ZAda_2b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_SHHU, 0, 0), + SME_TMOP_INSN ("utmopa", 0x81608000, 0xffe0e00c, sme_misc, OP4 (SME_ZAda_2b, SME_Znx2, SVE_Zm_16, SME_Zk_INDEX), OP_SVE_SBBU, 0, 0), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -8125,6 +8186,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a shift-right immediate operand") \ Y(IMMEDIATE, sve_shrimm, "SME_SHRIMM5", 1 << OPD_F_OD_LSB, \ F(FLD_SVE_tszh,FLD_SVE_imm5b), "a shift-right immediate operand") \ + Y(SVE_REG, simple_index, "SME_Zk_INDEX", 0, \ + F(FLD_imm2_4, FLD_CONST_1, FLD_SVE_i3l2, FLD_CONST_1, FLD_imm2_10),\ + "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX1", 0, \ F(FLD_imm1_10, FLD_CONST_0, FLD_SME_Zm), \ "an indexed SVE vector register") \