From: Sean Anderson Date: Fri, 27 Sep 2024 20:13:13 +0000 (-0400) Subject: arm64: dts: renesas: beacon: Add SD/OE pin properties X-Git-Tag: v6.13-rc1~140^2~37^2~24 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=07aca8190a4ff9370823f577b66f23b8f2de4442;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: renesas: beacon: Add SD/OE pin properties Add SD/OE pin properties to the devicetree so that Linux can configure the pin without relying on the OTP. This matches the register configuration reported by Adam [1] as well as his analysis of the schematic. [1] https://lore.kernel.org/linux-arm-kernel/CAHCN7x+tcvih1-kmUs8tVLCAk0Gnj11t0yEZLPWk3UBNyad7Jg@mail.gmail.com/ Signed-off-by: Sean Anderson Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240927201313.624762-4-sean.anderson@linux.dev Signed-off-by: Geert Uytterhoeven --- diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 9436b249ebdd9..5887b31852f91 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -364,6 +364,8 @@ #clock-cells = <1>; clocks = <&x304_clk>; clock-names = "xin"; + idt,shutdown = <0>; + idt,output-enable-active = <0>; assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>, <&versaclock6_bb 3>, <&versaclock6_bb 4>; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 68b04e56ae562..06ad9db420d63 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -166,6 +166,8 @@ #clock-cells = <1>; clocks = <&x304_clk>; clock-names = "xin"; + idt,shutdown = <0>; + idt,output-enable-active = <0>; /* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */ assigned-clocks = <&versaclock5 1>, <&versaclock5 2>,